From 0010f5bb4b52ac791c86af69e5e24285f96fe6ae Mon Sep 17 00:00:00 2001 From: Nathan Wiebe Neufeldt Date: Mon, 22 Jul 2019 13:13:54 -0400 Subject: [PATCH] Fix typos in core_arch documentation --- .../stdarch/crates/core_arch/src/mips/msa.rs | 1730 ++++++++--------- .../stdarch/crates/core_arch/src/x86/avx.rs | 2 +- .../stdarch/crates/core_arch/src/x86/sse2.rs | 4 +- 3 files changed, 868 insertions(+), 868 deletions(-) diff --git a/library/stdarch/crates/core_arch/src/mips/msa.rs b/library/stdarch/crates/core_arch/src/mips/msa.rs index 46c9bd089af5..60c6c89f45b6 100644 --- a/library/stdarch/crates/core_arch/src/mips/msa.rs +++ b/library/stdarch/crates/core_arch/src/mips/msa.rs @@ -1137,7 +1137,7 @@ extern "C" { /// Vector Add Absolute Values. /// /// The absolute values of the elements in vector in `a` (sixteen signed 8-bit integer numbers) -/// are added to the absolute values of the elements in vector `b` (sixteen signed 8-bit integer numbers) +/// are added to the absolute values of the elements in vector `b` (sixteen signed 8-bit integer numbers). /// The result is written to vector (sixteen signed 8-bit integer numbers). /// #[inline] @@ -1150,7 +1150,7 @@ pub unsafe fn __msa_add_a_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Add Absolute Values /// /// The absolute values of the elements in vector in `a` (eight signed 16-bit integer numbers) -/// are added to the absolute values of the elements in vector `b` (eight signed 16-bit integer numbers) +/// are added to the absolute values of the elements in vector `b` (eight signed 16-bit integer numbers). /// The result is written to vector (eight signed 16-bit integer numbers). /// #[inline] @@ -1163,7 +1163,7 @@ pub unsafe fn __msa_add_a_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Add Absolute Values /// /// The absolute values of the elements in vector in `a` (four signed 32-bit integer numbers) -/// are added to the absolute values of the elements in vector `b` (four signed 32-bit integer numbers) +/// are added to the absolute values of the elements in vector `b` (four signed 32-bit integer numbers). /// The result is written to vector (four signed 32-bit integer numbers). /// #[inline] @@ -1176,8 +1176,8 @@ pub unsafe fn __msa_add_a_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Add Absolute Values /// /// The absolute values of the elements in vector in `a` (two signed 64-bit integer numbers) -/// are added to the absolute values of the elements in vector `b` (two signed 64-bit integer numbers) -// The result is written to vector (two signed 64-bit integer numbers). +/// are added to the absolute values of the elements in vector `b` (two signed 64-bit integer numbers). +/// The result is written to vector (two signed 64-bit integer numbers). /// #[inline] #[target_feature(enable = "msa")] @@ -1189,7 +1189,7 @@ pub unsafe fn __msa_add_a_d(a: v2i64, b: v2i64) -> v2i64 { /// Signed Saturated Vector Saturated Add of Absolute Values /// /// The absolute values of the elements in vector in `a` (sixteen signed 8-bit integer numbers) -/// are added to the absolute values of the elements in vector `b` (sixteen signed 8-bit integer numbers) +/// are added to the absolute values of the elements in vector `b` (sixteen signed 8-bit integer numbers). /// The saturated signed result is written to vector (sixteen signed 8-bit integer numbers). /// #[inline] @@ -1202,7 +1202,7 @@ pub unsafe fn __msa_adds_a_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Saturated Add of Absolute Values /// /// The absolute values of the elements in vector in `a` (eight signed 16-bit integer numbers) -/// are added to the absolute values of the elements in vector `b` (eight signed 16-bit integer numbers) +/// are added to the absolute values of the elements in vector `b` (eight signed 16-bit integer numbers). /// The saturated signed result is written to vector (eight signed 16-bit integer numbers). /// #[inline] @@ -1215,7 +1215,7 @@ pub unsafe fn __msa_adds_a_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Saturated Add of Absolute Values /// /// The absolute values of the elements in vector in `a` (four signed 32-bit integer numbers) -/// are added to the absolute values of the elements in vector `b` (four signed 32-bit integer numbers) +/// are added to the absolute values of the elements in vector `b` (four signed 32-bit integer numbers). /// The saturated signed result is written to vector (four signed 32-bit integer numbers). /// #[inline] @@ -1228,8 +1228,8 @@ pub unsafe fn __msa_adds_a_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Saturated Add of Absolute Values /// /// The absolute values of the elements in vector in `a` (two signed 64-bit integer numbers) -/// are added to the absolute values of the elements in vector `b` (two signed 64-bit integer numbers) -// The saturated signed result is written to vector (two signed 64-bit integer numbers). +/// are added to the absolute values of the elements in vector `b` (two signed 64-bit integer numbers). +/// The saturated signed result is written to vector (two signed 64-bit integer numbers). /// #[inline] #[target_feature(enable = "msa")] @@ -1241,7 +1241,7 @@ pub unsafe fn __msa_adds_a_d(a: v2i64, b: v2i64) -> v2i64 { /// Vector Signed Saturated Add of Signed Values /// /// The elements in vector in `a` (sixteen signed 8-bit integer numbers) -/// are added to the elements in vector `b` (sixteen signed 8-bit integer numbers) +/// are added to the elements in vector `b` (sixteen signed 8-bit integer numbers). /// Signed arithmetic is performed and overflows clamp to the largest and/or smallest /// representable signed values before writing the result to vector (sixteen signed 8-bit integer numbers). /// @@ -1255,7 +1255,7 @@ pub unsafe fn __msa_adds_s_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Signed Saturated Add of Signed Values /// /// The elements in vector in `a` (eight signed 16-bit integer numbers) -/// are added to the elements in vector `b` (eight signed 16-bit integer numbers) +/// are added to the elements in vector `b` (eight signed 16-bit integer numbers). /// Signed arithmetic is performed and overflows clamp to the largest and/or smallest /// representable signed values before writing the result to vector (eight signed 16-bit integer numbers). /// @@ -1269,7 +1269,7 @@ pub unsafe fn __msa_adds_s_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Signed Saturated Add of Signed Values /// /// The elements in vector in `a` (four signed 32-bit integer numbers) -/// are added to the elements in vector `b` (four signed 32-bit integer numbers) +/// are added to the elements in vector `b` (four signed 32-bit integer numbers). /// Signed arithmetic is performed and overflows clamp to the largest and/or smallest /// representable signed values before writing the result to vector (four signed 32-bit integer numbers). /// @@ -1283,7 +1283,7 @@ pub unsafe fn __msa_adds_s_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Signed Saturated Add of Signed Values /// /// The elements in vector in `a` (two signed 64-bit integer numbers) -/// are added to the elements in vector `b` (two signed 64-bit integer numbers) +/// are added to the elements in vector `b` (two signed 64-bit integer numbers). /// Signed arithmetic is performed and overflows clamp to the largest and/or smallest /// representable signed values before writing the result to vector (two signed 64-bit integer numbers). /// @@ -1297,7 +1297,7 @@ pub unsafe fn __msa_adds_s_d(a: v2i64, b: v2i64) -> v2i64 { /// Vector Unsigned Saturated Add of Unsigned Values /// /// The elements in vector in `a` (sixteen unsigned 8-bit integer numbers) -/// are added to the elements in vector `b` (sixteen unsigned 8-bit integer numbers) +/// are added to the elements in vector `b` (sixteen unsigned 8-bit integer numbers). /// Signed arithmetic is performed and overflows clamp to the largest and/or smallest /// representable signed values before writing the result to vector (sixteen unsigned 8-bit integer numbers). /// @@ -1311,7 +1311,7 @@ pub unsafe fn __msa_adds_u_b(a: v16u8, b: v16u8) -> v16u8 { /// Vector Unsigned Saturated Add of Unsigned Values /// /// The elements in vector in `a` (eight unsigned 16-bit integer numbers) -/// are added to the elements in vector `b` (eight unsigned 16-bit integer numbers) +/// are added to the elements in vector `b` (eight unsigned 16-bit integer numbers). /// Signed arithmetic is performed and overflows clamp to the largest and/or smallest /// representable signed values before writing the result to vector (eight unsigned 16-bit integer numbers). /// @@ -1325,7 +1325,7 @@ pub unsafe fn __msa_adds_u_h(a: v8u16, b: v8u16) -> v8u16 { /// Vector Unsigned Saturated Add of Unsigned Values /// /// The elements in vector in `a` (four unsigned 32-bit integer numbers) -/// are added to the elements in vector `b` (four unsigned 32-bit integer numbers) +/// are added to the elements in vector `b` (four unsigned 32-bit integer numbers). /// Signed arithmetic is performed and overflows clamp to the largest and/or smallest /// representable signed values before writing the result to vector (four unsigned 32-bit integer numbers). /// @@ -1339,7 +1339,7 @@ pub unsafe fn __msa_adds_u_w(a: v4u32, b: v4u32) -> v4u32 { /// Vector Unsigned Saturated Add of Unsigned Values /// /// The elements in vector in `a` (two unsigned 64-bit integer numbers) -/// are added to the elements in vector `b` (two unsigned 64-bit integer numbers) +/// are added to the elements in vector `b` (two unsigned 64-bit integer numbers). /// Signed arithmetic is performed and overflows clamp to the largest and/or smallest /// representable signed values before writing the result to vector (two unsigned 64-bit integer numbers). /// @@ -1353,7 +1353,7 @@ pub unsafe fn __msa_adds_u_d(a: v2u64, b: v2u64) -> v2u64 { /// Vector Add /// /// The elements in vector in `a` (sixteen signed 8-bit integer numbers) -/// are added to the elements in vector `b` (sixteen signed 8-bit integer numbers) +/// are added to the elements in vector `b` (sixteen signed 8-bit integer numbers). /// The result is written to vector (sixteen signed 8-bit integer numbers). /// #[inline] @@ -1366,7 +1366,7 @@ pub unsafe fn __msa_addv_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Add /// /// The elements in vector in `a` (eight signed 16-bit integer numbers) -/// are added to the elements in vector `b` (eight signed 16-bit integer numbers) +/// are added to the elements in vector `b` (eight signed 16-bit integer numbers). /// The result is written to vector (eight signed 16-bit integer numbers). /// #[inline] @@ -1379,7 +1379,7 @@ pub unsafe fn __msa_addv_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Add /// /// The elements in vector in `a` (four signed 32-bit integer numbers) -/// are added to the elements in vector `b` (four signed 32-bit integer numbers) +/// are added to the elements in vector `b` (four signed 32-bit integer numbers). /// The result is written to vector (four signed 32-bit integer numbers). /// #[inline] @@ -1392,7 +1392,7 @@ pub unsafe fn __msa_addv_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Add /// /// The elements in vector in `a` (two signed 64-bit integer numbers) -/// are added to the elements in vector `b` (two signed 64-bit integer numbers) +/// are added to the elements in vector `b` (two signed 64-bit integer numbers). /// The result is written to vector (two signed 64-bit integer numbers). /// #[inline] @@ -1405,7 +1405,7 @@ pub unsafe fn __msa_addv_d(a: v2i64, b: v2i64) -> v2i64 { /// Immediate Add /// /// The 5-bit immediate unsigned value u5 is added to the elements -/// vector in `a` (sixteen signed 8-bit integer numbers) +/// vector in `a` (sixteen signed 8-bit integer numbers). /// The result is written to vector (sixteen signed 8-bit integer numbers). /// #[inline] @@ -1424,7 +1424,7 @@ pub unsafe fn __msa_addvi_b(a: v16i8, imm5: i32) -> v16i8 { /// Immediate Add /// /// The 5-bit immediate unsigned value u5 is added to the elements -/// vector in `a` (eight signed 16-bit integer numbers) +/// vector in `a` (eight signed 16-bit integer numbers). /// The result is written to vector (eight signed 16-bit integer numbers). /// #[inline] @@ -1443,7 +1443,7 @@ pub unsafe fn __msa_addvi_h(a: v8i16, imm5: i32) -> v8i16 { /// Immediate Add /// /// The 5-bit immediate unsigned value u5 is added to the elements -/// vector in `a` (four signed 32-bit integer numbers) +/// vector in `a` (four signed 32-bit integer numbers). /// The result is written to vector (four signed 32-bit integer numbers). /// #[inline] @@ -1462,7 +1462,7 @@ pub unsafe fn __msa_addvi_w(a: v4i32, imm5: i32) -> v4i32 { /// Immediate Add /// /// The 5-bit immediate unsigned value u5 is added to the elements -/// vector in `a` (two signed 64-bit integer numbers) +/// vector in `a` (two signed 64-bit integer numbers). /// The result is written to vector (two signed 64-bit integer numbers). /// #[inline] @@ -1481,7 +1481,7 @@ pub unsafe fn __msa_addvi_d(a: v2i64, imm5: i32) -> v2i64 { /// Vector Logical And /// /// Each bit of vector `a` (sixteen unsigned 8-bit integer numbers) -/// is combined with the corresponding bit of vector 'b' (sixteen unsigned 8-bit integer numbers). +/// is combined with the corresponding bit of vector `b` (sixteen unsigned 8-bit integer numbers) /// in a bitwise logical AND operation. /// The result is written to vector (sixteen unsigned 8-bit integer numbers). /// @@ -1922,7 +1922,7 @@ pub unsafe fn __msa_bclr_d(a: v2u64, b: v2u64) -> v2u64 { /// Immediate Bit Clear /// /// Clear (set to 0) one bit in each element of vector `a` (sixteen unsigned 8-bit integer numbers) -/// The bit position is given by the immediate 'm' modulo the size of the element in bits. +/// The bit position is given by the immediate `m` modulo the size of the element in bits. /// The result is written to vector (sixteen unsigned 8-bit integer numbers). /// #[inline] @@ -1941,7 +1941,7 @@ pub unsafe fn __msa_bclri_b(a: v16u8, imm3: i32) -> v16u8 { /// Immediate Bit Clear /// /// Clear (set to 0) one bit in each element of vector `a` (eight unsigned 16-bit integer numbers) -/// The bit position is given by the immediate 'm' modulo the size of the element in bits. +/// The bit position is given by the immediate `m` modulo the size of the element in bits. /// The result is written to vector (eight unsigned 16-bit integer numbers). /// #[inline] @@ -1960,7 +1960,7 @@ pub unsafe fn __msa_bclri_h(a: v8u16, imm4: i32) -> v8u16 { /// Immediate Bit Clear /// /// Clear (set to 0) one bit in each element of vector `a` (four unsigned 32-bit integer numbers) -/// The bit position is given by the immediate 'm' modulo the size of the element in bits. +/// The bit position is given by the immediate `m` modulo the size of the element in bits. /// The result is written to vector (four unsigned 32-bit integer numbers). /// #[inline] @@ -1979,7 +1979,7 @@ pub unsafe fn __msa_bclri_w(a: v4u32, imm5: i32) -> v4u32 { /// Immediate Bit Clear /// /// Clear (set to 0) one bit in each element of vector `a` (two unsigned 64-bit integer numbers) -/// The bit position is given by the immediate 'm' modulo the size of the element in bits. +/// The bit position is given by the immediate `m` modulo the size of the element in bits. /// The result is written to vector (two unsigned 64-bit integer numbers). /// #[inline] @@ -1998,9 +1998,9 @@ pub unsafe fn __msa_bclri_d(a: v2u64, imm6: i32) -> v2u64 { /// Vector Bit Insert Left /// /// Copy most significant (left) bits in each element of vector `b` (sixteen unsigned 8-bit integer numbers) -/// to elements in vector 'a' (sixteen unsigned 8-bit integer numbers) while preserving the least sig-nificant (right) bits. -/// The number of bits to copy is given by the elements in vector 'c' (sixteen unsigned 8-bit integer numbers) -/// modulo the size of the element inbits plus 1. +/// to elements in vector `a` (sixteen unsigned 8-bit integer numbers) while preserving the least significant (right) bits. +/// The number of bits to copy is given by the elements in vector `c` (sixteen unsigned 8-bit integer numbers) +/// modulo the size of the element in bits plus 1. /// #[inline] #[target_feature(enable = "msa")] @@ -2012,9 +2012,9 @@ pub unsafe fn __msa_binsl_b(a: v16u8, b: v16u8, c: v16u8) -> v16u8 { /// Vector Bit Insert Left /// /// Copy most significant (left) bits in each element of vector `b` (eight unsigned 16-bit integer numbers) -/// to elements in vector 'a' (eight unsigned 16-bit integer numbers) while preserving the least sig-nificant (right) bits. -/// The number of bits to copy is given by the elements in vector 'c' (eight unsigned 16-bit integer numbers) -/// modulo the size of the element inbits plus 1. +/// to elements in vector `a` (eight unsigned 16-bit integer numbers) while preserving the least significant (right) bits. +/// The number of bits to copy is given by the elements in vector `c` (eight unsigned 16-bit integer numbers) +/// modulo the size of the element in bits plus 1. /// #[inline] #[target_feature(enable = "msa")] @@ -2026,9 +2026,9 @@ pub unsafe fn __msa_binsl_h(a: v8u16, b: v8u16, c: v8u16) -> v8u16 { /// Vector Bit Insert Left /// /// Copy most significant (left) bits in each element of vector `b` (four unsigned 32-bit integer numbers) -/// to elements in vector 'a' (four unsigned 32-bit integer numbers) while preserving the least sig-nificant (right) bits. -/// The number of bits to copy is given by the elements in vector 'c' (four unsigned 32-bit integer numbers) -/// modulo the size of the element inbits plus 1. +/// to elements in vector `a` (four unsigned 32-bit integer numbers) while preserving the least significant (right) bits. +/// The number of bits to copy is given by the elements in vector `c` (four unsigned 32-bit integer numbers) +/// modulo the size of the element in bits plus 1. /// #[inline] #[target_feature(enable = "msa")] @@ -2040,9 +2040,9 @@ pub unsafe fn __msa_binsl_w(a: v4u32, b: v4u32, c: v4u32) -> v4u32 { /// Vector Bit Insert Left /// /// Copy most significant (left) bits in each element of vector `b` (two unsigned 64-bit integer numbers) -/// to elements in vector 'a' (two unsigned 64-bit integer numbers) while preserving the least sig-nificant (right) bits. -/// The number of bits to copy is given by the elements in vector 'c' (two unsigned 64-bit integer numbers) -/// modulo the size of the element inbits plus 1. +/// to elements in vector `a` (two unsigned 64-bit integer numbers) while preserving the least significant (right) bits. +/// The number of bits to copy is given by the elements in vector `c` (two unsigned 64-bit integer numbers) +/// modulo the size of the element in bits plus 1. /// #[inline] #[target_feature(enable = "msa")] @@ -2054,8 +2054,8 @@ pub unsafe fn __msa_binsl_d(a: v2u64, b: v2u64, c: v2u64) -> v2u64 { /// Immediate Bit Insert Left /// /// Copy most significant (left) bits in each element of vector `b` (sixteen unsigned 8-bit integer numbers) -/// to elements in vector 'a' (sixteen unsigned 8-bit integer numbers) while preserving the least sig-nificant (right) bits. -/// The number of bits to copy is given by the immediate imm3 modulo the size of the element in bitsplus 1. +/// to elements in vector `a` (sixteen unsigned 8-bit integer numbers) while preserving the least significant (right) bits. +/// The number of bits to copy is given by the immediate imm3 modulo the size of the element in bits plus 1. /// #[inline] #[target_feature(enable = "msa")] @@ -2073,8 +2073,8 @@ pub unsafe fn __msa_binsli_b(a: v16u8, b: v16u8, imm3: i32) -> v16u8 { /// Immediate Bit Insert Left /// /// Copy most significant (left) bits in each element of vector `b` (eight unsigned 16-bit integer numbers) -/// to elements in vector 'a' (eight unsigned 16-bit integer numbers) while preserving the least sig-nificant (right) bits. -/// The number of bits to copy is given by the immediate imm4 modulo the size of the element in bitsplus 1. +/// to elements in vector `a` (eight unsigned 16-bit integer numbers) while preserving the least significant (right) bits. +/// The number of bits to copy is given by the immediate imm4 modulo the size of the element in bits plus 1. /// #[inline] #[target_feature(enable = "msa")] @@ -2092,8 +2092,8 @@ pub unsafe fn __msa_binsli_h(a: v8u16, b: v8u16, imm4: i32) -> v8u16 { /// Immediate Bit Insert Left /// /// Copy most significant (left) bits in each element of vector `b` (four unsigned 32-bit integer numbers) -/// to elements in vector 'a' (four unsigned 32-bit integer numbers) while preserving the least sig-nificant (right) bits. -/// The number of bits to copy is given by the immediate imm5 modulo the size of the element in bitsplus 1. +/// to elements in vector `a` (four unsigned 32-bit integer numbers) while preserving the least significant (right) bits. +/// The number of bits to copy is given by the immediate imm5 modulo the size of the element in bits plus 1. /// #[inline] #[target_feature(enable = "msa")] @@ -2111,8 +2111,8 @@ pub unsafe fn __msa_binsli_w(a: v4u32, b: v4u32, imm5: i32) -> v4u32 { /// Immediate Bit Insert Left /// /// Copy most significant (left) bits in each element of vector `b` (two unsigned 64-bit integer numbers) -/// to elements in vector 'a' (two unsigned 64-bit integer numbers) while preserving the least sig-nificant (right) bits. -/// The number of bits to copy is given by the immediate imm6 modulo the size of the element in bitsplus 1. +/// to elements in vector `a` (two unsigned 64-bit integer numbers) while preserving the least significant (right) bits. +/// The number of bits to copy is given by the immediate imm6 modulo the size of the element in bits plus 1. /// #[inline] #[target_feature(enable = "msa")] @@ -2130,9 +2130,9 @@ pub unsafe fn __msa_binsli_d(a: v2u64, b: v2u64, imm6: i32) -> v2u64 { /// Vector Bit Insert Right /// /// Copy most significant (right) bits in each element of vector `b` (sixteen unsigned 8-bit integer numbers) -/// to elements in vector 'a' (sixteen unsigned 8-bit integer numbers) while preserving the least sig-nificant (left) bits. -/// The number of bits to copy is given by the elements in vector 'c' (sixteen unsigned 8-bit integer numbers) -/// modulo the size of the element inbits plus 1. +/// to elements in vector `a` (sixteen unsigned 8-bit integer numbers) while preserving the least significant (left) bits. +/// The number of bits to copy is given by the elements in vector `c` (sixteen unsigned 8-bit integer numbers) +/// modulo the size of the element in bits plus 1. /// #[inline] #[target_feature(enable = "msa")] @@ -2144,9 +2144,9 @@ pub unsafe fn __msa_binsr_b(a: v16u8, b: v16u8, c: v16u8) -> v16u8 { /// Vector Bit Insert Right /// /// Copy most significant (right) bits in each element of vector `b` (eight unsigned 16-bit integer numbers) -/// to elements in vector 'a' (eight unsigned 16-bit integer numbers) while preserving the least sig-nificant (left) bits. -/// The number of bits to copy is given by the elements in vector 'c' (eight unsigned 16-bit integer numbers) -/// modulo the size of the element inbits plus 1. +/// to elements in vector `a` (eight unsigned 16-bit integer numbers) while preserving the least significant (left) bits. +/// The number of bits to copy is given by the elements in vector `c` (eight unsigned 16-bit integer numbers) +/// modulo the size of the element in bits plus 1. /// #[inline] #[target_feature(enable = "msa")] @@ -2158,9 +2158,9 @@ pub unsafe fn __msa_binsr_h(a: v8u16, b: v8u16, c: v8u16) -> v8u16 { /// Vector Bit Insert Right /// /// Copy most significant (right) bits in each element of vector `b` (four unsigned 32-bit integer numbers) -/// to elements in vector 'a' (four unsigned 32-bit integer numbers) while preserving the least sig-nificant (left) bits. -/// The number of bits to copy is given by the elements in vector 'c' (four unsigned 32-bit integer numbers) -/// modulo the size of the element inbits plus 1. +/// to elements in vector `a` (four unsigned 32-bit integer numbers) while preserving the least significant (left) bits. +/// The number of bits to copy is given by the elements in vector `c` (four unsigned 32-bit integer numbers) +/// modulo the size of the element in bits plus 1. /// #[inline] #[target_feature(enable = "msa")] @@ -2172,9 +2172,9 @@ pub unsafe fn __msa_binsr_w(a: v4u32, b: v4u32, c: v4u32) -> v4u32 { /// Vector Bit Insert Right /// /// Copy most significant (right) bits in each element of vector `b` (two unsigned 64-bit integer numbers) -/// to elements in vector 'a' (two unsigned 64-bit integer numbers) while preserving the least sig-nificant (left) bits. -/// The number of bits to copy is given by the elements in vector 'c' (two unsigned 64-bit integer numbers) -/// modulo the size of the element inbits plus 1. +/// to elements in vector `a` (two unsigned 64-bit integer numbers) while preserving the least significant (left) bits. +/// The number of bits to copy is given by the elements in vector `c` (two unsigned 64-bit integer numbers) +/// modulo the size of the element in bits plus 1. /// #[inline] #[target_feature(enable = "msa")] @@ -2186,8 +2186,8 @@ pub unsafe fn __msa_binsr_d(a: v2u64, b: v2u64, c: v2u64) -> v2u64 { /// Immediate Bit Insert Right /// /// Copy most significant (right) bits in each element of vector `b` (sixteen unsigned 8-bit integer numbers) -/// to elements in vector 'a' (sixteen unsigned 8-bit integer numbers) while preserving the least sig-nificant (left) bits. -/// The number of bits to copy is given by the immediate imm3 modulo the size of the element in bitsplus 1. +/// to elements in vector `a` (sixteen unsigned 8-bit integer numbers) while preserving the least significant (left) bits. +/// The number of bits to copy is given by the immediate imm3 modulo the size of the element in bits plus 1. /// #[inline] #[target_feature(enable = "msa")] @@ -2205,8 +2205,8 @@ pub unsafe fn __msa_binsri_b(a: v16u8, b: v16u8, imm3: i32) -> v16u8 { /// Immediate Bit Insert Right /// /// Copy most significant (right) bits in each element of vector `b` (eight unsigned 16-bit integer numbers) -/// to elements in vector 'a' (eight unsigned 16-bit integer numbers) while preserving the least sig-nificant (left) bits. -/// The number of bits to copy is given by the immediate imm4 modulo the size of the element in bitsplus 1. +/// to elements in vector `a` (eight unsigned 16-bit integer numbers) while preserving the least significant (left) bits. +/// The number of bits to copy is given by the immediate imm4 modulo the size of the element in bits plus 1. /// #[inline] #[target_feature(enable = "msa")] @@ -2224,8 +2224,8 @@ pub unsafe fn __msa_binsri_h(a: v8u16, b: v8u16, imm4: i32) -> v8u16 { /// Immediate Bit Insert Right /// /// Copy most significant (right) bits in each element of vector `b` (four unsigned 32-bit integer numbers) -/// to elements in vector 'a' (four unsigned 32-bit integer numbers) while preserving the least sig-nificant (left) bits. -/// The number of bits to copy is given by the immediate imm5 modulo the size of the element in bitsplus 1. +/// to elements in vector `a` (four unsigned 32-bit integer numbers) while preserving the least significant (left) bits. +/// The number of bits to copy is given by the immediate imm5 modulo the size of the element in bits plus 1. /// #[inline] #[target_feature(enable = "msa")] @@ -2243,8 +2243,8 @@ pub unsafe fn __msa_binsri_w(a: v4u32, b: v4u32, imm5: i32) -> v4u32 { /// Immediate Bit Insert Right /// /// Copy most significant (right) bits in each element of vector `b` (two unsigned 64-bit integer numbers) -/// to elements in vector 'a' (two unsigned 64-bit integer numbers) while preserving the least sig-nificant (left) bits. -/// The number of bits to copy is given by the immediate imm6 modulo the size of the element in bitsplus 1. +/// to elements in vector `a` (two unsigned 64-bit integer numbers) while preserving the least significant (left) bits. +/// The number of bits to copy is given by the immediate imm6 modulo the size of the element in bits plus 1. /// #[inline] #[target_feature(enable = "msa")] @@ -2261,8 +2261,8 @@ pub unsafe fn __msa_binsri_d(a: v2u64, b: v2u64, imm6: i32) -> v2u64 { /// Vector Bit Move If Not Zero /// -/// Copy to destination vector 'a' (sixteen unsigned 8-bit integer numbers) all bits from source vector -/// 'b' (sixteen unsigned 8-bit integer numbers) for which the corresponding bits from target vector 'c' +/// Copy to destination vector `a` (sixteen unsigned 8-bit integer numbers) all bits from source vector +/// `b` (sixteen unsigned 8-bit integer numbers) for which the corresponding bits from target vector `c` /// (sixteen unsigned 8-bit integer numbers) are 1 and leaves unchanged all destination bits /// for which the corresponding target bits are 0. /// @@ -2275,8 +2275,8 @@ pub unsafe fn __msa_bmnz_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 { /// Immediate Bit Move If Not Zero /// -/// Copy to destination vector 'a' (sixteen unsigned 8-bit integer numbers) all bits from source vector -/// 'b' (sixteen unsigned 8-bit integer numbers) for which the corresponding bits from from immediate imm8 +/// Copy to destination vector `a` (sixteen unsigned 8-bit integer numbers) all bits from source vector +/// `b` (sixteen unsigned 8-bit integer numbers) for which the corresponding bits from from immediate imm8 /// are 1 and leaves unchanged all destination bits for which the corresponding target bits are 0. /// #[inline] @@ -2294,8 +2294,8 @@ pub unsafe fn __msa_bmnzi_b(a: v16u8, b: v16u8, imm8: i32) -> v16u8 { /// Vector Bit Move If Zero /// -/// Copy to destination vector 'a' (sixteen unsigned 8-bit integer numbers) all bits from source vector -/// 'b' (sixteen unsigned 8-bit integer numbers) for which the corresponding bits from target vector 'c' +/// Copy to destination vector `a` (sixteen unsigned 8-bit integer numbers) all bits from source vector +/// `b` (sixteen unsigned 8-bit integer numbers) for which the corresponding bits from target vector `c` /// (sixteen unsigned 8-bit integer numbers) are 0 and leaves unchanged all destination bits /// for which the corresponding target bits are 1 /// @@ -2308,8 +2308,8 @@ pub unsafe fn __msa_bmz_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 { /// Immediate Bit Move If Zero /// -/// Copy to destination vector 'a' (sixteen unsigned 8-bit integer numbers) all bits from source vector -/// 'b' (sixteen unsigned 8-bit integer numbers) for which the corresponding bits from from immediate imm8 +/// Copy to destination vector `a` (sixteen unsigned 8-bit integer numbers) all bits from source vector +/// `b` (sixteen unsigned 8-bit integer numbers) for which the corresponding bits from from immediate imm8 /// are 0 and leaves unchanged all destination bits for which the corresponding immediate bits are 1. /// #[inline] @@ -2328,7 +2328,7 @@ pub unsafe fn __msa_bmzi_b(a: v16u8, b: v16u8, imm8: i32) -> v16u8 { /// Vector Bit Negate /// /// Negate (complement) one bit in each element of vector `a` (sixteen unsigned 8-bit integer numbers) -/// The bit position is given by the elements in vector 'b' (sixteen unsigned 8-bit integer numbers) +/// The bit position is given by the elements in vector `b` (sixteen unsigned 8-bit integer numbers) /// modulo thesize of the element in bits. /// The result is written to vector (sixteen unsigned 8-bit integer numbers) /// @@ -2342,7 +2342,7 @@ pub unsafe fn __msa_bneg_b(a: v16u8, b: v16u8) -> v16u8 { /// Vector Bit Negate /// /// Negate (complement) one bit in each element of vector `a` (eight unsigned 16-bit integer numbers) -/// The bit position is given by the elements in vector 'b' (eight unsigned 16-bit integer numbers) +/// The bit position is given by the elements in vector `b` (eight unsigned 16-bit integer numbers) /// modulo thesize of the element in bits. /// The result is written to vector (eight unsigned 16-bit integer numbers) /// @@ -2356,7 +2356,7 @@ pub unsafe fn __msa_bneg_h(a: v8u16, b: v8u16) -> v8u16 { /// Vector Bit Negate /// /// Negate (complement) one bit in each element of vector `a` (four unsigned 32-bit integer numbers) -/// The bit position is given by the elements in vector 'b' (four unsigned 32-bit integer numbers) +/// The bit position is given by the elements in vector `b` (four unsigned 32-bit integer numbers) /// modulo thesize of the element in bits. /// The result is written to vector (four unsigned 32-bit integer numbers) /// @@ -2370,7 +2370,7 @@ pub unsafe fn __msa_bneg_w(a: v4u32, b: v4u32) -> v4u32 { /// Vector Bit Negate /// /// Negate (complement) one bit in each element of vector `a` (two unsigned 64-bit integer numbers) -/// The bit position is given by the elements in vector 'b' (two unsigned 64-bit integer numbers) +/// The bit position is given by the elements in vector `b` (two unsigned 64-bit integer numbers) /// modulo thesize of the element in bits. /// The result is written to vector (two unsigned 64-bit integer numbers) /// @@ -2459,7 +2459,7 @@ pub unsafe fn __msa_bnegi_d(a: v2u64, imm6: i32) -> v2u64 { /// Immediate Branch If All Elements Are Not Zero /// -/// PC-relative branch if all elements in 'a' (sixteen unsigned 8-bit integer numbers) are not zero. +/// PC-relative branch if all elements in `a` (sixteen unsigned 8-bit integer numbers) are not zero. /// #[inline] #[target_feature(enable = "msa")] @@ -2470,7 +2470,7 @@ pub unsafe fn __msa_bnz_b(a: v16u8) -> i32 { /// Immediate Branch If All Elements Are Not Zero /// -/// PC-relative branch if all elements in 'a' (eight unsigned 16-bit integer numbers) are not zero. +/// PC-relative branch if all elements in `a` (eight unsigned 16-bit integer numbers) are not zero. /// #[inline] #[target_feature(enable = "msa")] @@ -2481,7 +2481,7 @@ pub unsafe fn __msa_bnz_h(a: v8u16) -> i32 { /// Immediate Branch If All Elements Are Not Zero /// -/// PC-relative branch if all elements in 'a' (four unsigned 32-bit integer numbers) are not zero. +/// PC-relative branch if all elements in `a` (four unsigned 32-bit integer numbers) are not zero. /// #[inline] #[target_feature(enable = "msa")] @@ -2492,7 +2492,7 @@ pub unsafe fn __msa_bnz_w(a: v4u32) -> i32 { /// Immediate Branch If All Elements Are Not Zero /// -/// PC-relative branch if all elements in 'a' (two unsigned 64-bit integer numbers) are not zero. +/// PC-relative branch if all elements in `a` (two unsigned 64-bit integer numbers) are not zero. /// #[inline] #[target_feature(enable = "msa")] @@ -2503,7 +2503,7 @@ pub unsafe fn __msa_bnz_d(a: v2u64) -> i32 { /// Immediate Branch If Not Zero (At Least One Element of Any Format Is Not Zero) /// -/// PC-relative branch if at least one bit in 'a' (four unsigned 32-bit integer numbers) are not zero. +/// PC-relative branch if at least one bit in `a` (four unsigned 32-bit integer numbers) are not zero. /// i.e at least one element is not zero regardless of the data format. /// #[inline] @@ -2515,10 +2515,10 @@ pub unsafe fn __msa_bnz_v(a: v16u8) -> i32 { /// Vector Bit Select /// -/// Selectively copy bits from the source vectors 'b' (eight unsigned 16-bit integer numbers) -/// and 'c' (eight unsigned 16-bit integer numbers) -/// into destination vector 'a' (eight unsigned 16-bit integer numbers) based on the corresponding bit in a: -/// if 0 copies the bit from 'b', if 1 copies the bit from 'c'. +/// Selectively copy bits from the source vectors `b` (eight unsigned 16-bit integer numbers) +/// and `c` (eight unsigned 16-bit integer numbers) +/// into destination vector `a` (eight unsigned 16-bit integer numbers) based on the corresponding bit in `a`: +/// if 0 copies the bit from `b`, if 1 copies the bit from `c`. /// #[inline] #[target_feature(enable = "msa")] @@ -2529,9 +2529,9 @@ pub unsafe fn __msa_bsel_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 { /// Immediate Bit Select /// -/// Selectively copy bits from the 8-bit immediate imm8 and 'c' (eight unsigned 16-bit integer numbers) -/// into destination vector 'a' (eight unsigned 16-bit integer numbers) based on the corresponding bit in a: -/// if 0 copies the bit from 'b', if 1 copies the bit from 'c'. +/// Selectively copy bits from the 8-bit immediate imm8 and `c` (eight unsigned 16-bit integer numbers) +/// into destination vector `a` (eight unsigned 16-bit integer numbers) based on the corresponding bit in `a`: +/// if 0 copies the bit from `b`, if 1 copies the bit from `c`. /// #[inline] #[target_feature(enable = "msa")] @@ -2549,7 +2549,7 @@ pub unsafe fn __msa_bseli_b(a: v16u8, b: v16u8, imm8: i32) -> v16u8 { /// Vector Bit Set /// /// Set to 1 one bit in each element of vector `a` (sixteen unsigned 8-bit integer numbers) -/// The bit position is given by the elements in vector 'b' (sixteen unsigned 8-bit integer numbers) +/// The bit position is given by the elements in vector `b` (sixteen unsigned 8-bit integer numbers) /// modulo the size of the element in bits. /// The result is written to vector (sixteen unsigned 8-bit integer numbers) /// @@ -2563,7 +2563,7 @@ pub unsafe fn __msa_bset_b(a: v16u8, b: v16u8) -> v16u8 { /// Vector Bit Set /// /// Set to 1 one bit in each element of vector `a` (eight unsigned 16-bit integer numbers) -/// The bit position is given by the elements in vector 'b' (eight unsigned 16-bit integer numbers) +/// The bit position is given by the elements in vector `b` (eight unsigned 16-bit integer numbers) /// modulo the size of the element in bits. /// The result is written to vector (eight unsigned 16-bit integer numbers) /// @@ -2577,7 +2577,7 @@ pub unsafe fn __msa_bset_h(a: v8u16, b: v8u16) -> v8u16 { /// Vector Bit Set /// /// Set to 1 one bit in each element of vector `a` (four unsigned 32-bit integer numbers) -/// The bit position is given by the elements in vector 'b' (four unsigned 32-bit integer numbers) +/// The bit position is given by the elements in vector `b` (four unsigned 32-bit integer numbers) /// modulo the size of the element in bits. /// The result is written to vector (four unsigned 32-bit integer numbers) /// @@ -2591,7 +2591,7 @@ pub unsafe fn __msa_bset_w(a: v4u32, b: v4u32) -> v4u32 { /// Vector Bit Set /// /// Set to 1 one bit in each element of vector `a` (two unsigned 64-bit integer numbers) -/// The bit position is given by the elements in vector 'b' (two unsigned 64-bit integer numbers) +/// The bit position is given by the elements in vector `b` (two unsigned 64-bit integer numbers) /// modulo the size of the element in bits. /// The result is written to vector (two unsigned 64-bit integer numbers) /// @@ -2606,7 +2606,7 @@ pub unsafe fn __msa_bset_d(a: v2u64, b: v2u64) -> v2u64 { /// /// Set to 1 one bit in each element of vector `a` (sixteen unsigned 8-bit integer numbers) /// The bit position is given by immediate imm3. -/// The result is written to vector 'a'(sixteen unsigned 8-bit integer numbers) +/// The result is written to vector `a` (sixteen unsigned 8-bit integer numbers) /// #[inline] #[target_feature(enable = "msa")] @@ -2625,7 +2625,7 @@ pub unsafe fn __msa_bseti_b(a: v16u8, imm3: i32) -> v16u8 { /// /// Set to 1 one bit in each element of vector `a` (eight unsigned 16-bit integer numbers) /// The bit position is given by immediate imm4. -/// The result is written to vector 'a'(eight unsigned 16-bit integer numbers) +/// The result is written to vector `a` (eight unsigned 16-bit integer numbers) /// #[inline] #[target_feature(enable = "msa")] @@ -2644,7 +2644,7 @@ pub unsafe fn __msa_bseti_h(a: v8u16, imm4: i32) -> v8u16 { /// /// Set to 1 one bit in each element of vector `a` (four unsigned 32-bit integer numbers) /// The bit position is given by immediate imm5. -/// The result is written to vector 'a'(four unsigned 32-bit integer numbers) +/// The result is written to vector `a` (four unsigned 32-bit integer numbers) /// #[inline] #[target_feature(enable = "msa")] @@ -2663,7 +2663,7 @@ pub unsafe fn __msa_bseti_w(a: v4u32, imm5: i32) -> v4u32 { /// /// Set to 1 one bit in each element of vector `a` (two unsigned 64-bit integer numbers) /// The bit position is given by immediate imm6. -/// The result is written to vector 'a'(two unsigned 64-bit integer numbers) +/// The result is written to vector `a` (two unsigned 64-bit integer numbers) /// #[inline] #[target_feature(enable = "msa")] @@ -2680,7 +2680,7 @@ pub unsafe fn __msa_bseti_d(a: v2u64, imm6: i32) -> v2u64 { /// Immediate Branch If At Least One Element Is Zero /// -/// PC-relative branch if at least one element in 'a' (sixteen unsigned 8-bit integer numbers) is zero. +/// PC-relative branch if at least one element in `a` (sixteen unsigned 8-bit integer numbers) is zero. /// #[inline] #[target_feature(enable = "msa")] @@ -2691,7 +2691,7 @@ pub unsafe fn __msa_bz_b(a: v16u8) -> i32 { /// Immediate Branch If At Least One Element Is Zero /// -/// PC-relative branch if at least one element in 'a' (eight unsigned 16-bit integer numbers) is zero. +/// PC-relative branch if at least one element in `a` (eight unsigned 16-bit integer numbers) is zero. /// #[inline] #[target_feature(enable = "msa")] @@ -2702,7 +2702,7 @@ pub unsafe fn __msa_bz_h(a: v8u16) -> i32 { /// Immediate Branch If At Least One Element Is Zero /// -/// PC-relative branch if at least one element in 'a' (four unsigned 32-bit integer numbers) is zero. +/// PC-relative branch if at least one element in `a` (four unsigned 32-bit integer numbers) is zero. /// #[inline] #[target_feature(enable = "msa")] @@ -2713,7 +2713,7 @@ pub unsafe fn __msa_bz_w(a: v4u32) -> i32 { /// Immediate Branch If At Least One Element Is Zero /// -/// PC-relative branch if at least one element in 'a' (two unsigned 64-bit integer numbers) is zero. +/// PC-relative branch if at least one element in `a` (two unsigned 64-bit integer numbers) is zero. /// #[inline] #[target_feature(enable = "msa")] @@ -2724,7 +2724,7 @@ pub unsafe fn __msa_bz_d(a: v2u64) -> i32 { /// Immediate Branch If Zero (All Elements of Any Format Are Zero) /// -/// PC-relative branch if all elements in 'a' (sixteen unsigned 8-bit integer numbers) bits are zero, +/// PC-relative branch if all elements in `a` (sixteen unsigned 8-bit integer numbers) bits are zero, /// i.e. all elements are zero regardless of the data format /// #[inline] @@ -2737,7 +2737,7 @@ pub unsafe fn __msa_bz_v(a: v16u8) -> i32 { /// Vector Compare Equal /// /// Set all bits to 1 in vector (sixteen signed 8-bit integer numbers) elements -/// if the corresponding 'a' (sixteen signed 8-bit integer numbers) and 'b' (sixteen signed 8-bit integer numbers) +/// if the corresponding `a` (sixteen signed 8-bit integer numbers) and `b` (sixteen signed 8-bit integer numbers) /// elements are equal, otherwise set all bits to 0. /// #[inline] @@ -2750,7 +2750,7 @@ pub unsafe fn __msa_ceq_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Compare Equal /// /// Set all bits to 1 in vector (eight signed 16-bit integer numbers) elements -/// if the corresponding 'a' (eight signed 16-bit integer numbers) and 'b' (eight signed 16-bit integer numbers) +/// if the corresponding `a` (eight signed 16-bit integer numbers) and `b` (eight signed 16-bit integer numbers) /// elements are equal, otherwise set all bits to 0. /// #[inline] @@ -2763,7 +2763,7 @@ pub unsafe fn __msa_ceq_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Compare Equal /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements -/// if the corresponding 'a' (four signed 32-bit integer numbers) and 'b' (four signed 32-bit integer numbers) +/// if the corresponding `a` (four signed 32-bit integer numbers) and `b` (four signed 32-bit integer numbers) /// elements are equal, otherwise set all bits to 0. /// #[inline] @@ -2776,7 +2776,7 @@ pub unsafe fn __msa_ceq_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Compare Equal /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements -/// if the corresponding 'a' (two signed 64-bit integer numbers) and 'b' (two signed 64-bit integer numbers) +/// if the corresponding `a` (two signed 64-bit integer numbers) and `b` (two signed 64-bit integer numbers) /// elements are equal, otherwise set all bits to 0. /// #[inline] @@ -2789,7 +2789,7 @@ pub unsafe fn __msa_ceq_d(a: v2i64, b: v2i64) -> v2i64 { /// Immediate Compare Equal /// /// Set all bits to 1 in vector (sixteen signed 8-bit integer numbers) elements -/// if the corresponding 'a' (sixteen signed 8-bit integer numbers) the 5-bit signed immediate imm_s5 +/// if the corresponding `a` (sixteen signed 8-bit integer numbers) the 5-bit signed immediate imm_s5 /// are equal, otherwise set all bits to 0. /// #[inline] @@ -2808,7 +2808,7 @@ pub unsafe fn __msa_ceqi_b(a: v16i8, imm_s5: i32) -> v16i8 { /// Immediate Compare Equal /// /// Set all bits to 1 in vector (eight signed 16-bit integer numbers) elements -/// if the corresponding 'a' (eight signed 16-bit integer numbers) the 5-bit signed immediate imm_s5 +/// if the corresponding `a` (eight signed 16-bit integer numbers) the 5-bit signed immediate imm_s5 /// are equal, otherwise set all bits to 0. /// #[inline] @@ -2827,7 +2827,7 @@ pub unsafe fn __msa_ceqi_h(a: v8i16, imm_s5: i32) -> v8i16 { /// Immediate Compare Equal /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements -/// if the corresponding 'a' (four signed 32-bit integer numbers) the 5-bit signed immediate imm_s5 +/// if the corresponding `a` (four signed 32-bit integer numbers) the 5-bit signed immediate imm_s5 /// are equal, otherwise set all bits to 0. /// #[inline] @@ -2846,7 +2846,7 @@ pub unsafe fn __msa_ceqi_w(a: v4i32, imm_s5: i32) -> v4i32 { /// Immediate Compare Equal /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements -/// if the corresponding 'a' (two signed 64-bit integer numbers) the 5-bit signed immediate imm_s5 +/// if the corresponding `a` (two signed 64-bit integer numbers) the 5-bit signed immediate imm_s5 /// are equal, otherwise set all bits to 0. /// #[inline] @@ -2883,8 +2883,8 @@ pub unsafe fn __msa_cfcmsa(imm5: i32) -> i32 { /// Vector Compare Signed Less Than or Equal /// /// Set all bits to 1 in vector (sixteen signed 8-bit integer numbers) elements -/// if the corresponding 'a' (sixteen signed 8-bit integer numbers) element -/// are signed less than or equal to 'b' (sixteen signed 8-bit integer numbers) element. +/// if the corresponding `a` (sixteen signed 8-bit integer numbers) element +/// are signed less than or equal to `b` (sixteen signed 8-bit integer numbers) element. /// otherwise set all bits to 0. /// #[inline] @@ -2897,8 +2897,8 @@ pub unsafe fn __msa_cle_s_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Compare Signed Less Than or Equal /// /// Set all bits to 1 in vector (eight signed 16-bit integer numbers) elements -/// if the corresponding 'a' (eight signed 16-bit integer numbers) element -/// are signed less than or equal to 'b' (eight signed 16-bit integer numbers) element. +/// if the corresponding `a` (eight signed 16-bit integer numbers) element +/// are signed less than or equal to `b` (eight signed 16-bit integer numbers) element. /// otherwise set all bits to 0. /// #[inline] @@ -2911,8 +2911,8 @@ pub unsafe fn __msa_cle_s_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Compare Signed Less Than or Equal /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements -/// if the corresponding 'a' (four signed 32-bit integer numbers) element -/// are signed less than or equal to 'b' (four signed 32-bit integer numbers) element. +/// if the corresponding `a` (four signed 32-bit integer numbers) element +/// are signed less than or equal to `b` (four signed 32-bit integer numbers) element. /// otherwise set all bits to 0. /// #[inline] @@ -2925,8 +2925,8 @@ pub unsafe fn __msa_cle_s_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Compare Signed Less Than or Equal /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements -/// if the corresponding 'a' (two signed 64-bit integer numbers) element -/// are signed less than or equal to 'b' (two signed 64-bit integer numbers) element. +/// if the corresponding `a` (two signed 64-bit integer numbers) element +/// are signed less than or equal to `b` (two signed 64-bit integer numbers) element. /// otherwise set all bits to 0. /// #[inline] @@ -2939,8 +2939,8 @@ pub unsafe fn __msa_cle_s_d(a: v2i64, b: v2i64) -> v2i64 { /// Vector Compare Unsigned Less Than or Equal /// /// Set all bits to 1 in vector (sixteen signed 8-bit integer numbers) elements -/// if the corresponding 'a' (sixteen unsigned 8-bit integer numbers) element -/// are unsigned less than or equal to 'b' (sixteen unsigned 8-bit integer numbers) element. +/// if the corresponding `a` (sixteen unsigned 8-bit integer numbers) element +/// are unsigned less than or equal to `b` (sixteen unsigned 8-bit integer numbers) element. /// otherwise set all bits to 0. /// #[inline] @@ -2953,8 +2953,8 @@ pub unsafe fn __msa_cle_u_b(a: v16u8, b: v16u8) -> v16i8 { /// Vector Compare Unsigned Less Than or Equal /// /// Set all bits to 1 in vector (eight signed 16-bit integer numbers) elements -/// if the corresponding 'a' (eight unsigned 16-bit integer numbers) element -/// are unsigned less than or equal to 'b' (eight unsigned 16-bit integer numbers) element. +/// if the corresponding `a` (eight unsigned 16-bit integer numbers) element +/// are unsigned less than or equal to `b` (eight unsigned 16-bit integer numbers) element. /// otherwise set all bits to 0. /// #[inline] @@ -2967,8 +2967,8 @@ pub unsafe fn __msa_cle_u_h(a: v8u16, b: v8u16) -> v8i16 { /// Vector Compare Unsigned Less Than or Equal /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements -/// if the corresponding 'a' (four unsigned 32-bit integer numbers) element -/// are unsigned less than or equal to 'b' (four unsigned 32-bit integer numbers) element. +/// if the corresponding `a` (four unsigned 32-bit integer numbers) element +/// are unsigned less than or equal to `b` (four unsigned 32-bit integer numbers) element. /// otherwise set all bits to 0. /// #[inline] @@ -2981,8 +2981,8 @@ pub unsafe fn __msa_cle_u_w(a: v4u32, b: v4u32) -> v4i32 { /// Vector Compare Unsigned Less Than or Equal /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements -/// if the corresponding 'a' (two unsigned 64-bit integer numbers) element -/// are unsigned less than or equal to 'b' (two unsigned 64-bit integer numbers) element. +/// if the corresponding `a` (two unsigned 64-bit integer numbers) element +/// are unsigned less than or equal to `b` (two unsigned 64-bit integer numbers) element. /// otherwise set all bits to 0. /// #[inline] @@ -2995,7 +2995,7 @@ pub unsafe fn __msa_cle_u_d(a: v2u64, b: v2u64) -> v2i64 { /// Immediate Compare Signed Less Than or Equal /// /// Set all bits to 1 in vector (sixteen signed 8-bit integer numbers) elements -/// if the corresponding 'a' (sixteen signed 8-bit integer numbers) element +/// if the corresponding `a` (sixteen signed 8-bit integer numbers) element /// is less than or equal to the 5-bit signed immediate imm_s5, /// otherwise set all bits to 0. /// @@ -3015,7 +3015,7 @@ pub unsafe fn __msa_clei_s_b(a: v16i8, imm_s5: i32) -> v16i8 { /// Immediate Compare Signed Less Than or Equal /// /// Set all bits to 1 in vector (eight signed 16-bit integer numbers) elements -/// if the corresponding 'a' (eight signed 16-bit integer numbers) element +/// if the corresponding `a` (eight signed 16-bit integer numbers) element /// is less than or equal to the 5-bit signed immediate imm_s5, /// otherwise set all bits to 0. /// @@ -3035,7 +3035,7 @@ pub unsafe fn __msa_clei_s_h(a: v8i16, imm_s5: i32) -> v8i16 { /// Immediate Compare Signed Less Than or Equal /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements -/// if the corresponding 'a' (four signed 32-bit integer numbers) element +/// if the corresponding `a` (four signed 32-bit integer numbers) element /// is less than or equal to the 5-bit signed immediate imm_s5, /// otherwise set all bits to 0. /// @@ -3055,7 +3055,7 @@ pub unsafe fn __msa_clei_s_w(a: v4i32, imm_s5: i32) -> v4i32 { /// Immediate Compare Signed Less Than or Equal /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements -/// if the corresponding 'a' (two signed 64-bit integer numbers) element +/// if the corresponding `a` (two signed 64-bit integer numbers) element /// is less than or equal to the 5-bit signed immediate imm_s5, /// otherwise set all bits to 0. /// @@ -3075,7 +3075,7 @@ pub unsafe fn __msa_clei_s_d(a: v2i64, imm_s5: i32) -> v2i64 { /// Immediate Compare Unsigned Less Than or Equal /// /// Set all bits to 1 in vector (sixteen signed 8-bit integer numbers) elements -/// if the corresponding 'a' (sixteen unsigned 8-bit integer numbers) element +/// if the corresponding `a` (sixteen unsigned 8-bit integer numbers) element /// is unsigned less than or equal to the 5-bit unsigned immediate imm5, /// otherwise set all bits to 0. /// @@ -3095,7 +3095,7 @@ pub unsafe fn __msa_clei_u_b(a: v16u8, imm5: i32) -> v16i8 { /// Immediate Compare Unsigned Less Than or Equal /// /// Set all bits to 1 in vector (eight signed 16-bit integer numbers) elements -/// if the corresponding 'a' (eight unsigned 16-bit integer numbers) element +/// if the corresponding `a` (eight unsigned 16-bit integer numbers) element /// is unsigned less than or equal to the 5-bit unsigned immediate imm5, /// otherwise set all bits to 0. /// @@ -3115,7 +3115,7 @@ pub unsafe fn __msa_clei_u_h(a: v8u16, imm5: i32) -> v8i16 { /// Immediate Compare Unsigned Less Than or Equal /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements -/// if the corresponding 'a' (four unsigned 32-bit integer numbers) element +/// if the corresponding `a` (four unsigned 32-bit integer numbers) element /// is unsigned less than or equal to the 5-bit unsigned immediate imm5, /// otherwise set all bits to 0. /// @@ -3135,7 +3135,7 @@ pub unsafe fn __msa_clei_u_w(a: v4u32, imm5: i32) -> v4i32 { /// Immediate Compare Unsigned Less Than or Equal /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements -/// if the corresponding 'a' (two unsigned 64-bit integer numbers) element +/// if the corresponding `a` (two unsigned 64-bit integer numbers) element /// is unsigned less than or equal to the 5-bit unsigned immediate imm5, /// otherwise set all bits to 0. /// @@ -3155,8 +3155,8 @@ pub unsafe fn __msa_clei_u_d(a: v2u64, imm5: i32) -> v2i64 { /// Vector Compare Signed Less Than /// /// Set all bits to 1 in vector (sixteen signed 8-bit integer numbers) elements -/// if the corresponding 'a' (sixteen signed 8-bit integer numbers) element -/// are signed less than 'b' (sixteen signed 8-bit integer numbers) element. +/// if the corresponding `a` (sixteen signed 8-bit integer numbers) element +/// are signed less than `b` (sixteen signed 8-bit integer numbers) element. /// otherwise set all bits to 0. /// #[inline] @@ -3169,8 +3169,8 @@ pub unsafe fn __msa_clt_s_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Compare Signed Less Than /// /// Set all bits to 1 in vector (eight signed 16-bit integer numbers) elements -/// if the corresponding 'a' (eight signed 16-bit integer numbers) element -/// are signed less than 'b' (eight signed 16-bit integer numbers) element. +/// if the corresponding `a` (eight signed 16-bit integer numbers) element +/// are signed less than `b` (eight signed 16-bit integer numbers) element. /// otherwise set all bits to 0. /// #[inline] @@ -3183,8 +3183,8 @@ pub unsafe fn __msa_clt_s_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Compare Signed Less Than /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements -/// if the corresponding 'a' (four signed 32-bit integer numbers) element -/// are signed less than 'b' (four signed 32-bit integer numbers) element. +/// if the corresponding `a` (four signed 32-bit integer numbers) element +/// are signed less than `b` (four signed 32-bit integer numbers) element. /// otherwise set all bits to 0. /// #[inline] @@ -3197,8 +3197,8 @@ pub unsafe fn __msa_clt_s_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Compare Signed Less Than /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements -/// if the corresponding 'a' (two signed 64-bit integer numbers) element -/// are signed less than 'b' (two signed 64-bit integer numbers) element. +/// if the corresponding `a` (two signed 64-bit integer numbers) element +/// are signed less than `b` (two signed 64-bit integer numbers) element. /// otherwise set all bits to 0. /// #[inline] @@ -3211,8 +3211,8 @@ pub unsafe fn __msa_clt_s_d(a: v2i64, b: v2i64) -> v2i64 { /// Vector Compare Unsigned Less Than /// /// Set all bits to 1 in vector (sixteen signed 8-bit integer numbers) elements -/// if the corresponding 'a' (sixteen unsigned 8-bit integer numbers) element -/// are unsigned less than 'b' (sixteen unsigned 8-bit integer numbers) element. +/// if the corresponding `a` (sixteen unsigned 8-bit integer numbers) element +/// are unsigned less than `b` (sixteen unsigned 8-bit integer numbers) element. /// otherwise set all bits to 0. /// #[inline] @@ -3225,8 +3225,8 @@ pub unsafe fn __msa_clt_u_b(a: v16u8, b: v16u8) -> v16i8 { /// Vector Compare Unsigned Less Than /// /// Set all bits to 1 in vector (eight signed 16-bit integer numbers) elements -/// if the corresponding 'a' (eight unsigned 16-bit integer numbers) element -/// are unsigned less than 'b' (eight unsigned 16-bit integer numbers) element. +/// if the corresponding `a` (eight unsigned 16-bit integer numbers) element +/// are unsigned less than `b` (eight unsigned 16-bit integer numbers) element. /// otherwise set all bits to 0. /// #[inline] @@ -3239,8 +3239,8 @@ pub unsafe fn __msa_clt_u_h(a: v8u16, b: v8u16) -> v8i16 { /// Vector Compare Unsigned Less Than /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements -/// if the corresponding 'a' (four unsigned 32-bit integer numbers) element -/// are unsigned less than 'b' (four unsigned 32-bit integer numbers) element. +/// if the corresponding `a` (four unsigned 32-bit integer numbers) element +/// are unsigned less than `b` (four unsigned 32-bit integer numbers) element. /// otherwise set all bits to 0. /// #[inline] @@ -3253,8 +3253,8 @@ pub unsafe fn __msa_clt_u_w(a: v4u32, b: v4u32) -> v4i32 { /// Vector Compare Unsigned Less Than /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements -/// if the corresponding 'a' (two unsigned 64-bit integer numbers) element -/// are unsigned less than 'b' (two unsigned 64-bit integer numbers) element. +/// if the corresponding `a` (two unsigned 64-bit integer numbers) element +/// are unsigned less than `b` (two unsigned 64-bit integer numbers) element. /// otherwise set all bits to 0. /// #[inline] @@ -3267,7 +3267,7 @@ pub unsafe fn __msa_clt_u_d(a: v2u64, b: v2u64) -> v2i64 { /// Immediate Compare Signed Less Than /// /// Set all bits to 1 in vector (sixteen signed 8-bit integer numbers) elements -/// if the corresponding 'a' (sixteen signed 8-bit integer numbers) element +/// if the corresponding `a` (sixteen signed 8-bit integer numbers) element /// is less than the 5-bit signed immediate imm_s5, /// otherwise set all bits to 0. /// @@ -3287,7 +3287,7 @@ pub unsafe fn __msa_clti_s_b(a: v16i8, imm_s5: i32) -> v16i8 { /// Immediate Compare Signed Less Than /// /// Set all bits to 1 in vector (eight signed 16-bit integer numbers) elements -/// if the corresponding 'a' (eight signed 16-bit integer numbers) element +/// if the corresponding `a` (eight signed 16-bit integer numbers) element /// is less than the 5-bit signed immediate imm_s5, /// otherwise set all bits to 0. /// @@ -3307,7 +3307,7 @@ pub unsafe fn __msa_clti_s_h(a: v8i16, imm_s5: i32) -> v8i16 { /// Immediate Compare Signed Less Than /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements -/// if the corresponding 'a' (four signed 32-bit integer numbers) element +/// if the corresponding `a` (four signed 32-bit integer numbers) element /// is less than the 5-bit signed immediate imm_s5, /// otherwise set all bits to 0. /// @@ -3327,7 +3327,7 @@ pub unsafe fn __msa_clti_s_w(a: v4i32, imm_s5: i32) -> v4i32 { /// Immediate Compare Signed Less Than /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements -/// if the corresponding 'a' (two signed 64-bit integer numbers) element +/// if the corresponding `a` (two signed 64-bit integer numbers) element /// is less than the 5-bit signed immediate imm_s5, /// otherwise set all bits to 0. /// @@ -3347,7 +3347,7 @@ pub unsafe fn __msa_clti_s_d(a: v2i64, imm_s5: i32) -> v2i64 { /// Immediate Compare Unsigned Less Than /// /// Set all bits to 1 in vector (sixteen signed 8-bit integer numbers) elements -/// if the corresponding 'a' (sixteen unsigned 8-bit integer numbers) element +/// if the corresponding `a` (sixteen unsigned 8-bit integer numbers) element /// is unsigned less than the 5-bit unsigned immediate imm5, /// otherwise set all bits to 0. /// @@ -3367,7 +3367,7 @@ pub unsafe fn __msa_clti_u_b(a: v16u8, imm5: i32) -> v16i8 { /// Immediate Compare Unsigned Less Than /// /// Set all bits to 1 in vector (eight signed 16-bit integer numbers) elements -/// if the corresponding 'a' (eight unsigned 16-bit integer numbers) element +/// if the corresponding `a` (eight unsigned 16-bit integer numbers) element /// is unsigned less than the 5-bit unsigned immediate imm5, /// otherwise set all bits to 0. /// @@ -3387,7 +3387,7 @@ pub unsafe fn __msa_clti_u_h(a: v8u16, imm5: i32) -> v8i16 { /// Immediate Compare Unsigned Less Than /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements -/// if the corresponding 'a' (four unsigned 32-bit integer numbers) element +/// if the corresponding `a` (four unsigned 32-bit integer numbers) element /// is unsigned less than the 5-bit unsigned immediate imm5, /// otherwise set all bits to 0. /// @@ -3407,7 +3407,7 @@ pub unsafe fn __msa_clti_u_w(a: v4u32, imm5: i32) -> v4i32 { /// Immediate Compare Unsigned Less Than /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements -/// if the corresponding 'a' (two unsigned 64-bit integer numbers) element +/// if the corresponding `a` (two unsigned 64-bit integer numbers) element /// is unsigned less than the 5-bit unsigned immediate imm5, /// otherwise set all bits to 0. /// @@ -3426,7 +3426,7 @@ pub unsafe fn __msa_clti_u_d(a: v2u64, imm5: i32) -> v2i64 { /// Element Copy to GPR Signed /// -/// Sign-extend element imm4 of vector 'a' (sixteen signed 8-bit integer numbers) +/// Sign-extend element imm4 of vector `a` (sixteen signed 8-bit integer numbers) /// and copy the result to GPR rd /// #[inline] @@ -3444,7 +3444,7 @@ pub unsafe fn __msa_copy_s_b(a: v16i8, imm4: i32) -> i32 { /// Element Copy to GPR Signed /// -/// Sign-extend element imm3 of vector 'a' (eight signed 16-bit integer numbers) +/// Sign-extend element imm3 of vector `a` (eight signed 16-bit integer numbers) /// and copy the result to GPR rd /// #[inline] @@ -3462,7 +3462,7 @@ pub unsafe fn __msa_copy_s_h(a: v8i16, imm3: i32) -> i32 { /// Element Copy to GPR Signed /// -/// Sign-extend element imm2 of vector 'a' (four signed 32-bit integer numbers) +/// Sign-extend element imm2 of vector `a` (four signed 32-bit integer numbers) /// and copy the result to GPR rd /// #[inline] @@ -3480,7 +3480,7 @@ pub unsafe fn __msa_copy_s_w(a: v4i32, imm2: i32) -> i32 { /// Element Copy to GPR Signed /// -/// Sign-extend element imm1 of vector 'a' (two signed 64-bit integer numbers) +/// Sign-extend element imm1 of vector `a` (two signed 64-bit integer numbers) /// and copy the result to GPR rd /// #[inline] @@ -3498,7 +3498,7 @@ pub unsafe fn __msa_copy_s_d(a: v2i64, imm1: i32) -> i64 { /// Element Copy to GPR Unsigned /// -/// Zero-extend element imm4 of vector 'a' (sixteen signed 8-bit integer numbers) +/// Zero-extend element imm4 of vector `a` (sixteen signed 8-bit integer numbers) /// and copy the result to GPR rd /// #[inline] @@ -3516,7 +3516,7 @@ pub unsafe fn __msa_copy_u_b(a: v16i8, imm4: i32) -> u32 { /// Element Copy to GPR Unsigned /// -/// Zero-extend element imm3 of vector 'a' (eight signed 16-bit integer numbers) +/// Zero-extend element imm3 of vector `a` (eight signed 16-bit integer numbers) /// and copy the result to GPR rd /// #[inline] @@ -3534,7 +3534,7 @@ pub unsafe fn __msa_copy_u_h(a: v8i16, imm3: i32) -> u32 { /// Element Copy to GPR Unsigned /// -/// Zero-extend element imm2 of vector 'a' (four signed 32-bit integer numbers) +/// Zero-extend element imm2 of vector `a` (four signed 32-bit integer numbers) /// and copy the result to GPR rd /// #[inline] @@ -3552,7 +3552,7 @@ pub unsafe fn __msa_copy_u_w(a: v4i32, imm2: i32) -> u32 { /// Element Copy to GPR Unsigned /// -/// Zero-extend element imm1 of vector 'a' (two signed 64-bit integer numbers) +/// Zero-extend element imm1 of vector `a` (two signed 64-bit integer numbers) /// and copy the result to GPR rd /// #[inline] @@ -3587,8 +3587,8 @@ pub unsafe fn __msa_ctcmsa(imm5: i32, a: i32) -> () { /// Vector Signed Divide /// -/// The signed integer elements in vector 'a' (sixteen signed 8-bit integer numbers) -/// are divided by signed integer elements in vector 'b' (sixteen signed 8-bit integer numbers). +/// The signed integer elements in vector `a` (sixteen signed 8-bit integer numbers) +/// are divided by signed integer elements in vector `b` (sixteen signed 8-bit integer numbers). /// The result is written to vector (sixteen signed 8-bit integer numbers). /// #[inline] @@ -3600,8 +3600,8 @@ pub unsafe fn __msa_div_s_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Signed Divide /// -/// The signed integer elements in vector 'a' (eight signed 16-bit integer numbers) -/// are divided by signed integer elements in vector 'b' (eight signed 16-bit integer numbers). +/// The signed integer elements in vector `a` (eight signed 16-bit integer numbers) +/// are divided by signed integer elements in vector `b` (eight signed 16-bit integer numbers). /// The result is written to vector (eight signed 16-bit integer numbers). /// #[inline] @@ -3613,8 +3613,8 @@ pub unsafe fn __msa_div_s_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Signed Divide /// -/// The signed integer elements in vector 'a' (four signed 32-bit integer numbers) -/// are divided by signed integer elements in vector 'b' (four signed 32-bit integer numbers). +/// The signed integer elements in vector `a` (four signed 32-bit integer numbers) +/// are divided by signed integer elements in vector `b` (four signed 32-bit integer numbers). /// The result is written to vector (four signed 32-bit integer numbers). /// #[inline] @@ -3626,8 +3626,8 @@ pub unsafe fn __msa_div_s_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Signed Divide /// -/// The signed integer elements in vector 'a' (two signed 64-bit integer numbers) -/// are divided by signed integer elements in vector 'b' (two signed 64-bit integer numbers). +/// The signed integer elements in vector `a` (two signed 64-bit integer numbers) +/// are divided by signed integer elements in vector `b` (two signed 64-bit integer numbers). /// The result is written to vector (two signed 64-bit integer numbers). /// #[inline] @@ -3639,8 +3639,8 @@ pub unsafe fn __msa_div_s_d(a: v2i64, b: v2i64) -> v2i64 { /// Vector Unsigned Divide /// -/// The unsigned integer elements in vector 'a' (sixteen unsigned 8-bit integer numbers) -/// are divided by unsigned integer elements in vector 'b' (sixteen unsigned 8-bit integer numbers). +/// The unsigned integer elements in vector `a` (sixteen unsigned 8-bit integer numbers) +/// are divided by unsigned integer elements in vector `b` (sixteen unsigned 8-bit integer numbers). /// The result is written to vector (sixteen unsigned 8-bit integer numbers). /// #[inline] @@ -3652,8 +3652,8 @@ pub unsafe fn __msa_div_u_b(a: v16u8, b: v16u8) -> v16u8 { /// Vector Unsigned Divide /// -/// The unsigned integer elements in vector 'a' (eight unsigned 16-bit integer numbers) -/// are divided by unsigned integer elements in vector 'b' (eight unsigned 16-bit integer numbers). +/// The unsigned integer elements in vector `a` (eight unsigned 16-bit integer numbers) +/// are divided by unsigned integer elements in vector `b` (eight unsigned 16-bit integer numbers). /// The result is written to vector (eight unsigned 16-bit integer numbers). /// #[inline] @@ -3665,8 +3665,8 @@ pub unsafe fn __msa_div_u_h(a: v8u16, b: v8u16) -> v8u16 { /// Vector Unsigned Divide /// -/// The unsigned integer elements in vector 'a' (four unsigned 32-bit integer numbers) -/// are divided by unsigned integer elements in vector 'b' (four unsigned 32-bit integer numbers). +/// The unsigned integer elements in vector `a` (four unsigned 32-bit integer numbers) +/// are divided by unsigned integer elements in vector `b` (four unsigned 32-bit integer numbers). /// The result is written to vector (four unsigned 32-bit integer numbers). /// #[inline] @@ -3678,8 +3678,8 @@ pub unsafe fn __msa_div_u_w(a: v4u32, b: v4u32) -> v4u32 { /// Vector Unsigned Divide /// -/// The unsigned integer elements in vector 'a' (two unsigned 64-bit integer numbers) -/// are divided by unsigned integer elements in vector 'b' (two unsigned 64-bit integer numbers). +/// The unsigned integer elements in vector `a` (two unsigned 64-bit integer numbers) +/// are divided by unsigned integer elements in vector `b` (two unsigned 64-bit integer numbers). /// The result is written to vector (two unsigned 64-bit integer numbers). /// #[inline] @@ -3691,8 +3691,8 @@ pub unsafe fn __msa_div_u_d(a: v2u64, b: v2u64) -> v2u64 { /// Vector Signed Dot Product /// -/// The signed integer elements in vector 'a' (sixteen signed 8-bit integer numbers) -/// are multiplied by signed integer elements in vector 'b' (sixteen signed 8-bit integer numbers). +/// The signed integer elements in vector `a` (sixteen signed 8-bit integer numbers) +/// are multiplied by signed integer elements in vector `b` (sixteen signed 8-bit integer numbers). /// producing a result the size of the input operands. The multiplication resultsof /// adjacent odd/even elements are added and stored to the destination /// vector (eight signed 16-bit integer numbers). @@ -3706,8 +3706,8 @@ pub unsafe fn __msa_dotp_s_h(a: v16i8, b: v16i8) -> v8i16 { /// Vector Signed Dot Product /// -/// The signed integer elements in vector 'a' (eight signed 16-bit integer numbers) -/// are multiplied by signed integer elements in vector 'b' (eight signed 16-bit integer numbers). +/// The signed integer elements in vector `a` (eight signed 16-bit integer numbers) +/// are multiplied by signed integer elements in vector `b` (eight signed 16-bit integer numbers). /// producing a result the size of the input operands. The multiplication resultsof /// adjacent odd/even elements are added and stored to the destination /// vector (four signed 32-bit integer numbers). @@ -3721,8 +3721,8 @@ pub unsafe fn __msa_dotp_s_w(a: v8i16, b: v8i16) -> v4i32 { /// Vector Signed Dot Product /// -/// The signed integer elements in vector 'a' (four signed 32-bit integer numbers) -/// are multiplied by signed integer elements in vector 'b' (four signed 32-bit integer numbers). +/// The signed integer elements in vector `a` (four signed 32-bit integer numbers) +/// are multiplied by signed integer elements in vector `b` (four signed 32-bit integer numbers). /// producing a result the size of the input operands. The multiplication resultsof /// adjacent odd/even elements are added and stored to the destination /// vector (two signed 64-bit integer numbers). @@ -3736,8 +3736,8 @@ pub unsafe fn __msa_dotp_s_d(a: v4i32, b: v4i32) -> v2i64 { /// Vector Unsigned Dot Product /// -/// The unsigned integer elements in vector 'a' (sixteen unsigned 8-bit integer numbers) -/// are multiplied by unsigned integer elements in vector 'b' (sixteen unsigned 8-bit integer numbers). +/// The unsigned integer elements in vector `a` (sixteen unsigned 8-bit integer numbers) +/// are multiplied by unsigned integer elements in vector `b` (sixteen unsigned 8-bit integer numbers). /// producing a result the size of the input operands. The multiplication resultsof /// adjacent odd/even elements are added and stored to the destination /// vector (eight unsigned 16-bit integer numbers). @@ -3751,8 +3751,8 @@ pub unsafe fn __msa_dotp_u_h(a: v16u8, b: v16u8) -> v8u16 { /// Vector Unsigned Dot Product /// -/// The unsigned integer elements in vector 'a' (eight unsigned 16-bit integer numbers) -/// are multiplied by unsigned integer elements in vector 'b' (eight unsigned 16-bit integer numbers). +/// The unsigned integer elements in vector `a` (eight unsigned 16-bit integer numbers) +/// are multiplied by unsigned integer elements in vector `b` (eight unsigned 16-bit integer numbers). /// producing a result the size of the input operands. The multiplication resultsof /// adjacent odd/even elements are added and stored to the destination /// vector (four unsigned 32-bit integer numbers). @@ -3766,8 +3766,8 @@ pub unsafe fn __msa_dotp_u_w(a: v8u16, b: v8u16) -> v4u32 { /// Vector Unsigned Dot Product /// -/// The unsigned integer elements in vector 'a' (four unsigned 32-bit integer numbers) -/// are multiplied by unsigned integer elements in vector 'b' (four unsigned 32-bit integer numbers). +/// The unsigned integer elements in vector `a` (four unsigned 32-bit integer numbers) +/// are multiplied by unsigned integer elements in vector `b` (four unsigned 32-bit integer numbers). /// producing a result the size of the input operands. The multiplication resultsof /// adjacent odd/even elements are added and stored to the destination /// vector (two unsigned 64-bit integer numbers). @@ -3781,10 +3781,10 @@ pub unsafe fn __msa_dotp_u_d(a: v4u32, b: v4u32) -> v2u64 { /// Vector Signed Dot Product and Add /// -/// The signed integer elements in vector 'b' (sixteen signed 8-bit integer numbers) -/// are multiplied by signed integer elements in vector 'c' (sixteen signed 8-bit integer numbers). +/// The signed integer elements in vector `b` (sixteen signed 8-bit integer numbers) +/// are multiplied by signed integer elements in vector `c` (sixteen signed 8-bit integer numbers). /// producing a result twice the size of the input operands. The multiplication results -/// of adjacent odd/even elements are added to the vector 'a' (eight signed 16-bit integer numbers). +/// of adjacent odd/even elements are added to the vector `a` (eight signed 16-bit integer numbers). /// #[inline] #[target_feature(enable = "msa")] @@ -3795,10 +3795,10 @@ pub unsafe fn __msa_dpadd_s_h(a: v8i16, b: v16i8, c: v16i8) -> v8i16 { /// Vector Signed Dot Product and Add /// -/// The signed integer elements in vector 'b' (eight signed 16-bit integer numbers) -/// are multiplied by signed integer elements in vector 'c' (eight signed 16-bit integer numbers). +/// The signed integer elements in vector `b` (eight signed 16-bit integer numbers) +/// are multiplied by signed integer elements in vector `c` (eight signed 16-bit integer numbers). /// producing a result twice the size of the input operands. The multiplication results -/// of adjacent odd/even elements are added to the vector 'a' (four signed 32-bit integer numbers). +/// of adjacent odd/even elements are added to the vector `a` (four signed 32-bit integer numbers). /// #[inline] #[target_feature(enable = "msa")] @@ -3809,10 +3809,10 @@ pub unsafe fn __msa_dpadd_s_w(a: v4i32, b: v8i16, c: v8i16) -> v4i32 { /// Vector Signed Dot Product and Add /// -/// The signed integer elements in vector 'b' (four signed 32-bit integer numbers) -/// are multiplied by signed integer elements in vector 'c' (four signed 32-bit integer numbers). +/// The signed integer elements in vector `b` (four signed 32-bit integer numbers) +/// are multiplied by signed integer elements in vector `c` (four signed 32-bit integer numbers). /// producing a result twice the size of the input operands. The multiplication results -/// of adjacent odd/even elements are added to the vector 'a' (two signed 64-bit integer numbers). +/// of adjacent odd/even elements are added to the vector `a` (two signed 64-bit integer numbers). /// #[inline] #[target_feature(enable = "msa")] @@ -3823,10 +3823,10 @@ pub unsafe fn __msa_dpadd_s_d(a: v2i64, b: v4i32, c: v4i32) -> v2i64 { /// Vector Unsigned Dot Product and Add /// -/// The unsigned integer elements in vector 'b' (sixteen unsigned 8-bit integer numbers) -/// are multiplied by unsigned integer elements in vector 'c' (sixteen unsigned 8-bit integer numbers). +/// The unsigned integer elements in vector `b` (sixteen unsigned 8-bit integer numbers) +/// are multiplied by unsigned integer elements in vector `c` (sixteen unsigned 8-bit integer numbers). /// producing a result twice the size of the input operands. The multiplication results -/// of adjacent odd/even elements are added to the vector 'a' (eight unsigned 16-bit integer numbers). +/// of adjacent odd/even elements are added to the vector `a` (eight unsigned 16-bit integer numbers). /// #[inline] #[target_feature(enable = "msa")] @@ -3837,10 +3837,10 @@ pub unsafe fn __msa_dpadd_u_h(a: v8u16, b: v16u8, c: v16u8) -> v8u16 { /// Vector Unsigned Dot Product and Add /// -/// The unsigned integer elements in vector 'b' (eight unsigned 16-bit integer numbers) -/// are multiplied by unsigned integer elements in vector 'c' (eight unsigned 16-bit integer numbers). +/// The unsigned integer elements in vector `b` (eight unsigned 16-bit integer numbers) +/// are multiplied by unsigned integer elements in vector `c` (eight unsigned 16-bit integer numbers). /// producing a result twice the size of the input operands. The multiplication results -/// of adjacent odd/even elements are added to the vector 'a' (four unsigned 32-bit integer numbers). +/// of adjacent odd/even elements are added to the vector `a` (four unsigned 32-bit integer numbers). /// #[inline] #[target_feature(enable = "msa")] @@ -3851,10 +3851,10 @@ pub unsafe fn __msa_dpadd_u_w(a: v4u32, b: v8u16, c: v8u16) -> v4u32 { /// Vector Unsigned Dot Product and Add /// -/// The unsigned integer elements in vector 'b' (four unsigned 32-bit integer numbers) -/// are multiplied by unsigned integer elements in vector 'c' (four unsigned 32-bit integer numbers). +/// The unsigned integer elements in vector `b` (four unsigned 32-bit integer numbers) +/// are multiplied by unsigned integer elements in vector `c` (four unsigned 32-bit integer numbers). /// producing a result twice the size of the input operands. The multiplication results -/// of adjacent odd/even elements are added to the vector 'a' (two unsigned 64-bit integer numbers). +/// of adjacent odd/even elements are added to the vector `a` (two unsigned 64-bit integer numbers). /// #[inline] #[target_feature(enable = "msa")] @@ -3865,10 +3865,10 @@ pub unsafe fn __msa_dpadd_u_d(a: v2u64, b: v4u32, c: v4u32) -> v2u64 { /// Vector Signed Dot Product and Add /// -/// The signed integer elements in vector 'b' (sixteen signed 8-bit integer numbers) -/// are multiplied by signed integer elements in vector 'c' (sixteen signed 8-bit integer numbers). +/// The signed integer elements in vector `b` (sixteen signed 8-bit integer numbers) +/// are multiplied by signed integer elements in vector `c` (sixteen signed 8-bit integer numbers). /// producing a result twice the size of the input operands. The multiplication results -/// of adjacent odd/even elements are sub-tracted from the integer elements in vector 'a' +/// of adjacent odd/even elements are subtracted from the integer elements in vector `a` /// (eight signed 16-bit integer numbers). /// #[inline] @@ -3880,10 +3880,10 @@ pub unsafe fn __msa_dpsub_s_h(a: v8i16, b: v16i8, c: v16i8) -> v8i16 { /// Vector Signed Dot Product and Add /// -/// The signed integer elements in vector 'b' (eight signed 16-bit integer numbers) -/// are multiplied by signed integer elements in vector 'c' (eight signed 16-bit integer numbers). +/// The signed integer elements in vector `b` (eight signed 16-bit integer numbers) +/// are multiplied by signed integer elements in vector `c` (eight signed 16-bit integer numbers). /// producing a result twice the size of the input operands. The multiplication results -/// of adjacent odd/even elements are sub-tracted from the integer elements in vector 'a' +/// of adjacent odd/even elements are subtracted from the integer elements in vector `a` /// (four signed 32-bit integer numbers). /// #[inline] @@ -3895,10 +3895,10 @@ pub unsafe fn __msa_dpsub_s_w(a: v4i32, b: v8i16, c: v8i16) -> v4i32 { /// Vector Signed Dot Product and Add /// -/// The signed integer elements in vector 'b' (four signed 32-bit integer numbers) -/// are multiplied by signed integer elements in vector 'c' (four signed 32-bit integer numbers). +/// The signed integer elements in vector `b` (four signed 32-bit integer numbers) +/// are multiplied by signed integer elements in vector `c` (four signed 32-bit integer numbers). /// producing a result twice the size of the input operands. The multiplication results -/// of adjacent odd/even elements are sub-tracted from the integer elements in vector 'a' +/// of adjacent odd/even elements are subtracted from the integer elements in vector `a` /// (two signed 64-bit integer numbers). /// #[inline] @@ -3910,10 +3910,10 @@ pub unsafe fn __msa_dpsub_s_d(a: v2i64, b: v4i32, c: v4i32) -> v2i64 { /// Vector Unsigned Dot Product and Add /// -/// The unsigned integer elements in vector 'b' (sixteen unsigned 8-bit integer numbers) -/// are multiplied by unsigned integer elements in vector 'c' (sixteen unsigned 8-bit integer numbers). +/// The unsigned integer elements in vector `b` (sixteen unsigned 8-bit integer numbers) +/// are multiplied by unsigned integer elements in vector `c` (sixteen unsigned 8-bit integer numbers). /// producing a result twice the size of the input operands. The multiplication results -/// of adjacent odd/even elements are sub-tracted from the integer elements in vector 'a' +/// of adjacent odd/even elements are subtracted from the integer elements in vector `a` /// (eight signed 16-bit integer numbers). /// #[inline] @@ -3925,10 +3925,10 @@ pub unsafe fn __msa_dpsub_u_h(a: v8i16, b: v16u8, c: v16u8) -> v8i16 { /// Vector Unsigned Dot Product and Add /// -/// The unsigned integer elements in vector 'b' (eight unsigned 16-bit integer numbers) -/// are multiplied by unsigned integer elements in vector 'c' (eight unsigned 16-bit integer numbers). +/// The unsigned integer elements in vector `b` (eight unsigned 16-bit integer numbers) +/// are multiplied by unsigned integer elements in vector `c` (eight unsigned 16-bit integer numbers). /// producing a result twice the size of the input operands. The multiplication results -/// of adjacent odd/even elements are sub-tracted from the integer elements in vector 'a' +/// of adjacent odd/even elements are subtracted from the integer elements in vector `a` /// (four signed 32-bit integer numbers). /// #[inline] @@ -3940,10 +3940,10 @@ pub unsafe fn __msa_dpsub_u_w(a: v4i32, b: v8u16, c: v8u16) -> v4i32 { /// Vector Unsigned Dot Product and Add /// -/// The unsigned integer elements in vector 'b' (four unsigned 32-bit integer numbers) -/// are multiplied by unsigned integer elements in vector 'c' (four unsigned 32-bit integer numbers). +/// The unsigned integer elements in vector `b` (four unsigned 32-bit integer numbers) +/// are multiplied by unsigned integer elements in vector `c` (four unsigned 32-bit integer numbers). /// producing a result twice the size of the input operands. The multiplication results -/// of adjacent odd/even elements are sub-tracted from the integer elements in vector 'a' +/// of adjacent odd/even elements are subtracted from the integer elements in vector `a` /// (two signed 64-bit integer numbers). /// #[inline] @@ -3955,8 +3955,8 @@ pub unsafe fn __msa_dpsub_u_d(a: v2i64, b: v4u32, c: v4u32) -> v2i64 { /// Vector Floating-Point Addition /// -/// The floating-point elements in vector 'a' (four 32-bit floating point numbers) -/// are added to the floating-point elements in 'bc' (four 32-bit floating point numbers). +/// The floating-point elements in vector `a` (four 32-bit floating point numbers) +/// are added to the floating-point elements in `bc` (four 32-bit floating point numbers). /// The result is written to vector (four 32-bit floating point numbers) /// #[inline] @@ -3968,8 +3968,8 @@ pub unsafe fn __msa_fadd_w(a: v4f32, b: v4f32) -> v4f32 { /// Vector Floating-Point Addition /// -/// The floating-point elements in vector 'a' (two 64-bit floating point numbers) -/// are added to the floating-point elements in 'bc' (two 64-bit floating point numbers). +/// The floating-point elements in vector `a` (two 64-bit floating point numbers) +/// are added to the floating-point elements in `bc` (two 64-bit floating point numbers). /// The result is written to vector (two 64-bit floating point numbers) /// #[inline] @@ -3982,8 +3982,8 @@ pub unsafe fn __msa_fadd_d(a: v2f64, b: v2f64) -> v2f64 { /// Vector Floating-Point Quiet Compare Always False /// /// Set all bits to 0 in vector (four signed 32-bit integer numbers) -/// Signaling NaN elements in 'a' (four 32-bit floating point numbers) -/// or 'b' (four 32-bit floating point numbers)signal Invalid Operation exception. +/// Signaling NaN elements in `a` (four 32-bit floating point numbers) +/// or `b` (four 32-bit floating point numbers)signal Invalid Operation exception. /// #[inline] #[target_feature(enable = "msa")] @@ -3995,8 +3995,8 @@ pub unsafe fn __msa_fcaf_w(a: v4f32, b: v4f32) -> v4i32 { /// Vector Floating-Point Quiet Compare Always False /// /// Set all bits to 0 in vector (two signed 64-bit integer numbers) -/// Signaling NaN elements in 'a' (two 64-bit floating point numbers) -/// or 'b' (two 64-bit floating point numbers) signal Invalid Operation exception. +/// Signaling NaN elements in `a` (two 64-bit floating point numbers) +/// or `b` (two 64-bit floating point numbers) signal Invalid Operation exception. /// #[inline] #[target_feature(enable = "msa")] @@ -4008,8 +4008,8 @@ pub unsafe fn __msa_fcaf_d(a: v2f64, b: v2f64) -> v2i64 { /// Vector Floating-Point Quiet Compare Equal /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) -/// elements if the corresponding in 'a' (four 32-bit floating point numbers) -/// and 'b' (four 32-bit floating point numbers)elements are ordered and equal, +/// elements if the corresponding in `a` (four 32-bit floating point numbers) +/// and `b` (four 32-bit floating point numbers)elements are ordered and equal, /// otherwise set all bits to 0. /// #[inline] @@ -4022,8 +4022,8 @@ pub unsafe fn __msa_fceq_w(a: v4f32, b: v4f32) -> v4i32 { /// Vector Floating-Point Quiet Compare Equal /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) -/// elements if the corresponding in 'a' (two 64-bit floating point numbers) -/// and 'b' (two 64-bit floating point numbers) elementsare ordered and equal, +/// elements if the corresponding in `a` (two 64-bit floating point numbers) +/// and `b` (two 64-bit floating point numbers) elementsare ordered and equal, /// otherwise set all bits to 0. /// #[inline] @@ -4037,7 +4037,7 @@ pub unsafe fn __msa_fceq_d(a: v2f64, b: v2f64) -> v2i64 { /// /// Store in each element of vector (four signed 32-bit integer numbers) /// a bit mask reflecting the floating-point class of the corresponding element of vector -/// 'a' (four 32-bit floating point numbers). +/// `a` (four 32-bit floating point numbers). /// The mask has 10 bits as follows. Bits 0 and 1 indicate NaN values: signaling NaN (bit 0) and quiet NaN (bit 1). /// Bits 2, 3, 4, 5 classify negative values: infinity (bit 2), normal (bit 3), subnormal (bit 4), and zero (bit 5). /// Bits 6, 7, 8, 9classify positive values:infinity (bit 6), normal (bit 7), subnormal (bit 8), and zero (bit 9). @@ -4053,7 +4053,7 @@ pub unsafe fn __msa_fclass_w(a: v4f32) -> v4i32 { /// /// Store in each element of vector (wto signed 64-bit integer numbers) /// a bit mask reflecting the floating-point class of the corresponding element of vector -/// 'a' (wto 64-bit floating point numbers). +/// `a` (wto 64-bit floating point numbers). /// The mask has 10 bits as follows. Bits 0 and 1 indicate NaN values: signaling NaN (bit 0) and quiet NaN (bit 1). /// Bits 2, 3, 4, 5 classify negative values: infinity (bit 2), normal (bit 3), subnormal (bit 4), and zero (bit 5). /// Bits 6, 7, 8, 9classify positive values:infinity (bit 6), normal (bit 7), subnormal (bit 8), and zero (bit 9). @@ -4068,8 +4068,8 @@ pub unsafe fn __msa_fclass_d(a: v2f64) -> v2i64 { /// Vector Floating-Point Quiet Compare Less or Equal /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) -/// elements if the corresponding 'a' (four 32-bit floating point numbers)elements are ordered -/// and either less than or equal to 'b' (four 32-bit floating point numbers)elements +/// elements if the corresponding `a` (four 32-bit floating point numbers)elements are ordered +/// and either less than or equal to `b` (four 32-bit floating point numbers)elements /// otherwise set all bits to 0. /// #[inline] @@ -4082,8 +4082,8 @@ pub unsafe fn __msa_fcle_w(a: v4f32, b: v4f32) -> v4i32 { /// Vector Floating-Point Quiet Compare Less or Equal /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) -/// elements if the corresponding 'a' (two 64-bit floating point numbers) elementsare ordered -/// and either less than or equal to 'b' (two 64-bit floating point numbers) elements +/// elements if the corresponding `a` (two 64-bit floating point numbers) elementsare ordered +/// and either less than or equal to `b` (two 64-bit floating point numbers) elements /// otherwise set all bits to 0. /// #[inline] @@ -4096,8 +4096,8 @@ pub unsafe fn __msa_fcle_d(a: v2f64, b: v2f64) -> v2i64 { /// Vector Floating-Point Quiet Compare Less Than /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) -/// elements if the corresponding 'a' (four 32-bit floating point numbers)elements are ordered -/// and less than 'b' (four 32-bit floating point numbers)elements +/// elements if the corresponding `a` (four 32-bit floating point numbers)elements are ordered +/// and less than `b` (four 32-bit floating point numbers)elements /// otherwise set all bits to 0. /// #[inline] @@ -4110,8 +4110,8 @@ pub unsafe fn __msa_fclt_w(a: v4f32, b: v4f32) -> v4i32 { /// Vector Floating-Point Quiet Compare Less Than /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) -/// elements if the corresponding 'a' (two 64-bit floating point numbers) elementsare ordered -/// and less than 'b' (two 64-bit floating point numbers) elements +/// elements if the corresponding `a` (two 64-bit floating point numbers) elementsare ordered +/// and less than `b` (two 64-bit floating point numbers) elements /// otherwise set all bits to 0. /// #[inline] @@ -4124,8 +4124,8 @@ pub unsafe fn __msa_fclt_d(a: v2f64, b: v2f64) -> v2i64 { /// Vector Floating-Point Quiet Compare Not Equal /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) -/// elements if the corresponding 'a' (four 32-bit floating point numbers)and -/// 'b' (four 32-bit floating point numbers)elements are ordered and not equal +/// elements if the corresponding `a` (four 32-bit floating point numbers)and +/// `b` (four 32-bit floating point numbers)elements are ordered and not equal /// otherwise set all bits to 0. /// #[inline] @@ -4138,8 +4138,8 @@ pub unsafe fn __msa_fcne_w(a: v4f32, b: v4f32) -> v4i32 { /// Vector Floating-Point Quiet Compare Not Equal /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) -/// elements if the corresponding 'a' (two 64-bit floating point numbers) and -/// 'b' (two 64-bit floating point numbers) elementsare ordered and not equal +/// elements if the corresponding `a` (two 64-bit floating point numbers) and +/// `b` (two 64-bit floating point numbers) elementsare ordered and not equal /// otherwise set all bits to 0. /// #[inline] @@ -4152,8 +4152,8 @@ pub unsafe fn __msa_fcne_d(a: v2f64, b: v2f64) -> v2i64 { /// Vector Floating-Point Quiet Compare Ordered /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) -/// elements if the corresponding 'a' (four 32-bit floating point numbers)and -/// 'b' (four 32-bit floating point numbers)elements are ordered, i.e. both elementsare not NaN values, +/// elements if the corresponding `a` (four 32-bit floating point numbers)and +/// `b` (four 32-bit floating point numbers)elements are ordered, i.e. both elementsare not NaN values, /// otherwise set all bits to 0. /// #[inline] @@ -4166,8 +4166,8 @@ pub unsafe fn __msa_fcor_w(a: v4f32, b: v4f32) -> v4i32 { /// Vector Floating-Point Quiet Compare Ordered /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) -/// elements if the corresponding 'a' (two 64-bit floating point numbers) and -/// 'b' (two 64-bit floating point numbers) elementsare ordered, i.e. both elementsare not NaN values, +/// elements if the corresponding `a` (two 64-bit floating point numbers) and +/// `b` (two 64-bit floating point numbers) elementsare ordered, i.e. both elementsare not NaN values, /// otherwise set all bits to 0. /// #[inline] @@ -4180,8 +4180,8 @@ pub unsafe fn __msa_fcor_d(a: v2f64, b: v2f64) -> v2i64 { /// Vector Floating-Point Quiet Compare Unordered or Equal /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) -/// elements if the corresponding 'a' (four 32-bit floating point numbers)and -/// 'b' (four 32-bit floating point numbers)elements are unordered or equal, +/// elements if the corresponding `a` (four 32-bit floating point numbers)and +/// `b` (four 32-bit floating point numbers)elements are unordered or equal, /// otherwise set all bits to 0. /// #[inline] @@ -4194,8 +4194,8 @@ pub unsafe fn __msa_fcueq_w(a: v4f32, b: v4f32) -> v4i32 { /// Vector Floating-Point Quiet Compare Unordered or Equal /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) -/// elements if the corresponding 'a' (two 64-bit floating point numbers) and -/// 'b' (two 64-bit floating point numbers) elementsare unordered or equal, +/// elements if the corresponding `a` (two 64-bit floating point numbers) and +/// `b` (two 64-bit floating point numbers) elementsare unordered or equal, /// otherwise set all bits to 0. /// #[inline] @@ -4208,8 +4208,8 @@ pub unsafe fn __msa_fcueq_d(a: v2f64, b: v2f64) -> v2i64 { /// Vector Floating-Point Quiet Compare Unordered or Less or Equal /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) -/// elements if the corresponding elements in 'a' (four 32-bit floating point numbers) -/// are unordered or less than or equal to 'b' (four 32-bit floating point numbers)elements, +/// elements if the corresponding elements in `a` (four 32-bit floating point numbers) +/// are unordered or less than or equal to `b` (four 32-bit floating point numbers)elements, /// otherwise set all bits to 0. /// #[inline] @@ -4222,8 +4222,8 @@ pub unsafe fn __msa_fcule_w(a: v4f32, b: v4f32) -> v4i32 { /// Vector Floating-Point Quiet Compare Unordered or Less or Equal /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) -/// elements if the corresponding elements in 'a' (two 64-bit floating point numbers) -/// are unordered or less than or equal to 'b' (two 64-bit floating point numbers) elements, +/// elements if the corresponding elements in `a` (two 64-bit floating point numbers) +/// are unordered or less than or equal to `b` (two 64-bit floating point numbers) elements, /// otherwise set all bits to 0. /// #[inline] @@ -4236,8 +4236,8 @@ pub unsafe fn __msa_fcule_d(a: v2f64, b: v2f64) -> v2i64 { /// Vector Floating-Point Quiet Compare Unordered or Less Than /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) -/// elements if the corresponding elements in 'a' (four 32-bit floating point numbers) -/// are unordered or less than 'b' (four 32-bit floating point numbers)elements, +/// elements if the corresponding elements in `a` (four 32-bit floating point numbers) +/// are unordered or less than `b` (four 32-bit floating point numbers)elements, /// otherwise set all bits to 0. /// #[inline] @@ -4250,8 +4250,8 @@ pub unsafe fn __msa_fcult_w(a: v4f32, b: v4f32) -> v4i32 { /// Vector Floating-Point Quiet Compare Unordered or Less Than /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) -/// elements if the corresponding elements in 'a' (two 64-bit floating point numbers) -/// are unordered or less than 'b' (two 64-bit floating point numbers) elements, +/// elements if the corresponding elements in `a` (two 64-bit floating point numbers) +/// are unordered or less than `b` (two 64-bit floating point numbers) elements, /// otherwise set all bits to 0. /// #[inline] @@ -4264,8 +4264,8 @@ pub unsafe fn __msa_fcult_d(a: v2f64, b: v2f64) -> v2i64 { /// Vector Floating-Point Quiet Compare Unordered /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) -/// elements if the corresponding 'a' (four 32-bit floating point numbers) -/// and 'b' (four 32-bit floating point numbers)elements are unordered, +/// elements if the corresponding `a` (four 32-bit floating point numbers) +/// and `b` (four 32-bit floating point numbers)elements are unordered, /// i.e. at least oneelement is a NaN value, otherwise set all bits to 0. /// #[inline] @@ -4278,8 +4278,8 @@ pub unsafe fn __msa_fcun_w(a: v4f32, b: v4f32) -> v4i32 { /// Vector Floating-Point Quiet Compare Unordered /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) -/// elements if the corresponding 'a' (two 64-bit floating point numbers) -/// and 'b' (two 64-bit floating point numbers) elementsare unordered, +/// elements if the corresponding `a` (two 64-bit floating point numbers) +/// and `b` (two 64-bit floating point numbers) elementsare unordered, /// i.e. at least oneelement is a NaN value, otherwise set all bits to 0. /// #[inline] @@ -4292,8 +4292,8 @@ pub unsafe fn __msa_fcun_d(a: v2f64, b: v2f64) -> v2i64 { /// Vector Floating-Point Quiet Compare Unordered or Not Equal /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) -/// elements if the corresponding 'a' (four 32-bit floating point numbers) -/// and 'b' (four 32-bit floating point numbers)elements are unordered or not equal, +/// elements if the corresponding `a` (four 32-bit floating point numbers) +/// and `b` (four 32-bit floating point numbers)elements are unordered or not equal, /// otherwise set all bits to 0. /// #[inline] @@ -4306,8 +4306,8 @@ pub unsafe fn __msa_fcune_w(a: v4f32, b: v4f32) -> v4i32 { /// Vector Floating-Point Quiet Compare Unordered or Not Equal /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) -/// elements if the corresponding 'a' (two 64-bit floating point numbers) -/// and 'b' (two 64-bit floating point numbers) elementsare unordered or not equal, +/// elements if the corresponding `a` (two 64-bit floating point numbers) +/// and `b` (two 64-bit floating point numbers) elementsare unordered or not equal, /// otherwise set all bits to 0. /// #[inline] @@ -4319,8 +4319,8 @@ pub unsafe fn __msa_fcune_d(a: v2f64, b: v2f64) -> v2i64 { /// Vector Floating-Point Division /// -/// The floating-point elements in vector 'a' (four 32-bit floating point numbers) -/// are divided by the floating-point elements in vector 'b' (four 32-bit floating point numbers) +/// The floating-point elements in vector `a` (four 32-bit floating point numbers) +/// are divided by the floating-point elements in vector `b` (four 32-bit floating point numbers) /// The result is written to vector (four 32-bit floating point numbers). /// #[inline] @@ -4332,8 +4332,8 @@ pub unsafe fn __msa_fdiv_w(a: v4f32, b: v4f32) -> v4f32 { /// Vector Floating-Point Division /// -/// The floating-point elements in vector 'a' (two 64-bit floating point numbers) -/// are divided by the floating-point elements in vector 'b' (two 64-bit floating point numbers) +/// The floating-point elements in vector `a` (two 64-bit floating point numbers) +/// are divided by the floating-point elements in vector `b` (two 64-bit floating point numbers) /// The result is written to vector (two 64-bit floating point numbers). /// #[inline] @@ -4346,8 +4346,8 @@ pub unsafe fn __msa_fdiv_d(a: v2f64, b: v2f64) -> v2f64 { /* FIXME: 16-bit float /// Vector Floating-Point Down-Convert Interchange Format /// -/// The floating-point elements in vector 'a' (four 64-bit floating point numbers) -/// and vector 'b' (four 64-bit floating point numbers) are down-converted +/// The floating-point elements in vector `a` (four 64-bit floating point numbers) +/// and vector `b` (four 64-bit floating point numbers) are down-converted /// to a smaller interchange format, i.e. from 64-bitto 32-bit, or from 32-bit to 16-bit. /// The result is written to vector (8 16-bit floating point numbers). /// @@ -4360,8 +4360,8 @@ pub unsafe fn __msa_fexdo_h(a: v4f32, b: v4f32) -> f16x8 { /// Vector Floating-Point Down-Convert Interchange Format /// -/// The floating-point elements in vector 'a' (two 64-bit floating point numbers) -/// and vector 'b' (two 64-bit floating point numbers) are down-converted +/// The floating-point elements in vector `a` (two 64-bit floating point numbers) +/// and vector `b` (two 64-bit floating point numbers) are down-converted /// to a smaller interchange format, i.e. from 64-bitto 32-bit, or from 32-bit to 16-bit. /// The result is written to vector (four 32-bit floating point numbers). /// @@ -4374,8 +4374,8 @@ pub unsafe fn __msa_fexdo_w(a: v2f64, b: v2f64) -> v4f32 { /// Vector Floating-Point Down-Convert Interchange Format /// -/// The floating-point elements in vector 'a' (four 32-bit floating point numbers) -/// are scaled, i.e. multiplied, by 2 to the power of integer elements in vector 'b' +/// The floating-point elements in vector `a` (four 32-bit floating point numbers) +/// are scaled, i.e. multiplied, by 2 to the power of integer elements in vector `b` /// (four signed 32-bit integer numbers). /// The result is written to vector (four 32-bit floating point numbers). /// @@ -4388,8 +4388,8 @@ pub unsafe fn __msa_fexp2_w(a: v4f32, b: v4i32) -> v4f32 { /// Vector Floating-Point Down-Convert Interchange Format /// -/// The floating-point elements in vector 'a' (two 64-bit floating point numbers) -/// are scaled, i.e. multiplied, by 2 to the power of integer elements in vector 'b' +/// The floating-point elements in vector `a` (two 64-bit floating point numbers) +/// are scaled, i.e. multiplied, by 2 to the power of integer elements in vector `b` /// (two signed 64-bit integer numbers). /// The result is written to vector (two 64-bit floating point numbers). /// @@ -4403,7 +4403,7 @@ pub unsafe fn __msa_fexp2_d(a: v2f64, b: v2i64) -> v2f64 { /* FIXME: 16-bit float /// Vector Floating-Point Up-Convert Interchange Format Left /// -/// The left half floating-point elements in vector 'a' (two 16-bit floating point numbers) +/// The left half floating-point elements in vector `a` (two 16-bit floating point numbers) /// are up-converted to a larger interchange format, /// i.e. from 16-bit to 32-bit, or from 32-bit to 64-bit. /// The result is written to vector (four 32-bit floating point numbers). @@ -4417,7 +4417,7 @@ pub unsafe fn __msa_fexupl_w(a: f16x8) -> v4f32 { /// Vector Floating-Point Up-Convert Interchange Format Left /// -/// The left half floating-point elements in vector 'a' (four 32-bit floating point numbers) +/// The left half floating-point elements in vector `a` (four 32-bit floating point numbers) /// are up-converted to a larger interchange format, /// i.e. from 16-bit to 32-bit, or from 32-bit to 64-bit. /// The result is written to vector (two 64-bit floating point numbers). @@ -4432,7 +4432,7 @@ pub unsafe fn __msa_fexupl_d(a: v4f32) -> v2f64 { /* FIXME: 16-bit float /// Vector Floating-Point Up-Convert Interchange Format Left /// -/// The right half floating-point elements in vector 'a' (two 16-bit floating point numbers) +/// The right half floating-point elements in vector `a` (two 16-bit floating point numbers) /// are up-converted to a larger interchange format, /// i.e. from 16-bit to 32-bit, or from 32-bit to 64-bit. /// The result is written to vector (four 32-bit floating point numbers). @@ -4446,7 +4446,7 @@ pub unsafe fn __msa_fexupr_w(a: f16x8) -> v4f32 { /// Vector Floating-Point Up-Convert Interchange Format Left /// -/// The right half floating-point elements in vector 'a' (four 32-bit floating point numbers) +/// The right half floating-point elements in vector `a` (four 32-bit floating point numbers) /// are up-converted to a larger interchange format, /// i.e. from 16-bit to 32-bit, or from 32-bit to 64-bit. /// The result is written to vector (two 64-bit floating point numbers). @@ -4460,7 +4460,7 @@ pub unsafe fn __msa_fexupr_d(a: v4f32) -> v2f64 { /// Vector Floating-Point Round and Convert from Signed Integer /// -/// The signed integer elements in vector 'a' (four signed 32-bit integer numbers) +/// The signed integer elements in vector `a` (four signed 32-bit integer numbers) /// are converted to floating-point values. /// The result is written to vector (four 32-bit floating point numbers). /// @@ -4473,7 +4473,7 @@ pub unsafe fn __msa_ffint_s_w(a: v4i32) -> v4f32 { /// Vector Floating-Point Round and Convert from Signed Integer /// -/// The signed integer elements in vector 'a' (two signed 64-bit integer numbers) +/// The signed integer elements in vector `a` (two signed 64-bit integer numbers) /// are converted to floating-point values. /// The result is written to vector (two 64-bit floating point numbers). /// @@ -4486,7 +4486,7 @@ pub unsafe fn __msa_ffint_s_d(a: v2i64) -> v2f64 { /// Vector Floating-Point Round and Convert from Unsigned Integer /// -/// The unsigned integer elements in vector 'a' (four unsigned 32-bit integer numbers) +/// The unsigned integer elements in vector `a` (four unsigned 32-bit integer numbers) /// are converted to floating-point values. /// The result is written to vector (four 32-bit floating point numbers). /// @@ -4499,7 +4499,7 @@ pub unsafe fn __msa_ffint_u_w(a: v4u32) -> v4f32 { /// Vector Floating-Point Round and Convert from Unsigned Integer /// -/// The unsigned integer elements in vector 'a' (two unsigned 64-bit integer numbers) +/// The unsigned integer elements in vector `a` (two unsigned 64-bit integer numbers) /// are converted to floating-point values. /// The result is written to vector (two 64-bit floating point numbers). /// @@ -4512,7 +4512,7 @@ pub unsafe fn __msa_ffint_u_d(a: v2u64) -> v2f64 { /// Vector Floating-Point Convert from Fixed-Point Left /// -/// The left half fixed-point elements in vector 'a' (eight signed 16-bit integer numbers) +/// The left half fixed-point elements in vector `a` (eight signed 16-bit integer numbers) /// are up-converted to floating-point data format. /// i.e. from 16-bit Q15 to 32-bit floating-point, or from 32-bit Q31 to 64-bit floating-point. /// The result is written to vector (four 32-bit floating point numbers). @@ -4526,7 +4526,7 @@ pub unsafe fn __msa_ffql_w(a: v8i16) -> v4f32 { /// Vector Floating-Point Convert from Fixed-Point Left /// -/// The left half fixed-point elements in vector 'a' (four signed 32-bit integer numbers) +/// The left half fixed-point elements in vector `a` (four signed 32-bit integer numbers) /// are up-converted to floating-point data format. /// i.e. from 16-bit Q15 to 32-bit floating-point, or from 32-bit Q31 to 64-bit floating-point. /// The result is written to vector (two 64-bit floating point numbers). @@ -4540,7 +4540,7 @@ pub unsafe fn __msa_ffql_d(a: v4i32) -> v2f64 { /// Vector Floating-Point Convert from Fixed-Point Left /// -/// The right half fixed-point elements in vector 'a' (eight signed 16-bit integer numbers) +/// The right half fixed-point elements in vector `a` (eight signed 16-bit integer numbers) /// are up-converted to floating-point data format. /// i.e. from 16-bit Q15 to 32-bit floating-point, or from 32-bit Q31 to 64-bit floating-point. /// The result is written to vector (four 32-bit floating point numbers). @@ -4554,7 +4554,7 @@ pub unsafe fn __msa_ffqr_w(a: v8i16) -> v4f32 { /// Vector Floating-Point Convert from Fixed-Point Left /// -/// The right half fixed-point elements in vector 'a' (four signed 32-bit integer numbers) +/// The right half fixed-point elements in vector `a` (four signed 32-bit integer numbers) /// are up-converted to floating-point data format. /// i.e. from 16-bit Q15 to 32-bit floating-point, or from 32-bit Q31 to 64-bit floating-point. /// The result is written to vector (two 64-bit floating point numbers). @@ -4620,7 +4620,7 @@ pub unsafe fn __msa_fill_d(a: i64) -> v2i64 { /// Vector Floating-Point Base 2 Logarithm /// -/// The signed integral base 2 exponents of floating-point elements in vector 'a' +/// The signed integral base 2 exponents of floating-point elements in vector `a` /// (four 32-bit floating point numbers)are written as floating-point values to vector elements /// (four 32-bit floating point numbers). /// @@ -4633,7 +4633,7 @@ pub unsafe fn __msa_flog2_w(a: v4f32) -> v4f32 { /// Vector Floating-Point Base 2 Logarithm /// -/// The signed integral base 2 exponents of floating-point elements in vector 'a' +/// The signed integral base 2 exponents of floating-point elements in vector `a` /// (two 64-bit floating point numbers) are written as floating-point values to vector elements /// (two 64-bit floating point numbers). /// @@ -4646,9 +4646,9 @@ pub unsafe fn __msa_flog2_d(a: v2f64) -> v2f64 { /// Vector Floating-Point Multiply-Add /// -/// The floating-point elements in vector 'b' (four 32-bit floating point numbers) -/// multiplied by floating-point elements in vector 'c' (four 32-bit floating point numbers) -/// are added to the floating-point elements in vector 'a' (four 32-bit floating point numbers) +/// The floating-point elements in vector `b` (four 32-bit floating point numbers) +/// multiplied by floating-point elements in vector `c` (four 32-bit floating point numbers) +/// are added to the floating-point elements in vector `a` (four 32-bit floating point numbers) /// #[inline] #[target_feature(enable = "msa")] @@ -4659,9 +4659,9 @@ pub unsafe fn __msa_fmadd_w(a: v4f32, b: v4f32, c: v4f32) -> v4f32 { /// Vector Floating-Point Multiply-Add /// -/// The floating-point elements in vector 'b' (two 64-bit floating point numbers) -/// multiplied by floating-point elements in vector 'c' (two 64-bit floating point numbers) -/// are added to the floating-point elements in vector 'a' (two 64-bit floating point numbers) +/// The floating-point elements in vector `b` (two 64-bit floating point numbers) +/// multiplied by floating-point elements in vector `c` (two 64-bit floating point numbers) +/// are added to the floating-point elements in vector `a` (two 64-bit floating point numbers) /// #[inline] #[target_feature(enable = "msa")] @@ -4672,8 +4672,8 @@ pub unsafe fn __msa_fmadd_d(a: v2f64, b: v2f64, c: v2f64) -> v2f64 { /// Vector Floating-Point Maximum /// -/// The largest values between corresponding floating-point elements in vector 'a' -/// (four 32-bit floating point numbers)andvector 'b' (four 32-bit floating point numbers) +/// The largest values between corresponding floating-point elements in vector `a` +/// (four 32-bit floating point numbers)andvector `b` (four 32-bit floating point numbers) /// are written to vector (four 32-bit floating point numbers) /// #[inline] @@ -4685,8 +4685,8 @@ pub unsafe fn __msa_fmax_w(a: v4f32, b: v4f32) -> v4f32 { /// Vector Floating-Point Maximum /// -/// The largest values between corresponding floating-point elements in vector 'a' -/// (two 64-bit floating point numbers) and vector 'b' (two 64-bit floating point numbers) +/// The largest values between corresponding floating-point elements in vector `a` +/// (two 64-bit floating point numbers) and vector `b` (two 64-bit floating point numbers) /// are written to vector (two 64-bit floating point numbers) /// #[inline] @@ -4699,8 +4699,8 @@ pub unsafe fn __msa_fmax_d(a: v2f64, b: v2f64) -> v2f64 { /// Vector Floating-Point Maximum Based on Absolute Values /// /// The value with the largest magnitude, i.e. absolute value, between corresponding -/// floating-point elements in vector 'a' (four 32-bit floating point numbers) -/// and vector 'b' (four 32-bit floating point numbers) +/// floating-point elements in vector `a` (four 32-bit floating point numbers) +/// and vector `b` (four 32-bit floating point numbers) /// are written to vector (four 32-bit floating point numbers) /// #[inline] @@ -4713,8 +4713,8 @@ pub unsafe fn __msa_fmax_a_w(a: v4f32, b: v4f32) -> v4f32 { /// Vector Floating-Point Maximum Based on Absolute Values /// /// The value with the largest magnitude, i.e. absolute value, between corresponding -/// floating-point elements in vector 'a' (two 64-bit floating point numbers) -/// and vector 'b' (two 64-bit floating point numbers) +/// floating-point elements in vector `a` (two 64-bit floating point numbers) +/// and vector `b` (two 64-bit floating point numbers) /// are written to vector (two 64-bit floating point numbers) /// #[inline] @@ -4726,8 +4726,8 @@ pub unsafe fn __msa_fmax_a_d(a: v2f64, b: v2f64) -> v2f64 { /// Vector Floating-Point Minimum /// -/// The smallest values between corresponding floating-point elements in vector 'a' -/// (four 32-bit floating point numbers)andvector 'b' (four 32-bit floating point numbers) +/// The smallest values between corresponding floating-point elements in vector `a` +/// (four 32-bit floating point numbers)andvector `b` (four 32-bit floating point numbers) /// are written to vector (four 32-bit floating point numbers) /// #[inline] @@ -4739,8 +4739,8 @@ pub unsafe fn __msa_fmin_w(a: v4f32, b: v4f32) -> v4f32 { /// Vector Floating-Point Minimum /// -/// The smallest values between corresponding floating-point elements in vector 'a' -/// (two 64-bit floating point numbers) and vector 'b' (two 64-bit floating point numbers) +/// The smallest values between corresponding floating-point elements in vector `a` +/// (two 64-bit floating point numbers) and vector `b` (two 64-bit floating point numbers) /// are written to vector (two 64-bit floating point numbers) /// #[inline] @@ -4753,8 +4753,8 @@ pub unsafe fn __msa_fmin_d(a: v2f64, b: v2f64) -> v2f64 { /// Vector Floating-Point Minimum Based on Absolute Values /// /// The value with the smallest magnitude, i.e. absolute value, between corresponding -/// floating-point elements in vector 'a' (four 32-bit floating point numbers) -/// and vector 'b' (four 32-bit floating point numbers) +/// floating-point elements in vector `a` (four 32-bit floating point numbers) +/// and vector `b` (four 32-bit floating point numbers) /// are written to vector (four 32-bit floating point numbers) /// #[inline] @@ -4767,8 +4767,8 @@ pub unsafe fn __msa_fmin_a_w(a: v4f32, b: v4f32) -> v4f32 { /// Vector Floating-Point Minimum Based on Absolute Values /// /// The value with the smallest magnitude, i.e. absolute value, between corresponding -/// floating-point elements in vector 'a' (two 64-bit floating point numbers) -/// and vector 'b' (two 64-bit floating point numbers) +/// floating-point elements in vector `a` (two 64-bit floating point numbers) +/// and vector `b` (two 64-bit floating point numbers) /// are written to vector (two 64-bit floating point numbers) /// #[inline] @@ -4780,9 +4780,9 @@ pub unsafe fn __msa_fmin_a_d(a: v2f64, b: v2f64) -> v2f64 { /// Vector Floating-Point Multiply-Sub /// -/// The floating-point elements in vector 'b' (four 32-bit floating point numbers) -/// multiplied by floating-point elements in vector 'c' (four 32-bit floating point numbers) -/// are subtracted from the floating-point elements in vector 'a' (four 32-bit floating point numbers) +/// The floating-point elements in vector `b` (four 32-bit floating point numbers) +/// multiplied by floating-point elements in vector `c` (four 32-bit floating point numbers) +/// are subtracted from the floating-point elements in vector `a` (four 32-bit floating point numbers) /// #[inline] #[target_feature(enable = "msa")] @@ -4793,9 +4793,9 @@ pub unsafe fn __msa_fmsub_w(a: v4f32, b: v4f32, c: v4f32) -> v4f32 { /// Vector Floating-Point Multiply-Sub /// -/// The floating-point elements in vector 'b' (two 64-bit floating point numbers) -/// multiplied by floating-point elements in vector 'c' (two 64-bit floating point numbers) -/// are subtracted from the floating-point elements in vector 'a' (two 64-bit floating point numbers) +/// The floating-point elements in vector `b` (two 64-bit floating point numbers) +/// multiplied by floating-point elements in vector `c` (two 64-bit floating point numbers) +/// are subtracted from the floating-point elements in vector `a` (two 64-bit floating point numbers) /// #[inline] #[target_feature(enable = "msa")] @@ -4806,8 +4806,8 @@ pub unsafe fn __msa_fmsub_d(a: v2f64, b: v2f64, c: v2f64) -> v2f64 { /// Vector Floating-Point Multiplication /// -/// The floating-point elements in vector 'a' (four 32-bit floating point numbers)are -/// multiplied by floating-point elements in vector 'b' (four 32-bit floating point numbers) +/// The floating-point elements in vector `a` (four 32-bit floating point numbers)are +/// multiplied by floating-point elements in vector `b` (four 32-bit floating point numbers) /// #[inline] #[target_feature(enable = "msa")] @@ -4818,8 +4818,8 @@ pub unsafe fn __msa_fmul_w(a: v4f32, b: v4f32) -> v4f32 { /// Vector Floating-Point Multiplication /// -/// The floating-point elements in vector 'a' (two 64-bit floating point numbers) are -/// multiplied by floating-point elements in vector 'b' (two 64-bit floating point numbers) +/// The floating-point elements in vector `a` (two 64-bit floating point numbers) are +/// multiplied by floating-point elements in vector `b` (two 64-bit floating point numbers) /// #[inline] #[target_feature(enable = "msa")] @@ -4830,7 +4830,7 @@ pub unsafe fn __msa_fmul_d(a: v2f64, b: v2f64) -> v2f64 { /// Vector Floating-Point Round to Integer /// -/// The floating-point elements in vector 'a' (four 32-bit floating point numbers) +/// The floating-point elements in vector `a` (four 32-bit floating point numbers) /// are rounded to an integral valued floating-point number in the same format based /// on the rounding mode bits RM in MSA Control and Status Register MSACSR. /// @@ -4843,7 +4843,7 @@ pub unsafe fn __msa_frint_w(a: v4f32) -> v4f32 { /// Vector Floating-Point Round to Integer /// -/// The floating-point elements in vector 'a' (two 64-bit floating point numbers) +/// The floating-point elements in vector `a` (two 64-bit floating point numbers) /// are rounded to an integral valued floating-point number in the same format based /// on the rounding mode bits RM in MSA Control and Status Register MSACSR. /// @@ -4856,7 +4856,7 @@ pub unsafe fn __msa_frint_d(a: v2f64) -> v2f64 { /// Vector Approximate Floating-Point Reciprocal /// -/// The reciprocals of floating-point elements in vector 'a' (four 32-bit floating point numbers) +/// The reciprocals of floating-point elements in vector `a` (four 32-bit floating point numbers) /// are calculated and the result is written to vector (four 32-bit floating point numbers) /// #[inline] @@ -4868,7 +4868,7 @@ pub unsafe fn __msa_frcp_w(a: v4f32) -> v4f32 { /// Vector Approximate Floating-Point Reciprocal /// -/// The reciprocals of floating-point elements in vector 'a' (two 64-bit floating point numbers) +/// The reciprocals of floating-point elements in vector `a` (two 64-bit floating point numbers) /// are calculated and the result is written to vector (two 64-bit floating point numbers) /// #[inline] @@ -4880,7 +4880,7 @@ pub unsafe fn __msa_frcp_d(a: v2f64) -> v2f64 { /// Vector Approximate Floating-Point Reciprocal of Square Root /// -/// The reciprocals of the square roots of floating-point elements in vector 'a' (four 32-bit floating point numbers) +/// The reciprocals of the square roots of floating-point elements in vector `a` (four 32-bit floating point numbers) /// are calculated and the result is written to vector (four 32-bit floating point numbers) /// #[inline] @@ -4892,7 +4892,7 @@ pub unsafe fn __msa_frsqrt_w(a: v4f32) -> v4f32 { /// Vector Approximate Floating-Point Reciprocal of Square Root /// -/// The reciprocals of the square roots of floating-point elements in vector 'a' (two 64-bit floating point numbers) +/// The reciprocals of the square roots of floating-point elements in vector `a` (two 64-bit floating point numbers) /// are calculated and the result is written to vector (two 64-bit floating point numbers) /// #[inline] @@ -4905,8 +4905,8 @@ pub unsafe fn __msa_frsqrt_d(a: v2f64) -> v2f64 { /// Vector Floating-Point Signaling Compare Always False /// /// Set all bits to 0 in vector (four signed 32-bit integer numbers) elements. -/// Signaling and quiet NaN elements in vector 'a' (four 32-bit floating point numbers) -/// or 'b' (four 32-bit floating point numbers)signal Invalid Operation exception. +/// Signaling and quiet NaN elements in vector `a` (four 32-bit floating point numbers) +/// or `b` (four 32-bit floating point numbers)signal Invalid Operation exception. /// In case of a floating-point exception, the default result has all bits set to 0 /// #[inline] @@ -4919,8 +4919,8 @@ pub unsafe fn __msa_fsaf_w(a: v4f32, b: v4f32) -> v4i32 { /// Vector Floating-Point Signaling Compare Always False /// /// Set all bits to 0 in vector (two signed 64-bit integer numbers) elements. -/// Signaling and quiet NaN elements in vector 'a' (two 64-bit floating point numbers) -/// or 'b' (two 64-bit floating point numbers) signal Invalid Operation exception. +/// Signaling and quiet NaN elements in vector `a` (two 64-bit floating point numbers) +/// or `b` (two 64-bit floating point numbers) signal Invalid Operation exception. /// In case of a floating-point exception, the default result has all bits set to 0 /// #[inline] @@ -4933,8 +4933,8 @@ pub unsafe fn __msa_fsaf_d(a: v2f64, b: v2f64) -> v2i64 { /// Vector Floating-Point Signaling Compare Equal /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements -/// if the corresponding 'a' (four 32-bit floating point numbers) -/// and 'b' (four 32-bit floating point numbers)elements are equal, otherwise set all bits to 0. +/// if the corresponding `a` (four 32-bit floating point numbers) +/// and `b` (four 32-bit floating point numbers)elements are equal, otherwise set all bits to 0. /// #[inline] #[target_feature(enable = "msa")] @@ -4946,8 +4946,8 @@ pub unsafe fn __msa_fseq_w(a: v4f32, b: v4f32) -> v4i32 { /// Vector Floating-Point Signaling Compare Equal /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements -/// if the corresponding 'a' (two 64-bit floating point numbers) -/// and 'b' (two 64-bit floating point numbers) elementsare equal, otherwise set all bits to 0. +/// if the corresponding `a` (two 64-bit floating point numbers) +/// and `b` (two 64-bit floating point numbers) elementsare equal, otherwise set all bits to 0. /// #[inline] #[target_feature(enable = "msa")] @@ -4959,8 +4959,8 @@ pub unsafe fn __msa_fseq_d(a: v2f64, b: v2f64) -> v2i64 { /// Vector Floating-Point Signaling Compare Less or Equal /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements -/// if the corresponding 'a' (four 32-bit floating point numbers)elements -/// are less than or equal to 'b' (four 32-bit floating point numbers)elements, otherwise set all bits to 0. +/// if the corresponding `a` (four 32-bit floating point numbers)elements +/// are less than or equal to `b` (four 32-bit floating point numbers)elements, otherwise set all bits to 0. /// #[inline] #[target_feature(enable = "msa")] @@ -4972,8 +4972,8 @@ pub unsafe fn __msa_fsle_w(a: v4f32, b: v4f32) -> v4i32 { /// Vector Floating-Point Signaling Compare Less or Equal /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements -/// if the corresponding 'a' (two 64-bit floating point numbers) elements -/// are less than or equal to 'b' (two 64-bit floating point numbers) elements, otherwise set all bits to 0. +/// if the corresponding `a` (two 64-bit floating point numbers) elements +/// are less than or equal to `b` (two 64-bit floating point numbers) elements, otherwise set all bits to 0. /// #[inline] #[target_feature(enable = "msa")] @@ -4985,8 +4985,8 @@ pub unsafe fn __msa_fsle_d(a: v2f64, b: v2f64) -> v2i64 { /// Vector Floating-Point Signaling Compare Less Than /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements -/// if the corresponding 'a' (four 32-bit floating point numbers)elements -/// are less than 'b' (four 32-bit floating point numbers)elements, otherwise set all bits to 0. +/// if the corresponding `a` (four 32-bit floating point numbers)elements +/// are less than `b` (four 32-bit floating point numbers)elements, otherwise set all bits to 0. /// #[inline] #[target_feature(enable = "msa")] @@ -4998,8 +4998,8 @@ pub unsafe fn __msa_fslt_w(a: v4f32, b: v4f32) -> v4i32 { /// Vector Floating-Point Signaling Compare Less Than /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements -/// if the corresponding 'a' (two 64-bit floating point numbers) elements -/// are less than 'b' (two 64-bit floating point numbers) elements, otherwise set all bits to 0. +/// if the corresponding `a` (two 64-bit floating point numbers) elements +/// are less than `b` (two 64-bit floating point numbers) elements, otherwise set all bits to 0. /// #[inline] #[target_feature(enable = "msa")] @@ -5011,8 +5011,8 @@ pub unsafe fn __msa_fslt_d(a: v2f64, b: v2f64) -> v2i64 { /// Vector Floating-Point Signaling Compare Not Equal /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements -/// if the corresponding 'a' (four 32-bit floating point numbers)and -/// 'b' (four 32-bit floating point numbers)elements are not equal, otherwise set all bits to 0. +/// if the corresponding `a` (four 32-bit floating point numbers)and +/// `b` (four 32-bit floating point numbers)elements are not equal, otherwise set all bits to 0. /// #[inline] #[target_feature(enable = "msa")] @@ -5024,8 +5024,8 @@ pub unsafe fn __msa_fsne_w(a: v4f32, b: v4f32) -> v4i32 { /// Vector Floating-Point Signaling Compare Not Equal /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements -/// if the corresponding 'a' (two 64-bit floating point numbers) and -/// 'b' (two 64-bit floating point numbers) elementsare not equal, otherwise set all bits to 0. +/// if the corresponding `a` (two 64-bit floating point numbers) and +/// `b` (two 64-bit floating point numbers) elementsare not equal, otherwise set all bits to 0. /// #[inline] #[target_feature(enable = "msa")] @@ -5037,8 +5037,8 @@ pub unsafe fn __msa_fsne_d(a: v2f64, b: v2f64) -> v2i64 { /// Vector Floating-Point Signaling Compare Ordered /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements -/// if the corresponding 'a' (four 32-bit floating point numbers)and -/// 'b' (four 32-bit floating point numbers)elements are ordered, +/// if the corresponding `a` (four 32-bit floating point numbers)and +/// `b` (four 32-bit floating point numbers)elements are ordered, /// i.e. both elementsare not NaN values, otherwise set all bits to 0. /// #[inline] @@ -5051,8 +5051,8 @@ pub unsafe fn __msa_fsor_w(a: v4f32, b: v4f32) -> v4i32 { /// Vector Floating-Point Signaling Compare Ordered /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements -/// if the corresponding 'a' (two 64-bit floating point numbers) and -/// 'b' (two 64-bit floating point numbers) elementsare ordered, +/// if the corresponding `a` (two 64-bit floating point numbers) and +/// `b` (two 64-bit floating point numbers) elementsare ordered, /// i.e. both elementsare not NaN values, otherwise set all bits to 0. /// #[inline] @@ -5064,7 +5064,7 @@ pub unsafe fn __msa_fsor_d(a: v2f64, b: v2f64) -> v2i64 { /// Vector Floating-Point Square Root /// -/// The square roots of floating-point elements in vector 'a' +/// The square roots of floating-point elements in vector `a` /// (four 32-bit floating point numbers)are written to vector /// (four 32-bit floating point numbers)elements are ordered, /// @@ -5077,7 +5077,7 @@ pub unsafe fn __msa_fsqrt_w(a: v4f32) -> v4f32 { /// Vector Floating-Point Square Root /// -/// The square roots of floating-point elements in vector 'a' +/// The square roots of floating-point elements in vector `a` /// (two 64-bit floating point numbers) are written to vector /// (two 64-bit floating point numbers) elementsare ordered, /// @@ -5090,8 +5090,8 @@ pub unsafe fn __msa_fsqrt_d(a: v2f64) -> v2f64 { /// Vector Floating-Point Subtraction /// -/// The floating-point elements in vector 'b' (four 32-bit floating point numbers) -/// are subtracted from the floating-point elements in vector 'a' +/// The floating-point elements in vector `b` (four 32-bit floating point numbers) +/// are subtracted from the floating-point elements in vector `a` /// (four 32-bit floating point numbers). /// The result is written to vector (four 32-bit floating point numbers). /// @@ -5104,8 +5104,8 @@ pub unsafe fn __msa_fsub_w(a: v4f32, b: v4f32) -> v4f32 { /// Vector Floating-Point Subtraction /// -/// The floating-point elements in vector 'b' (two 64-bit floating point numbers) -/// are subtracted from the floating-point elements in vector 'a' +/// The floating-point elements in vector `b` (two 64-bit floating point numbers) +/// are subtracted from the floating-point elements in vector `a` /// (two 64-bit floating point numbers). /// The result is written to vector (two 64-bit floating point numbers). /// @@ -5119,8 +5119,8 @@ pub unsafe fn __msa_fsub_d(a: v2f64, b: v2f64) -> v2f64 { /// Vector Floating-Point Signaling Compare Ordered /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements -/// if the corresponding 'a' (four 32-bit floating point numbers)and -/// 'b' (four 32-bit floating point numbers)elements are unordered or equal, +/// if the corresponding `a` (four 32-bit floating point numbers)and +/// `b` (four 32-bit floating point numbers)elements are unordered or equal, /// otherwise set all bits to 0. /// #[inline] @@ -5133,8 +5133,8 @@ pub unsafe fn __msa_fsueq_w(a: v4f32, b: v4f32) -> v4i32 { /// Vector Floating-Point Signaling Compare Ordered /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements -/// if the corresponding 'a' (two 64-bit floating point numbers) and -/// 'b' (two 64-bit floating point numbers) elementsare unordered or equal, +/// if the corresponding `a` (two 64-bit floating point numbers) and +/// `b` (two 64-bit floating point numbers) elementsare unordered or equal, /// otherwise set all bits to 0. /// #[inline] @@ -5147,8 +5147,8 @@ pub unsafe fn __msa_fsueq_d(a: v2f64, b: v2f64) -> v2i64 { /// Vector Floating-Point Signaling Compare Unordered or Less or Equal /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements -/// if the corresponding 'a' (four 32-bit floating point numbers)elements are -/// unordered or less than or equal to 'b' (four 32-bit floating point numbers)elements +/// if the corresponding `a` (four 32-bit floating point numbers)elements are +/// unordered or less than or equal to `b` (four 32-bit floating point numbers)elements /// otherwise set all bits to 0. /// #[inline] @@ -5161,8 +5161,8 @@ pub unsafe fn __msa_fsule_w(a: v4f32, b: v4f32) -> v4i32 { /// Vector Floating-Point Signaling Compare Unordered or Less or Equal /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements -/// if the corresponding 'a' (two 64-bit floating point numbers) elementsare -/// unordered or less than or equal to 'b' (two 64-bit floating point numbers) elements +/// if the corresponding `a` (two 64-bit floating point numbers) elementsare +/// unordered or less than or equal to `b` (two 64-bit floating point numbers) elements /// otherwise set all bits to 0. /// #[inline] @@ -5175,8 +5175,8 @@ pub unsafe fn __msa_fsule_d(a: v2f64, b: v2f64) -> v2i64 { /// Vector Floating-Point Signaling Compare Unordered or Less Than /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements -/// if the corresponding 'a' (four 32-bit floating point numbers)elements -/// are unordered or less than 'b' (four 32-bit floating point numbers)elements +/// if the corresponding `a` (four 32-bit floating point numbers)elements +/// are unordered or less than `b` (four 32-bit floating point numbers)elements /// otherwise set all bits to 0. /// #[inline] @@ -5189,8 +5189,8 @@ pub unsafe fn __msa_fsult_w(a: v4f32, b: v4f32) -> v4i32 { /// Vector Floating-Point Signaling Compare Unordered or Less Than /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements -/// if the corresponding 'a' (two 64-bit floating point numbers) elements -/// are unordered or less than 'b' (two 64-bit floating point numbers) elements +/// if the corresponding `a` (two 64-bit floating point numbers) elements +/// are unordered or less than `b` (two 64-bit floating point numbers) elements /// otherwise set all bits to 0. /// #[inline] @@ -5203,8 +5203,8 @@ pub unsafe fn __msa_fsult_d(a: v2f64, b: v2f64) -> v2i64 { /// Vector Floating-Point Signaling Compare Unordered /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements -/// if the corresponding 'a' (four 32-bit floating point numbers)and -/// 'b' (four 32-bit floating point numbers)elements are unordered, +/// if the corresponding `a` (four 32-bit floating point numbers)and +/// `b` (four 32-bit floating point numbers)elements are unordered, /// i.e. at least one element is a NaN value otherwise set all bits to 0. /// #[inline] @@ -5217,8 +5217,8 @@ pub unsafe fn __msa_fsun_w(a: v4f32, b: v4f32) -> v4i32 { /// Vector Floating-Point Signaling Compare Unordered /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements -/// if the corresponding 'a' (two 64-bit floating point numbers) and -/// 'b' (two 64-bit floating point numbers) elementsare unordered, +/// if the corresponding `a` (two 64-bit floating point numbers) and +/// `b` (two 64-bit floating point numbers) elementsare unordered, /// i.e. at least one element is a NaN value otherwise set all bits to 0. /// #[inline] @@ -5231,8 +5231,8 @@ pub unsafe fn __msa_fsun_d(a: v2f64, b: v2f64) -> v2i64 { /// Vector Floating-Point Signaling Compare Unordered or Not Equal /// /// Set all bits to 1 in vector (four signed 32-bit integer numbers) elements -/// if the corresponding 'a' (four 32-bit floating point numbers)and -/// 'b' (four 32-bit floating point numbers)elements are unordered or not equal, +/// if the corresponding `a` (four 32-bit floating point numbers)and +/// `b` (four 32-bit floating point numbers)elements are unordered or not equal, /// otherwise set all bits to 0. /// #[inline] @@ -5245,8 +5245,8 @@ pub unsafe fn __msa_fsune_w(a: v4f32, b: v4f32) -> v4i32 { /// Vector Floating-Point Signaling Compare Unordered or Not Equal /// /// Set all bits to 1 in vector (two signed 64-bit integer numbers) elements -/// if the corresponding 'a' (two 64-bit floating point numbers) and -/// 'b' (two 64-bit floating point numbers) elementsare unordered or not equal, +/// if the corresponding `a` (two 64-bit floating point numbers) and +/// `b` (two 64-bit floating point numbers) elementsare unordered or not equal, /// otherwise set all bits to 0. /// #[inline] @@ -5258,7 +5258,7 @@ pub unsafe fn __msa_fsune_d(a: v2f64, b: v2f64) -> v2i64 { /// Vector Floating-Point Convert to Signed Integer /// -///The elements in vector 'a' (four 32-bit floating point numbers) +///The elements in vector `a` (four 32-bit floating point numbers) /// are rounded and converted to signed integer values based on the /// rounding mode bits RM in MSA Control and Status Register MSACSR. /// The result is written to vector (four signed 32-bit integer numbers). @@ -5272,7 +5272,7 @@ pub unsafe fn __msa_ftint_s_w(a: v4f32) -> v4i32 { /// Vector Floating-Point Convert to Signed Integer /// -///The elements in vector 'a' (two 64-bit floating point numbers) +///The elements in vector `a` (two 64-bit floating point numbers) /// are rounded and converted to signed integer values based on the /// rounding mode bits RM in MSA Control and Status Register MSACSR. /// The result is written to vector (two signed 64-bit integer numbers). @@ -5286,7 +5286,7 @@ pub unsafe fn __msa_ftint_s_d(a: v2f64) -> v2i64 { /// Vector Floating-Point Convert to Unsigned Integer /// -/// The elements in vector 'a' (four 32-bit floating point numbers) +/// The elements in vector `a` (four 32-bit floating point numbers) /// are rounded and converted to signed integer values based on the /// rounding mode bits RM in MSA Control and Status Register MSACSR. /// The result is written to vector (four unsigned 32-bit integer numbers). @@ -5300,7 +5300,7 @@ pub unsafe fn __msa_ftint_u_w(a: v4f32) -> v4u32 { /// Vector Floating-Point Convert to Unsigned Integer /// -/// The elements in vector 'a' (two 64-bit floating point numbers) +/// The elements in vector `a` (two 64-bit floating point numbers) /// are rounded and converted to signed integer values based on the /// rounding mode bits RM in MSA Control and Status Register MSACSR. /// The result is written to vector (two unsigned 64-bit integer numbers). @@ -5314,8 +5314,8 @@ pub unsafe fn __msa_ftint_u_d(a: v2f64) -> v2u64 { /// Vector Floating-Point Convert to Fixed-Point /// -/// The elements in vector 'a' (four 32-bit floating point numbers) -/// and 'b' (four 32-bit floating point numbers)are down-converted to a fixed-point +/// The elements in vector `a` (four 32-bit floating point numbers) +/// and `b` (four 32-bit floating point numbers)are down-converted to a fixed-point /// representation, i.e. from 64-bit floating-point to 32-bit Q31 fixed-point /// representation, or from 32-bit floating-point to 16-bit Q15 fixed-point representation. /// The result is written to vector (eight signed 16-bit integer numbers). @@ -5329,8 +5329,8 @@ pub unsafe fn __msa_ftq_h(a: v4f32, b: v4f32) -> v8i16 { /// Vector Floating-Point Convert to Fixed-Point /// -/// The elements in vector 'a' (two 64-bit floating point numbers) -/// and 'b' (two 64-bit floating point numbers) are down-converted to a fixed-point +/// The elements in vector `a` (two 64-bit floating point numbers) +/// and `b` (two 64-bit floating point numbers) are down-converted to a fixed-point /// representation, i.e. from 64-bit floating-point to 32-bit Q31 fixed-point /// representation, or from 32-bit floating-point to 16-bit Q15 fixed-point representation. /// The result is written to vector (four signed 32-bit integer numbers). @@ -5344,7 +5344,7 @@ pub unsafe fn __msa_ftq_w(a: v2f64, b: v2f64) -> v4i32 { /// Vector Floating-Point Truncate and Convert to Signed Integer /// -/// The elements in vector 'a' (four 32-bit floating point numbers) +/// The elements in vector `a` (four 32-bit floating point numbers) /// are truncated, i.e. rounded toward zero, to signed integer values. /// The result is written to vector (four signed 32-bit integer numbers). /// @@ -5357,7 +5357,7 @@ pub unsafe fn __msa_ftrunc_s_w(a: v4f32) -> v4i32 { /// Vector Floating-Point Truncate and Convert to Signed Integer /// -/// The elements in vector 'a' (two 64-bit floating point numbers) +/// The elements in vector `a` (two 64-bit floating point numbers) /// are truncated, i.e. rounded toward zero, to signed integer values. /// The result is written to vector (two signed 64-bit integer numbers). /// @@ -5370,7 +5370,7 @@ pub unsafe fn __msa_ftrunc_s_d(a: v2f64) -> v2i64 { /// Vector Floating-Point Truncate and Convert to Unsigned Integer /// -/// The elements in vector 'a' (four 32-bit floating point numbers) +/// The elements in vector `a` (four 32-bit floating point numbers) /// are truncated, i.e. rounded toward zero, to unsigned integer values. /// The result is written to vector (four unsigned 32-bit integer numbers). /// @@ -5383,7 +5383,7 @@ pub unsafe fn __msa_ftrunc_u_w(a: v4f32) -> v4u32 { /// Vector Floating-Point Truncate and Convert to Unsigned Integer /// -/// The elements in vector 'a' (two 64-bit floating point numbers) +/// The elements in vector `a` (two 64-bit floating point numbers) /// are truncated, i.e. rounded toward zero, to unsigned integer values. /// The result is written to vector (two unsigned 64-bit integer numbers). /// @@ -5396,8 +5396,8 @@ pub unsafe fn __msa_ftrunc_u_d(a: v2f64) -> v2u64 { /// Vector Signed Horizontal Add /// -/// The sign-extended odd elements in vector 'a' (sixteen signed 8-bit integer numbers) -/// are added to the sign-extended even elements in vector 'b' (sixteen signed 8-bit integer numbers) +/// The sign-extended odd elements in vector `a` (sixteen signed 8-bit integer numbers) +/// are added to the sign-extended even elements in vector `b` (sixteen signed 8-bit integer numbers) /// producing aresult twice the size of the input operands. /// The result is written to vector (eight signed 16-bit integer numbers). /// @@ -5410,8 +5410,8 @@ pub unsafe fn __msa_hadd_s_h(a: v16i8, b: v16i8) -> v8i16 { /// Vector Signed Horizontal Add /// -/// The sign-extended odd elements in vector 'a' (eight signed 16-bit integer numbers) -/// are added to the sign-extended even elements in vector 'b' (eight signed 16-bit integer numbers) +/// The sign-extended odd elements in vector `a` (eight signed 16-bit integer numbers) +/// are added to the sign-extended even elements in vector `b` (eight signed 16-bit integer numbers) /// producing aresult twice the size of the input operands. /// The result is written to vector (four signed 32-bit integer numbers). /// @@ -5424,8 +5424,8 @@ pub unsafe fn __msa_hadd_s_w(a: v8i16, b: v8i16) -> v4i32 { /// Vector Signed Horizontal Add /// -/// The sign-extended odd elements in vector 'a' (four signed 32-bit integer numbers) -/// are added to the sign-extended even elements in vector 'b' (four signed 32-bit integer numbers) +/// The sign-extended odd elements in vector `a` (four signed 32-bit integer numbers) +/// are added to the sign-extended even elements in vector `b` (four signed 32-bit integer numbers) /// producing aresult twice the size of the input operands. /// The result is written to vector (two signed 64-bit integer numbers). /// @@ -5438,8 +5438,8 @@ pub unsafe fn __msa_hadd_s_d(a: v4i32, b: v4i32) -> v2i64 { /// Vector Unsigned Horizontal Add /// -/// The zero-extended odd elements in vector 'a' (sixteen unsigned 8-bit integer numbers) -/// are added to the zero-extended even elements in vector 'b' (sixteen unsigned 8-bit integer numbers) +/// The zero-extended odd elements in vector `a` (sixteen unsigned 8-bit integer numbers) +/// are added to the zero-extended even elements in vector `b` (sixteen unsigned 8-bit integer numbers) /// producing aresult twice the size of the input operands. /// The result is written to vector (eight unsigned 16-bit integer numbers). /// @@ -5452,8 +5452,8 @@ pub unsafe fn __msa_hadd_u_h(a: v16u8, b: v16u8) -> v8u16 { /// Vector Unsigned Horizontal Add /// -/// The zero-extended odd elements in vector 'a' (eight unsigned 16-bit integer numbers) -/// are added to the zero-extended even elements in vector 'b' (eight unsigned 16-bit integer numbers) +/// The zero-extended odd elements in vector `a` (eight unsigned 16-bit integer numbers) +/// are added to the zero-extended even elements in vector `b` (eight unsigned 16-bit integer numbers) /// producing aresult twice the size of the input operands. /// The result is written to vector (four unsigned 32-bit integer numbers). /// @@ -5466,8 +5466,8 @@ pub unsafe fn __msa_hadd_u_w(a: v8u16, b: v8u16) -> v4u32 { /// Vector Unsigned Horizontal Add /// -/// The zero-extended odd elements in vector 'a' (four unsigned 32-bit integer numbers) -/// are added to the zero-extended even elements in vector 'b' (four unsigned 32-bit integer numbers) +/// The zero-extended odd elements in vector `a` (four unsigned 32-bit integer numbers) +/// are added to the zero-extended even elements in vector `b` (four unsigned 32-bit integer numbers) /// producing aresult twice the size of the input operands. /// The result is written to vector (two unsigned 64-bit integer numbers). /// @@ -5480,8 +5480,8 @@ pub unsafe fn __msa_hadd_u_d(a: v4u32, b: v4u32) -> v2u64 { /// Vector Signed Horizontal Subtract /// -/// The sign-extended odd elements in vector 'b' (sixteen signed 8-bit integer numbers) -/// are subtracted from the sign-extended elements in vector 'a' (sixteen signed 8-bit integer numbers) +/// The sign-extended odd elements in vector `b` (sixteen signed 8-bit integer numbers) +/// are subtracted from the sign-extended elements in vector `a` (sixteen signed 8-bit integer numbers) /// producing aresult twice the size of the input operands. /// The result is written to vector (eight signed 16-bit integer numbers). /// @@ -5494,8 +5494,8 @@ pub unsafe fn __msa_hsub_s_h(a: v16i8, b: v16i8) -> v8i16 { /// Vector Signed Horizontal Subtract /// -/// The sign-extended odd elements in vector 'b' (eight signed 16-bit integer numbers) -/// are subtracted from the sign-extended elements in vector 'a' (eight signed 16-bit integer numbers) +/// The sign-extended odd elements in vector `b` (eight signed 16-bit integer numbers) +/// are subtracted from the sign-extended elements in vector `a` (eight signed 16-bit integer numbers) /// producing aresult twice the size of the input operands. /// The result is written to vector (four signed 32-bit integer numbers). /// @@ -5508,8 +5508,8 @@ pub unsafe fn __msa_hsub_s_w(a: v8i16, b: v8i16) -> v4i32 { /// Vector Signed Horizontal Subtract /// -/// The sign-extended odd elements in vector 'b' (four signed 32-bit integer numbers) -/// are subtracted from the sign-extended elements in vector 'a' (four signed 32-bit integer numbers) +/// The sign-extended odd elements in vector `b` (four signed 32-bit integer numbers) +/// are subtracted from the sign-extended elements in vector `a` (four signed 32-bit integer numbers) /// producing aresult twice the size of the input operands. /// The result is written to vector (two signed 64-bit integer numbers). /// @@ -5522,8 +5522,8 @@ pub unsafe fn __msa_hsub_s_d(a: v4i32, b: v4i32) -> v2i64 { /// Vector Unsigned Horizontal Subtract /// -/// The zero-extended odd elements in vector 'b' (sixteen unsigned 8-bit integer numbers) -/// are subtracted from the zero-extended elements in vector 'a' (sixteen unsigned 8-bit integer numbers) +/// The zero-extended odd elements in vector `b` (sixteen unsigned 8-bit integer numbers) +/// are subtracted from the zero-extended elements in vector `a` (sixteen unsigned 8-bit integer numbers) /// producing aresult twice the size of the input operands. /// The result is written to vector (eight signed 16-bit integer numbers). /// @@ -5536,8 +5536,8 @@ pub unsafe fn __msa_hsub_u_h(a: v16u8, b: v16u8) -> v8i16 { /// Vector Unsigned Horizontal Subtract /// -/// The zero-extended odd elements in vector 'b' (eight unsigned 16-bit integer numbers) -/// are subtracted from the zero-extended elements in vector 'a' (eight unsigned 16-bit integer numbers) +/// The zero-extended odd elements in vector `b` (eight unsigned 16-bit integer numbers) +/// are subtracted from the zero-extended elements in vector `a` (eight unsigned 16-bit integer numbers) /// producing aresult twice the size of the input operands. /// The result is written to vector (four signed 32-bit integer numbers). /// @@ -5550,8 +5550,8 @@ pub unsafe fn __msa_hsub_u_w(a: v8u16, b: v8u16) -> v4i32 { /// Vector Unsigned Horizontal Subtract /// -/// The zero-extended odd elements in vector 'b' (four unsigned 32-bit integer numbers) -/// are subtracted from the zero-extended elements in vector 'a' (four unsigned 32-bit integer numbers) +/// The zero-extended odd elements in vector `b` (four unsigned 32-bit integer numbers) +/// are subtracted from the zero-extended elements in vector `a` (four unsigned 32-bit integer numbers) /// producing aresult twice the size of the input operands. /// The result is written to vector (two signed 64-bit integer numbers). /// @@ -5564,10 +5564,10 @@ pub unsafe fn __msa_hsub_u_d(a: v4u32, b: v4u32) -> v2i64 { /// Vector Interleave Even /// -/// Even elements in vectors 'a' (sixteen signed 8-bit integer numbers) -/// and vector 'b' (sixteen signed 8-bit integer numbers) are copied to the result +/// Even elements in vectors `a` (sixteen signed 8-bit integer numbers) +/// and vector `b` (sixteen signed 8-bit integer numbers) are copied to the result /// (sixteen signed 8-bit integer numbers) -/// alternating one element from 'a' with one element from 'b'. +/// alternating one element from `a` with one element from `b`. /// #[inline] #[target_feature(enable = "msa")] @@ -5578,10 +5578,10 @@ pub unsafe fn __msa_ilvev_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Interleave Even /// -/// Even elements in vectors 'a' (eight signed 16-bit integer numbers) -/// and vector 'b' (eight signed 16-bit integer numbers) are copied to the result +/// Even elements in vectors `a` (eight signed 16-bit integer numbers) +/// and vector `b` (eight signed 16-bit integer numbers) are copied to the result /// (eight signed 16-bit integer numbers) -/// alternating one element from 'a' with one element from 'b'. +/// alternating one element from `a` with one element from `b`. /// #[inline] #[target_feature(enable = "msa")] @@ -5592,10 +5592,10 @@ pub unsafe fn __msa_ilvev_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Interleave Even /// -/// Even elements in vectors 'a' (four signed 32-bit integer numbers) -/// and vector 'b' (four signed 32-bit integer numbers) are copied to the result +/// Even elements in vectors `a` (four signed 32-bit integer numbers) +/// and vector `b` (four signed 32-bit integer numbers) are copied to the result /// (four signed 32-bit integer numbers) -/// alternating one element from 'a' with one element from 'b'. +/// alternating one element from `a` with one element from `b`. /// #[inline] #[target_feature(enable = "msa")] @@ -5606,10 +5606,10 @@ pub unsafe fn __msa_ilvev_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Interleave Even /// -/// Even elements in vectors 'a' (two signed 64-bit integer numbers) -/// and vector 'b' (two signed 64-bit integer numbers) are copied to the result +/// Even elements in vectors `a` (two signed 64-bit integer numbers) +/// and vector `b` (two signed 64-bit integer numbers) are copied to the result /// (two signed 64-bit integer numbers) -/// alternating one element from 'a' with one element from 'b'. +/// alternating one element from `a` with one element from `b`. /// #[inline] #[target_feature(enable = "msa")] @@ -5620,10 +5620,10 @@ pub unsafe fn __msa_ilvev_d(a: v2i64, b: v2i64) -> v2i64 { /// Vector Interleave Left /// -/// The left half elements in vectors 'a' (sixteen signed 8-bit integer numbers) -/// and vector 'b' (sixteen signed 8-bit integer numbers) are copied to the result +/// The left half elements in vectors `a` (sixteen signed 8-bit integer numbers) +/// and vector `b` (sixteen signed 8-bit integer numbers) are copied to the result /// (sixteen signed 8-bit integer numbers) -/// alternating one element from 'a' with one element from 'b'. +/// alternating one element from `a` with one element from `b`. /// #[inline] #[target_feature(enable = "msa")] @@ -5634,10 +5634,10 @@ pub unsafe fn __msa_ilvl_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Interleave Left /// -/// The left half elements in vectors 'a' (eight signed 16-bit integer numbers) -/// and vector 'b' (eight signed 16-bit integer numbers) are copied to the result +/// The left half elements in vectors `a` (eight signed 16-bit integer numbers) +/// and vector `b` (eight signed 16-bit integer numbers) are copied to the result /// (eight signed 16-bit integer numbers) -/// alternating one element from 'a' with one element from 'b'. +/// alternating one element from `a` with one element from `b`. /// #[inline] #[target_feature(enable = "msa")] @@ -5648,10 +5648,10 @@ pub unsafe fn __msa_ilvl_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Interleave Left /// -/// The left half elements in vectors 'a' (four signed 32-bit integer numbers) -/// and vector 'b' (four signed 32-bit integer numbers) are copied to the result +/// The left half elements in vectors `a` (four signed 32-bit integer numbers) +/// and vector `b` (four signed 32-bit integer numbers) are copied to the result /// (four signed 32-bit integer numbers) -/// alternating one element from 'a' with one element from 'b'. +/// alternating one element from `a` with one element from `b`. /// #[inline] #[target_feature(enable = "msa")] @@ -5662,10 +5662,10 @@ pub unsafe fn __msa_ilvl_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Interleave Left /// -/// The left half elements in vectors 'a' (two signed 64-bit integer numbers) -/// and vector 'b' (two signed 64-bit integer numbers) are copied to the result +/// The left half elements in vectors `a` (two signed 64-bit integer numbers) +/// and vector `b` (two signed 64-bit integer numbers) are copied to the result /// (two signed 64-bit integer numbers) -/// alternating one element from 'a' with one element from 'b'. +/// alternating one element from `a` with one element from `b`. /// #[inline] #[target_feature(enable = "msa")] @@ -5676,10 +5676,10 @@ pub unsafe fn __msa_ilvl_d(a: v2i64, b: v2i64) -> v2i64 { /// Vector Interleave Odd /// -/// Odd elements in vectors 'a' (sixteen signed 8-bit integer numbers) -/// and vector 'b' (sixteen signed 8-bit integer numbers) are copied to the result +/// Odd elements in vectors `a` (sixteen signed 8-bit integer numbers) +/// and vector `b` (sixteen signed 8-bit integer numbers) are copied to the result /// (sixteen signed 8-bit integer numbers) -/// alternating one element from 'a' with one element from 'b'. +/// alternating one element from `a` with one element from `b`. /// #[inline] #[target_feature(enable = "msa")] @@ -5690,10 +5690,10 @@ pub unsafe fn __msa_ilvod_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Interleave Odd /// -/// Odd elements in vectors 'a' (eight signed 16-bit integer numbers) -/// and vector 'b' (eight signed 16-bit integer numbers) are copied to the result +/// Odd elements in vectors `a` (eight signed 16-bit integer numbers) +/// and vector `b` (eight signed 16-bit integer numbers) are copied to the result /// (eight signed 16-bit integer numbers) -/// alternating one element from 'a' with one element from 'b'. +/// alternating one element from `a` with one element from `b`. /// #[inline] #[target_feature(enable = "msa")] @@ -5704,10 +5704,10 @@ pub unsafe fn __msa_ilvod_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Interleave Odd /// -/// Odd elements in vectors 'a' (four signed 32-bit integer numbers) -/// and vector 'b' (four signed 32-bit integer numbers) are copied to the result +/// Odd elements in vectors `a` (four signed 32-bit integer numbers) +/// and vector `b` (four signed 32-bit integer numbers) are copied to the result /// (four signed 32-bit integer numbers) -/// alternating one element from 'a' with one element from 'b'. +/// alternating one element from `a` with one element from `b`. /// #[inline] #[target_feature(enable = "msa")] @@ -5718,10 +5718,10 @@ pub unsafe fn __msa_ilvod_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Interleave Odd /// -/// Odd elements in vectors 'a' (two signed 64-bit integer numbers) -/// and vector 'b' (two signed 64-bit integer numbers) are copied to the result +/// Odd elements in vectors `a` (two signed 64-bit integer numbers) +/// and vector `b` (two signed 64-bit integer numbers) are copied to the result /// (two signed 64-bit integer numbers) -/// alternating one element from 'a' with one element from 'b'. +/// alternating one element from `a` with one element from `b`. /// #[inline] #[target_feature(enable = "msa")] @@ -5732,10 +5732,10 @@ pub unsafe fn __msa_ilvod_d(a: v2i64, b: v2i64) -> v2i64 { /// Vector Interleave Right /// -/// The right half elements in vectors 'a' (sixteen signed 8-bit integer numbers) -/// and vector 'b' (sixteen signed 8-bit integer numbers) are copied to the result +/// The right half elements in vectors `a` (sixteen signed 8-bit integer numbers) +/// and vector `b` (sixteen signed 8-bit integer numbers) are copied to the result /// (sixteen signed 8-bit integer numbers) -/// alternating one element from 'a' with one element from 'b'. +/// alternating one element from `a` with one element from `b`. /// #[inline] #[target_feature(enable = "msa")] @@ -5746,10 +5746,10 @@ pub unsafe fn __msa_ilvr_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Interleave Right /// -/// The right half elements in vectors 'a' (eight signed 16-bit integer numbers) -/// and vector 'b' (eight signed 16-bit integer numbers) are copied to the result +/// The right half elements in vectors `a` (eight signed 16-bit integer numbers) +/// and vector `b` (eight signed 16-bit integer numbers) are copied to the result /// (eight signed 16-bit integer numbers) -/// alternating one element from 'a' with one element from 'b'. +/// alternating one element from `a` with one element from `b`. /// #[inline] #[target_feature(enable = "msa")] @@ -5760,10 +5760,10 @@ pub unsafe fn __msa_ilvr_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Interleave Right /// -/// The right half elements in vectors 'a' (four signed 32-bit integer numbers) -/// and vector 'b' (four signed 32-bit integer numbers) are copied to the result +/// The right half elements in vectors `a` (four signed 32-bit integer numbers) +/// and vector `b` (four signed 32-bit integer numbers) are copied to the result /// (four signed 32-bit integer numbers) -/// alternating one element from 'a' with one element from 'b'. +/// alternating one element from `a` with one element from `b`. /// #[inline] #[target_feature(enable = "msa")] @@ -5774,10 +5774,10 @@ pub unsafe fn __msa_ilvr_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Interleave Right /// -/// The right half elements in vectors 'a' (two signed 64-bit integer numbers) -/// and vector 'b' (two signed 64-bit integer numbers) are copied to the result +/// The right half elements in vectors `a` (two signed 64-bit integer numbers) +/// and vector `b` (two signed 64-bit integer numbers) are copied to the result /// (two signed 64-bit integer numbers) -/// alternating one element from 'a' with one element from 'b'. +/// alternating one element from `a` with one element from `b`. /// #[inline] #[target_feature(enable = "msa")] @@ -5788,8 +5788,8 @@ pub unsafe fn __msa_ilvr_d(a: v2i64, b: v2i64) -> v2i64 { /// GPR Insert Element /// -/// Set element imm4 in vector 'a' (sixteen signed 8-bit integer numbers) to GPR 'c' value. -/// All other elements in vector 'a' are unchanged. If the source GPR is wider than the +/// Set element imm4 in vector `a` (sixteen signed 8-bit integer numbers) to GPR `c` value. +/// All other elements in vector `a` are unchanged. If the source GPR is wider than the /// destination data format, the destination's elements will be set to the least significant bits of the GPR. /// #[inline] @@ -5807,8 +5807,8 @@ pub unsafe fn __msa_insert_b(a: v16i8, imm4: i32, c: i32) -> v16i8 { /// GPR Insert Element /// -/// Set element imm3 in vector 'a' (eight signed 16-bit integer numbers) to GPR 'c' value. -/// All other elements in vector 'a' are unchanged. If the source GPR is wider than the +/// Set element imm3 in vector `a` (eight signed 16-bit integer numbers) to GPR `c` value. +/// All other elements in vector `a` are unchanged. If the source GPR is wider than the /// destination data format, the destination's elements will be set to the least significant bits of the GPR. /// #[inline] @@ -5826,8 +5826,8 @@ pub unsafe fn __msa_insert_h(a: v8i16, imm3: i32, c: i32) -> v8i16 { /// GPR Insert Element /// -/// Set element imm2 in vector 'a' (four signed 32-bit integer numbers) to GPR 'c' value. -/// All other elements in vector 'a' are unchanged. If the source GPR is wider than the +/// Set element imm2 in vector `a` (four signed 32-bit integer numbers) to GPR `c` value. +/// All other elements in vector `a` are unchanged. If the source GPR is wider than the /// destination data format, the destination's elements will be set to the least significant bits of the GPR. /// #[inline] @@ -5845,8 +5845,8 @@ pub unsafe fn __msa_insert_w(a: v4i32, imm2: i32, c: i32) -> v4i32 { /// GPR Insert Element /// -/// Set element imm1 in vector 'a' (two signed 64-bit integer numbers) to GPR 'c' value. -/// All other elements in vector 'a' are unchanged. If the source GPR is wider than the +/// Set element imm1 in vector `a` (two signed 64-bit integer numbers) to GPR `c` value. +/// All other elements in vector `a` are unchanged. If the source GPR is wider than the /// destination data format, the destination's elements will be set to the least significant bits of the GPR. /// #[inline] @@ -5864,9 +5864,9 @@ pub unsafe fn __msa_insert_d(a: v2i64, imm1: i32, c: i64) -> v2i64 { /// Element Insert Element /// -/// Set element imm1 in the result vector 'a' (sixteen signed 8-bit integer numbers) to element 0 -/// in vector 'c' (sixteen signed 8-bit integer numbers) value. -/// All other elements in vector 'a' are unchanged. +/// Set element imm1 in the result vector `a` (sixteen signed 8-bit integer numbers) to element 0 +/// in vector `c` (sixteen signed 8-bit integer numbers) value. +/// All other elements in vector `a` are unchanged. /// #[inline] #[target_feature(enable = "msa")] @@ -5883,9 +5883,9 @@ pub unsafe fn __msa_insve_b(a: v16i8, imm4: i32, c: v16i8) -> v16i8 { /// Element Insert Element /// -/// Set element imm1 in the result vector 'a' (eight signed 16-bit integer numbers) to element 0 -/// in vector 'c' (eight signed 16-bit integer numbers) value. -/// All other elements in vector 'a' are unchanged. +/// Set element imm1 in the result vector `a` (eight signed 16-bit integer numbers) to element 0 +/// in vector `c` (eight signed 16-bit integer numbers) value. +/// All other elements in vector `a` are unchanged. /// #[inline] #[target_feature(enable = "msa")] @@ -5902,9 +5902,9 @@ pub unsafe fn __msa_insve_h(a: v8i16, imm3: i32, c: v8i16) -> v8i16 { /// Element Insert Element /// -/// Set element imm1 in the result vector 'a' (four signed 32-bit integer numbers) to element 0 -/// in vector 'c' (four signed 32-bit integer numbers) value. -/// All other elements in vector 'a' are unchanged. +/// Set element imm1 in the result vector `a` (four signed 32-bit integer numbers) to element 0 +/// in vector `c` (four signed 32-bit integer numbers) value. +/// All other elements in vector `a` are unchanged. /// #[inline] #[target_feature(enable = "msa")] @@ -5921,9 +5921,9 @@ pub unsafe fn __msa_insve_w(a: v4i32, imm2: i32, c: v4i32) -> v4i32 { /// Element Insert Element /// -/// Set element imm1 in the result vector 'a' (two signed 64-bit integer numbers) to element 0 -/// in vector 'c' (two signed 64-bit integer numbers) value. -/// All other elements in vector 'a' are unchanged. +/// Set element imm1 in the result vector `a` (two signed 64-bit integer numbers) to element 0 +/// in vector `c` (two signed 64-bit integer numbers) value. +/// All other elements in vector `a` are unchanged. /// #[inline] #[target_feature(enable = "msa")] @@ -6092,11 +6092,11 @@ pub unsafe fn __msa_ldi_d(imm_s10: i32) -> v2i64 { /// Vector Fixed-Point Multiply and Add /// -/// The products of fixed-point elements in 'b' (eight signed 16-bit integer numbers) -/// by fixed-point elements in vector 'c' (eight signed 16-bit integer numbers) -/// are added to the fixed-pointelements in vector 'a' (eight signed 16-bit integer numbers) +/// The products of fixed-point elements in `b` (eight signed 16-bit integer numbers) +/// by fixed-point elements in vector `c` (eight signed 16-bit integer numbers) +/// are added to the fixed-point elements in vector `a` (eight signed 16-bit integer numbers) /// The multiplication result is not saturated, i.e. exact (-1) * (-1) = 1 is added to the destination. -/// The saturated fixed-point results are stored to vector 'a' +/// The saturated fixed-point results are stored to vector `a` /// #[inline] #[target_feature(enable = "msa")] @@ -6107,11 +6107,11 @@ pub unsafe fn __msa_madd_q_h(a: v8i16, b: v8i16, c: v8i16) -> v8i16 { /// Vector Fixed-Point Multiply and Add /// -/// The products of fixed-point elements in 'b' (four signed 32-bit integer numbers) -/// by fixed-point elements in vector 'c' (four signed 32-bit integer numbers) -/// are added to the fixed-pointelements in vector 'a' (four signed 32-bit integer numbers) +/// The products of fixed-point elements in `b` (four signed 32-bit integer numbers) +/// by fixed-point elements in vector `c` (four signed 32-bit integer numbers) +/// are added to the fixed-point elements in vector `a` (four signed 32-bit integer numbers) /// The multiplication result is not saturated, i.e. exact (-1) * (-1) = 1 is added to the destination. -/// The saturated fixed-point results are stored to vector 'a' +/// The saturated fixed-point results are stored to vector `a` /// #[inline] #[target_feature(enable = "msa")] @@ -6122,11 +6122,11 @@ pub unsafe fn __msa_madd_q_w(a: v4i32, b: v4i32, c: v4i32) -> v4i32 { /// Vector Fixed-Point Multiply and Add Rounded /// -/// The products of fixed-point elements in 'b' (eight signed 16-bit integer numbers) -/// by fixed-point elements in vector 'c' (eight signed 16-bit integer numbers) -/// are added to the fixed-pointelements in vector 'a' (eight signed 16-bit integer numbers) +/// The products of fixed-point elements in `b` (eight signed 16-bit integer numbers) +/// by fixed-point elements in vector `c` (eight signed 16-bit integer numbers) +/// are added to the fixed-point elements in vector `a` (eight signed 16-bit integer numbers) /// The multiplication result is not saturated, i.e. exact (-1) * (-1) = 1 is added to the destination. -/// The rounded and saturated fixed-point results are stored to vector 'a' +/// The rounded and saturated fixed-point results are stored to vector `a` /// #[inline] #[target_feature(enable = "msa")] @@ -6137,11 +6137,11 @@ pub unsafe fn __msa_maddr_q_h(a: v8i16, b: v8i16, c: v8i16) -> v8i16 { /// Vector Fixed-Point Multiply and Add Rounded /// -/// The products of fixed-point elements in 'b' (four signed 32-bit integer numbers) -/// by fixed-point elements in vector 'c' (four signed 32-bit integer numbers) -/// are added to the fixed-pointelements in vector 'a' (four signed 32-bit integer numbers) +/// The products of fixed-point elements in `b` (four signed 32-bit integer numbers) +/// by fixed-point elements in vector `c` (four signed 32-bit integer numbers) +/// are added to the fixed-point elements in vector `a` (four signed 32-bit integer numbers) /// The multiplication result is not saturated, i.e. exact (-1) * (-1) = 1 is added to the destination. -/// The rounded and saturated fixed-point results are stored to vector 'a' +/// The rounded and saturated fixed-point results are stored to vector `a` /// #[inline] #[target_feature(enable = "msa")] @@ -6152,9 +6152,9 @@ pub unsafe fn __msa_maddr_q_w(a: v4i32, b: v4i32, c: v4i32) -> v4i32 { /// Vector Multiply and Add /// -/// The integer elements in vector 'b' (sixteen signed 8-bit integer numbers) -/// are multiplied by integer elements in vector 'c' (sixteen signed 8-bit integer numbers) -/// and added to the integer elements in vector 'a' (sixteen signed 8-bit integer numbers) +/// The integer elements in vector `b` (sixteen signed 8-bit integer numbers) +/// are multiplied by integer elements in vector `c` (sixteen signed 8-bit integer numbers) +/// and added to the integer elements in vector `a` (sixteen signed 8-bit integer numbers) /// The most significant half of the multiplication result is discarded. /// #[inline] @@ -6166,9 +6166,9 @@ pub unsafe fn __msa_maddv_b(a: v16i8, b: v16i8, c: v16i8) -> v16i8 { /// Vector Multiply and Add /// -/// The integer elements in vector 'b' (eight signed 16-bit integer numbers) -/// are multiplied by integer elements in vector 'c' (eight signed 16-bit integer numbers) -/// and added to the integer elements in vector 'a' (eight signed 16-bit integer numbers) +/// The integer elements in vector `b` (eight signed 16-bit integer numbers) +/// are multiplied by integer elements in vector `c` (eight signed 16-bit integer numbers) +/// and added to the integer elements in vector `a` (eight signed 16-bit integer numbers) /// The most significant half of the multiplication result is discarded. /// #[inline] @@ -6180,9 +6180,9 @@ pub unsafe fn __msa_maddv_h(a: v8i16, b: v8i16, c: v8i16) -> v8i16 { /// Vector Multiply and Add /// -/// The integer elements in vector 'b' (four signed 32-bit integer numbers) -/// are multiplied by integer elements in vector 'c' (four signed 32-bit integer numbers) -/// and added to the integer elements in vector 'a' (four signed 32-bit integer numbers) +/// The integer elements in vector `b` (four signed 32-bit integer numbers) +/// are multiplied by integer elements in vector `c` (four signed 32-bit integer numbers) +/// and added to the integer elements in vector `a` (four signed 32-bit integer numbers) /// The most significant half of the multiplication result is discarded. /// #[inline] @@ -6194,9 +6194,9 @@ pub unsafe fn __msa_maddv_w(a: v4i32, b: v4i32, c: v4i32) -> v4i32 { /// Vector Multiply and Add /// -/// The integer elements in vector 'b' (two signed 64-bit integer numbers) -/// are multiplied by integer elements in vector 'c' (two signed 64-bit integer numbers) -/// and added to the integer elements in vector 'a' (two signed 64-bit integer numbers) +/// The integer elements in vector `b` (two signed 64-bit integer numbers) +/// are multiplied by integer elements in vector `c` (two signed 64-bit integer numbers) +/// and added to the integer elements in vector `a` (two signed 64-bit integer numbers) /// The most significant half of the multiplication result is discarded. /// #[inline] @@ -6209,8 +6209,8 @@ pub unsafe fn __msa_maddv_d(a: v2i64, b: v2i64, c: v2i64) -> v2i64 { /// Vector Maximum Based on Absolute Values /// /// The value with the largest magnitude, i.e. absolute value, between corresponding -/// signed elements in vector 'a'(sixteen signed 8-bit integer numbers) and -/// 'b'(sixteen signed 8-bit integer numbers) are written to vector +/// signed elements in vector `a` (sixteen signed 8-bit integer numbers) and +/// `b` (sixteen signed 8-bit integer numbers) are written to vector /// (sixteen signed 8-bit integer numbers) /// #[inline] @@ -6223,8 +6223,8 @@ pub unsafe fn __msa_max_a_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Maximum Based on Absolute Values /// /// The value with the largest magnitude, i.e. absolute value, between corresponding -/// signed elements in vector 'a'(eight signed 16-bit integer numbers) and -/// 'b'(eight signed 16-bit integer numbers) are written to vector +/// signed elements in vector `a` (eight signed 16-bit integer numbers) and +/// `b` (eight signed 16-bit integer numbers) are written to vector /// (eight signed 16-bit integer numbers) /// #[inline] @@ -6237,8 +6237,8 @@ pub unsafe fn __msa_max_a_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Maximum Based on Absolute Values /// /// The value with the largest magnitude, i.e. absolute value, between corresponding -/// signed elements in vector 'a'(four signed 32-bit integer numbers) and -/// 'b'(four signed 32-bit integer numbers) are written to vector +/// signed elements in vector `a` (four signed 32-bit integer numbers) and +/// `b` (four signed 32-bit integer numbers) are written to vector /// (four signed 32-bit integer numbers) /// #[inline] @@ -6251,8 +6251,8 @@ pub unsafe fn __msa_max_a_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Maximum Based on Absolute Values /// /// The value with the largest magnitude, i.e. absolute value, between corresponding -/// signed elements in vector 'a'(two signed 64-bit integer numbers) and -/// 'b'(two signed 64-bit integer numbers) are written to vector +/// signed elements in vector `a` (two signed 64-bit integer numbers) and +/// `b` (two signed 64-bit integer numbers) are written to vector /// (two signed 64-bit integer numbers) /// #[inline] @@ -6264,8 +6264,8 @@ pub unsafe fn __msa_max_a_d(a: v2i64, b: v2i64) -> v2i64 { /// Vector Signed Maximum /// -/// Maximum values between signed elements in vector 'a'(sixteen signed 8-bit integer numbers) -/// and signed elements in vector 'b'(sixteen signed 8-bit integer numbers) are written to vector +/// Maximum values between signed elements in vector `a` (sixteen signed 8-bit integer numbers) +/// and signed elements in vector `b` (sixteen signed 8-bit integer numbers) are written to vector /// (sixteen signed 8-bit integer numbers) /// #[inline] @@ -6277,8 +6277,8 @@ pub unsafe fn __msa_max_s_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Signed Maximum /// -/// Maximum values between signed elements in vector 'a'(eight signed 16-bit integer numbers) -/// and signed elements in vector 'b'(eight signed 16-bit integer numbers) are written to vector +/// Maximum values between signed elements in vector `a` (eight signed 16-bit integer numbers) +/// and signed elements in vector `b` (eight signed 16-bit integer numbers) are written to vector /// (eight signed 16-bit integer numbers) /// #[inline] @@ -6290,8 +6290,8 @@ pub unsafe fn __msa_max_s_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Signed Maximum /// -/// Maximum values between signed elements in vector 'a'(four signed 32-bit integer numbers) -/// and signed elements in vector 'b'(four signed 32-bit integer numbers) are written to vector +/// Maximum values between signed elements in vector `a` (four signed 32-bit integer numbers) +/// and signed elements in vector `b` (four signed 32-bit integer numbers) are written to vector /// (four signed 32-bit integer numbers) /// #[inline] @@ -6303,8 +6303,8 @@ pub unsafe fn __msa_max_s_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Signed Maximum /// -/// Maximum values between signed elements in vector 'a'(two signed 64-bit integer numbers) -/// and signed elements in vector 'b'(two signed 64-bit integer numbers) are written to vector +/// Maximum values between signed elements in vector `a` (two signed 64-bit integer numbers) +/// and signed elements in vector `b` (two signed 64-bit integer numbers) are written to vector /// (two signed 64-bit integer numbers) /// #[inline] @@ -6316,8 +6316,8 @@ pub unsafe fn __msa_max_s_d(a: v2i64, b: v2i64) -> v2i64 { /// Vector Unsigned Maximum /// -/// Maximum values between unsigned elements in vector 'a'(sixteen unsigned 8-bit integer numbers) -/// and unsigned elements in vector 'b'(sixteen unsigned 8-bit integer numbers) are written to vector +/// Maximum values between unsigned elements in vector `a` (sixteen unsigned 8-bit integer numbers) +/// and unsigned elements in vector `b` (sixteen unsigned 8-bit integer numbers) are written to vector /// (sixteen unsigned 8-bit integer numbers) /// #[inline] @@ -6329,8 +6329,8 @@ pub unsafe fn __msa_max_u_b(a: v16u8, b: v16u8) -> v16u8 { /// Vector Unsigned Maximum /// -/// Maximum values between unsigned elements in vector 'a'(eight unsigned 16-bit integer numbers) -/// and unsigned elements in vector 'b'(eight unsigned 16-bit integer numbers) are written to vector +/// Maximum values between unsigned elements in vector `a` (eight unsigned 16-bit integer numbers) +/// and unsigned elements in vector `b` (eight unsigned 16-bit integer numbers) are written to vector /// (eight unsigned 16-bit integer numbers) /// #[inline] @@ -6342,8 +6342,8 @@ pub unsafe fn __msa_max_u_h(a: v8u16, b: v8u16) -> v8u16 { /// Vector Unsigned Maximum /// -/// Maximum values between unsigned elements in vector 'a'(four unsigned 32-bit integer numbers) -/// and unsigned elements in vector 'b'(four unsigned 32-bit integer numbers) are written to vector +/// Maximum values between unsigned elements in vector `a` (four unsigned 32-bit integer numbers) +/// and unsigned elements in vector `b` (four unsigned 32-bit integer numbers) are written to vector /// (four unsigned 32-bit integer numbers) /// #[inline] @@ -6355,8 +6355,8 @@ pub unsafe fn __msa_max_u_w(a: v4u32, b: v4u32) -> v4u32 { /// Vector Unsigned Maximum /// -/// Maximum values between unsigned elements in vector 'a'(two unsigned 64-bit integer numbers) -/// and unsigned elements in vector 'b'(two unsigned 64-bit integer numbers) are written to vector +/// Maximum values between unsigned elements in vector `a` (two unsigned 64-bit integer numbers) +/// and unsigned elements in vector `b` (two unsigned 64-bit integer numbers) are written to vector /// (two unsigned 64-bit integer numbers) /// #[inline] @@ -6368,7 +6368,7 @@ pub unsafe fn __msa_max_u_d(a: v2u64, b: v2u64) -> v2u64 { /// Immediate Signed Maximum /// -/// Maximum values between signed elements in vector 'a'(sixteen signed 8-bit integer numbers) +/// Maximum values between signed elements in vector `a` (sixteen signed 8-bit integer numbers) /// and the 5-bit signed immediate imm_s5 are written to vector /// (sixteen signed 8-bit integer numbers) /// @@ -6387,7 +6387,7 @@ pub unsafe fn __msa_maxi_s_b(a: v16i8, imm_s5: i32) -> v16i8 { /// Immediate Signed Maximum /// -/// Maximum values between signed elements in vector 'a'(eight signed 16-bit integer numbers) +/// Maximum values between signed elements in vector `a` (eight signed 16-bit integer numbers) /// and the 5-bit signed immediate imm_s5 are written to vector /// (eight signed 16-bit integer numbers) /// @@ -6406,7 +6406,7 @@ pub unsafe fn __msa_maxi_s_h(a: v8i16, imm_s5: i32) -> v8i16 { /// Immediate Signed Maximum /// -/// Maximum values between signed elements in vector 'a'(four signed 32-bit integer numbers) +/// Maximum values between signed elements in vector `a` (four signed 32-bit integer numbers) /// and the 5-bit signed immediate imm_s5 are written to vector /// (four signed 32-bit integer numbers) /// @@ -6425,7 +6425,7 @@ pub unsafe fn __msa_maxi_s_w(a: v4i32, imm_s5: i32) -> v4i32 { /// Immediate Signed Maximum /// -/// Maximum values between signed elements in vector 'a'(two signed 64-bit integer numbers) +/// Maximum values between signed elements in vector `a` (two signed 64-bit integer numbers) /// and the 5-bit signed immediate imm_s5 are written to vector /// (two signed 64-bit integer numbers) /// @@ -6444,7 +6444,7 @@ pub unsafe fn __msa_maxi_s_d(a: v2i64, imm_s5: i32) -> v2i64 { /// Immediate Unsigned Maximum /// -/// Maximum values between unsigned elements in vector 'a'(sixteen unsigned 8-bit integer numbers) +/// Maximum values between unsigned elements in vector `a` (sixteen unsigned 8-bit integer numbers) /// and the 5-bit unsigned immediate imm5 are written to vector /// (sixteen unsigned 8-bit integer numbers) /// @@ -6463,7 +6463,7 @@ pub unsafe fn __msa_maxi_u_b(a: v16u8, imm5: i32) -> v16u8 { /// Immediate Unsigned Maximum /// -/// Maximum values between unsigned elements in vector 'a'(eight unsigned 16-bit integer numbers) +/// Maximum values between unsigned elements in vector `a` (eight unsigned 16-bit integer numbers) /// and the 5-bit unsigned immediate imm5 are written to vector /// (eight unsigned 16-bit integer numbers) /// @@ -6482,7 +6482,7 @@ pub unsafe fn __msa_maxi_u_h(a: v8u16, imm5: i32) -> v8u16 { /// Immediate Unsigned Maximum /// -/// Maximum values between unsigned elements in vector 'a'(four unsigned 32-bit integer numbers) +/// Maximum values between unsigned elements in vector `a` (four unsigned 32-bit integer numbers) /// and the 5-bit unsigned immediate imm5 are written to vector /// (four unsigned 32-bit integer numbers) /// @@ -6501,7 +6501,7 @@ pub unsafe fn __msa_maxi_u_w(a: v4u32, imm5: i32) -> v4u32 { /// Immediate Unsigned Maximum /// -/// Maximum values between unsigned elements in vector 'a'(two unsigned 64-bit integer numbers) +/// Maximum values between unsigned elements in vector `a` (two unsigned 64-bit integer numbers) /// and the 5-bit unsigned immediate imm5 are written to vector /// (two unsigned 64-bit integer numbers) /// @@ -6521,8 +6521,8 @@ pub unsafe fn __msa_maxi_u_d(a: v2u64, imm5: i32) -> v2u64 { /// Vector Minimum Based on Absolute Value /// /// The value with the smallest magnitude, i.e. absolute value, between corresponding -/// signed elements in vector 'a'(sixteen signed 8-bit integer numbers) and -/// 'b'(sixteen signed 8-bit integer numbers) are written to vector +/// signed elements in vector `a` (sixteen signed 8-bit integer numbers) and +/// `b` (sixteen signed 8-bit integer numbers) are written to vector /// (sixteen signed 8-bit integer numbers) /// #[inline] @@ -6535,8 +6535,8 @@ pub unsafe fn __msa_min_a_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Minimum Based on Absolute Value /// /// The value with the smallest magnitude, i.e. absolute value, between corresponding -/// signed elements in vector 'a'(eight signed 16-bit integer numbers) and -/// 'b'(eight signed 16-bit integer numbers) are written to vector +/// signed elements in vector `a` (eight signed 16-bit integer numbers) and +/// `b` (eight signed 16-bit integer numbers) are written to vector /// (eight signed 16-bit integer numbers) /// #[inline] @@ -6549,8 +6549,8 @@ pub unsafe fn __msa_min_a_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Minimum Based on Absolute Value /// /// The value with the smallest magnitude, i.e. absolute value, between corresponding -/// signed elements in vector 'a'(four signed 32-bit integer numbers) and -/// 'b'(four signed 32-bit integer numbers) are written to vector +/// signed elements in vector `a` (four signed 32-bit integer numbers) and +/// `b` (four signed 32-bit integer numbers) are written to vector /// (four signed 32-bit integer numbers) /// #[inline] @@ -6563,8 +6563,8 @@ pub unsafe fn __msa_min_a_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Minimum Based on Absolute Value /// /// The value with the smallest magnitude, i.e. absolute value, between corresponding -/// signed elements in vector 'a'(two signed 64-bit integer numbers) and -/// 'b'(two signed 64-bit integer numbers) are written to vector +/// signed elements in vector `a` (two signed 64-bit integer numbers) and +/// `b` (two signed 64-bit integer numbers) are written to vector /// (two signed 64-bit integer numbers) /// #[inline] @@ -6576,8 +6576,8 @@ pub unsafe fn __msa_min_a_d(a: v2i64, b: v2i64) -> v2i64 { /// Vector Signed Minimum /// -/// Minimum values between signed elements in vector 'a'(sixteen signed 8-bit integer numbers) -/// and signed elements in vector 'b'(sixteen signed 8-bit integer numbers) are written to vector +/// Minimum values between signed elements in vector `a` (sixteen signed 8-bit integer numbers) +/// and signed elements in vector `b` (sixteen signed 8-bit integer numbers) are written to vector /// (sixteen signed 8-bit integer numbers) /// #[inline] @@ -6589,8 +6589,8 @@ pub unsafe fn __msa_min_s_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Signed Minimum /// -/// Minimum values between signed elements in vector 'a'(eight signed 16-bit integer numbers) -/// and signed elements in vector 'b'(eight signed 16-bit integer numbers) are written to vector +/// Minimum values between signed elements in vector `a` (eight signed 16-bit integer numbers) +/// and signed elements in vector `b` (eight signed 16-bit integer numbers) are written to vector /// (eight signed 16-bit integer numbers) /// #[inline] @@ -6602,8 +6602,8 @@ pub unsafe fn __msa_min_s_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Signed Minimum /// -/// Minimum values between signed elements in vector 'a'(four signed 32-bit integer numbers) -/// and signed elements in vector 'b'(four signed 32-bit integer numbers) are written to vector +/// Minimum values between signed elements in vector `a` (four signed 32-bit integer numbers) +/// and signed elements in vector `b` (four signed 32-bit integer numbers) are written to vector /// (four signed 32-bit integer numbers) /// #[inline] @@ -6615,8 +6615,8 @@ pub unsafe fn __msa_min_s_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Signed Minimum /// -/// Minimum values between signed elements in vector 'a'(two signed 64-bit integer numbers) -/// and signed elements in vector 'b'(two signed 64-bit integer numbers) are written to vector +/// Minimum values between signed elements in vector `a` (two signed 64-bit integer numbers) +/// and signed elements in vector `b` (two signed 64-bit integer numbers) are written to vector /// (two signed 64-bit integer numbers) /// #[inline] @@ -6628,7 +6628,7 @@ pub unsafe fn __msa_min_s_d(a: v2i64, b: v2i64) -> v2i64 { /// Immediate Signed Minimum /// -/// Minimum values between signed elements in vector 'a'(sixteen signed 8-bit integer numbers) +/// Minimum values between signed elements in vector `a` (sixteen signed 8-bit integer numbers) /// and the 5-bit signed immediate imm_s5 are written to vector /// (sixteen signed 8-bit integer numbers) /// @@ -6647,7 +6647,7 @@ pub unsafe fn __msa_mini_s_b(a: v16i8, imm_s5: i32) -> v16i8 { /// Immediate Signed Minimum /// -/// Minimum values between signed elements in vector 'a'(eight signed 16-bit integer numbers) +/// Minimum values between signed elements in vector `a` (eight signed 16-bit integer numbers) /// and the 5-bit signed immediate imm_s5 are written to vector /// (eight signed 16-bit integer numbers) /// @@ -6666,7 +6666,7 @@ pub unsafe fn __msa_mini_s_h(a: v8i16, imm_s5: i32) -> v8i16 { /// Immediate Signed Minimum /// -/// Minimum values between signed elements in vector 'a'(four signed 32-bit integer numbers) +/// Minimum values between signed elements in vector `a` (four signed 32-bit integer numbers) /// and the 5-bit signed immediate imm_s5 are written to vector /// (four signed 32-bit integer numbers) /// @@ -6685,7 +6685,7 @@ pub unsafe fn __msa_mini_s_w(a: v4i32, imm_s5: i32) -> v4i32 { /// Immediate Signed Minimum /// -/// Minimum values between signed elements in vector 'a'(two signed 64-bit integer numbers) +/// Minimum values between signed elements in vector `a` (two signed 64-bit integer numbers) /// and the 5-bit signed immediate imm_s5 are written to vector /// (two signed 64-bit integer numbers) /// @@ -6704,8 +6704,8 @@ pub unsafe fn __msa_mini_s_d(a: v2i64, imm_s5: i32) -> v2i64 { /// Vector Unsigned Minimum /// -/// Minimum values between unsigned elements in vector 'a'(sixteen unsigned 8-bit integer numbers) -/// and unsigned elements in vector 'b'(sixteen unsigned 8-bit integer numbers) are written to vector +/// Minimum values between unsigned elements in vector `a` (sixteen unsigned 8-bit integer numbers) +/// and unsigned elements in vector `b` (sixteen unsigned 8-bit integer numbers) are written to vector /// (sixteen unsigned 8-bit integer numbers) /// #[inline] @@ -6717,8 +6717,8 @@ pub unsafe fn __msa_min_u_b(a: v16u8, b: v16u8) -> v16u8 { /// Vector Unsigned Minimum /// -/// Minimum values between unsigned elements in vector 'a'(eight unsigned 16-bit integer numbers) -/// and unsigned elements in vector 'b'(eight unsigned 16-bit integer numbers) are written to vector +/// Minimum values between unsigned elements in vector `a` (eight unsigned 16-bit integer numbers) +/// and unsigned elements in vector `b` (eight unsigned 16-bit integer numbers) are written to vector /// (eight unsigned 16-bit integer numbers) /// #[inline] @@ -6730,8 +6730,8 @@ pub unsafe fn __msa_min_u_h(a: v8u16, b: v8u16) -> v8u16 { /// Vector Unsigned Minimum /// -/// Minimum values between unsigned elements in vector 'a'(four unsigned 32-bit integer numbers) -/// and unsigned elements in vector 'b'(four unsigned 32-bit integer numbers) are written to vector +/// Minimum values between unsigned elements in vector `a` (four unsigned 32-bit integer numbers) +/// and unsigned elements in vector `b` (four unsigned 32-bit integer numbers) are written to vector /// (four unsigned 32-bit integer numbers) /// #[inline] @@ -6743,8 +6743,8 @@ pub unsafe fn __msa_min_u_w(a: v4u32, b: v4u32) -> v4u32 { /// Vector Unsigned Minimum /// -/// Minimum values between unsigned elements in vector 'a'(two unsigned 64-bit integer numbers) -/// and unsigned elements in vector 'b'(two unsigned 64-bit integer numbers) are written to vector +/// Minimum values between unsigned elements in vector `a` (two unsigned 64-bit integer numbers) +/// and unsigned elements in vector `b` (two unsigned 64-bit integer numbers) are written to vector /// (two unsigned 64-bit integer numbers) /// #[inline] @@ -6756,7 +6756,7 @@ pub unsafe fn __msa_min_u_d(a: v2u64, b: v2u64) -> v2u64 { /// Immediate Unsigned Minimum /// -/// Minimum values between unsigned elements in vector 'a'(sixteen unsigned 8-bit integer numbers) +/// Minimum values between unsigned elements in vector `a` (sixteen unsigned 8-bit integer numbers) /// and the 5-bit unsigned immediate imm5 are written to vector /// (sixteen unsigned 8-bit integer numbers) /// @@ -6775,7 +6775,7 @@ pub unsafe fn __msa_mini_u_b(a: v16u8, imm5: i32) -> v16u8 { /// Immediate Unsigned Minimum /// -/// Minimum values between unsigned elements in vector 'a'(eight unsigned 16-bit integer numbers) +/// Minimum values between unsigned elements in vector `a` (eight unsigned 16-bit integer numbers) /// and the 5-bit unsigned immediate imm5 are written to vector /// (eight unsigned 16-bit integer numbers) /// @@ -6794,7 +6794,7 @@ pub unsafe fn __msa_mini_u_h(a: v8u16, imm5: i32) -> v8u16 { /// Immediate Unsigned Minimum /// -/// Minimum values between unsigned elements in vector 'a'(four unsigned 32-bit integer numbers) +/// Minimum values between unsigned elements in vector `a` (four unsigned 32-bit integer numbers) /// and the 5-bit unsigned immediate imm5 are written to vector /// (four unsigned 32-bit integer numbers) /// @@ -6813,7 +6813,7 @@ pub unsafe fn __msa_mini_u_w(a: v4u32, imm5: i32) -> v4u32 { /// Immediate Unsigned Minimum /// -/// Minimum values between unsigned elements in vector 'a'(two unsigned 64-bit integer numbers) +/// Minimum values between unsigned elements in vector `a` (two unsigned 64-bit integer numbers) /// and the 5-bit unsigned immediate imm5 are written to vector /// (two unsigned 64-bit integer numbers) /// @@ -6832,8 +6832,8 @@ pub unsafe fn __msa_mini_u_d(a: v2u64, imm5: i32) -> v2u64 { /// Vector Signed Modulo /// -/// The signed integer elements in vector 'a'(sixteen signed 8-bit integer numbers) -/// are divided by signed integer elements in vector 'b'(sixteen signed 8-bit integer numbers) +/// The signed integer elements in vector `a` (sixteen signed 8-bit integer numbers) +/// are divided by signed integer elements in vector `b` (sixteen signed 8-bit integer numbers) /// The remainder of thesame sign as the dividend is written to vector /// (sixteen signed 8-bit integer numbers).If a divisor element vectorwt is zero, /// the result value is UNPREDICTABLE. @@ -6847,10 +6847,10 @@ pub unsafe fn __msa_mod_s_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Signed Modulo /// -/// The signed integer elements in vector 'a'(eight signed 16-bit integer numbers) -/// are divided by signed integer elements in vector 'b'(eight signed 16-bit integer numbers) -/// The remainder of thesame sign as the dividend is written to vector -/// (eight signed 16-bit integer numbers).If a divisor element vectorwt is zero, +/// The signed integer elements in vector `a` (eight signed 16-bit integer numbers) +/// are divided by signed integer elements in vector `b` (eight signed 16-bit integer numbers) +/// The remainder of the same sign as the dividend is written to vector +/// (eight signed 16-bit integer numbers). If a divisor element vectorwt is zero, /// the result value is UNPREDICTABLE. /// #[inline] @@ -6862,10 +6862,10 @@ pub unsafe fn __msa_mod_s_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Signed Modulo /// -/// The signed integer elements in vector 'a'(four signed 32-bit integer numbers) -/// are divided by signed integer elements in vector 'b'(four signed 32-bit integer numbers) -/// The remainder of thesame sign as the dividend is written to vector -/// (four signed 32-bit integer numbers).If a divisor element vectorwt is zero, +/// The signed integer elements in vector `a` (four signed 32-bit integer numbers) +/// are divided by signed integer elements in vector `b` (four signed 32-bit integer numbers) +/// The remainder of the same sign as the dividend is written to vector +/// (four signed 32-bit integer numbers). If a divisor element vectorwt is zero, /// the result value is UNPREDICTABLE. /// #[inline] @@ -6877,10 +6877,10 @@ pub unsafe fn __msa_mod_s_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Signed Modulo /// -/// The signed integer elements in vector 'a'(two signed 64-bit integer numbers) -/// are divided by signed integer elements in vector 'b'(two signed 64-bit integer numbers) -/// The remainder of thesame sign as the dividend is written to vector -/// (two signed 64-bit integer numbers).If a divisor element vectorwt is zero, +/// The signed integer elements in vector `a` (two signed 64-bit integer numbers) +/// are divided by signed integer elements in vector `b` (two signed 64-bit integer numbers). +/// The remainder of the same sign as the dividend is written to vector +/// (two signed 64-bit integer numbers). If a divisor element vectorwt is zero, /// the result value is UNPREDICTABLE. /// #[inline] @@ -6892,10 +6892,10 @@ pub unsafe fn __msa_mod_s_d(a: v2i64, b: v2i64) -> v2i64 { /// Vector Unsigned Modulo /// -/// The unsigned integer elements in vector 'a'(sixteen unsigned 8-bit integer numbers) -/// are divided by unsigned integer elements in vector 'b'(sixteen unsigned 8-bit integer numbers) -/// The remainder of thesame sign as the dividend is written to vector -/// (sixteen unsigned 8-bit integer numbers).If a divisor element vectorwt is zero, +/// The unsigned integer elements in vector `a` (sixteen unsigned 8-bit integer numbers) +/// are divided by unsigned integer elements in vector `b` (sixteen unsigned 8-bit integer numbers). +/// The remainder of the same sign as the dividend is written to vector +/// (sixteen unsigned 8-bit integer numbers). If a divisor element vectorwt is zero, /// the result value is UNPREDICTABLE. /// #[inline] @@ -6907,8 +6907,8 @@ pub unsafe fn __msa_mod_u_b(a: v16u8, b: v16u8) -> v16u8 { /// Vector Unsigned Modulo /// -/// The unsigned integer elements in vector 'a'(eight unsigned 16-bit integer numbers) -/// are divided by unsigned integer elements in vector 'b'(eight unsigned 16-bit integer numbers) +/// The unsigned integer elements in vector `a` (eight unsigned 16-bit integer numbers) +/// are divided by unsigned integer elements in vector `b` (eight unsigned 16-bit integer numbers). /// The remainder of thesame sign as the dividend is written to vector /// (eight unsigned 16-bit integer numbers).If a divisor element vectorwt is zero, /// the result value is UNPREDICTABLE. @@ -6922,10 +6922,10 @@ pub unsafe fn __msa_mod_u_h(a: v8u16, b: v8u16) -> v8u16 { /// Vector Unsigned Modulo /// -/// The unsigned integer elements in vector 'a'(four unsigned 32-bit integer numbers) -/// are divided by unsigned integer elements in vector 'b'(four unsigned 32-bit integer numbers) +/// The unsigned integer elements in vector `a` (four unsigned 32-bit integer numbers) +/// are divided by unsigned integer elements in vector `b` (four unsigned 32-bit integer numbers). /// The remainder of thesame sign as the dividend is written to vector -/// (four unsigned 32-bit integer numbers).If a divisor element vectorwt is zero, +/// (four unsigned 32-bit integer numbers). If a divisor element vectorwt is zero, /// the result value is UNPREDICTABLE. /// #[inline] @@ -6937,8 +6937,8 @@ pub unsafe fn __msa_mod_u_w(a: v4u32, b: v4u32) -> v4u32 { /// Vector Unsigned Modulo /// -/// The unsigned integer elements in vector 'a'(two unsigned 64-bit integer numbers) -/// are divided by unsigned integer elements in vector 'b'(two unsigned 64-bit integer numbers) +/// The unsigned integer elements in vector `a` (two unsigned 64-bit integer numbers) +/// are divided by unsigned integer elements in vector `b` (two unsigned 64-bit integer numbers). /// The remainder of thesame sign as the dividend is written to vector /// (two unsigned 64-bit integer numbers).If a divisor element vectorwt is zero, /// the result value is UNPREDICTABLE. @@ -6952,7 +6952,7 @@ pub unsafe fn __msa_mod_u_d(a: v2u64, b: v2u64) -> v2u64 { /// Vector Move /// -/// Copy all WRLEN bits in vector 'a'(eight signed 16-bit integer numbers) +/// Copy all WRLEN bits in vector `a` (eight signed 16-bit integer numbers) /// to vector (eight signed 16-bit integer numbers). /// #[inline] @@ -6964,12 +6964,12 @@ pub unsafe fn __msa_move_v(a: v16i8) -> v16i8 { /// Vector Fixed-Point Multiply and Subtract /// -/// The product of fixed-point elements in vector 'c'(eight signed 16-bit integer numbers) -/// by fixed-point elements in vector 'b'(eight signed 16-bit integer numbers) -/// are subtracted from the fixed-point elements in vector 'a' -/// (eight signed 16-bit integer numbers).The multiplication result is not saturated, +/// The product of fixed-point elements in vector `c` (eight signed 16-bit integer numbers) +/// by fixed-point elements in vector `b` (eight signed 16-bit integer numbers) +/// are subtracted from the fixed-point elements in vector `a` +/// (eight signed 16-bit integer numbers). The multiplication result is not saturated, /// i.e. exact (-1) * (-1) = 1 is subtracted from the destination. -/// The saturated fixed-point results are stored back to vector 'a' +/// The saturated fixed-point results are stored back to vector `a`. /// #[inline] #[target_feature(enable = "msa")] @@ -6980,12 +6980,12 @@ pub unsafe fn __msa_msub_q_h(a: v8i16, b: v8i16, c: v8i16) -> v8i16 { /// Vector Fixed-Point Multiply and Subtract /// -/// The product of fixed-point elements in vector 'c'(four signed 32-bit integer numbers) -/// by fixed-point elements in vector 'b'(four signed 32-bit integer numbers) -/// are subtracted from the fixed-point elements in vector 'a' -/// (four signed 32-bit integer numbers).The multiplication result is not saturated, +/// The product of fixed-point elements in vector `c` (four signed 32-bit integer numbers) +/// by fixed-point elements in vector `b` (four signed 32-bit integer numbers) +/// are subtracted from the fixed-point elements in vector `a` +/// (four signed 32-bit integer numbers). The multiplication result is not saturated, /// i.e. exact (-1) * (-1) = 1 is subtracted from the destination. -/// The saturated fixed-point results are stored back to vector 'a' +/// The saturated fixed-point results are stored back to vector `a`. /// #[inline] #[target_feature(enable = "msa")] @@ -6996,12 +6996,12 @@ pub unsafe fn __msa_msub_q_w(a: v4i32, b: v4i32, c: v4i32) -> v4i32 { /// Vector Fixed-Point Multiply and Subtract Rounded /// -/// The product of fixed-point elements in vector 'c'(eight signed 16-bit integer numbers) -/// by fixed-point elements in vector 'b'(eight signed 16-bit integer numbers) -/// are subtracted from the fixed-point elements in vector 'a' -/// (eight signed 16-bit integer numbers).The multiplication result is not saturated, +/// The product of fixed-point elements in vector `c` (eight signed 16-bit integer numbers) +/// by fixed-point elements in vector `b` (eight signed 16-bit integer numbers) +/// are subtracted from the fixed-point elements in vector `a` +/// (eight signed 16-bit integer numbers). The multiplication result is not saturated, /// i.e. exact (-1) * (-1) = 1 is subtracted from the destination. -/// The rounded and saturated fixed-point results are stored back to vector 'a' +/// The rounded and saturated fixed-point results are stored back to vector `a`. /// #[inline] #[target_feature(enable = "msa")] @@ -7012,12 +7012,12 @@ pub unsafe fn __msa_msubr_q_h(a: v8i16, b: v8i16, c: v8i16) -> v8i16 { /// Vector Fixed-Point Multiply and Subtract Rounded /// -/// The product of fixed-point elements in vector 'c'(four signed 32-bit integer numbers) -/// by fixed-point elements in vector 'b'(four signed 32-bit integer numbers) -/// are subtracted from the fixed-point elements in vector 'a' -/// (four signed 32-bit integer numbers).The multiplication result is not saturated, +/// The product of fixed-point elements in vector `c` (four signed 32-bit integer numbers) +/// by fixed-point elements in vector `b` (four signed 32-bit integer numbers) +/// are subtracted from the fixed-point elements in vector `a` +/// (four signed 32-bit integer numbers). The multiplication result is not saturated, /// i.e. exact (-1) * (-1) = 1 is subtracted from the destination. -/// The rounded and saturated fixed-point results are stored back to vector 'a' +/// The rounded and saturated fixed-point results are stored back to vector `a`. /// #[inline] #[target_feature(enable = "msa")] @@ -7028,9 +7028,9 @@ pub unsafe fn __msa_msubr_q_w(a: v4i32, b: v4i32, c: v4i32) -> v4i32 { /// Vector Multiply and Subtract /// -/// The integer elements in vector 'c'(sixteen signed 8-bit integer numbers) -/// are multiplied by integer elements in vector 'b'(sixteen signed 8-bit integer numbers) -/// and subtracted from the integer elements in vector 'a'(sixteen signed 8-bit integer numbers) +/// The integer elements in vector `c` (sixteen signed 8-bit integer numbers) +/// are multiplied by integer elements in vector `b` (sixteen signed 8-bit integer numbers) +/// and subtracted from the integer elements in vector `a` (sixteen signed 8-bit integer numbers). /// The most significant half of the multiplication result is discarded. /// #[inline] @@ -7042,9 +7042,9 @@ pub unsafe fn __msa_msubv_b(a: v16i8, b: v16i8, c: v16i8) -> v16i8 { /// Vector Multiply and Subtract /// -/// The integer elements in vector 'c'(eight signed 16-bit integer numbers) -/// are multiplied by integer elements in vector 'b'(eight signed 16-bit integer numbers) -/// and subtracted from the integer elements in vector 'a'(eight signed 16-bit integer numbers) +/// The integer elements in vector `c` (eight signed 16-bit integer numbers) +/// are multiplied by integer elements in vector `b` (eight signed 16-bit integer numbers) +/// and subtracted from the integer elements in vector `a` (eight signed 16-bit integer numbers). /// The most significant half of the multiplication result is discarded. /// #[inline] @@ -7056,9 +7056,9 @@ pub unsafe fn __msa_msubv_h(a: v8i16, b: v8i16, c: v8i16) -> v8i16 { /// Vector Multiply and Subtract /// -/// The integer elements in vector 'c'(four signed 32-bit integer numbers) -/// are multiplied by integer elements in vector 'b'(four signed 32-bit integer numbers) -/// and subtracted from the integer elements in vector 'a'(four signed 32-bit integer numbers) +/// The integer elements in vector `c` (four signed 32-bit integer numbers) +/// are multiplied by integer elements in vector `b` (four signed 32-bit integer numbers) +/// and subtracted from the integer elements in vector `a` (four signed 32-bit integer numbers). /// The most significant half of the multiplication result is discarded. /// #[inline] @@ -7070,9 +7070,9 @@ pub unsafe fn __msa_msubv_w(a: v4i32, b: v4i32, c: v4i32) -> v4i32 { /// Vector Multiply and Subtract /// -/// The integer elements in vector 'c'(two signed 64-bit integer numbers) -/// are multiplied by integer elements in vector 'b'(two signed 64-bit integer numbers) -/// and subtracted from the integer elements in vector 'a'(two signed 64-bit integer numbers) +/// The integer elements in vector `c` (two signed 64-bit integer numbers) +/// are multiplied by integer elements in vector `b` (two signed 64-bit integer numbers) +/// and subtracted from the integer elements in vector `a` (two signed 64-bit integer numbers). /// The most significant half of the multiplication result is discarded. /// #[inline] @@ -7084,9 +7084,9 @@ pub unsafe fn __msa_msubv_d(a: v2i64, b: v2i64, c: v2i64) -> v2i64 { /// Vector Fixed-Point Multiply /// -/// The fixed-point elements in vector 'a'(eight signed 16-bit integer numbers) -/// multiplied by fixed-point elements in vector 'b'(eight signed 16-bit integer numbers) -/// The result is written to vector (eight signed 16-bit integer numbers) +/// The fixed-point elements in vector `a` (eight signed 16-bit integer numbers) +/// multiplied by fixed-point elements in vector `b` (eight signed 16-bit integer numbers). +/// The result is written to vector (eight signed 16-bit integer numbers). /// #[inline] #[target_feature(enable = "msa")] @@ -7097,9 +7097,9 @@ pub unsafe fn __msa_mul_q_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Fixed-Point Multiply /// -/// The fixed-point elements in vector 'a'(four signed 32-bit integer numbers) -/// multiplied by fixed-point elements in vector 'b'(four signed 32-bit integer numbers) -/// The result is written to vector (four signed 32-bit integer numbers) +/// The fixed-point elements in vector `a` (four signed 32-bit integer numbers) +/// multiplied by fixed-point elements in vector `b` (four signed 32-bit integer numbers). +/// The result is written to vector (four signed 32-bit integer numbers). /// #[inline] #[target_feature(enable = "msa")] @@ -7110,9 +7110,9 @@ pub unsafe fn __msa_mul_q_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Fixed-Point Multiply Rounded /// -/// The fixed-point elements in vector 'a'(eight signed 16-bit integer numbers) -/// multiplied by fixed-point elements in vector 'b'(eight signed 16-bit integer numbers) -/// The rounded result is written to vector (eight signed 16-bit integer numbers) +/// The fixed-point elements in vector `a` (eight signed 16-bit integer numbers) +/// multiplied by fixed-point elements in vector `b` (eight signed 16-bit integer numbers). +/// The rounded result is written to vector (eight signed 16-bit integer numbers). /// #[inline] #[target_feature(enable = "msa")] @@ -7123,9 +7123,9 @@ pub unsafe fn __msa_mulr_q_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Fixed-Point Multiply Rounded /// -/// The fixed-point elements in vector 'a'(four signed 32-bit integer numbers) -/// multiplied by fixed-point elements in vector 'b'(four signed 32-bit integer numbers) -/// The rounded result is written to vector (four signed 32-bit integer numbers) +/// The fixed-point elements in vector `a` (four signed 32-bit integer numbers) +/// multiplied by fixed-point elements in vector `b` (four signed 32-bit integer numbers). +/// The rounded result is written to vector (four signed 32-bit integer numbers). /// #[inline] #[target_feature(enable = "msa")] @@ -7136,8 +7136,8 @@ pub unsafe fn __msa_mulr_q_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Multiply /// -/// The integer elements in vector 'a'(sixteen signed 8-bit integer numbers) -/// are multiplied by integer elements in vector 'b'(sixteen signed 8-bit integer numbers) +/// The integer elements in vector `a` (sixteen signed 8-bit integer numbers) +/// are multiplied by integer elements in vector `b` (sixteen signed 8-bit integer numbers) /// The result is written to vector (sixteen signed 8-bit integer numbers) /// The most significant half of the multiplication result is discarded. /// @@ -7150,8 +7150,8 @@ pub unsafe fn __msa_mulv_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Multiply /// -/// The integer elements in vector 'a'(eight signed 16-bit integer numbers) -/// are multiplied by integer elements in vector 'b'(eight signed 16-bit integer numbers) +/// The integer elements in vector `a` (eight signed 16-bit integer numbers) +/// are multiplied by integer elements in vector `b` (eight signed 16-bit integer numbers) /// The result is written to vector (eight signed 16-bit integer numbers) /// The most significant half of the multiplication result is discarded. /// @@ -7164,8 +7164,8 @@ pub unsafe fn __msa_mulv_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Multiply /// -/// The integer elements in vector 'a'(four signed 32-bit integer numbers) -/// are multiplied by integer elements in vector 'b'(four signed 32-bit integer numbers) +/// The integer elements in vector `a` (four signed 32-bit integer numbers) +/// are multiplied by integer elements in vector `b` (four signed 32-bit integer numbers) /// The result is written to vector (four signed 32-bit integer numbers) /// The most significant half of the multiplication result is discarded. /// @@ -7178,8 +7178,8 @@ pub unsafe fn __msa_mulv_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Multiply /// -/// The integer elements in vector 'a'(two signed 64-bit integer numbers) -/// are multiplied by integer elements in vector 'b'(two signed 64-bit integer numbers) +/// The integer elements in vector `a` (two signed 64-bit integer numbers) +/// are multiplied by integer elements in vector `b` (two signed 64-bit integer numbers) /// The result is written to vector (two signed 64-bit integer numbers) /// The most significant half of the multiplication result is discarded. /// @@ -7192,7 +7192,7 @@ pub unsafe fn __msa_mulv_d(a: v2i64, b: v2i64) -> v2i64 { /// Vector Leading Ones Count /// -/// The number of leading ones for elements in vector 'a'(sixteen signed 8-bit integer numbers) +/// The number of leading ones for elements in vector `a` (sixteen signed 8-bit integer numbers) /// is stored to the elements in vector (sixteen signed 8-bit integer numbers) /// #[inline] @@ -7204,7 +7204,7 @@ pub unsafe fn __msa_nloc_b(a: v16i8) -> v16i8 { /// Vector Leading Ones Count /// -/// The number of leading ones for elements in vector 'a'(eight signed 16-bit integer numbers) +/// The number of leading ones for elements in vector `a` (eight signed 16-bit integer numbers) /// is stored to the elements in vector (eight signed 16-bit integer numbers) /// #[inline] @@ -7216,7 +7216,7 @@ pub unsafe fn __msa_nloc_h(a: v8i16) -> v8i16 { /// Vector Leading Ones Count /// -/// The number of leading ones for elements in vector 'a'(four signed 32-bit integer numbers) +/// The number of leading ones for elements in vector `a` (four signed 32-bit integer numbers) /// is stored to the elements in vector (four signed 32-bit integer numbers) /// #[inline] @@ -7228,7 +7228,7 @@ pub unsafe fn __msa_nloc_w(a: v4i32) -> v4i32 { /// Vector Leading Ones Count /// -/// The number of leading ones for elements in vector 'a'(two signed 64-bit integer numbers) +/// The number of leading ones for elements in vector `a` (two signed 64-bit integer numbers) /// is stored to the elements in vector (two signed 64-bit integer numbers) /// #[inline] @@ -7240,7 +7240,7 @@ pub unsafe fn __msa_nloc_d(a: v2i64) -> v2i64 { /// Vector Leading Zeros Count /// -/// The number of leading zeros for elements in vector 'a'(sixteen signed 8-bit integer numbers) +/// The number of leading zeros for elements in vector `a` (sixteen signed 8-bit integer numbers) /// is stored to the elements in vector (sixteen signed 8-bit integer numbers) /// #[inline] @@ -7252,7 +7252,7 @@ pub unsafe fn __msa_nlzc_b(a: v16i8) -> v16i8 { /// Vector Leading Zeros Count /// -/// The number of leading zeros for elements in vector 'a'(eight signed 16-bit integer numbers) +/// The number of leading zeros for elements in vector `a` (eight signed 16-bit integer numbers) /// is stored to the elements in vector (eight signed 16-bit integer numbers) /// #[inline] @@ -7264,7 +7264,7 @@ pub unsafe fn __msa_nlzc_h(a: v8i16) -> v8i16 { /// Vector Leading Zeros Count /// -/// The number of leading zeros for elements in vector 'a'(four signed 32-bit integer numbers) +/// The number of leading zeros for elements in vector `a` (four signed 32-bit integer numbers) /// is stored to the elements in vector (four signed 32-bit integer numbers) /// #[inline] @@ -7276,7 +7276,7 @@ pub unsafe fn __msa_nlzc_w(a: v4i32) -> v4i32 { /// Vector Leading Zeros Count /// -/// The number of leading zeros for elements in vector 'a'(two signed 64-bit integer numbers) +/// The number of leading zeros for elements in vector `a` (two signed 64-bit integer numbers) /// is stored to the elements in vector (two signed 64-bit integer numbers) /// #[inline] @@ -7288,8 +7288,8 @@ pub unsafe fn __msa_nlzc_d(a: v2i64) -> v2i64 { /// Vector Logical Negated Or /// -/// Each bit of vector 'a'(sixteen unsigned 8-bit integer numbers) -/// is combined with the corresponding bit of vector 'b' (sixteen unsigned 8-bit integer numbers) +/// Each bit of vector `a` (sixteen unsigned 8-bit integer numbers) +/// is combined with the corresponding bit of vector `b` (sixteen unsigned 8-bit integer numbers) /// in a bitwise logical NOR operation. The result is written to vector /// (sixteen unsigned 8-bit integer numbers) /// @@ -7302,7 +7302,7 @@ pub unsafe fn __msa_nor_v(a: v16u8, b: v16u8) -> v16u8 { /// Immediate Logical Negated Or /// -/// Each bit of vector 'a'(sixteen unsigned 8-bit integer numbers) +/// Each bit of vector `a` (sixteen unsigned 8-bit integer numbers) /// is combined with the 8-bit immediate imm8 /// in a bitwise logical NOR operation. The result is written to vector /// (sixteen unsigned 8-bit integer numbers) @@ -7322,8 +7322,8 @@ pub unsafe fn __msa_nori_b(a: v16u8, imm8: i32) -> v16u8 { /// Vector Logical Or /// -/// Each bit of vector 'a'(sixteen unsigned 8-bit integer numbers) -/// is combined with the corresponding bit of vector 'b' (sixteen unsigned 8-bit integer numbers) +/// Each bit of vector `a` (sixteen unsigned 8-bit integer numbers) +/// is combined with the corresponding bit of vector `b` (sixteen unsigned 8-bit integer numbers) /// in a bitwise logical OR operation. The result is written to vector /// (sixteen unsigned 8-bit integer numbers) /// @@ -7336,7 +7336,7 @@ pub unsafe fn __msa_or_v(a: v16u8, b: v16u8) -> v16u8 { /// Immediate Logical Or /// -/// Each bit of vector 'a'(sixteen unsigned 8-bit integer numbers) +/// Each bit of vector `a` (sixteen unsigned 8-bit integer numbers) /// is combined with the 8-bit immediate imm8 /// in a bitwise logical OR operation. The result is written to vector /// (sixteen unsigned 8-bit integer numbers) @@ -7356,8 +7356,8 @@ pub unsafe fn __msa_ori_b(a: v16u8, imm8: i32) -> v16u8 { /// Vector Pack Even /// -/// Even elements in vectors 'a' (sixteen signed 8-bit integer numbers) -/// are copied to the left half of the result vector and even elements in vector 'b' +/// Even elements in vectors `a` (sixteen signed 8-bit integer numbers) +/// are copied to the left half of the result vector and even elements in vector `b` /// (sixteen signed 8-bit integer numbers) are copied to the right half of the result vector. /// #[inline] @@ -7369,8 +7369,8 @@ pub unsafe fn __msa_pckev_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Pack Even /// -/// Even elements in vectors 'a' (eight signed 16-bit integer numbers) -/// are copied to the left half of the result vector and even elements in vector 'b' +/// Even elements in vectors `a` (eight signed 16-bit integer numbers) +/// are copied to the left half of the result vector and even elements in vector `b` /// (eight signed 16-bit integer numbers) are copied to the right half of the result vector. /// #[inline] @@ -7382,8 +7382,8 @@ pub unsafe fn __msa_pckev_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Pack Even /// -/// Even elements in vectors 'a' (four signed 32-bit integer numbers) -/// are copied to the left half of the result vector and even elements in vector 'b' +/// Even elements in vectors `a` (four signed 32-bit integer numbers) +/// are copied to the left half of the result vector and even elements in vector `b` /// (four signed 32-bit integer numbers) are copied to the right half of the result vector. /// #[inline] @@ -7395,8 +7395,8 @@ pub unsafe fn __msa_pckev_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Pack Even /// -/// Even elements in vectors 'a' (two signed 64-bit integer numbers) -/// are copied to the left half of the result vector and even elements in vector 'b' +/// Even elements in vectors `a` (two signed 64-bit integer numbers) +/// are copied to the left half of the result vector and even elements in vector `b` /// (two signed 64-bit integer numbers) are copied to the right half of the result vector. /// #[inline] @@ -7408,8 +7408,8 @@ pub unsafe fn __msa_pckev_d(a: v2i64, b: v2i64) -> v2i64 { /// Vector Pack Odd /// -/// Odd elements in vectors 'a' (sixteen signed 8-bit integer numbers) -/// are copied to the left half of the result vector and odd elements in vector 'b' +/// Odd elements in vectors `a` (sixteen signed 8-bit integer numbers) +/// are copied to the left half of the result vector and odd elements in vector `b` /// (sixteen signed 8-bit integer numbers) are copied to the right half of the result vector. /// #[inline] @@ -7421,8 +7421,8 @@ pub unsafe fn __msa_pckod_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Pack Odd /// -/// Odd elements in vectors 'a' (eight signed 16-bit integer numbers) -/// are copied to the left half of the result vector and odd elements in vector 'b' +/// Odd elements in vectors `a` (eight signed 16-bit integer numbers) +/// are copied to the left half of the result vector and odd elements in vector `b` /// (eight signed 16-bit integer numbers) are copied to the right half of the result vector. /// #[inline] @@ -7434,8 +7434,8 @@ pub unsafe fn __msa_pckod_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Pack Odd /// -/// Odd elements in vectors 'a' (four signed 32-bit integer numbers) -/// are copied to the left half of the result vector and odd elements in vector 'b' +/// Odd elements in vectors `a` (four signed 32-bit integer numbers) +/// are copied to the left half of the result vector and odd elements in vector `b` /// (four signed 32-bit integer numbers) are copied to the right half of the result vector. /// #[inline] @@ -7447,8 +7447,8 @@ pub unsafe fn __msa_pckod_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Pack Odd /// -/// Odd elements in vectors 'a' (two signed 64-bit integer numbers) -/// are copied to the left half of the result vector and odd elements in vector 'b' +/// Odd elements in vectors `a` (two signed 64-bit integer numbers) +/// are copied to the left half of the result vector and odd elements in vector `b` /// (two signed 64-bit integer numbers) are copied to the right half of the result vector. /// #[inline] @@ -7460,7 +7460,7 @@ pub unsafe fn __msa_pckod_d(a: v2i64, b: v2i64) -> v2i64 { /// Vector Population Count /// -/// The number of bits set to 1 for elements in vector 'a' (sixteen signed 8-bit integer numbers) +/// The number of bits set to 1 for elements in vector `a` (sixteen signed 8-bit integer numbers) /// is stored to the elements in the result vector (sixteen signed 8-bit integer numbers) /// #[inline] @@ -7472,7 +7472,7 @@ pub unsafe fn __msa_pcnt_b(a: v16i8) -> v16i8 { /// Vector Population Count /// -/// The number of bits set to 1 for elements in vector 'a' (eight signed 16-bit integer numbers) +/// The number of bits set to 1 for elements in vector `a` (eight signed 16-bit integer numbers) /// is stored to the elements in the result vector (eight signed 16-bit integer numbers) /// #[inline] @@ -7484,7 +7484,7 @@ pub unsafe fn __msa_pcnt_h(a: v8i16) -> v8i16 { /// Vector Population Count /// -/// The number of bits set to 1 for elements in vector 'a' (four signed 32-bit integer numbers) +/// The number of bits set to 1 for elements in vector `a` (four signed 32-bit integer numbers) /// is stored to the elements in the result vector (four signed 32-bit integer numbers) /// #[inline] @@ -7496,7 +7496,7 @@ pub unsafe fn __msa_pcnt_w(a: v4i32) -> v4i32 { /// Vector Population Count /// -/// The number of bits set to 1 for elements in vector 'a' (two signed 64-bit integer numbers) +/// The number of bits set to 1 for elements in vector `a` (two signed 64-bit integer numbers) /// is stored to the elements in the result vector (two signed 64-bit integer numbers) /// #[inline] @@ -7508,7 +7508,7 @@ pub unsafe fn __msa_pcnt_d(a: v2i64) -> v2i64 { /// Immediate Signed Saturate /// -/// Signed elements in vector 'a' (sixteen signed 8-bit integer numbers) +/// Signed elements in vector `a` (sixteen signed 8-bit integer numbers) /// are saturated to signed values of imm3+1 bits without changing the data width /// The result is stored in the vector (sixteen signed 8-bit integer numbers) /// @@ -7527,7 +7527,7 @@ pub unsafe fn __msa_sat_s_b(a: v16i8, imm3: i32) -> v16i8 { /// Immediate Signed Saturate /// -/// Signed elements in vector 'a' (eight signed 16-bit integer numbers) +/// Signed elements in vector `a` (eight signed 16-bit integer numbers) /// are saturated to signed values of imm4+1 bits without changing the data width /// The result is stored in the vector (eight signed 16-bit integer numbers) /// @@ -7546,7 +7546,7 @@ pub unsafe fn __msa_sat_s_h(a: v8i16, imm4: i32) -> v8i16 { /// Immediate Signed Saturate /// -/// Signed elements in vector 'a' (four signed 32-bit integer numbers) +/// Signed elements in vector `a` (four signed 32-bit integer numbers) /// are saturated to signed values of imm5+1 bits without changing the data width /// The result is stored in the vector (four signed 32-bit integer numbers) /// @@ -7565,7 +7565,7 @@ pub unsafe fn __msa_sat_s_w(a: v4i32, imm5: i32) -> v4i32 { /// Immediate Signed Saturate /// -/// Signed elements in vector 'a' (two signed 64-bit integer numbers) +/// Signed elements in vector `a` (two signed 64-bit integer numbers) /// are saturated to signed values of imm6+1 bits without changing the data width /// The result is stored in the vector (two signed 64-bit integer numbers) /// @@ -7584,7 +7584,7 @@ pub unsafe fn __msa_sat_s_d(a: v2i64, imm6: i32) -> v2i64 { /// Immediate Unsigned Saturate /// -/// Unsigned elements in vector 'a' (sixteen unsigned 8-bit integer numbers) +/// Unsigned elements in vector `a` (sixteen unsigned 8-bit integer numbers) /// are saturated to unsigned values of imm3+1 bits without changing the data width /// The result is stored in the vector (sixteen unsigned 8-bit integer numbers) /// @@ -7603,7 +7603,7 @@ pub unsafe fn __msa_sat_u_b(a: v16u8, imm3: i32) -> v16u8 { /// Immediate Unsigned Saturate /// -/// Unsigned elements in vector 'a' (eight unsigned 16-bit integer numbers) +/// Unsigned elements in vector `a` (eight unsigned 16-bit integer numbers) /// are saturated to unsigned values of imm4+1 bits without changing the data width /// The result is stored in the vector (eight unsigned 16-bit integer numbers) /// @@ -7622,7 +7622,7 @@ pub unsafe fn __msa_sat_u_h(a: v8u16, imm4: i32) -> v8u16 { /// Immediate Unsigned Saturate /// -/// Unsigned elements in vector 'a' (four unsigned 32-bit integer numbers) +/// Unsigned elements in vector `a` (four unsigned 32-bit integer numbers) /// are saturated to unsigned values of imm5+1 bits without changing the data width /// The result is stored in the vector (four unsigned 32-bit integer numbers) /// @@ -7641,7 +7641,7 @@ pub unsafe fn __msa_sat_u_w(a: v4u32, imm5: i32) -> v4u32 { /// Immediate Unsigned Saturate /// -/// Unsigned elements in vector 'a' (two unsigned 64-bit integer numbers) +/// Unsigned elements in vector `a` (two unsigned 64-bit integer numbers) /// are saturated to unsigned values of imm6+1 bits without changing the data width /// The result is stored in the vector (two unsigned 64-bit integer numbers) /// @@ -7661,7 +7661,7 @@ pub unsafe fn __msa_sat_u_d(a: v2u64, imm6: i32) -> v2u64 { /// Immediate Set Shuffle Elements /// /// The set shuffle instruction works on 4-element sets. -/// All sets are shuffled in the same way: the element i82i+1..2i in 'a' +/// All sets are shuffled in the same way: the element i82i+1..2i in `a` /// (sixteen signed 8-bit integer numbers) is copied over the element i in result vector /// (sixteen signed 8-bit integer numbers), where i is 0, 1, 2, 3. /// @@ -7681,7 +7681,7 @@ pub unsafe fn __msa_shf_b(a: v16i8, imm8: i32) -> v16i8 { /// Immediate Set Shuffle Elements /// /// The set shuffle instruction works on 4-element sets. -/// All sets are shuffled in the same way: the element i82i+1..2i in 'a' +/// All sets are shuffled in the same way: the element i82i+1..2i in `a` /// (eight signed 16-bit integer numbers) is copied over the element i in result vector /// (eight signed 16-bit integer numbers), where i is 0, 1, 2, 3. /// @@ -7701,7 +7701,7 @@ pub unsafe fn __msa_shf_h(a: v8i16, imm8: i32) -> v8i16 { /// Immediate Set Shuffle Elements /// /// The set shuffle instruction works on 4-element sets. -/// All sets are shuffled in the same way: the element i82i+1..2i in 'a' +/// All sets are shuffled in the same way: the element i82i+1..2i in `a` /// (four signed 32-bit integer numbers) is copied over the element i in result vector /// (four signed 32-bit integer numbers), where i is 0, 1, 2, 3. /// @@ -7720,15 +7720,15 @@ pub unsafe fn __msa_shf_w(a: v4i32, imm8: i32) -> v4i32 { /// GPR Columns Slide /// -/// Vector registers 'a' (sixteen signed 8-bit integer numbers) and 'b' +/// Vector registers `a` (sixteen signed 8-bit integer numbers) and `b` /// (sixteen signed 8-bit integer numbers) contain 2-dimensional byte arrays (rectangles) /// stored row-wise with as many rows asbytes in integer data format df. -/// The two source rectangles 'b' and 'a' are concatenated horizontally in the order -/// they appear in the syntax, i.e. first 'a' and then 'b'. Place a new destination -/// rectangle over 'b' and then slide it to the left over the concatenation of 'a' and 'b' -/// by the number of columns given in GPR 'c'. +/// The two source rectangles `b` and `a` are concatenated horizontally in the order +/// they appear in the syntax, i.e. first `a` and then `b`. Place a new destination +/// rectangle over `b` and then slide it to the left over the concatenation of `a` and `b` +/// by the number of columns given in GPR `c`. /// The result is written to vector (sixteen signed 8-bit integer numbers). -/// GPR 'c' value is interpreted modulo the number of columns in destination rectangle, +/// GPR `c` value is interpreted modulo the number of columns in destination rectangle, /// or equivalently, the number of data format df elements in the destination vector. /// #[inline] @@ -7740,15 +7740,15 @@ pub unsafe fn __msa_sld_b(a: v16i8, b: v16i8, c: i32) -> v16i8 { /// GPR Columns Slide /// -/// Vector registers 'a' (eight signed 16-bit integer numbers) and 'b' +/// Vector registers `a` (eight signed 16-bit integer numbers) and `b` /// (eight signed 16-bit integer numbers) contain 2-dimensional byte arrays (rectangles) /// stored row-wise with as many rows asbytes in integer data format df. -/// The two source rectangles 'b' and 'a' are concatenated horizontally in the order -/// they appear in the syntax, i.e. first 'a' and then 'b'. Place a new destination -/// rectangle over 'b' and then slide it to the left over the concatenation of 'a' and 'b' -/// by the number of columns given in GPR 'c'. +/// The two source rectangles `b` and `a` are concatenated horizontally in the order +/// they appear in the syntax, i.e. first `a` and then `b`. Place a new destination +/// rectangle over `b` and then slide it to the left over the concatenation of `a` and `b` +/// by the number of columns given in GPR `c`. /// The result is written to vector (eight signed 16-bit integer numbers). -/// GPR 'c' value is interpreted modulo the number of columns in destination rectangle, +/// GPR `c` value is interpreted modulo the number of columns in destination rectangle, /// or equivalently, the number of data format df elements in the destination vector. /// #[inline] @@ -7760,15 +7760,15 @@ pub unsafe fn __msa_sld_h(a: v8i16, b: v8i16, c: i32) -> v8i16 { /// GPR Columns Slide /// -/// Vector registers 'a' (four signed 32-bit integer numbers) and 'b' +/// Vector registers `a` (four signed 32-bit integer numbers) and `b` /// (four signed 32-bit integer numbers) contain 2-dimensional byte arrays (rectangles) /// stored row-wise with as many rows asbytes in integer data format df. -/// The two source rectangles 'b' and 'a' are concatenated horizontally in the order -/// they appear in the syntax, i.e. first 'a' and then 'b'. Place a new destination -/// rectangle over 'b' and then slide it to the left over the concatenation of 'a' and 'b' -/// by the number of columns given in GPR 'c'. +/// The two source rectangles `b` and `a` are concatenated horizontally in the order +/// they appear in the syntax, i.e. first `a` and then `b`. Place a new destination +/// rectangle over `b` and then slide it to the left over the concatenation of `a` and `b` +/// by the number of columns given in GPR `c`. /// The result is written to vector (four signed 32-bit integer numbers). -/// GPR 'c' value is interpreted modulo the number of columns in destination rectangle, +/// GPR `c` value is interpreted modulo the number of columns in destination rectangle, /// or equivalently, the number of data format df elements in the destination vector. /// #[inline] @@ -7780,15 +7780,15 @@ pub unsafe fn __msa_sld_w(a: v4i32, b: v4i32, c: i32) -> v4i32 { /// GPR Columns Slide /// -/// Vector registers 'a' (two signed 64-bit integer numbers) and 'b' +/// Vector registers `a` (two signed 64-bit integer numbers) and `b` /// (two signed 64-bit integer numbers) contain 2-dimensional byte arrays (rectangles) /// stored row-wise with as many rows asbytes in integer data format df. -/// The two source rectangles 'b' and 'a' are concatenated horizontally in the order -/// they appear in the syntax, i.e. first 'a' and then 'b'. Place a new destination -/// rectangle over 'b' and then slide it to the left over the concatenation of 'a' and 'b' -/// by the number of columns given in GPR 'c'. +/// The two source rectangles `b` and `a` are concatenated horizontally in the order +/// they appear in the syntax, i.e. first `a` and then `b`. Place a new destination +/// rectangle over `b` and then slide it to the left over the concatenation of `a` and `b` +/// by the number of columns given in GPR `c`. /// The result is written to vector (two signed 64-bit integer numbers). -/// GPR 'c' value is interpreted modulo the number of columns in destination rectangle, +/// GPR `c` value is interpreted modulo the number of columns in destination rectangle, /// or equivalently, the number of data format df elements in the destination vector. /// #[inline] @@ -7800,12 +7800,12 @@ pub unsafe fn __msa_sld_d(a: v2i64, b: v2i64, c: i32) -> v2i64 { /// Immediate Columns Slide /// -/// Vector registers 'a' (sixteen signed 8-bit integer numbers) and 'b' +/// Vector registers `a` (sixteen signed 8-bit integer numbers) and `b` /// (sixteen signed 8-bit integer numbers) contain 2-dimensional byte arrays (rectangles) /// stored row-wise with as many rows asbytes in integer data format df. -/// The two source rectangles 'b' and 'a' are concatenated horizontally in the order -/// they appear in the syntax, i.e. first 'a' and then 'b'. Place a new destination -/// rectangle over 'b' and then slide it to the left over the concatenation of 'a' and 'b' +/// The two source rectangles `b` and `a` are concatenated horizontally in the order +/// they appear in the syntax, i.e. first `a` and then `b`. Place a new destination +/// rectangle over `b` and then slide it to the left over the concatenation of `a` and `b` /// by imm1 columns /// The result is written to vector (sixteen signed 8-bit integer numbers). /// @@ -7824,12 +7824,12 @@ pub unsafe fn __msa_sldi_b(a: v16i8, b: v16i8, imm4: i32) -> v16i8 { /// Immediate Columns Slide /// -/// Vector registers 'a' (eight signed 16-bit integer numbers) and 'b' +/// Vector registers `a` (eight signed 16-bit integer numbers) and `b` /// (eight signed 16-bit integer numbers) contain 2-dimensional byte arrays (rectangles) /// stored row-wise with as many rows asbytes in integer data format df. -/// The two source rectangles 'b' and 'a' are concatenated horizontally in the order -/// they appear in the syntax, i.e. first 'a' and then 'b'. Place a new destination -/// rectangle over 'b' and then slide it to the left over the concatenation of 'a' and 'b' +/// The two source rectangles `b` and `a` are concatenated horizontally in the order +/// they appear in the syntax, i.e. first `a` and then `b`. Place a new destination +/// rectangle over `b` and then slide it to the left over the concatenation of `a` and `b` /// by imm1 columns /// The result is written to vector (eight signed 16-bit integer numbers). /// @@ -7848,12 +7848,12 @@ pub unsafe fn __msa_sldi_h(a: v8i16, b: v8i16, imm3: i32) -> v8i16 { /// Immediate Columns Slide /// -/// Vector registers 'a' (four signed 32-bit integer numbers) and 'b' +/// Vector registers `a` (four signed 32-bit integer numbers) and `b` /// (four signed 32-bit integer numbers) contain 2-dimensional byte arrays (rectangles) /// stored row-wise with as many rows asbytes in integer data format df. -/// The two source rectangles 'b' and 'a' are concatenated horizontally in the order -/// they appear in the syntax, i.e. first 'a' and then 'b'. Place a new destination -/// rectangle over 'b' and then slide it to the left over the concatenation of 'a' and 'b' +/// The two source rectangles `b` and `a` are concatenated horizontally in the order +/// they appear in the syntax, i.e. first `a` and then `b`. Place a new destination +/// rectangle over `b` and then slide it to the left over the concatenation of `a` and `b` /// by imm1 columns /// The result is written to vector (four signed 32-bit integer numbers). /// @@ -7872,12 +7872,12 @@ pub unsafe fn __msa_sldi_w(a: v4i32, b: v4i32, imm2: i32) -> v4i32 { /// Immediate Columns Slide /// -/// Vector registers 'a' (two signed 64-bit integer numbers) and 'b' +/// Vector registers `a` (two signed 64-bit integer numbers) and `b` /// (two signed 64-bit integer numbers) contain 2-dimensional byte arrays (rectangles) /// stored row-wise with as many rows asbytes in integer data format df. -/// The two source rectangles 'b' and 'a' are concatenated horizontally in the order -/// they appear in the syntax, i.e. first 'a' and then 'b'. Place a new destination -/// rectangle over 'b' and then slide it to the left over the concatenation of 'a' and 'b' +/// The two source rectangles `b` and `a` are concatenated horizontally in the order +/// they appear in the syntax, i.e. first `a` and then `b`. Place a new destination +/// rectangle over `b` and then slide it to the left over the concatenation of `a` and `b` /// by imm1 columns /// The result is written to vector (two signed 64-bit integer numbers). /// @@ -7896,8 +7896,8 @@ pub unsafe fn __msa_sldi_d(a: v2i64, b: v2i64, imm1: i32) -> v2i64 { /// Vector Shift Left /// -/// The elements in vector 'a'(sixteen signed 8-bit integer numbers) -/// are shifted left by the number of bits the elements in vector 'b' +/// The elements in vector `a` (sixteen signed 8-bit integer numbers) +/// are shifted left by the number of bits the elements in vector `b` /// (sixteen signed 8-bit integer numbers) specify modulo the size of the /// element in bits.The result is written to vector (sixteen signed 8-bit integer numbers). /// @@ -7910,8 +7910,8 @@ pub unsafe fn __msa_sll_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Shift Left /// -/// The elements in vector 'a'(eight signed 16-bit integer numbers) -/// are shifted left by the number of bits the elements in vector 'b' +/// The elements in vector `a` (eight signed 16-bit integer numbers) +/// are shifted left by the number of bits the elements in vector `b` /// (eight signed 16-bit integer numbers) specify modulo the size of the /// element in bits.The result is written to vector (eight signed 16-bit integer numbers). /// @@ -7924,8 +7924,8 @@ pub unsafe fn __msa_sll_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Shift Left /// -/// The elements in vector 'a'(four signed 32-bit integer numbers) -/// are shifted left by the number of bits the elements in vector 'b' +/// The elements in vector `a` (four signed 32-bit integer numbers) +/// are shifted left by the number of bits the elements in vector `b` /// (four signed 32-bit integer numbers) specify modulo the size of the /// element in bits.The result is written to vector (four signed 32-bit integer numbers). /// @@ -7938,8 +7938,8 @@ pub unsafe fn __msa_sll_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Shift Left /// -/// The elements in vector 'a'(two signed 64-bit integer numbers) -/// are shifted left by the number of bits the elements in vector 'b' +/// The elements in vector `a` (two signed 64-bit integer numbers) +/// are shifted left by the number of bits the elements in vector `b` /// (two signed 64-bit integer numbers) specify modulo the size of the /// element in bits.The result is written to vector(two signed 64-bit integer numbers). /// @@ -7952,7 +7952,7 @@ pub unsafe fn __msa_sll_d(a: v2i64, b: v2i64) -> v2i64 { /// Immediate Shift Left /// -/// The elements in vector 'a'(sixteen signed 8-bit integer numbers) +/// The elements in vector `a` (sixteen signed 8-bit integer numbers) /// are shifted left by the imm4 bits. /// The result is written to vector(sixteen signed 8-bit integer numbers). /// @@ -7971,7 +7971,7 @@ pub unsafe fn __msa_slli_b(a: v16i8, imm4: i32) -> v16i8 { /// Immediate Shift Left /// -/// The elements in vector 'a'(eight signed 16-bit integer numbers) +/// The elements in vector `a` (eight signed 16-bit integer numbers) /// are shifted left by the imm3 bits. /// The result is written to vector(eight signed 16-bit integer numbers). /// @@ -7990,7 +7990,7 @@ pub unsafe fn __msa_slli_h(a: v8i16, imm3: i32) -> v8i16 { /// Immediate Shift Left /// -/// The elements in vector 'a'(four signed 32-bit integer numbers) +/// The elements in vector `a` (four signed 32-bit integer numbers) /// are shifted left by the imm2 bits. /// The result is written to vector(four signed 32-bit integer numbers). /// @@ -8009,7 +8009,7 @@ pub unsafe fn __msa_slli_w(a: v4i32, imm2: i32) -> v4i32 { /// Immediate Shift Left /// -/// The elements in vector 'a'(two signed 64-bit integer numbers) +/// The elements in vector `a` (two signed 64-bit integer numbers) /// are shifted left by the imm1 bits. /// The result is written to vector(two signed 64-bit integer numbers). /// @@ -8028,9 +8028,9 @@ pub unsafe fn __msa_slli_d(a: v2i64, imm1: i32) -> v2i64 { /// GPR Element Splat /// -/// Replicate vector 'a'(sixteen signed 8-bit integer numbers) -/// element with index given by GPR 'b' to all elements in vector -/// (sixteen signed 8-bit integer numbers) GPR 'b' value is interpreted +/// Replicate vector `a` (sixteen signed 8-bit integer numbers) +/// element with index given by GPR `b` to all elements in vector +/// (sixteen signed 8-bit integer numbers) GPR `b` value is interpreted /// modulo the number of data format df elements in the destination vector. /// #[inline] @@ -8042,9 +8042,9 @@ pub unsafe fn __msa_splat_b(a: v16i8, b: i32) -> v16i8 { /// GPR Element Splat /// -/// Replicate vector 'a'(eight signed 16-bit integer numbers) -/// element with index given by GPR 'b' to all elements in vector -/// (eight signed 16-bit integer numbers) GPR 'b' value is interpreted +/// Replicate vector `a` (eight signed 16-bit integer numbers) +/// element with index given by GPR `b` to all elements in vector +/// (eight signed 16-bit integer numbers) GPR `b` value is interpreted /// modulo the number of data format df elements in the destination vector. /// #[inline] @@ -8056,9 +8056,9 @@ pub unsafe fn __msa_splat_h(a: v8i16, b: i32) -> v8i16 { /// GPR Element Splat /// -/// Replicate vector 'a'(four signed 32-bit integer numbers) -/// element with index given by GPR 'b' to all elements in vector -/// (four signed 32-bit integer numbers) GPR 'b' value is interpreted +/// Replicate vector `a` (four signed 32-bit integer numbers) +/// element with index given by GPR `b` to all elements in vector +/// (four signed 32-bit integer numbers) GPR `b` value is interpreted /// modulo the number of data format df elements in the destination vector. /// #[inline] @@ -8070,9 +8070,9 @@ pub unsafe fn __msa_splat_w(a: v4i32, b: i32) -> v4i32 { /// GPR Element Splat /// -/// Replicate vector 'a'(two signed 64-bit integer numbers) -/// element with index given by GPR 'b' to all elements in vector -/// (two signed 64-bit integer numbers) GPR 'b' value is interpreted +/// Replicate vector `a` (two signed 64-bit integer numbers) +/// element with index given by GPR `b` to all elements in vector +/// (two signed 64-bit integer numbers) GPR `b` value is interpreted /// modulo the number of data format df elements in the destination vector. /// #[inline] @@ -8084,7 +8084,7 @@ pub unsafe fn __msa_splat_d(a: v2i64, b: i32) -> v2i64 { /// Immediate Element Splat /// -/// Replicate element imm4 in vector 'a'(sixteen signed 8-bit integer numbers) +/// Replicate element imm4 in vector `a` (sixteen signed 8-bit integer numbers) /// to all elements in vector (sixteen signed 8-bit integer numbers). /// #[inline] @@ -8102,7 +8102,7 @@ pub unsafe fn __msa_splati_b(a: v16i8, imm4: i32) -> v16i8 { /// Immediate Element Splat /// -/// Replicate element imm3 in vector 'a'(eight signed 16-bit integer numbers) +/// Replicate element imm3 in vector `a` (eight signed 16-bit integer numbers) /// to all elements in vector (eight signed 16-bit integer numbers). /// #[inline] @@ -8120,7 +8120,7 @@ pub unsafe fn __msa_splati_h(a: v8i16, imm3: i32) -> v8i16 { /// Immediate Element Splat /// -/// Replicate element imm2 in vector 'a'(four signed 32-bit integer numbers) +/// Replicate element imm2 in vector `a` (four signed 32-bit integer numbers) /// to all elements in vector (four signed 32-bit integer numbers). /// #[inline] @@ -8138,7 +8138,7 @@ pub unsafe fn __msa_splati_w(a: v4i32, imm2: i32) -> v4i32 { /// Immediate Element Splat /// -/// Replicate element imm1 in vector 'a'(two signed 64-bit integer numbers) +/// Replicate element imm1 in vector `a` (two signed 64-bit integer numbers) /// to all elements in vector (two signed 64-bit integer numbers). /// #[inline] @@ -8156,8 +8156,8 @@ pub unsafe fn __msa_splati_d(a: v2i64, imm1: i32) -> v2i64 { /// Vector Shift Right Arithmetic /// -/// The elements in vector 'a'(sixteen signed 8-bit integer numbers) -/// are shifted right arithmetic by the number of bits the elements in vector 'b' +/// The elements in vector `a` (sixteen signed 8-bit integer numbers) +/// are shifted right arithmetic by the number of bits the elements in vector `b` /// (sixteen signed 8-bit integer numbers) specify modulo the size of the /// element in bits.The result is written to vector(sixteen signed 8-bit integer numbers). /// @@ -8170,8 +8170,8 @@ pub unsafe fn __msa_sra_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Shift Right Arithmetic /// -/// The elements in vector 'a'(eight signed 16-bit integer numbers) -/// are shifted right arithmetic by the number of bits the elements in vector 'b' +/// The elements in vector `a` (eight signed 16-bit integer numbers) +/// are shifted right arithmetic by the number of bits the elements in vector `b` /// (eight signed 16-bit integer numbers) specify modulo the size of the /// element in bits.The result is written to vector(eight signed 16-bit integer numbers). /// @@ -8184,8 +8184,8 @@ pub unsafe fn __msa_sra_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Shift Right Arithmetic /// -/// The elements in vector 'a'(four signed 32-bit integer numbers) -/// are shifted right arithmetic by the number of bits the elements in vector 'b' +/// The elements in vector `a` (four signed 32-bit integer numbers) +/// are shifted right arithmetic by the number of bits the elements in vector `b` /// (four signed 32-bit integer numbers) specify modulo the size of the /// element in bits.The result is written to vector(four signed 32-bit integer numbers). /// @@ -8198,8 +8198,8 @@ pub unsafe fn __msa_sra_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Shift Right Arithmetic /// -/// The elements in vector 'a'(two signed 64-bit integer numbers) -/// are shifted right arithmetic by the number of bits the elements in vector 'b' +/// The elements in vector `a` (two signed 64-bit integer numbers) +/// are shifted right arithmetic by the number of bits the elements in vector `b` /// (two signed 64-bit integer numbers) specify modulo the size of the /// element in bits.The result is written to vector(two signed 64-bit integer numbers). /// @@ -8212,7 +8212,7 @@ pub unsafe fn __msa_sra_d(a: v2i64, b: v2i64) -> v2i64 { /// Immediate Shift Right Arithmetic /// -/// The elements in vector 'a'(sixteen signed 8-bit integer numbers) +/// The elements in vector `a` (sixteen signed 8-bit integer numbers) /// are shifted right arithmetic by imm3 bits. /// The result is written to vector(sixteen signed 8-bit integer numbers). /// @@ -8231,7 +8231,7 @@ pub unsafe fn __msa_srai_b(a: v16i8, imm3: i32) -> v16i8 { /// Immediate Shift Right Arithmetic /// -/// The elements in vector 'a'(eight signed 16-bit integer numbers) +/// The elements in vector `a` (eight signed 16-bit integer numbers) /// are shifted right arithmetic by imm4 bits. /// The result is written to vector(eight signed 16-bit integer numbers). /// @@ -8250,7 +8250,7 @@ pub unsafe fn __msa_srai_h(a: v8i16, imm4: i32) -> v8i16 { /// Immediate Shift Right Arithmetic /// -/// The elements in vector 'a'(four signed 32-bit integer numbers) +/// The elements in vector `a` (four signed 32-bit integer numbers) /// are shifted right arithmetic by imm5 bits. /// The result is written to vector(four signed 32-bit integer numbers). /// @@ -8269,7 +8269,7 @@ pub unsafe fn __msa_srai_w(a: v4i32, imm5: i32) -> v4i32 { /// Immediate Shift Right Arithmetic /// -/// The elements in vector 'a'(two signed 64-bit integer numbers) +/// The elements in vector `a` (two signed 64-bit integer numbers) /// are shifted right arithmetic by imm6 bits. /// The result is written to vector(two signed 64-bit integer numbers). /// @@ -8288,8 +8288,8 @@ pub unsafe fn __msa_srai_d(a: v2i64, imm6: i32) -> v2i64 { /// Vector Shift Right Arithmetic Rounded /// -/// The elements in vector 'a'(sixteen signed 8-bit integer numbers) -/// are shifted right arithmetic by the number of bits the elements in vector 'b' +/// The elements in vector `a` (sixteen signed 8-bit integer numbers) +/// are shifted right arithmetic by the number of bits the elements in vector `b` /// (sixteen signed 8-bit integer numbers) specify modulo the size of the /// element in bits.The most significant discarded bit is added to the shifted /// value (for rounding) and the result is written to vector(sixteen signed 8-bit integer numbers). @@ -8303,8 +8303,8 @@ pub unsafe fn __msa_srar_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Shift Right Arithmetic Rounded /// -/// The elements in vector 'a'(eight signed 16-bit integer numbers) -/// are shifted right arithmetic by the number of bits the elements in vector 'b' +/// The elements in vector `a` (eight signed 16-bit integer numbers) +/// are shifted right arithmetic by the number of bits the elements in vector `b` /// (eight signed 16-bit integer numbers) specify modulo the size of the /// element in bits.The most significant discarded bit is added to the shifted /// value (for rounding) and the result is written to vector(eight signed 16-bit integer numbers). @@ -8318,8 +8318,8 @@ pub unsafe fn __msa_srar_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Shift Right Arithmetic Rounded /// -/// The elements in vector 'a'(four signed 32-bit integer numbers) -/// are shifted right arithmetic by the number of bits the elements in vector 'b' +/// The elements in vector `a` (four signed 32-bit integer numbers) +/// are shifted right arithmetic by the number of bits the elements in vector `b` /// (four signed 32-bit integer numbers) specify modulo the size of the /// element in bits.The most significant discarded bit is added to the shifted /// value (for rounding) and the result is written to vector(four signed 32-bit integer numbers). @@ -8333,8 +8333,8 @@ pub unsafe fn __msa_srar_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Shift Right Arithmetic Rounded /// -/// The elements in vector 'a'(two signed 64-bit integer numbers) -/// are shifted right arithmetic by the number of bits the elements in vector 'b' +/// The elements in vector `a` (two signed 64-bit integer numbers) +/// are shifted right arithmetic by the number of bits the elements in vector `b` /// (two signed 64-bit integer numbers) specify modulo the size of the /// element in bits.The most significant discarded bit is added to the shifted /// value (for rounding) and the result is written to vector(two signed 64-bit integer numbers). @@ -8348,7 +8348,7 @@ pub unsafe fn __msa_srar_d(a: v2i64, b: v2i64) -> v2i64 { /// Immediate Shift Right Arithmetic Rounded /// -/// The elements in vector 'a'(sixteen signed 8-bit integer numbers) +/// The elements in vector `a` (sixteen signed 8-bit integer numbers) /// are shifted right arithmetic by imm3 bits.The most significant /// discarded bit is added to the shifted value (for rounding) and /// the result is written to vector(sixteen signed 8-bit integer numbers). @@ -8368,7 +8368,7 @@ pub unsafe fn __msa_srari_b(a: v16i8, imm3: i32) -> v16i8 { /// Immediate Shift Right Arithmetic Rounded /// -/// The elements in vector 'a'(eight signed 16-bit integer numbers) +/// The elements in vector `a` (eight signed 16-bit integer numbers) /// are shifted right arithmetic by imm4 bits.The most significant /// discarded bit is added to the shifted value (for rounding) and /// the result is written to vector(eight signed 16-bit integer numbers). @@ -8388,7 +8388,7 @@ pub unsafe fn __msa_srari_h(a: v8i16, imm4: i32) -> v8i16 { /// Immediate Shift Right Arithmetic Rounded /// -/// The elements in vector 'a'(four signed 32-bit integer numbers) +/// The elements in vector `a` (four signed 32-bit integer numbers) /// are shifted right arithmetic by imm5 bits.The most significant /// discarded bit is added to the shifted value (for rounding) and /// the result is written to vector(four signed 32-bit integer numbers). @@ -8408,7 +8408,7 @@ pub unsafe fn __msa_srari_w(a: v4i32, imm5: i32) -> v4i32 { /// Immediate Shift Right Arithmetic Rounded /// -/// The elements in vector 'a'(two signed 64-bit integer numbers) +/// The elements in vector `a` (two signed 64-bit integer numbers) /// are shifted right arithmetic by imm6 bits.The most significant /// discarded bit is added to the shifted value (for rounding) and /// the result is written to vector(two signed 64-bit integer numbers). @@ -8428,8 +8428,8 @@ pub unsafe fn __msa_srari_d(a: v2i64, imm6: i32) -> v2i64 { /// Vector Shift Right Logical /// -/// The elements in vector 'a'(sixteen signed 8-bit integer numbers) -/// are shifted right logical by the number of bits the elements in vector 'b' +/// The elements in vector `a` (sixteen signed 8-bit integer numbers) +/// are shifted right logical by the number of bits the elements in vector `b` /// (sixteen signed 8-bit integer numbers) specify modulo the size of the /// element in bits.The result is written to vector(sixteen signed 8-bit integer numbers). /// @@ -8442,8 +8442,8 @@ pub unsafe fn __msa_srl_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Shift Right Logical /// -/// The elements in vector 'a'(eight signed 16-bit integer numbers) -/// are shifted right logical by the number of bits the elements in vector 'b' +/// The elements in vector `a` (eight signed 16-bit integer numbers) +/// are shifted right logical by the number of bits the elements in vector `b` /// (eight signed 16-bit integer numbers) specify modulo the size of the /// element in bits.The result is written to vector(eight signed 16-bit integer numbers). /// @@ -8456,8 +8456,8 @@ pub unsafe fn __msa_srl_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Shift Right Logical /// -/// The elements in vector 'a'(four signed 32-bit integer numbers) -/// are shifted right logical by the number of bits the elements in vector 'b' +/// The elements in vector `a` (four signed 32-bit integer numbers) +/// are shifted right logical by the number of bits the elements in vector `b` /// (four signed 32-bit integer numbers) specify modulo the size of the /// element in bits.The result is written to vector(four signed 32-bit integer numbers). /// @@ -8470,8 +8470,8 @@ pub unsafe fn __msa_srl_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Shift Right Logical /// -/// The elements in vector 'a'(two signed 64-bit integer numbers) -/// are shifted right logical by the number of bits the elements in vector 'b' +/// The elements in vector `a` (two signed 64-bit integer numbers) +/// are shifted right logical by the number of bits the elements in vector `b` /// (two signed 64-bit integer numbers) specify modulo the size of the /// element in bits.The result is written to vector(two signed 64-bit integer numbers). /// @@ -8484,7 +8484,7 @@ pub unsafe fn __msa_srl_d(a: v2i64, b: v2i64) -> v2i64 { /// Immediate Shift Right Logical /// -/// The elements in vector 'a'(sixteen signed 8-bit integer numbers) +/// The elements in vector `a` (sixteen signed 8-bit integer numbers) /// are shifted right logical by imm4 bits. /// The result is written to vector(sixteen signed 8-bit integer numbers). /// @@ -8503,7 +8503,7 @@ pub unsafe fn __msa_srli_b(a: v16i8, imm4: i32) -> v16i8 { /// Immediate Shift Right Logical /// -/// The elements in vector 'a'(eight signed 16-bit integer numbers) +/// The elements in vector `a` (eight signed 16-bit integer numbers) /// are shifted right logical by imm3 bits. /// The result is written to vector(eight signed 16-bit integer numbers). /// @@ -8522,7 +8522,7 @@ pub unsafe fn __msa_srli_h(a: v8i16, imm3: i32) -> v8i16 { /// Immediate Shift Right Logical /// -/// The elements in vector 'a'(four signed 32-bit integer numbers) +/// The elements in vector `a` (four signed 32-bit integer numbers) /// are shifted right logical by imm2 bits. /// The result is written to vector(four signed 32-bit integer numbers). /// @@ -8541,7 +8541,7 @@ pub unsafe fn __msa_srli_w(a: v4i32, imm2: i32) -> v4i32 { /// Immediate Shift Right Logical /// -/// The elements in vector 'a'(two signed 64-bit integer numbers) +/// The elements in vector `a` (two signed 64-bit integer numbers) /// are shifted right logical by imm1 bits. /// The result is written to vector(two signed 64-bit integer numbers). /// @@ -8560,8 +8560,8 @@ pub unsafe fn __msa_srli_d(a: v2i64, imm1: i32) -> v2i64 { /// Vector Shift Right Logical Rounded /// -/// The elements in vector 'a'(sixteen signed 8-bit integer numbers) -/// are shifted right logical by the number of bits the elements in vector 'b' +/// The elements in vector `a` (sixteen signed 8-bit integer numbers) +/// are shifted right logical by the number of bits the elements in vector `b` /// (sixteen signed 8-bit integer numbers) specify modulo the size of the /// element in bits.The most significant discarded bit is added to the shifted /// value (for rounding) and the result is written to vector(sixteen signed 8-bit integer numbers). @@ -8575,8 +8575,8 @@ pub unsafe fn __msa_srlr_b(a: v16i8, b: v16i8) -> v16i8 { /// Vector Shift Right Logical Rounded /// -/// The elements in vector 'a'(eight signed 16-bit integer numbers) -/// are shifted right logical by the number of bits the elements in vector 'b' +/// The elements in vector `a` (eight signed 16-bit integer numbers) +/// are shifted right logical by the number of bits the elements in vector `b` /// (eight signed 16-bit integer numbers) specify modulo the size of the /// element in bits.The most significant discarded bit is added to the shifted /// value (for rounding) and the result is written to vector(eight signed 16-bit integer numbers). @@ -8590,8 +8590,8 @@ pub unsafe fn __msa_srlr_h(a: v8i16, b: v8i16) -> v8i16 { /// Vector Shift Right Logical Rounded /// -/// The elements in vector 'a'(four signed 32-bit integer numbers) -/// are shifted right logical by the number of bits the elements in vector 'b' +/// The elements in vector `a` (four signed 32-bit integer numbers) +/// are shifted right logical by the number of bits the elements in vector `b` /// (four signed 32-bit integer numbers) specify modulo the size of the /// element in bits.The most significant discarded bit is added to the shifted /// value (for rounding) and the result is written to vector(four signed 32-bit integer numbers). @@ -8605,8 +8605,8 @@ pub unsafe fn __msa_srlr_w(a: v4i32, b: v4i32) -> v4i32 { /// Vector Shift Right Logical Rounded /// -/// The elements in vector 'a'(two signed 64-bit integer numbers) -/// are shifted right logical by the number of bits the elements in vector 'b' +/// The elements in vector `a` (two signed 64-bit integer numbers) +/// are shifted right logical by the number of bits the elements in vector `b` /// (two signed 64-bit integer numbers) specify modulo the size of the /// element in bits.The most significant discarded bit is added to the shifted /// value (for rounding) and the result is written to vector(two signed 64-bit integer numbers). @@ -8620,7 +8620,7 @@ pub unsafe fn __msa_srlr_d(a: v2i64, b: v2i64) -> v2i64 { /// Immediate Shift Right Logical Rounded /// -/// The elements in vector 'a'(sixteen signed 8-bit integer numbers) +/// The elements in vector `a` (sixteen signed 8-bit integer numbers) /// are shifted right logical by imm6 bits.The most significant /// discarded bit is added to the shifted value (for rounding) and /// the result is written to vector(sixteen signed 8-bit integer numbers). @@ -8640,7 +8640,7 @@ pub unsafe fn __msa_srlri_b(a: v16i8, imm3: i32) -> v16i8 { /// Immediate Shift Right Logical Rounded /// -/// The elements in vector 'a'(eight signed 16-bit integer numbers) +/// The elements in vector `a` (eight signed 16-bit integer numbers) /// are shifted right logical by imm6 bits.The most significant /// discarded bit is added to the shifted value (for rounding) and /// the result is written to vector(eight signed 16-bit integer numbers). @@ -8660,7 +8660,7 @@ pub unsafe fn __msa_srlri_h(a: v8i16, imm4: i32) -> v8i16 { /// Immediate Shift Right Logical Rounded /// -/// The elements in vector 'a'(four signed 32-bit integer numbers) +/// The elements in vector `a` (four signed 32-bit integer numbers) /// are shifted right logical by imm6 bits.The most significant /// discarded bit is added to the shifted value (for rounding) and /// the result is written to vector(four signed 32-bit integer numbers). @@ -8680,7 +8680,7 @@ pub unsafe fn __msa_srlri_w(a: v4i32, imm5: i32) -> v4i32 { /// Immediate Shift Right Logical Rounded /// -/// The elements in vector 'a'(two signed 64-bit integer numbers) +/// The elements in vector `a` (two signed 64-bit integer numbers) /// are shifted right logical by imm6 bits.The most significant /// discarded bit is added to the shifted value (for rounding) and /// the result is written to vector(two signed 64-bit integer numbers). @@ -8700,7 +8700,7 @@ pub unsafe fn __msa_srlri_d(a: v2i64, imm6: i32) -> v2i64 { /// Vector Store /// -/// TheWRLEN / 8 bytes in vector 'a'(sixteen signed 8-bit integer numbers) +/// TheWRLEN / 8 bytes in vector `a` (sixteen signed 8-bit integer numbers) /// are stored as elements of data format df at the effective memory location /// addressed by the base mem_addr and the 10-bit signed immediate offset imm_s10 /// @@ -8719,7 +8719,7 @@ pub unsafe fn __msa_st_b(a: v16i8, mem_addr: *mut u8, imm_s10: i32) -> () { /// Vector Store /// -/// TheWRLEN / 8 bytes in vector 'a'(eight signed 16-bit integer numbers) +/// TheWRLEN / 8 bytes in vector `a` (eight signed 16-bit integer numbers) /// are stored as elements of data format df at the effective memory location /// addressed by the base mem_addr and the 11-bit signed immediate offset imm_s11 /// @@ -8738,7 +8738,7 @@ pub unsafe fn __msa_st_h(a: v8i16, mem_addr: *mut u8, imm_s11: i32) -> () { /// Vector Store /// -/// TheWRLEN / 8 bytes in vector 'a'(four signed 32-bit integer numbers) +/// TheWRLEN / 8 bytes in vector `a` (four signed 32-bit integer numbers) /// are stored as elements of data format df at the effective memory location /// addressed by the base mem_addr and the 12-bit signed immediate offset imm_s12 /// @@ -8757,7 +8757,7 @@ pub unsafe fn __msa_st_w(a: v4i32, mem_addr: *mut u8, imm_s12: i32) -> () { /// Vector Store /// -/// TheWRLEN / 8 bytes in vector 'a'(two signed 64-bit integer numbers) +/// TheWRLEN / 8 bytes in vector `a` (two signed 64-bit integer numbers) /// are stored as elements of data format df at the effective memory location /// addressed by the base mem_addr and the 13-bit signed immediate offset imm_s13 /// @@ -9129,11 +9129,11 @@ pub unsafe fn __msa_subvi_d(a: v2i64, imm5: i32) -> v2i64 { /// Vector Data Preserving Shuffle /// /// The vector shuffle instructions selectively copy data elements from the -/// concatenation of vectors 'b' (sixteen signed 8-bit integer numbers) -/// and `c` (sixteen signed 8-bit integer numbers) in to vector 'a' -/// (sixteen signed 8-bit integer numbers) based on the corresponding control element in 'a' -/// The least significant 6 bits in 'a' control elements modulo the number of elements in -/// the concatenated vectors 'b','a' specify the index of the source element. +/// concatenation of vectors `b` (sixteen signed 8-bit integer numbers) +/// and `c` (sixteen signed 8-bit integer numbers) in to vector `a` +/// (sixteen signed 8-bit integer numbers) based on the corresponding control element in `a` +/// The least significant 6 bits in `a` control elements modulo the number of elements in +/// the concatenated vectors `b`, `a` specify the index of the source element. /// If bit 6 or bit 7 is 1, there will be no copy, but rather the destination elementis set to 0. /// #[inline] @@ -9146,11 +9146,11 @@ pub unsafe fn __msa_vshf_b(a: v16i8, b: v16i8, c: v16i8) -> v16i8 { /// Vector Data Preserving Shuffle /// /// The vector shuffle instructions selectively copy data elements from the -/// concatenation of vectors 'b' (eight signed 16-bit integer numbers) -/// and `c` (eight signed 16-bit integer numbers) in to vector 'a' -/// (eight signed 16-bit integer numbers) based on the corresponding control element in 'a' -/// The least significant 6 bits in 'a' control elements modulo the number of elements in -/// the concatenated vectors 'b','a' specify the index of the source element. +/// concatenation of vectors `b` (eight signed 16-bit integer numbers) +/// and `c` (eight signed 16-bit integer numbers) in to vector `a` +/// (eight signed 16-bit integer numbers) based on the corresponding control element in `a` +/// The least significant 6 bits in `a` control elements modulo the number of elements in +/// the concatenated vectors `b`, `a` specify the index of the source element. /// If bit 6 or bit 7 is 1, there will be no copy, but rather the destination elementis set to 0. /// #[inline] @@ -9163,11 +9163,11 @@ pub unsafe fn __msa_vshf_h(a: v8i16, b: v8i16, c: v8i16) -> v8i16 { /// Vector Data Preserving Shuffle /// /// The vector shuffle instructions selectively copy data elements from the -/// concatenation of vectors 'b' (four signed 32-bit integer numbers) -/// and `c` (four signed 32-bit integer numbers) in to vector 'a' -/// (four signed 32-bit integer numbers) based on the corresponding control element in 'a' -/// The least significant 6 bits in 'a' control elements modulo the number of elements in -/// the concatenated vectors 'b','a' specify the index of the source element. +/// concatenation of vectors `b` (four signed 32-bit integer numbers) +/// and `c` (four signed 32-bit integer numbers) in to vector `a` +/// (four signed 32-bit integer numbers) based on the corresponding control element in `a` +/// The least significant 6 bits in `a` control elements modulo the number of elements in +/// the concatenated vectors `b`, `a` specify the index of the source element. /// If bit 6 or bit 7 is 1, there will be no copy, but rather the destination elementis set to 0. /// #[inline] @@ -9180,11 +9180,11 @@ pub unsafe fn __msa_vshf_w(a: v4i32, b: v4i32, c: v4i32) -> v4i32 { /// Vector Data Preserving Shuffle /// /// The vector shuffle instructions selectively copy data elements from the -/// concatenation of vectors 'b' (two signed 64-bit integer numbers) -/// and `c` (two signed 64-bit integer numbers) in to vector 'a' -/// (two signed 64-bit integer numbers) based on the corresponding control element in 'a' -/// The least significant 6 bits in 'a' control elements modulo the number of elements in -/// the concatenated vectors 'b','a' specify the index of the source element. +/// concatenation of vectors `b` (two signed 64-bit integer numbers) +/// and `c` (two signed 64-bit integer numbers) in to vector `a` +/// (two signed 64-bit integer numbers) based on the corresponding control element in `a` +/// The least significant 6 bits in `a` control elements modulo the number of elements in +/// the concatenated vectors `b`, `a` specify the index of the source element. /// If bit 6 or bit 7 is 1, there will be no copy, but rather the destination elementis set to 0. /// #[inline] @@ -9196,8 +9196,8 @@ pub unsafe fn __msa_vshf_d(a: v2i64, b: v2i64, c: v2i64) -> v2i64 { /// Vector Logical Exclusive Or /// -/// Each bit of vector 'a'(sixteen unsigned 8-bit integer numbers) -/// is combined with the corresponding bit of vector 'b' (sixteen unsigned 8-bit integer numbers) +/// Each bit of vector `a` (sixteen unsigned 8-bit integer numbers) +/// is combined with the corresponding bit of vector `b` (sixteen unsigned 8-bit integer numbers) /// in a bitwise logical XOR operation. The result is written to vector /// (sixteen unsigned 8-bit integer numbers) /// @@ -9210,7 +9210,7 @@ pub unsafe fn __msa_xor_v(a: v16u8, b: v16u8) -> v16u8 { /// Immediate Logical Exclusive Or /// -/// Each byte of vector 'a'(sixteen unsigned 8-bit integer numbers) +/// Each byte of vector `a` (sixteen unsigned 8-bit integer numbers) /// is combined with the 8-bit immediate imm8 /// in a bitwise logical XOR operation. The result is written to vector /// (sixteen unsigned 8-bit integer numbers) @@ -11417,7 +11417,7 @@ mod tests { // FIXME: https://reviews.llvm.org/D59884 // If target type is i64, negative immediate loses the sign - // Test passes if 4294967293 is used instead -3 in vector 'a' + // Test passes if 4294967293 is used instead -3 in vector `a` // #[simd_test(enable = "msa")] // unsafe fn test_msa_ceqi_d() { // #[rustfmt::skip] @@ -14880,7 +14880,7 @@ mod tests { // FIXME: https://reviews.llvm.org/D59884 // If target type is i64, negative immediate loses the sign - // Test passes if 4294967185 is used instead -111 in vector 'r' + // Test passes if 4294967185 is used instead -111 in vector `r` // #[simd_test(enable = "msa")] // unsafe fn test_msa_ldi_d() { // let r = i64x2::new(-111, -111); @@ -15361,7 +15361,7 @@ mod tests { // FIXME: https://reviews.llvm.org/D59884 // If target type is i64, negative immediate loses the sign - // Test passes if 4294967293 is used instead -3 in vector 'r' + // Test passes if 4294967293 is used instead -3 in vector `r` // #[simd_test(enable = "msa")] // unsafe fn test_msa_maxi_s_d() { // #[rustfmt::skip] diff --git a/library/stdarch/crates/core_arch/src/x86/avx.rs b/library/stdarch/crates/core_arch/src/x86/avx.rs index 56067ba5c93f..20f95d94971c 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx.rs @@ -1913,7 +1913,7 @@ pub unsafe fn _mm256_moveldup_ps(a: __m256) -> __m256 { } /// Duplicate even-indexed double-precision (64-bit) floating-point elements -/// from "a", and returns the results. +/// from `a`, and returns the results. /// /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_movedup_pd) #[inline] diff --git a/library/stdarch/crates/core_arch/src/x86/sse2.rs b/library/stdarch/crates/core_arch/src/x86/sse2.rs index 21a3b4a08161..0408c5ae07f9 100644 --- a/library/stdarch/crates/core_arch/src/x86/sse2.rs +++ b/library/stdarch/crates/core_arch/src/x86/sse2.rs @@ -2315,7 +2315,7 @@ pub unsafe fn _mm_ucomineq_sd(a: __m128d, b: __m128d) -> i32 { ucomineqsd(a, b) } -/// Converts packed double-precision (64-bit) floating-point elements in "a" to +/// Converts packed double-precision (64-bit) floating-point elements in `a` to /// packed single-precision (32-bit) floating-point elements /// /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtpd_ps) @@ -2378,7 +2378,7 @@ pub unsafe fn _mm_cvtsd_ss(a: __m128, b: __m128d) -> __m128 { cvtsd2ss(a, b) } -/// Returns the lower double-precision (64-bit) floating-point element of "a". +/// Returns the lower double-precision (64-bit) floating-point element of `a`. /// /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsd_f64) #[inline]