From 3970825b9272411c665bba95bc30894299c8520e Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Wed, 30 Mar 2022 16:20:58 +0200 Subject: [PATCH] Add intrinsic translation for x86 arch --- src/intrinsic/llvm.rs | 135 +------- src/intrinsic/x86.rs | 770 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 777 insertions(+), 128 deletions(-) create mode 100644 src/intrinsic/x86.rs diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 7634c649bc34..e6d8f78da603 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -3,134 +3,13 @@ use gccjit::Function; use crate::context::CodegenCx; pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function<'gcc> { - let gcc_name = - match name { - "llvm.x86.xgetbv" => "__builtin_ia32_xgetbv", - // NOTE: this doc specifies the equivalent GCC builtins: http://huonw.github.io/llvmint/llvmint/x86/index.html - "llvm.x86.sse2.pmovmskb.128" => "__builtin_ia32_pmovmskb128", - "llvm.x86.avx2.pmovmskb" => "__builtin_ia32_pmovmskb256", - "llvm.x86.sse2.cmp.pd" => "__builtin_ia32_cmppd", - "llvm.x86.sse2.movmsk.pd" => "__builtin_ia32_movmskpd", - "llvm.x86.ssse3.pshuf.b.128" => "__builtin_ia32_pshufb128", - "llvm.x86.sse2.pause" => "__builtin_ia32_pause", - "llvm.x86.avx2.pshuf.b" => "__builtin_ia32_pshufb256", - "llvm.x86.avx2.pslli.d" => "__builtin_ia32_pslldi256", - "llvm.x86.avx2.psrli.d" => "__builtin_ia32_psrldi256", - "llvm.x86.sse2.pslli.q" => "__builtin_ia32_psllqi128", - "llvm.x86.avx.vzeroupper" => "__builtin_ia32_vzeroupper", - "llvm.x86.avx2.vperm2i128" => "__builtin_ia32_permti256", - "llvm.x86.avx2.psrli.w" => "__builtin_ia32_psrlwi256", - "llvm.x86.sse2.storeu.dq" => "__builtin_ia32_storedqu", - "llvm.x86.sse2.psrli.w" => "__builtin_ia32_psrlwi128", - "llvm.x86.avx2.pabs.d" => "__builtin_ia32_pabsd256", - "llvm.x86.sse2.psrli.q" => "__builtin_ia32_psrlqi128", - "llvm.x86.avx2.pabs.w" => "__builtin_ia32_pabsw256", - "llvm.x86.avx2.pblendvb" => "__builtin_ia32_pblendvb256", - "llvm.x86.avx2.pabs.b" => "__builtin_ia32_pabsb256", - "llvm.x86.avx2.psrli.q" => "__builtin_ia32_psrlqi256", - "llvm.x86.sse41.pblendvb" => "__builtin_ia32_pblendvb128", - "llvm.x86.sse41.pblendw" => "__builtin_ia32_pblendw128", - "llvm.x86.sse42.crc32.32.8" => "__builtin_ia32_crc32qi", - "llvm.x86.sse42.crc32.32.16" => "__builtin_ia32_crc32hi", - "llvm.x86.sse42.crc32.32.32" => "__builtin_ia32_crc32si", - "llvm.x86.sse42.crc32.64.64" => "__builtin_ia32_crc32di", - "llvm.x86.avx2.pavg.w" => "__builtin_ia32_pavgw256", - "llvm.x86.avx2.pavg.b" => "__builtin_ia32_pavgb256", - "llvm.x86.avx2.phadd.w" => "__builtin_ia32_phaddw256", - "llvm.x86.avx2.phadd.d" => "__builtin_ia32_phaddd256", - "llvm.x86.avx2.phadd.sw" => "__builtin_ia32_phaddsw256", - "llvm.x86.avx2.phsub.w" => "__builtin_ia32_phsubw256", - "llvm.x86.avx2.phsub.d" => "__builtin_ia32_phsubd256", - "llvm.x86.avx2.phsub.sw" => "__builtin_ia32_phsubsw256", - "llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gatherd_d", - "llvm.x86.avx2.gather.d.d.256" => "__builtin_ia32_gatherd_d256", - "llvm.x86.avx2.gather.d.ps" => "__builtin_ia32_gatherd_ps", - "llvm.x86.avx2.gather.d.ps.256" => "__builtin_ia32_gatherd_ps256", - "llvm.x86.avx2.gather.d.q" => "__builtin_ia32_gatherd_q", - "llvm.x86.avx2.gather.d.q.256" => "__builtin_ia32_gatherd_q256", - "llvm.x86.avx2.gather.d.pd" => "__builtin_ia32_gatherd_pd", - "llvm.x86.avx2.gather.d.pd.256" => "__builtin_ia32_gatherd_pd256", - "llvm.x86.avx2.gather.q.d" => "__builtin_ia32_gatherq_d", - "llvm.x86.avx2.gather.q.d.256" => "__builtin_ia32_gatherq_d256", - "llvm.x86.avx2.gather.q.ps" => "__builtin_ia32_gatherq_ps", - "llvm.x86.avx2.gather.q.ps.256" => "__builtin_ia32_gatherq_ps256", - "llvm.x86.avx2.gather.q.q" => "__builtin_ia32_gatherq_q", - "llvm.x86.avx2.gather.q.q.256" => "__builtin_ia32_gatherq_q256", - "llvm.x86.avx2.gather.q.pd" => "__builtin_ia32_gatherq_pd", - "llvm.x86.avx2.gather.q.pd.256" => "__builtin_ia32_gatherq_pd256", - "llvm.x86.avx2.pmadd.wd" => "__builtin_ia32_pmaddwd256", - "llvm.x86.avx2.pmadd.ub.sw" => "__builtin_ia32_pmaddubsw256", - "llvm.x86.avx2.maskload.d" => "__builtin_ia32_maskloadd", - "llvm.x86.avx2.maskload.d.256" => "__builtin_ia32_maskloadd256", - "llvm.x86.avx2.maskload.q" => "__builtin_ia32_maskloadq", - "llvm.x86.avx2.maskload.q.256" => "__builtin_ia32_maskloadq256", - "llvm.x86.avx2.maskstore.d" => "__builtin_ia32_maskstored", - "llvm.x86.avx2.maskstore.d.256" => "__builtin_ia32_maskstored256", - "llvm.x86.avx2.maskstore.q" => "__builtin_ia32_maskstoreq", - "llvm.x86.avx2.maskstore.q.256" => "__builtin_ia32_maskstoreq256", - "llvm.x86.avx2.pmaxs.w" => "__builtin_ia32_pmaxsw256", - "llvm.x86.avx2.pmaxs.d" => "__builtin_ia32_pmaxsd256", - "llvm.x86.avx2.pmaxs.b" => "__builtin_ia32_pmaxsb256", - "llvm.x86.avx2.pmaxu.w" => "__builtin_ia32_pmaxuw256", - "llvm.x86.avx2.pmaxu.d" => "__builtin_ia32_pmaxud256", - "llvm.x86.avx2.pmaxu.b" => "__builtin_ia32_pmaxub256", - "llvm.x86.avx2.pmins.w" => "__builtin_ia32_pminsw256", - "llvm.x86.avx2.pmins.d" => "__builtin_ia32_pminsd256", - "llvm.x86.avx2.pmins.b" => "__builtin_ia32_pminsb256", - "llvm.x86.avx2.pminu.w" => "__builtin_ia32_pminuw256", - "llvm.x86.avx2.pminu.d" => "__builtin_ia32_pminud256", - "llvm.x86.avx2.pminu.b" => "__builtin_ia32_pminub256", - "llvm.x86.avx2.mpsadbw" => "__builtin_ia32_mpsadbw256", - "llvm.x86.avx2.pmul.dq" => "__builtin_ia32_pmuldq256", - "llvm.x86.avx2.pmulu.dq" => "__builtin_ia32_pmuludq256", - "llvm.x86.avx2.pmulh.w" => "__builtin_ia32_pmulhw256", - "llvm.x86.avx2.pmulhu.w" => "__builtin_ia32_pmulhuw256", - "llvm.x86.avx2.pmul.hr.sw" => "__builtin_ia32_pmulhrsw256", - "llvm.x86.avx2.packsswb" => "__builtin_ia32_packsswb256", - "llvm.x86.avx2.packssdw" => "__builtin_ia32_packssdw256", - "llvm.x86.avx2.packuswb" => "__builtin_ia32_packuswb256", - "llvm.x86.avx2.packusdw" => "__builtin_ia32_packusdw256", - "llvm.x86.avx2.permd" => "__builtin_ia32_permvarsi256", - "llvm.x86.avx2.permps" => "__builtin_ia32_permvarsf256", - "llvm.x86.avx2.psad.bw" => "__builtin_ia32_psadbw256", - "llvm.x86.avx2.psign.w" => "__builtin_ia32_psignw256", - "llvm.x86.avx2.psign.d" => "__builtin_ia32_psignd256", - "llvm.x86.avx2.psign.b" => "__builtin_ia32_psignb256", - "llvm.x86.avx2.psll.w" => "__builtin_ia32_psllw256", - "llvm.x86.avx2.psll.d" => "__builtin_ia32_pslld256", - "llvm.x86.avx2.psll.q" => "__builtin_ia32_psllq256", - "llvm.x86.avx2.pslli.w" => "__builtin_ia32_psllwi256", - "llvm.x86.avx2.pslli.q" => "__builtin_ia32_psllqi256", - "llvm.x86.avx2.psllv.d" => "__builtin_ia32_psllv4si", - "llvm.x86.avx2.psllv.d.256" => "__builtin_ia32_psllv8si", - "llvm.x86.avx2.psllv.q" => "__builtin_ia32_psllv2di", - "llvm.x86.avx2.psllv.q.256" => "__builtin_ia32_psllv4di", - "llvm.x86.avx2.psra.w" => "__builtin_ia32_psraw256", - "llvm.x86.avx2.psra.d" => "__builtin_ia32_psrad256", - "llvm.x86.avx2.psrai.w" => "__builtin_ia32_psrawi256", - "llvm.x86.avx2.psrai.d" => "__builtin_ia32_psradi256", - "llvm.x86.avx2.psrav.d" => "__builtin_ia32_psrav4si", - "llvm.x86.avx2.psrav.d.256" => "__builtin_ia32_psrav8si", - "llvm.x86.avx2.psrl.w" => "__builtin_ia32_psrlw256", - "llvm.x86.avx2.psrl.d" => "__builtin_ia32_psrld256", - "llvm.x86.avx2.psrl.q" => "__builtin_ia32_psrlq256", - "llvm.x86.avx2.psrlv.d" => "__builtin_ia32_psrlv4si", - "llvm.x86.avx2.psrlv.d.256" => "__builtin_ia32_psrlv8si", - "llvm.x86.avx2.psrlv.q" => "__builtin_ia32_psrlv2di", - "llvm.x86.avx2.psrlv.q.256" => "__builtin_ia32_psrlv4di", - "llvm.x86.sse.sqrt.ss" => "__builtin_ia32_sqrtss", - "llvm.x86.pclmulqdq" => "__builtin_ia32_pclmulqdq128", - "llvm.x86.sha1msg1" => "__builtin_ia32_sha1msg1", - "llvm.x86.sha1msg2" => "__builtin_ia32_sha1msg2", - "llvm.x86.sha1nexte" => "__builtin_ia32_sha1nexte", - "llvm.x86.sha1rnds4" => "__builtin_ia32_sha1rnds4", - "llvm.x86.sha256msg1" => "__builtin_ia32_sha256msg1", - "llvm.x86.sha256msg2" => "__builtin_ia32_sha256msg2", - "llvm.x86.sha256rnds2" => "__builtin_ia32_sha256rnds2", - - "llvm.sqrt.v2f64" => "__builtin_ia32_sqrtpd", - _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), - }; + let gcc_name = match name { + "llvm.x86.xgetbv" => "__builtin_ia32_xgetbv", + // NOTE: this doc specifies the equivalent GCC builtins: http://huonw.github.io/llvmint/llvmint/x86/index.html + "llvm.sqrt.v2f64" => "__builtin_ia32_sqrtpd", + // NOTE: this file is generated by https://github.com/GuillaumeGomez/llvmint/blob/master/generate_list.py + _ => include!("x86.rs"), + }; let func = cx.context.get_target_builtin_function(gcc_name); cx.functions.borrow_mut().insert(gcc_name.to_string(), func); diff --git a/src/intrinsic/x86.rs b/src/intrinsic/x86.rs new file mode 100644 index 000000000000..4918325e74c8 --- /dev/null +++ b/src/intrinsic/x86.rs @@ -0,0 +1,770 @@ +match name { +// x86 +"llvm.x86.addcarry.u32" => "__builtin_ia32_addcarry_u32", +"llvm.x86.addcarry.u64" => "__builtin_ia32_addcarry_u64", +"llvm.x86.addcarryx.u32" => "__builtin_ia32_addcarryx_u32", +"llvm.x86.addcarryx.u64" => "__builtin_ia32_addcarryx_u64", +"llvm.x86.aesni.aesdec" => "__builtin_ia32_aesdec128", +"llvm.x86.aesni.aesdeclast" => "__builtin_ia32_aesdeclast128", +"llvm.x86.aesni.aesenc" => "__builtin_ia32_aesenc128", +"llvm.x86.aesni.aesenclast" => "__builtin_ia32_aesenclast128", +"llvm.x86.aesni.aesimc" => "__builtin_ia32_aesimc128", +"llvm.x86.aesni.aeskeygenassist" => "__builtin_ia32_aeskeygenassist128", +"llvm.x86.avx.addsub.pd.256" => "__builtin_ia32_addsubpd256", +"llvm.x86.avx.addsub.ps.256" => "__builtin_ia32_addsubps256", +"llvm.x86.avx.blend.pd.256" => "__builtin_ia32_blendpd256", +"llvm.x86.avx.blend.ps.256" => "__builtin_ia32_blendps256", +"llvm.x86.avx.blendv.pd.256" => "__builtin_ia32_blendvpd256", +"llvm.x86.avx.blendv.ps.256" => "__builtin_ia32_blendvps256", +"llvm.x86.avx.cmp.pd.256" => "__builtin_ia32_cmppd256", +"llvm.x86.avx.cmp.ps.256" => "__builtin_ia32_cmpps256", +"llvm.x86.avx.cvt.pd2.ps.256" => "__builtin_ia32_cvtpd2ps256", +"llvm.x86.avx.cvt.pd2dq.256" => "__builtin_ia32_cvtpd2dq256", +"llvm.x86.avx.cvt.ps2.pd.256" => "__builtin_ia32_cvtps2pd256", +"llvm.x86.avx.cvt.ps2dq.256" => "__builtin_ia32_cvtps2dq256", +"llvm.x86.avx.cvtdq2.pd.256" => "__builtin_ia32_cvtdq2pd256", +"llvm.x86.avx.cvtdq2.ps.256" => "__builtin_ia32_cvtdq2ps256", +"llvm.x86.avx.cvtt.pd2dq.256" => "__builtin_ia32_cvttpd2dq256", +"llvm.x86.avx.cvtt.ps2dq.256" => "__builtin_ia32_cvttps2dq256", +"llvm.x86.avx.dp.ps.256" => "__builtin_ia32_dpps256", +"llvm.x86.avx.hadd.pd.256" => "__builtin_ia32_haddpd256", +"llvm.x86.avx.hadd.ps.256" => "__builtin_ia32_haddps256", +"llvm.x86.avx.hsub.pd.256" => "__builtin_ia32_hsubpd256", +"llvm.x86.avx.hsub.ps.256" => "__builtin_ia32_hsubps256", +"llvm.x86.avx.ldu.dq.256" => "__builtin_ia32_lddqu256", +"llvm.x86.avx.maskload.pd" => "__builtin_ia32_maskloadpd", +"llvm.x86.avx.maskload.pd.256" => "__builtin_ia32_maskloadpd256", +"llvm.x86.avx.maskload.ps" => "__builtin_ia32_maskloadps", +"llvm.x86.avx.maskload.ps.256" => "__builtin_ia32_maskloadps256", +"llvm.x86.avx.maskstore.pd" => "__builtin_ia32_maskstorepd", +"llvm.x86.avx.maskstore.pd.256" => "__builtin_ia32_maskstorepd256", +"llvm.x86.avx.maskstore.ps" => "__builtin_ia32_maskstoreps", +"llvm.x86.avx.maskstore.ps.256" => "__builtin_ia32_maskstoreps256", +"llvm.x86.avx.max.pd.256" => "__builtin_ia32_maxpd256", +"llvm.x86.avx.max.ps.256" => "__builtin_ia32_maxps256", +"llvm.x86.avx.min.pd.256" => "__builtin_ia32_minpd256", +"llvm.x86.avx.min.ps.256" => "__builtin_ia32_minps256", +"llvm.x86.avx.movmsk.pd.256" => "__builtin_ia32_movmskpd256", +"llvm.x86.avx.movmsk.ps.256" => "__builtin_ia32_movmskps256", +"llvm.x86.avx.ptestc.256" => "__builtin_ia32_ptestc256", +"llvm.x86.avx.ptestnzc.256" => "__builtin_ia32_ptestnzc256", +"llvm.x86.avx.ptestz.256" => "__builtin_ia32_ptestz256", +"llvm.x86.avx.rcp.ps.256" => "__builtin_ia32_rcpps256", +"llvm.x86.avx.round.pd.256" => "__builtin_ia32_roundpd256", +"llvm.x86.avx.round.ps.256" => "__builtin_ia32_roundps256", +"llvm.x86.avx.rsqrt.ps.256" => "__builtin_ia32_rsqrtps256", +"llvm.x86.avx.sqrt.pd.256" => "__builtin_ia32_sqrtpd256", +"llvm.x86.avx.sqrt.ps.256" => "__builtin_ia32_sqrtps256", +"llvm.x86.avx.storeu.dq.256" => "__builtin_ia32_storedqu256", +"llvm.x86.avx.storeu.pd.256" => "__builtin_ia32_storeupd256", +"llvm.x86.avx.storeu.ps.256" => "__builtin_ia32_storeups256", +"llvm.x86.avx.vbroadcastf128.pd.256" => "__builtin_ia32_vbroadcastf128_pd256", +"llvm.x86.avx.vbroadcastf128.ps.256" => "__builtin_ia32_vbroadcastf128_ps256", +"llvm.x86.avx.vextractf128.pd.256" => "__builtin_ia32_vextractf128_pd256", +"llvm.x86.avx.vextractf128.ps.256" => "__builtin_ia32_vextractf128_ps256", +"llvm.x86.avx.vextractf128.si.256" => "__builtin_ia32_vextractf128_si256", +"llvm.x86.avx.vinsertf128.pd.256" => "__builtin_ia32_vinsertf128_pd256", +"llvm.x86.avx.vinsertf128.ps.256" => "__builtin_ia32_vinsertf128_ps256", +"llvm.x86.avx.vinsertf128.si.256" => "__builtin_ia32_vinsertf128_si256", +"llvm.x86.avx.vperm2f128.pd.256" => "__builtin_ia32_vperm2f128_pd256", +"llvm.x86.avx.vperm2f128.ps.256" => "__builtin_ia32_vperm2f128_ps256", +"llvm.x86.avx.vperm2f128.si.256" => "__builtin_ia32_vperm2f128_si256", +"llvm.x86.avx.vpermilvar.pd" => "__builtin_ia32_vpermilvarpd", +"llvm.x86.avx.vpermilvar.pd.256" => "__builtin_ia32_vpermilvarpd256", +"llvm.x86.avx.vpermilvar.ps" => "__builtin_ia32_vpermilvarps", +"llvm.x86.avx.vpermilvar.ps.256" => "__builtin_ia32_vpermilvarps256", +"llvm.x86.avx.vtestc.pd" => "__builtin_ia32_vtestcpd", +"llvm.x86.avx.vtestc.pd.256" => "__builtin_ia32_vtestcpd256", +"llvm.x86.avx.vtestc.ps" => "__builtin_ia32_vtestcps", +"llvm.x86.avx.vtestc.ps.256" => "__builtin_ia32_vtestcps256", +"llvm.x86.avx.vtestnzc.pd" => "__builtin_ia32_vtestnzcpd", +"llvm.x86.avx.vtestnzc.pd.256" => "__builtin_ia32_vtestnzcpd256", +"llvm.x86.avx.vtestnzc.ps" => "__builtin_ia32_vtestnzcps", +"llvm.x86.avx.vtestnzc.ps.256" => "__builtin_ia32_vtestnzcps256", +"llvm.x86.avx.vtestz.pd" => "__builtin_ia32_vtestzpd", +"llvm.x86.avx.vtestz.pd.256" => "__builtin_ia32_vtestzpd256", +"llvm.x86.avx.vtestz.ps" => "__builtin_ia32_vtestzps", +"llvm.x86.avx.vtestz.ps.256" => "__builtin_ia32_vtestzps256", +"llvm.x86.avx.vzeroall" => "__builtin_ia32_vzeroall", +"llvm.x86.avx.vzeroupper" => "__builtin_ia32_vzeroupper", +"llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gatherd_d", +"llvm.x86.avx2.gather.d.d.256" => "__builtin_ia32_gatherd_d256", +"llvm.x86.avx2.gather.d.pd" => "__builtin_ia32_gatherd_pd", +"llvm.x86.avx2.gather.d.pd.256" => "__builtin_ia32_gatherd_pd256", +"llvm.x86.avx2.gather.d.ps" => "__builtin_ia32_gatherd_ps", +"llvm.x86.avx2.gather.d.ps.256" => "__builtin_ia32_gatherd_ps256", +"llvm.x86.avx2.gather.d.q" => "__builtin_ia32_gatherd_q", +"llvm.x86.avx2.gather.d.q.256" => "__builtin_ia32_gatherd_q256", +"llvm.x86.avx2.gather.q.d" => "__builtin_ia32_gatherq_d", +"llvm.x86.avx2.gather.q.d.256" => "__builtin_ia32_gatherq_d256", +"llvm.x86.avx2.gather.q.pd" => "__builtin_ia32_gatherq_pd", +"llvm.x86.avx2.gather.q.pd.256" => "__builtin_ia32_gatherq_pd256", +"llvm.x86.avx2.gather.q.ps" => "__builtin_ia32_gatherq_ps", +"llvm.x86.avx2.gather.q.ps.256" => "__builtin_ia32_gatherq_ps256", +"llvm.x86.avx2.gather.q.q" => "__builtin_ia32_gatherq_q", +"llvm.x86.avx2.gather.q.q.256" => "__builtin_ia32_gatherq_q256", +"llvm.x86.avx2.maskload.d" => "__builtin_ia32_maskloadd", +"llvm.x86.avx2.maskload.d.256" => "__builtin_ia32_maskloadd256", +"llvm.x86.avx2.maskload.q" => "__builtin_ia32_maskloadq", +"llvm.x86.avx2.maskload.q.256" => "__builtin_ia32_maskloadq256", +"llvm.x86.avx2.maskstore.d" => "__builtin_ia32_maskstored", +"llvm.x86.avx2.maskstore.d.256" => "__builtin_ia32_maskstored256", +"llvm.x86.avx2.maskstore.q" => "__builtin_ia32_maskstoreq", +"llvm.x86.avx2.maskstore.q.256" => "__builtin_ia32_maskstoreq256", +"llvm.x86.avx2.movntdqa" => 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"__builtin_ia32_blendmq_512_mask", +"llvm.x86.avx512.mask.cmp.pd.512" => "__builtin_ia32_cmppd512_mask", +"llvm.x86.avx512.mask.cmp.ps.512" => "__builtin_ia32_cmpps512_mask", +"llvm.x86.avx512.mask.conflict.d.512" => "__builtin_ia32_vpconflictsi_512_mask", +"llvm.x86.avx512.mask.conflict.q.512" => "__builtin_ia32_vpconflictdi_512_mask", +"llvm.x86.avx512.mask.cvtdq2pd.512" => "__builtin_ia32_cvtdq2pd512_mask", +"llvm.x86.avx512.mask.cvtdq2ps.512" => "__builtin_ia32_cvtdq2ps512_mask", +"llvm.x86.avx512.mask.cvtpd2dq.512" => "__builtin_ia32_cvtpd2dq512_mask", +"llvm.x86.avx512.mask.cvtpd2ps.512" => "__builtin_ia32_cvtpd2ps512_mask", +"llvm.x86.avx512.mask.cvtpd2udq.512" => "__builtin_ia32_cvtpd2udq512_mask", +"llvm.x86.avx512.mask.cvtps2dq.512" => "__builtin_ia32_cvtps2dq512_mask", +"llvm.x86.avx512.mask.cvtps2udq.512" => "__builtin_ia32_cvtps2udq512_mask", +"llvm.x86.avx512.mask.cvttpd2dq.512" => "__builtin_ia32_cvttpd2dq512_mask", +"llvm.x86.avx512.mask.cvttpd2udq.512" => "__builtin_ia32_cvttpd2udq512_mask", +"llvm.x86.avx512.mask.cvttps2dq.512" => "__builtin_ia32_cvttps2dq512_mask", +"llvm.x86.avx512.mask.cvttps2udq.512" => "__builtin_ia32_cvttps2udq512_mask", +"llvm.x86.avx512.mask.cvtudq2pd.512" => "__builtin_ia32_cvtudq2pd512_mask", +"llvm.x86.avx512.mask.cvtudq2ps.512" => "__builtin_ia32_cvtudq2ps512_mask", +"llvm.x86.avx512.mask.loadu.d.512" => "__builtin_ia32_loaddqusi512_mask", +"llvm.x86.avx512.mask.loadu.pd.512" => "__builtin_ia32_loadupd512_mask", +"llvm.x86.avx512.mask.loadu.ps.512" => "__builtin_ia32_loadups512_mask", +"llvm.x86.avx512.mask.loadu.q.512" => "__builtin_ia32_loaddqudi512_mask", +"llvm.x86.avx512.mask.lzcnt.d.512" => "__builtin_ia32_vplzcntd_512_mask", +"llvm.x86.avx512.mask.lzcnt.q.512" => "__builtin_ia32_vplzcntq_512_mask", +"llvm.x86.avx512.mask.max.pd.512" => "__builtin_ia32_maxpd512_mask", +"llvm.x86.avx512.mask.max.ps.512" => "__builtin_ia32_maxps512_mask", +"llvm.x86.avx512.mask.min.pd.512" => "__builtin_ia32_minpd512_mask", +"llvm.x86.avx512.mask.min.ps.512" => "__builtin_ia32_minps512_mask", +"llvm.x86.avx512.mask.pabs.d.512" => "__builtin_ia32_pabsd512_mask", +"llvm.x86.avx512.mask.pabs.q.512" => "__builtin_ia32_pabsq512_mask", +"llvm.x86.avx512.mask.pand.d.512" => "__builtin_ia32_pandd512_mask", +"llvm.x86.avx512.mask.pand.q.512" => "__builtin_ia32_pandq512_mask", +"llvm.x86.avx512.mask.pbroadcast.d.gpr.512" => "__builtin_ia32_pbroadcastd512_gpr_mask", +"llvm.x86.avx512.mask.pbroadcast.q.gpr.512" => "__builtin_ia32_pbroadcastq512_gpr_mask", +"llvm.x86.avx512.mask.pbroadcast.q.mem.512" => "__builtin_ia32_pbroadcastq512_mem_mask", +"llvm.x86.avx512.mask.pcmpeq.b.128" => "__builtin_ia32_pcmpeqb128_mask", +"llvm.x86.avx512.mask.pcmpeq.b.256" => "__builtin_ia32_pcmpeqb256_mask", +"llvm.x86.avx512.mask.pcmpeq.b.512" => "__builtin_ia32_pcmpeqb512_mask", +"llvm.x86.avx512.mask.pcmpeq.d.128" => "__builtin_ia32_pcmpeqd128_mask", +"llvm.x86.avx512.mask.pcmpeq.d.256" => "__builtin_ia32_pcmpeqd256_mask", +"llvm.x86.avx512.mask.pcmpeq.d.512" => "__builtin_ia32_pcmpeqd512_mask", +"llvm.x86.avx512.mask.pcmpeq.q.128" => "__builtin_ia32_pcmpeqq128_mask", +"llvm.x86.avx512.mask.pcmpeq.q.256" => "__builtin_ia32_pcmpeqq256_mask", +"llvm.x86.avx512.mask.pcmpeq.q.512" => "__builtin_ia32_pcmpeqq512_mask", +"llvm.x86.avx512.mask.pcmpeq.w.128" => "__builtin_ia32_pcmpeqw128_mask", +"llvm.x86.avx512.mask.pcmpeq.w.256" => "__builtin_ia32_pcmpeqw256_mask", +"llvm.x86.avx512.mask.pcmpeq.w.512" => "__builtin_ia32_pcmpeqw512_mask", +"llvm.x86.avx512.mask.pcmpgt.b.128" => "__builtin_ia32_pcmpgtb128_mask", +"llvm.x86.avx512.mask.pcmpgt.b.256" => "__builtin_ia32_pcmpgtb256_mask", +"llvm.x86.avx512.mask.pcmpgt.b.512" => "__builtin_ia32_pcmpgtb512_mask", +"llvm.x86.avx512.mask.pcmpgt.d.128" => "__builtin_ia32_pcmpgtd128_mask", +"llvm.x86.avx512.mask.pcmpgt.d.256" => "__builtin_ia32_pcmpgtd256_mask", +"llvm.x86.avx512.mask.pcmpgt.d.512" => "__builtin_ia32_pcmpgtd512_mask", +"llvm.x86.avx512.mask.pcmpgt.q.128" => "__builtin_ia32_pcmpgtq128_mask", +"llvm.x86.avx512.mask.pcmpgt.q.256" => "__builtin_ia32_pcmpgtq256_mask", +"llvm.x86.avx512.mask.pcmpgt.q.512" => "__builtin_ia32_pcmpgtq512_mask", +"llvm.x86.avx512.mask.pcmpgt.w.128" => "__builtin_ia32_pcmpgtw128_mask", +"llvm.x86.avx512.mask.pcmpgt.w.256" => "__builtin_ia32_pcmpgtw256_mask", +"llvm.x86.avx512.mask.pcmpgt.w.512" => "__builtin_ia32_pcmpgtw512_mask", +"llvm.x86.avx512.mask.pmaxs.d.512" => "__builtin_ia32_pmaxsd512_mask", +"llvm.x86.avx512.mask.pmaxs.q.512" => "__builtin_ia32_pmaxsq512_mask", +"llvm.x86.avx512.mask.pmaxu.d.512" => "__builtin_ia32_pmaxud512_mask", +"llvm.x86.avx512.mask.pmaxu.q.512" => "__builtin_ia32_pmaxuq512_mask", +"llvm.x86.avx512.mask.pmins.d.512" => "__builtin_ia32_pminsd512_mask", +"llvm.x86.avx512.mask.pmins.q.512" => "__builtin_ia32_pminsq512_mask", +"llvm.x86.avx512.mask.pminu.d.512" => "__builtin_ia32_pminud512_mask", +"llvm.x86.avx512.mask.pminu.q.512" => "__builtin_ia32_pminuq512_mask", +"llvm.x86.avx512.mask.pmul.dq.512" => "__builtin_ia32_pmuldq512_mask", +"llvm.x86.avx512.mask.pmulu.dq.512" => "__builtin_ia32_pmuludq512_mask", +"llvm.x86.avx512.mask.ptestm.d.512" => "__builtin_ia32_ptestmd512", +"llvm.x86.avx512.mask.ptestm.q.512" => "__builtin_ia32_ptestmq512", +"llvm.x86.avx512.mask.rndscale.pd.512" => "__builtin_ia32_rndscalepd_mask", +"llvm.x86.avx512.mask.rndscale.ps.512" => "__builtin_ia32_rndscaleps_mask", +"llvm.x86.avx512.mask.store.ss" => "__builtin_ia32_storess_mask", +"llvm.x86.avx512.mask.storeu.d.512" => "__builtin_ia32_storedqusi512_mask", +"llvm.x86.avx512.mask.storeu.pd.512" => "__builtin_ia32_storeupd512_mask", +"llvm.x86.avx512.mask.storeu.ps.512" => "__builtin_ia32_storeups512_mask", +"llvm.x86.avx512.mask.storeu.q.512" => "__builtin_ia32_storedqudi512_mask", +"llvm.x86.avx512.mask.valign.d.512" => "__builtin_ia32_alignd512_mask", +"llvm.x86.avx512.mask.valign.q.512" => "__builtin_ia32_alignq512_mask", +"llvm.x86.avx512.mask.vcvtph2ps.512" => "__builtin_ia32_vcvtph2ps512_mask", +"llvm.x86.avx512.mask.vcvtps2ph.512" => "__builtin_ia32_vcvtps2ph512_mask", +"llvm.x86.avx512.mask.vpermt.d.512" => "__builtin_ia32_vpermt2vard512_mask", +"llvm.x86.avx512.mask.vpermt.pd.512" => "__builtin_ia32_vpermt2varpd512_mask", +"llvm.x86.avx512.mask.vpermt.ps.512" => "__builtin_ia32_vpermt2varps512_mask", +"llvm.x86.avx512.mask.vpermt.q.512" => "__builtin_ia32_vpermt2varq512_mask", +"llvm.x86.avx512.movntdqa" => "__builtin_ia32_movntdqa512", +"llvm.x86.avx512.pbroadcastd.512" => "__builtin_ia32_pbroadcastd512", +"llvm.x86.avx512.pbroadcastq.512" => "__builtin_ia32_pbroadcastq512", +"llvm.x86.avx512.pmovzxbd" => "__builtin_ia32_pmovzxbd512", +"llvm.x86.avx512.pmovzxbq" => "__builtin_ia32_pmovzxbq512", +"llvm.x86.avx512.pmovzxdq" => "__builtin_ia32_pmovzxdq512", +"llvm.x86.avx512.pmovzxwd" => "__builtin_ia32_pmovzxwd512", +"llvm.x86.avx512.pmovzxwq" => "__builtin_ia32_pmovzxwq512", +"llvm.x86.avx512.psll.dq" => "__builtin_ia32_pslldqi512", +"llvm.x86.avx512.psll.dq.bs" => "__builtin_ia32_pslldqi512_byteshift", +"llvm.x86.avx512.psrl.dq" => "__builtin_ia32_psrldqi512", +"llvm.x86.avx512.psrl.dq.bs" => "__builtin_ia32_psrldqi512_byteshift", +"llvm.x86.avx512.rcp14.pd.512" => "__builtin_ia32_rcp14pd512_mask", +"llvm.x86.avx512.rcp14.ps.512" => "__builtin_ia32_rcp14ps512_mask", +"llvm.x86.avx512.rcp14.sd" => "__builtin_ia32_rcp14sd_mask", +"llvm.x86.avx512.rcp14.ss" => "__builtin_ia32_rcp14ss_mask", +"llvm.x86.avx512.rcp28.pd" => "__builtin_ia32_rcp28pd_mask", +"llvm.x86.avx512.rcp28.ps" => "__builtin_ia32_rcp28ps_mask", +"llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_mask", +"llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_mask", +"llvm.x86.avx512.rndscale.sd" => "__builtin_ia32_rndscalesd", +"llvm.x86.avx512.rndscale.ss" => "__builtin_ia32_rndscaless", +"llvm.x86.avx512.rsqrt14.pd.512" => "__builtin_ia32_rsqrt14pd512_mask", +"llvm.x86.avx512.rsqrt14.ps.512" => "__builtin_ia32_rsqrt14ps512_mask", +"llvm.x86.avx512.rsqrt14.sd" => "__builtin_ia32_rsqrt14sd_mask", +"llvm.x86.avx512.rsqrt14.ss" => "__builtin_ia32_rsqrt14ss_mask", +"llvm.x86.avx512.rsqrt28.pd" => "__builtin_ia32_rsqrt28pd_mask", +"llvm.x86.avx512.rsqrt28.ps" => "__builtin_ia32_rsqrt28ps_mask", +"llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_mask", +"llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_mask", +"llvm.x86.avx512.scatter.dpd.512" => "__builtin_ia32_scattersiv8df", +"llvm.x86.avx512.scatter.dpi.512" => "__builtin_ia32_scattersiv16si", +"llvm.x86.avx512.scatter.dpq.512" => "__builtin_ia32_scattersiv8di", +"llvm.x86.avx512.scatter.dps.512" => "__builtin_ia32_scattersiv16sf", +"llvm.x86.avx512.scatter.qpd.512" => "__builtin_ia32_scatterdiv8df", +"llvm.x86.avx512.scatter.qpi.512" => "__builtin_ia32_scatterdiv16si", +"llvm.x86.avx512.scatter.qpq.512" => "__builtin_ia32_scatterdiv8di", +"llvm.x86.avx512.scatter.qps.512" => "__builtin_ia32_scatterdiv16sf", +"llvm.x86.avx512.scatterpf.dpd.512" => "__builtin_ia32_scatterpfdpd", +"llvm.x86.avx512.scatterpf.dps.512" => "__builtin_ia32_scatterpfdps", +"llvm.x86.avx512.scatterpf.qpd.512" => "__builtin_ia32_scatterpfqpd", +"llvm.x86.avx512.scatterpf.qps.512" => "__builtin_ia32_scatterpfqps", +"llvm.x86.avx512.sqrt.pd.512" => "__builtin_ia32_sqrtpd512_mask", +"llvm.x86.avx512.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask", +"llvm.x86.avx512.sqrt.sd" => "__builtin_ia32_sqrtrndsd", +"llvm.x86.avx512.sqrt.ss" => "__builtin_ia32_sqrtrndss", +"llvm.x86.avx512.vbroadcast.sd.512" => "__builtin_ia32_vbroadcastsd512", +"llvm.x86.avx512.vbroadcast.sd.pd.512" => "__builtin_ia32_vbroadcastsd_pd512", +"llvm.x86.avx512.vbroadcast.ss.512" => "__builtin_ia32_vbroadcastss512", +"llvm.x86.avx512.vbroadcast.ss.ps.512" => "__builtin_ia32_vbroadcastss_ps512", +"llvm.x86.bmi.bextr.32" => "__builtin_ia32_bextr_u32", +"llvm.x86.bmi.bextr.64" => "__builtin_ia32_bextr_u64", +"llvm.x86.bmi.bzhi.32" => "__builtin_ia32_bzhi_si", +"llvm.x86.bmi.bzhi.64" => "__builtin_ia32_bzhi_di", +"llvm.x86.bmi.pdep.32" => "__builtin_ia32_pdep_si", +"llvm.x86.bmi.pdep.64" => "__builtin_ia32_pdep_di", +"llvm.x86.bmi.pext.32" => "__builtin_ia32_pext_si", +"llvm.x86.bmi.pext.64" => "__builtin_ia32_pext_di", +"llvm.x86.fma.mask.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask", +"llvm.x86.fma.mask.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask", +"llvm.x86.fma.mask.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask", +"llvm.x86.fma.mask.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask", +"llvm.x86.fma.mask.vfmsub.pd.512" => "__builtin_ia32_vfmsubpd512_mask", +"llvm.x86.fma.mask.vfmsub.ps.512" => "__builtin_ia32_vfmsubps512_mask", +"llvm.x86.fma.mask.vfmsubadd.pd.512" => "__builtin_ia32_vfmsubaddpd512_mask", +"llvm.x86.fma.mask.vfmsubadd.ps.512" => "__builtin_ia32_vfmsubaddps512_mask", +"llvm.x86.fma.mask.vfnmadd.pd.512" => "__builtin_ia32_vfnmaddpd512_mask", +"llvm.x86.fma.mask.vfnmadd.ps.512" => "__builtin_ia32_vfnmaddps512_mask", +"llvm.x86.fma.mask.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask", +"llvm.x86.fma.mask.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask", +"llvm.x86.fma.vfmadd.pd" => "__builtin_ia32_vfmaddpd", +"llvm.x86.fma.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256", +"llvm.x86.fma.vfmadd.ps" => "__builtin_ia32_vfmaddps", +"llvm.x86.fma.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256", +"llvm.x86.fma.vfmadd.sd" => "__builtin_ia32_vfmaddsd", +"llvm.x86.fma.vfmadd.ss" => "__builtin_ia32_vfmaddss", +"llvm.x86.fma.vfmaddsub.pd" => "__builtin_ia32_vfmaddsubpd", +"llvm.x86.fma.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256", +"llvm.x86.fma.vfmaddsub.ps" => "__builtin_ia32_vfmaddsubps", +"llvm.x86.fma.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256", +"llvm.x86.fma.vfmsub.pd" => "__builtin_ia32_vfmsubpd", +"llvm.x86.fma.vfmsub.pd.256" => "__builtin_ia32_vfmsubpd256", +"llvm.x86.fma.vfmsub.ps" => "__builtin_ia32_vfmsubps", +"llvm.x86.fma.vfmsub.ps.256" => "__builtin_ia32_vfmsubps256", +"llvm.x86.fma.vfmsub.sd" => "__builtin_ia32_vfmsubsd", +"llvm.x86.fma.vfmsub.ss" => "__builtin_ia32_vfmsubss", +"llvm.x86.fma.vfmsubadd.pd" => "__builtin_ia32_vfmsubaddpd", +"llvm.x86.fma.vfmsubadd.pd.256" => "__builtin_ia32_vfmsubaddpd256", +"llvm.x86.fma.vfmsubadd.ps" => "__builtin_ia32_vfmsubaddps", +"llvm.x86.fma.vfmsubadd.ps.256" => "__builtin_ia32_vfmsubaddps256", +"llvm.x86.fma.vfnmadd.pd" => "__builtin_ia32_vfnmaddpd", +"llvm.x86.fma.vfnmadd.pd.256" => "__builtin_ia32_vfnmaddpd256", +"llvm.x86.fma.vfnmadd.ps" => "__builtin_ia32_vfnmaddps", +"llvm.x86.fma.vfnmadd.ps.256" => "__builtin_ia32_vfnmaddps256", +"llvm.x86.fma.vfnmadd.sd" => "__builtin_ia32_vfnmaddsd", +"llvm.x86.fma.vfnmadd.ss" => "__builtin_ia32_vfnmaddss", +"llvm.x86.fma.vfnmsub.pd" => "__builtin_ia32_vfnmsubpd", +"llvm.x86.fma.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256", +"llvm.x86.fma.vfnmsub.ps" => "__builtin_ia32_vfnmsubps", +"llvm.x86.fma.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256", +"llvm.x86.fma.vfnmsub.sd" => "__builtin_ia32_vfnmsubsd", +"llvm.x86.fma.vfnmsub.ss" => "__builtin_ia32_vfnmsubss", +"llvm.x86.mmx.emms" => "__builtin_ia32_emms", +"llvm.x86.mmx.femms" => "__builtin_ia32_femms", +"llvm.x86.pclmulqdq" => "__builtin_ia32_pclmulqdq128", +"llvm.x86.rdfsbase.32" => "__builtin_ia32_rdfsbase32", +"llvm.x86.rdfsbase.64" => "__builtin_ia32_rdfsbase64", +"llvm.x86.rdgsbase.32" => "__builtin_ia32_rdgsbase32", +"llvm.x86.rdgsbase.64" => "__builtin_ia32_rdgsbase64", +"llvm.x86.rdpmc" => "__builtin_ia32_rdpmc", +"llvm.x86.rdtsc" => "__builtin_ia32_rdtsc", +"llvm.x86.rdtscp" => "__builtin_ia32_rdtscp", +"llvm.x86.sha1msg1" => "__builtin_ia32_sha1msg1", +"llvm.x86.sha1msg2" => "__builtin_ia32_sha1msg2", +"llvm.x86.sha1nexte" => "__builtin_ia32_sha1nexte", +"llvm.x86.sha1rnds4" => "__builtin_ia32_sha1rnds4", +"llvm.x86.sha256msg1" => "__builtin_ia32_sha256msg1", +"llvm.x86.sha256msg2" => "__builtin_ia32_sha256msg2", +"llvm.x86.sha256rnds2" => "__builtin_ia32_sha256rnds2", +"llvm.x86.sse.add.ss" => "__builtin_ia32_addss", +"llvm.x86.sse.cmp.ps" => "__builtin_ia32_cmpps", +"llvm.x86.sse.cmp.ss" => "__builtin_ia32_cmpss", +"llvm.x86.sse.comieq.ss" => "__builtin_ia32_comieq", +"llvm.x86.sse.comige.ss" => "__builtin_ia32_comige", +"llvm.x86.sse.comigt.ss" => "__builtin_ia32_comigt", +"llvm.x86.sse.comile.ss" => "__builtin_ia32_comile", +"llvm.x86.sse.comilt.ss" => "__builtin_ia32_comilt", +"llvm.x86.sse.comineq.ss" => "__builtin_ia32_comineq", +"llvm.x86.sse.cvtsi2ss" => "__builtin_ia32_cvtsi2ss", +"llvm.x86.sse.cvtsi642ss" => "__builtin_ia32_cvtsi642ss", +"llvm.x86.sse.cvtss2si" => "__builtin_ia32_cvtss2si", +"llvm.x86.sse.cvtss2si64" => "__builtin_ia32_cvtss2si64", +"llvm.x86.sse.cvttss2si" => "__builtin_ia32_cvttss2si", +"llvm.x86.sse.cvttss2si64" => "__builtin_ia32_cvttss2si64", +"llvm.x86.sse.div.ss" => "__builtin_ia32_divss", +"llvm.x86.sse.max.ps" => "__builtin_ia32_maxps", +"llvm.x86.sse.max.ss" => "__builtin_ia32_maxss", +"llvm.x86.sse.min.ps" => "__builtin_ia32_minps", +"llvm.x86.sse.min.ss" => "__builtin_ia32_minss", +"llvm.x86.sse.movmsk.ps" => "__builtin_ia32_movmskps", +"llvm.x86.sse.mul.ss" => "__builtin_ia32_mulss", +"llvm.x86.sse.rcp.ps" => "__builtin_ia32_rcpps", +"llvm.x86.sse.rcp.ss" => "__builtin_ia32_rcpss", +"llvm.x86.sse.rsqrt.ps" => "__builtin_ia32_rsqrtps", +"llvm.x86.sse.rsqrt.ss" => "__builtin_ia32_rsqrtss", +"llvm.x86.sse.sfence" => "__builtin_ia32_sfence", +"llvm.x86.sse.sqrt.ps" => "__builtin_ia32_sqrtps", +"llvm.x86.sse.sqrt.ss" => "__builtin_ia32_sqrtss", +"llvm.x86.sse.storeu.ps" => "__builtin_ia32_storeups", +"llvm.x86.sse.sub.ss" => "__builtin_ia32_subss", +"llvm.x86.sse.ucomieq.ss" => "__builtin_ia32_ucomieq", +"llvm.x86.sse.ucomige.ss" => "__builtin_ia32_ucomige", +"llvm.x86.sse.ucomigt.ss" => "__builtin_ia32_ucomigt", +"llvm.x86.sse.ucomile.ss" => "__builtin_ia32_ucomile", +"llvm.x86.sse.ucomilt.ss" => "__builtin_ia32_ucomilt", +"llvm.x86.sse.ucomineq.ss" => "__builtin_ia32_ucomineq", +"llvm.x86.sse2.add.sd" => "__builtin_ia32_addsd", +"llvm.x86.sse2.clflush" => "__builtin_ia32_clflush", +"llvm.x86.sse2.cmp.pd" => "__builtin_ia32_cmppd", +"llvm.x86.sse2.cmp.sd" => "__builtin_ia32_cmpsd", +"llvm.x86.sse2.comieq.sd" => "__builtin_ia32_comisdeq", +"llvm.x86.sse2.comige.sd" => "__builtin_ia32_comisdge", +"llvm.x86.sse2.comigt.sd" => "__builtin_ia32_comisdgt", +"llvm.x86.sse2.comile.sd" => "__builtin_ia32_comisdle", +"llvm.x86.sse2.comilt.sd" => "__builtin_ia32_comisdlt", +"llvm.x86.sse2.comineq.sd" => "__builtin_ia32_comisdneq", +"llvm.x86.sse2.cvtdq2pd" => "__builtin_ia32_cvtdq2pd", +"llvm.x86.sse2.cvtdq2ps" => "__builtin_ia32_cvtdq2ps", +"llvm.x86.sse2.cvtpd2dq" => "__builtin_ia32_cvtpd2dq", +"llvm.x86.sse2.cvtpd2ps" => "__builtin_ia32_cvtpd2ps", +"llvm.x86.sse2.cvtps2dq" => "__builtin_ia32_cvtps2dq", +"llvm.x86.sse2.cvtps2pd" => "__builtin_ia32_cvtps2pd", +"llvm.x86.sse2.cvtsd2si" => "__builtin_ia32_cvtsd2si", +"llvm.x86.sse2.cvtsd2si64" => "__builtin_ia32_cvtsd2si64", +"llvm.x86.sse2.cvtsd2ss" => "__builtin_ia32_cvtsd2ss", +"llvm.x86.sse2.cvtsi2sd" => "__builtin_ia32_cvtsi2sd", +"llvm.x86.sse2.cvtsi642sd" => "__builtin_ia32_cvtsi642sd", +"llvm.x86.sse2.cvtss2sd" => "__builtin_ia32_cvtss2sd", +"llvm.x86.sse2.cvttpd2dq" => "__builtin_ia32_cvttpd2dq", +"llvm.x86.sse2.cvttps2dq" => "__builtin_ia32_cvttps2dq", +"llvm.x86.sse2.cvttsd2si" => "__builtin_ia32_cvttsd2si", +"llvm.x86.sse2.cvttsd2si64" => "__builtin_ia32_cvttsd2si64", +"llvm.x86.sse2.div.sd" => "__builtin_ia32_divsd", +"llvm.x86.sse2.lfence" => "__builtin_ia32_lfence", +"llvm.x86.sse2.maskmov.dqu" => "__builtin_ia32_maskmovdqu", +"llvm.x86.sse2.max.pd" => "__builtin_ia32_maxpd", +"llvm.x86.sse2.max.sd" => "__builtin_ia32_maxsd", +"llvm.x86.sse2.mfence" => "__builtin_ia32_mfence", +"llvm.x86.sse2.min.pd" => "__builtin_ia32_minpd", +"llvm.x86.sse2.min.sd" => "__builtin_ia32_minsd", +"llvm.x86.sse2.movmsk.pd" => "__builtin_ia32_movmskpd", +"llvm.x86.sse2.mul.sd" => "__builtin_ia32_mulsd", +"llvm.x86.sse2.packssdw.128" => "__builtin_ia32_packssdw128", +"llvm.x86.sse2.packsswb.128" => "__builtin_ia32_packsswb128", +"llvm.x86.sse2.packuswb.128" => "__builtin_ia32_packuswb128", +"llvm.x86.sse2.padds.b" => "__builtin_ia32_paddsb128", +"llvm.x86.sse2.padds.w" => "__builtin_ia32_paddsw128", +"llvm.x86.sse2.paddus.b" => "__builtin_ia32_paddusb128", +"llvm.x86.sse2.paddus.w" => "__builtin_ia32_paddusw128", +"llvm.x86.sse2.pause" => "__builtin_ia32_pause", +"llvm.x86.sse2.pavg.b" => "__builtin_ia32_pavgb128", +"llvm.x86.sse2.pavg.w" => "__builtin_ia32_pavgw128", +"llvm.x86.sse2.pmadd.wd" => "__builtin_ia32_pmaddwd128", +"llvm.x86.sse2.pmaxs.w" => "__builtin_ia32_pmaxsw128", +"llvm.x86.sse2.pmaxu.b" => "__builtin_ia32_pmaxub128", +"llvm.x86.sse2.pmins.w" => "__builtin_ia32_pminsw128", +"llvm.x86.sse2.pminu.b" => "__builtin_ia32_pminub128", +"llvm.x86.sse2.pmovmskb.128" => "__builtin_ia32_pmovmskb128", +"llvm.x86.sse2.pmulh.w" => "__builtin_ia32_pmulhw128", +"llvm.x86.sse2.pmulhu.w" => "__builtin_ia32_pmulhuw128", +"llvm.x86.sse2.pmulu.dq" => "__builtin_ia32_pmuludq128", +"llvm.x86.sse2.psad.bw" => "__builtin_ia32_psadbw128", +"llvm.x86.sse2.pshuf.d" => "__builtin_ia32_pshufd", +"llvm.x86.sse2.pshufh.w" => "__builtin_ia32_pshufhw", +"llvm.x86.sse2.pshufl.w" => "__builtin_ia32_pshuflw", +"llvm.x86.sse2.psll.d" => "__builtin_ia32_pslld128", +"llvm.x86.sse2.psll.dq" => "__builtin_ia32_pslldqi128", +"llvm.x86.sse2.psll.dq.bs" => "__builtin_ia32_pslldqi128_byteshift", +"llvm.x86.sse2.psll.q" => "__builtin_ia32_psllq128", +"llvm.x86.sse2.psll.w" => "__builtin_ia32_psllw128", +"llvm.x86.sse2.pslli.d" => "__builtin_ia32_pslldi128", +"llvm.x86.sse2.pslli.q" => "__builtin_ia32_psllqi128", +"llvm.x86.sse2.pslli.w" => "__builtin_ia32_psllwi128", +"llvm.x86.sse2.psra.d" => "__builtin_ia32_psrad128", +"llvm.x86.sse2.psra.w" => "__builtin_ia32_psraw128", +"llvm.x86.sse2.psrai.d" => "__builtin_ia32_psradi128", +"llvm.x86.sse2.psrai.w" => "__builtin_ia32_psrawi128", +"llvm.x86.sse2.psrl.d" => "__builtin_ia32_psrld128", +"llvm.x86.sse2.psrl.dq" => "__builtin_ia32_psrldqi128", +"llvm.x86.sse2.psrl.dq.bs" => "__builtin_ia32_psrldqi128_byteshift", +"llvm.x86.sse2.psrl.q" => "__builtin_ia32_psrlq128", +"llvm.x86.sse2.psrl.w" => "__builtin_ia32_psrlw128", +"llvm.x86.sse2.psrli.d" => "__builtin_ia32_psrldi128", +"llvm.x86.sse2.psrli.q" => "__builtin_ia32_psrlqi128", +"llvm.x86.sse2.psrli.w" => "__builtin_ia32_psrlwi128", +"llvm.x86.sse2.psubs.b" => "__builtin_ia32_psubsb128", +"llvm.x86.sse2.psubs.w" => "__builtin_ia32_psubsw128", +"llvm.x86.sse2.psubus.b" => "__builtin_ia32_psubusb128", +"llvm.x86.sse2.psubus.w" => "__builtin_ia32_psubusw128", +"llvm.x86.sse2.sqrt.pd" => "__builtin_ia32_sqrtpd", +"llvm.x86.sse2.sqrt.sd" => "__builtin_ia32_sqrtsd", +"llvm.x86.sse2.storel.dq" => "__builtin_ia32_storelv4si", +"llvm.x86.sse2.storeu.dq" => "__builtin_ia32_storedqu", +"llvm.x86.sse2.storeu.pd" => "__builtin_ia32_storeupd", +"llvm.x86.sse2.sub.sd" => "__builtin_ia32_subsd", +"llvm.x86.sse2.ucomieq.sd" => "__builtin_ia32_ucomisdeq", +"llvm.x86.sse2.ucomige.sd" => "__builtin_ia32_ucomisdge", +"llvm.x86.sse2.ucomigt.sd" => "__builtin_ia32_ucomisdgt", +"llvm.x86.sse2.ucomile.sd" => "__builtin_ia32_ucomisdle", +"llvm.x86.sse2.ucomilt.sd" => "__builtin_ia32_ucomisdlt", +"llvm.x86.sse2.ucomineq.sd" => "__builtin_ia32_ucomisdneq", +"llvm.x86.sse3.addsub.pd" => "__builtin_ia32_addsubpd", +"llvm.x86.sse3.addsub.ps" => "__builtin_ia32_addsubps", +"llvm.x86.sse3.hadd.pd" => "__builtin_ia32_haddpd", +"llvm.x86.sse3.hadd.ps" => "__builtin_ia32_haddps", +"llvm.x86.sse3.hsub.pd" => "__builtin_ia32_hsubpd", +"llvm.x86.sse3.hsub.ps" => "__builtin_ia32_hsubps", +"llvm.x86.sse3.ldu.dq" => "__builtin_ia32_lddqu", +"llvm.x86.sse3.monitor" => "__builtin_ia32_monitor", +"llvm.x86.sse3.mwait" => "__builtin_ia32_mwait", +"llvm.x86.sse41.blendpd" => "__builtin_ia32_blendpd", +"llvm.x86.sse41.blendps" => "__builtin_ia32_blendps", +"llvm.x86.sse41.blendvpd" => "__builtin_ia32_blendvpd", +"llvm.x86.sse41.blendvps" => "__builtin_ia32_blendvps", +"llvm.x86.sse41.dppd" => "__builtin_ia32_dppd", +"llvm.x86.sse41.dpps" => "__builtin_ia32_dpps", +"llvm.x86.sse41.extractps" => "__builtin_ia32_extractps128", +"llvm.x86.sse41.insertps" => "__builtin_ia32_insertps128", +"llvm.x86.sse41.movntdqa" => "__builtin_ia32_movntdqa", +"llvm.x86.sse41.mpsadbw" => "__builtin_ia32_mpsadbw128", +"llvm.x86.sse41.packusdw" => "__builtin_ia32_packusdw128", +"llvm.x86.sse41.pblendvb" => "__builtin_ia32_pblendvb128", +"llvm.x86.sse41.pblendw" => "__builtin_ia32_pblendw128", +"llvm.x86.sse41.phminposuw" => "__builtin_ia32_phminposuw128", +"llvm.x86.sse41.pmaxsb" => "__builtin_ia32_pmaxsb128", +"llvm.x86.sse41.pmaxsd" => "__builtin_ia32_pmaxsd128", +"llvm.x86.sse41.pmaxud" => "__builtin_ia32_pmaxud128", +"llvm.x86.sse41.pmaxuw" => "__builtin_ia32_pmaxuw128", +"llvm.x86.sse41.pminsb" => "__builtin_ia32_pminsb128", +"llvm.x86.sse41.pminsd" => "__builtin_ia32_pminsd128", +"llvm.x86.sse41.pminud" => "__builtin_ia32_pminud128", +"llvm.x86.sse41.pminuw" => "__builtin_ia32_pminuw128", +"llvm.x86.sse41.pmovsxbd" => "__builtin_ia32_pmovsxbd128", +"llvm.x86.sse41.pmovsxbq" => "__builtin_ia32_pmovsxbq128", +"llvm.x86.sse41.pmovsxbw" => "__builtin_ia32_pmovsxbw128", +"llvm.x86.sse41.pmovsxdq" => "__builtin_ia32_pmovsxdq128", +"llvm.x86.sse41.pmovsxwd" => "__builtin_ia32_pmovsxwd128", +"llvm.x86.sse41.pmovsxwq" => "__builtin_ia32_pmovsxwq128", +"llvm.x86.sse41.pmovzxbd" => "__builtin_ia32_pmovzxbd128", +"llvm.x86.sse41.pmovzxbq" => "__builtin_ia32_pmovzxbq128", +"llvm.x86.sse41.pmovzxbw" => "__builtin_ia32_pmovzxbw128", +"llvm.x86.sse41.pmovzxdq" => "__builtin_ia32_pmovzxdq128", +"llvm.x86.sse41.pmovzxwd" => "__builtin_ia32_pmovzxwd128", +"llvm.x86.sse41.pmovzxwq" => "__builtin_ia32_pmovzxwq128", +"llvm.x86.sse41.pmuldq" => "__builtin_ia32_pmuldq128", +"llvm.x86.sse41.ptestc" => "__builtin_ia32_ptestc128", +"llvm.x86.sse41.ptestnzc" => "__builtin_ia32_ptestnzc128", +"llvm.x86.sse41.ptestz" => "__builtin_ia32_ptestz128", +"llvm.x86.sse41.round.pd" => "__builtin_ia32_roundpd", +"llvm.x86.sse41.round.ps" => "__builtin_ia32_roundps", +"llvm.x86.sse41.round.sd" => "__builtin_ia32_roundsd", +"llvm.x86.sse41.round.ss" => "__builtin_ia32_roundss", +"llvm.x86.sse42.crc32.32.16" => "__builtin_ia32_crc32hi", +"llvm.x86.sse42.crc32.32.32" => "__builtin_ia32_crc32si", +"llvm.x86.sse42.crc32.32.8" => "__builtin_ia32_crc32qi", +"llvm.x86.sse42.crc32.64.64" => "__builtin_ia32_crc32di", +"llvm.x86.sse42.pcmpestri128" => "__builtin_ia32_pcmpestri128", +"llvm.x86.sse42.pcmpestria128" => "__builtin_ia32_pcmpestria128", +"llvm.x86.sse42.pcmpestric128" => "__builtin_ia32_pcmpestric128", +"llvm.x86.sse42.pcmpestrio128" => "__builtin_ia32_pcmpestrio128", +"llvm.x86.sse42.pcmpestris128" => "__builtin_ia32_pcmpestris128", +"llvm.x86.sse42.pcmpestriz128" => "__builtin_ia32_pcmpestriz128", +"llvm.x86.sse42.pcmpestrm128" => "__builtin_ia32_pcmpestrm128", +"llvm.x86.sse42.pcmpistri128" => "__builtin_ia32_pcmpistri128", +"llvm.x86.sse42.pcmpistria128" => "__builtin_ia32_pcmpistria128", +"llvm.x86.sse42.pcmpistric128" => "__builtin_ia32_pcmpistric128", +"llvm.x86.sse42.pcmpistrio128" => "__builtin_ia32_pcmpistrio128", +"llvm.x86.sse42.pcmpistris128" => "__builtin_ia32_pcmpistris128", +"llvm.x86.sse42.pcmpistriz128" => "__builtin_ia32_pcmpistriz128", +"llvm.x86.sse42.pcmpistrm128" => "__builtin_ia32_pcmpistrm128", +"llvm.x86.sse4a.extrq" => "__builtin_ia32_extrq", +"llvm.x86.sse4a.extrqi" => "__builtin_ia32_extrqi", +"llvm.x86.sse4a.insertq" => "__builtin_ia32_insertq", +"llvm.x86.sse4a.insertqi" => "__builtin_ia32_insertqi", +"llvm.x86.sse4a.movnt.sd" => "__builtin_ia32_movntsd", +"llvm.x86.sse4a.movnt.ss" => "__builtin_ia32_movntss", +"llvm.x86.ssse3.pabs.b.128" => "__builtin_ia32_pabsb128", +"llvm.x86.ssse3.pabs.d.128" => "__builtin_ia32_pabsd128", +"llvm.x86.ssse3.pabs.w.128" => "__builtin_ia32_pabsw128", +"llvm.x86.ssse3.phadd.d.128" => "__builtin_ia32_phaddd128", +"llvm.x86.ssse3.phadd.sw.128" => "__builtin_ia32_phaddsw128", +"llvm.x86.ssse3.phadd.w.128" => "__builtin_ia32_phaddw128", +"llvm.x86.ssse3.phsub.d.128" => "__builtin_ia32_phsubd128", +"llvm.x86.ssse3.phsub.sw.128" => "__builtin_ia32_phsubsw128", +"llvm.x86.ssse3.phsub.w.128" => "__builtin_ia32_phsubw128", +"llvm.x86.ssse3.pmadd.ub.sw.128" => "__builtin_ia32_pmaddubsw128", +"llvm.x86.ssse3.pmul.hr.sw.128" => "__builtin_ia32_pmulhrsw128", +"llvm.x86.ssse3.pshuf.b.128" => "__builtin_ia32_pshufb128", +"llvm.x86.ssse3.psign.b.128" => "__builtin_ia32_psignb128", +"llvm.x86.ssse3.psign.d.128" => "__builtin_ia32_psignd128", +"llvm.x86.ssse3.psign.w.128" => "__builtin_ia32_psignw128", +"llvm.x86.subborrow.u32" => "__builtin_ia32_subborrow_u32", +"llvm.x86.subborrow.u64" => "__builtin_ia32_subborrow_u64", +"llvm.x86.tbm.bextri.u32" => "__builtin_ia32_bextri_u32", +"llvm.x86.tbm.bextri.u64" => "__builtin_ia32_bextri_u64", +"llvm.x86.vcvtph2ps.128" => "__builtin_ia32_vcvtph2ps", +"llvm.x86.vcvtph2ps.256" => "__builtin_ia32_vcvtph2ps256", +"llvm.x86.vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph", +"llvm.x86.vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256", +"llvm.x86.wrfsbase.32" => "__builtin_ia32_wrfsbase32", +"llvm.x86.wrfsbase.64" => "__builtin_ia32_wrfsbase64", +"llvm.x86.wrgsbase.32" => "__builtin_ia32_wrgsbase32", +"llvm.x86.wrgsbase.64" => "__builtin_ia32_wrgsbase64", +"llvm.x86.xabort" => "__builtin_ia32_xabort", +"llvm.x86.xbegin" => "__builtin_ia32_xbegin", +"llvm.x86.xend" => "__builtin_ia32_xend", +"llvm.x86.xop.vfrcz.pd" => "__builtin_ia32_vfrczpd", +"llvm.x86.xop.vfrcz.pd.256" => "__builtin_ia32_vfrczpd256", +"llvm.x86.xop.vfrcz.ps" => "__builtin_ia32_vfrczps", +"llvm.x86.xop.vfrcz.ps.256" => "__builtin_ia32_vfrczps256", +"llvm.x86.xop.vfrcz.sd" => "__builtin_ia32_vfrczsd", +"llvm.x86.xop.vfrcz.ss" => "__builtin_ia32_vfrczss", +"llvm.x86.xop.vpcmov" => "__builtin_ia32_vpcmov", +"llvm.x86.xop.vpcmov.256" => "__builtin_ia32_vpcmov_256", +"llvm.x86.xop.vpcomb" => "__builtin_ia32_vpcomb", +"llvm.x86.xop.vpcomd" => "__builtin_ia32_vpcomd", +"llvm.x86.xop.vpcomq" => "__builtin_ia32_vpcomq", +"llvm.x86.xop.vpcomub" => "__builtin_ia32_vpcomub", +"llvm.x86.xop.vpcomud" => "__builtin_ia32_vpcomud", +"llvm.x86.xop.vpcomuq" => "__builtin_ia32_vpcomuq", +"llvm.x86.xop.vpcomuw" => "__builtin_ia32_vpcomuw", +"llvm.x86.xop.vpcomw" => "__builtin_ia32_vpcomw", +"llvm.x86.xop.vpermil2pd" => "__builtin_ia32_vpermil2pd", +"llvm.x86.xop.vpermil2pd.256" => "__builtin_ia32_vpermil2pd256", +"llvm.x86.xop.vpermil2ps" => "__builtin_ia32_vpermil2ps", +"llvm.x86.xop.vpermil2ps.256" => "__builtin_ia32_vpermil2ps256", +"llvm.x86.xop.vphaddbd" => "__builtin_ia32_vphaddbd", +"llvm.x86.xop.vphaddbq" => "__builtin_ia32_vphaddbq", +"llvm.x86.xop.vphaddbw" => "__builtin_ia32_vphaddbw", +"llvm.x86.xop.vphadddq" => "__builtin_ia32_vphadddq", +"llvm.x86.xop.vphaddubd" => "__builtin_ia32_vphaddubd", +"llvm.x86.xop.vphaddubq" => "__builtin_ia32_vphaddubq", +"llvm.x86.xop.vphaddubw" => "__builtin_ia32_vphaddubw", +"llvm.x86.xop.vphaddudq" => "__builtin_ia32_vphaddudq", +"llvm.x86.xop.vphadduwd" => "__builtin_ia32_vphadduwd", +"llvm.x86.xop.vphadduwq" => "__builtin_ia32_vphadduwq", +"llvm.x86.xop.vphaddwd" => "__builtin_ia32_vphaddwd", +"llvm.x86.xop.vphaddwq" => "__builtin_ia32_vphaddwq", +"llvm.x86.xop.vphsubbw" => "__builtin_ia32_vphsubbw", +"llvm.x86.xop.vphsubdq" => "__builtin_ia32_vphsubdq", +"llvm.x86.xop.vphsubwd" => "__builtin_ia32_vphsubwd", +"llvm.x86.xop.vpmacsdd" => "__builtin_ia32_vpmacsdd", +"llvm.x86.xop.vpmacsdqh" => "__builtin_ia32_vpmacsdqh", +"llvm.x86.xop.vpmacsdql" => "__builtin_ia32_vpmacsdql", +"llvm.x86.xop.vpmacssdd" => "__builtin_ia32_vpmacssdd", +"llvm.x86.xop.vpmacssdqh" => "__builtin_ia32_vpmacssdqh", +"llvm.x86.xop.vpmacssdql" => "__builtin_ia32_vpmacssdql", +"llvm.x86.xop.vpmacsswd" => "__builtin_ia32_vpmacsswd", +"llvm.x86.xop.vpmacssww" => "__builtin_ia32_vpmacssww", +"llvm.x86.xop.vpmacswd" => "__builtin_ia32_vpmacswd", +"llvm.x86.xop.vpmacsww" => "__builtin_ia32_vpmacsww", +"llvm.x86.xop.vpmadcsswd" => "__builtin_ia32_vpmadcsswd", +"llvm.x86.xop.vpmadcswd" => "__builtin_ia32_vpmadcswd", +"llvm.x86.xop.vpperm" => "__builtin_ia32_vpperm", +"llvm.x86.xop.vprotb" => "__builtin_ia32_vprotb", +"llvm.x86.xop.vprotbi" => "__builtin_ia32_vprotbi", +"llvm.x86.xop.vprotd" => "__builtin_ia32_vprotd", +"llvm.x86.xop.vprotdi" => "__builtin_ia32_vprotdi", +"llvm.x86.xop.vprotq" => "__builtin_ia32_vprotq", +"llvm.x86.xop.vprotqi" => "__builtin_ia32_vprotqi", +"llvm.x86.xop.vprotw" => "__builtin_ia32_vprotw", +"llvm.x86.xop.vprotwi" => "__builtin_ia32_vprotwi", +"llvm.x86.xop.vpshab" => "__builtin_ia32_vpshab", +"llvm.x86.xop.vpshad" => "__builtin_ia32_vpshad", +"llvm.x86.xop.vpshaq" => "__builtin_ia32_vpshaq", +"llvm.x86.xop.vpshaw" => "__builtin_ia32_vpshaw", +"llvm.x86.xop.vpshlb" => "__builtin_ia32_vpshlb", +"llvm.x86.xop.vpshld" => "__builtin_ia32_vpshld", +"llvm.x86.xop.vpshlq" => "__builtin_ia32_vpshlq", +"llvm.x86.xop.vpshlw" => "__builtin_ia32_vpshlw", +"llvm.x86.xtest" => "__builtin_ia32_xtest", +_ => unimplemented!("***** unsupported LLVM intrinsic {}", name), +}