Auto merge of #38579 - whitequark:min_atomic_width, r=alexcrichton
Add a min_atomic_width target option, like max_atomic_width Rationale: some ISAs, e.g. OR1K, do not have atomic instructions for byte and halfword access, and at the same time do not have a fixed endianness, which makes it unreasonable to implement these through word-sized atomic accesses.
This commit is contained in:
commit
0807104c8f
2 changed files with 14 additions and 1 deletions
|
|
@ -943,6 +943,7 @@ pub fn default_configuration(sess: &Session) -> ast::CrateConfig {
|
|||
let os = &sess.target.target.target_os;
|
||||
let env = &sess.target.target.target_env;
|
||||
let vendor = &sess.target.target.target_vendor;
|
||||
let min_atomic_width = sess.target.target.min_atomic_width();
|
||||
let max_atomic_width = sess.target.target.max_atomic_width();
|
||||
|
||||
let mut ret = HashSet::new();
|
||||
|
|
@ -963,7 +964,7 @@ pub fn default_configuration(sess: &Session) -> ast::CrateConfig {
|
|||
ret.insert((Symbol::intern("target_thread_local"), None));
|
||||
}
|
||||
for &i in &[8, 16, 32, 64, 128] {
|
||||
if i <= max_atomic_width {
|
||||
if i >= min_atomic_width && i <= max_atomic_width {
|
||||
let s = i.to_string();
|
||||
ret.insert((Symbol::intern("target_has_atomic"), Some(Symbol::intern(&s))));
|
||||
if &s == wordsz {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue