riscv: K extension (part 1), floating-point control and state register (#1278)
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Luo Jia
GitHub
parent
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commit
0888677e5c
2 changed files with 304 additions and 14 deletions
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@ -10,7 +10,7 @@ use crate::arch::asm;
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/// This operation is not available under RV32 base instruction set.
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///
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/// This function is unsafe for it accesses the virtual supervisor or user via a `HLV.WU`
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/// instruction which is effectively an unreference to any memory address.
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/// instruction which is effectively a dereference to any memory address.
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#[inline]
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pub unsafe fn hlv_wu(src: *const u32) -> u32 {
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let value: u32;
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@ -18,7 +18,7 @@ pub unsafe fn hlv_wu(src: *const u32) -> u32 {
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value
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}
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/// Loads virtual machine memory by unsigned double integer
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/// Loads virtual machine memory by double integer
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///
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/// This instruction performs an explicit memory access as though `V=1`;
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/// i.e., with the address translation and protection, and the endianness, that apply to memory
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@ -27,7 +27,7 @@ pub unsafe fn hlv_wu(src: *const u32) -> u32 {
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/// This operation is not available under RV32 base instruction set.
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///
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/// This function is unsafe for it accesses the virtual supervisor or user via a `HLV.D`
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/// instruction which is effectively an unreference to any memory address.
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/// instruction which is effectively a dereference to any memory address.
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#[inline]
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pub unsafe fn hlv_d(src: *const i64) -> i64 {
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let value: i64;
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@ -42,7 +42,7 @@ pub unsafe fn hlv_d(src: *const i64) -> i64 {
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/// accesses in either VS-mode or VU-mode.
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///
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/// This function is unsafe for it accesses the virtual supervisor or user via a `HSV.D`
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/// instruction which is effectively an unreference to any memory address.
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/// instruction which is effectively a dereference to any memory address.
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#[inline]
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pub unsafe fn hsv_d(dst: *mut i64, src: i64) {
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asm!(".insn r 0x73, 0x4, 0x37, x0, {}, {}", in(reg) dst, in(reg) src, options(nostack));
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@ -153,7 +153,7 @@ pub unsafe fn sfence_inval_ir() {
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/// accesses in either VS-mode or VU-mode.
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///
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/// This function is unsafe for it accesses the virtual supervisor or user via a `HLV.B`
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/// instruction which is effectively an unreference to any memory address.
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/// instruction which is effectively a dereference to any memory address.
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#[inline]
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pub unsafe fn hlv_b(src: *const i8) -> i8 {
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let value: i8;
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@ -168,7 +168,7 @@ pub unsafe fn hlv_b(src: *const i8) -> i8 {
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/// accesses in either VS-mode or VU-mode.
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///
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/// This function is unsafe for it accesses the virtual supervisor or user via a `HLV.BU`
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/// instruction which is effectively an unreference to any memory address.
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/// instruction which is effectively a dereference to any memory address.
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#[inline]
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pub unsafe fn hlv_bu(src: *const u8) -> u8 {
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let value: u8;
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@ -183,7 +183,7 @@ pub unsafe fn hlv_bu(src: *const u8) -> u8 {
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/// accesses in either VS-mode or VU-mode.
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///
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/// This function is unsafe for it accesses the virtual supervisor or user via a `HLV.H`
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/// instruction which is effectively an unreference to any memory address.
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/// instruction which is effectively a dereference to any memory address.
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#[inline]
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pub unsafe fn hlv_h(src: *const i16) -> i16 {
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let value: i16;
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@ -198,7 +198,7 @@ pub unsafe fn hlv_h(src: *const i16) -> i16 {
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/// accesses in either VS-mode or VU-mode.
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///
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/// This function is unsafe for it accesses the virtual supervisor or user via a `HLV.HU`
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/// instruction which is effectively an unreference to any memory address.
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/// instruction which is effectively a dereference to any memory address.
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#[inline]
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pub unsafe fn hlv_hu(src: *const u16) -> u16 {
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let value: u16;
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@ -213,7 +213,7 @@ pub unsafe fn hlv_hu(src: *const u16) -> u16 {
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/// but read permission is not required.
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///
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/// This function is unsafe for it accesses the virtual supervisor or user via a `HLVX.HU`
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/// instruction which is effectively an unreference to any memory address.
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/// instruction which is effectively a dereference to any memory address.
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#[inline]
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pub unsafe fn hlvx_hu(src: *const u16) -> u16 {
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let insn: u16;
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@ -228,7 +228,7 @@ pub unsafe fn hlvx_hu(src: *const u16) -> u16 {
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/// accesses in either VS-mode or VU-mode.
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///
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/// This function is unsafe for it accesses the virtual supervisor or user via a `HLV.W`
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/// instruction which is effectively an unreference to any memory address.
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/// instruction which is effectively a dereference to any memory address.
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#[inline]
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pub unsafe fn hlv_w(src: *const i32) -> i32 {
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let value: i32;
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@ -243,7 +243,7 @@ pub unsafe fn hlv_w(src: *const i32) -> i32 {
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/// but read permission is not required.
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///
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/// This function is unsafe for it accesses the virtual supervisor or user via a `HLVX.WU`
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/// instruction which is effectively an unreference to any memory address.
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/// instruction which is effectively a dereference to any memory address.
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#[inline]
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pub unsafe fn hlvx_wu(src: *const u32) -> u32 {
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let insn: u32;
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@ -258,7 +258,7 @@ pub unsafe fn hlvx_wu(src: *const u32) -> u32 {
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/// accesses in either VS-mode or VU-mode.
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///
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/// This function is unsafe for it accesses the virtual supervisor or user via a `HSV.B`
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/// instruction which is effectively an unreference to any memory address.
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/// instruction which is effectively a dereference to any memory address.
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#[inline]
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pub unsafe fn hsv_b(dst: *mut i8, src: i8) {
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asm!(".insn r 0x73, 0x4, 0x31, x0, {}, {}", in(reg) dst, in(reg) src, options(nostack));
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@ -271,7 +271,7 @@ pub unsafe fn hsv_b(dst: *mut i8, src: i8) {
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/// accesses in either VS-mode or VU-mode.
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///
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/// This function is unsafe for it accesses the virtual supervisor or user via a `HSV.H`
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/// instruction which is effectively an unreference to any memory address.
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/// instruction which is effectively a dereference to any memory address.
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#[inline]
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pub unsafe fn hsv_h(dst: *mut i16, src: i16) {
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asm!(".insn r 0x73, 0x4, 0x33, x0, {}, {}", in(reg) dst, in(reg) src, options(nostack));
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@ -284,7 +284,7 @@ pub unsafe fn hsv_h(dst: *mut i16, src: i16) {
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/// accesses in either VS-mode or VU-mode.
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///
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/// This function is unsafe for it accesses the virtual supervisor or user via a `HSV.W`
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/// instruction which is effectively an unreference to any memory address.
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/// instruction which is effectively a dereference to any memory address.
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#[inline]
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pub unsafe fn hsv_w(dst: *mut i32, src: i32) {
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asm!(".insn r 0x73, 0x4, 0x35, x0, {}, {}", in(reg) dst, in(reg) src, options(nostack));
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@ -469,6 +469,111 @@ pub unsafe fn hinval_gvma_vmid(vmid: usize) {
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asm!(".insn r 0x73, 0, 0x33, x0, x0, {}", in(reg) vmid, options(nostack))
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}
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/// Reads the floating-point control and status register `fcsr`
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///
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/// Register `fcsr` is a 32-bit read/write register that selects the dynamic rounding mode
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/// for floating-point arithmetic operations and holds the accrued exception flag.
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///
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/// Accoding to "F" Standard Extension for Single-Precision Floating-Point, Version 2.2,
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/// register `fcsr` is defined as:
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///
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/// | Bit index | Meaning |
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/// |:----------|:--------|
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/// | 0..=4 | Accrued Exceptions (`fflags`) |
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/// | 5..=7 | Rounding Mode (`frm`) |
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/// | 8..=31 | _Reserved_ |
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///
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/// For definition of each field, visit [`frrm`] and [`frflags`].
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///
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/// [`frrm`]: fn.frrm.html
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/// [`frflags`]: fn.frflags.html
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#[inline]
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pub fn frcsr() -> u32 {
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let value: u32;
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unsafe { asm!("frcsr {}", out(reg) value, options(nomem, nostack)) };
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value
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}
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/// Swaps the floating-point control and status register `fcsr`
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///
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/// This function swaps the value in `fcsr` by copying the original value to be returned,
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/// and then writing a new value obtained from input variable `value` into `fcsr`.
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#[inline]
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pub fn fscsr(value: u32) -> u32 {
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let original: u32;
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unsafe { asm!("fscsr {}, {}", out(reg) original, in(reg) value, options(nomem, nostack)) }
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original
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}
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/// Reads the floating-point rounding mode register `frm`
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///
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/// Accoding to "F" Standard Extension for Single-Precision Floating-Point, Version 2.2,
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/// the rounding mode field is defined as listed in the table below:
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///
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/// | Rounding Mode | Mnemonic | Meaning |
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/// |:-------------|:----------|:---------|
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/// | 000 | RNE | Round to Nearest, ties to Even |
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/// | 001 | RTZ | Round towards Zero |
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/// | 010 | RDN | Round Down (towards −∞) |
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/// | 011 | RUP | Round Up (towards +∞) |
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/// | 100 | RMM | Round to Nearest, ties to Max Magnitude |
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/// | 101 | | _Reserved for future use._ |
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/// | 110 | | _Reserved for future use._ |
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/// | 111 | DYN | In Rounding Mode register, _reserved_. |
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#[inline]
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pub fn frrm() -> u32 {
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let value: u32;
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unsafe { asm!("frrm {}", out(reg) value, options(nomem, nostack)) };
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value
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}
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/// Swaps the floating-point rounding mode register `frm`
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///
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/// This function swaps the value in `frm` by copying the original value to be returned,
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/// and then writing a new value obtained from the three least-significant bits of
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/// input variable `value` into `frm`.
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#[inline]
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pub fn fsrm(value: u32) -> u32 {
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let original: u32;
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unsafe { asm!("fsrm {}, {}", out(reg) original, in(reg) value, options(nomem, nostack)) }
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original
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}
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/// Reads the floating-point accrued exception flags register `fflags`
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///
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/// The accrued exception flags indicate the exception conditions that have arisen
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/// on any floating-point arithmetic instruction since the field was last reset by software.
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///
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/// Accoding to "F" Standard Extension for Single-Precision Floating-Point, Version 2.2,
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/// the accured exception flags is defined as a bit vector of 5 bits.
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/// The meaning of each binary bit is listed in the table below.
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///
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/// | Bit index | Mnemonic | Meaning |
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/// |:--|:---|:-----------------|
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/// | 4 | NV | Invalid Operation |
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/// | 3 | DZ | Divide by Zero |
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/// | 2 | OF | Overflow |
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/// | 1 | UF | Underflow |
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/// | 0 | NX | Inexact |
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#[inline]
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pub fn frflags() -> u32 {
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let value: u32;
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unsafe { asm!("frflags {}", out(reg) value, options(nomem, nostack)) };
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value
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}
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/// Swaps the floating-point accrued exception flags register `fflags`
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///
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/// This function swaps the value in `fflags` by copying the original value to be returned,
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/// and then writing a new value obtained from the five least-significant bits of
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/// input variable `value` into `fflags`.
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#[inline]
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pub fn fsflags(value: u32) -> u32 {
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let original: u32;
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unsafe { asm!("fsflags {}, {}", out(reg) original, in(reg) value, options(nomem, nostack)) }
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original
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}
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/// Invalidate hypervisor translation cache for all virtual machines and guest physical addresses
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///
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/// This instruction invalidates any address-translation cache entries that an
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@ -479,3 +584,188 @@ pub unsafe fn hinval_gvma_vmid(vmid: usize) {
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pub unsafe fn hinval_gvma_all() {
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asm!(".insn r 0x73, 0, 0x33, x0, x0, x0", options(nostack))
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}
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/// `P0` transformation function as is used in the SM3 hash algorithm
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///
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/// This function is included in `Zksh` extension. It's defined as:
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///
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/// ```text
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/// P0(X) = X ⊕ (X ≪ 9) ⊕ (X ≪ 17)
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/// ```
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///
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/// where `⊕` represents 32-bit xor, and `≪ k` represents rotate left by `k` bits.
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///
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/// In the SM3 algorithm, the `P0` transformation is used as `E ← P0(TT2)` when the
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/// compression function `CF` uses the intermediate value `TT2` to calculate
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/// the variable `E` in one iteration for subsequent processes.
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///
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/// According to RISC-V Cryptography Extensions, Volume I, the execution latency of
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/// this instruction must always be independent from the data it operates on.
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#[inline]
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pub fn sm3p0(x: u32) -> u32 {
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let ans: u32;
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unsafe {
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// asm!("sm3p0 {}, {}", out(reg) ans, in(reg) x, options(nomem, nostack))
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asm!(".insn i 0x13, 0x1, {}, {}, 0x108", out(reg) ans, in(reg) x, options(nomem, nostack))
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};
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ans
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}
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/// `P1` transformation function as is used in the SM3 hash algorithm
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///
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/// This function is included in `Zksh` extension. It's defined as:
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///
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/// ```text
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/// P1(X) = X ⊕ (X ≪ 15) ⊕ (X ≪ 23)
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/// ```
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///
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/// where `⊕` represents 32-bit xor, and `≪ k` represents rotate left by `k` bits.
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///
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/// In the SM3 algorithm, the `P1` transformation is used to expand message,
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/// where expanded word `Wj` can be generated from the previous words.
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/// The whole process can be described as the following pseudocode:
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///
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/// ```text
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/// FOR j=16 TO 67
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/// Wj ← P1(Wj−16 ⊕ Wj−9 ⊕ (Wj−3 ≪ 15)) ⊕ (Wj−13 ≪ 7) ⊕ Wj−6
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/// ENDFOR
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/// ```
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///
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/// According to RISC-V Cryptography Extensions, Volume I, the execution latency of
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/// this instruction must always be independent from the data it operates on.
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#[inline]
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pub fn sm3p1(x: u32) -> u32 {
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let ans: u32;
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unsafe {
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// asm!("sm3p1 {}, {}", out(reg) ans, in(reg) x, options(nomem, nostack))
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asm!(".insn i 0x13, 0x1, {}, {}, 0x109", out(reg) ans, in(reg) x, options(nomem, nostack))
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};
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ans
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}
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/// Accelerates the round function `F` in the SM4 block cipher algorithm
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///
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/// This instruction is included in extension `Zksed`. It's defined as:
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///
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/// ```text
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/// SM4ED(x, a, BS) = x ⊕ T(ai)
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/// ... where
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/// ai = a.bytes[BS]
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/// T(ai) = L(τ(ai))
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/// bi = τ(ai) = SM4-S-Box(ai)
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/// ci = L(bi) = bi ⊕ (bi ≪ 2) ⊕ (bi ≪ 10) ⊕ (bi ≪ 18) ⊕ (bi ≪ 24)
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/// SM4ED = (ci ≪ (BS * 8)) ⊕ x
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/// ```
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///
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/// where `⊕` represents 32-bit xor, and `≪ k` represents rotate left by `k` bits.
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/// As is defined above, `T` is a combined transformation of non linear S-Box transform `τ`
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/// and linear layer transform `L`.
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///
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/// In the SM4 algorithm, the round function `F` is defined as:
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///
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/// ```text
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/// F(x0, x1, x2, x3, rk) = x0 ⊕ T(x1 ⊕ x2 ⊕ x3 ⊕ rk)
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/// ... where
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/// T(A) = L(τ(A))
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/// B = τ(A) = (SM4-S-Box(a0), SM4-S-Box(a1), SM4-S-Box(a2), SM4-S-Box(a3))
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/// C = L(B) = B ⊕ (B ≪ 2) ⊕ (B ≪ 10) ⊕ (B ≪ 18) ⊕ (B ≪ 24)
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/// ```
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///
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/// It can be implemented by `sm4ed` instruction like:
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///
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/// ```no_run
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/// let a = x1 ^ x2 ^ x3 ^ rk;
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/// let c0 = sm4ed::<0>(x0, a);
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/// let c1 = sm4ed::<1>(c0, a); // c1 represents c[0..=1], etc.
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/// let c2 = sm4ed::<2>(c1, a);
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/// let c3 = sm4ed::<3>(c2, a);
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/// return c3; // c3 represents c[0..=3]
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/// ```
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///
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/// According to RISC-V Cryptography Extensions, Volume I, the execution latency of
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/// this instruction must always be independent from the data it operates on.
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pub fn sm4ed<const BS: u8>(x: u32, a: u32) -> u32 {
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static_assert!(BS: u8 where BS <= 3);
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let ans: u32;
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match BS {
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0 => unsafe {
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asm!(".insn r 0x33, 0, 0x18, {}, {}, {}", out(reg) ans, in(reg) x, in(reg) a, options(nomem, nostack))
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},
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1 => unsafe {
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asm!(".insn r 0x33, 0, 0x38, {}, {}, {}", out(reg) ans, in(reg) x, in(reg) a, options(nomem, nostack))
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},
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2 => unsafe {
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asm!(".insn r 0x33, 0, 0x58, {}, {}, {}", out(reg) ans, in(reg) x, in(reg) a, options(nomem, nostack))
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},
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3 => unsafe {
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asm!(".insn r 0x33, 0, 0x78, {}, {}, {}", out(reg) ans, in(reg) x, in(reg) a, options(nomem, nostack))
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},
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_ => unreachable!(),
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};
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ans
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}
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/// Accelerates the key schedule operation in the SM4 block cipher algorithm
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///
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/// This instruction is included in extension `Zksed`. It's defined as:
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///
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/// ```text
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/// SM4KS(x, k, BS) = x ⊕ T'(ki)
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/// ... where
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/// ki = k.bytes[BS]
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/// T'(ki) = L'(τ(ki))
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/// bi = τ(ki) = SM4-S-Box(ki)
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/// ci = L'(bi) = bi ⊕ (bi ≪ 13) ⊕ (bi ≪ 23)
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/// SM4KS = (ci ≪ (BS * 8)) ⊕ x
|
||||
/// ```
|
||||
///
|
||||
/// where `⊕` represents 32-bit xor, and `≪ k` represents rotate left by `k` bits.
|
||||
/// As is defined above, `T'` is a combined transformation of non linear S-Box transform `τ`
|
||||
/// and the replaced linear layer transform `L'`.
|
||||
///
|
||||
/// In the SM4 algorithm, the key schedule is defined as:
|
||||
///
|
||||
/// ```text
|
||||
/// rk[i] = K[i+4] = K[i] ⊕ T'(K[i+1] ⊕ K[i+2] ⊕ K[i+3] ⊕ CK[i])
|
||||
/// ... where
|
||||
/// K[0..=3] = MK[0..=3] ⊕ FK[0..=3]
|
||||
/// T'(K) = L'(τ(K))
|
||||
/// B = τ(K) = (SM4-S-Box(k0), SM4-S-Box(k1), SM4-S-Box(k2), SM4-S-Box(k3))
|
||||
/// C = L'(B) = B ⊕ (B ≪ 13) ⊕ (B ≪ 23)
|
||||
/// ```
|
||||
///
|
||||
/// where `MK` represents the input 128-bit encryption key,
|
||||
/// constants `FK` and `CK` are fixed system configuration constant values defined by the SM4 algorithm.
|
||||
/// Hence, the key schedule operation can be implemented by `sm4ks` instruction like:
|
||||
///
|
||||
/// ```no_run
|
||||
/// let k = k1 ^ k2 ^ k3 ^ ck_i;
|
||||
/// let c0 = sm4ks::<0>(k0, k);
|
||||
/// let c1 = sm4ks::<1>(c0, k); // c1 represents c[0..=1], etc.
|
||||
/// let c2 = sm4ks::<2>(c1, k);
|
||||
/// let c3 = sm4ks::<3>(c2, k);
|
||||
/// return c3; // c3 represents c[0..=3]
|
||||
/// ```
|
||||
///
|
||||
/// According to RISC-V Cryptography Extensions, Volume I, the execution latency of
|
||||
/// this instruction must always be independent from the data it operates on.
|
||||
pub fn sm4ks<const BS: u8>(x: u32, k: u32) -> u32 {
|
||||
static_assert!(BS: u8 where BS <= 3);
|
||||
let ans: u32;
|
||||
match BS {
|
||||
0 => unsafe {
|
||||
asm!(".insn r 0x33, 0, 0x1A, {}, {}, {}", out(reg) ans, in(reg) x, in(reg) k, options(nomem, nostack))
|
||||
},
|
||||
1 => unsafe {
|
||||
asm!(".insn r 0x33, 0, 0x3A, {}, {}, {}", out(reg) ans, in(reg) x, in(reg) k, options(nomem, nostack))
|
||||
},
|
||||
2 => unsafe {
|
||||
asm!(".insn r 0x33, 0, 0x5A, {}, {}, {}", out(reg) ans, in(reg) x, in(reg) k, options(nomem, nostack))
|
||||
},
|
||||
3 => unsafe {
|
||||
asm!(".insn r 0x33, 0, 0x7A, {}, {}, {}", out(reg) ans, in(reg) x, in(reg) k, options(nomem, nostack))
|
||||
},
|
||||
_ => unreachable!(),
|
||||
};
|
||||
ans
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue