Fix: Utilize LLVM intrinsics where possible
This commit is contained in:
Gijs Burghoorn
Amanieu d'Antras
parent
7fd998870d
commit
0e0a78a3f0
3 changed files with 112 additions and 310 deletions
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@ -1,4 +1,5 @@
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use core::arch::asm;
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#[cfg(test)]
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use stdarch_test::assert_instr;
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macro_rules! static_assert_imm2 {
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($imm:ident) => {
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@ -21,6 +22,30 @@ extern "unadjusted" {
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#[link_name = "llvm.riscv.aes32dsmi"]
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fn _aes32dsmi(rs1: i32, rs2: i32, bs: i32) -> i32;
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#[link_name = "llvm.riscv.zip.i32"]
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fn _zip(rs1: i32) -> i32;
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#[link_name = "llvm.riscv.unzip.i32"]
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fn _unzip(rs1: i32) -> i32;
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#[link_name = "llvm.riscv.sha512sig0h"]
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fn _sha512sig0h(rs1: i32, rs2: i32) -> i32;
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#[link_name = "llvm.riscv.sha512sig0l"]
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fn _sha512sig0l(rs1: i32, rs2: i32) -> i32;
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#[link_name = "llvm.riscv.sha512sig1h"]
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fn _sha512sig1h(rs1: i32, rs2: i32) -> i32;
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#[link_name = "llvm.riscv.sha512sig1l"]
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fn _sha512sig1l(rs1: i32, rs2: i32) -> i32;
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#[link_name = "llvm.riscv.sha512sum0r"]
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fn _sha512sum0r(rs1: i32, rs2: i32) -> i32;
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#[link_name = "llvm.riscv.sha512sum1r"]
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fn _sha512sum1r(rs1: i32, rs2: i32) -> i32;
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}
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/// AES final round encryption instruction for RV32.
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@ -166,17 +191,8 @@ pub unsafe fn aes32dsmi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
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#[target_feature(enable = "zbkb")]
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#[cfg_attr(test, assert_instr(zip))]
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#[inline]
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pub unsafe fn zip(rs: usize) -> usize {
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let value: usize;
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unsafe {
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asm!(
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"zip {rd},{rs}",
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rd = lateout(reg) value,
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rs = in(reg) rs,
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options(pure, nomem, nostack),
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)
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}
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value
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pub unsafe fn zip(rs: u32) -> u32 {
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_zip(rs as i32) as u32
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}
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/// Place odd and even bits of the source word into upper/lower halves of the destination.
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@ -197,17 +213,8 @@ pub unsafe fn zip(rs: usize) -> usize {
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#[target_feature(enable = "zbkb")]
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#[cfg_attr(test, assert_instr(unzip))]
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#[inline]
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pub unsafe fn unzip(rs: usize) -> usize {
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let value: usize;
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unsafe {
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asm!(
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"unzip {rd},{rs}",
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rd = lateout(reg) value,
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rs = in(reg) rs,
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options(pure, nomem, nostack),
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)
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}
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value
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pub unsafe fn unzip(rs: u32) -> u32 {
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_unzip(rs as i32) as u32
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}
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/// Implements the high half of the Sigma0 transformation, as used in the SHA2-512 hash
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@ -232,17 +239,7 @@ pub unsafe fn unzip(rs: usize) -> usize {
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#[cfg_attr(test, assert_instr(sha512sig0h))]
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#[inline]
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pub unsafe fn sha512sig0h(rs1: u32, rs2: u32) -> u32 {
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let value: u32;
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unsafe {
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asm!(
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"sha512sig0h {rd},{rs1},{rs2}",
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rd = lateout(reg) value,
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rs1 = in(reg) rs1,
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rs2 = in(reg) rs2,
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options(pure, nomem, nostack),
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)
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}
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value
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_sha512sig0h(rs1 as i32, rs2 as i32) as u32
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}
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/// Implements the low half of the Sigma0 transformation, as used in the SHA2-512 hash function
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@ -267,17 +264,7 @@ pub unsafe fn sha512sig0h(rs1: u32, rs2: u32) -> u32 {
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#[cfg_attr(test, assert_instr(sha512sig0l))]
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#[inline]
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pub unsafe fn sha512sig0l(rs1: u32, rs2: u32) -> u32 {
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let value: u32;
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unsafe {
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asm!(
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"sha512sig0l {rd},{rs1},{rs2}",
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rd = lateout(reg) value,
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rs1 = in(reg) rs1,
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rs2 = in(reg) rs2,
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options(pure, nomem, nostack),
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)
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}
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value
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_sha512sig0l(rs1 as i32, rs2 as i32) as u32
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}
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/// Implements the high half of the Sigma1 transformation, as used in the SHA2-512 hash
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@ -302,17 +289,7 @@ pub unsafe fn sha512sig0l(rs1: u32, rs2: u32) -> u32 {
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#[cfg_attr(test, assert_instr(sha512sig1h))]
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#[inline]
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pub unsafe fn sha512sig1h(rs1: u32, rs2: u32) -> u32 {
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let value: u32;
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unsafe {
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asm!(
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"sha512sig1h {rd},{rs1},{rs2}",
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rd = lateout(reg) value,
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rs1 = in(reg) rs1,
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rs2 = in(reg) rs2,
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options(pure, nomem, nostack),
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)
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}
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value
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_sha512sig1h(rs1 as i32, rs2 as i32) as u32
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}
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/// Implements the low half of the Sigma1 transformation, as used in the SHA2-512 hash function
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@ -337,17 +314,7 @@ pub unsafe fn sha512sig1h(rs1: u32, rs2: u32) -> u32 {
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#[cfg_attr(test, assert_instr(sha512sig1l))]
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#[inline]
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pub unsafe fn sha512sig1l(rs1: u32, rs2: u32) -> u32 {
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let value: u32;
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unsafe {
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asm!(
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"sha512sig1l {rd},{rs1},{rs2}",
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rd = lateout(reg) value,
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rs1 = in(reg) rs1,
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rs2 = in(reg) rs2,
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options(pure, nomem, nostack),
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)
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}
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value
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_sha512sig1l(rs1 as i32, rs2 as i32) as u32
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}
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/// Implements the Sum0 transformation, as used in the SHA2-512 hash function \[49\] (Section
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@ -371,17 +338,7 @@ pub unsafe fn sha512sig1l(rs1: u32, rs2: u32) -> u32 {
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#[cfg_attr(test, assert_instr(sha512sum0r))]
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#[inline]
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pub unsafe fn sha512sum0r(rs1: u32, rs2: u32) -> u32 {
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let value: u32;
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unsafe {
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asm!(
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"sha512sum0r {rd},{rs1},{rs2}",
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rd = lateout(reg) value,
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rs1 = in(reg) rs1,
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rs2 = in(reg) rs2,
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options(pure, nomem, nostack),
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)
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}
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value
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_sha512sum0r(rs1 as i32, rs2 as i32) as u32
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}
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/// Implements the Sum1 transformation, as used in the SHA2-512 hash function \[49\] (Section
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@ -405,15 +362,5 @@ pub unsafe fn sha512sum0r(rs1: u32, rs2: u32) -> u32 {
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#[cfg_attr(test, assert_instr(sha512sum1r))]
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#[inline]
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pub unsafe fn sha512sum1r(rs1: u32, rs2: u32) -> u32 {
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let value: u32;
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unsafe {
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asm!(
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"sha512sum1r {rd},{rs1},{rs2}",
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rd = lateout(reg) value,
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rs1 = in(reg) rs1,
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rs2 = in(reg) rs2,
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options(pure, nomem, nostack),
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)
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}
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value
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_sha512sum1r(rs1 as i32, rs2 as i32) as u32
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}
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@ -1,5 +1,8 @@
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use core::arch::asm;
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#[cfg(test)]
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use stdarch_test::assert_instr;
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macro_rules! static_assert_imm_0_until_10 {
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($imm:ident) => {
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static_assert!(
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@ -10,8 +13,35 @@ macro_rules! static_assert_imm_0_until_10 {
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}
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extern "unadjusted" {
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#[link_name = "llvm.riscv.aes64es"]
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fn _aes64es(rs1: i64, rs2: i64) -> i64;
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#[link_name = "llvm.riscv.aes64esm"]
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fn _aes64esm(rs1: i64, rs2: i64) -> i64;
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#[link_name = "llvm.riscv.aes64ds"]
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fn _aes64ds(rs1: i64, rs2: i64) -> i64;
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#[link_name = "llvm.riscv.aes64dsm"]
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fn _aes64dsm(rs1: i64, rs2: i64) -> i64;
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#[link_name = "llvm.riscv.aes64ks1i"]
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fn _aes64ks1i(rs1: i64, rnum: i32) -> i64;
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#[link_name = "llvm.riscv.aes64ks2"]
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fn _aes64ks2(rs1: i64, rs2: i64) -> i64;
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#[link_name = "llvm.riscv.sha512sig0"]
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fn _sha512sig0(rs1: i64) -> i64;
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#[link_name = "llvm.riscv.sha512sig1"]
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fn _sha512sig1(rs1: i64) -> i64;
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#[link_name = "llvm.riscv.sha512sum0"]
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fn _sha512sum0(rs1: i64) -> i64;
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#[link_name = "llvm.riscv.sha512sum1"]
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fn _sha512sum1(rs1: i64) -> i64;
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}
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/// AES final round encryption instruction for RV64.
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@ -34,17 +64,7 @@ extern "unadjusted" {
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#[cfg_attr(test, assert_instr(aes64es))]
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#[inline]
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pub unsafe fn aes64es(rs1: u64, rs2: u64) -> u64 {
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let value: u64;
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unsafe {
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asm!(
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"aes64es {rd},{rs1},{rs2}",
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rd = lateout(reg) value,
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rs1 = in(reg) rs1,
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rs2 = in(reg) rs2,
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options(pure, nomem, nostack),
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)
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}
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value
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_aes64es(rs1 as i64, rs2 as i64) as u64
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}
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/// AES middle round encryption instruction for RV64.
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@ -67,17 +87,7 @@ pub unsafe fn aes64es(rs1: u64, rs2: u64) -> u64 {
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#[cfg_attr(test, assert_instr(aes64esm))]
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#[inline]
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pub unsafe fn aes64esm(rs1: u64, rs2: u64) -> u64 {
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let value: u64;
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unsafe {
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asm!(
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"aes64esm {rd},{rs1},{rs2}",
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rd = lateout(reg) value,
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rs1 = in(reg) rs1,
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rs2 = in(reg) rs2,
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options(pure, nomem, nostack),
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)
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}
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value
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_aes64esm(rs1 as i64, rs2 as i64) as u64
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}
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/// AES final round decryption instruction for RV64.
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@ -100,17 +110,7 @@ pub unsafe fn aes64esm(rs1: u64, rs2: u64) -> u64 {
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#[cfg_attr(test, assert_instr(aes64ds))]
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#[inline]
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pub unsafe fn aes64ds(rs1: u64, rs2: u64) -> u64 {
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let value: u64;
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unsafe {
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asm!(
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"aes64ds {rd},{rs1},{rs2}",
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rd = lateout(reg) value,
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rs1 = in(reg) rs1,
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rs2 = in(reg) rs2,
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options(pure, nomem, nostack),
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)
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}
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value
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_aes64ds(rs1 as i64, rs2 as i64) as u64
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}
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/// AES middle round decryption instruction for RV64.
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@ -133,17 +133,7 @@ pub unsafe fn aes64ds(rs1: u64, rs2: u64) -> u64 {
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#[cfg_attr(test, assert_instr(aes64dsm))]
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#[inline]
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pub unsafe fn aes64dsm(rs1: u64, rs2: u64) -> u64 {
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let value: u64;
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unsafe {
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asm!(
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"aes64dsm {rd},{rs1},{rs2}",
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rd = lateout(reg) value,
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rs1 = in(reg) rs1,
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rs2 = in(reg) rs2,
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options(pure, nomem, nostack),
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)
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}
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value
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_aes64dsm(rs1 as i64, rs2 as i64) as u64
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}
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/// This instruction implements part of the KeySchedule operation for the AES Block cipher
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@ -196,17 +186,7 @@ pub unsafe fn aes64ks1i<const RNUM: u8>(rs1: u64) -> u64 {
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#[cfg_attr(test, assert_instr(aes64ks2))]
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#[inline]
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pub unsafe fn aes64ks2(rs1: u64, rs2: u64) -> u64 {
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let value: u64;
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unsafe {
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asm!(
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"aes64ks2 {rd},{rs1},{rs2}",
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rd = lateout(reg) value,
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rs1 = in(reg) rs1,
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rs2 = in(reg) rs2,
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options(pure, nomem, nostack),
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)
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}
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value
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_aes64ks2(rs1 as i64, rs2 as i64) as u64
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}
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/// Pack the low 16-bits of rs1 and rs2 into rd on RV64
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@ -228,6 +208,8 @@ pub unsafe fn aes64ks2(rs1: u64, rs2: u64) -> u64 {
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#[cfg_attr(test, assert_instr(packw))]
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#[inline]
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pub unsafe fn packw(rs1: u64, rs2: u64) -> u64 {
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// Note: There is no LLVM intrinsic for this instruction currently.
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let value: u64;
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unsafe {
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asm!(
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@ -261,16 +243,7 @@ pub unsafe fn packw(rs1: u64, rs2: u64) -> u64 {
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#[cfg_attr(test, assert_instr(sha512sig0))]
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#[inline]
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pub unsafe fn sha512sig0(rs1: u64) -> u64 {
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let value: u64;
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unsafe {
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asm!(
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"sha512sig0 {rd},{rs1}",
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rd = lateout(reg) value,
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rs1 = in(reg) rs1,
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options(pure, nomem, nostack),
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)
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}
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value
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_sha512sig0(rs1 as i64) as u64
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}
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/// Implements the Sigma1 transformation function as used in the SHA2-512 hash function \[49\]
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@ -293,16 +266,7 @@ pub unsafe fn sha512sig0(rs1: u64) -> u64 {
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#[cfg_attr(test, assert_instr(sha512sig1))]
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#[inline]
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pub unsafe fn sha512sig1(rs1: u64) -> u64 {
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let value: u64;
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unsafe {
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asm!(
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"sha512sig1 {rd},{rs1}",
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rd = lateout(reg) value,
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rs1 = in(reg) rs1,
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options(pure, nomem, nostack),
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)
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}
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value
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_sha512sig1(rs1 as i64) as u64
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}
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/// Implements the Sum0 transformation function as used in the SHA2-512 hash function \[49\]
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@ -325,16 +289,7 @@ pub unsafe fn sha512sig1(rs1: u64) -> u64 {
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#[cfg_attr(test, assert_instr(sha512sum0))]
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#[inline]
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pub unsafe fn sha512sum0(rs1: u64) -> u64 {
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let value: u64;
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unsafe {
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asm!(
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"sha512sum0 {rd},{rs1}",
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rd = lateout(reg) value,
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rs1 = in(reg) rs1,
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options(pure, nomem, nostack),
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)
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}
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value
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_sha512sum0(rs1 as i64) as u64
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}
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/// Implements the Sum1 transformation function as used in the SHA2-512 hash function \[49\]
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@ -357,14 +312,5 @@ pub unsafe fn sha512sum0(rs1: u64) -> u64 {
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#[cfg_attr(test, assert_instr(sha512sum1))]
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#[inline]
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pub unsafe fn sha512sum1(rs1: u64) -> u64 {
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let value: u64;
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unsafe {
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asm!(
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"sha512sum1 {rd},{rs1}",
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rd = lateout(reg) value,
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rs1 = in(reg) rs1,
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options(pure, nomem, nostack),
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)
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}
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value
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_sha512sum1(rs1 as i64) as u64
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}
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|
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@ -1,5 +1,8 @@
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use core::arch::asm;
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#[cfg(test)]
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use stdarch_test::assert_instr;
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macro_rules! static_assert_imm2 {
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($imm:ident) => {
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static_assert!(
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@ -15,6 +18,24 @@ extern "unadjusted" {
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#[link_name = "llvm.riscv.sm4ks"]
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fn _sm4ks(rs1: i32, rs2: i32, bs: i32) -> i32;
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#[link_name = "llvm.riscv.sm3p0"]
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fn _sm3p0(rs1: i32) -> i32;
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#[link_name = "llvm.riscv.sm3p1"]
|
||||
fn _sm3p1(rs1: i32) -> i32;
|
||||
|
||||
#[link_name = "llvm.riscv.sha256sig0"]
|
||||
fn _sha256sig0(rs1: i32) -> i32;
|
||||
|
||||
#[link_name = "llvm.riscv.sha256sig1"]
|
||||
fn _sha256sig1(rs1: i32) -> i32;
|
||||
|
||||
#[link_name = "llvm.riscv.sha256sum0"]
|
||||
fn _sha256sum0(rs1: i32) -> i32;
|
||||
|
||||
#[link_name = "llvm.riscv.sha256sum1"]
|
||||
fn _sha256sum1(rs1: i32) -> i32;
|
||||
}
|
||||
|
||||
#[cfg(target_arch = "riscv32")]
|
||||
|
|
@ -35,37 +56,6 @@ extern "unadjusted" {
|
|||
fn _xperm4_64(rs1: i64, rs2: i64) -> i64;
|
||||
}
|
||||
|
||||
/// Pack the low halves of rs1 and rs2 into rd.
|
||||
///
|
||||
/// The pack instruction packs the XLEN/2-bit lower halves of rs1 and rs2 into rd, with rs1 in
|
||||
/// the lower half and rs2 in the upper half.
|
||||
///
|
||||
/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions
|
||||
///
|
||||
/// Version: v1.0.1
|
||||
///
|
||||
/// Section: 3.17
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// This function is safe to use if the `zbkb` target feature is present.
|
||||
#[target_feature(enable = "zbkb")]
|
||||
#[cfg_attr(test, assert_instr(pack))]
|
||||
#[inline]
|
||||
pub unsafe fn pack(rs1: usize, rs2: usize) -> usize {
|
||||
let value: usize;
|
||||
unsafe {
|
||||
asm!(
|
||||
"pack {rd},{rs1},{rs2}",
|
||||
rd = lateout(reg) value,
|
||||
rs1 = in(reg) rs1,
|
||||
rs2 = in(reg) rs2,
|
||||
options(pure, nomem, nostack),
|
||||
)
|
||||
}
|
||||
value
|
||||
}
|
||||
|
||||
/// Pack the low bytes of rs1 and rs2 into rd.
|
||||
///
|
||||
/// And the packh instruction packs the least-significant bytes of rs1 and rs2 into the 16
|
||||
|
|
@ -84,6 +74,8 @@ pub unsafe fn pack(rs1: usize, rs2: usize) -> usize {
|
|||
#[cfg_attr(test, assert_instr(packh))]
|
||||
#[inline]
|
||||
pub unsafe fn packh(rs1: usize, rs2: usize) -> usize {
|
||||
// Note: There is no LLVM intrinsic for this instruction currently.
|
||||
|
||||
let value: usize;
|
||||
unsafe {
|
||||
asm!(
|
||||
|
|
@ -97,35 +89,6 @@ pub unsafe fn packh(rs1: usize, rs2: usize) -> usize {
|
|||
value
|
||||
}
|
||||
|
||||
/// Reverse the bits in each byte of a source register.
|
||||
///
|
||||
/// This instruction reverses the order of the bits in every byte of a register.
|
||||
///
|
||||
/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions
|
||||
///
|
||||
/// Version: v1.0.1
|
||||
///
|
||||
/// Section: 3.13
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// This function is safe to use if the `zbkb` target feature is present.
|
||||
#[target_feature(enable = "zbkb")]
|
||||
#[cfg_attr(test, assert_instr(brev8))]
|
||||
#[inline]
|
||||
pub unsafe fn brev8(rs: usize) -> usize {
|
||||
let value: usize;
|
||||
unsafe {
|
||||
asm!(
|
||||
"brev8 {rd},{rs}",
|
||||
rd = lateout(reg) value,
|
||||
rs = in(reg) rs,
|
||||
options(pure, nomem, nostack),
|
||||
)
|
||||
}
|
||||
value
|
||||
}
|
||||
|
||||
/// Byte-wise lookup of indicies into a vector in registers.
|
||||
///
|
||||
/// The xperm8 instruction operates on bytes. The rs1 register contains a vector of XLEN/8
|
||||
|
|
@ -210,17 +173,8 @@ pub unsafe fn xperm4(rs1: usize, rs2: usize) -> usize {
|
|||
#[target_feature(enable = "zknh")]
|
||||
#[cfg_attr(test, assert_instr(sha256sig0))]
|
||||
#[inline]
|
||||
pub unsafe fn sha256sig0(rs1: usize) -> usize {
|
||||
let value: usize;
|
||||
unsafe {
|
||||
asm!(
|
||||
"sha256sig0 {rd},{rs1}",
|
||||
rd = lateout(reg) value,
|
||||
rs1 = in(reg) rs1,
|
||||
options(pure, nomem, nostack),
|
||||
)
|
||||
}
|
||||
value
|
||||
pub unsafe fn sha256sig0(rs1: u32) -> u32 {
|
||||
_sha256sig0(rs1 as i32) as u32
|
||||
}
|
||||
|
||||
/// Implements the Sigma1 transformation function as used in the SHA2-256 hash function \[49\]
|
||||
|
|
@ -245,17 +199,8 @@ pub unsafe fn sha256sig0(rs1: usize) -> usize {
|
|||
#[target_feature(enable = "zknh")]
|
||||
#[cfg_attr(test, assert_instr(sha256sig1))]
|
||||
#[inline]
|
||||
pub unsafe fn sha256sig1(rs1: usize) -> usize {
|
||||
let value: usize;
|
||||
unsafe {
|
||||
asm!(
|
||||
"sha256sig1 {rd},{rs1}",
|
||||
rd = lateout(reg) value,
|
||||
rs1 = in(reg) rs1,
|
||||
options(pure, nomem, nostack),
|
||||
)
|
||||
}
|
||||
value
|
||||
pub unsafe fn sha256sig1(rs1: u32) -> u32 {
|
||||
_sha256sig1(rs1 as i32) as u32
|
||||
}
|
||||
|
||||
/// Implements the Sum0 transformation function as used in the SHA2-256 hash function \[49\]
|
||||
|
|
@ -280,17 +225,8 @@ pub unsafe fn sha256sig1(rs1: usize) -> usize {
|
|||
#[target_feature(enable = "zknh")]
|
||||
#[cfg_attr(test, assert_instr(sha256sum0))]
|
||||
#[inline]
|
||||
pub unsafe fn sha256sum0(rs1: usize) -> usize {
|
||||
let value: usize;
|
||||
unsafe {
|
||||
asm!(
|
||||
"sha256sum0 {rd},{rs1}",
|
||||
rd = lateout(reg) value,
|
||||
rs1 = in(reg) rs1,
|
||||
options(pure, nomem, nostack),
|
||||
)
|
||||
}
|
||||
value
|
||||
pub unsafe fn sha256sum0(rs1: u32) -> u32 {
|
||||
_sha256sum0(rs1 as i32) as u32
|
||||
}
|
||||
|
||||
/// Implements the Sum1 transformation function as used in the SHA2-256 hash function \[49\]
|
||||
|
|
@ -315,17 +251,8 @@ pub unsafe fn sha256sum0(rs1: usize) -> usize {
|
|||
#[target_feature(enable = "zknh")]
|
||||
#[cfg_attr(test, assert_instr(sha256sum1))]
|
||||
#[inline]
|
||||
pub unsafe fn sha256sum1(rs1: usize) -> usize {
|
||||
let value: usize;
|
||||
unsafe {
|
||||
asm!(
|
||||
"sha256sum1 {rd},{rs1}",
|
||||
rd = lateout(reg) value,
|
||||
rs1 = in(reg) rs1,
|
||||
options(pure, nomem, nostack),
|
||||
)
|
||||
}
|
||||
value
|
||||
pub unsafe fn sha256sum1(rs1: u32) -> u32 {
|
||||
_sha256sum1(rs1 as i32) as u32
|
||||
}
|
||||
|
||||
/// Accelerates the block encrypt/decrypt operation of the SM4 block cipher \[5, 31\].
|
||||
|
|
@ -520,17 +447,8 @@ pub unsafe fn sm4ks<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
|
|||
#[target_feature(enable = "zksh")]
|
||||
#[cfg_attr(test, assert_instr(sm3p0))]
|
||||
#[inline]
|
||||
pub unsafe fn sm3p0(rs1: usize) -> usize {
|
||||
let value: usize;
|
||||
unsafe {
|
||||
asm!(
|
||||
"sm3p0 {rd},{rs1}",
|
||||
rd = lateout(reg) value,
|
||||
rs1 = in(reg) rs1,
|
||||
options(pure, nomem, nostack),
|
||||
)
|
||||
}
|
||||
value
|
||||
pub unsafe fn sm3p0(rs1: u32) -> u32 {
|
||||
_sm3p0(rs1 as i32) as u32
|
||||
}
|
||||
|
||||
/// Implements the P1 transformation function as used in the SM3 hash function [4, 30].
|
||||
|
|
@ -573,15 +491,6 @@ pub unsafe fn sm3p0(rs1: usize) -> usize {
|
|||
#[target_feature(enable = "zksh")]
|
||||
#[cfg_attr(test, assert_instr(sm3p1))]
|
||||
#[inline]
|
||||
pub unsafe fn sm3p1(rs1: usize) -> usize {
|
||||
let value: usize;
|
||||
unsafe {
|
||||
asm!(
|
||||
"sm3p1 {rd},{rs1}",
|
||||
rd = lateout(reg) value,
|
||||
rs1 = in(reg) rs1,
|
||||
options(pure, nomem, nostack),
|
||||
)
|
||||
}
|
||||
value
|
||||
pub unsafe fn sm3p1(rs1: u32) -> u32 {
|
||||
_sm3p1(rs1 as i32) as u32
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue