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Avx512f avx512vl (#995)

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minybot 2021-02-06 11:56:47 -05:00 • committed by GitHub
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library/stdarch/crates/core_arch/avx512f.md
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@ -1176,22 +1176,167 @@
* [x] [`_mm256_mask_andnot_epi64`]
* [x] [`_mm256_maskz_andnot_epi64`]
* [x] [`_mm512_andnot_si512`]
* [x] [`_mm512_mask_unpackhi_epi32`]
* [x] [`_mm512_unpackhi_epi32`]
* [x] [`_mm_mask_unpackhi_epi32`]
* [x] [`_mm_maskz_unpackhi_epi32`]
* [x] [`_mm256_mask_unpackhi_epi32`]
* [x] [`_mm256_maskz_unpackhi_epi32`]
* [x] [`_mm512_unpackhi_epi64`]
* [x] [`_mm512_mask_unpackhi_epi64`]
* [x] [`_mm_mask_unpackhi_epi64`]
* [x] [`_mm_maskz_unpackhi_epi64`]
* [x] [`_mm256_mask_unpackhi_epi64`]
* [x] [`_mm256_maskz_unpackhi_epi64`]
* [x] [`_mm512_unpackhi_ps`]
* [x] [`_mm512_mask_unpackhi_ps`]
* [x] [`_mm_mask_unpackhi_ps`]
* [x] [`_mm_maskz_unpackhi_ps`]
* [x] [`_mm256_mask_unpackhi_ps`]
* [x] [`_mm256_maskz_unpackhi_ps`]
* [x] [`_mm512_unpackhi_pd`]
* [x] [`_mm512_mask_unpackhi_pd`]
* [x] [`_mm_mask_unpackhi_pd`]
* [x] [`_mm_maskz_unpackhi_pd`]
* [x] [`_mm256_mask_unpackhi_pd`]
* [x] [`_mm256_maskz_unpackhi_pd`]
* [x] [`_mm512_mask_unpacklo_epi32`]
* [x] [`_mm512_unpacklo_epi32`]
* [x] [`_mm_mask_unpacklo_epi32`]
* [x] [`_mm_maskz_unpacklo_epi32`]
* [x] [`_mm256_mask_unpacklo_epi32`]
* [x] [`_mm256_maskz_unpacklo_epi32`]
* [x] [`_mm512_unpacklo_epi64`]
* [x] [`_mm512_mask_unpacklo_epi64`]
* [x] [`_mm_mask_unpacklo_epi64`]
* [x] [`_mm_maskz_unpacklo_epi64`]
* [x] [`_mm256_mask_unpacklo_epi64`]
* [x] [`_mm256_maskz_unpacklo_epi64`]
* [x] [`_mm512_unpacklo_ps`]
* [x] [`_mm512_mask_unpacklo_ps`]
* [x] [`_mm_mask_unpacklo_ps`]
* [x] [`_mm_maskz_unpacklo_ps`]
* [x] [`_mm256_mask_unpacklo_ps`]
* [x] [`_mm256_maskz_unpacklo_ps`]
* [x] [`_mm512_unpacklo_pd`]
* [x] [`_mm512_mask_unpacklo_pd`]
* [x] [`_mm_mask_unpacklo_pd`]
* [x] [`_mm_maskz_unpacklo_pd`]
* [x] [`_mm256_mask_unpacklo_pd`]
* [x] [`_mm256_maskz_unpacklo_pd`]
* [x] [`_mm512_mask_blend_epi32`]
* [x] [`_mm_mask_blend_epi32`]
* [x] [`_mm256_mask_blend_epi32`]
* [x] [`_mm512_mask_blend_epi64`]
* [x] [`_mm_mask_blend_epi64`]
* [x] [`_mm256_mask_blend_epi64`]
* [x] [`_mm512_mask_blend_ps`]
* [x] [`_mm_mask_blend_ps`]
* [x] [`_mm256_mask_blend_ps`]
* [x] [`_mm512_mask_blend_pd`]
* [x] [`_mm_mask_blend_pd`]
* [x] [`_mm256_mask_blend_pd`]
* [x] [`_mm512_broadcast_f32x4`]
* [x] [`_mm512_mask_broadcast_f32x4`]
* [x] [`_mm512_maskz_broadcast_f32x4`]
* [x] [`_mm256_broadcast_f32x4`]
* [x] [`_mm256_mask_broadcast_f32x4`]
* [x] [`_mm256_maskz_broadcast_f32x4`]
* [x] [`_mm512_broadcast_f64x4`]
* [x] [`_mm512_mask_broadcast_f64x4`]
* [x] [`_mm512_maskz_broadcast_f64x4`]
* [x] [`_mm512_broadcast_i32x4`]
* [x] [`_mm512_mask_broadcast_i32x4`]
* [x] [`_mm512_maskz_broadcast_i32x4`]
* [x] [`_mm256_broadcast_i32x4`]
* [x] [`_mm256_mask_broadcast_i32x4`]
* [x] [`_mm256_maskz_broadcast_i32x4`]
* [x] [`_mm512_broadcast_i64x4`]
* [x] [`_mm512_mask_broadcast_i64x4`]
* [x] [`_mm512_maskz_broadcast_i64x4`]
* [x] [`_mm512_broadcastd_epi32`]
* [x] [`_mm512_mask_broadcastd_epi32`]
* [x] [`_mm512_maskz_broadcastd_epi32`]
* [x] [`_mm_mask_broadcastd_epi32`]
* [x] [`_mm_maskz_broadcastd_epi32`]
* [x] [`_mm256_mask_broadcastd_epi32`]
* [x] [`_mm256_maskz_broadcastd_epi32`]
* [x] [`_mm512_broadcastq_epi64`]
* [x] [`_mm512_mask_broadcastq_epi64`]
* [x] [`_mm512_maskz_broadcastq_epi64`]
* [x] [`_mm_mask_broadcastq_epi64`]
* [x] [`_mm_maskz_broadcastq_epi64`]
* [x] [`_mm256_mask_broadcastq_epi64`]
* [x] [`_mm256_maskz_broadcastq_epi64`]
* [x] [`_mm512_broadcastss_ps`]
* [x] [`_mm512_mask_broadcastss_ps`]
* [x] [`_mm512_maskz_broadcastss_ps`]
* [x] [`_mm_mask_broadcastss_ps`]
* [x] [`_mm_maskz_broadcastss_ps`]
* [x] [`_mm256_mask_broadcastss_ps`]
* [x] [`_mm256_maskz_broadcastss_ps`]
* [x] [`_mm512_broadcastsd_pd`]
* [x] [`_mm512_mask_broadcastsd_pd`]
* [x] [`_mm512_maskz_broadcastsd_pd`]
* [x] [`_mm256_mask_broadcastsd_pd`]
* [x] [`_mm256_maskz_broadcastsd_pd`]
* [x] [`_mm512_shuffle_epi32`]
* [x] [`_mm512_mask_shuffle_epi32`]
* [x] [`_mm_mask_shuffle_epi32`]
* [x] [`_mm_maskz_shuffle_epi32`]
* [x] [`_mm256_mask_shuffle_epi32`]
* [x] [`_mm256_maskz_shuffle_epi32`]
* [x] [`_mm512_shuffle_ps`]
* [x] [`_mm512_mask_shuffle_ps`]
* [x] [`_mm_mask_shuffle_ps`]
* [x] [`_mm_maskz_shuffle_ps`]
* [x] [`_mm256_mask_shuffle_ps`]
* [x] [`_mm256_maskz_shuffle_ps`]
* [x] [`_mm512_shuffle_pd`]
* [x] [`_mm512_mask_shuffle_pd`]
* [x] [`_mm_mask_shuffle_pd`]
* [x] [`_mm_maskz_shuffle_pd`]
* [x] [`_mm256_mask_shuffle_pd`]
* [x] [`_mm256_maskz_shuffle_pd`]
* [x] [`_mm512_shuffle_i32x4`]
* [x] [`_mm512_mask_shuffle_i32x4`]
* [x] [`_mm256_mask_shuffle_i32x4`]
* [x] [`_mm256_maskz_shuffle_i32x4`]
* [x] [`_mm256_shuffle_i32x4`]
* [x] [`_mm512_shuffle_i64x2`]
* [x] [`_mm512_mask_shuffle_i64x2`]
* [x] [`_mm256_mask_shuffle_i64x2`]
* [x] [`_mm256_maskz_shuffle_i64x2`]
* [x] [`_mm256_shuffle_i64x2`]
* [x] [`_mm512_shuffle_f32x4`]
* [x] [`_mm512_mask_shuffle_f32x4`]
* [x] [`_mm256_mask_shuffle_f32x4`]
* [x] [`_mm256_maskz_shuffle_f32x4`]
* [x] [`_mm256_shuffle_f32x4`]
* [x] [`_mm512_shuffle_f64x2`]
* [x] [`_mm512_mask_shuffle_f64x2`]
* [x] [`_mm256_mask_shuffle_f64x2`]
* [x] [`_mm256_maskz_shuffle_f64x2`]
* [x] [`_mm256_shuffle_f64x2`]
* [x] [`_mm512_alignr_epi32`]
* [x] [`_mm512_mask_alignr_epi32`]
* [x] [`_mm512_maskz_alignr_epi32`]
* [x] [`_mm_alignr_epi32`]
* [x] [`_mm_mask_alignr_epi32`]
* [x] [`_mm_maskz_alignr_epi32`]
* [x] [`_mm256_alignr_epi32`]
* [x] [`_mm256_mask_alignr_epi32`]
* [x] [`_mm256_maskz_alignr_epi32`]
* [x] [`_mm512_alignr_epi64`]
* [x] [`_mm512_mask_alignr_epi64`]
* [x] [`_mm512_maskz_alignr_epi64`]
* [x] [`_mm_alignr_epi64`]
* [x] [`_mm_mask_alignr_epi64`]
* [x] [`_mm_maskz_alignr_epi64`]
* [x] [`_mm256_alignr_epi64`]
* [x] [`_mm256_mask_alignr_epi64`]
* [x] [`_mm256_maskz_alignr_epi64`]
* [x] [`_mm512_broadcast_f32x4`]
* [x] [`_mm512_broadcast_f64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_broadcast_f64x4&expand=5236)
* [x] [`_mm512_broadcast_i32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_broadcast_i32x4&expand=5236)
* [x] [`_mm512_broadcast_i64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_broadcast_i64x4&expand=5236)
* [x] [`_mm512_broadcastd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_broadcastd_epi32&expand=5236)
* [x] [`_mm512_broadcastq_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_broadcastq_epi64&expand=5236)
* [x] [`_mm512_broadcastsd_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_broadcastsd_pd&expand=5236)
* [x] [`_mm512_broadcastss_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_broadcastss_ps&expand=5236)
* [x] [`_mm512_castpd128_pd512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd128_pd512&expand=5236)
* [x] [`_mm512_castpd256_pd512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd256_pd512&expand=5236)
* [x] [`_mm512_castpd512_pd128`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd512_pd128&expand=5236)
@ -1330,20 +1475,8 @@
* [x] [`_mm512_mask2_permutex2var_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask2_permutex2var_pd&expand=5236)
* [x] [`_mm512_mask2_permutex2var_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask2_permutex2var_ps&expand=5236)
* [x] [`_mm512_mask2int`]
* [x] [`_mm512_mask_blend_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_blend_epi32&expand=5236)
* [x] [`_mm512_mask_blend_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_blend_epi64&expand=5236)
* [x] [`_mm512_mask_blend_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_blend_pd&expand=5236)
* [x] [`_mm512_mask_blend_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_blend_ps&expand=5236)
* [x] [`_mm512_mask_broadcast_f32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_broadcast_f32x4&expand=5236)
* [x] [`_mm512_mask_broadcast_f64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_broadcast_f64x4&expand=5236)
* [x] [`_mm512_mask_broadcast_i32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_broadcast_i32x4&expand=5236)
* [x] [`_mm512_mask_broadcast_i64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_broadcast_i64x4&expand=5236)
* [x] [`_mm512_mask_broadcastd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_broadcastd_epi32&expand=5236)
* [x] [`_mm512_mask_broadcastq_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_broadcastq_epi64&expand=5236)
* [x] [`_mm512_mask_broadcastsd_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_broadcastsd_pd&expand=5236)
* [x] [`_mm512_mask_broadcastss_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_broadcastss_ps&expand=5236)
* [x] [`_mm512_mask_compress_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_compress_epi32&expand=5236)
* [x] [`_mm512_mask_compress_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_compress_epi64&expand=5236)
* [x] [`_mm512_mask_compress_epi32`]
* [x] [`_mm512_mask_compress_epi64`]
* [x] [`_mm512_mask_compress_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_compress_pd&expand=5236)
* [x] [`_mm512_mask_compress_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_compress_ps&expand=5236)
* [ ] [`_mm512_mask_compressstoreu_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_compressstoreu_epi32&expand=5236)
@ -1492,13 +1625,6 @@
* [x] [`_mm512_mask_permutexvar_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_permutexvar_ps&expand=5236)
* [x] [`_mm512_mask_set1_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_set1_epi32&expand=5236)
* [x] [`_mm512_mask_set1_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_set1_epi64&expand=5236)
* [x] [`_mm512_mask_shuffle_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_shuffle_epi32&expand=5236)
* [x] [`_mm512_mask_shuffle_f32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_shuffle_f32x4&expand=5236)
* [x] [`_mm512_mask_shuffle_f64x2`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_shuffle_f64x2&expand=5236)
* [x] [`_mm512_mask_shuffle_i32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_shuffle_i32x4&expand=5236)
* [x] [`_mm512_mask_shuffle_i64x2`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_shuffle_i64x2&expand=5236)
* [x] [`_mm512_mask_shuffle_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_shuffle_pd&expand=5236)
* [x] [`_mm512_mask_shuffle_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_shuffle_ps&expand=5236)
* [ ] [`_mm512_mask_store_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_store_epi32&expand=5236)
* [ ] [`_mm512_mask_store_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_store_epi64&expand=5236)
* [ ] [`_mm512_mask_store_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_store_pd&expand=5236)
@ -1513,22 +1639,6 @@
* [x] [`_mm512_mask_test_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_test_epi64_mask&expand=5236)
* [x] [`_mm512_mask_testn_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_testn_epi32_mask&expand=5236)
* [x] [`_mm512_mask_testn_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_testn_epi64_mask&expand=5236)
* [x] [`_mm512_mask_unpackhi_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_unpackhi_epi32&expand=5236)
* [x] [`_mm512_mask_unpackhi_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_unpackhi_epi64&expand=5236)
* [x] [`_mm512_mask_unpackhi_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_unpackhi_pd&expand=5236)
* [x] [`_mm512_mask_unpackhi_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_unpackhi_ps&expand=5236)
* [x] [`_mm512_mask_unpacklo_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_unpacklo_epi32&expand=5236)
* [x] [`_mm512_mask_unpacklo_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_unpacklo_epi64&expand=5236)
* [x] [`_mm512_mask_unpacklo_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_unpacklo_pd&expand=5236)
* [x] [`_mm512_mask_unpacklo_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_unpacklo_ps&expand=5236)
* [x] [`_mm512_maskz_broadcast_f32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_broadcast_f32x4&expand=5236)
* [x] [`_mm512_maskz_broadcast_f64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_broadcast_f64x4&expand=5236)
* [x] [`_mm512_maskz_broadcast_i32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_broadcast_i32x4&expand=5236)
* [x] [`_mm512_maskz_broadcast_i64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_broadcast_i64x4&expand=5236)
* [x] [`_mm512_maskz_broadcastd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_broadcastd_epi32&expand=5236)
* [x] [`_mm512_maskz_broadcastq_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_broadcastq_epi64&expand=5236)
* [x] [`_mm512_maskz_broadcastsd_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_broadcastsd_pd&expand=5236)
* [x] [`_mm512_maskz_broadcastss_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_broadcastss_ps&expand=5236)
* [x] [`_mm512_maskz_compress_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_compress_epi32&expand=5236)
* [x] [`_mm512_maskz_compress_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_compress_epi64&expand=5236)
* [x] [`_mm512_maskz_compress_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_compress_pd&expand=5236)
@ -1680,22 +1790,15 @@
* [x] [`_mm512_setr4_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setr4_epi64&expand=5236)
* [x] [`_mm512_setr4_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setr4_pd&expand=5236)
* [x] [`_mm512_setr4_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setr4_ps&expand=5236)
* [x] [`_mm512_setr_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setr_epi32&expand=5236)
* [x] [`_mm512_setr_epi64`](https:/software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setr_epi64&expand=5236)
* [x] [`_mm512_setr_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setr_pd&expand=5236)
* [x] [`_mm512_setr_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setr_ps&expand=5236)
* [x] [`_mm512_setzero_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setzero_epi32&expand=5236)
* [x] [`_mm512_setzero_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setzero_pd&expand=5236)
* [x] [`_mm512_setzero_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setzero_ps&expand=5236)
* [x] [`_mm512_setzero_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setzero_si512&expand=5236)
* [x] [`_mm512_setzero`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setzero&expand=5236)
* [x] [`_mm512_shuffle_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_shuffle_epi32&expand=5236)
* [x] [`_mm512_shuffle_f32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_shuffle_f32x4&expand=5236)
* [x] [`_mm512_shuffle_f64x2`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_shuffle_f64x2&expand=5236)
* [x] [`_mm512_shuffle_i32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_shuffle_i32x4&expand=5236)
* [x] [`_mm512_shuffle_i64x2`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_shuffle_i64x2&expand=5236)
* [x] [`_mm512_shuffle_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_shuffle_pd&expand=5236)
* [x] [`_mm512_shuffle_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_shuffle_ps&expand=5236)
* [x] [`_mm512_setr_epi32`]
* [x] [`_mm512_setr_epi64`]
* [x] [`_mm512_setr_pd`]
* [x] [`_mm512_setr_ps`]
* [x] [`_mm512_setzero_epi32`]
* [x] [`_mm512_setzero_pd`]
* [x] [`_mm512_setzero_ps`]
* [x] [`_mm512_setzero_si512`]
* [x] [`_mm512_setzero`]
* [x] [`_mm512_store_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_store_epi32&expand=5236)
* [x] [`_mm512_store_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_store_epi64&expand=5236)
* [x] [`_mm512_store_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_store_pd&expand=5236)
@ -1721,14 +1824,6 @@
* [x] [`_mm512_undefined_pd`]
* [x] [`_mm512_undefined_ps`]
* [x] [`_mm512_undefined`]
* [x] [`_mm512_unpackhi_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_unpackhi_epi32&expand=5236)
* [x] [`_mm512_unpackhi_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_unpackhi_epi64&expand=5236)
* [x] [`_mm512_unpackhi_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_unpackhi_pd&expand=5236)
* [x] [`_mm512_unpackhi_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_unpackhi_ps&expand=5236)
* [x] [`_mm512_unpacklo_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_unpacklo_epi32&expand=5236)
* [x] [`_mm512_unpacklo_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_unpacklo_epi64&expand=5236)
* [x] [`_mm512_unpacklo_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_unpacklo_pd&expand=5236)
* [x] [`_mm512_unpacklo_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_unpacklo_ps&expand=5236)
* [x] [`_mm512_zextpd128_pd512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextpd128_pd512&expand=5236)
* [x] [`_mm512_zextpd256_pd512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextpd256_pd512&expand=5236)
* [x] [`_mm512_zextps128_ps512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextps128_ps512&expand=5236)

2677
library/stdarch/crates/core_arch/src/x86/avx512f.rs
View file

File diff suppressed because it is too large Load diff

454
library/stdarch/crates/core_arch/src/x86_64/avx512f.rs
View file

@ -7612,6 +7612,50 @@ mod tests {
assert_eq_m512d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_shuffle_pd() {
let a = _mm256_set_pd(1., 4., 5., 8.);
let b = _mm256_set_pd(2., 3., 6., 7.);
let r = _mm256_mask_shuffle_pd(a, 0, a, b, 1 << 0 | 1 << 1 | 1 << 2 | 1 << 3);
assert_eq_m256d(r, a);
let r = _mm256_mask_shuffle_pd(a, 0b00001111, a, b, 1 << 0 | 1 << 1 | 1 << 2 | 1 << 3);
let e = _mm256_set_pd(2., 1., 6., 5.);
assert_eq_m256d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_maskz_shuffle_pd() {
let a = _mm256_set_pd(1., 4., 5., 8.);
let b = _mm256_set_pd(2., 3., 6., 7.);
let r = _mm256_maskz_shuffle_pd(0, a, b, 1 << 0 | 1 << 1 | 1 << 2 | 1 << 3);
assert_eq_m256d(r, _mm256_setzero_pd());
let r = _mm256_maskz_shuffle_pd(0b00001111, a, b, 1 << 0 | 1 << 1 | 1 << 2 | 1 << 3);
let e = _mm256_set_pd(2., 1., 6., 5.);
assert_eq_m256d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_shuffle_pd() {
let a = _mm_set_pd(1., 4.);
let b = _mm_set_pd(2., 3.);
let r = _mm_mask_shuffle_pd(a, 0, a, b, 1 << 0 | 1 << 1);
assert_eq_m128d(r, a);
let r = _mm_mask_shuffle_pd(a, 0b00000011, a, b, 1 << 0 | 1 << 1);
let e = _mm_set_pd(2., 1.);
assert_eq_m128d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_maskz_shuffle_pd() {
let a = _mm_set_pd(1., 4.);
let b = _mm_set_pd(2., 3.);
let r = _mm_maskz_shuffle_pd(0, a, b, 1 << 0 | 1 << 1);
assert_eq_m128d(r, _mm_setzero_pd());
let r = _mm_maskz_shuffle_pd(0b00000011, a, b, 1 << 0 | 1 << 1);
let e = _mm_set_pd(2., 1.);
assert_eq_m128d(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_shuffle_i64x2() {
let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
@ -7643,6 +7687,37 @@ mod tests {
assert_eq_m512i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_shuffle_i64x2() {
let a = _mm256_set_epi64x(1, 4, 5, 8);
let b = _mm256_set_epi64x(2, 3, 6, 7);
let r = _mm256_shuffle_i64x2(a, b, 0b00);
let e = _mm256_set_epi64x(6, 7, 5, 8);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_shuffle_i64x2() {
let a = _mm256_set_epi64x(1, 4, 5, 8);
let b = _mm256_set_epi64x(2, 3, 6, 7);
let r = _mm256_mask_shuffle_i64x2(a, 0, a, b, 0b00);
assert_eq_m256i(r, a);
let r = _mm256_mask_shuffle_i64x2(a, 0b00001111, a, b, 0b00);
let e = _mm256_set_epi64x(6, 7, 5, 8);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_maskz_shuffle_i64x2() {
let a = _mm256_set_epi64x(1, 4, 5, 8);
let b = _mm256_set_epi64x(2, 3, 6, 7);
let r = _mm256_maskz_shuffle_i64x2(0, a, b, 0b00);
assert_eq_m256i(r, _mm256_setzero_si256());
let r = _mm256_maskz_shuffle_i64x2(0b00001111, a, b, 0b00);
let e = _mm256_set_epi64x(6, 7, 5, 8);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_shuffle_f64x2() {
let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
@ -7674,6 +7749,37 @@ mod tests {
assert_eq_m512d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_shuffle_f64x2() {
let a = _mm256_set_pd(1., 4., 5., 8.);
let b = _mm256_set_pd(2., 3., 6., 7.);
let r = _mm256_shuffle_f64x2(a, b, 0b00);
let e = _mm256_set_pd(6., 7., 5., 8.);
assert_eq_m256d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_shuffle_f64x2() {
let a = _mm256_set_pd(1., 4., 5., 8.);
let b = _mm256_set_pd(2., 3., 6., 7.);
let r = _mm256_mask_shuffle_f64x2(a, 0, a, b, 0b00);
assert_eq_m256d(r, a);
let r = _mm256_mask_shuffle_f64x2(a, 0b00001111, a, b, 0b00);
let e = _mm256_set_pd(6., 7., 5., 8.);
assert_eq_m256d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_maskz_shuffle_f64x2() {
let a = _mm256_set_pd(1., 4., 5., 8.);
let b = _mm256_set_pd(2., 3., 6., 7.);
let r = _mm256_maskz_shuffle_f64x2(0, a, b, 0b00);
assert_eq_m256d(r, _mm256_setzero_pd());
let r = _mm256_maskz_shuffle_f64x2(0b00001111, a, b, 0b00);
let e = _mm256_set_pd(6., 7., 5., 8.);
assert_eq_m256d(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_movedup_pd() {
let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
@ -7969,9 +8075,51 @@ mod tests {
assert_eq_m512i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_broadcastq_epi64() {
let src = _mm256_set1_epi64x(18);
let a = _mm_set_epi64x(17, 18);
let r = _mm256_mask_broadcastq_epi64(src, 0, a);
assert_eq_m256i(r, src);
let r = _mm256_mask_broadcastq_epi64(src, 0b00001111, a);
let e = _mm256_set1_epi64x(18);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_maskz_broadcastq_epi64() {
let a = _mm_set_epi64x(17, 18);
let r = _mm256_maskz_broadcastq_epi64(0, a);
assert_eq_m256i(r, _mm256_setzero_si256());
let r = _mm256_maskz_broadcastq_epi64(0b00001111, a);
let e = _mm256_set1_epi64x(18);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_broadcastq_epi64() {
let src = _mm_set1_epi64x(18);
let a = _mm_set_epi64x(17, 18);
let r = _mm_mask_broadcastq_epi64(src, 0, a);
assert_eq_m128i(r, src);
let r = _mm_mask_broadcastq_epi64(src, 0b00000011, a);
let e = _mm_set1_epi64x(18);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_maskz_broadcastq_epi64() {
let a = _mm_set_epi64x(17, 18);
let r = _mm_maskz_broadcastq_epi64(0, a);
assert_eq_m128i(r, _mm_setzero_si128());
let r = _mm_maskz_broadcastq_epi64(0b00000011, a);
let e = _mm_set1_epi64x(18);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_broadcastsd_pd() {
let a = _mm_setr_pd(17., 18.);
let a = _mm_set_pd(17., 18.);
let r = _mm512_broadcastsd_pd(a);
let e = _mm512_set1_pd(18.);
assert_eq_m512d(r, e);
@ -7980,17 +8128,17 @@ mod tests {
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_mask_broadcastsd_pd() {
let src = _mm512_set1_pd(18.);
let a = _mm_setr_pd(17., 18.);
let a = _mm_set_pd(17., 18.);
let r = _mm512_mask_broadcastsd_pd(src, 0, a);
assert_eq_m512d(r, src);
let r = _mm512_mask_broadcastsd_pd(src, 0b01111111, a);
let r = _mm512_mask_broadcastsd_pd(src, 0b11111111, a);
let e = _mm512_set1_pd(18.);
assert_eq_m512d(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_maskz_broadcastsd_pd() {
let a = _mm_setr_pd(17., 18.);
let a = _mm_set_pd(17., 18.);
let r = _mm512_maskz_broadcastsd_pd(0, a);
assert_eq_m512d(r, _mm512_setzero_pd());
let r = _mm512_maskz_broadcastsd_pd(0b00001111, a);
@ -7998,6 +8146,27 @@ mod tests {
assert_eq_m512d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_broadcastsd_pd() {
let src = _mm256_set1_pd(18.);
let a = _mm_set_pd(17., 18.);
let r = _mm256_mask_broadcastsd_pd(src, 0, a);
assert_eq_m256d(r, src);
let r = _mm256_mask_broadcastsd_pd(src, 0b00001111, a);
let e = _mm256_set1_pd(18.);
assert_eq_m256d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_maskz_broadcastsd_pd() {
let a = _mm_set_pd(17., 18.);
let r = _mm256_maskz_broadcastsd_pd(0, a);
assert_eq_m256d(r, _mm256_setzero_pd());
let r = _mm256_maskz_broadcastsd_pd(0b00001111, a);
let e = _mm256_set1_pd(18.);
assert_eq_m256d(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_broadcast_i64x4() {
let a = _mm256_set_epi64x(17, 18, 19, 20);
@ -8065,6 +8234,24 @@ mod tests {
assert_eq_m512i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_blend_epi64() {
let a = _mm256_set1_epi64x(1);
let b = _mm256_set1_epi64x(2);
let r = _mm256_mask_blend_epi64(0b00001111, a, b);
let e = _mm256_set1_epi64x(2);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_blend_epi64() {
let a = _mm_set1_epi64x(1);
let b = _mm_set1_epi64x(2);
let r = _mm_mask_blend_epi64(0b00000011, a, b);
let e = _mm_set1_epi64x(2);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_mask_blend_pd() {
let a = _mm512_set1_pd(1.);
@ -8074,6 +8261,24 @@ mod tests {
assert_eq_m512d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_blend_pd() {
let a = _mm256_set1_pd(1.);
let b = _mm256_set1_pd(2.);
let r = _mm256_mask_blend_pd(0b00001111, a, b);
let e = _mm256_set1_pd(2.);
assert_eq_m256d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_blend_pd() {
let a = _mm_set1_pd(1.);
let b = _mm_set1_pd(2.);
let r = _mm_mask_blend_pd(0b00000011, a, b);
let e = _mm_set1_pd(2.);
assert_eq_m128d(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_unpackhi_epi64() {
let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@ -8105,6 +8310,50 @@ mod tests {
assert_eq_m512i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_unpackhi_epi64() {
let a = _mm256_set_epi64x(1, 2, 3, 4);
let b = _mm256_set_epi64x(17, 18, 19, 20);
let r = _mm256_mask_unpackhi_epi64(a, 0, a, b);
assert_eq_m256i(r, a);
let r = _mm256_mask_unpackhi_epi64(a, 0b00001111, a, b);
let e = _mm256_set_epi64x(17, 1, 19, 3);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_maskz_unpackhi_epi64() {
let a = _mm256_set_epi64x(1, 2, 3, 4);
let b = _mm256_set_epi64x(17, 18, 19, 20);
let r = _mm256_maskz_unpackhi_epi64(0, a, b);
assert_eq_m256i(r, _mm256_setzero_si256());
let r = _mm256_maskz_unpackhi_epi64(0b00001111, a, b);
let e = _mm256_set_epi64x(17, 1, 19, 3);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_unpackhi_epi64() {
let a = _mm_set_epi64x(1, 2);
let b = _mm_set_epi64x(17, 18);
let r = _mm_mask_unpackhi_epi64(a, 0, a, b);
assert_eq_m128i(r, a);
let r = _mm_mask_unpackhi_epi64(a, 0b00000011, a, b);
let e = _mm_set_epi64x(17, 1);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_maskz_unpackhi_epi64() {
let a = _mm_set_epi64x(1, 2);
let b = _mm_set_epi64x(17, 18);
let r = _mm_maskz_unpackhi_epi64(0, a, b);
assert_eq_m128i(r, _mm_setzero_si128());
let r = _mm_maskz_unpackhi_epi64(0b00000011, a, b);
let e = _mm_set_epi64x(17, 1);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_unpackhi_pd() {
let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
@ -8136,6 +8385,50 @@ mod tests {
assert_eq_m512d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_unpackhi_pd() {
let a = _mm256_set_pd(1., 2., 3., 4.);
let b = _mm256_set_pd(17., 18., 19., 20.);
let r = _mm256_mask_unpackhi_pd(a, 0, a, b);
assert_eq_m256d(r, a);
let r = _mm256_mask_unpackhi_pd(a, 0b00001111, a, b);
let e = _mm256_set_pd(17., 1., 19., 3.);
assert_eq_m256d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_maskz_unpackhi_pd() {
let a = _mm256_set_pd(1., 2., 3., 4.);
let b = _mm256_set_pd(17., 18., 19., 20.);
let r = _mm256_maskz_unpackhi_pd(0, a, b);
assert_eq_m256d(r, _mm256_setzero_pd());
let r = _mm256_maskz_unpackhi_pd(0b00001111, a, b);
let e = _mm256_set_pd(17., 1., 19., 3.);
assert_eq_m256d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_unpackhi_pd() {
let a = _mm_set_pd(1., 2.);
let b = _mm_set_pd(17., 18.);
let r = _mm_mask_unpackhi_pd(a, 0, a, b);
assert_eq_m128d(r, a);
let r = _mm_mask_unpackhi_pd(a, 0b00000011, a, b);
let e = _mm_set_pd(17., 1.);
assert_eq_m128d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_maskz_unpackhi_pd() {
let a = _mm_set_pd(1., 2.);
let b = _mm_set_pd(17., 18.);
let r = _mm_maskz_unpackhi_pd(0, a, b);
assert_eq_m128d(r, _mm_setzero_pd());
let r = _mm_maskz_unpackhi_pd(0b00000011, a, b);
let e = _mm_set_pd(17., 1.);
assert_eq_m128d(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_unpacklo_epi64() {
let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
@ -8167,6 +8460,50 @@ mod tests {
assert_eq_m512i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_unpacklo_epi64() {
let a = _mm256_set_epi64x(1, 2, 3, 4);
let b = _mm256_set_epi64x(17, 18, 19, 20);
let r = _mm256_mask_unpacklo_epi64(a, 0, a, b);
assert_eq_m256i(r, a);
let r = _mm256_mask_unpacklo_epi64(a, 0b00001111, a, b);
let e = _mm256_set_epi64x(18, 2, 20, 4);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_maskz_unpacklo_epi64() {
let a = _mm256_set_epi64x(1, 2, 3, 4);
let b = _mm256_set_epi64x(17, 18, 19, 20);
let r = _mm256_maskz_unpacklo_epi64(0, a, b);
assert_eq_m256i(r, _mm256_setzero_si256());
let r = _mm256_maskz_unpacklo_epi64(0b00001111, a, b);
let e = _mm256_set_epi64x(18, 2, 20, 4);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_unpacklo_epi64() {
let a = _mm_set_epi64x(1, 2);
let b = _mm_set_epi64x(17, 18);
let r = _mm_mask_unpacklo_epi64(a, 0, a, b);
assert_eq_m128i(r, a);
let r = _mm_mask_unpacklo_epi64(a, 0b00000011, a, b);
let e = _mm_set_epi64x(18, 2);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_maskz_unpacklo_epi64() {
let a = _mm_set_epi64x(1, 2);
let b = _mm_set_epi64x(17, 18);
let r = _mm_maskz_unpacklo_epi64(0, a, b);
assert_eq_m128i(r, _mm_setzero_si128());
let r = _mm_maskz_unpacklo_epi64(0b00000011, a, b);
let e = _mm_set_epi64x(18, 2);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_unpacklo_pd() {
let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
@ -8198,6 +8535,50 @@ mod tests {
assert_eq_m512d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_unpacklo_pd() {
let a = _mm256_set_pd(1., 2., 3., 4.);
let b = _mm256_set_pd(17., 18., 19., 20.);
let r = _mm256_mask_unpacklo_pd(a, 0, a, b);
assert_eq_m256d(r, a);
let r = _mm256_mask_unpacklo_pd(a, 0b00001111, a, b);
let e = _mm256_set_pd(18., 2., 20., 4.);
assert_eq_m256d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_maskz_unpacklo_pd() {
let a = _mm256_set_pd(1., 2., 3., 4.);
let b = _mm256_set_pd(17., 18., 19., 20.);
let r = _mm256_maskz_unpacklo_pd(0, a, b);
assert_eq_m256d(r, _mm256_setzero_pd());
let r = _mm256_maskz_unpacklo_pd(0b00001111, a, b);
let e = _mm256_set_pd(18., 2., 20., 4.);
assert_eq_m256d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_unpacklo_pd() {
let a = _mm_set_pd(1., 2.);
let b = _mm_set_pd(17., 18.);
let r = _mm_mask_unpacklo_pd(a, 0, a, b);
assert_eq_m128d(r, a);
let r = _mm_mask_unpacklo_pd(a, 0b00000011, a, b);
let e = _mm_set_pd(18., 2.);
assert_eq_m128d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_maskz_unpacklo_pd() {
let a = _mm_set_pd(1., 2.);
let b = _mm_set_pd(17., 18.);
let r = _mm_maskz_unpacklo_pd(0, a, b);
assert_eq_m128d(r, _mm_setzero_pd());
let r = _mm_maskz_unpacklo_pd(0b00000011, a, b);
let e = _mm_set_pd(18., 2.);
assert_eq_m128d(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_alignr_epi64() {
let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
@ -8233,6 +8614,71 @@ mod tests {
assert_eq_m512i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_alignr_epi64() {
let a = _mm256_set_epi64x(4, 3, 2, 1);
let b = _mm256_set_epi64x(8, 7, 6, 5);
let r = _mm256_alignr_epi64(a, b, 0);
let e = _mm256_set_epi64x(8, 7, 6, 5);
assert_eq_m256i(r, e);
let r = _mm256_alignr_epi64(a, b, 6);
let e = _mm256_set_epi64x(6, 5, 4, 3);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_alignr_epi64() {
let a = _mm256_set_epi64x(4, 3, 2, 1);
let b = _mm256_set_epi64x(8, 7, 6, 5);
let r = _mm256_mask_alignr_epi64(a, 0, a, b, 1);
assert_eq_m256i(r, a);
let r = _mm256_mask_alignr_epi64(a, 0b00001111, a, b, 0);
let e = _mm256_set_epi64x(8, 7, 6, 5);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_maskz_alignr_epi64() {
let a = _mm256_set_epi64x(4, 3, 2, 1);
let b = _mm256_set_epi64x(8, 7, 6, 5);
let r = _mm256_maskz_alignr_epi64(0, a, b, 1);
assert_eq_m256i(r, _mm256_setzero_si256());
let r = _mm256_maskz_alignr_epi64(0b00001111, a, b, 0);
let e = _mm256_set_epi64x(8, 7, 6, 5);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_alignr_epi64() {
let a = _mm_set_epi64x(2, 1);
let b = _mm_set_epi64x(4, 3);
let r = _mm_alignr_epi64(a, b, 0);
let e = _mm_set_epi64x(4, 3);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_alignr_epi64() {
let a = _mm_set_epi64x(2, 1);
let b = _mm_set_epi64x(4, 3);
let r = _mm_mask_alignr_epi64(a, 0, a, b, 1);
assert_eq_m128i(r, a);
let r = _mm_mask_alignr_epi64(a, 0b00000011, a, b, 0);
let e = _mm_set_epi64x(4, 3);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_maskz_alignr_epi64() {
let a = _mm_set_epi64x(2, 1);
let b = _mm_set_epi64x(4, 3);
let r = _mm_maskz_alignr_epi64(0, a, b, 1);
assert_eq_m128i(r, _mm_setzero_si128());
let r = _mm_maskz_alignr_epi64(0b00000011, a, b, 0);
let e = _mm_set_epi64x(4, 3);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_and_epi64() {
let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);