From 13bd2979fc8798b6a5c27f15c68e89b08b9819ae Mon Sep 17 00:00:00 2001
From: Luca Barbato <lu_zero@gentoo.org>
Date: Wed, 21 Feb 2024 21:12:00 +0000
Subject: [PATCH] Add vec_sel

---
 .../crates/core_arch/src/powerpc/altivec.rs   | 120 ++++++++++++++++++
 1 file changed, 120 insertions(+)

diff --git a/library/stdarch/crates/core_arch/src/powerpc/altivec.rs b/library/stdarch/crates/core_arch/src/powerpc/altivec.rs
index 6497d01a34c7..547cac4058fb 100644
--- a/library/stdarch/crates/core_arch/src/powerpc/altivec.rs
+++ b/library/stdarch/crates/core_arch/src/powerpc/altivec.rs
@@ -478,6 +478,15 @@ macro_rules! t_t_s {
 }
 
 macro_rules! t_u {
+    (vector_bool_char) => {
+        vector_unsigned_char
+    };
+    (vector_bool_short) => {
+        vector_unsigned_short
+    };
+    (vector_bool_int) => {
+        vector_unsigned_int
+    };
     (vector_unsigned_char) => {
         vector_unsigned_char
     };
@@ -496,6 +505,42 @@ macro_rules! t_u {
     (vector_signed_int) => {
         vector_unsigned_int
     };
+    (vector_float) => {
+        vector_unsigned_int
+    };
+}
+
+macro_rules! t_b {
+    (vector_bool_char) => {
+        vector_bool_char
+    };
+    (vector_bool_short) => {
+        vector_bool_short
+    };
+    (vector_bool_int) => {
+        vector_bool_int
+    };
+    (vector_signed_char) => {
+        vector_bool_char
+    };
+    (vector_signed_short) => {
+        vector_bool_short
+    };
+    (vector_signed_int) => {
+        vector_bool_int
+    };
+    (vector_unsigned_char) => {
+        vector_bool_char
+    };
+    (vector_unsigned_short) => {
+        vector_bool_short
+    };
+    (vector_unsigned_int) => {
+        vector_bool_int
+    };
+    (vector_float) => {
+        vector_bool_int
+    };
 }
 
 macro_rules! impl_from {
@@ -2572,6 +2617,62 @@ mod sealed {
 
     impl_vec_trait! { [VectorNand vec_nand]+ 2b (vec_vnandsb, vec_vnandsh, vec_vnandsw) }
 
+    #[inline]
+    #[target_feature(enable = "altivec")]
+    #[cfg_attr(all(test, not(target_feature = "vsx")), assert_instr(vsel))]
+    #[cfg_attr(all(test, target_feature = "vsx"), assert_instr(xxsel))]
+    pub unsafe fn vec_vsel(
+        a: vector_signed_char,
+        b: vector_signed_char,
+        c: vector_signed_char,
+    ) -> vector_signed_char {
+        let a: i8x16 = transmute(a);
+        let b: i8x16 = transmute(b);
+        let c: i8x16 = transmute(c);
+        let not_c = simd_xor(c, i8x16::splat(!0));
+
+        transmute(simd_or(simd_and(a, not_c), simd_and(b, c)))
+    }
+
+    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
+    pub trait VectorSel<Mask> {
+        unsafe fn vec_sel(self, b: Self, c: Mask) -> Self;
+    }
+
+    macro_rules! vector_sel {
+        ($ty: ty, $m: ty) => {
+            #[unstable(feature = "stdarch_powerpc", issue = "111145")]
+            impl VectorSel<$m> for $ty {
+                #[inline]
+                #[target_feature(enable = "altivec")]
+                unsafe fn vec_sel(self, b: Self, c: $m) -> Self {
+                    let a = transmute(self);
+                    let b = transmute(b);
+                    let c = transmute(c);
+
+                    transmute(vec_vsel(a, b, c))
+                }
+            }
+        };
+        ($ty: ident) => {
+            vector_sel! { $ty, t_b!{ $ty } }
+            vector_sel! { $ty, t_u!{ $ty } }
+            vector_sel! { t_u!{ $ty }, t_b!{ $ty } }
+            vector_sel! { t_u!{ $ty }, t_u!{ $ty } }
+            vector_sel! { t_b!{ $ty }, t_b!{ $ty } }
+            vector_sel! { t_b!{ $ty }, t_u!{ $ty } }
+        };
+        (- $ty: ident) => {
+            vector_sel! { $ty, t_b!{ $ty } }
+            vector_sel! { $ty, t_u!{ $ty } }
+        };
+    }
+
+    vector_sel! { vector_signed_char }
+    vector_sel! { vector_signed_short }
+    vector_sel! { vector_signed_int }
+    vector_sel! {- vector_float }
+
     #[inline]
     #[target_feature(enable = "altivec")]
     #[cfg_attr(test, assert_instr(vcfsx, IMM5 = 1))]
@@ -4188,6 +4289,25 @@ pub unsafe fn vec_nmsub(a: vector_float, b: vector_float, c: vector_float) -> ve
     vnmsubfp(a, b, c)
 }
 
+/// Vector Select
+///
+/// ## Purpose
+/// Returns a vector selecting bits from two source vectors depending on the corresponding
+/// bit values of a third source vector.
+///
+/// ## Result value
+/// Each bit of r has the value of the corresponding bit of a if the corresponding
+/// bit of c is 0. Otherwise, the bit of r has the value of the corresponding bit of b.
+#[inline]
+#[target_feature(enable = "altivec")]
+#[unstable(feature = "stdarch_powerpc", issue = "111145")]
+pub unsafe fn vec_sel<T, U>(a: T, b: T, c: U) -> T
+where
+    T: sealed::VectorSel<U>,
+{
+    a.vec_sel(b, c)
+}
+
 /// Vector Sum Across Partial (1/4) Saturated
 #[inline]
 #[target_feature(enable = "altivec")]