From 1ccc7dbd0d27f13bbe3618bd97752e3df7d6b8fe Mon Sep 17 00:00:00 2001
From: sayantn <sayantan.chakraborty@students.iiserpune.ac.in>
Date: Sat, 8 Jun 2024 14:21:17 +0530
Subject: [PATCH] Fixed `_mm256_cvtsd_f64`

This intrinsic should have `target_feature` AVX, (according to Intel Intrinsics Guide) but had AVX2
---
 .../stdarch/crates/core_arch/src/x86/avx.rs   | 20 ++++++++++++++++++-
 .../stdarch/crates/core_arch/src/x86/avx2.rs  | 18 -----------------
 2 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/library/stdarch/crates/core_arch/src/x86/avx.rs b/library/stdarch/crates/core_arch/src/x86/avx.rs
index cd2ca2c9cfef..018786ee9f43 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx.rs
@@ -889,6 +889,17 @@ pub unsafe fn _mm256_cvtps_pd(a: __m128) -> __m256d {
     simd_cast(a)
 }
 
+/// Returns the first element of the input vector of `[4 x double]`.
+///
+/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtsd_f64)
+#[inline]
+#[target_feature(enable = "avx")]
+#[cfg_attr(test, assert_instr(vmovsd))]
+#[stable(feature = "simd_x86", since = "1.27.0")]
+pub unsafe fn _mm256_cvtsd_f64(a: __m256d) -> f64 {
+    simd_extract!(a, 0)
+}
+
 /// Converts packed double-precision (64-bit) floating-point elements in `a`
 /// to packed 32-bit integers with truncation.
 ///
@@ -2937,7 +2948,7 @@ pub unsafe fn _mm256_storeu2_m128i(hiaddr: *mut __m128i, loaddr: *mut __m128i, a
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtss_f32)
 #[inline]
 #[target_feature(enable = "avx")]
-//#[cfg_attr(test, assert_instr(movss))] FIXME
+#[cfg_attr(test, assert_instr(vmovss))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub unsafe fn _mm256_cvtss_f32(a: __m256) -> f32 {
     simd_extract!(a, 0)
@@ -3640,6 +3651,13 @@ mod tests {
         assert_eq_m256d(r, e);
     }
 
+    #[simd_test(enable = "avx")]
+    unsafe fn test_mm256_cvtsd_f64() {
+        let a = _mm256_setr_pd(1., 2., 3., 4.);
+        let r = _mm256_cvtsd_f64(a);
+        assert_eq!(r, 1.);
+    }
+
     #[simd_test(enable = "avx")]
     unsafe fn test_mm256_cvttpd_epi32() {
         let a = _mm256_setr_pd(4., 9., 16., 25.);
diff --git a/library/stdarch/crates/core_arch/src/x86/avx2.rs b/library/stdarch/crates/core_arch/src/x86/avx2.rs
index 59c85d1e84a3..68a2f34a57a3 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx2.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx2.rs
@@ -3625,17 +3625,6 @@ pub unsafe fn _mm256_extract_epi32<const INDEX: i32>(a: __m256i) -> i32 {
     simd_extract!(a.as_i32x8(), INDEX as u32)
 }
 
-/// Returns the first element of the input vector of `[4 x double]`.
-///
-/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtsd_f64)
-#[inline]
-#[target_feature(enable = "avx2")]
-//#[cfg_attr(test, assert_instr(movsd))] FIXME
-#[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_cvtsd_f64(a: __m256d) -> f64 {
-    simd_extract!(a, 0)
-}
-
 /// Returns the first element of the input vector of `[8 x i32]`.
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtsi256_si32)
@@ -5776,13 +5765,6 @@ mod tests {
         assert_eq!(r2, 3);
     }
 
-    #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_cvtsd_f64() {
-        let a = _mm256_setr_pd(1., 2., 3., 4.);
-        let r = _mm256_cvtsd_f64(a);
-        assert_eq!(r, 1.);
-    }
-
     #[simd_test(enable = "avx2")]
     unsafe fn test_mm256_cvtsi256_si32() {
         let a = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);