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Rollup merge of #143769 - tmiasko:rm-backward-switch-int, r=lqd

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Remove support for SwitchInt edge effects in backward dataflow

Those effects are untested and unused. Remove them along with the implementation of `BasicBlocks::switch_sources`.
This commit is contained in:
Matthias Krüger 2025-07-11 19:45:26 +02:00 • committed by GitHub
commit 1d2aa4d8dd
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GPG key ID: B5690EEEBB952194
2 changed files with 7 additions and 48 deletions
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40
compiler/rustc_middle/src/mir/basic_blocks.rs
View file

@ -1,6 +1,5 @@
use std::sync::OnceLock;
use rustc_data_structures::fx::FxHashMap;
use rustc_data_structures::graph;
use rustc_data_structures::graph::dominators::{Dominators, dominators};
use rustc_data_structures::stable_hasher::{HashStable, StableHasher};
@ -10,7 +9,7 @@ use rustc_serialize::{Decodable, Decoder, Encodable, Encoder};
use smallvec::SmallVec;
use crate::mir::traversal::Postorder;
use crate::mir::{BasicBlock, BasicBlockData, START_BLOCK, Terminator, TerminatorKind};
use crate::mir::{BasicBlock, BasicBlockData, START_BLOCK};
#[derive(Clone, TyEncodable, TyDecodable, Debug, HashStable, TypeFoldable, TypeVisitable)]
pub struct BasicBlocks<'tcx> {
@ -21,15 +20,6 @@ pub struct BasicBlocks<'tcx> {
// Typically 95%+ of basic blocks have 4 or fewer predecessors.
type Predecessors = IndexVec<BasicBlock, SmallVec<[BasicBlock; 4]>>;
/// Each `(target, switch)` entry in the map contains a list of switch values
/// that lead to a `target` block from a `switch` block.
///
/// Note: this type is currently never instantiated, because it's only used for
/// `BasicBlocks::switch_sources`, which is only called by backwards analyses
/// that do `SwitchInt` handling, and we don't have any of those, not even in
/// tests. See #95120 and #94576.
type SwitchSources = FxHashMap<(BasicBlock, BasicBlock), SmallVec<[SwitchTargetValue; 1]>>;
#[derive(Debug, Clone, Copy)]
pub enum SwitchTargetValue {
// A normal switch value.
@ -41,7 +31,6 @@ pub enum SwitchTargetValue {
#[derive(Clone, Default, Debug)]
struct Cache {
predecessors: OnceLock<Predecessors>,
switch_sources: OnceLock<SwitchSources>,
reverse_postorder: OnceLock<Vec<BasicBlock>>,
dominators: OnceLock<Dominators<BasicBlock>>,
}
@ -86,33 +75,6 @@ impl<'tcx> BasicBlocks<'tcx> {
})
}
/// Returns info about switch values that lead from one block to another
/// block. See `SwitchSources`.
#[inline]
pub fn switch_sources(&self) -> &SwitchSources {
self.cache.switch_sources.get_or_init(|| {
let mut switch_sources: SwitchSources = FxHashMap::default();
for (bb, data) in self.basic_blocks.iter_enumerated() {
if let Some(Terminator {
kind: TerminatorKind::SwitchInt { targets, .. }, ..
}) = &data.terminator
{
for (value, target) in targets.iter() {
switch_sources
.entry((target, bb))
.or_default()
.push(SwitchTargetValue::Normal(value));
}
switch_sources
.entry((targets.otherwise(), bb))
.or_default()
.push(SwitchTargetValue::Otherwise);
}
}
switch_sources
})
}
/// Returns mutable reference to basic blocks. Invalidates CFG cache.
#[inline]
pub fn as_mut(&mut self) -> &mut IndexVec<BasicBlock, BasicBlockData<'tcx>> {

15
compiler/rustc_mir_dataflow/src/framework/direction.rs
View file

@ -1,5 +1,6 @@
use std::ops::RangeInclusive;
use rustc_middle::bug;
use rustc_middle::mir::{
self, BasicBlock, CallReturnPlaces, Location, SwitchTargetValue, TerminatorEdges,
};
@ -112,15 +113,11 @@ impl Direction for Backward {
propagate(pred, &tmp);
}
mir::TerminatorKind::SwitchInt { ref targets, ref discr } => {
if let Some(mut data) = analysis.get_switch_int_data(block, discr) {
let mut tmp = analysis.bottom_value(body);
for &value in &body.basic_blocks.switch_sources()[&(block, pred)] {
tmp.clone_from(exit_state);
analysis
.apply_switch_int_edge_effect(&mut data, &mut tmp, value, targets);
propagate(pred, &tmp);
}
mir::TerminatorKind::SwitchInt { ref discr, .. } => {
if let Some(_data) = analysis.get_switch_int_data(pred, discr) {
bug!(
"SwitchInt edge effects are unsupported in backward dataflow analyses"
);
} else {
propagate(pred, exit_state)
}