From 22c691f703e303129d453a6c94f01026040438d7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Sat, 6 Mar 2021 00:48:54 +0100 Subject: [PATCH] convert `_mm256_mask_i32gather_ps` to const generics --- .../stdarch/crates/core_arch/src/x86/avx2.rs | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/library/stdarch/crates/core_arch/src/x86/avx2.rs b/library/stdarch/crates/core_arch/src/x86/avx2.rs index 9bd559180eb4..c39774c0c41c 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx2.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx2.rs @@ -1245,24 +1245,19 @@ pub unsafe fn _mm256_i32gather_ps(slice: *const f32, offsets: /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_i32gather_ps) #[inline] #[target_feature(enable = "avx2")] -#[cfg_attr(test, assert_instr(vgatherdps, scale = 1))] -#[rustc_args_required_const(4)] +#[cfg_attr(test, assert_instr(vgatherdps, SCALE = 1))] +#[rustc_legacy_const_generics(4)] #[stable(feature = "simd_x86", since = "1.27.0")] -pub unsafe fn _mm256_mask_i32gather_ps( +pub unsafe fn _mm256_mask_i32gather_ps( src: __m256, slice: *const f32, offsets: __m256i, mask: __m256, - scale: i32, ) -> __m256 { + static_assert_imm8_scale!(SCALE); let offsets = offsets.as_i32x8(); let slice = slice as *const i8; - macro_rules! call { - ($imm8:expr) => { - vpgatherdps(src, slice, offsets, mask, $imm8) - }; - } - constify_imm8_gather!(scale, call) + vpgatherdps(src, slice, offsets, mask, SCALE as i8) } /// Returns values from `slice` at offsets determined by `offsets * scale`, @@ -5650,12 +5645,11 @@ mod tests { j += 1.0; } // A multiplier of 4 is word-addressing for f32s - let r = _mm256_mask_i32gather_ps( + let r = _mm256_mask_i32gather_ps::<4>( _mm256_set1_ps(256.0), arr.as_ptr(), _mm256_setr_epi32(0, 16, 64, 96, 0, 0, 0, 0), _mm256_setr_ps(-1.0, -1.0, -1.0, 0.0, 0.0, 0.0, 0.0, 0.0), - 4, ); assert_eq_m256( r,