From 2aedbf0993737939fdff3eb9ded7c8630144f1bc Mon Sep 17 00:00:00 2001
From: Corey Farwell <coreyf@rwell.org>
Date: Fri, 22 Jan 2021 09:16:27 -0500
Subject: [PATCH] Add shim for libc::sysconf(libc::_SC_NPROCESSORS_CONF)

---
 src/shims/posix/foreign_items.rs | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/shims/posix/foreign_items.rs b/src/shims/posix/foreign_items.rs
index aac164b709b2..f92242f56d9e 100644
--- a/src/shims/posix/foreign_items.rs
+++ b/src/shims/posix/foreign_items.rs
@@ -180,6 +180,7 @@ pub trait EvalContextExt<'mir, 'tcx: 'mir>: crate::MiriEvalContextExt<'mir, 'tcx
 
                 let sysconfs = &[
                     ("_SC_PAGESIZE", Scalar::from_int(PAGE_SIZE, this.pointer_size())),
+                    ("_SC_NPROCESSORS_CONF", Scalar::from_int(NUM_CPUS, this.pointer_size())),
                     ("_SC_NPROCESSORS_ONLN", Scalar::from_int(NUM_CPUS, this.pointer_size())),
                 ];
                 let mut result = None;