mips: Convert *const(2) to const generics
This commit is contained in:
Lzu Tao
Amanieu d'Antras
parent
5c1f6cb035
commit
2b08a71689
1 changed files with 79 additions and 152 deletions
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@ -2024,14 +2024,10 @@ pub unsafe fn __msa_binsl_d(a: v2u64, b: v2u64, c: v2u64) -> v2u64 {
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#[inline]
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#[target_feature(enable = "msa")]
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#[cfg_attr(test, assert_instr(binsli.b, imm3 = 0b111))]
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#[rustc_args_required_const(2)]
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pub unsafe fn __msa_binsli_b(a: v16u8, b: v16u8, imm3: i32) -> v16u8 {
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macro_rules! call {
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($imm3:expr) => {
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msa_binsli_b(a, mem::transmute(b), $imm3)
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};
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}
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constify_imm3!(imm3, call)
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn __msa_binsli_b<const IMM3: i32>(a: v16u8, b: v16u8) -> v16u8 {
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static_assert_imm3!(IMM3);
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msa_binsli_b(a, mem::transmute(b), IMM3)
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}
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/// Immediate Bit Insert Left
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@ -2043,14 +2039,10 @@ pub unsafe fn __msa_binsli_b(a: v16u8, b: v16u8, imm3: i32) -> v16u8 {
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#[inline]
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#[target_feature(enable = "msa")]
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#[cfg_attr(test, assert_instr(binsli.h, imm4 = 0b1111))]
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#[rustc_args_required_const(2)]
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pub unsafe fn __msa_binsli_h(a: v8u16, b: v8u16, imm4: i32) -> v8u16 {
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macro_rules! call {
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($imm4:expr) => {
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msa_binsli_h(a, mem::transmute(b), $imm4)
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};
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}
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constify_imm4!(imm4, call)
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn __msa_binsli_h<const IMM4: i32>(a: v8u16, b: v8u16) -> v8u16 {
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static_assert_imm4!(IMM4);
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msa_binsli_h(a, mem::transmute(b), IMM4)
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}
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/// Immediate Bit Insert Left
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@ -2062,14 +2054,10 @@ pub unsafe fn __msa_binsli_h(a: v8u16, b: v8u16, imm4: i32) -> v8u16 {
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#[inline]
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#[target_feature(enable = "msa")]
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#[cfg_attr(test, assert_instr(binsli.w, imm5 = 0b11111))]
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#[rustc_args_required_const(2)]
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pub unsafe fn __msa_binsli_w(a: v4u32, b: v4u32, imm5: i32) -> v4u32 {
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macro_rules! call {
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($imm5:expr) => {
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msa_binsli_w(a, mem::transmute(b), $imm5)
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};
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}
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constify_imm5!(imm5, call)
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn __msa_binsli_w<const IMM5: i32>(a: v4u32, b: v4u32) -> v4u32 {
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static_assert_imm5!(IMM5);
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msa_binsli_w(a, mem::transmute(b), IMM5)
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}
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/// Immediate Bit Insert Left
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@ -2081,14 +2069,10 @@ pub unsafe fn __msa_binsli_w(a: v4u32, b: v4u32, imm5: i32) -> v4u32 {
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#[inline]
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#[target_feature(enable = "msa")]
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#[cfg_attr(test, assert_instr(binsli.d, imm6 = 0b111111))]
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#[rustc_args_required_const(2)]
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pub unsafe fn __msa_binsli_d(a: v2u64, b: v2u64, imm6: i32) -> v2u64 {
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macro_rules! call {
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($imm6:expr) => {
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msa_binsli_d(a, mem::transmute(b), $imm6)
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};
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}
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constify_imm6!(imm6, call)
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn __msa_binsli_d<const IMM6: i32>(a: v2u64, b: v2u64) -> v2u64 {
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static_assert_imm6!(IMM6);
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msa_binsli_d(a, mem::transmute(b), IMM6)
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}
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/// Vector Bit Insert Right
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@ -2156,14 +2140,10 @@ pub unsafe fn __msa_binsr_d(a: v2u64, b: v2u64, c: v2u64) -> v2u64 {
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#[inline]
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#[target_feature(enable = "msa")]
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#[cfg_attr(test, assert_instr(binsri.b, imm3 = 0b111))]
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#[rustc_args_required_const(2)]
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pub unsafe fn __msa_binsri_b(a: v16u8, b: v16u8, imm3: i32) -> v16u8 {
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macro_rules! call {
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($imm3:expr) => {
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msa_binsri_b(a, mem::transmute(b), $imm3)
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};
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}
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constify_imm3!(imm3, call)
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn __msa_binsri_b<const IMM3: i32>(a: v16u8, b: v16u8) -> v16u8 {
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static_assert_imm3!(IMM3);
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msa_binsri_b(a, mem::transmute(b), IMM3)
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}
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/// Immediate Bit Insert Right
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@ -2175,14 +2155,10 @@ pub unsafe fn __msa_binsri_b(a: v16u8, b: v16u8, imm3: i32) -> v16u8 {
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#[inline]
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#[target_feature(enable = "msa")]
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#[cfg_attr(test, assert_instr(binsri.h, imm4 = 0b1111))]
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#[rustc_args_required_const(2)]
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pub unsafe fn __msa_binsri_h(a: v8u16, b: v8u16, imm4: i32) -> v8u16 {
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macro_rules! call {
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($imm4:expr) => {
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msa_binsri_h(a, mem::transmute(b), $imm4)
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};
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}
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constify_imm4!(imm4, call)
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn __msa_binsri_h<const IMM4: i32>(a: v8u16, b: v8u16) -> v8u16 {
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static_assert_imm4!(IMM4);
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msa_binsri_h(a, mem::transmute(b), IMM4)
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}
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/// Immediate Bit Insert Right
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@ -2194,14 +2170,10 @@ pub unsafe fn __msa_binsri_h(a: v8u16, b: v8u16, imm4: i32) -> v8u16 {
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#[inline]
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#[target_feature(enable = "msa")]
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#[cfg_attr(test, assert_instr(binsri.w, imm5 = 0b11111))]
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#[rustc_args_required_const(2)]
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pub unsafe fn __msa_binsri_w(a: v4u32, b: v4u32, imm5: i32) -> v4u32 {
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macro_rules! call {
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($imm5:expr) => {
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msa_binsri_w(a, mem::transmute(b), $imm5)
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};
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}
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constify_imm5!(imm5, call)
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn __msa_binsri_w<const IMM5: i32>(a: v4u32, b: v4u32) -> v4u32 {
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static_assert_imm5!(IMM5);
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msa_binsri_w(a, mem::transmute(b), IMM5)
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}
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/// Immediate Bit Insert Right
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@ -2213,14 +2185,10 @@ pub unsafe fn __msa_binsri_w(a: v4u32, b: v4u32, imm5: i32) -> v4u32 {
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#[inline]
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#[target_feature(enable = "msa")]
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#[cfg_attr(test, assert_instr(binsri.d, imm6 = 0b111111))]
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#[rustc_args_required_const(2)]
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pub unsafe fn __msa_binsri_d(a: v2u64, b: v2u64, imm6: i32) -> v2u64 {
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macro_rules! call {
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($imm6:expr) => {
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msa_binsri_d(a, mem::transmute(b), $imm6)
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};
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}
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constify_imm6!(imm6, call)
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn __msa_binsri_d<const IMM6: i32>(a: v2u64, b: v2u64) -> v2u64 {
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static_assert_imm6!(IMM6);
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msa_binsri_d(a, mem::transmute(b), IMM6)
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}
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/// Vector Bit Move If Not Zero
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@ -2246,14 +2214,10 @@ pub unsafe fn __msa_bmnz_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 {
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#[inline]
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#[target_feature(enable = "msa")]
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#[cfg_attr(test, assert_instr(bmnzi.b, imm8 = 0b11111111))]
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#[rustc_args_required_const(2)]
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pub unsafe fn __msa_bmnzi_b(a: v16u8, b: v16u8, imm8: i32) -> v16u8 {
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macro_rules! call {
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($imm8:expr) => {
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msa_bmnzi_b(a, mem::transmute(b), $imm8)
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};
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}
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constify_imm8!(imm8, call)
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn __msa_bmnzi_b<const IMM8: i32>(a: v16u8, b: v16u8) -> v16u8 {
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static_assert_imm8!(IMM8);
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msa_bmnzi_b(a, mem::transmute(b), IMM8)
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}
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/// Vector Bit Move If Zero
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@ -2279,14 +2243,10 @@ pub unsafe fn __msa_bmz_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 {
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#[inline]
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#[target_feature(enable = "msa")]
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#[cfg_attr(test, assert_instr(bmzi.b, imm8 = 0b11111111))]
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#[rustc_args_required_const(2)]
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pub unsafe fn __msa_bmzi_b(a: v16u8, b: v16u8, imm8: i32) -> v16u8 {
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macro_rules! call {
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($imm8:expr) => {
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msa_bmzi_b(a, mem::transmute(b), $imm8)
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};
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}
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constify_imm8!(imm8, call)
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn __msa_bmzi_b<const IMM8: i32>(a: v16u8, b: v16u8) -> v16u8 {
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static_assert_imm8!(IMM8);
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msa_bmzi_b(a, mem::transmute(b), IMM8)
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}
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/// Vector Bit Negate
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@ -2484,14 +2444,10 @@ pub unsafe fn __msa_bsel_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 {
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#[inline]
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#[target_feature(enable = "msa")]
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#[cfg_attr(test, assert_instr(bseli.b, imm8 = 0b11111111))]
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#[rustc_args_required_const(2)]
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pub unsafe fn __msa_bseli_b(a: v16u8, b: v16u8, imm8: i32) -> v16u8 {
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macro_rules! call {
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($imm8:expr) => {
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msa_bseli_b(a, mem::transmute(b), $imm8)
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};
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}
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constify_imm8!(imm8, call)
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn __msa_bseli_b<const IMM8: i32>(a: v16u8, b: v16u8) -> v16u8 {
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static_assert_imm8!(IMM8);
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msa_bseli_b(a, mem::transmute(b), IMM8)
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}
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/// Vector Bit Set
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@ -7450,14 +7406,10 @@ pub unsafe fn __msa_sld_d(a: v2i64, b: v2i64, c: i32) -> v2i64 {
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#[inline]
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#[target_feature(enable = "msa")]
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#[cfg_attr(test, assert_instr(sldi.b, imm4 = 0b1111))]
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#[rustc_args_required_const(2)]
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pub unsafe fn __msa_sldi_b(a: v16i8, b: v16i8, imm4: i32) -> v16i8 {
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macro_rules! call {
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($imm4:expr) => {
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msa_sldi_b(a, mem::transmute(b), $imm4)
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};
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}
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constify_imm4!(imm4, call)
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn __msa_sldi_b<const IMM4: i32>(a: v16i8, b: v16i8) -> v16i8 {
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static_assert_imm4!(IMM4);
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msa_sldi_b(a, mem::transmute(b), IMM4)
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}
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/// Immediate Columns Slide
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@ -7474,14 +7426,10 @@ pub unsafe fn __msa_sldi_b(a: v16i8, b: v16i8, imm4: i32) -> v16i8 {
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#[inline]
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#[target_feature(enable = "msa")]
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#[cfg_attr(test, assert_instr(sldi.h, imm3 = 0b111))]
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#[rustc_args_required_const(2)]
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pub unsafe fn __msa_sldi_h(a: v8i16, b: v8i16, imm3: i32) -> v8i16 {
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macro_rules! call {
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($imm3:expr) => {
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msa_sldi_h(a, mem::transmute(b), $imm3)
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};
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}
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constify_imm3!(imm3, call)
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn __msa_sldi_h<const IMM3: i32>(a: v8i16, b: v8i16) -> v8i16 {
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static_assert_imm3!(IMM3);
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msa_sldi_h(a, mem::transmute(b), IMM3)
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}
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/// Immediate Columns Slide
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@ -7498,14 +7446,10 @@ pub unsafe fn __msa_sldi_h(a: v8i16, b: v8i16, imm3: i32) -> v8i16 {
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#[inline]
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#[target_feature(enable = "msa")]
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#[cfg_attr(test, assert_instr(sldi.w, imm2 = 0b11))]
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#[rustc_args_required_const(2)]
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pub unsafe fn __msa_sldi_w(a: v4i32, b: v4i32, imm2: i32) -> v4i32 {
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macro_rules! call {
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($imm2:expr) => {
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msa_sldi_w(a, mem::transmute(b), $imm2)
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};
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}
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constify_imm2!(imm2, call)
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn __msa_sldi_w<const IMM2: i32>(a: v4i32, b: v4i32) -> v4i32 {
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static_assert_imm2!(IMM2);
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msa_sldi_w(a, mem::transmute(b), IMM2)
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}
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/// Immediate Columns Slide
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@ -7522,14 +7466,10 @@ pub unsafe fn __msa_sldi_w(a: v4i32, b: v4i32, imm2: i32) -> v4i32 {
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#[inline]
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#[target_feature(enable = "msa")]
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#[cfg_attr(test, assert_instr(sldi.d, imm1 = 0b1))]
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#[rustc_args_required_const(2)]
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pub unsafe fn __msa_sldi_d(a: v2i64, b: v2i64, imm1: i32) -> v2i64 {
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macro_rules! call {
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($imm1:expr) => {
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msa_sldi_d(a, mem::transmute(b), $imm1)
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};
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}
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constify_imm1!(imm1, call)
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn __msa_sldi_d<const IMM1: i32>(a: v2i64, b: v2i64) -> v2i64 {
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static_assert_imm1!(IMM1);
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msa_sldi_d(a, mem::transmute(b), IMM1)
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}
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/// Vector Shift Left
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@ -8249,14 +8189,10 @@ pub unsafe fn __msa_srlri_d<const IMM6: i32>(a: v2i64) -> v2i64 {
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#[inline]
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#[target_feature(enable = "msa")]
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#[cfg_attr(test, assert_instr(st.b, imm_s10 = 0b1111111111))]
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#[rustc_args_required_const(2)]
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pub unsafe fn __msa_st_b(a: v16i8, mem_addr: *mut u8, imm_s10: i32) -> () {
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macro_rules! call {
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($imm_s10:expr) => {
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msa_st_b(a, mem_addr, $imm_s10)
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};
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}
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constify_imm_s10!(imm_s10, call)
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn __msa_st_b<const IMM_S10: i32>(a: v16i8, mem_addr: *mut u8) -> () {
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static_assert_imm_s10!(IMM_S10);
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msa_st_b(a, mem_addr, IMM_S10)
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}
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/// Vector Store
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@ -8268,14 +8204,11 @@ pub unsafe fn __msa_st_b(a: v16i8, mem_addr: *mut u8, imm_s10: i32) -> () {
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#[inline]
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#[target_feature(enable = "msa")]
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#[cfg_attr(test, assert_instr(st.h, imm_s11 = 0b11111111111))]
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#[rustc_args_required_const(2)]
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pub unsafe fn __msa_st_h(a: v8i16, mem_addr: *mut u8, imm_s11: i32) -> () {
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macro_rules! call {
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($imm_s11:expr) => {
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msa_st_h(a, mem_addr, $imm_s11)
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};
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}
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constify_imm_s11!(imm_s11, call)
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn __msa_st_h<const IMM_S11: i32>(a: v8i16, mem_addr: *mut u8) -> () {
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static_assert_imm_s11!(IMM_S11);
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static_assert!(IMM_S11: i32 where IMM_S11 % 2 == 0);
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msa_st_h(a, mem_addr, IMM_S11)
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}
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/// Vector Store
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@ -8287,14 +8220,11 @@ pub unsafe fn __msa_st_h(a: v8i16, mem_addr: *mut u8, imm_s11: i32) -> () {
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#[inline]
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#[target_feature(enable = "msa")]
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#[cfg_attr(test, assert_instr(st.w, imm_s12 = 0b111111111111))]
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#[rustc_args_required_const(2)]
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pub unsafe fn __msa_st_w(a: v4i32, mem_addr: *mut u8, imm_s12: i32) -> () {
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macro_rules! call {
|
||||
($imm_s12:expr) => {
|
||||
msa_st_w(a, mem_addr, $imm_s12)
|
||||
};
|
||||
}
|
||||
constify_imm_s12!(imm_s12, call)
|
||||
#[rustc_legacy_const_generics(2)]
|
||||
pub unsafe fn __msa_st_w<const IMM_S12: i32>(a: v4i32, mem_addr: *mut u8) -> () {
|
||||
static_assert_imm_s12!(IMM_S12);
|
||||
static_assert!(IMM_S12: i32 where IMM_S12 % 4 == 0);
|
||||
msa_st_w(a, mem_addr, IMM_S12)
|
||||
}
|
||||
|
||||
/// Vector Store
|
||||
|
|
@ -8306,14 +8236,11 @@ pub unsafe fn __msa_st_w(a: v4i32, mem_addr: *mut u8, imm_s12: i32) -> () {
|
|||
#[inline]
|
||||
#[target_feature(enable = "msa")]
|
||||
#[cfg_attr(test, assert_instr(st.d, imm_s13 = 0b1111111111111))]
|
||||
#[rustc_args_required_const(2)]
|
||||
pub unsafe fn __msa_st_d(a: v2i64, mem_addr: *mut u8, imm_s13: i32) -> () {
|
||||
macro_rules! call {
|
||||
($imm_s13:expr) => {
|
||||
msa_st_d(a, mem_addr, $imm_s13)
|
||||
};
|
||||
}
|
||||
constify_imm_s13!(imm_s13, call)
|
||||
#[rustc_legacy_const_generics(2)]
|
||||
pub unsafe fn __msa_st_d<const IMM_S13: i32>(a: v2i64, mem_addr: *mut u8) -> () {
|
||||
static_assert_imm_s13!(IMM_S13);
|
||||
static_assert!(IMM_S13: i32 where IMM_S13 % 8 == 0);
|
||||
msa_st_d(a, mem_addr, IMM_S13)
|
||||
}
|
||||
|
||||
/// Vector Signed Saturated Subtract of Signed Values
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue