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Fix tests/codegen-llvm/const-vector.rs test failure on riscv64

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Caiweiran 2025-07-23 11:23:36 +00:00
parent a7a1618e6c
commit 2e49c52855
1 changed files with 2 additions and 0 deletions
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2
tests/codegen-llvm/const-vector.rs
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@ -15,6 +15,7 @@
#![feature(arm_target_feature)]
#![feature(mips_target_feature)]
#![allow(non_camel_case_types)]
#![feature(riscv_target_feature)]
#[path = "../auxiliary/minisimd.rs"]
mod minisimd;
@ -42,6 +43,7 @@ extern "unadjusted" {
#[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))]
#[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))]
#[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))]
#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))]
pub fn do_call() {
unsafe {
// CHECK: call void @test_i8x2(<2 x i8> <i8 32, i8 64>