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Fix panic due to overflow in riscv.rs and int/shift.rs

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This commit is contained in:
Taiki Endo 2023-03-23 22:00:22 +09:00
parent da5001e4c6
commit 2f43b93603
2 changed files with 7 additions and 7 deletions
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6
library/compiler-builtins/src/int/shift.rs
View file

@ -12,7 +12,7 @@ trait Ashl: DInt {
} else {
Self::from_lo_hi(
self.lo().wrapping_shl(shl),
self.lo().logical_shr(n_h - shl) | self.hi().wrapping_shl(shl),
self.lo().logical_shr(n_h.wrapping_sub(shl)) | self.hi().wrapping_shl(shl),
)
}
}
@ -36,7 +36,7 @@ trait Ashr: DInt {
self
} else {
Self::from_lo_hi(
self.lo().logical_shr(shr) | self.hi().wrapping_shl(n_h - shr),
self.lo().logical_shr(shr) | self.hi().wrapping_shl(n_h.wrapping_sub(shr)),
self.hi().wrapping_shr(shr),
)
}
@ -57,7 +57,7 @@ trait Lshr: DInt {
self
} else {
Self::from_lo_hi(
self.lo().logical_shr(shr) | self.hi().wrapping_shl(n_h - shr),
self.lo().logical_shr(shr) | self.hi().wrapping_shl(n_h.wrapping_sub(shr)),
self.hi().logical_shr(shr),
)
}

8
library/compiler-builtins/src/riscv.rs
View file

@ -19,11 +19,11 @@ intrinsics! {
// https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/builtins/riscv/int_mul_impl.inc
pub extern "C" fn __mulsi3(a: u32, b: u32) -> u32 {
let (mut a, mut b) = (a, b);
let mut r = 0;
let mut r: u32 = 0;
while a > 0 {
if a & 1 > 0 {
r += b;
r = r.wrapping_add(b);
}
a >>= 1;
b <<= 1;
@ -35,11 +35,11 @@ intrinsics! {
#[cfg(not(target_feature = "m"))]
pub extern "C" fn __muldi3(a: u64, b: u64) -> u64 {
let (mut a, mut b) = (a, b);
let mut r = 0;
let mut r: u64 = 0;
while a > 0 {
if a & 1 > 0 {
r += b;
r = r.wrapping_add(b);
}
a >>= 1;
b <<= 1;