Add bare metal riscv32 target.

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Roy Buitenhuis 2024-03-18 17:15:12 +01:00
parent c86f3ac24f
commit 2fca27cd3b
6 changed files with 40 additions and 1 deletions

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@ -339,6 +339,7 @@ target | std | host | notes
`riscv32gc-unknown-linux-gnu` | | | RISC-V Linux (kernel 5.4, glibc 2.33)
`riscv32gc-unknown-linux-musl` | | | RISC-V Linux (kernel 5.4, musl 1.2.3 + RISCV32 support patches)
[`riscv32im-risc0-zkvm-elf`](platform-support/riscv32im-risc0-zkvm-elf.md) | ? | | RISC Zero's zero-knowledge Virtual Machine (RV32IM ISA)
[`riscv32ima-unknown-none-elf`](platform-support/riscv32-unknown-none-elf.md) | * | | Bare RISC-V (RV32IMA ISA)
[`riscv32imac-unknown-xous-elf`](platform-support/riscv32imac-unknown-xous-elf.md) | ? | | RISC-V Xous (RV32IMAC ISA)
[`riscv32imc-esp-espidf`](platform-support/esp-idf.md) | ✓ | | RISC-V ESP-IDF
[`riscv32imac-esp-espidf`](platform-support/esp-idf.md) | ✓ | | RISC-V ESP-IDF

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@ -1,9 +1,13 @@
# `riscv32{i,im,imc,imac,imafc}-unknown-none-elf`
# `riscv32{i,im,ima,imc,imac,imafc}-unknown-none-elf`
**Tier: 2**
Bare-metal target for RISC-V CPUs with the RV32I, RV32IM, RV32IMC, RV32IMAFC and RV32IMAC ISAs.
**Tier: 3**
Bare-metal target for RISC-V CPUs with the RV32IMA ISA.
## Target maintainers
* Rust Embedded Working Group, [RISC-V team](https://github.com/rust-embedded/wg#the-risc-v-team)