Remove the bootstrap directive for cryptographic target_features
This commit is contained in:
Adam Gemmell
Amanieu d'Antras
parent
8cb8cd2142
commit
3347e8cc98
1 changed files with 57 additions and 126 deletions
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@ -51,17 +51,12 @@ extern "C" {
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#[cfg(test)]
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use stdarch_test::assert_instr;
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// Rust compilers without 8a57820bca64a252489790a57cb5ea23db6f9198 need crypto (hence the bootstrap check)
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// LLVM builds without b8baa2a9132498ea286dbb0d03f005760ecc6fdb need crypto for arm (hence the target_arch check)
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// TODO: Use AES for ARM when the minimum LLVM version includes b8baa2a9132498ea286dbb0d03f005760ecc6fdb
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/// AES single round encryption.
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#[inline]
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#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
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#[cfg_attr(
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not(any(bootstrap, target_arch = "arm")),
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target_feature(enable = "aes")
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)]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "aes"))]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
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#[cfg_attr(test, assert_instr(aese))]
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pub unsafe fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
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vaeseq_u8_(data, key)
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@ -69,12 +64,8 @@ pub unsafe fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
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/// AES single round decryption.
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#[inline]
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#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
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#[cfg_attr(
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not(any(bootstrap, target_arch = "arm")),
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target_feature(enable = "aes")
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)]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "aes"))]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
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#[cfg_attr(test, assert_instr(aesd))]
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pub unsafe fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
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vaesdq_u8_(data, key)
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@ -82,12 +73,8 @@ pub unsafe fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
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/// AES mix columns.
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#[inline]
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#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
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#[cfg_attr(
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not(any(bootstrap, target_arch = "arm")),
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target_feature(enable = "aes")
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)]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "aes"))]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
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#[cfg_attr(test, assert_instr(aesmc))]
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pub unsafe fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t {
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vaesmcq_u8_(data)
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@ -95,12 +82,8 @@ pub unsafe fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t {
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/// AES inverse mix columns.
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#[inline]
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#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
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#[cfg_attr(
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not(any(bootstrap, target_arch = "arm")),
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target_feature(enable = "aes")
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)]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "aes"))]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
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#[cfg_attr(test, assert_instr(aesimc))]
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pub unsafe fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t {
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vaesimcq_u8_(data)
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@ -108,12 +91,8 @@ pub unsafe fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t {
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/// SHA1 fixed rotate.
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#[inline]
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#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
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#[cfg_attr(
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not(any(bootstrap, target_arch = "arm")),
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target_feature(enable = "sha2")
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)]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
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#[cfg_attr(test, assert_instr(sha1h))]
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pub unsafe fn vsha1h_u32(hash_e: u32) -> u32 {
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vsha1h_u32_(hash_e)
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@ -121,12 +100,8 @@ pub unsafe fn vsha1h_u32(hash_e: u32) -> u32 {
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/// SHA1 hash update accelerator, choose.
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#[inline]
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#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
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#[cfg_attr(
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not(any(bootstrap, target_arch = "arm")),
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target_feature(enable = "sha2")
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)]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
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#[cfg_attr(test, assert_instr(sha1c))]
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pub unsafe fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
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vsha1cq_u32_(hash_abcd, hash_e, wk)
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@ -134,12 +109,8 @@ pub unsafe fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) ->
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/// SHA1 hash update accelerator, majority.
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#[inline]
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#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
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#[cfg_attr(
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not(any(bootstrap, target_arch = "arm")),
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target_feature(enable = "sha2")
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)]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
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#[cfg_attr(test, assert_instr(sha1m))]
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pub unsafe fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
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vsha1mq_u32_(hash_abcd, hash_e, wk)
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@ -147,12 +118,8 @@ pub unsafe fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) ->
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/// SHA1 hash update accelerator, parity.
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#[inline]
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#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
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#[cfg_attr(
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not(any(bootstrap, target_arch = "arm")),
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target_feature(enable = "sha2")
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)]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
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#[cfg_attr(test, assert_instr(sha1p))]
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pub unsafe fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
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vsha1pq_u32_(hash_abcd, hash_e, wk)
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@ -160,12 +127,8 @@ pub unsafe fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) ->
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/// SHA1 schedule update accelerator, first part.
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#[inline]
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#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
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#[cfg_attr(
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not(any(bootstrap, target_arch = "arm")),
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target_feature(enable = "sha2")
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)]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
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#[cfg_attr(test, assert_instr(sha1su0))]
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pub unsafe fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t {
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vsha1su0q_u32_(w0_3, w4_7, w8_11)
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@ -173,12 +136,8 @@ pub unsafe fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_
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/// SHA1 schedule update accelerator, second part.
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#[inline]
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#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
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#[cfg_attr(
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not(any(bootstrap, target_arch = "arm")),
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target_feature(enable = "sha2")
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)]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
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#[cfg_attr(test, assert_instr(sha1su1))]
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pub unsafe fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t {
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vsha1su1q_u32_(tw0_3, w12_15)
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@ -186,12 +145,8 @@ pub unsafe fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t
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/// SHA256 hash update accelerator.
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#[inline]
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#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
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#[cfg_attr(
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not(any(bootstrap, target_arch = "arm")),
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target_feature(enable = "sha2")
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)]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
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#[cfg_attr(test, assert_instr(sha256h))]
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pub unsafe fn vsha256hq_u32(
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hash_abcd: uint32x4_t,
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@ -203,12 +158,8 @@ pub unsafe fn vsha256hq_u32(
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/// SHA256 hash update accelerator, upper part.
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#[inline]
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#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
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#[cfg_attr(
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not(any(bootstrap, target_arch = "arm")),
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target_feature(enable = "sha2")
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)]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
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#[cfg_attr(test, assert_instr(sha256h2))]
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pub unsafe fn vsha256h2q_u32(
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hash_efgh: uint32x4_t,
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@ -220,12 +171,8 @@ pub unsafe fn vsha256h2q_u32(
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/// SHA256 schedule update accelerator, first part.
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#[inline]
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#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
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#[cfg_attr(
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not(any(bootstrap, target_arch = "arm")),
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target_feature(enable = "sha2")
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)]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
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#[cfg_attr(test, assert_instr(sha256su0))]
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pub unsafe fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t {
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vsha256su0q_u32_(w0_3, w4_7)
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@ -233,12 +180,8 @@ pub unsafe fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t
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/// SHA256 schedule update accelerator, second part.
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#[inline]
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#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
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#[cfg_attr(
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not(any(bootstrap, target_arch = "arm")),
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target_feature(enable = "sha2")
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)]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
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#[cfg_attr(test, assert_instr(sha256su1))]
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pub unsafe fn vsha256su1q_u32(
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tw0_3: uint32x4_t,
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@ -255,11 +198,8 @@ mod tests {
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use std::mem;
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use stdarch_test::simd_test;
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#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
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#[cfg_attr(
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all(not(bootstrap), target_arch = "aarch64"),
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simd_test(enable = "aes")
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)]
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#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
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#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "aes"))]
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unsafe fn test_vaeseq_u8() {
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let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
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let key = mem::transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
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@ -272,11 +212,8 @@ mod tests {
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);
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}
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#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
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#[cfg_attr(
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all(not(bootstrap), target_arch = "aarch64"),
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simd_test(enable = "aes")
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)]
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#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
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#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "aes"))]
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unsafe fn test_vaesdq_u8() {
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let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
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let key = mem::transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
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@ -287,11 +224,8 @@ mod tests {
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);
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}
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#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
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#[cfg_attr(
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all(not(bootstrap), target_arch = "aarch64"),
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simd_test(enable = "aes")
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)]
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#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
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#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "aes"))]
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unsafe fn test_vaesmcq_u8() {
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let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
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let r: u8x16 = mem::transmute(vaesmcq_u8(data));
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@ -301,11 +235,8 @@ mod tests {
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);
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}
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#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
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#[cfg_attr(
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all(not(bootstrap), target_arch = "aarch64"),
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simd_test(enable = "aes")
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)]
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#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
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#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "aes"))]
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unsafe fn test_vaesimcq_u8() {
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let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
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let r: u8x16 = mem::transmute(vaesimcq_u8(data));
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@ -315,15 +246,15 @@ mod tests {
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);
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}
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#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
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#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
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#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
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#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
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unsafe fn test_vsha1h_u32() {
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assert_eq!(vsha1h_u32(0x1234), 0x048d);
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assert_eq!(vsha1h_u32(0x5678), 0x159e);
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}
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#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
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#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
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#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
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#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
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unsafe fn test_vsha1su0q_u32() {
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let r: u32x4 = mem::transmute(vsha1su0q_u32(
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mem::transmute(u32x4::new(0x1234_u32, 0x5678_u32, 0x9abc_u32, 0xdef0_u32)),
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@ -333,8 +264,8 @@ mod tests {
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assert_eq!(r, u32x4::new(0x9abc, 0xdef0, 0x1234, 0x5678));
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}
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#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
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#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
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#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
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#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
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unsafe fn test_vsha1su1q_u32() {
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let r: u32x4 = mem::transmute(vsha1su1q_u32(
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mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
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@ -346,8 +277,8 @@ mod tests {
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);
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}
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#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
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#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
|
||||
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
|
||||
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
|
||||
unsafe fn test_vsha1cq_u32() {
|
||||
let r: u32x4 = mem::transmute(vsha1cq_u32(
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
|
|
@ -360,8 +291,8 @@ mod tests {
|
|||
);
|
||||
}
|
||||
|
||||
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
|
||||
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
|
||||
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
|
||||
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
|
||||
unsafe fn test_vsha1pq_u32() {
|
||||
let r: u32x4 = mem::transmute(vsha1pq_u32(
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
|
|
@ -374,8 +305,8 @@ mod tests {
|
|||
);
|
||||
}
|
||||
|
||||
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
|
||||
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
|
||||
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
|
||||
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
|
||||
unsafe fn test_vsha1mq_u32() {
|
||||
let r: u32x4 = mem::transmute(vsha1mq_u32(
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
|
|
@ -388,8 +319,8 @@ mod tests {
|
|||
);
|
||||
}
|
||||
|
||||
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
|
||||
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
|
||||
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
|
||||
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
|
||||
unsafe fn test_vsha256hq_u32() {
|
||||
let r: u32x4 = mem::transmute(vsha256hq_u32(
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
|
|
@ -402,8 +333,8 @@ mod tests {
|
|||
);
|
||||
}
|
||||
|
||||
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
|
||||
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
|
||||
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
|
||||
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
|
||||
unsafe fn test_vsha256h2q_u32() {
|
||||
let r: u32x4 = mem::transmute(vsha256h2q_u32(
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
|
|
@ -416,8 +347,8 @@ mod tests {
|
|||
);
|
||||
}
|
||||
|
||||
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
|
||||
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
|
||||
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
|
||||
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
|
||||
unsafe fn test_vsha256su0q_u32() {
|
||||
let r: u32x4 = mem::transmute(vsha256su0q_u32(
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
|
|
@ -429,8 +360,8 @@ mod tests {
|
|||
);
|
||||
}
|
||||
|
||||
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
|
||||
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
|
||||
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
|
||||
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
|
||||
unsafe fn test_vsha256su1q_u32() {
|
||||
let r: u32x4 = mem::transmute(vsha256su1q_u32(
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue