Fix more missing/incorrect feature specifications

library/stdarch/crates/core_arch/src/arm_shared/barrier/mod.rs

@@ -16,6 +16,7 @@ mod cp15;
     target_feature = "v7",
     target_feature = "mclass"
 )))]
+#[unstable(feature = "stdarch_arm_barrier", issue = "117219")]
 pub use self::cp15::*;
 
 // Dedicated instructions

library/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs

@@ -8888,7 +8888,7 @@ pub unsafe fn vcombine_p16(low: poly16x4_t, high: poly16x4_t) -> poly16x8_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
 #[cfg_attr(
-    target_arch = "aarch64",
+    not(target_arch = "arm"),
     stable(feature = "neon_intrinsics", since = "1.59.0")
 )]
 #[cfg_attr(
@@ -8909,7 +8909,7 @@ pub unsafe fn vcombine_s8(low: int8x8_t, high: int8x8_t) -> int8x16_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
 #[cfg_attr(
-    target_arch = "aarch64",
+    not(target_arch = "arm"),
     stable(feature = "neon_intrinsics", since = "1.59.0")
 )]
 #[cfg_attr(
@@ -8926,7 +8926,7 @@ pub unsafe fn vcombine_s16(low: int16x4_t, high: int16x4_t) -> int16x8_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
 #[cfg_attr(
-    target_arch = "aarch64",
+    not(target_arch = "arm"),
     stable(feature = "neon_intrinsics", since = "1.59.0")
 )]
 #[cfg_attr(
@@ -8943,7 +8943,7 @@ pub unsafe fn vcombine_s32(low: int32x2_t, high: int32x2_t) -> int32x4_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
 #[cfg_attr(
-    target_arch = "aarch64",
+    not(target_arch = "arm"),
     stable(feature = "neon_intrinsics", since = "1.59.0")
 )]
 #[cfg_attr(
@@ -8960,7 +8960,7 @@ pub unsafe fn vcombine_s64(low: int64x1_t, high: int64x1_t) -> int64x2_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
 #[cfg_attr(
-    target_arch = "aarch64",
+    not(target_arch = "arm"),
     stable(feature = "neon_intrinsics", since = "1.59.0")
 )]
 #[cfg_attr(
@@ -8981,7 +8981,7 @@ pub unsafe fn vcombine_u8(low: uint8x8_t, high: uint8x8_t) -> uint8x16_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
 #[cfg_attr(
-    target_arch = "aarch64",
+    not(target_arch = "arm"),
     stable(feature = "neon_intrinsics", since = "1.59.0")
 )]
 #[cfg_attr(
@@ -8999,7 +8999,7 @@ pub unsafe fn vcombine_u16(low: uint16x4_t, high: uint16x4_t) -> uint16x8_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mov))]
 #[cfg_attr(
-    target_arch = "aarch64",
+    not(target_arch = "arm"),
     stable(feature = "neon_intrinsics", since = "1.59.0")
 )]
 #[cfg_attr(
@@ -9016,7 +9016,7 @@ pub unsafe fn vcombine_u32(low: uint32x2_t, high: uint32x2_t) -> uint32x4_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
 #[cfg_attr(
-    target_arch = "aarch64",
+    not(target_arch = "arm"),
     stable(feature = "neon_intrinsics", since = "1.59.0")
 )]
 #[cfg_attr(
@@ -9033,7 +9033,7 @@ pub unsafe fn vcombine_u64(low: uint64x1_t, high: uint64x1_t) -> uint64x2_t {
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
 #[cfg_attr(
-    target_arch = "aarch64",
+    not(target_arch = "arm"),
     stable(feature = "neon_intrinsics", since = "1.59.0")
 )]
 #[cfg_attr(

library/stdarch/crates/core_arch/src/lib.rs

@@ -57,7 +57,10 @@
     test(attr(deny(warnings))),
     test(attr(allow(dead_code, deprecated, unused_variables, unused_mut)))
 )]
-#![cfg_attr(test, feature(stdarch_arm_feature_detection))]
+#![cfg_attr(
+    test,
+    feature(stdarch_arm_feature_detection, stdarch_powerpc_feature_detection)
+)]
 
 #[cfg(test)]
 #[macro_use]

library/stdarch/crates/core_arch/src/powerpc/altivec.rs

@@ -551,6 +551,7 @@ mod sealed {
 
     impl_vec_lde! { vec_lde_f32 lvewx f32 }
 
+    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
     pub trait VectorXl {
         type Result;
         unsafe fn vec_xl(self, a: isize) -> Self::Result;
@@ -586,6 +587,7 @@ mod sealed {
                 r.assume_init()
             }
 
+            #[unstable(feature = "stdarch_powerpc", issue = "111145")]
             impl VectorXl for *const $ty {
                 type Result = t_t_l!($ty);
                 #[inline]
@@ -1303,12 +1305,14 @@ mod sealed {
         vec_perm(a, a, transmute(b))
     }
 
+    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
     pub trait VectorSplat {
         unsafe fn vec_splat<const IMM: u32>(self) -> Self;
     }
 
     macro_rules! impl_vec_splat {
         ($ty:ty, $fun:ident) => {
+            #[unstable(feature = "stdarch_powerpc", issue = "111145")]
             impl VectorSplat for $ty {
                 #[inline]
                 #[target_feature(enable = "altivec")]
@@ -1335,6 +1339,7 @@ mod sealed {
             #[inline]
             #[target_feature(enable = "altivec")]
             #[cfg_attr(test, assert_instr($instr, IMM5 = 1))]
+            #[unstable(feature = "stdarch_powerpc", issue = "111145")]
             pub unsafe fn $name<const IMM5: i8>() -> s_t_l!($r) {
                 static_assert_simm_bits!(IMM5, 5);
                 transmute($r::splat(IMM5 as $v))
@@ -2363,6 +2368,7 @@ mod sealed {
         vec_perm(a, b, mergel_perm)
     }
 
+    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
     pub trait VectorMergeh<Other> {
         type Result;
         unsafe fn vec_mergeh(self, b: Other) -> Self::Result;
@@ -2371,6 +2377,7 @@ mod sealed {
     impl_vec_trait! { [VectorMergeh vec_mergeh]+ 2b (vec_vmrghb, vec_vmrghh, vec_vmrghw) }
     impl_vec_trait! { [VectorMergeh vec_mergeh]+ vec_vmrghw (vector_float, vector_float) -> vector_float }
 
+    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
     pub trait VectorMergel<Other> {
         type Result;
         unsafe fn vec_mergel(self, b: Other) -> Self::Result;
@@ -2417,6 +2424,7 @@ mod sealed {
         transmute(vec_perm(a, b, pack_perm))
     }
 
+    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
     pub trait VectorPack<Other> {
         type Result;
         unsafe fn vec_pack(self, b: Other) -> Self::Result;
@@ -2498,6 +2506,7 @@ mod sealed {
         }
     }
 
+    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
     pub trait VectorPacks<Other> {
         type Result;
         unsafe fn vec_packs(self, b: Other) -> Self::Result;
@@ -2508,6 +2517,7 @@ mod sealed {
     impl_vec_trait! { [VectorPacks vec_packs] vec_vpkswss (vector_signed_int, vector_signed_int) -> vector_signed_short }
     impl_vec_trait! { [VectorPacks vec_packs] vec_vpkuwus (vector_unsigned_int, vector_unsigned_int) -> vector_unsigned_short }
 
+    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
     pub trait VectorPacksu<Other> {
         type Result;
         unsafe fn vec_packsu(self, b: Other) -> Self::Result;
@@ -2539,6 +2549,7 @@ mod sealed {
     impl_vec_unpack! { vec_vupkhsh (vector_signed_short) -> vector_signed_int [vupklsh, vupkhsh] }
     impl_vec_unpack! { vec_vupklsh (vector_signed_short) -> vector_signed_int [vupkhsh, vupklsh] }
 
+    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
     pub trait VectorUnpackh {
         type Result;
         unsafe fn vec_unpackh(self) -> Self::Result;
@@ -2549,6 +2560,7 @@ mod sealed {
     impl_vec_trait! { [VectorUnpackh vec_unpackh] vec_vupkhsh (vector_signed_short) -> vector_signed_int }
     impl_vec_trait! { [VectorUnpackh vec_unpackh]+ vec_vupkhsh (vector_bool_short) -> vector_bool_int }
 
+    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
     pub trait VectorUnpackl {
         type Result;
         unsafe fn vec_unpackl(self) -> Self::Result;
@@ -2563,6 +2575,7 @@ mod sealed {
 /// Vector Merge Low
 #[inline]
 #[target_feature(enable = "altivec")]
+#[unstable(feature = "stdarch_powerpc", issue = "111145")]
 pub unsafe fn vec_mergel<T, U>(a: T, b: U) -> <T as sealed::VectorMergel<U>>::Result
 where
     T: sealed::VectorMergel<U>,
@@ -2573,6 +2586,7 @@ where
 /// Vector Merge High
 #[inline]
 #[target_feature(enable = "altivec")]
+#[unstable(feature = "stdarch_powerpc", issue = "111145")]
 pub unsafe fn vec_mergeh<T, U>(a: T, b: U) -> <T as sealed::VectorMergeh<U>>::Result
 where
     T: sealed::VectorMergeh<U>,
@@ -2583,6 +2597,7 @@ where
 /// Vector Pack
 #[inline]
 #[target_feature(enable = "altivec")]
+#[unstable(feature = "stdarch_powerpc", issue = "111145")]
 pub unsafe fn vec_pack<T, U>(a: T, b: U) -> <T as sealed::VectorPack<U>>::Result
 where
     T: sealed::VectorPack<U>,
@@ -2593,6 +2608,7 @@ where
 /// Vector Pack Saturated
 #[inline]
 #[target_feature(enable = "altivec")]
+#[unstable(feature = "stdarch_powerpc", issue = "111145")]
 pub unsafe fn vec_packs<T, U>(a: T, b: U) -> <T as sealed::VectorPacks<U>>::Result
 where
     T: sealed::VectorPacks<U>,
@@ -2603,6 +2619,7 @@ where
 /// Vector Pack Saturated Unsigned
 #[inline]
 #[target_feature(enable = "altivec")]
+#[unstable(feature = "stdarch_powerpc", issue = "111145")]
 pub unsafe fn vec_packsu<T, U>(a: T, b: U) -> <T as sealed::VectorPacksu<U>>::Result
 where
     T: sealed::VectorPacksu<U>,
@@ -2613,6 +2630,7 @@ where
 /// Vector Unpack High
 #[inline]
 #[target_feature(enable = "altivec")]
+#[unstable(feature = "stdarch_powerpc", issue = "111145")]
 pub unsafe fn vec_unpackh<T>(a: T) -> <T as sealed::VectorUnpackh>::Result
 where
     T: sealed::VectorUnpackh,
@@ -2623,6 +2641,7 @@ where
 /// Vector Unpack Low
 #[inline]
 #[target_feature(enable = "altivec")]
+#[unstable(feature = "stdarch_powerpc", issue = "111145")]
 pub unsafe fn vec_unpackl<T>(a: T) -> <T as sealed::VectorUnpackl>::Result
 where
     T: sealed::VectorUnpackl,
@@ -2666,6 +2685,7 @@ where
 /// VSX Unaligned Load
 #[inline]
 #[target_feature(enable = "altivec")]
+#[unstable(feature = "stdarch_powerpc", issue = "111145")]
 pub unsafe fn vec_xl<T>(off: isize, p: T) -> <T as sealed::VectorXl>::Result
 where
     T: sealed::VectorXl,
@@ -2677,6 +2697,7 @@ where
 #[inline]
 #[target_feature(enable = "altivec")]
 #[cfg_attr(test, assert_instr(vlogefp))]
+#[unstable(feature = "stdarch_powerpc", issue = "111145")]
 pub unsafe fn vec_loge(a: vector_float) -> vector_float {
     vlogefp(a)
 }
@@ -2872,6 +2893,7 @@ where
 /// Vector Splat
 #[inline]
 #[target_feature(enable = "altivec")]
+#[unstable(feature = "stdarch_powerpc", issue = "111145")]
 pub unsafe fn vec_splat<T, const IMM: u32>(a: T) -> T
 where
     T: sealed::VectorSplat,
@@ -2945,6 +2967,7 @@ where
 #[inline]
 #[target_feature(enable = "altivec")]
 #[cfg_attr(test, assert_instr(mfvscr))]
+#[unstable(feature = "stdarch_powerpc", issue = "111145")]
 pub unsafe fn vec_mfvscr() -> vector_unsigned_short {
     mfvscr()
 }
@@ -3406,6 +3429,7 @@ mod endian {
     /// Vector permute.
     #[inline]
     #[target_feature(enable = "altivec")]
+    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
     pub unsafe fn vec_perm<T>(a: T, b: T, c: vector_unsigned_char) -> T
     where
         T: sealed::VectorPerm,
@@ -3416,6 +3440,7 @@ mod endian {
     /// Vector Sum Across Partial (1/2) Saturated
     #[inline]
     #[target_feature(enable = "altivec")]
+    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
     pub unsafe fn vec_sum2s(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int {
         vsum2sws(a, b)
     }
@@ -3423,6 +3448,7 @@ mod endian {
     /// Vector Multiply Even
     #[inline]
     #[target_feature(enable = "altivec")]
+    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
     pub unsafe fn vec_mule<T, U>(a: T, b: T) -> U
     where
         T: sealed::VectorMule<U>,
@@ -3432,6 +3458,7 @@ mod endian {
     /// Vector Multiply Odd
     #[inline]
     #[target_feature(enable = "altivec")]
+    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
     pub unsafe fn vec_mulo<T, U>(a: T, b: T) -> U
     where
         T: sealed::VectorMulo<U>,

library/stdarch/crates/core_arch/src/powerpc/macros.rs

@@ -42,6 +42,7 @@ macro_rules! impl_vec_trait {
         }
     };
     ([$Trait:ident $m:ident]+ $fun:ident ($a:ty) -> $r:ty) => {
+        #[unstable(feature = "stdarch_powerpc", issue = "111145")]
         impl $Trait for $a {
             type Result = $r;
             #[inline]
@@ -72,6 +73,7 @@ macro_rules! impl_vec_trait {
         }
     };
     ([$Trait:ident $m:ident]+ $fun:ident ($a:ty, $b:ty) -> $r:ty) => {
+        #[unstable(feature = "stdarch_powerpc", issue = "111145")]
         impl $Trait<$b> for $a {
             type Result = $r;
             #[inline]

library/stdarch/crates/core_arch/src/riscv32/mod.rs

@@ -2,4 +2,5 @@
 
 mod zk;
 
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub use zk::*;

library/stdarch/crates/core_arch/src/riscv32/zk.rs

@@ -65,6 +65,7 @@ extern "unadjusted" {
 // See #1464
 // #[cfg_attr(test, assert_instr(aes32esi, BS = 0))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn aes32esi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
     static_assert!(BS < 4);
 
@@ -97,6 +98,7 @@ pub unsafe fn aes32esi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
 // See #1464
 // #[cfg_attr(test, assert_instr(aes32esmi, BS = 0))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn aes32esmi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
     static_assert!(BS < 4);
 
@@ -128,6 +130,7 @@ pub unsafe fn aes32esmi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
 // See #1464
 // #[cfg_attr(test, assert_instr(aes32dsi, BS = 0))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn aes32dsi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
     static_assert!(BS < 4);
 
@@ -160,6 +163,7 @@ pub unsafe fn aes32dsi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
 // See #1464
 // #[cfg_attr(test, assert_instr(aes32dsmi, BS = 0))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn aes32dsmi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
     static_assert!(BS < 4);
 
@@ -187,6 +191,7 @@ pub unsafe fn aes32dsmi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
 // See #1464
 // #[cfg_attr(test, assert_instr(zip))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn zip(rs: u32) -> u32 {
     _zip(rs as i32) as u32
 }
@@ -209,6 +214,7 @@ pub unsafe fn zip(rs: u32) -> u32 {
 #[target_feature(enable = "zbkb")]
 #[cfg_attr(test, assert_instr(unzip))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn unzip(rs: u32) -> u32 {
     _unzip(rs as i32) as u32
 }
@@ -235,6 +241,7 @@ pub unsafe fn unzip(rs: u32) -> u32 {
 // See #1464
 // #[cfg_attr(test, assert_instr(sha512sig0h))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn sha512sig0h(rs1: u32, rs2: u32) -> u32 {
     _sha512sig0h(rs1 as i32, rs2 as i32) as u32
 }
@@ -261,6 +268,7 @@ pub unsafe fn sha512sig0h(rs1: u32, rs2: u32) -> u32 {
 // See #1464
 // #[cfg_attr(test, assert_instr(sha512sig0l))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn sha512sig0l(rs1: u32, rs2: u32) -> u32 {
     _sha512sig0l(rs1 as i32, rs2 as i32) as u32
 }
@@ -287,6 +295,7 @@ pub unsafe fn sha512sig0l(rs1: u32, rs2: u32) -> u32 {
 // See #1464
 // #[cfg_attr(test, assert_instr(sha512sig1h))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn sha512sig1h(rs1: u32, rs2: u32) -> u32 {
     _sha512sig1h(rs1 as i32, rs2 as i32) as u32
 }
@@ -312,6 +321,7 @@ pub unsafe fn sha512sig1h(rs1: u32, rs2: u32) -> u32 {
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha512sig1l))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn sha512sig1l(rs1: u32, rs2: u32) -> u32 {
     _sha512sig1l(rs1 as i32, rs2 as i32) as u32
 }
@@ -337,6 +347,7 @@ pub unsafe fn sha512sig1l(rs1: u32, rs2: u32) -> u32 {
 // See #1464
 // #[cfg_attr(test, assert_instr(sha512sum0r))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn sha512sum0r(rs1: u32, rs2: u32) -> u32 {
     _sha512sum0r(rs1 as i32, rs2 as i32) as u32
 }
@@ -362,6 +373,7 @@ pub unsafe fn sha512sum0r(rs1: u32, rs2: u32) -> u32 {
 // See #1464
 // #[cfg_attr(test, assert_instr(sha512sum1r))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn sha512sum1r(rs1: u32, rs2: u32) -> u32 {
     _sha512sum1r(rs1 as i32, rs2 as i32) as u32
 }

library/stdarch/crates/core_arch/src/riscv64/mod.rs

@@ -3,6 +3,7 @@ use crate::arch::asm;
 
 mod zk;
 
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub use zk::*;
 
 /// Loads virtual machine memory by unsigned word integer

library/stdarch/crates/core_arch/src/riscv64/zk.rs

@@ -55,6 +55,7 @@ extern "unadjusted" {
 #[target_feature(enable = "zkne")]
 #[cfg_attr(test, assert_instr(aes64es))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn aes64es(rs1: u64, rs2: u64) -> u64 {
     _aes64es(rs1 as i64, rs2 as i64) as u64
 }
@@ -78,6 +79,7 @@ pub unsafe fn aes64es(rs1: u64, rs2: u64) -> u64 {
 #[target_feature(enable = "zkne")]
 #[cfg_attr(test, assert_instr(aes64esm))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn aes64esm(rs1: u64, rs2: u64) -> u64 {
     _aes64esm(rs1 as i64, rs2 as i64) as u64
 }
@@ -101,6 +103,7 @@ pub unsafe fn aes64esm(rs1: u64, rs2: u64) -> u64 {
 #[target_feature(enable = "zknd")]
 #[cfg_attr(test, assert_instr(aes64ds))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn aes64ds(rs1: u64, rs2: u64) -> u64 {
     _aes64ds(rs1 as i64, rs2 as i64) as u64
 }
@@ -124,6 +127,7 @@ pub unsafe fn aes64ds(rs1: u64, rs2: u64) -> u64 {
 #[target_feature(enable = "zknd")]
 #[cfg_attr(test, assert_instr(aes64dsm))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn aes64dsm(rs1: u64, rs2: u64) -> u64 {
     _aes64dsm(rs1 as i64, rs2 as i64) as u64
 }
@@ -153,6 +157,7 @@ pub unsafe fn aes64dsm(rs1: u64, rs2: u64) -> u64 {
 #[rustc_legacy_const_generics(1)]
 #[cfg_attr(test, assert_instr(aes64ks1i, RNUM = 0))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn aes64ks1i<const RNUM: u8>(rs1: u64) -> u64 {
     static_assert!(RNUM <= 10);
 
@@ -177,6 +182,7 @@ pub unsafe fn aes64ks1i<const RNUM: u8>(rs1: u64) -> u64 {
 #[target_feature(enable = "zkne", enable = "zknd")]
 #[cfg_attr(test, assert_instr(aes64ks2))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn aes64ks2(rs1: u64, rs2: u64) -> u64 {
     _aes64ks2(rs1 as i64, rs2 as i64) as u64
 }
@@ -201,6 +207,7 @@ pub unsafe fn aes64ks2(rs1: u64, rs2: u64) -> u64 {
 #[target_feature(enable = "zkne", enable = "zknd")]
 #[cfg_attr(test, assert_instr(aes64im))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn aes64im(rs1: u64) -> u64 {
     _aes64im(rs1 as i64) as u64
 }
@@ -224,6 +231,7 @@ pub unsafe fn aes64im(rs1: u64) -> u64 {
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha512sig0))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn sha512sig0(rs1: u64) -> u64 {
     _sha512sig0(rs1 as i64) as u64
 }
@@ -247,6 +255,7 @@ pub unsafe fn sha512sig0(rs1: u64) -> u64 {
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha512sig1))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn sha512sig1(rs1: u64) -> u64 {
     _sha512sig1(rs1 as i64) as u64
 }
@@ -270,6 +279,7 @@ pub unsafe fn sha512sig1(rs1: u64) -> u64 {
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha512sum0))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn sha512sum0(rs1: u64) -> u64 {
     _sha512sum0(rs1 as i64) as u64
 }
@@ -293,6 +303,7 @@ pub unsafe fn sha512sum0(rs1: u64) -> u64 {
 #[target_feature(enable = "zknh")]
 #[cfg_attr(test, assert_instr(sha512sum1))]
 #[inline]
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub unsafe fn sha512sum1(rs1: u64) -> u64 {
     _sha512sum1(rs1 as i64) as u64
 }

library/stdarch/crates/core_arch/src/riscv_shared/mod.rs

@@ -6,7 +6,9 @@ mod zk;
 
 #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub use p::*;
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub use zb::*;
+#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")]
 pub use zk::*;
 
 use crate::arch::asm;

library/stdarch/crates/std_detect/tests/cpu-detection.rs

@@ -1,4 +1,8 @@
-#![feature(stdarch_internal, stdarch_arm_feature_detection)]
+#![feature(
+    stdarch_internal,
+    stdarch_arm_feature_detection,
+    stdarch_powerpc_feature_detection
+)]
 #![allow(clippy::unwrap_used, clippy::use_debug, clippy::print_stdout)]
 #![cfg(any(
     target_arch = "arm",

library/stdarch/crates/std_detect/tests/macro_trailing_commas.rs

@@ -1,4 +1,4 @@
-#![feature(stdarch_arm_feature_detection)]
+#![feature(stdarch_arm_feature_detection, stdarch_powerpc_feature_detection)]
 #![allow(clippy::unwrap_used, clippy::use_debug, clippy::print_stdout)]
 
 #[cfg(any(