[DRAFT] intrinsics for all architectures appear in rustdoc (#1104)

library/stdarch/crates/core_arch/src/aarch64/armclang.rs

@@ -0,0 +1,23 @@
+//! ARM compiler specific intrinsics
+//!
+//! # References
+//!
+//! - [ARM Compiler v 6.10 - armclang Reference Guide][arm_comp_ref]
+//!
+//! [arm_comp_ref]: https://developer.arm.com/docs/100067/0610
+
+#[cfg(test)]
+use stdarch_test::assert_instr;
+
+/// Inserts a breakpoint instruction.
+///
+/// `VAL` is a compile-time constant integer in range `[0, 65535]`.
+///
+/// The breakpoint instruction inserted is `BRK` on A64.
+#[cfg_attr(test, assert_instr(brk, VAL = 0))]
+#[inline(always)]
+#[rustc_legacy_const_generics(0)]
+pub unsafe fn __breakpoint<const VAL: i32>() {
+    static_assert_imm16!(VAL);
+    asm!("brk {}", const VAL);
+}

library/stdarch/crates/core_arch/src/aarch64/mod.rs

@@ -21,7 +21,11 @@ pub use self::crc::*;
 mod prefetch;
 pub use self::prefetch::*;
 
-pub use super::acle::*;
+pub use super::arm_shared::*;
+
+mod armclang;
+
+pub use self::armclang::*;
 
 #[cfg(test)]
 use stdarch_test::assert_instr;

library/stdarch/crates/core_arch/src/aarch64/neon/mod.rs

@@ -10,7 +10,7 @@ pub use self::generated::*;
 // FIXME: replace neon with asimd
 
 use crate::{
-    core_arch::{arm::*, simd::*, simd_llvm::*},
+    core_arch::{arm_shared::*, simd::*, simd_llvm::*},
     hint::unreachable_unchecked,
     mem::{transmute, zeroed},
 };
@@ -2812,7 +2812,7 @@ pub unsafe fn vsriq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x
 #[cfg(test)]
 mod tests {
     use crate::core_arch::aarch64::test_support::*;
-    use crate::core_arch::arm::test_support::*;
+    use crate::core_arch::arm_shared::test_support::*;
     use crate::core_arch::{aarch64::neon::*, aarch64::*, simd::*};
     use std::mem::transmute;
     use stdarch_test::simd_test;
@@ -4261,13 +4261,13 @@ mod tests {
 
 #[cfg(test)]
 #[cfg(target_endian = "little")]
-#[path = "../../arm/neon/table_lookup_tests.rs"]
+#[path = "../../arm_shared/neon/table_lookup_tests.rs"]
 mod table_lookup_tests;
 
 #[cfg(test)]
-#[path = "../../arm/neon/shift_and_insert_tests.rs"]
+#[path = "../../arm_shared/neon/shift_and_insert_tests.rs"]
 mod shift_and_insert_tests;
 
 #[cfg(test)]
-#[path = "../../arm/neon/load_tests.rs"]
+#[path = "../../arm_shared/neon/load_tests.rs"]
 mod load_tests;

library/stdarch/crates/core_arch/src/aarch64/test_support.rs

@@ -1,4 +1,4 @@
-use crate::core_arch::{aarch64::neon::*, arm::*, simd::*};
+use crate::core_arch::{aarch64::neon::*, arm_shared::*, simd::*};
 use std::{i16, i32, i8, mem::transmute, u16, u32, u8, vec::Vec};
 
 macro_rules! V_u64 {

library/stdarch/crates/core_arch/src/arm/armclang.rs

@@ -9,20 +9,6 @@
 #[cfg(test)]
 use stdarch_test::assert_instr;
 
-/// Inserts a breakpoint instruction.
-///
-/// `VAL` is a compile-time constant integer in range `[0, 65535]`.
-///
-/// The breakpoint instruction inserted is `BRK` on A64.
-#[cfg(all(target_arch = "aarch64", not(doc)))]
-#[cfg_attr(test, assert_instr(brk, VAL = 0))]
-#[inline(always)]
-#[rustc_legacy_const_generics(0)]
-pub unsafe fn __breakpoint<const VAL: i32>() {
-    static_assert_imm16!(VAL);
-    asm!("brk {}", const VAL);
-}
-
 /// Inserts a breakpoint instruction.
 ///
 /// `VAL` is a compile-time constant integer in range `[0, 255]`.
@@ -40,8 +26,6 @@ pub unsafe fn __breakpoint<const VAL: i32>() {
 /// The current implementation only accepts values in range `[0, 255]`.
 ///
 /// [arm_docs]: https://developer.arm.com/docs/100067/latest/compiler-specific-intrinsics/__breakpoint-intrinsic
-#[cfg(any(target_arch = "arm", doc))]
-#[doc(cfg(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(bkpt, VAL = 0))]
 #[inline(always)]
 #[rustc_legacy_const_generics(0)]

library/stdarch/crates/core_arch/src/arm/ex.rs

@@ -8,6 +8,7 @@
 #[cfg(any(
     all(target_feature = "v6k", not(target_feature = "mclass")), // excludes v6-M
     all(target_feature = "v7", target_feature = "mclass"), // v7-M
+    doc
 ))]
 pub unsafe fn __clrex() {
     extern "C" {
@@ -21,9 +22,10 @@ pub unsafe fn __clrex() {
 /// Executes a exclusive LDR instruction for 8 bit value.
 // Supported: v6K, v7-M, v7-A, v7-R
 // Not supported: v5, v6, v6-M
-#[cfg(
+#[cfg(any(
     target_feature = "v6k", // includes v7-M but excludes v6-M
-)]
+    doc
+))]
 pub unsafe fn __ldrexb(p: *const u8) -> u8 {
     extern "C" {
         #[link_name = "llvm.arm.ldrex.p0i8"]
@@ -36,9 +38,10 @@ pub unsafe fn __ldrexb(p: *const u8) -> u8 {
 /// Executes a exclusive LDR instruction for 16 bit value.
 // Supported: v6K, v7-M, v7-A, v7-R, v8
 // Not supported: v5, v6, v6-M
-#[cfg(
+#[cfg(any(
     target_feature = "v6k", // includes v7-M but excludes v6-M
-)]
+    doc
+))]
 pub unsafe fn __ldrexh(p: *const u16) -> u16 {
     extern "C" {
         #[link_name = "llvm.arm.ldrex.p0i16"]
@@ -54,6 +57,7 @@ pub unsafe fn __ldrexh(p: *const u16) -> u16 {
 #[cfg(any(
     all(target_feature = "v6", not(target_feature = "mclass")), // excludes v6-M
     all(target_feature = "v7", target_feature = "mclass"), // v7-M
+    doc
 ))]
 pub unsafe fn __ldrex(p: *const u32) -> u32 {
     extern "C" {
@@ -69,9 +73,10 @@ pub unsafe fn __ldrex(p: *const u32) -> u32 {
 /// Returns `0` if the operation succeeded, or `1` if it failed
 // supported: v6K, v7-M, v7-A, v7-R
 // Not supported: v5, v6, v6-M
-#[cfg(
+#[cfg(any(
     target_feature = "v6k", // includes v7-M but excludes v6-M
-)]
+    doc
+))]
 pub unsafe fn __strexb(value: u32, addr: *mut u8) -> u32 {
     extern "C" {
         #[link_name = "llvm.arm.strex.p0i8"]
@@ -86,9 +91,11 @@ pub unsafe fn __strexb(value: u32, addr: *mut u8) -> u32 {
 /// Returns `0` if the operation succeeded, or `1` if it failed
 // Supported: v6K, v7-M, v7-A, v7-R, v8
 // Not supported: v5, v6, v6-M
-#[cfg(
+#[cfg(target_feature = "aarch64")]
+#[cfg(any(
     target_feature = "v6k", // includes v7-M but excludes v6-M
-)]
+    doc
+))]
 pub unsafe fn __strexh(value: u16, addr: *mut u16) -> u32 {
     extern "C" {
         #[link_name = "llvm.arm.strex.p0i16"]
@@ -106,6 +113,7 @@ pub unsafe fn __strexh(value: u16, addr: *mut u16) -> u32 {
 #[cfg(any(
     all(target_feature = "v6", not(target_feature = "mclass")), // excludes v6-M
     all(target_feature = "v7", target_feature = "mclass"), // v7-M
+    doc
 ))]
 pub unsafe fn __strex(value: u32, addr: *mut u32) -> u32 {
     extern "C" {

library/stdarch/crates/core_arch/src/arm/mod.rs

@@ -5,40 +5,81 @@
 //!
 //! [arm_ref]: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0073a/IHI0073A_arm_neon_intrinsics_ref.pdf
 //! [arm_dat]: https://developer.arm.com/technologies/neon/intrinsics
-#![allow(non_camel_case_types)]
 
 mod armclang;
-
 pub use self::armclang::*;
 
 mod v6;
 pub use self::v6::*;
 
-#[cfg(any(target_arch = "aarch64", target_feature = "v7"))]
+// Supported arches: 6, 7-M. See Section 10.1 of ACLE (e.g. SSAT)
+#[cfg(any(target_feature = "v6", doc))]
+mod sat;
+
+#[cfg(any(target_feature = "v6", doc))]
+pub use self::sat::*;
+
+// Supported arches: 5TE, 7E-M. See Section 10.1 of ACLE (e.g. QADD)
+// We also include the A profile even though DSP is deprecated on that profile as of ACLE 2.0 (see
+// section 5.4.7)
+// Here we workaround the difference between LLVM's +dsp and ACLE's __ARM_FEATURE_DSP by gating on
+// '+v5te' rather than on '+dsp'
+#[cfg(any(
+    // >= v5TE but excludes v7-M
+    all(target_feature = "v5te", not(target_feature = "mclass")),
+    // v7E-M
+    all(target_feature = "mclass", target_feature = "dsp"),
+    doc,
+))]
+pub mod dsp;
+
+#[cfg(any(
+    // >= v5TE but excludes v7-M
+    all(target_feature = "v5te", not(target_feature = "mclass")),
+    // v7E-M
+    all(target_feature = "mclass", target_feature = "dsp"),
+    doc,
+))]
+pub use self::dsp::*;
+
+// Deprecated in ACLE 2.0 for the A profile but fully supported on the M and R profiles, says
+// Section 5.4.9 of ACLE. We'll expose these for the A profile even if deprecated
+#[cfg(any(
+    // v7-A, v7-R
+    all(target_feature = "v6", not(target_feature = "mclass")),
+    // v7E-M
+    all(target_feature = "mclass", target_feature = "dsp"),
+    doc,
+))]
+mod simd32;
+
+#[cfg(any(
+    // v7-A, v7-R
+    all(target_feature = "v6", not(target_feature = "mclass")),
+    // v7E-M
+    all(target_feature = "mclass", target_feature = "dsp"),
+    doc,
+))]
+pub use self::simd32::*;
+
+#[cfg(any(target_feature = "v7", doc))]
 mod v7;
-#[cfg(any(target_arch = "aarch64", target_feature = "v7"))]
+#[cfg(any(target_feature = "v7", doc))]
 pub use self::v7::*;
 
-#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
-mod neon;
-#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
-pub use self::neon::*;
+mod ex;
+pub use self::ex::*;
 
-#[cfg(any(target_arch = "aarch64", target_feature = "v7"))]
-mod crc;
-#[cfg(any(target_arch = "aarch64", target_feature = "v7"))]
-pub use self::crc::*;
-
-#[cfg(any(target_arch = "aarch64", target_feature = "v7"))]
-mod crypto;
-#[cfg(any(target_arch = "aarch64", target_feature = "v7"))]
-pub use self::crypto::*;
-
-pub use crate::core_arch::acle::*;
+pub use crate::core_arch::arm_shared::*;
 
 #[cfg(test)]
 use stdarch_test::assert_instr;
 
+#[cfg(any(target_feature = "v7", doc))]
+pub(crate) mod neon;
+#[cfg(any(target_feature = "v7", doc))]
+pub use neon::*;
+
 /// Generates the trap instruction `UDF`
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(udf))]
@@ -47,6 +88,26 @@ pub unsafe fn udf() -> ! {
     crate::intrinsics::abort()
 }
 
-#[cfg(test)]
-#[cfg(any(target_arch = "aarch64", target_feature = "v7"))]
-pub(crate) mod test_support;
+/// Generates a DBG instruction.
+///
+/// This provides a hint to debugging and related systems. The argument must be
+/// a constant integer from 0 to 15 inclusive. See implementation documentation
+/// for the effect (if any) of this instruction and the meaning of the
+/// argument. This is available only when compliling for AArch32.
+// Section 10.1 of ACLE says that the supported arches are: 7, 7-M
+// "The DBG hint instruction is added in ARMv7. It is UNDEFINED in the ARMv6 base architecture, and
+// executes as a NOP instruction in ARMv6K and ARMv6T2." - ARM Architecture Reference Manual ARMv7-A
+// and ARMv7-R edition (ARM DDI 0406C.c) sections D12.4.1 "ARM instruction set support" and D12.4.2
+// "Thumb instruction set support"
+#[cfg(any(target_feature = "v7", doc))]
+#[inline(always)]
+#[rustc_legacy_const_generics(0)]
+pub unsafe fn __dbg<const IMM4: i32>() {
+    static_assert_imm4!(IMM4);
+    dbg(IMM4);
+}
+
+extern "C" {
+    #[link_name = "llvm.arm.dbg"]
+    fn dbg(_: i32);
+}

library/stdarch/crates/core_arch/src/arm/simd32.rs

@@ -65,7 +65,7 @@
 #[cfg(test)]
 use stdarch_test::assert_instr;
 
-use crate::{core_arch::acle::dsp::int16x2_t, mem::transmute};
+use crate::{core_arch::arm::dsp::int16x2_t, mem::transmute};
 
 types! {
     /// ARM-specific 32-bit wide vector of four packed `i8`.

library/stdarch/crates/core_arch/src/arm_shared/crc.rs

@@ -79,7 +79,7 @@ pub unsafe fn __crc32cw(crc: u32, data: u32) -> u32 {
 
 #[cfg(test)]
 mod tests {
-    use crate::core_arch::{arm::*, simd::*};
+    use crate::core_arch::{arm_shared::*, simd::*};
     use std::mem;
     use stdarch_test::simd_test;
 

library/stdarch/crates/core_arch/src/arm_shared/crypto.rs

@@ -1,4 +1,4 @@
-use crate::core_arch::arm::{uint32x4_t, uint8x16_t};
+use crate::core_arch::arm_shared::{uint32x4_t, uint8x16_t};
 
 #[allow(improper_ctypes)]
 extern "C" {
@@ -191,7 +191,8 @@ pub unsafe fn vsha256su1q_u32(
 
 #[cfg(test)]
 mod tests {
-    use crate::core_arch::{arm::*, simd::*};
+    use super::*;
+    use crate::core_arch::{arm_shared::*, simd::*};
     use std::mem;
     use stdarch_test::simd_test;
 

library/stdarch/crates/core_arch/src/arm_shared/hints.rs

@@ -9,7 +9,7 @@
 /// low-power state until one of a number of asynchronous events occurs.
 // Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M
 // LLVM says "instruction requires: armv6k"
-#[cfg(any(target_feature = "v6", target_arch = "aarch64"))]
+#[cfg(any(target_feature = "v6", target_arch = "aarch64", doc))]
 #[inline(always)]
 pub unsafe fn __wfi() {
     hint(HINT_WFI);
@@ -22,7 +22,7 @@ pub unsafe fn __wfi() {
 /// another processor.
 // Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M
 // LLVM says "instruction requires: armv6k"
-#[cfg(any(target_feature = "v6", target_arch = "aarch64"))]
+#[cfg(any(target_feature = "v6", target_arch = "aarch64", doc))]
 #[inline(always)]
 pub unsafe fn __wfe() {
     hint(HINT_WFE);
@@ -34,7 +34,7 @@ pub unsafe fn __wfe() {
 /// system. It is a NOP on a uniprocessor system.
 // Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M, 7-M
 // LLVM says "instruction requires: armv6k"
-#[cfg(any(target_feature = "v6", target_arch = "aarch64"))]
+#[cfg(any(target_feature = "v6", target_arch = "aarch64", doc))]
 #[inline(always)]
 pub unsafe fn __sev() {
     hint(HINT_SEV);
@@ -49,6 +49,7 @@ pub unsafe fn __sev() {
 #[cfg(any(
     target_feature = "v8", // 32-bit ARMv8
     target_arch = "aarch64", // AArch64
+    doc,
 ))]
 #[inline(always)]
 pub unsafe fn __sevl() {
@@ -62,33 +63,12 @@ pub unsafe fn __sevl() {
 /// improve overall system performance.
 // Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M
 // LLVM says "instruction requires: armv6k"
-#[cfg(any(target_feature = "v6", target_arch = "aarch64"))]
+#[cfg(any(target_feature = "v6", target_arch = "aarch64", doc))]
 #[inline(always)]
 pub unsafe fn __yield() {
     hint(HINT_YIELD);
 }
 
-/// Generates a DBG instruction.
-///
-/// This provides a hint to debugging and related systems. The argument must be
-/// a constant integer from 0 to 15 inclusive. See implementation documentation
-/// for the effect (if any) of this instruction and the meaning of the
-/// argument. This is available only when compliling for AArch32.
-// Section 10.1 of ACLE says that the supported arches are: 7, 7-M
-// "The DBG hint instruction is added in ARMv7. It is UNDEFINED in the ARMv6 base architecture, and
-// executes as a NOP instruction in ARMv6K and ARMv6T2." - ARM Architecture Reference Manual ARMv7-A
-// and ARMv7-R edition (ARM DDI 0406C.c) sections D12.4.1 "ARM instruction set support" and D12.4.2
-// "Thumb instruction set support"
-#[cfg(target_feature = "v7")]
-#[cfg(any(target_arch = "arm", doc))]
-#[doc(cfg(target_arch = "arm"))]
-#[inline(always)]
-#[rustc_legacy_const_generics(0)]
-pub unsafe fn __dbg<const IMM4: i32>() {
-    static_assert_imm4!(IMM4);
-    dbg(IMM4);
-}
-
 /// Generates an unspecified no-op instruction.
 ///
 /// Note that not all architectures provide a distinguished NOP instruction. On
@@ -104,10 +84,6 @@ extern "C" {
     #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.hint")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.hint")]
     fn hint(_: i32);
-
-    #[cfg(target_arch = "arm")]
-    #[link_name = "llvm.arm.dbg"]
-    fn dbg(_: i32);
 }
 
 // from LLVM 7.0.1's lib/Target/ARM/{ARMInstrThumb,ARMInstrInfo,ARMInstrThumb2}.td

library/stdarch/crates/core_arch/src/arm_shared/mod.rs

@@ -47,6 +47,9 @@
 //!
 //! - [ACLE Q2 2018](https://developer.arm.com/docs/101028/latest)
 
+// Only for 'neon' submodule
+#![allow(non_camel_case_types)]
+
 // 8, 7 and 6-M are supported via dedicated instructions like DMB. All other arches are supported
 // via CP15 instructions. See Section 10.1 of ACLE
 mod barrier;
@@ -54,70 +57,29 @@ mod barrier;
 pub use self::barrier::*;
 
 mod hints;
-
 pub use self::hints::*;
 
 mod registers;
-
 pub use self::registers::*;
 
-mod ex;
+#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+mod crc;
+#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+pub use crc::*;
 
-pub use self::ex::*;
+#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+mod crypto;
+#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+pub use self::crypto::*;
 
-// Supported arches: 5TE, 7E-M. See Section 10.1 of ACLE (e.g. QADD)
-// We also include the A profile even though DSP is deprecated on that profile as of ACLE 2.0 (see
-// section 5.4.7)
-// Here we workaround the difference between LLVM's +dsp and ACLE's __ARM_FEATURE_DSP by gating on
-// '+v5te' rather than on '+dsp'
-#[cfg(all(
-    not(target_arch = "aarch64"),
-    any(
-        // >= v5TE but excludes v7-M
-        all(target_feature = "v5te", not(target_feature = "mclass")),
-        // v7E-M
-        all(target_feature = "mclass", target_feature = "dsp"),
-    )
-))]
-mod dsp;
+#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+pub(crate) mod neon;
+#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+pub use self::neon::*;
 
-#[cfg(all(
-    not(target_arch = "aarch64"),
-    any(
-        all(target_feature = "v5te", not(target_feature = "mclass")),
-        all(target_feature = "mclass", target_feature = "dsp"),
-    )
-))]
-pub use self::dsp::*;
-
-// Supported arches: 6, 7-M. See Section 10.1 of ACLE (e.g. SSAT)
-#[cfg(all(not(target_arch = "aarch64"), target_feature = "v6",))]
-mod sat;
-
-#[cfg(all(not(target_arch = "aarch64"), target_feature = "v6",))]
-pub use self::sat::*;
-
-// Deprecated in ACLE 2.0 for the A profile but fully supported on the M and R profiles, says
-// Section 5.4.9 of ACLE. We'll expose these for the A profile even if deprecated
-#[cfg(all(
-    not(target_arch = "aarch64"),
-    any(
-        // v7-A, v7-R
-        all(target_feature = "v6", not(target_feature = "mclass")),
-        // v7E-M
-        all(target_feature = "mclass", target_feature = "dsp")
-    )
-))]
-mod simd32;
-
-#[cfg(all(
-    not(target_arch = "aarch64"),
-    any(
-        all(target_feature = "v6", not(target_feature = "mclass")),
-        all(target_feature = "mclass", target_feature = "dsp")
-    )
-))]
-pub use self::simd32::*;
+#[cfg(test)]
+#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+pub(crate) mod test_support;
 
 mod sealed {
     pub trait Dmb {

library/stdarch/crates/core_arch/src/arm_shared/test_support.rs

@@ -1,4 +1,10 @@
-use crate::core_arch::{arm::*, simd::*};
+#[cfg(target_arch = "arm")]
+use crate::core_arch::arm::*;
+
+#[cfg(target_arch = "aarch64")]
+use crate::core_arch::aarch64::*;
+
+use crate::core_arch::simd::*;
 use std::{i16, i32, i8, mem::transmute, u16, u32, u8, vec::Vec};
 
 macro_rules! V_u8 {

library/stdarch/crates/core_arch/src/mod.rs

@@ -5,7 +5,7 @@
 mod macros;
 
 #[cfg(any(target_arch = "arm", target_arch = "aarch64", doc))]
-mod acle;
+mod arm_shared;
 
 mod simd;
 
@@ -53,7 +53,7 @@ pub mod arch {
     #[doc(cfg(target_arch = "aarch64"))]
     #[unstable(feature = "stdsimd", issue = "27731")]
     pub mod aarch64 {
-        pub use crate::core_arch::{aarch64::*, arm::*};
+        pub use crate::core_arch::aarch64::*;
     }
 
     /// Platform-specific intrinsics for the `wasm32` platform.
@@ -234,8 +234,8 @@ mod x86_64;
 #[cfg(any(target_arch = "aarch64", doc))]
 #[doc(cfg(target_arch = "aarch64"))]
 mod aarch64;
-#[cfg(any(target_arch = "arm", target_arch = "aarch64", doc))]
-#[doc(cfg(any(target_arch = "arm", target_arch = "aarch64")))]
+#[cfg(any(target_arch = "arm", doc))]
+#[doc(cfg(any(target_arch = "arm")))]
 mod arm;
 
 #[cfg(any(target_arch = "wasm32", doc))]

library/stdarch/crates/stdarch-gen/src/main.rs

@@ -2253,7 +2253,7 @@ mod test {
 
     let arm_out_path: PathBuf = PathBuf::from(env::var("OUT_DIR").unwrap())
         .join("src")
-        .join("arm")
+        .join("arm_shared")
         .join("neon");
     std::fs::create_dir_all(&arm_out_path)?;
 

library/stdarch/crates/stdarch-test/src/lib.rs

@@ -121,7 +121,7 @@ pub fn assert(shim_addr: usize, fnname: &str, expected: &str) {
                 // in some cases exceed the limit.
                 "cvtpi2ps" => 25,
 
-                // core_arch/src/acle/simd32
+                // core_arch/src/arm_shared/simd32
                 "usad8" => 27,
                 "qadd8" | "qsub8" | "sadd8" | "sel" | "shadd8" | "shsub8" | "usub8" | "ssub8" => 29,
 

library/stdarch/crates/stdarch-verify/src/lib.rs

@@ -224,6 +224,7 @@ fn to_type(t: &syn::Type) -> proc_macro2::TokenStream {
             "int64x1_t" => quote! { &I64X1 },
             "int64x2_t" => quote! { &I64X2 },
             "uint8x8_t" => quote! { &U8X8 },
+            "uint8x4_t" => quote! { &U8X4 },
             "uint8x8x2_t" => quote! { &U8X8X2 },
             "uint8x16x2_t" => quote! { &U8X16X2 },
             "uint8x16x3_t" => quote! { &U8X16X3 },

library/stdarch/crates/stdarch-verify/tests/arm.rs

@@ -149,6 +149,7 @@ static U8X16X2: Type = Type::U(8, 16, 2);
 static U8X16X3: Type = Type::U(8, 16, 3);
 static U8X16X4: Type = Type::U(8, 16, 4);
 static U8X8: Type = Type::U(8, 8, 1);
+static U8X4: Type = Type::U(8, 4, 1);
 static U8X8X2: Type = Type::U(8, 8, 2);
 static U8X8X3: Type = Type::U(8, 8, 3);
 static U8X8X4: Type = Type::U(8, 8, 4);
@@ -371,6 +372,90 @@ fn verify_all_signatures() {
                 "vsriq_n_p8",
                 "vsri_n_p16",
                 "vsriq_n_p16",
+                "__smulbb",
+                "__smultb",
+                "__smulbt",
+                "__smultt",
+                "__smulwb",
+                "__smulwt",
+                "__qadd",
+                "__qsub",
+                "__qdbl",
+                "__smlabb",
+                "__smlabt",
+                "__smlatb",
+                "__smlatt",
+                "__smlawb",
+                "__smlawt",
+                "__qadd8",
+                "__qsub8",
+                "__qsub16",
+                "__qadd16",
+                "__qasx",
+                "__qsax",
+                "__sadd16",
+                "__sadd8",
+                "__smlad",
+                "__smlsd",
+                "__sasx",
+                "__sel",
+                "__shadd8",
+                "__shadd16",
+                "__shsub8",
+                "__usub8",
+                "__ssub8",
+                "__shsub16",
+                "__smuad",
+                "__smuadx",
+                "__smusd",
+                "__smusdx",
+                "__usad8",
+                "__usada8",
+                "vld1_s8",
+                "vld1q_s8",
+                "vld1q_s8",
+                "vld1_s16",
+                "vld1q_s16",
+                "vld1_s32",
+                "vld1q_s32",
+                "vld1_s64",
+                "vld1q_s64",
+                "vld1_u8",
+                "vld1q_u8",
+                "vld1_u16",
+                "vld1q_u16",
+                "vld1_u32",
+                "vld1q_u32",
+                "vld1_u64",
+                "vld1q_u64",
+                "vld1_p8",
+                "vld1q_p8",
+                "vld1_p16",
+                "vld1q_p16",
+                "vld1_f32",
+                "vld1q_f32",
+                "vld1_f64",
+                "vld1q_f64",
+                "vpadal_s8",
+                "vpadal_s16",
+                "vpadal_s32",
+                "vpadalq_s8",
+                "vpadalq_s16",
+                "vpadalq_s32",
+                "vpadal_u8",
+                "vpadal_u16",
+                "vpadal_u32",
+                "vpadalq_u8",
+                "vpadalq_u16",
+                "vpadalq_u32",
+                "__ldrex",
+                "__strex",
+                "__ldrexb",
+                "__strexb",
+                "__ldrexh",
+                "__strexh",
+                "__clrex",
+                "__dbg",
             ];
             if !skip.contains(&rust.name) {
                 println!(
@@ -402,6 +487,7 @@ fn verify_all_signatures() {
             "vreinterpret_p64_s64",
             "vreinterpret_f32_p64",
             "vreinterpretq_f32_p64",
+            "__dbg",
         ];
         let arm = match map.get(rust.name) {
             Some(i) => i,
@@ -412,11 +498,13 @@ fn verify_all_signatures() {
                 // TODO: we still need to verify these intrinsics or find a
                 // reference for them, need to figure out where though!
                 if !rust.file.ends_with("dsp.rs\"")
+                    && !rust.file.ends_with("simd32.rs\"")
                     && !rust.file.ends_with("cmsis.rs\"")
                     && !rust.file.ends_with("v6.rs\"")
                     && !rust.file.ends_with("v7.rs\"")
                     && !rust.file.ends_with("v8.rs\"")
                     && !rust.file.ends_with("tme.rs\"")
+                    && !rust.file.ends_with("ex.rs\"")
                     && !skip_intrinsic_verify.contains(&rust.name)
                 {
                     println!(