make some const generic immediates better match their width or the intel intrinsics guide
This commit is contained in:
Rémy Rakic
Amanieu d'Antras
parent
569de84ba2
commit
4faf16f979
2 changed files with 42 additions and 42 deletions
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@ -787,66 +787,66 @@ pub const _CMP_TRUE_US: i32 = 0x1f;
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/// Compares packed double-precision (64-bit) floating-point
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/// elements in `a` and `b` based on the comparison operand
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/// specified by `imm8`.
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/// specified by `IMM5`.
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///
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_pd)
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#[inline]
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#[target_feature(enable = "avx,sse2")]
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#[cfg_attr(test, assert_instr(vcmpeqpd, IMM8 = 0))] // TODO Validate vcmppd
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#[cfg_attr(test, assert_instr(vcmpeqpd, IMM5 = 0))] // TODO Validate vcmppd
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#[rustc_legacy_const_generics(2)]
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#[stable(feature = "simd_x86", since = "1.27.0")]
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pub unsafe fn _mm_cmp_pd<const IMM8: i32>(a: __m128d, b: __m128d) -> __m128d {
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static_assert_imm5!(IMM8);
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vcmppd(a, b, IMM8 as i8)
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pub unsafe fn _mm_cmp_pd<const IMM5: i32>(a: __m128d, b: __m128d) -> __m128d {
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static_assert_imm5!(IMM5);
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vcmppd(a, b, IMM5 as i8)
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}
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/// Compares packed double-precision (64-bit) floating-point
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/// elements in `a` and `b` based on the comparison operand
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/// specified by `imm8`.
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/// specified by `IMM5`.
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///
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cmp_pd)
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#[inline]
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#[target_feature(enable = "avx")]
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#[cfg_attr(test, assert_instr(vcmpeqpd, IMM8 = 0))] // TODO Validate vcmppd
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#[cfg_attr(test, assert_instr(vcmpeqpd, IMM5 = 0))] // TODO Validate vcmppd
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#[rustc_legacy_const_generics(2)]
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#[stable(feature = "simd_x86", since = "1.27.0")]
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pub unsafe fn _mm256_cmp_pd<const IMM8: i32>(a: __m256d, b: __m256d) -> __m256d {
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static_assert_imm5!(IMM8);
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vcmppd256(a, b, IMM8 as u8)
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pub unsafe fn _mm256_cmp_pd<const IMM5: i32>(a: __m256d, b: __m256d) -> __m256d {
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static_assert_imm5!(IMM5);
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vcmppd256(a, b, IMM5 as u8)
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}
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/// Compares packed single-precision (32-bit) floating-point
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/// elements in `a` and `b` based on the comparison operand
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/// specified by `imm8`.
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/// specified by `IMM5`.
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///
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_ps)
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#[inline]
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#[target_feature(enable = "avx,sse")]
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#[cfg_attr(test, assert_instr(vcmpeqps, IMM8 = 0))] // TODO Validate vcmpps
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#[cfg_attr(test, assert_instr(vcmpeqps, IMM5 = 0))] // TODO Validate vcmpps
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#[rustc_legacy_const_generics(2)]
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#[stable(feature = "simd_x86", since = "1.27.0")]
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pub unsafe fn _mm_cmp_ps<const IMM8: i32>(a: __m128, b: __m128) -> __m128 {
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static_assert_imm5!(IMM8);
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vcmpps(a, b, IMM8 as i8)
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pub unsafe fn _mm_cmp_ps<const IMM5: i32>(a: __m128, b: __m128) -> __m128 {
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static_assert_imm5!(IMM5);
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vcmpps(a, b, IMM5 as i8)
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}
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/// Compares packed single-precision (32-bit) floating-point
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/// elements in `a` and `b` based on the comparison operand
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/// specified by `imm8`.
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/// specified by `IMM5`.
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///
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cmp_ps)
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#[inline]
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#[target_feature(enable = "avx")]
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#[cfg_attr(test, assert_instr(vcmpeqps, IMM8 = 0))] // TODO Validate vcmpps
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#[cfg_attr(test, assert_instr(vcmpeqps, IMM5 = 0))] // TODO Validate vcmpps
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#[rustc_legacy_const_generics(2)]
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#[stable(feature = "simd_x86", since = "1.27.0")]
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pub unsafe fn _mm256_cmp_ps<const IMM8: i32>(a: __m256, b: __m256) -> __m256 {
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static_assert_imm5!(IMM8);
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vcmpps256(a, b, IMM8 as u8)
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pub unsafe fn _mm256_cmp_ps<const IMM5: i32>(a: __m256, b: __m256) -> __m256 {
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static_assert_imm5!(IMM5);
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vcmpps256(a, b, IMM5 as u8)
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}
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/// Compares the lower double-precision (64-bit) floating-point element in
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/// `a` and `b` based on the comparison operand specified by `imm8`,
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/// `a` and `b` based on the comparison operand specified by `IMM5`,
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/// store the result in the lower element of returned vector,
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/// and copies the upper element from `a` to the upper element of returned
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/// vector.
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@ -854,16 +854,16 @@ pub unsafe fn _mm256_cmp_ps<const IMM8: i32>(a: __m256, b: __m256) -> __m256 {
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_sd)
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#[inline]
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#[target_feature(enable = "avx,sse2")]
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#[cfg_attr(test, assert_instr(vcmpeqsd, IMM8 = 0))] // TODO Validate vcmpsd
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#[cfg_attr(test, assert_instr(vcmpeqsd, IMM5 = 0))] // TODO Validate vcmpsd
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#[rustc_legacy_const_generics(2)]
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#[stable(feature = "simd_x86", since = "1.27.0")]
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pub unsafe fn _mm_cmp_sd<const IMM8: i32>(a: __m128d, b: __m128d) -> __m128d {
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static_assert_imm5!(IMM8);
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vcmpsd(a, b, IMM8 as i8)
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pub unsafe fn _mm_cmp_sd<const IMM5: i32>(a: __m128d, b: __m128d) -> __m128d {
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static_assert_imm5!(IMM5);
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vcmpsd(a, b, IMM5 as i8)
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}
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/// Compares the lower single-precision (32-bit) floating-point element in
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/// `a` and `b` based on the comparison operand specified by `imm8`,
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/// `a` and `b` based on the comparison operand specified by `IMM5`,
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/// store the result in the lower element of returned vector,
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/// and copies the upper 3 packed elements from `a` to the upper elements of
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/// returned vector.
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@ -871,12 +871,12 @@ pub unsafe fn _mm_cmp_sd<const IMM8: i32>(a: __m128d, b: __m128d) -> __m128d {
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_ss)
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#[inline]
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#[target_feature(enable = "avx,sse")]
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#[cfg_attr(test, assert_instr(vcmpeqss, IMM8 = 0))] // TODO Validate vcmpss
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#[cfg_attr(test, assert_instr(vcmpeqss, IMM5 = 0))] // TODO Validate vcmpss
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#[rustc_legacy_const_generics(2)]
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#[stable(feature = "simd_x86", since = "1.27.0")]
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pub unsafe fn _mm_cmp_ss<const IMM8: i32>(a: __m128, b: __m128) -> __m128 {
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static_assert_imm5!(IMM8);
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vcmpss(a, b, IMM8 as i8)
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pub unsafe fn _mm_cmp_ss<const IMM5: i32>(a: __m128, b: __m128) -> __m128 {
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static_assert_imm5!(IMM5);
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vcmpss(a, b, IMM5 as i8)
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}
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/// Converts packed 32-bit integers in `a` to packed double-precision (64-bit)
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@ -3734,7 +3734,7 @@ pub unsafe fn _mm256_xor_si256(a: __m256i, b: __m256i) -> __m256i {
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transmute(simd_xor(a.as_i64x4(), b.as_i64x4()))
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}
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/// Extracts an 8-bit integer from `a`, selected with `imm8`. Returns a 32-bit
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/// Extracts an 8-bit integer from `a`, selected with `INDEX`. Returns a 32-bit
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/// integer containing the zero-extended integer data.
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///
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/// See [LLVM commit D20468](https://reviews.llvm.org/D20468).
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@ -3745,12 +3745,12 @@ pub unsafe fn _mm256_xor_si256(a: __m256i, b: __m256i) -> __m256i {
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// This intrinsic has no corresponding instruction.
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#[rustc_legacy_const_generics(1)]
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#[stable(feature = "simd_x86", since = "1.27.0")]
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pub unsafe fn _mm256_extract_epi8<const IMM8: i32>(a: __m256i) -> i32 {
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static_assert_imm5!(IMM8);
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simd_extract::<_, u8>(a.as_u8x32(), IMM8 as u32) as i32
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pub unsafe fn _mm256_extract_epi8<const INDEX: i32>(a: __m256i) -> i32 {
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static_assert_imm5!(INDEX);
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simd_extract::<_, u8>(a.as_u8x32(), INDEX as u32) as i32
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}
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/// Extracts a 16-bit integer from `a`, selected with `imm8`. Returns a 32-bit
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/// Extracts a 16-bit integer from `a`, selected with `INDEX`. Returns a 32-bit
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/// integer containing the zero-extended integer data.
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///
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/// See [LLVM commit D20468](https://reviews.llvm.org/D20468).
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@ -3761,12 +3761,12 @@ pub unsafe fn _mm256_extract_epi8<const IMM8: i32>(a: __m256i) -> i32 {
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// This intrinsic has no corresponding instruction.
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#[rustc_legacy_const_generics(1)]
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#[stable(feature = "simd_x86", since = "1.27.0")]
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pub unsafe fn _mm256_extract_epi16<const IMM8: i32>(a: __m256i) -> i32 {
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static_assert_imm4!(IMM8);
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simd_extract::<_, u16>(a.as_u16x16(), IMM8 as u32) as i32
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pub unsafe fn _mm256_extract_epi16<const INDEX: i32>(a: __m256i) -> i32 {
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static_assert_imm4!(INDEX);
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simd_extract::<_, u16>(a.as_u16x16(), INDEX as u32) as i32
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}
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/// Extracts a 32-bit integer from `a`, selected with `imm8`.
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/// Extracts a 32-bit integer from `a`, selected with `INDEX`.
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///
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_extract_epi32)
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#[inline]
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@ -3774,9 +3774,9 @@ pub unsafe fn _mm256_extract_epi16<const IMM8: i32>(a: __m256i) -> i32 {
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// This intrinsic has no corresponding instruction.
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#[rustc_legacy_const_generics(1)]
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#[stable(feature = "simd_x86", since = "1.27.0")]
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pub unsafe fn _mm256_extract_epi32<const IMM8: i32>(a: __m256i) -> i32 {
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static_assert_imm3!(IMM8);
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simd_extract(a.as_i32x8(), IMM8 as u32)
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pub unsafe fn _mm256_extract_epi32<const INDEX: i32>(a: __m256i) -> i32 {
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static_assert_imm3!(INDEX);
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simd_extract(a.as_i32x8(), INDEX as u32)
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}
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/// Returns the first element of the input vector of `[4 x double]`.
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