From 5c0c7ac77c4f73a5e60f65771c57b2bbc73759ee Mon Sep 17 00:00:00 2001 From: Tsukasa OI Date: Fri, 11 Apr 2025 01:13:44 +0000 Subject: [PATCH] RISC-V: tidying: Make auxvec-based enablement a block Because this function will be no longer auxvec-only, this commit adds a comment to mark auxvec-based part. It *does not* add a comment to "base ISA" part because it may also use `riscv_hwprobe`-based results. --- library/stdarch/crates/std_detect/src/detect/os/linux/riscv.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/library/stdarch/crates/std_detect/src/detect/os/linux/riscv.rs b/library/stdarch/crates/std_detect/src/detect/os/linux/riscv.rs index 3e406b2c364e..6d77c89b4753 100644 --- a/library/stdarch/crates/std_detect/src/detect/os/linux/riscv.rs +++ b/library/stdarch/crates/std_detect/src/detect/os/linux/riscv.rs @@ -19,6 +19,7 @@ pub(crate) fn detect_features() -> cache::Initializer { } }; + // Use auxiliary vector to enable single-letter ISA extensions and Zicsr. // The values are part of the platform-specific [asm/hwcap.h][hwcap] // // [hwcap]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/riscv/include/uapi/asm/hwcap.h?h=v6.14