Rollup merge of #142481 - heiher:loong-asm-f16, r=Amanieu
Add `f16` inline asm support for LoongArch r? `````@Amanieu`````
This commit is contained in:
commit
5cce691c5a
3 changed files with 51 additions and 4 deletions
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@ -1021,6 +1021,15 @@ fn llvm_fixup_input<'ll, 'tcx>(
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) if element.primitive() == Primitive::Float(Float::F16) => {
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bx.bitcast(value, bx.type_vector(bx.type_i16(), count))
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}
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(LoongArch(LoongArchInlineAsmRegClass::freg), BackendRepr::Scalar(s))
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if s.primitive() == Primitive::Float(Float::F16) =>
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{
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// Smaller floats are always "NaN-boxed" inside larger floats on LoongArch.
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let value = bx.bitcast(value, bx.type_i16());
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let value = bx.zext(value, bx.type_i32());
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let value = bx.or(value, bx.const_u32(0xFFFF_0000));
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bx.bitcast(value, bx.type_f32())
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}
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(Mips(MipsInlineAsmRegClass::reg), BackendRepr::Scalar(s)) => {
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match s.primitive() {
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// MIPS only supports register-length arithmetics.
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@ -1178,6 +1187,13 @@ fn llvm_fixup_output<'ll, 'tcx>(
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) if element.primitive() == Primitive::Float(Float::F16) => {
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bx.bitcast(value, bx.type_vector(bx.type_f16(), count))
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}
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(LoongArch(LoongArchInlineAsmRegClass::freg), BackendRepr::Scalar(s))
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if s.primitive() == Primitive::Float(Float::F16) =>
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{
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let value = bx.bitcast(value, bx.type_i32());
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let value = bx.trunc(value, bx.type_i16());
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bx.bitcast(value, bx.type_f16())
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}
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(Mips(MipsInlineAsmRegClass::reg), BackendRepr::Scalar(s)) => {
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match s.primitive() {
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// MIPS only supports register-length arithmetics.
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@ -1318,6 +1334,11 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
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) if element.primitive() == Primitive::Float(Float::F16) => {
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cx.type_vector(cx.type_i16(), count)
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}
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(LoongArch(LoongArchInlineAsmRegClass::freg), BackendRepr::Scalar(s))
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if s.primitive() == Primitive::Float(Float::F16) =>
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{
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cx.type_f32()
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}
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(Mips(MipsInlineAsmRegClass::reg), BackendRepr::Scalar(s)) => {
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match s.primitive() {
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// MIPS only supports register-length arithmetics.
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@ -37,9 +37,11 @@ impl LoongArchInlineAsmRegClass {
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arch: InlineAsmArch,
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) -> &'static [(InlineAsmType, Option<Symbol>)] {
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match (self, arch) {
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(Self::reg, InlineAsmArch::LoongArch64) => types! { _: I8, I16, I32, I64, F32, F64; },
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(Self::reg, InlineAsmArch::LoongArch32) => types! { _: I8, I16, I32, F32; },
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(Self::freg, _) => types! { f: F32; d: F64; },
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(Self::reg, InlineAsmArch::LoongArch64) => {
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types! { _: I8, I16, I32, I64, F16, F32, F64; }
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}
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(Self::reg, InlineAsmArch::LoongArch32) => types! { _: I8, I16, I32, F16, F32; },
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(Self::freg, _) => types! { f: F16, F32; d: F64; },
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_ => unreachable!("unsupported register class"),
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}
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}
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@ -4,7 +4,7 @@
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//@ compile-flags: -Zmerge-functions=disabled
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//@ needs-llvm-components: loongarch
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#![feature(no_core)]
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#![feature(no_core, f16)]
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#![crate_type = "rlib"]
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#![no_core]
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#![allow(asm_sub_register, non_camel_case_types)]
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@ -69,6 +69,12 @@ check!(reg_i8, i8, reg, "move");
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// CHECK: #NO_APP
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check!(reg_i16, i16, reg, "move");
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// CHECK-LABEL: reg_f16:
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// CHECK: #APP
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// CHECK: move ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
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// CHECK: #NO_APP
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check!(reg_f16, f16, reg, "move");
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// CHECK-LABEL: reg_i32:
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// CHECK: #APP
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// CHECK: move ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
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@ -99,6 +105,12 @@ check!(reg_f64, f64, reg, "move");
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// CHECK: #NO_APP
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check!(reg_ptr, ptr, reg, "move");
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// CHECK-LABEL: freg_f16:
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// CHECK: #APP
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// CHECK: fmov.s $f{{[a-z0-9]+}}, $f{{[a-z0-9]+}}
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// CHECK: #NO_APP
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check!(freg_f16, f16, freg, "fmov.s");
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// CHECK-LABEL: freg_f32:
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// CHECK: #APP
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// CHECK: fmov.s $f{{[a-z0-9]+}}, $f{{[a-z0-9]+}}
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@ -123,6 +135,12 @@ check_reg!(r4_i8, i8, "$r4", "move");
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// CHECK: #NO_APP
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check_reg!(r4_i16, i16, "$r4", "move");
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// CHECK-LABEL: r4_f16:
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// CHECK: #APP
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// CHECK: move $a0, $a0
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// CHECK: #NO_APP
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check_reg!(r4_f16, f16, "$r4", "move");
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// CHECK-LABEL: r4_i32:
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// CHECK: #APP
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// CHECK: move $a0, $a0
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@ -153,6 +171,12 @@ check_reg!(r4_f64, f64, "$r4", "move");
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// CHECK: #NO_APP
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check_reg!(r4_ptr, ptr, "$r4", "move");
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// CHECK-LABEL: f0_f16:
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// CHECK: #APP
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// CHECK: fmov.s $f{{[a-z0-9]+}}, $f{{[a-z0-9]+}}
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// CHECK: #NO_APP
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check_reg!(f0_f16, f16, "$f0", "fmov.s");
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// CHECK-LABEL: f0_f32:
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// CHECK: #APP
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// CHECK: fmov.s $f{{[a-z0-9]+}}, $f{{[a-z0-9]+}}
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