From 669359530ec3dcfa5c1cc8d9afd80813a246f09b Mon Sep 17 00:00:00 2001 From: antoyo Date: Mon, 11 Oct 2021 10:56:08 -0400 Subject: [PATCH 001/356] Add missing cast and change some bitcasts to casts to avoid a gimple verification failure (#100) --- Readme.md | 2 ++ src/back/write.rs | 24 ++++++++++++------------ src/intrinsic/mod.rs | 32 +++++++++++++++++++++----------- 3 files changed, 35 insertions(+), 23 deletions(-) diff --git a/Readme.md b/Readme.md index 709d93c6edb0..1fcfb5f6e20a 100644 --- a/Readme.md +++ b/Readme.md @@ -111,6 +111,8 @@ Or add a breakpoint to `add_error` in gdb and print the line number using: p loc->m_line ``` +To get the `rustc` command to run in `gdb`, add the `--verbose` flag to `cargo build`. + ### How to use a custom-build rustc * Build the stage2 compiler (`rustup toolchain link debug-current build/x86_64-unknown-linux-gnu/stage2`). diff --git a/src/back/write.rs b/src/back/write.rs index c3e3847823d9..6cbce3c76dd2 100644 --- a/src/back/write.rs +++ b/src/back/write.rs @@ -1,4 +1,4 @@ -use std::fs; +use std::{env, fs}; use gccjit::OutputKind; use rustc_codegen_ssa::{CompiledModule, ModuleCodegen}; @@ -42,17 +42,17 @@ pub(crate) unsafe fn codegen(cgcx: &CodegenContext, _diag_han let _timer = cgcx .prof .generic_activity_with_arg("LLVM_module_codegen_emit_obj", &module.name[..]); - match &*module.name { - "std_example.7rcbfp3g-cgu.15" => { - println!("Dumping reproducer {}", module.name); - let _ = fs::create_dir("/tmp/reproducers"); - // FIXME(antoyo): segfault in dump_reproducer_to_file() might be caused by - // transmuting an rvalue to an lvalue. - // Segfault is actually in gcc::jit::reproducer::get_identifier_as_lvalue - context.dump_reproducer_to_file(&format!("/tmp/reproducers/{}.c", module.name)); - println!("Dumped reproducer {}", module.name); - }, - _ => (), + if env::var("CG_GCCJIT_DUMP_MODULE_NAMES").as_deref() == Ok("1") { + println!("Module {}", module.name); + } + if env::var("CG_GCCJIT_DUMP_MODULE").as_deref() == Ok(&module.name) { + println!("Dumping reproducer {}", module.name); + let _ = fs::create_dir("/tmp/reproducers"); + // FIXME(antoyo): segfault in dump_reproducer_to_file() might be caused by + // transmuting an rvalue to an lvalue. + // Segfault is actually in gcc::jit::reproducer::get_identifier_as_lvalue + context.dump_reproducer_to_file(&format!("/tmp/reproducers/{}.c", module.name)); + println!("Dumped reproducer {}", module.name); } context.compile_to_file(OutputKind::ObjectFile, obj_out.to_str().expect("path to str")); } diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index 375d422cb25c..1034eb75991e 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -525,7 +525,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let value = if result_type.is_signed(self.cx) { - self.context.new_bitcast(None, value, typ) + self.context.new_cast(None, value, typ) } else { value @@ -689,7 +689,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { }, }; - self.context.new_bitcast(None, result, result_type) + self.context.new_cast(None, result, result_type) } fn count_leading_zeroes(&self, width: u64, arg: RValue<'gcc>) -> RValue<'gcc> { @@ -740,6 +740,11 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let not_low = self.context.new_unary_op(None, UnaryOp::LogicalNegate, self.u64_type, low); let not_low_and_not_high = not_low & not_high; let index = not_high + not_low_and_not_high; + // NOTE: the following cast is necessary to avoid a GIMPLE verification failure in + // gcc. + // TODO(antoyo): do the correct verification in libgccjit to avoid an error at the + // compilation stage. + let index = self.context.new_cast(None, index, self.i32_type); let res = self.context.new_array_access(None, result, index); @@ -763,7 +768,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let arg = if result_type.is_signed(self.cx) { let new_type = result_type.to_unsigned(self.cx); - self.context.new_bitcast(None, arg, new_type) + self.context.new_cast(None, arg, new_type) } else { arg @@ -815,10 +820,15 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let not_high = self.context.new_unary_op(None, UnaryOp::LogicalNegate, self.u64_type, high); let not_low_and_not_high = not_low & not_high; let index = not_low + not_low_and_not_high; + // NOTE: the following cast is necessary to avoid a GIMPLE verification failure in + // gcc. + // TODO(antoyo): do the correct verification in libgccjit to avoid an error at the + // compilation stage. + let index = self.context.new_cast(None, index, self.i32_type); let res = self.context.new_array_access(None, result, index); - return self.context.new_bitcast(None, res, result_type); + return self.context.new_cast(None, res, result_type); } else { unimplemented!("count_trailing_zeroes for {:?}", arg_type); @@ -832,7 +842,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { arg }; let res = self.context.new_call(None, count_trailing_zeroes, &[arg]); - self.context.new_bitcast(None, res, result_type) + self.context.new_cast(None, res, result_type) } fn int_width(&self, typ: Type<'gcc>) -> i64 { @@ -846,7 +856,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let value = if result_type.is_signed(self.cx) { - self.context.new_bitcast(None, value, value_type) + self.context.new_cast(None, value, value_type) } else { value @@ -862,7 +872,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let low = self.context.new_cast(None, value, self.cx.ulonglong_type); let low = self.context.new_call(None, popcount, &[low]); let res = high + low; - return self.context.new_bitcast(None, res, result_type); + return self.context.new_cast(None, res, result_type); } // First step. @@ -887,7 +897,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let value = left + right; if value_type.is_u8(&self.cx) { - return self.context.new_bitcast(None, value, result_type); + return self.context.new_cast(None, value, result_type); } // Fourth step. @@ -898,7 +908,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let value = left + right; if value_type.is_u16(&self.cx) { - return self.context.new_bitcast(None, value, result_type); + return self.context.new_cast(None, value, result_type); } // Fifth step. @@ -909,7 +919,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let value = left + right; if value_type.is_u32(&self.cx) { - return self.context.new_bitcast(None, value, result_type); + return self.context.new_cast(None, value, result_type); } // Sixth step. @@ -919,7 +929,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let right = shifted & mask; let value = left + right; - self.context.new_bitcast(None, value, result_type) + self.context.new_cast(None, value, result_type) } // Algorithm from: https://blog.regehr.org/archives/1063 From 863cfb2d635188a42114a3f7578acbfa645f48ae Mon Sep 17 00:00:00 2001 From: Fisher Darling Date: Tue, 12 Oct 2021 09:39:14 -0700 Subject: [PATCH 002/356] Fix FIXME in `Builder::and` and `Builder::or` impls (#101) * impl bitwise and & or --- src/builder.rs | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index ac908418ee4b..0ccb38b8047a 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -605,22 +605,17 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn and(&mut self, a: RValue<'gcc>, mut b: RValue<'gcc>) -> RValue<'gcc> { - // FIXME(antoyo): hack by putting the result in a variable to workaround this bug: - // https://gcc.gnu.org/bugzilla//show_bug.cgi?id=95498 if a.get_type() != b.get_type() { b = self.context.new_cast(None, b, a.get_type()); } - let res = self.current_func().new_local(None, b.get_type(), "andResult"); - self.llbb().add_assignment(None, res, a & b); - res.to_rvalue() + a & b } - fn or(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { - // FIXME(antoyo): hack by putting the result in a variable to workaround this bug: - // https://gcc.gnu.org/bugzilla//show_bug.cgi?id=95498 - let res = self.current_func().new_local(None, b.get_type(), "orResult"); - self.llbb().add_assignment(None, res, a | b); - res.to_rvalue() + fn or(&mut self, a: RValue<'gcc>, mut b: RValue<'gcc>) -> RValue<'gcc> { + if a.get_type() != b.get_type() { + b = self.context.new_cast(None, b, a.get_type()); + } + a | b } fn xor(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { From 1d064f1741641ef66f8fe03965349a26b6939545 Mon Sep 17 00:00:00 2001 From: antoyo Date: Mon, 25 Oct 2021 17:48:15 -0400 Subject: [PATCH 003/356] Disable strict aliasing (#104) --- src/base.rs | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/base.rs b/src/base.rs index 9fd043607fc7..bb0f325faaa3 100644 --- a/src/base.rs +++ b/src/base.rs @@ -77,7 +77,10 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol) -> (Modul for arg in &tcx.sess.opts.cg.llvm_args { context.add_command_line_option(arg); } + // NOTE: an optimization (https://github.com/rust-lang/rustc_codegen_gcc/issues/53). context.add_command_line_option("-fno-semantic-interposition"); + // NOTE: Rust relies on LLVM not doing TBAA (https://github.com/rust-lang/unsafe-code-guidelines/issues/292). + context.add_command_line_option("-fno-strict-aliasing"); if env::var("CG_GCCJIT_DUMP_CODE").as_deref() == Ok("1") { context.set_dump_code_on_compile(true); } From fc8e79fea9d0eef9b8c945d86cd4313a5438cd19 Mon Sep 17 00:00:00 2001 From: antoyo Date: Sat, 30 Oct 2021 18:21:33 -0400 Subject: [PATCH 004/356] Sync from rust (#107) * Rebase fallout. * Move rustc_middle::middle::cstore to rustc_session. * Create more accurate debuginfo for vtables. Before this commit all vtables would have the same name "vtable" in debuginfo. Now they get a name that identifies the implementing type and the trait that is being implemented. * Remove alloc::prelude As per the libs team decision in #58935. Closes #58935 * Make hash_result an Option. * Properly check `target_features` not to trigger an assertion * Add LLVM CFI support to the Rust compiler This commit adds LLVM Control Flow Integrity (CFI) support to the Rust compiler. It initially provides forward-edge control flow protection for Rust-compiled code only by aggregating function pointers in groups identified by their number of arguments. Forward-edge control flow protection for C or C++ and Rust -compiled code "mixed binaries" (i.e., for when C or C++ and Rust -compiled code share the same virtual address space) will be provided in later work as part of this project by defining and using compatible type identifiers (see Type metadata in the design document in the tracking issue #89653). LLVM CFI can be enabled with -Zsanitizer=cfi and requires LTO (i.e., -Clto). * Update to nightly-2021-10-30 * Add deduplication of constant values as rustc relies on LLVM doing that Co-authored-by: Camille GILLOT Co-authored-by: Michael Woerister Co-authored-by: Amanieu d'Antras Co-authored-by: Yuki Okushi Co-authored-by: Ramon de C Valle --- example/alloc_example.rs | 4 ++-- rust-toolchain | 2 +- src/archive.rs | 5 ++--- src/asm.rs | 2 +- src/base.rs | 12 +++++++++--- src/builder.rs | 10 ++++++++++ src/consts.rs | 10 +++++++--- src/debuginfo.rs | 4 ++-- src/intrinsic/mod.rs | 5 +++++ src/lib.rs | 2 +- 10 files changed, 40 insertions(+), 16 deletions(-) diff --git a/example/alloc_example.rs b/example/alloc_example.rs index bc6dd007ba01..74ea7ec4ede6 100644 --- a/example/alloc_example.rs +++ b/example/alloc_example.rs @@ -1,10 +1,10 @@ -#![feature(start, box_syntax, core_intrinsics, alloc_prelude, alloc_error_handler)] +#![feature(start, box_syntax, core_intrinsics, alloc_error_handler)] #![no_std] extern crate alloc; extern crate alloc_system; -use alloc::prelude::v1::*; +use alloc::boxed::Box; use alloc_system::System; diff --git a/rust-toolchain b/rust-toolchain index d311a33f807b..3f315e099762 100644 --- a/rust-toolchain +++ b/rust-toolchain @@ -1 +1 @@ -nightly-2021-09-28 +nightly-2021-10-30 diff --git a/src/archive.rs b/src/archive.rs index d749d763402b..11dd6d49aa76 100644 --- a/src/archive.rs +++ b/src/archive.rs @@ -1,12 +1,11 @@ use std::fs::File; use std::path::{Path, PathBuf}; -use rustc_session::Session; use rustc_codegen_ssa::back::archive::ArchiveBuilder; +use rustc_session::Session; use rustc_data_structures::temp_dir::MaybeTempDir; -use rustc_middle::middle::cstore::DllImport; - +use rustc_session::cstore::DllImport; struct ArchiveConfig<'a> { sess: &'a Session, diff --git a/src/asm.rs b/src/asm.rs index 3b77097e9ad0..7c3ed3c5ee9d 100644 --- a/src/asm.rs +++ b/src/asm.rs @@ -118,7 +118,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { true } - fn codegen_inline_asm(&mut self, template: &[InlineAsmTemplatePiece], rust_operands: &[InlineAsmOperandRef<'tcx, Self>], options: InlineAsmOptions, _span: &[Span]) { + fn codegen_inline_asm(&mut self, template: &[InlineAsmTemplatePiece], rust_operands: &[InlineAsmOperandRef<'tcx, Self>], options: InlineAsmOptions, _span: &[Span], _instance: Instance<'_>) { let asm_arch = self.tcx.sess.asm_arch.unwrap(); let is_x86 = matches!(asm_arch, InlineAsmArch::X86 | InlineAsmArch::X86_64); let att_dialect = is_x86 && options.contains(InlineAsmOptions::ATT_SYNTAX); diff --git a/src/base.rs b/src/base.rs index bb0f325faaa3..e861658a0946 100644 --- a/src/base.rs +++ b/src/base.rs @@ -7,7 +7,6 @@ use gccjit::{ GlobalKind, }; use rustc_middle::dep_graph; -use rustc_middle::middle::cstore::EncodedMetadata; use rustc_middle::middle::exported_symbols; use rustc_middle::ty::TyCtxt; use rustc_middle::mir::mono::Linkage; @@ -15,6 +14,7 @@ use rustc_codegen_ssa::{ModuleCodegen, ModuleKind}; use rustc_codegen_ssa::base::maybe_create_entry_wrapper; use rustc_codegen_ssa::mono_item::MonoItemExt; use rustc_codegen_ssa::traits::DebugInfoMethods; +use rustc_metadata::EncodedMetadata; use rustc_session::config::DebugInfo; use rustc_span::Symbol; @@ -59,7 +59,13 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol) -> (Modul let start_time = Instant::now(); let dep_node = tcx.codegen_unit(cgu_name).codegen_dep_node(tcx); - let (module, _) = tcx.dep_graph.with_task(dep_node, tcx, cgu_name, module_codegen, dep_graph::hash_result); + let (module, _) = tcx.dep_graph.with_task( + dep_node, + tcx, + cgu_name, + module_codegen, + Some(dep_graph::hash_result), + ); let time_to_codegen = start_time.elapsed(); drop(prof_timer); @@ -152,7 +158,7 @@ pub fn write_compressed_metadata<'tcx>(tcx: TyCtxt<'tcx>, metadata: &EncodedMeta let context = &gcc_module.context; let mut compressed = rustc_metadata::METADATA_HEADER.to_vec(); - FrameEncoder::new(&mut compressed).write_all(&metadata.raw_data).unwrap(); + FrameEncoder::new(&mut compressed).write_all(&metadata.raw_data()).unwrap(); let name = exported_symbols::metadata_symbol_name(tcx); let typ = context.new_array_type(None, context.new_type::(), compressed.len() as i32); diff --git a/src/builder.rs b/src/builder.rs index 0ccb38b8047a..58b7f8cb8e97 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -910,6 +910,16 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { // TODO(antoyo) } + fn type_metadata(&mut self, _function: RValue<'gcc>, _typeid: String) { + // Unsupported. + } + + fn typeid_metadata(&mut self, _typeid: String) -> RValue<'gcc> { + // Unsupported. + self.context.new_rvalue_from_int(self.int_type, 0) + } + + fn store(&mut self, val: RValue<'gcc>, ptr: RValue<'gcc>, align: Align) -> RValue<'gcc> { self.store_with_flags(val, ptr, align, MemFlags::empty()) } diff --git a/src/consts.rs b/src/consts.rs index 205498acc318..628901269655 100644 --- a/src/consts.rs +++ b/src/consts.rs @@ -31,9 +31,13 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { impl<'gcc, 'tcx> StaticMethods for CodegenCx<'gcc, 'tcx> { fn static_addr_of(&self, cv: RValue<'gcc>, align: Align, kind: Option<&str>) -> RValue<'gcc> { - if let Some(global_value) = self.const_globals.borrow().get(&cv) { - // TODO(antoyo): upgrade alignment. - return *global_value; + // TODO(antoyo): implement a proper rvalue comparison in libgccjit instead of doing the + // following: + for (value, variable) in &*self.const_globals.borrow() { + if format!("{:?}", value) == format!("{:?}", cv) { + // TODO(antoyo): upgrade alignment. + return *variable; + } } let global_value = self.static_addr_of_mut(cv, align, kind); // TODO(antoyo): set global constant. diff --git a/src/debuginfo.rs b/src/debuginfo.rs index 4d3b4f04bade..31959fa19c58 100644 --- a/src/debuginfo.rs +++ b/src/debuginfo.rs @@ -2,7 +2,7 @@ use gccjit::RValue; use rustc_codegen_ssa::mir::debuginfo::{FunctionDebugContext, VariableKind}; use rustc_codegen_ssa::traits::{DebugInfoBuilderMethods, DebugInfoMethods}; use rustc_middle::mir; -use rustc_middle::ty::{Instance, Ty}; +use rustc_middle::ty::{Instance, PolyExistentialTraitRef, Ty}; use rustc_span::{SourceFile, Span, Symbol}; use rustc_target::abi::Size; use rustc_target::abi::call::FnAbi; @@ -31,7 +31,7 @@ impl<'a, 'gcc, 'tcx> DebugInfoBuilderMethods for Builder<'a, 'gcc, 'tcx> { } impl<'gcc, 'tcx> DebugInfoMethods<'tcx> for CodegenCx<'gcc, 'tcx> { - fn create_vtable_metadata(&self, _ty: Ty<'tcx>, _vtable: Self::Value) { + fn create_vtable_metadata(&self, _ty: Ty<'tcx>, _trait_ref: Option>, _vtable: Self::Value) { // TODO(antoyo) } diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index 1034eb75991e..5c7ec711ad71 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -367,6 +367,11 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { // TODO(antoyo) } + fn type_test(&mut self, _pointer: Self::Value, _typeid: Self::Value) -> Self::Value { + // Unsupported. + self.context.new_rvalue_from_int(self.int_type, 0) + } + fn va_start(&mut self, _va_list: RValue<'gcc>) -> RValue<'gcc> { unimplemented!(); } diff --git a/src/lib.rs b/src/lib.rs index f3c02e2634ff..629003d7982b 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -60,8 +60,8 @@ use rustc_codegen_ssa::target_features::supported_target_features; use rustc_codegen_ssa::traits::{CodegenBackend, ExtraBackendMethods, ModuleBufferMethods, ThinBufferMethods, WriteBackendMethods}; use rustc_data_structures::fx::FxHashMap; use rustc_errors::{ErrorReported, Handler}; +use rustc_metadata::EncodedMetadata; use rustc_middle::dep_graph::{WorkProduct, WorkProductId}; -use rustc_middle::middle::cstore::EncodedMetadata; use rustc_middle::ty::TyCtxt; use rustc_session::config::{Lto, OptLevel, OutputFilenames}; use rustc_session::Session; From 08183f9f2d6b438faf5771ee6a7e87dff03b4723 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Sun, 31 Oct 2021 17:17:13 +0100 Subject: [PATCH 005/356] Remove unused dependency on object (#102) --- Cargo.lock | 43 ------------------------------------------- Cargo.toml | 5 ----- 2 files changed, 48 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 60a2101c689c..e794bc621140 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -17,12 +17,6 @@ version = "0.8.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "450575f58f7bee32816abbff470cbc47797397c2a81e0eaced4b98436daf52e1" -[[package]] -name = "autocfg" -version = "1.0.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "cdb031dd78e28731d87d56cc8ffef4a8f36ca26c38fe2de700543e627f8a464a" - [[package]] name = "bitflags" version = "1.3.2" @@ -35,15 +29,6 @@ version = "1.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd" -[[package]] -name = "crc32fast" -version = "1.2.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "81156fece84ab6a9f2afdb109ce3ae577e42b1228441eded99bd77f627953b1a" -dependencies = [ - "cfg-if", -] - [[package]] name = "fm" version = "0.1.4" @@ -89,12 +74,6 @@ dependencies = [ "wasi", ] -[[package]] -name = "hashbrown" -version = "0.11.2" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ab5ef0d4909ef3724cc8cce6ccc8572c5c817592e9285f5464f8e86f8bd3726e" - [[package]] name = "hermit-abi" version = "0.1.19" @@ -104,16 +83,6 @@ dependencies = [ "libc 0.2.102", ] -[[package]] -name = "indexmap" -version = "1.7.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "bc633605454125dec4b66843673f01c7df2b89479b32e0ed634e43a91cff62a5" -dependencies = [ - "autocfg", - "hashbrown", -] - [[package]] name = "lang_tester" version = "0.3.13" @@ -158,17 +127,6 @@ dependencies = [ "libc 0.2.102", ] -[[package]] -name = "object" -version = "0.25.3" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a38f2be3697a57b4060074ff41b44c16870d916ad7877c17696e063257482bc7" -dependencies = [ - "crc32fast", - "indexmap", - "memchr", -] - [[package]] name = "ppv-lite86" version = "0.2.10" @@ -257,7 +215,6 @@ dependencies = [ "ar", "gccjit", "lang_tester", - "object", "target-lexicon", "tempfile", ] diff --git a/Cargo.toml b/Cargo.toml index 9e8c195c15f6..21f0bfbf69d7 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -23,11 +23,6 @@ target-lexicon = "0.10.0" ar = "0.8.0" -[dependencies.object] -version = "0.25.0" -default-features = false -features = ["read", "std", "write"] # We don't need WASM support. - [dev-dependencies] lang_tester = "0.3.9" tempfile = "3.1.0" From ebe6f6785c5f3ba6c2a18876829774bc215476f5 Mon Sep 17 00:00:00 2001 From: antoyo Date: Sun, 31 Oct 2021 14:27:52 -0400 Subject: [PATCH 006/356] Fix negation operation (#108) --- src/builder.rs | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index 58b7f8cb8e97..17a8a4acc242 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -623,8 +623,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn neg(&mut self, a: RValue<'gcc>) -> RValue<'gcc> { - // TODO(antoyo): use new_unary_op()? - self.cx.context.new_rvalue_from_long(a.get_type(), 0) - a + self.cx.context.new_unary_op(None, UnaryOp::Minus, a.get_type(), a) } fn fneg(&mut self, a: RValue<'gcc>) -> RValue<'gcc> { From ddb015a09e9512a035b5c2017feb65d8b9a44bd8 Mon Sep 17 00:00:00 2001 From: antoyo Date: Wed, 15 Dec 2021 22:06:16 -0500 Subject: [PATCH 007/356] Fix discarded in-out constraint in inline asm (#110) Fixes #109 --- src/asm.rs | 111 ++++++++++++++++++++++------------------------- tests/run/asm.rs | 27 +++++++++--- 2 files changed, 73 insertions(+), 65 deletions(-) diff --git a/src/asm.rs b/src/asm.rs index 7c3ed3c5ee9d..2d3cde7b69e4 100644 --- a/src/asm.rs +++ b/src/asm.rs @@ -18,30 +18,30 @@ use crate::type_of::LayoutGccExt; // Rust asm! and GCC Extended Asm semantics differ substantially. // -// 1. Rust asm operands go along as one list of operands. Operands themselves indicate -// if they're "in" or "out". "In" and "out" operands can interleave. One operand can be +// 1. Rust asm operands go along as one list of operands. Operands themselves indicate +// if they're "in" or "out". "In" and "out" operands can interleave. One operand can be // both "in" and "out" (`inout(reg)`). // -// GCC asm has two different lists for "in" and "out" operands. In terms of gccjit, -// this means that all "out" operands must go before "in" operands. "In" and "out" operands +// GCC asm has two different lists for "in" and "out" operands. In terms of gccjit, +// this means that all "out" operands must go before "in" operands. "In" and "out" operands // cannot interleave. // -// 2. Operand lists in both Rust and GCC are indexed. Index starts from 0. Indexes are important +// 2. Operand lists in both Rust and GCC are indexed. Index starts from 0. Indexes are important // because the asm template refers to operands by index. // // Mapping from Rust to GCC index would be 1-1 if it wasn't for... // -// 3. Clobbers. GCC has a separate list of clobbers, and clobbers don't have indexes. -// Contrary, Rust expresses clobbers through "out" operands that aren't tied to +// 3. Clobbers. GCC has a separate list of clobbers, and clobbers don't have indexes. +// Contrary, Rust expresses clobbers through "out" operands that aren't tied to // a variable (`_`), and such "clobbers" do have index. // -// 4. Furthermore, GCC Extended Asm does not support explicit register constraints -// (like `out("eax")`) directly, offering so-called "local register variables" -// as a workaround. These variables need to be declared and initialized *before* -// the Extended Asm block but *after* normal local variables +// 4. Furthermore, GCC Extended Asm does not support explicit register constraints +// (like `out("eax")`) directly, offering so-called "local register variables" +// as a workaround. These variables need to be declared and initialized *before* +// the Extended Asm block but *after* normal local variables // (see comment in `codegen_inline_asm` for explanation). // -// With that in mind, let's see how we translate Rust syntax to GCC +// With that in mind, let's see how we translate Rust syntax to GCC // (from now on, `CC` stands for "constraint code"): // // * `out(reg_class) var` -> translated to output operand: `"=CC"(var)` @@ -52,18 +52,17 @@ use crate::type_of::LayoutGccExt; // // * `out("explicit register") _` -> not translated to any operands, register is simply added to clobbers list // -// * `inout(reg_class) in_var => out_var` -> translated to two operands: +// * `inout(reg_class) in_var => out_var` -> translated to two operands: // output: `"=CC"(in_var)` -// input: `"num"(out_var)` where num is the GCC index +// input: `"num"(out_var)` where num is the GCC index // of the corresponding output operand // -// * `inout(reg_class) in_var => _` -> same as `inout(reg_class) in_var => tmp`, +// * `inout(reg_class) in_var => _` -> same as `inout(reg_class) in_var => tmp`, // where "tmp" is a temporary unused variable // -// * `out/in/inout("explicit register") var` -> translated to one or two operands as described above -// with `"r"(var)` constraint, +// * `out/in/inout("explicit register") var` -> translated to one or two operands as described above +// with `"r"(var)` constraint, // and one register variable assigned to the desired register. -// const ATT_SYNTAX_INS: &str = ".att_syntax noprefix\n\t"; const INTEL_SYNTAX_INS: &str = "\n\t.intel_syntax noprefix"; @@ -124,7 +123,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { let att_dialect = is_x86 && options.contains(InlineAsmOptions::ATT_SYNTAX); let intel_dialect = is_x86 && !options.contains(InlineAsmOptions::ATT_SYNTAX); - // GCC index of an output operand equals its position in the array + // GCC index of an output operand equals its position in the array let mut outputs = vec![]; // GCC index of an input operand equals its position in the array @@ -138,9 +137,9 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { let mut constants_len = 0; // There are rules we must adhere to if we want GCC to do the right thing: - // + // // * Every local variable that the asm block uses as an output must be declared *before* - // the asm block. + // the asm block. // * There must be no instructions whatsoever between the register variables and the asm. // // Therefore, the backend must generate the instructions strictly in this order: @@ -152,7 +151,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { // We also must make sure that no input operands are emitted before output operands. // // This is why we work in passes, first emitting local vars, then local register vars. - // Also, we don't emit any asm operands immediately; we save them to + // Also, we don't emit any asm operands immediately; we save them to // the one of the buffers to be emitted later. // 1. Normal variables (and saving operands to buffers). @@ -165,7 +164,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { (Constraint(constraint), Some(place)) => (constraint, place.layout.gcc_type(self.cx, false)), // When `reg` is a class and not an explicit register but the out place is not specified, // we need to create an unused output variable to assign the output to. This var - // needs to be of a type that's "compatible" with the register class, but specific type + // needs to be of a type that's "compatible" with the register class, but specific type // doesn't matter. (Constraint(constraint), None) => (constraint, dummy_output_type(self.cx, reg.reg_class())), (Register(_), Some(_)) => { @@ -193,7 +192,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { let tmp_var = self.current_func().new_local(None, ty, "output_register"); outputs.push(AsmOutOperand { - constraint, + constraint, rust_idx, late, readwrite: false, @@ -204,12 +203,12 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { InlineAsmOperandRef::In { reg, value } => { if let ConstraintOrRegister::Constraint(constraint) = reg_to_gcc(reg) { - inputs.push(AsmInOperand { - constraint: Cow::Borrowed(constraint), - rust_idx, + inputs.push(AsmInOperand { + constraint: Cow::Borrowed(constraint), + rust_idx, val: value.immediate() }); - } + } else { // left for the next pass continue @@ -219,7 +218,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { InlineAsmOperandRef::InOut { reg, late, in_value, out_place } => { let constraint = if let ConstraintOrRegister::Constraint(constraint) = reg_to_gcc(reg) { constraint - } + } else { // left for the next pass continue @@ -228,22 +227,22 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { // Rustc frontend guarantees that input and output types are "compatible", // so we can just use input var's type for the output variable. // - // This decision is also backed by the fact that LLVM needs in and out - // values to be of *exactly the same type*, not just "compatible". + // This decision is also backed by the fact that LLVM needs in and out + // values to be of *exactly the same type*, not just "compatible". // I'm not sure if GCC is so picky too, but better safe than sorry. let ty = in_value.layout.gcc_type(self.cx, false); let tmp_var = self.current_func().new_local(None, ty, "output_register"); // If the out_place is None (i.e `inout(reg) _` syntax was used), we translate - // it to one "readwrite (+) output variable", otherwise we translate it to two + // it to one "readwrite (+) output variable", otherwise we translate it to two // "out and tied in" vars as described above. let readwrite = out_place.is_none(); outputs.push(AsmOutOperand { - constraint, + constraint, rust_idx, late, readwrite, - tmp_var, + tmp_var, out_place, }); @@ -252,8 +251,8 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { let constraint = Cow::Owned(out_gcc_idx.to_string()); inputs.push(AsmInOperand { - constraint, - rust_idx, + constraint, + rust_idx, val: in_value.immediate() }); } @@ -280,7 +279,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { if let ConstraintOrRegister::Register(reg_name) = reg_to_gcc(reg) { let out_place = if let Some(place) = place { place - } + } else { // processed in the previous pass continue @@ -291,7 +290,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { tmp_var.set_register_name(reg_name); outputs.push(AsmOutOperand { - constraint: "r".into(), + constraint: "r".into(), rust_idx, late, readwrite: false, @@ -311,9 +310,9 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { reg_var.set_register_name(reg_name); self.llbb().add_assignment(None, reg_var, value.immediate()); - inputs.push(AsmInOperand { - constraint: "r".into(), - rust_idx, + inputs.push(AsmInOperand { + constraint: "r".into(), + rust_idx, val: reg_var.to_rvalue() }); } @@ -324,31 +323,23 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { // `inout("explicit register") in_var => out_var` InlineAsmOperandRef::InOut { reg, late, in_value, out_place } => { if let ConstraintOrRegister::Register(reg_name) = reg_to_gcc(reg) { - let out_place = if let Some(place) = out_place { - place - } - else { - // processed in the previous pass - continue - }; - // See explanation in the first pass. let ty = in_value.layout.gcc_type(self.cx, false); let tmp_var = self.current_func().new_local(None, ty, "output_register"); tmp_var.set_register_name(reg_name); outputs.push(AsmOutOperand { - constraint: "r".into(), + constraint: "r".into(), rust_idx, late, readwrite: false, tmp_var, - out_place: Some(out_place) + out_place, }); let constraint = Cow::Owned((outputs.len() - 1).to_string()); - inputs.push(AsmInOperand { - constraint, + inputs.push(AsmInOperand { + constraint, rust_idx, val: in_value.immediate() }); @@ -357,8 +348,8 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { // processed in the previous pass } - InlineAsmOperandRef::Const { .. } - | InlineAsmOperandRef::SymFn { .. } + InlineAsmOperandRef::Const { .. } + | InlineAsmOperandRef::SymFn { .. } | InlineAsmOperandRef::SymStatic { .. } => { // processed in the previous pass } @@ -453,7 +444,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { if !intel_dialect { template_str.push_str(INTEL_SYNTAX_INS); } - + // 4. Generate Extended Asm block let block = self.llbb(); @@ -472,7 +463,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { } if !options.contains(InlineAsmOptions::PRESERVES_FLAGS) { - // TODO(@Commeownist): I'm not 100% sure this one clobber is sufficient + // TODO(@Commeownist): I'm not 100% sure this one clobber is sufficient // on all architectures. For instance, what about FP stack? extended_asm.add_clobber("cc"); } @@ -491,10 +482,10 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { self.call(self.type_void(), builtin_unreachable, &[], None); } - // Write results to outputs. + // Write results to outputs. // // We need to do this because: - // 1. Turning `PlaceRef` into `RValue` is error-prone and has nasty edge cases + // 1. Turning `PlaceRef` into `RValue` is error-prone and has nasty edge cases // (especially with current `rustc_backend_ssa` API). // 2. Not every output operand has an `out_place`, and it's required by `add_output_operand`. // @@ -502,7 +493,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { // generates `out_place = tmp_var;` assignments if out_place exists. for op in &outputs { if let Some(place) = op.out_place { - OperandValue::Immediate(op.tmp_var.to_rvalue()).store(self, place); + OperandValue::Immediate(op.tmp_var.to_rvalue()).store(self, place); } } diff --git a/tests/run/asm.rs b/tests/run/asm.rs index 9c0055b0b6b5..254d946e5276 100644 --- a/tests/run/asm.rs +++ b/tests/run/asm.rs @@ -17,6 +17,16 @@ extern "C" { fn add_asm(a: i64, b: i64) -> i64; } +pub unsafe fn mem_cpy(dst: *mut u8, src: *const u8, len: usize) { + asm!( + "rep movsb", + inout("rdi") dst => _, + inout("rsi") src => _, + inout("rcx") len => _, + options(preserves_flags, nostack) + ); +} + fn main() { unsafe { asm!("nop"); @@ -62,11 +72,11 @@ fn main() { } assert_eq!(x, 43); - // check inout(reg_class) x + // check inout(reg_class) x let mut x: u64 = 42; unsafe { asm!("add {0}, {0}", - inout(reg) x + inout(reg) x ); } assert_eq!(x, 84); @@ -75,7 +85,7 @@ fn main() { let mut x: u64 = 42; unsafe { asm!("add r11, r11", - inout("r11") x + inout("r11") x ); } assert_eq!(x, 84); @@ -98,12 +108,12 @@ fn main() { assert_eq!(res, 7); assert_eq!(rem, 2); - // check const + // check const let mut x: u64 = 42; unsafe { asm!("add {}, {}", inout(reg) x, - const 1 + const 1 ); } assert_eq!(x, 43); @@ -150,4 +160,11 @@ fn main() { assert_eq!(x, 42); assert_eq!(unsafe { add_asm(40, 2) }, 42); + + let array1 = [1u8, 2, 3]; + let mut array2 = [0u8, 0, 0]; + unsafe { + mem_cpy(array2.as_mut_ptr(), array1.as_ptr(), 3); + } + assert_eq!(array1, array2); } From 2989a25273013dd90c2704b4c0a484c6455b78aa Mon Sep 17 00:00:00 2001 From: antoyo Date: Wed, 15 Dec 2021 23:48:10 -0500 Subject: [PATCH 008/356] Feature/global rvalue initialization petter tomner (#111) * Use new initialization functions * Fix for new reflection patch * Fix for new TLS patch --- Cargo.lock | 26 +++++++++++++------------- src/builder.rs | 29 +++++++++++++++++------------ src/common.rs | 14 +++----------- src/consts.rs | 8 ++++---- src/context.rs | 12 +----------- src/type_.rs | 6 +++--- 6 files changed, 41 insertions(+), 54 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index e794bc621140..47925f72c2cb 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -41,7 +41,7 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" -source = "git+https://github.com/antoyo/gccjit.rs#2d4fea7319f80531b2e5d264fca9f1c498a3a62e" +source = "git+https://github.com/antoyo/gccjit.rs#0672b78d162d65b6f36ea4062947253affe9fdef" dependencies = [ "gccjit_sys", ] @@ -49,7 +49,7 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" -source = "git+https://github.com/antoyo/gccjit.rs#2d4fea7319f80531b2e5d264fca9f1c498a3a62e" +source = "git+https://github.com/antoyo/gccjit.rs#0672b78d162d65b6f36ea4062947253affe9fdef" dependencies = [ "libc 0.1.12", ] @@ -70,7 +70,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "7fcd999463524c52659517fe2cea98493cfe485d10565e7b0fb07dbba7ad2753" dependencies = [ "cfg-if", - "libc 0.2.102", + "libc 0.2.112", "wasi", ] @@ -80,7 +80,7 @@ version = "0.1.19" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "62b467343b94ba476dcb2500d242dadbb39557df889310ac77c5d99100aaac33" dependencies = [ - "libc 0.2.102", + "libc 0.2.112", ] [[package]] @@ -91,7 +91,7 @@ checksum = "96bd995a092cac79868250589869b5a5d656b02a02bd74c8ebdc566dc7203090" dependencies = [ "fm", "getopts", - "libc 0.2.102", + "libc 0.2.112", "num_cpus", "termcolor", "threadpool", @@ -107,9 +107,9 @@ checksum = "e32a70cf75e5846d53a673923498228bbec6a8624708a9ea5645f075d6276122" [[package]] name = "libc" -version = "0.2.102" +version = "0.2.112" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a2a5ac8f984bfcf3a823267e5fde638acc3325f6496633a5da6bb6eb2171e103" +checksum = "1b03d17f364a3a042d5e5d46b053bbbf82c92c9430c592dd4c064dc6ee997125" [[package]] name = "memchr" @@ -124,14 +124,14 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "05499f3756671c15885fee9034446956fff3f243d6077b91e5767df161f766b3" dependencies = [ "hermit-abi", - "libc 0.2.102", + "libc 0.2.112", ] [[package]] name = "ppv-lite86" -version = "0.2.10" +version = "0.2.15" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ac74c624d6b2d21f425f752262f42188365d7b8ff1aff74c82e45136510a4857" +checksum = "ed0cfbc8191465bed66e1718596ee0b0b35d5ee1f41c5df2189d0fe8bde535ba" [[package]] name = "rand" @@ -139,7 +139,7 @@ version = "0.8.4" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "2e7573632e6454cf6b99d7aac4ccca54be06da05aca2ef7423d22d27d4d4bcd8" dependencies = [ - "libc 0.2.102", + "libc 0.2.112", "rand_chacha", "rand_core", "rand_hc", @@ -241,7 +241,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "dac1c663cfc93810f88aed9b8941d48cabf856a1b111c29a40439018d870eb22" dependencies = [ "cfg-if", - "libc 0.2.102", + "libc 0.2.112", "rand", "redox_syscall", "remove_dir_all", @@ -278,7 +278,7 @@ version = "0.2.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "9f200f5b12eb75f8c1ed65abd4b2db8a6e1b138a20de009dacee265a2498f3f6" dependencies = [ - "libc 0.2.102", + "libc 0.2.112", ] [[package]] diff --git a/src/builder.rs b/src/builder.rs index 17a8a4acc242..ccf8123000cf 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -200,7 +200,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { fn check_ptr_call<'b>(&mut self, _typ: &str, func_ptr: RValue<'gcc>, args: &'b [RValue<'gcc>]) -> Cow<'b, [RValue<'gcc>]> { let mut all_args_match = true; let mut param_types = vec![]; - let gcc_func = func_ptr.get_type().is_function_ptr_type().expect("function ptr"); + let gcc_func = func_ptr.get_type().dyncast_function_ptr_type().expect("function ptr"); for (index, arg) in args.iter().enumerate().take(gcc_func.get_param_count()) { let param = gcc_func.get_param_type(index); if param != arg.get_type() { @@ -277,7 +277,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { // gccjit requires to use the result of functions, even when it's not used. // That's why we assign the result to a local or call add_eval(). - let gcc_func = func_ptr.get_type().is_function_ptr_type().expect("function ptr"); + let gcc_func = func_ptr.get_type().dyncast_function_ptr_type().expect("function ptr"); let mut return_type = gcc_func.get_return_type(); let current_block = self.current_block.borrow().expect("block"); let void_type = self.context.new_type::<()>(); @@ -810,7 +810,10 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { let atomic_load = self.context.get_builtin_function(&format!("__atomic_load_{}", size.bytes())); let ordering = self.context.new_rvalue_from_int(self.i32_type, order.to_gcc()); - let volatile_const_void_ptr_type = self.context.new_type::<*mut ()>().make_const().make_volatile(); + let volatile_const_void_ptr_type = self.context.new_type::<()>() + .make_const() + .make_volatile() + .make_pointer(); let ptr = self.context.new_cast(None, ptr, volatile_const_void_ptr_type); self.context.new_call(None, atomic_load, &[ptr, ordering]) } @@ -935,7 +938,9 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { // TODO(antoyo): handle alignment. let atomic_store = self.context.get_builtin_function(&format!("__atomic_store_{}", size.bytes())); let ordering = self.context.new_rvalue_from_int(self.i32_type, order.to_gcc()); - let volatile_const_void_ptr_type = self.context.new_type::<*mut ()>().make_const().make_volatile(); + let volatile_const_void_ptr_type = self.context.new_type::<()>() + .make_volatile() + .make_pointer(); let ptr = self.context.new_cast(None, ptr, volatile_const_void_ptr_type); // FIXME(antoyo): fix libgccjit to allow comparing an integer type with an aligned integer type because @@ -975,12 +980,12 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { assert_eq!(idx as usize as u64, idx); let value = ptr.dereference(None).to_rvalue(); - if value_type.is_array().is_some() { + if value_type.dyncast_array().is_some() { let index = self.context.new_rvalue_from_long(self.u64_type, i64::try_from(idx).expect("i64::try_from")); let element = self.context.new_array_access(None, value, index); element.get_address(None) } - else if let Some(vector_type) = value_type.is_vector() { + else if let Some(vector_type) = value_type.dyncast_vector() { let array_type = vector_type.get_element_type().make_pointer(); let array = self.bitcast(ptr, array_type); let index = self.context.new_rvalue_from_long(self.u64_type, i64::try_from(idx).expect("i64::try_from")); @@ -1003,7 +1008,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { fn sext(&mut self, value: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { // TODO(antoyo): check that it indeed sign extend the value. - if dest_ty.is_vector().is_some() { + if dest_ty.dyncast_vector().is_some() { // TODO(antoyo): nothing to do as it is only for LLVM? return value; } @@ -1075,7 +1080,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { let right_type = rhs.get_type(); if left_type != right_type { // NOTE: because libgccjit cannot compare function pointers. - if left_type.is_function_ptr_type().is_some() && right_type.is_function_ptr_type().is_some() { + if left_type.dyncast_function_ptr_type().is_some() && right_type.dyncast_function_ptr_type().is_some() { lhs = self.context.new_cast(None, lhs, self.usize_type.make_pointer()); rhs = self.context.new_cast(None, rhs, self.usize_type.make_pointer()); } @@ -1183,12 +1188,12 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { assert_eq!(idx as usize as u64, idx); let value_type = aggregate_value.get_type(); - if value_type.is_array().is_some() { + if value_type.dyncast_array().is_some() { let index = self.context.new_rvalue_from_long(self.u64_type, i64::try_from(idx).expect("i64::try_from")); let element = self.context.new_array_access(None, aggregate_value, index); element.get_address(None) } - else if value_type.is_vector().is_some() { + else if value_type.dyncast_vector().is_some() { panic!(); } else if let Some(pointer_type) = value_type.get_pointee() { @@ -1215,11 +1220,11 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { let value_type = aggregate_value.get_type(); let lvalue = - if value_type.is_array().is_some() { + if value_type.dyncast_array().is_some() { let index = self.context.new_rvalue_from_long(self.u64_type, i64::try_from(idx).expect("i64::try_from")); self.context.new_array_access(None, aggregate_value, index) } - else if value_type.is_vector().is_some() { + else if value_type.dyncast_vector().is_some() { panic!(); } else if let Some(pointer_type) = value_type.get_pointee() { diff --git a/src/common.rs b/src/common.rs index bda08b653f05..e972a91acede 100644 --- a/src/common.rs +++ b/src/common.rs @@ -1,5 +1,4 @@ use std::convert::TryFrom; -use std::convert::TryInto; use gccjit::LValue; use gccjit::{Block, CType, RValue, Type, ToRValue}; @@ -44,7 +43,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { let string = self.context.new_string_literal(&*string); let sym = self.generate_local_symbol_name("str"); let global = self.declare_private_global(&sym, self.val_ty(string)); - global.global_set_initializer_value(string); + global.global_set_initializer_rvalue(string); global // TODO(antoyo): set linkage. } @@ -79,7 +78,7 @@ pub fn bytes_in_context<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, bytes: &[u8]) -> bytes.iter() .map(|&byte| context.new_rvalue_from_int(byte_type, byte as i32)) .collect(); - context.new_rvalue_from_array(None, typ, &elements) + context.new_array_constructor(None, typ, &elements) } pub fn type_is_pointer<'gcc>(typ: Type<'gcc>) -> bool { @@ -120,13 +119,6 @@ impl<'gcc, 'tcx> ConstMethods<'tcx> for CodegenCx<'gcc, 'tcx> { } fn const_uint_big(&self, typ: Type<'gcc>, num: u128) -> RValue<'gcc> { - let num64: Result = num.try_into(); - if let Ok(num) = num64 { - // FIXME(antoyo): workaround for a bug where libgccjit is expecting a constant. - // The operations >> 64 and | low are making the normal case a non-constant. - return self.context.new_rvalue_from_long(typ, num as i64); - } - if num >> 64 != 0 { // FIXME(antoyo): use a new function new_rvalue_from_unsigned_long()? let low = self.context.new_rvalue_from_long(self.u64_type, num as u64 as i64); @@ -193,7 +185,7 @@ impl<'gcc, 'tcx> ConstMethods<'tcx> for CodegenCx<'gcc, 'tcx> { // TODO(antoyo): cache the type? It's anonymous, so probably not. let typ = self.type_struct(&fields, packed); let struct_type = typ.is_struct().expect("struct type"); - self.context.new_rvalue_from_struct(None, struct_type, values) + self.context.new_struct_constructor(None, struct_type.as_type(), None, values) } fn const_to_opt_uint(&self, _v: RValue<'gcc>) -> Option { diff --git a/src/consts.rs b/src/consts.rs index 628901269655..ba4589bd8102 100644 --- a/src/consts.rs +++ b/src/consts.rs @@ -20,7 +20,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { pub fn const_bitcast(&self, value: RValue<'gcc>, typ: Type<'gcc>) -> RValue<'gcc> { if value.get_type() == self.bool_type.make_pointer() { if let Some(pointee) = typ.get_pointee() { - if pointee.is_vector().is_some() { + if pointee.dyncast_vector().is_some() { panic!() } } @@ -81,7 +81,7 @@ impl<'gcc, 'tcx> StaticMethods for CodegenCx<'gcc, 'tcx> { else { value }; - global.global_set_initializer_value(value); + global.global_set_initializer_rvalue(value); // As an optimization, all shared statics which do not have interior // mutability are placed into read-only memory. @@ -180,7 +180,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { }; // FIXME(antoyo): I think the name coming from generate_local_symbol_name() above cannot be used // globally. - global.global_set_initializer_value(cv); + global.global_set_initializer_rvalue(cv); // TODO(antoyo): set unnamed address. global.get_address(None) } @@ -375,7 +375,7 @@ fn check_and_apply_linkage<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, attrs: &Codeg real_name.push_str(&sym); let global2 = cx.define_global(&real_name, llty, is_tls, attrs.link_section); // TODO(antoyo): set linkage. - global2.global_set_initializer_value(global1.get_address(None)); + global2.global_set_initializer_rvalue(global1.get_address(None)); // TODO(antoyo): use global_set_initializer() when it will work. global2 } diff --git a/src/context.rs b/src/context.rs index 7677ade7314e..dfcd1b623121 100644 --- a/src/context.rs +++ b/src/context.rs @@ -1,16 +1,6 @@ use std::cell::{Cell, RefCell}; -use gccjit::{ - Block, - Context, - CType, - Function, - FunctionType, - LValue, - RValue, - Struct, - Type, -}; +use gccjit::{Block, CType, Context, Function, FunctionType, LValue, RValue, Struct, Type}; use rustc_codegen_ssa::base::wants_msvc_seh; use rustc_codegen_ssa::traits::{ BackendTypes, diff --git a/src/type_.rs b/src/type_.rs index 3545e1b62810..28e2adc492bb 100644 --- a/src/type_.rs +++ b/src/type_.rs @@ -122,7 +122,7 @@ impl<'gcc, 'tcx> BaseTypeMethods<'tcx> for CodegenCx<'gcc, 'tcx> { if typ.is_integral() { TypeKind::Integer } - else if typ.is_vector().is_some() { + else if typ.dyncast_vector().is_some() { TypeKind::Vector } else { @@ -141,10 +141,10 @@ impl<'gcc, 'tcx> BaseTypeMethods<'tcx> for CodegenCx<'gcc, 'tcx> { } fn element_type(&self, ty: Type<'gcc>) -> Type<'gcc> { - if let Some(typ) = ty.is_array() { + if let Some(typ) = ty.dyncast_array() { typ } - else if let Some(vector_type) = ty.is_vector() { + else if let Some(vector_type) = ty.dyncast_vector() { vector_type.get_element_type() } else if let Some(typ) = ty.get_pointee() { From 049b6aeba4e9b89dd5ed6990609d50926af8db86 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Thu, 30 Dec 2021 15:26:08 +0100 Subject: [PATCH 009/356] Rustup to rustc 1.59.0-nightly (78fd0f633 2021-12-29) --- rust-toolchain | 2 +- src/base.rs | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/rust-toolchain b/rust-toolchain index 3f315e099762..ee0822f6c314 100644 --- a/rust-toolchain +++ b/rust-toolchain @@ -1 +1 @@ -nightly-2021-10-30 +nightly-2021-12-30 diff --git a/src/base.rs b/src/base.rs index c6df250d2fd2..8b23e96066ee 100644 --- a/src/base.rs +++ b/src/base.rs @@ -7,14 +7,12 @@ use gccjit::{ GlobalKind, }; use rustc_middle::dep_graph; -use rustc_middle::middle::exported_symbols; use rustc_middle::ty::TyCtxt; use rustc_middle::mir::mono::Linkage; use rustc_codegen_ssa::{ModuleCodegen, ModuleKind}; use rustc_codegen_ssa::base::maybe_create_entry_wrapper; use rustc_codegen_ssa::mono_item::MonoItemExt; use rustc_codegen_ssa::traits::DebugInfoMethods; -use rustc_metadata::EncodedMetadata; use rustc_session::config::DebugInfo; use rustc_span::Symbol; From 31482a94a0694f829023e31471d53e3821ccabf5 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Thu, 30 Dec 2021 15:36:30 +0100 Subject: [PATCH 010/356] Import std::arch::asm --- tests/run/asm.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/run/asm.rs b/tests/run/asm.rs index 42572bdedf00..9a24915edcd1 100644 --- a/tests/run/asm.rs +++ b/tests/run/asm.rs @@ -3,6 +3,8 @@ // Run-time: // status: 0 +use std::arch::{asm, global_asm}; + global_asm!(" .global add_asm add_asm: From a2c5d29fc95c23be146ddb3858ecef2c2ce0eecc Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Thu, 30 Dec 2021 16:28:53 +0100 Subject: [PATCH 011/356] Add missing feature gate --- tests/run/asm.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/run/asm.rs b/tests/run/asm.rs index 9a24915edcd1..46abbb553bf2 100644 --- a/tests/run/asm.rs +++ b/tests/run/asm.rs @@ -3,6 +3,8 @@ // Run-time: // status: 0 +#![feature(asm_const, asm_sym)] + use std::arch::{asm, global_asm}; global_asm!(" From d7fb7aa76dce64e71e4d37285901654bb898c754 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Thu, 30 Dec 2021 16:57:11 +0100 Subject: [PATCH 012/356] Disable portable-simd test Support for portable-simd isn't implemented yet --- ...0024-core-Disable-portable-simd-test.patch | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 patches/0024-core-Disable-portable-simd-test.patch diff --git a/patches/0024-core-Disable-portable-simd-test.patch b/patches/0024-core-Disable-portable-simd-test.patch new file mode 100644 index 000000000000..8954f91021f4 --- /dev/null +++ b/patches/0024-core-Disable-portable-simd-test.patch @@ -0,0 +1,24 @@ +From b1ae000f6da1abd3b8e9b80c40bc11c89b8ae93c Mon Sep 17 00:00:00 2001 +From: bjorn3 +Date: Thu, 30 Dec 2021 16:54:40 +0100 +Subject: [PATCH] [core] Disable portable-simd test + +--- + library/core/tests/lib.rs | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/library/core/tests/lib.rs b/library/core/tests/lib.rs +index ec70034..7cd9e21 100644 +--- a/library/core/tests/lib.rs ++++ b/library/core/tests/lib.rs +@@ -121,7 +121,6 @@ mod pattern; + mod pin; + mod ptr; + mod result; +-mod simd; + mod slice; + mod str; + mod str_lossy; +-- +2.26.2.7.g19db9cfb68 + From 0afd01283784c42906462fd0aee3ba116766983e Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Thu, 30 Dec 2021 17:50:52 +0100 Subject: [PATCH 013/356] Disable long running libcore tests These only finish in reasonable time with optimizations enabled. This patch file is copied from cg_clif. --- ...0028-core-Disable-long-running-tests.patch | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 patches/0028-core-Disable-long-running-tests.patch diff --git a/patches/0028-core-Disable-long-running-tests.patch b/patches/0028-core-Disable-long-running-tests.patch new file mode 100644 index 000000000000..bf74a74c7c4b --- /dev/null +++ b/patches/0028-core-Disable-long-running-tests.patch @@ -0,0 +1,30 @@ +From 0ffdd8eda8df364391c8ac6e1ce92c73ba9254d4 Mon Sep 17 00:00:00 2001 +From: bjorn3 +Date: Fri, 3 Dec 2021 12:16:30 +0100 +Subject: [PATCH] Disable long running tests + +--- + library/core/tests/slice.rs | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/library/core/tests/slice.rs b/library/core/tests/slice.rs +index 2c8f00a..44847ee 100644 +--- a/library/core/tests/slice.rs ++++ b/library/core/tests/slice.rs +@@ -2332,7 +2332,8 @@ macro_rules! empty_max_mut { + }; + } + ++/* + #[cfg(not(miri))] // Comparing usize::MAX many elements takes forever in Miri (and in rustc without optimizations) + take_tests! { + slice: &[(); usize::MAX], method: take, + (take_in_bounds_max_range_to, (..usize::MAX), Some(EMPTY_MAX), &[(); 0]), +@@ -2345,3 +2347,4 @@ take_tests! { + (take_mut_oob_max_range_to_inclusive, (..=usize::MAX), None, empty_max_mut!()), + (take_mut_in_bounds_max_range_from, (usize::MAX..), Some(&mut [] as _), empty_max_mut!()), + } ++*/ +-- +2.26.2.7.g19db9cfb68 + From 92fbc8f591c5c3869c207e499d2341301fc46078 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Thu, 30 Dec 2021 18:16:04 +0100 Subject: [PATCH 014/356] Ignore new failing test_is_sorted test --- patches/0023-core-Ignore-failing-tests.patch | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/patches/0023-core-Ignore-failing-tests.patch b/patches/0023-core-Ignore-failing-tests.patch index ee5ba449fb8e..73e9c858caf2 100644 --- a/patches/0023-core-Ignore-failing-tests.patch +++ b/patches/0023-core-Ignore-failing-tests.patch @@ -46,4 +46,24 @@ index 4bc44e9..8e3c7a4 100644 #[test] fn cell_allows_array_cycle() { +diff --git a/library/core/tests/slice.rs b/library/core/tests/slice.rs +index 3e00e0a..8e5663b 100644 +--- a/library/core/tests/slice.rs ++++ b/library/core/tests/slice.rs +@@ -2108,6 +2108,7 @@ fn test_copy_within_panics_src_out_of_bounds() { + bytes.copy_within(usize::MAX..=usize::MAX, 0); + } + ++/* + #[test] + fn test_is_sorted() { + let empty: [i32; 0] = []; +@@ -2122,6 +2123,7 @@ fn test_is_sorted() { + assert!(!["c", "bb", "aaa"].is_sorted()); + assert!(["c", "bb", "aaa"].is_sorted_by_key(|s| s.len())); + } ++*/ + + #[test] + fn test_slice_run_destructors() { -- 2.21.0 (Apple Git-122) From 1411a98352ba6bee8ba3b0131c9243e5db1e6a2e Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Thu, 30 Dec 2021 19:27:11 +0100 Subject: [PATCH 015/356] Remove unnecessary report_symbol_names call (#113) rustc_interface already calls it for you --- src/lib.rs | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/lib.rs b/src/lib.rs index 30a33b99e505..034558a879db 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -91,8 +91,6 @@ impl CodegenBackend for GccCodegenBackend { let target_cpu = target_cpu(tcx.sess); let res = codegen_crate(self.clone(), tcx, target_cpu.to_string(), metadata, need_metadata_module); - rustc_symbol_mangling::test::report_symbol_names(tcx); - Box::new(res) } From e690fb12731eb5f86d4c88400a344f65607af385 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 15 Jan 2022 08:57:34 -0500 Subject: [PATCH 016/356] Add comment --- src/lib.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib.rs b/src/lib.rs index 20347f187868..9b62bf418377 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -1,6 +1,6 @@ /* * TODO(antoyo): support #[inline] attributes. - * TODO(antoyo): support LTO. + * TODO(antoyo): support LTO (gcc's equivalent to Thin LTO is enabled by -fwhopr: https://stackoverflow.com/questions/64954525/does-gcc-have-thin-lto). * * TODO(antoyo): remove the patches. */ From cd5d42aad743d49a368d9e65d678be72387808c7 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Sun, 23 Jan 2022 19:39:55 +0100 Subject: [PATCH 017/356] Correctly import foreign statics Previously foreign statics would actually cause a local static to be defined and exported. This issue was found because std::env::vars() was found to return no env vars despite many being defined. This was caused by libstd importing environ as foreign static. The accidental definition of environ caused libstd to read a null pointer which was interpreted as there being no environment variables at all. Also fix tests. STDOUT is not defined by libc. The correct name is stdout. This previously worked as STDOUT was incorrectly defined as null pointer during codegen. --- src/consts.rs | 12 +++++++++--- src/declare.rs | 6 +++--- tests/run/assign.rs | 4 ++-- tests/run/int_overflow.rs | 4 ++-- tests/run/mut_ref.rs | 4 ++-- tests/run/operations.rs | 4 ++-- 6 files changed, 20 insertions(+), 14 deletions(-) diff --git a/src/consts.rs b/src/consts.rs index ba4589bd8102..e55da7952e75 100644 --- a/src/consts.rs +++ b/src/consts.rs @@ -1,4 +1,4 @@ -use gccjit::{LValue, RValue, ToRValue, Type}; +use gccjit::{GlobalKind, LValue, RValue, ToRValue, Type}; use rustc_codegen_ssa::traits::{BaseTypeMethods, ConstMethods, DerivedTypeMethods, StaticMethods}; use rustc_hir as hir; use rustc_hir::Node; @@ -218,7 +218,13 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { } let is_tls = fn_attrs.flags.contains(CodegenFnAttrFlags::THREAD_LOCAL); - let global = self.declare_global(&sym, llty, is_tls, fn_attrs.link_section); + let global = self.declare_global( + &sym, + llty, + GlobalKind::Exported, + is_tls, + fn_attrs.link_section, + ); if !self.tcx.is_reachable_non_generic(def_id) { // TODO(antoyo): set visibility. @@ -389,6 +395,6 @@ fn check_and_apply_linkage<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, attrs: &Codeg // don't do this then linker errors can be generated where the linker // complains that one object files has a thread local version of the // symbol and another one doesn't. - cx.declare_global(&sym, llty, is_tls, attrs.link_section) + cx.declare_global(&sym, llty, GlobalKind::Imported, is_tls, attrs.link_section) } } diff --git a/src/declare.rs b/src/declare.rs index dbee505a4977..ec6f8ea4dde0 100644 --- a/src/declare.rs +++ b/src/declare.rs @@ -22,7 +22,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { global } else { - self.declare_global(name, ty, is_tls, link_section) + self.declare_global(name, ty, GlobalKind::Exported, is_tls, link_section) } } @@ -47,8 +47,8 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { unsafe { std::mem::transmute(func) } }*/ - pub fn declare_global(&self, name: &str, ty: Type<'gcc>, is_tls: bool, link_section: Option) -> LValue<'gcc> { - let global = self.context.new_global(None, GlobalKind::Exported, ty, name); + pub fn declare_global(&self, name: &str, ty: Type<'gcc>, global_kind: GlobalKind, is_tls: bool, link_section: Option) -> LValue<'gcc> { + let global = self.context.new_global(None, global_kind, ty, name); if is_tls { global.set_tls_model(self.tls_model); } diff --git a/tests/run/assign.rs b/tests/run/assign.rs index cc8647006ca6..eb38a8a38357 100644 --- a/tests/run/assign.rs +++ b/tests/run/assign.rs @@ -51,7 +51,7 @@ mod libc { pub fn fflush(stream: *mut i32) -> i32; pub fn printf(format: *const i8, ...) -> i32; - pub static STDOUT: *mut i32; + pub static stdout: *mut i32; } } @@ -67,7 +67,7 @@ mod intrinsics { pub fn panic(_msg: &str) -> ! { unsafe { libc::puts("Panicking\0" as *const str as *const u8); - libc::fflush(libc::STDOUT); + libc::fflush(libc::stdout); intrinsics::abort(); } } diff --git a/tests/run/int_overflow.rs b/tests/run/int_overflow.rs index 7111703ca253..6477b8398280 100644 --- a/tests/run/int_overflow.rs +++ b/tests/run/int_overflow.rs @@ -49,7 +49,7 @@ mod libc { pub fn puts(s: *const u8) -> i32; pub fn fflush(stream: *mut i32) -> i32; - pub static STDOUT: *mut i32; + pub static stdout: *mut i32; } } @@ -65,7 +65,7 @@ mod intrinsics { pub fn panic(_msg: &str) -> ! { unsafe { libc::puts("Panicking\0" as *const str as *const u8); - libc::fflush(libc::STDOUT); + libc::fflush(libc::stdout); intrinsics::abort(); } } diff --git a/tests/run/mut_ref.rs b/tests/run/mut_ref.rs index e8876009cc61..52de20021f3e 100644 --- a/tests/run/mut_ref.rs +++ b/tests/run/mut_ref.rs @@ -53,7 +53,7 @@ mod libc { pub fn fflush(stream: *mut i32) -> i32; pub fn printf(format: *const i8, ...) -> i32; - pub static STDOUT: *mut i32; + pub static stdout: *mut i32; } } @@ -69,7 +69,7 @@ mod intrinsics { pub fn panic(_msg: &str) -> ! { unsafe { libc::puts("Panicking\0" as *const str as *const u8); - libc::fflush(libc::STDOUT); + libc::fflush(libc::stdout); intrinsics::abort(); } } diff --git a/tests/run/operations.rs b/tests/run/operations.rs index 4dc375309e42..e078b37b4aba 100644 --- a/tests/run/operations.rs +++ b/tests/run/operations.rs @@ -59,7 +59,7 @@ mod libc { pub fn puts(s: *const u8) -> i32; pub fn fflush(stream: *mut i32) -> i32; - pub static STDOUT: *mut i32; + pub static stdout: *mut i32; } } @@ -75,7 +75,7 @@ mod intrinsics { pub fn panic(_msg: &str) -> ! { unsafe { libc::puts("Panicking\0" as *const str as *const u8); - libc::fflush(libc::STDOUT); + libc::fflush(libc::stdout); intrinsics::abort(); } } From 6663f4e78e001fe711011ea9df7a0692a73a7695 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Mon, 24 Jan 2022 19:45:38 +0100 Subject: [PATCH 018/356] Move rustup component installation to rust-toolchain This allows cargo check to function correctly without having to first run prepare_build.sh. cg_clif has been using rust-toolchain too for a while now. --- cargo.sh | 2 +- prepare_build.sh | 1 - rust-toolchain | 4 +++- test.sh | 2 +- 4 files changed, 5 insertions(+), 4 deletions(-) diff --git a/cargo.sh b/cargo.sh index 1001c522052c..332f365ce0ce 100755 --- a/cargo.sh +++ b/cargo.sh @@ -8,7 +8,7 @@ pushd $(dirname "$0") >/dev/null source config.sh # read nightly compiler from rust-toolchain file -TOOLCHAIN=$(cat rust-toolchain) +TOOLCHAIN=$(cat rust-toolchain | grep channel | sed 's/channel = "\(.*\)"/\1/') popd >/dev/null diff --git a/prepare_build.sh b/prepare_build.sh index ccf535098301..3896775a0b9d 100755 --- a/prepare_build.sh +++ b/prepare_build.sh @@ -1,5 +1,4 @@ #!/bin/bash --verbose set -e -rustup component add rust-src rustc-dev llvm-tools-preview ./build_sysroot/prepare_sysroot_src.sh diff --git a/rust-toolchain b/rust-toolchain index ee0822f6c314..cab94c0b8cfa 100644 --- a/rust-toolchain +++ b/rust-toolchain @@ -1 +1,3 @@ -nightly-2021-12-30 +[toolchain] +channel = "nightly-2021-12-30" +components = ["rust-src", "rustc-dev", "llvm-tools-preview"] diff --git a/test.sh b/test.sh index 944d0ce516e0..70bd86edcbe2 100755 --- a/test.sh +++ b/test.sh @@ -145,7 +145,7 @@ function test_rustc() { echo echo "[TEST] rust-lang/rust" - rust_toolchain=$(cat rust-toolchain) + rust_toolchain=$(cat rust-toolchain | grep channel | sed 's/channel = "\(.*\)"/\1/') git clone https://github.com/rust-lang/rust.git || true cd rust From 5dc660b10647823842dfe3d8865b4802c7ab90f9 Mon Sep 17 00:00:00 2001 From: antoyo Date: Wed, 26 Jan 2022 08:57:17 -0500 Subject: [PATCH 019/356] Support upgrading the alignment of a global variable (#121) * Renable failing test * Update to newest gccjit.rs --- Cargo.lock | 4 ++-- patches/0023-core-Ignore-failing-tests.patch | 20 -------------------- src/consts.rs | 11 +++++++++-- src/context.rs | 4 ++++ 4 files changed, 15 insertions(+), 24 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 47925f72c2cb..2688ea4a4e14 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -41,7 +41,7 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" -source = "git+https://github.com/antoyo/gccjit.rs#0672b78d162d65b6f36ea4062947253affe9fdef" +source = "git+https://github.com/antoyo/gccjit.rs#e68fce53af18dce4d40e6b7090f881ff86a2e892" dependencies = [ "gccjit_sys", ] @@ -49,7 +49,7 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" -source = "git+https://github.com/antoyo/gccjit.rs#0672b78d162d65b6f36ea4062947253affe9fdef" +source = "git+https://github.com/antoyo/gccjit.rs#e68fce53af18dce4d40e6b7090f881ff86a2e892" dependencies = [ "libc 0.1.12", ] diff --git a/patches/0023-core-Ignore-failing-tests.patch b/patches/0023-core-Ignore-failing-tests.patch index 73e9c858caf2..ee5ba449fb8e 100644 --- a/patches/0023-core-Ignore-failing-tests.patch +++ b/patches/0023-core-Ignore-failing-tests.patch @@ -46,24 +46,4 @@ index 4bc44e9..8e3c7a4 100644 #[test] fn cell_allows_array_cycle() { -diff --git a/library/core/tests/slice.rs b/library/core/tests/slice.rs -index 3e00e0a..8e5663b 100644 ---- a/library/core/tests/slice.rs -+++ b/library/core/tests/slice.rs -@@ -2108,6 +2108,7 @@ fn test_copy_within_panics_src_out_of_bounds() { - bytes.copy_within(usize::MAX..=usize::MAX, 0); - } - -+/* - #[test] - fn test_is_sorted() { - let empty: [i32; 0] = []; -@@ -2122,6 +2123,7 @@ fn test_is_sorted() { - assert!(!["c", "bb", "aaa"].is_sorted()); - assert!(["c", "bb", "aaa"].is_sorted_by_key(|s| s.len())); - } -+*/ - - #[test] - fn test_slice_run_destructors() { -- 2.21.0 (Apple Git-122) diff --git a/src/consts.rs b/src/consts.rs index e55da7952e75..af00539f89b5 100644 --- a/src/consts.rs +++ b/src/consts.rs @@ -35,7 +35,12 @@ impl<'gcc, 'tcx> StaticMethods for CodegenCx<'gcc, 'tcx> { // following: for (value, variable) in &*self.const_globals.borrow() { if format!("{:?}", value) == format!("{:?}", cv) { - // TODO(antoyo): upgrade alignment. + if let Some(global_variable) = self.global_lvalues.borrow().get(variable) { + let alignment = align.bits() as i32; + if alignment > global_variable.get_alignment() { + global_variable.set_alignment(alignment); + } + } return *variable; } } @@ -182,7 +187,9 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { // globally. global.global_set_initializer_rvalue(cv); // TODO(antoyo): set unnamed address. - global.get_address(None) + let rvalue = global.get_address(None); + self.global_lvalues.borrow_mut().insert(rvalue, global); + rvalue } pub fn get_static(&self, def_id: DefId) -> LValue<'gcc> { diff --git a/src/context.rs b/src/context.rs index dfcd1b623121..d260a9833470 100644 --- a/src/context.rs +++ b/src/context.rs @@ -83,6 +83,9 @@ pub struct CodegenCx<'gcc, 'tcx> { /// Cache of emitted const globals (value -> global) pub const_globals: RefCell, RValue<'gcc>>>, + /// Map from the address of a global variable (rvalue) to the global variable itself (lvalue). + /// TODO(antoyo): remove when the rustc API is fixed. + pub global_lvalues: RefCell, LValue<'gcc>>>, /// Cache of constant strings, pub const_cstr_cache: RefCell>>, @@ -195,6 +198,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { function_instances: Default::default(), vtables: Default::default(), const_globals: Default::default(), + global_lvalues: Default::default(), const_cstr_cache: Default::default(), globals: Default::default(), scalar_types: Default::default(), From 99941cd9d26c3ef2d53ecdb4f7563367d66ca3c1 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Tue, 25 Jan 2022 18:16:17 +0100 Subject: [PATCH 020/356] Support -Zfunction-sections This puts every function and data object in their own section. This allows the linker to omit unused functions and data objects with --gc-sections. On linux this shrinks a hello world binary without optimizations (neither sysroot nor binary) from 17MB to 13MB. It shrinks a hello world binary with only sysroot optimizations from 14MB to 13MB. For comparison cg_llvm produces a 3.5MB debug mode hello world binary with an optimized sysroot. Cg_clif produces a 10MB debug mode hello world binary without an optimized sysroot. --- src/base.rs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/base.rs b/src/base.rs index 8b23e96066ee..45e791a99d60 100644 --- a/src/base.rs +++ b/src/base.rs @@ -85,6 +85,12 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol) -> (Modul context.add_command_line_option("-fno-semantic-interposition"); // NOTE: Rust relies on LLVM not doing TBAA (https://github.com/rust-lang/unsafe-code-guidelines/issues/292). context.add_command_line_option("-fno-strict-aliasing"); + + if tcx.sess.opts.debugging_opts.function_sections.unwrap_or(tcx.sess.target.function_sections) { + context.add_command_line_option("-ffunction-sections"); + context.add_command_line_option("-fdata-sections"); + } + if env::var("CG_GCCJIT_DUMP_CODE").as_deref() == Ok("1") { context.set_dump_code_on_compile(true); } From 41f20fa3a5c0cce3c9e56a1d05ed1c22ccfa8818 Mon Sep 17 00:00:00 2001 From: antoyo Date: Sun, 30 Jan 2022 21:45:14 -0500 Subject: [PATCH 021/356] Support 128-bit integers on platforms without native support (#103) * Use sized integer types * Add support for integer types not supported on some platforms * Add feature to test non-native integers in CI --- .github/workflows/{main.yml => ci.yml} | 17 +- .gitignore | 1 + Cargo.lock | 4 +- Readme.md | 8 + build.sh | 14 +- build_sysroot/build_sysroot.sh | 2 +- src/back/write.rs | 7 +- src/base.rs | 8 +- src/builder.rs | 228 ++------ src/common.rs | 28 +- src/context.rs | 85 ++- src/int.rs | 737 +++++++++++++++++++++++++ src/intrinsic/mod.rs | 194 ++++--- src/lib.rs | 27 +- src/type_.rs | 28 +- test.sh | 26 +- tests/run/int.rs | 151 +++++ 17 files changed, 1215 insertions(+), 350 deletions(-) rename .github/workflows/{main.yml => ci.yml} (77%) create mode 100644 src/int.rs create mode 100644 tests/run/int.rs diff --git a/.github/workflows/main.yml b/.github/workflows/ci.yml similarity index 77% rename from .github/workflows/main.yml rename to .github/workflows/ci.yml index 98bed8ef387f..337837c40bfb 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/ci.yml @@ -10,10 +10,17 @@ jobs: strategy: fail-fast: false + matrix: + libgccjit_version: ["libgccjit.so", "libgccjit_without_int128.so"] steps: - uses: actions/checkout@v2 + - uses: actions/checkout@v2 + with: + repository: llvm/llvm-project + path: llvm + - name: Install packages run: sudo apt-get install ninja-build ripgrep @@ -21,19 +28,25 @@ jobs: uses: dawidd6/action-download-artifact@v2 with: workflow: main.yml - name: libgccjit.so + name: ${{ matrix.libgccjit_version }} path: gcc-build repo: antoyo/gcc + search_artifacts: true # Because, instead, the action only check the last job ran and that won't work since we want multiple artifacts. - name: Setup path to libgccjit run: | echo $(readlink -f gcc-build) > gcc_path + # NOTE: the filename is still libgccjit.so even when the artifact name is different. ln gcc-build/libgccjit.so gcc-build/libgccjit.so.0 - - name: Set LIBRARY_PATH + - name: Set env run: | echo "LIBRARY_PATH=$(cat gcc_path)" >> $GITHUB_ENV echo "LD_LIBRARY_PATH=$(cat gcc_path)" >> $GITHUB_ENV + echo "workspace="$GITHUB_WORKSPACE >> $GITHUB_ENV + + - name: Set RUST_COMPILER_RT_ROOT + run: echo "RUST_COMPILER_RT_ROOT="${{ env.workspace }}/llvm/compiler-rt >> $GITHUB_ENV # https://github.com/actions/cache/issues/133 - name: Fixup owner of ~/.cargo/ diff --git a/.gitignore b/.gitignore index 1e2f9e3aebb2..efda74b2633a 100644 --- a/.gitignore +++ b/.gitignore @@ -18,3 +18,4 @@ gimple* res test-backend gcc_path +benchmarks diff --git a/Cargo.lock b/Cargo.lock index 2688ea4a4e14..d4c407b0974f 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -41,7 +41,7 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" -source = "git+https://github.com/antoyo/gccjit.rs#e68fce53af18dce4d40e6b7090f881ff86a2e892" +source = "git+https://github.com/antoyo/gccjit.rs#cbb07c6601ba4246fc2967c4d770403c57192ca2" dependencies = [ "gccjit_sys", ] @@ -49,7 +49,7 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" -source = "git+https://github.com/antoyo/gccjit.rs#e68fce53af18dce4d40e6b7090f881ff86a2e892" +source = "git+https://github.com/antoyo/gccjit.rs#cbb07c6601ba4246fc2967c4d770403c57192ca2" dependencies = [ "libc 0.1.12", ] diff --git a/Readme.md b/Readme.md index 1fcfb5f6e20a..6e333f1b641a 100644 --- a/Readme.md +++ b/Readme.md @@ -109,6 +109,13 @@ Or add a breakpoint to `add_error` in gdb and print the line number using: ``` p loc->m_line +p loc->m_filename->m_buffer +``` + +To print a debug representation of a tree: + +```c +debug_tree(expr); ``` To get the `rustc` command to run in `gdb`, add the `--verbose` flag to `cargo build`. @@ -134,4 +141,5 @@ To get the `rustc` command to run in `gdb`, add the `--verbose` flag to `cargo b * Set `linker='-Clinker=m68k-linux-gcc'`. * Set the path to the cross-compiling libgccjit in `gcc_path`. * Disable the 128-bit integer types if the target doesn't support them by using `let i128_type = context.new_type::();` in `context.rs` (same for u128_type). + * Comment the line: `context.add_command_line_option("-masm=intel");` in src/base.rs. * (might not be necessary) Disable the compilation of libstd.so (and possibly libcore.so?). diff --git a/build.sh b/build.sh index 17a0d2ab3f06..8a621e12b04e 100755 --- a/build.sh +++ b/build.sh @@ -3,7 +3,7 @@ #set -x set -e -if [ -f ./gcc_path ]; then +if [ -f ./gcc_path ]; then export GCC_PATH=$(cat gcc_path) else echo 'Please put the path to your custom build of libgccjit in the file `gcc_path`, see Readme.md for details' @@ -13,13 +13,21 @@ fi export LD_LIBRARY_PATH="$GCC_PATH" export LIBRARY_PATH="$GCC_PATH" +features= + +if [[ "$1" == "--features" ]]; then + shift + features="--features $1" + shift +fi + if [[ "$1" == "--release" ]]; then export CHANNEL='release' - CARGO_INCREMENTAL=1 cargo rustc --release + CARGO_INCREMENTAL=1 cargo rustc --release $features else echo $LD_LIBRARY_PATH export CHANNEL='debug' - cargo rustc + cargo rustc $features fi source config.sh diff --git a/build_sysroot/build_sysroot.sh b/build_sysroot/build_sysroot.sh index d1dcf495db8a..a965ca971a07 100755 --- a/build_sysroot/build_sysroot.sh +++ b/build_sysroot/build_sysroot.sh @@ -22,7 +22,7 @@ if [[ "$1" == "--release" ]]; then RUSTFLAGS="$RUSTFLAGS -Zmir-opt-level=3" cargo build --target $TARGET_TRIPLE --release else sysroot_channel='debug' - cargo build --target $TARGET_TRIPLE + cargo build --target $TARGET_TRIPLE --features compiler_builtins/c fi # Copy files to sysroot diff --git a/src/back/write.rs b/src/back/write.rs index 334ef32f1d1d..b503bd020f6b 100644 --- a/src/back/write.rs +++ b/src/back/write.rs @@ -45,7 +45,7 @@ pub(crate) unsafe fn codegen(cgcx: &CodegenContext, _diag_han if env::var("CG_GCCJIT_DUMP_MODULE_NAMES").as_deref() == Ok("1") { println!("Module {}", module.name); } - if env::var("CG_GCCJIT_DUMP_MODULE").as_deref() == Ok(&module.name) { + if env::var("CG_GCCJIT_DUMP_ALL_MODULES").as_deref() == Ok("1") || env::var("CG_GCCJIT_DUMP_MODULE").as_deref() == Ok(&module.name) { println!("Dumping reproducer {}", module.name); let _ = fs::create_dir("/tmp/reproducers"); // FIXME(antoyo): segfault in dump_reproducer_to_file() might be caused by @@ -54,6 +54,11 @@ pub(crate) unsafe fn codegen(cgcx: &CodegenContext, _diag_han context.dump_reproducer_to_file(&format!("/tmp/reproducers/{}.c", module.name)); println!("Dumped reproducer {}", module.name); } + if env::var("CG_GCCJIT_DUMP_TO_FILE").as_deref() == Ok("1") { + let _ = fs::create_dir("/tmp/gccjit_dumps"); + let path = &format!("/tmp/gccjit_dumps/{}.c", module.name); + context.dump_to_file(path, true); + } context.compile_to_file(OutputKind::ObjectFile, obj_out.to_str().expect("path to str")); } diff --git a/src/base.rs b/src/base.rs index 45e791a99d60..6808993182a0 100644 --- a/src/base.rs +++ b/src/base.rs @@ -52,7 +52,7 @@ pub fn linkage_to_gcc(linkage: Linkage) -> FunctionType { } } -pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol) -> (ModuleCodegen, u64) { +pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_128bit_integers: bool) -> (ModuleCodegen, u64) { let prof_timer = tcx.prof.generic_activity("codegen_module"); let start_time = Instant::now(); @@ -60,7 +60,7 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol) -> (Modul let (module, _) = tcx.dep_graph.with_task( dep_node, tcx, - cgu_name, + (cgu_name, supports_128bit_integers), module_codegen, Some(dep_graph::hash_result), ); @@ -71,7 +71,7 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol) -> (Modul // the time we needed for codegenning it. let cost = time_to_codegen.as_secs() * 1_000_000_000 + time_to_codegen.subsec_nanos() as u64; - fn module_codegen(tcx: TyCtxt<'_>, cgu_name: Symbol) -> ModuleCodegen { + fn module_codegen(tcx: TyCtxt<'_>, (cgu_name, supports_128bit_integers): (Symbol, bool)) -> ModuleCodegen { let cgu = tcx.codegen_unit(cgu_name); // Instantiate monomorphizations without filling out definitions yet... //let llvm_module = ModuleLlvm::new(tcx, &cgu_name.as_str()); @@ -106,7 +106,7 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol) -> (Modul } { - let cx = CodegenCx::new(&context, cgu, tcx); + let cx = CodegenCx::new(&context, cgu, tcx, supports_128bit_integers); let mono_items = cgu.items_in_deterministic_order(tcx); for &(mono_item, (linkage, visibility)) in &mono_items { diff --git a/src/builder.rs b/src/builder.rs index ccf8123000cf..2969eda2d532 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -94,7 +94,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { } fn atomic_extremum(&mut self, operation: ExtremumOperation, dst: RValue<'gcc>, src: RValue<'gcc>, order: AtomicOrdering) -> RValue<'gcc> { - let size = self.cx.int_width(src.get_type()) / 8; + let size = src.get_type().get_size(); let func = self.current_func(); @@ -141,8 +141,8 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { } fn compare_exchange(&self, dst: RValue<'gcc>, cmp: LValue<'gcc>, src: RValue<'gcc>, order: AtomicOrdering, failure_order: AtomicOrdering, weak: bool) -> RValue<'gcc> { - let size = self.cx.int_width(src.get_type()); - let compare_exchange = self.context.get_builtin_function(&format!("__atomic_compare_exchange_{}", size / 8)); + let size = src.get_type().get_size(); + let compare_exchange = self.context.get_builtin_function(&format!("__atomic_compare_exchange_{}", size)); let order = self.context.new_rvalue_from_int(self.i32_type, order.to_gcc()); let failure_order = self.context.new_rvalue_from_int(self.i32_type, failure_order.to_gcc()); let weak = self.context.new_rvalue_from_int(self.bool_type, weak as i32); @@ -290,7 +290,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { if return_type != void_type { unsafe { RETURN_VALUE_COUNT += 1 }; - let result = current_func.new_local(None, return_type, &format!("returnValue{}", unsafe { RETURN_VALUE_COUNT })); + let result = current_func.new_local(None, return_type, &format!("ptrReturnValue{}", unsafe { RETURN_VALUE_COUNT })); current_block.add_assignment(None, result, self.cx.context.new_call_through_ptr(None, func_ptr, &args)); result.to_rvalue() } @@ -309,7 +309,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { } } - pub fn overflow_call(&mut self, func: Function<'gcc>, args: &[RValue<'gcc>], _funclet: Option<&Funclet>) -> RValue<'gcc> { + pub fn overflow_call(&self, func: Function<'gcc>, args: &[RValue<'gcc>], _funclet: Option<&Funclet>) -> RValue<'gcc> { // gccjit requires to use the result of functions, even when it's not used. // That's why we assign the result to a local. let return_type = self.context.new_type::(); @@ -317,7 +317,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let current_func = current_block.get_function(); // TODO(antoyo): return the new_call() directly? Since the overflow function has no side-effects. unsafe { RETURN_VALUE_COUNT += 1 }; - let result = current_func.new_local(None, return_type, &format!("returnValue{}", unsafe { RETURN_VALUE_COUNT })); + let result = current_func.new_local(None, return_type, &format!("overflowReturnValue{}", unsafe { RETURN_VALUE_COUNT })); current_block.add_assignment(None, result, self.cx.context.new_call(None, func, &args)); result.to_rvalue() } @@ -468,23 +468,16 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } } - fn add(&mut self, a: RValue<'gcc>, mut b: RValue<'gcc>) -> RValue<'gcc> { - // FIXME(antoyo): this should not be required. - if format!("{:?}", a.get_type()) != format!("{:?}", b.get_type()) { - b = self.context.new_cast(None, b, a.get_type()); - } - a + b + fn add(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { + self.gcc_add(a, b) } fn fadd(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { a + b } - fn sub(&mut self, a: RValue<'gcc>, mut b: RValue<'gcc>) -> RValue<'gcc> { - if a.get_type() != b.get_type() { - b = self.context.new_cast(None, b, a.get_type()); - } - a - b + fn sub(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { + self.gcc_sub(a, b) } fn fsub(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { @@ -492,7 +485,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn mul(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { - a * b + self.gcc_mul(a, b) } fn fmul(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { @@ -500,8 +493,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn udiv(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { - // TODO(antoyo): convert the arguments to unsigned? - a / b + self.gcc_udiv(a, b) } fn exactudiv(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { @@ -511,8 +503,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn sdiv(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { - // TODO(antoyo): convert the arguments to signed? - a / b + self.gcc_sdiv(a, b) } fn exactsdiv(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { @@ -529,11 +520,11 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn urem(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { - a % b + self.gcc_urem(a, b) } fn srem(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { - a % b + self.gcc_srem(a, b) } fn frem(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { @@ -549,81 +540,33 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn shl(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { - // FIXME(antoyo): remove the casts when libgccjit can shift an unsigned number by an unsigned number. - let a_type = a.get_type(); - let b_type = b.get_type(); - if a_type.is_unsigned(self) && b_type.is_signed(self) { - let a = self.context.new_cast(None, a, b_type); - let result = a << b; - self.context.new_cast(None, result, a_type) - } - else if a_type.is_signed(self) && b_type.is_unsigned(self) { - let b = self.context.new_cast(None, b, a_type); - a << b - } - else { - a << b - } + self.gcc_shl(a, b) } fn lshr(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { - // FIXME(antoyo): remove the casts when libgccjit can shift an unsigned number by an unsigned number. - // TODO(antoyo): cast to unsigned to do a logical shift if that does not work. - let a_type = a.get_type(); - let b_type = b.get_type(); - if a_type.is_unsigned(self) && b_type.is_signed(self) { - let a = self.context.new_cast(None, a, b_type); - let result = a >> b; - self.context.new_cast(None, result, a_type) - } - else if a_type.is_signed(self) && b_type.is_unsigned(self) { - let b = self.context.new_cast(None, b, a_type); - a >> b - } - else { - a >> b - } + self.gcc_lshr(a, b) } fn ashr(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { // TODO(antoyo): check whether behavior is an arithmetic shift for >> . - // FIXME(antoyo): remove the casts when libgccjit can shift an unsigned number by an unsigned number. - let a_type = a.get_type(); - let b_type = b.get_type(); - if a_type.is_unsigned(self) && b_type.is_signed(self) { - let a = self.context.new_cast(None, a, b_type); - let result = a >> b; - self.context.new_cast(None, result, a_type) - } - else if a_type.is_signed(self) && b_type.is_unsigned(self) { - let b = self.context.new_cast(None, b, a_type); - a >> b - } - else { - a >> b - } + // It seems to be if the value is signed. + self.gcc_lshr(a, b) } - fn and(&mut self, a: RValue<'gcc>, mut b: RValue<'gcc>) -> RValue<'gcc> { - if a.get_type() != b.get_type() { - b = self.context.new_cast(None, b, a.get_type()); - } - a & b + fn and(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { + self.gcc_and(a, b) } - fn or(&mut self, a: RValue<'gcc>, mut b: RValue<'gcc>) -> RValue<'gcc> { - if a.get_type() != b.get_type() { - b = self.context.new_cast(None, b, a.get_type()); - } - a | b + fn or(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { + self.cx.gcc_or(a, b) } fn xor(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { - a ^ b + self.gcc_xor(a, b) } fn neg(&mut self, a: RValue<'gcc>) -> RValue<'gcc> { - self.cx.context.new_unary_op(None, UnaryOp::Minus, a.get_type(), a) + self.gcc_neg(a) } fn fneg(&mut self, a: RValue<'gcc>) -> RValue<'gcc> { @@ -631,14 +574,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn not(&mut self, a: RValue<'gcc>) -> RValue<'gcc> { - let operation = - if a.get_type().is_bool() { - UnaryOp::LogicalNegate - } - else { - UnaryOp::BitwiseNegate - }; - self.cx.context.new_unary_op(None, operation, a.get_type(), a) + self.gcc_not(a) } fn unchecked_sadd(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { @@ -646,7 +582,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn unchecked_uadd(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { - a + b + self.gcc_add(a, b) } fn unchecked_ssub(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { @@ -655,7 +591,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { fn unchecked_usub(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { // TODO(antoyo): should generate poison value? - a - b + self.gcc_sub(a, b) } fn unchecked_smul(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { @@ -687,76 +623,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn checked_binop(&mut self, oop: OverflowOp, typ: Ty<'_>, lhs: Self::Value, rhs: Self::Value) -> (Self::Value, Self::Value) { - use rustc_middle::ty::{Int, IntTy::*, Uint, UintTy::*}; - - let new_kind = - match typ.kind() { - Int(t @ Isize) => Int(t.normalize(self.tcx.sess.target.pointer_width)), - Uint(t @ Usize) => Uint(t.normalize(self.tcx.sess.target.pointer_width)), - t @ (Uint(_) | Int(_)) => t.clone(), - _ => panic!("tried to get overflow intrinsic for op applied to non-int type"), - }; - - // TODO(antoyo): remove duplication with intrinsic? - let name = - match oop { - OverflowOp::Add => - match new_kind { - Int(I8) => "__builtin_add_overflow", - Int(I16) => "__builtin_add_overflow", - Int(I32) => "__builtin_sadd_overflow", - Int(I64) => "__builtin_saddll_overflow", - Int(I128) => "__builtin_add_overflow", - - Uint(U8) => "__builtin_add_overflow", - Uint(U16) => "__builtin_add_overflow", - Uint(U32) => "__builtin_uadd_overflow", - Uint(U64) => "__builtin_uaddll_overflow", - Uint(U128) => "__builtin_add_overflow", - - _ => unreachable!(), - }, - OverflowOp::Sub => - match new_kind { - Int(I8) => "__builtin_sub_overflow", - Int(I16) => "__builtin_sub_overflow", - Int(I32) => "__builtin_ssub_overflow", - Int(I64) => "__builtin_ssubll_overflow", - Int(I128) => "__builtin_sub_overflow", - - Uint(U8) => "__builtin_sub_overflow", - Uint(U16) => "__builtin_sub_overflow", - Uint(U32) => "__builtin_usub_overflow", - Uint(U64) => "__builtin_usubll_overflow", - Uint(U128) => "__builtin_sub_overflow", - - _ => unreachable!(), - }, - OverflowOp::Mul => - match new_kind { - Int(I8) => "__builtin_mul_overflow", - Int(I16) => "__builtin_mul_overflow", - Int(I32) => "__builtin_smul_overflow", - Int(I64) => "__builtin_smulll_overflow", - Int(I128) => "__builtin_mul_overflow", - - Uint(U8) => "__builtin_mul_overflow", - Uint(U16) => "__builtin_mul_overflow", - Uint(U32) => "__builtin_umul_overflow", - Uint(U64) => "__builtin_umulll_overflow", - Uint(U128) => "__builtin_mul_overflow", - - _ => unreachable!(), - }, - }; - - let intrinsic = self.context.get_builtin_function(&name); - let res = self.current_func() - // TODO(antoyo): is it correct to use rhs type instead of the parameter typ? - .new_local(None, rhs.get_type(), "binopResult") - .get_address(None); - let overflow = self.overflow_call(intrinsic, &[lhs, rhs, res], None); - (res.dereference(None).to_rvalue(), overflow) + self.gcc_checked_binop(oop, typ, lhs, rhs) } fn alloca(&mut self, ty: Type<'gcc>, align: Align) -> RValue<'gcc> { @@ -1003,7 +870,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { /* Casts */ fn trunc(&mut self, value: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { // TODO(antoyo): check that it indeed truncate the value. - self.context.new_cast(None, value, dest_ty) + self.gcc_int_cast(value, dest_ty) } fn sext(&mut self, value: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { @@ -1016,19 +883,19 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn fptoui(&mut self, value: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { - self.context.new_cast(None, value, dest_ty) + self.gcc_float_to_uint_cast(value, dest_ty) } fn fptosi(&mut self, value: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { - self.context.new_cast(None, value, dest_ty) + self.gcc_float_to_int_cast(value, dest_ty) } fn uitofp(&mut self, value: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { - self.context.new_cast(None, value, dest_ty) + self.gcc_uint_to_float_cast(value, dest_ty) } fn sitofp(&mut self, value: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { - self.context.new_cast(None, value, dest_ty) + self.gcc_int_to_float_cast(value, dest_ty) } fn fptrunc(&mut self, value: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { @@ -1054,7 +921,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { fn intcast(&mut self, value: RValue<'gcc>, dest_typ: Type<'gcc>, _is_signed: bool) -> RValue<'gcc> { // NOTE: is_signed is for value, not dest_typ. - self.cx.context.new_cast(None, value, dest_typ) + self.gcc_int_cast(value, dest_typ) } fn pointercast(&mut self, value: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { @@ -1075,21 +942,8 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } /* Comparisons */ - fn icmp(&mut self, op: IntPredicate, mut lhs: RValue<'gcc>, mut rhs: RValue<'gcc>) -> RValue<'gcc> { - let left_type = lhs.get_type(); - let right_type = rhs.get_type(); - if left_type != right_type { - // NOTE: because libgccjit cannot compare function pointers. - if left_type.dyncast_function_ptr_type().is_some() && right_type.dyncast_function_ptr_type().is_some() { - lhs = self.context.new_cast(None, lhs, self.usize_type.make_pointer()); - rhs = self.context.new_cast(None, rhs, self.usize_type.make_pointer()); - } - // NOTE: hack because we try to cast a vector type to the same vector type. - else if format!("{:?}", left_type) != format!("{:?}", right_type) { - rhs = self.context.new_cast(None, rhs, left_type); - } - } - self.context.new_comparison(None, op.to_gcc_comparison(), lhs, rhs) + fn icmp(&mut self, op: IntPredicate, lhs: RValue<'gcc>, rhs: RValue<'gcc>) -> RValue<'gcc> { + self.gcc_icmp(op, lhs, rhs) } fn fcmp(&mut self, op: RealPredicate, lhs: RValue<'gcc>, rhs: RValue<'gcc>) -> RValue<'gcc> { @@ -1156,7 +1010,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { then_block.add_assignment(None, variable, then_val); then_block.end_with_jump(None, after_block); - if then_val.get_type() != else_val.get_type() { + if !then_val.get_type().is_compatible_with(else_val.get_type()) { else_val = self.context.new_cast(None, else_val, then_val.get_type()); } else_block.add_assignment(None, variable, else_val); @@ -1322,7 +1176,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn atomic_rmw(&mut self, op: AtomicRmwBinOp, dst: RValue<'gcc>, src: RValue<'gcc>, order: AtomicOrdering) -> RValue<'gcc> { - let size = self.cx.int_width(src.get_type()) / 8; + let size = src.get_type().get_size(); let name = match op { AtomicRmwBinOp::AtomicXchg => format!("__atomic_exchange_{}", size), @@ -1396,7 +1250,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { // Fix the code in codegen_ssa::base::from_immediate. return value; } - self.context.new_cast(None, value, dest_typ) + self.gcc_int_cast(value, dest_typ) } fn cx(&self) -> &CodegenCx<'gcc, 'tcx> { @@ -1470,7 +1324,7 @@ impl<'tcx> HasTargetSpec for Builder<'_, '_, 'tcx> { } } -trait ToGccComp { +pub trait ToGccComp { fn to_gcc_comparison(&self) -> ComparisonOp; } diff --git a/src/common.rs b/src/common.rs index 5851826147df..89a3dc052d83 100644 --- a/src/common.rs +++ b/src/common.rs @@ -1,7 +1,5 @@ -use std::convert::TryFrom; - use gccjit::LValue; -use gccjit::{Block, CType, RValue, Type, ToRValue}; +use gccjit::{Block, RValue, Type, ToRValue}; use rustc_codegen_ssa::mir::place::PlaceRef; use rustc_codegen_ssa::traits::{ BaseTypeMethods, @@ -111,29 +109,15 @@ impl<'gcc, 'tcx> ConstMethods<'tcx> for CodegenCx<'gcc, 'tcx> { } fn const_int(&self, typ: Type<'gcc>, int: i64) -> RValue<'gcc> { - self.context.new_rvalue_from_long(typ, i64::try_from(int).expect("i64::try_from")) + self.gcc_int(typ, int) } fn const_uint(&self, typ: Type<'gcc>, int: u64) -> RValue<'gcc> { - self.context.new_rvalue_from_long(typ, u64::try_from(int).expect("u64::try_from") as i64) + self.gcc_uint(typ, int) } fn const_uint_big(&self, typ: Type<'gcc>, num: u128) -> RValue<'gcc> { - if num >> 64 != 0 { - // FIXME(antoyo): use a new function new_rvalue_from_unsigned_long()? - let low = self.context.new_rvalue_from_long(self.u64_type, num as u64 as i64); - let high = self.context.new_rvalue_from_long(typ, (num >> 64) as u64 as i64); - - let sixty_four = self.context.new_rvalue_from_long(typ, 64); - (high << sixty_four) | self.context.new_cast(None, low, typ) - } - else if typ.is_i128(self) { - let num = self.context.new_rvalue_from_long(self.u64_type, num as u64 as i64); - self.context.new_cast(None, num, typ) - } - else { - self.context.new_rvalue_from_long(typ, num as u64 as i64) - } + self.gcc_uint_big(typ, num) } fn const_bool(&self, val: bool) -> RValue<'gcc> { @@ -425,11 +409,11 @@ impl<'gcc, 'tcx> TypeReflection<'gcc, 'tcx> for Type<'gcc> { } fn is_i128(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool { - self.unqualified() == cx.context.new_c_type(CType::Int128t) + self.unqualified() == cx.i128_type.unqualified() } fn is_u128(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool { - self.unqualified() == cx.context.new_c_type(CType::UInt128t) + self.unqualified() == cx.u128_type.unqualified() } fn is_f32(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool { diff --git a/src/context.rs b/src/context.rs index d260a9833470..795966d81830 100644 --- a/src/context.rs +++ b/src/context.rs @@ -62,6 +62,8 @@ pub struct CodegenCx<'gcc, 'tcx> { pub ulonglong_type: Type<'gcc>, pub sizet_type: Type<'gcc>, + pub supports_128bit_integers: bool, + pub float_type: Type<'gcc>, pub double_type: Type<'gcc>, @@ -110,22 +112,29 @@ pub struct CodegenCx<'gcc, 'tcx> { } impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { - pub fn new(context: &'gcc Context<'gcc>, codegen_unit: &'tcx CodegenUnit<'tcx>, tcx: TyCtxt<'tcx>) -> Self { + pub fn new(context: &'gcc Context<'gcc>, codegen_unit: &'tcx CodegenUnit<'tcx>, tcx: TyCtxt<'tcx>, supports_128bit_integers: bool) -> Self { let check_overflow = tcx.sess.overflow_checks(); - // TODO(antoyo): fix this mess. libgccjit seems to return random type when using new_int_type(). - let isize_type = context.new_c_type(CType::LongLong); - let usize_type = context.new_c_type(CType::ULongLong); - let bool_type = context.new_type::(); - let i8_type = context.new_type::(); - let i16_type = context.new_type::(); - let i32_type = context.new_type::(); - let i64_type = context.new_c_type(CType::LongLong); - let i128_type = context.new_c_type(CType::Int128t).get_aligned(8); // TODO(antoyo): should the alignment be hard-coded? - let u8_type = context.new_type::(); - let u16_type = context.new_type::(); - let u32_type = context.new_type::(); - let u64_type = context.new_c_type(CType::ULongLong); - let u128_type = context.new_c_type(CType::UInt128t).get_aligned(8); // TODO(antoyo): should the alignment be hard-coded? + + let i8_type = context.new_c_type(CType::Int8t); + let i16_type = context.new_c_type(CType::Int16t); + let i32_type = context.new_c_type(CType::Int32t); + let i64_type = context.new_c_type(CType::Int64t); + let u8_type = context.new_c_type(CType::UInt8t); + let u16_type = context.new_c_type(CType::UInt16t); + let u32_type = context.new_c_type(CType::UInt32t); + let u64_type = context.new_c_type(CType::UInt64t); + + let (i128_type, u128_type) = + if supports_128bit_integers { + let i128_type = context.new_c_type(CType::Int128t).get_aligned(8); // TODO(antoyo): should the alignment be hard-coded?; + let u128_type = context.new_c_type(CType::UInt128t).get_aligned(8); // TODO(antoyo): should the alignment be hard-coded?; + (i128_type, u128_type) + } + else { + let i128_type = context.new_array_type(None, i64_type, 2); + let u128_type = context.new_array_type(None, u64_type, 2); + (i128_type, u128_type) + }; let tls_model = to_gcc_tls_mode(tcx.sess.tls_model()); @@ -139,8 +148,13 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { let ulonglong_type = context.new_c_type(CType::ULongLong); let sizet_type = context.new_c_type(CType::SizeT); - assert_eq!(isize_type, i64_type); - assert_eq!(usize_type, u64_type); + let isize_type = context.new_c_type(CType::LongLong); + let usize_type = context.new_c_type(CType::ULongLong); + let bool_type = context.new_type::(); + + // TODO(antoyo): only have those assertions on x86_64. + assert_eq!(isize_type.get_size(), i64_type.get_size()); + assert_eq!(usize_type.get_size(), u64_type.get_size()); let mut functions = FxHashMap::default(); let builtins = [ @@ -190,6 +204,8 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { ulonglong_type, sizet_type, + supports_128bit_integers, + float_type, double_type, @@ -221,6 +237,41 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { function } + pub fn is_native_int_type(&self, typ: Type<'gcc>) -> bool { + let types = [ + self.u8_type, + self.u16_type, + self.u32_type, + self.u64_type, + self.i8_type, + self.i16_type, + self.i32_type, + self.i64_type, + ]; + + for native_type in types { + if native_type.is_compatible_with(typ) { + return true; + } + } + + self.supports_128bit_integers && + (self.u128_type.is_compatible_with(typ) || self.i128_type.is_compatible_with(typ)) + } + + pub fn is_non_native_int_type(&self, typ: Type<'gcc>) -> bool { + !self.supports_128bit_integers && + (self.u128_type.is_compatible_with(typ) || self.i128_type.is_compatible_with(typ)) + } + + pub fn is_native_int_type_or_bool(&self, typ: Type<'gcc>) -> bool { + self.is_native_int_type(typ) || typ == self.bool_type + } + + pub fn is_int_type_or_bool(&self, typ: Type<'gcc>) -> bool { + self.is_native_int_type(typ) || self.is_non_native_int_type(typ) || typ == self.bool_type + } + pub fn sess(&self) -> &Session { &self.tcx.sess } diff --git a/src/int.rs b/src/int.rs new file mode 100644 index 000000000000..a1f28f3f8812 --- /dev/null +++ b/src/int.rs @@ -0,0 +1,737 @@ +//! Module to handle integer operations. +//! This module exists because some integer types are not supported on some gcc platforms, e.g. +//! 128-bit integers on 32-bit platforms and thus require to be handled manually. + +use std::convert::TryFrom; + +use gccjit::{ComparisonOp, FunctionType, RValue, ToRValue, Type, UnaryOp, BinaryOp}; +use rustc_codegen_ssa::common::{IntPredicate, TypeKind}; +use rustc_codegen_ssa::traits::{BackendTypes, BaseTypeMethods, BuilderMethods, OverflowOp}; +use rustc_middle::ty::Ty; + +use crate::builder::ToGccComp; +use crate::{builder::Builder, common::{SignType, TypeReflection}, context::CodegenCx}; + +impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { + pub fn gcc_urem(&self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { + // 128-bit unsigned %: __umodti3 + self.multiplicative_operation(BinaryOp::Modulo, "mod", false, a, b) + } + + pub fn gcc_srem(&self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { + // 128-bit signed %: __modti3 + self.multiplicative_operation(BinaryOp::Modulo, "mod", true, a, b) + } + + pub fn gcc_not(&self, a: RValue<'gcc>) -> RValue<'gcc> { + let typ = a.get_type(); + if self.is_native_int_type_or_bool(typ) { + let operation = + if typ.is_bool() { + UnaryOp::LogicalNegate + } + else { + UnaryOp::BitwiseNegate + }; + self.cx.context.new_unary_op(None, operation, typ, a) + } + else { + // TODO(antoyo): use __negdi2 and __negti2 instead? + let element_type = typ.dyncast_array().expect("element type"); + let values = [ + self.cx.context.new_unary_op(None, UnaryOp::BitwiseNegate, element_type, self.low(a)), + self.cx.context.new_unary_op(None, UnaryOp::BitwiseNegate, element_type, self.high(a)), + ]; + self.cx.context.new_array_constructor(None, typ, &values) + } + } + + pub fn gcc_neg(&self, a: RValue<'gcc>) -> RValue<'gcc> { + let a_type = a.get_type(); + if self.is_native_int_type(a_type) { + self.cx.context.new_unary_op(None, UnaryOp::Minus, a.get_type(), a) + } + else { + let param_a = self.context.new_parameter(None, a_type, "a"); + let func = self.context.new_function(None, FunctionType::Extern, a_type, &[param_a], "__negti2", false); + self.context.new_call(None, func, &[a]) + } + } + + pub fn gcc_and(&self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { + self.cx.bitwise_operation(BinaryOp::BitwiseAnd, a, b) + } + + pub fn gcc_lshr(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { + let a_type = a.get_type(); + let b_type = b.get_type(); + let a_native = self.is_native_int_type(a_type); + let b_native = self.is_native_int_type(b_type); + if a_native && b_native { + // FIXME(antoyo): remove the casts when libgccjit can shift an unsigned number by an unsigned number. + // TODO(antoyo): cast to unsigned to do a logical shift if that does not work. + if a_type.is_unsigned(self) && b_type.is_signed(self) { + let a = self.context.new_cast(None, a, b_type); + let result = a >> b; + self.context.new_cast(None, result, a_type) + } + else if a_type.is_signed(self) && b_type.is_unsigned(self) { + let b = self.context.new_cast(None, b, a_type); + a >> b + } + else { + a >> b + } + } + else if a_native && !b_native { + self.gcc_lshr(a, self.gcc_int_cast(b, a_type)) + } + else { + // NOTE: we cannot use the lshr builtin because it's calling hi() (to get the most + // significant half of the number) which uses lshr. + + let native_int_type = a_type.dyncast_array().expect("get element type"); + + let func = self.current_func(); + let then_block = func.new_block("then"); + let else_block = func.new_block("else"); + let after_block = func.new_block("after"); + let b0_block = func.new_block("b0"); + let actual_else_block = func.new_block("actual_else"); + + let result = func.new_local(None, a_type, "shiftResult"); + + let sixty_four = self.gcc_int(native_int_type, 64); + let sixty_three = self.gcc_int(native_int_type, 63); + let zero = self.gcc_zero(native_int_type); + let b = self.gcc_int_cast(b, native_int_type); + let condition = self.gcc_icmp(IntPredicate::IntNE, self.gcc_and(b, sixty_four), zero); + self.llbb().end_with_conditional(None, condition, then_block, else_block); + + // TODO(antoyo): take endianness into account. + let shift_value = self.gcc_sub(b, sixty_four); + let high = self.high(a); + let sign = + if a_type.is_signed(self) { + high >> sixty_three + } + else { + zero + }; + let values = [ + high >> shift_value, + sign, + ]; + let array_value = self.context.new_array_constructor(None, a_type, &values); + then_block.add_assignment(None, result, array_value); + then_block.end_with_jump(None, after_block); + + let condition = self.gcc_icmp(IntPredicate::IntEQ, b, zero); + else_block.end_with_conditional(None, condition, b0_block, actual_else_block); + + b0_block.add_assignment(None, result, a); + b0_block.end_with_jump(None, after_block); + + let shift_value = self.gcc_sub(sixty_four, b); + // NOTE: cast low to its unsigned type in order to perform a logical right shift. + let unsigned_type = native_int_type.to_unsigned(&self.cx); + let casted_low = self.context.new_cast(None, self.low(a), unsigned_type); + let shifted_low = casted_low >> self.context.new_cast(None, b, unsigned_type); + let shifted_low = self.context.new_cast(None, shifted_low, native_int_type); + let values = [ + (high << shift_value) | shifted_low, + high >> b, + ]; + let array_value = self.context.new_array_constructor(None, a_type, &values); + actual_else_block.add_assignment(None, result, array_value); + actual_else_block.end_with_jump(None, after_block); + + // NOTE: since jumps were added in a place rustc does not expect, the current block in the + // state need to be updated. + self.block = Some(after_block); + *self.cx.current_block.borrow_mut() = Some(after_block); + + result.to_rvalue() + } + } + + fn additive_operation(&self, operation: BinaryOp, a: RValue<'gcc>, mut b: RValue<'gcc>) -> RValue<'gcc> { + let a_type = a.get_type(); + let b_type = b.get_type(); + if self.is_native_int_type_or_bool(a_type) && self.is_native_int_type_or_bool(b_type) { + if a.get_type() != b.get_type() { + b = self.context.new_cast(None, b, a.get_type()); + } + self.context.new_binary_op(None, operation, a_type, a, b) + } + else { + let signed = a_type.is_compatible_with(self.i128_type); + let func_name = + match (operation, signed) { + (BinaryOp::Plus, true) => "__rust_i128_add", + (BinaryOp::Plus, false) => "__rust_u128_add", + (BinaryOp::Minus, true) => "__rust_i128_sub", + (BinaryOp::Minus, false) => "__rust_u128_sub", + _ => unreachable!("unexpected additive operation {:?}", operation), + }; + let param_a = self.context.new_parameter(None, a_type, "a"); + let param_b = self.context.new_parameter(None, b_type, "b"); + let func = self.context.new_function(None, FunctionType::Extern, a_type, &[param_a, param_b], func_name, false); + self.context.new_call(None, func, &[a, b]) + } + } + + pub fn gcc_add(&self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { + self.additive_operation(BinaryOp::Plus, a, b) + } + + pub fn gcc_mul(&self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { + self.multiplicative_operation(BinaryOp::Mult, "mul", true, a, b) + } + + pub fn gcc_sub(&self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { + self.additive_operation(BinaryOp::Minus, a, b) + } + + fn multiplicative_operation(&self, operation: BinaryOp, operation_name: &str, signed: bool, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { + let a_type = a.get_type(); + let b_type = b.get_type(); + if self.is_native_int_type_or_bool(a_type) && self.is_native_int_type_or_bool(b_type) { + self.context.new_binary_op(None, operation, a_type, a, b) + } + else { + let sign = + if signed { + "" + } + else { + "u" + }; + let func_name = format!("__{}{}ti3", sign, operation_name); + let param_a = self.context.new_parameter(None, a_type, "a"); + let param_b = self.context.new_parameter(None, b_type, "b"); + let func = self.context.new_function(None, FunctionType::Extern, a_type, &[param_a, param_b], func_name, false); + self.context.new_call(None, func, &[a, b]) + } + } + + pub fn gcc_sdiv(&self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { + // TODO(antoyo): check if the types are signed? + // 128-bit, signed: __divti3 + // TODO(antoyo): convert the arguments to signed? + self.multiplicative_operation(BinaryOp::Divide, "div", true, a, b) + } + + pub fn gcc_udiv(&self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { + // 128-bit, unsigned: __udivti3 + self.multiplicative_operation(BinaryOp::Divide, "div", false, a, b) + } + + pub fn gcc_checked_binop(&self, oop: OverflowOp, typ: Ty<'_>, lhs: ::Value, rhs: ::Value) -> (::Value, ::Value) { + use rustc_middle::ty::{Int, IntTy::*, Uint, UintTy::*}; + + let new_kind = + match typ.kind() { + Int(t @ Isize) => Int(t.normalize(self.tcx.sess.target.pointer_width)), + Uint(t @ Usize) => Uint(t.normalize(self.tcx.sess.target.pointer_width)), + t @ (Uint(_) | Int(_)) => t.clone(), + _ => panic!("tried to get overflow intrinsic for op applied to non-int type"), + }; + + // TODO(antoyo): remove duplication with intrinsic? + let name = + if self.is_native_int_type(lhs.get_type()) { + match oop { + OverflowOp::Add => + match new_kind { + Int(I8) => "__builtin_add_overflow", + Int(I16) => "__builtin_add_overflow", + Int(I32) => "__builtin_sadd_overflow", + Int(I64) => "__builtin_saddll_overflow", + Int(I128) => "__builtin_add_overflow", + + Uint(U8) => "__builtin_add_overflow", + Uint(U16) => "__builtin_add_overflow", + Uint(U32) => "__builtin_uadd_overflow", + Uint(U64) => "__builtin_uaddll_overflow", + Uint(U128) => "__builtin_add_overflow", + + _ => unreachable!(), + }, + OverflowOp::Sub => + match new_kind { + Int(I8) => "__builtin_sub_overflow", + Int(I16) => "__builtin_sub_overflow", + Int(I32) => "__builtin_ssub_overflow", + Int(I64) => "__builtin_ssubll_overflow", + Int(I128) => "__builtin_sub_overflow", + + Uint(U8) => "__builtin_sub_overflow", + Uint(U16) => "__builtin_sub_overflow", + Uint(U32) => "__builtin_usub_overflow", + Uint(U64) => "__builtin_usubll_overflow", + Uint(U128) => "__builtin_sub_overflow", + + _ => unreachable!(), + }, + OverflowOp::Mul => + match new_kind { + Int(I8) => "__builtin_mul_overflow", + Int(I16) => "__builtin_mul_overflow", + Int(I32) => "__builtin_smul_overflow", + Int(I64) => "__builtin_smulll_overflow", + Int(I128) => "__builtin_mul_overflow", + + Uint(U8) => "__builtin_mul_overflow", + Uint(U16) => "__builtin_mul_overflow", + Uint(U32) => "__builtin_umul_overflow", + Uint(U64) => "__builtin_umulll_overflow", + Uint(U128) => "__builtin_mul_overflow", + + _ => unreachable!(), + }, + } + } + else { + match new_kind { + Int(I128) | Uint(U128) => { + let func_name = + match oop { + OverflowOp::Add => + match new_kind { + Int(I128) => "__rust_i128_addo", + Uint(U128) => "__rust_u128_addo", + _ => unreachable!(), + }, + OverflowOp::Sub => + match new_kind { + Int(I128) => "__rust_i128_subo", + Uint(U128) => "__rust_u128_subo", + _ => unreachable!(), + }, + OverflowOp::Mul => + match new_kind { + Int(I128) => "__rust_i128_mulo", // TODO(antoyo): use __muloti4d instead? + Uint(U128) => "__rust_u128_mulo", + _ => unreachable!(), + }, + }; + let a_type = lhs.get_type(); + let b_type = rhs.get_type(); + let param_a = self.context.new_parameter(None, a_type, "a"); + let param_b = self.context.new_parameter(None, b_type, "b"); + let result_field = self.context.new_field(None, a_type, "result"); + let overflow_field = self.context.new_field(None, self.bool_type, "overflow"); + let return_type = self.context.new_struct_type(None, "result_overflow", &[result_field, overflow_field]); + let func = self.context.new_function(None, FunctionType::Extern, return_type.as_type(), &[param_a, param_b], func_name, false); + let result = self.context.new_call(None, func, &[lhs, rhs]); + let overflow = result.access_field(None, overflow_field); + let int_result = result.access_field(None, result_field); + return (int_result, overflow); + }, + _ => { + match oop { + OverflowOp::Mul => + match new_kind { + Int(I32) => "__mulosi4", + Int(I64) => "__mulodi4", + _ => unreachable!(), + }, + _ => unimplemented!("overflow operation for {:?}", new_kind), + } + } + } + }; + + let intrinsic = self.context.get_builtin_function(&name); + let res = self.current_func() + // TODO(antoyo): is it correct to use rhs type instead of the parameter typ? + .new_local(None, rhs.get_type(), "binopResult") + .get_address(None); + let overflow = self.overflow_call(intrinsic, &[lhs, rhs, res], None); + (res.dereference(None).to_rvalue(), overflow) + } + + pub fn gcc_icmp(&self, op: IntPredicate, mut lhs: RValue<'gcc>, mut rhs: RValue<'gcc>) -> RValue<'gcc> { + let a_type = lhs.get_type(); + let b_type = rhs.get_type(); + if self.is_non_native_int_type(a_type) || self.is_non_native_int_type(b_type) { + let signed = a_type.is_compatible_with(self.i128_type); + let sign = + if signed { + "" + } + else { + "u" + }; + let func_name = format!("__{}cmpti2", sign); + let param_a = self.context.new_parameter(None, a_type, "a"); + let param_b = self.context.new_parameter(None, b_type, "b"); + let func = self.context.new_function(None, FunctionType::Extern, self.int_type, &[param_a, param_b], func_name, false); + let cmp = self.context.new_call(None, func, &[lhs, rhs]); + let (op, limit) = + match op { + IntPredicate::IntEQ => { + return self.context.new_comparison(None, ComparisonOp::Equals, cmp, self.context.new_rvalue_one(self.int_type)); + }, + IntPredicate::IntNE => { + return self.context.new_comparison(None, ComparisonOp::NotEquals, cmp, self.context.new_rvalue_one(self.int_type)); + }, + IntPredicate::IntUGT => (ComparisonOp::Equals, 2), + IntPredicate::IntUGE => (ComparisonOp::GreaterThanEquals, 1), + IntPredicate::IntULT => (ComparisonOp::Equals, 0), + IntPredicate::IntULE => (ComparisonOp::LessThanEquals, 1), + IntPredicate::IntSGT => (ComparisonOp::Equals, 2), + IntPredicate::IntSGE => (ComparisonOp::GreaterThanEquals, 1), + IntPredicate::IntSLT => (ComparisonOp::Equals, 0), + IntPredicate::IntSLE => (ComparisonOp::LessThanEquals, 1), + }; + self.context.new_comparison(None, op, cmp, self.context.new_rvalue_from_int(self.int_type, limit)) + } + else { + let left_type = lhs.get_type(); + let right_type = rhs.get_type(); + if left_type != right_type { + // NOTE: because libgccjit cannot compare function pointers. + if left_type.dyncast_function_ptr_type().is_some() && right_type.dyncast_function_ptr_type().is_some() { + lhs = self.context.new_cast(None, lhs, self.usize_type.make_pointer()); + rhs = self.context.new_cast(None, rhs, self.usize_type.make_pointer()); + } + // NOTE: hack because we try to cast a vector type to the same vector type. + else if format!("{:?}", left_type) != format!("{:?}", right_type) { + rhs = self.context.new_cast(None, rhs, left_type); + } + } + self.context.new_comparison(None, op.to_gcc_comparison(), lhs, rhs) + } + } + + pub fn gcc_xor(&self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { + let a_type = a.get_type(); + let b_type = b.get_type(); + if self.is_native_int_type_or_bool(a_type) && self.is_native_int_type_or_bool(b_type) { + a ^ b + } + else { + let values = [ + self.low(a) ^ self.low(b), + self.high(a) ^ self.high(b), + ]; + self.context.new_array_constructor(None, a_type, &values) + } + } + + pub fn gcc_shl(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { + let a_type = a.get_type(); + let b_type = b.get_type(); + let a_native = self.is_native_int_type(a_type); + let b_native = self.is_native_int_type(b_type); + if a_native && b_native { + // FIXME(antoyo): remove the casts when libgccjit can shift an unsigned number by an unsigned number. + if a_type.is_unsigned(self) && b_type.is_signed(self) { + let a = self.context.new_cast(None, a, b_type); + let result = a << b; + self.context.new_cast(None, result, a_type) + } + else if a_type.is_signed(self) && b_type.is_unsigned(self) { + let b = self.context.new_cast(None, b, a_type); + a << b + } + else { + a << b + } + } + else if a_native && !b_native { + self.gcc_shl(a, self.gcc_int_cast(b, a_type)) + } + else { + // NOTE: we cannot use the ashl builtin because it's calling widen_hi() which uses ashl. + let native_int_type = a_type.dyncast_array().expect("get element type"); + + let func = self.current_func(); + let then_block = func.new_block("then"); + let else_block = func.new_block("else"); + let after_block = func.new_block("after"); + let b0_block = func.new_block("b0"); + let actual_else_block = func.new_block("actual_else"); + + let result = func.new_local(None, a_type, "shiftResult"); + + let b = self.gcc_int_cast(b, native_int_type); + let sixty_four = self.gcc_int(native_int_type, 64); + let zero = self.gcc_zero(native_int_type); + let condition = self.gcc_icmp(IntPredicate::IntNE, self.gcc_and(b, sixty_four), zero); + self.llbb().end_with_conditional(None, condition, then_block, else_block); + + // TODO(antoyo): take endianness into account. + let values = [ + zero, + self.low(a) << (b - sixty_four), + ]; + let array_value = self.context.new_array_constructor(None, a_type, &values); + then_block.add_assignment(None, result, array_value); + then_block.end_with_jump(None, after_block); + + let condition = self.gcc_icmp(IntPredicate::IntEQ, b, zero); + else_block.end_with_conditional(None, condition, b0_block, actual_else_block); + + b0_block.add_assignment(None, result, a); + b0_block.end_with_jump(None, after_block); + + // NOTE: cast low to its unsigned type in order to perform a logical right shift. + let unsigned_type = native_int_type.to_unsigned(&self.cx); + let casted_low = self.context.new_cast(None, self.low(a), unsigned_type); + let shift_value = self.context.new_cast(None, sixty_four - b, unsigned_type); + let high_low = self.context.new_cast(None, casted_low >> shift_value, native_int_type); + let values = [ + self.low(a) << b, + (self.high(a) << b) | high_low, + ]; + + let array_value = self.context.new_array_constructor(None, a_type, &values); + actual_else_block.add_assignment(None, result, array_value); + actual_else_block.end_with_jump(None, after_block); + + // NOTE: since jumps were added in a place rustc does not expect, the current block in the + // state need to be updated. + self.block = Some(after_block); + *self.cx.current_block.borrow_mut() = Some(after_block); + + result.to_rvalue() + } + } + + pub fn gcc_bswap(&mut self, mut arg: RValue<'gcc>, width: u64) -> RValue<'gcc> { + let arg_type = arg.get_type(); + if !self.is_native_int_type(arg_type) { + let native_int_type = arg_type.dyncast_array().expect("get element type"); + let lsb = self.context.new_array_access(None, arg, self.context.new_rvalue_from_int(self.int_type, 0)).to_rvalue(); + let swapped_lsb = self.gcc_bswap(lsb, width / 2); + let swapped_lsb = self.context.new_cast(None, swapped_lsb, native_int_type); + let msb = self.context.new_array_access(None, arg, self.context.new_rvalue_from_int(self.int_type, 1)).to_rvalue(); + let swapped_msb = self.gcc_bswap(msb, width / 2); + let swapped_msb = self.context.new_cast(None, swapped_msb, native_int_type); + + // NOTE: we also need to swap the two elements here, in addition to swapping inside + // the elements themselves like done above. + return self.context.new_array_constructor(None, arg_type, &[swapped_msb, swapped_lsb]); + } + + // TODO(antoyo): check if it's faster to use string literals and a + // match instead of format!. + let bswap = self.cx.context.get_builtin_function(&format!("__builtin_bswap{}", width)); + // FIXME(antoyo): this cast should not be necessary. Remove + // when having proper sized integer types. + let param_type = bswap.get_param(0).to_rvalue().get_type(); + if param_type != arg_type { + arg = self.bitcast(arg, param_type); + } + self.cx.context.new_call(None, bswap, &[arg]) + } +} + +impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { + pub fn gcc_int(&self, typ: Type<'gcc>, int: i64) -> RValue<'gcc> { + if self.is_native_int_type_or_bool(typ) { + self.context.new_rvalue_from_long(typ, i64::try_from(int).expect("i64::try_from")) + } + else { + // NOTE: set the sign in high. + self.from_low_high(typ, int, -(int.is_negative() as i64)) + } + } + + pub fn gcc_uint(&self, typ: Type<'gcc>, int: u64) -> RValue<'gcc> { + if self.is_native_int_type_or_bool(typ) { + self.context.new_rvalue_from_long(typ, u64::try_from(int).expect("u64::try_from") as i64) + } + else { + self.from_low_high(typ, int as i64, 0) + } + } + + pub fn gcc_uint_big(&self, typ: Type<'gcc>, num: u128) -> RValue<'gcc> { + let low = num as u64; + let high = (num >> 64) as u64; + if num >> 64 != 0 { + // FIXME(antoyo): use a new function new_rvalue_from_unsigned_long()? + if self.is_native_int_type(typ) { + let low = self.context.new_rvalue_from_long(self.u64_type, low as i64); + let high = self.context.new_rvalue_from_long(typ, high as i64); + + let sixty_four = self.context.new_rvalue_from_long(typ, 64); + let shift = high << sixty_four; + shift | self.context.new_cast(None, low, typ) + } + else { + self.from_low_high(typ, low as i64, high as i64) + } + } + else if typ.is_i128(self) { + let num = self.context.new_rvalue_from_long(self.u64_type, num as u64 as i64); + self.gcc_int_cast(num, typ) + } + else { + self.gcc_uint(typ, num as u64) + } + } + + pub fn gcc_zero(&self, typ: Type<'gcc>) -> RValue<'gcc> { + if self.is_native_int_type_or_bool(typ) { + self.context.new_rvalue_zero(typ) + } + else { + self.from_low_high(typ, 0, 0) + } + } + + pub fn gcc_int_width(&self, typ: Type<'gcc>) -> u64 { + if self.is_native_int_type_or_bool(typ) { + typ.get_size() as u64 * 8 + } + else { + // NOTE: the only unsupported types are u128 and i128. + 128 + } + } + + fn bitwise_operation(&self, operation: BinaryOp, a: RValue<'gcc>, mut b: RValue<'gcc>) -> RValue<'gcc> { + let a_type = a.get_type(); + let b_type = b.get_type(); + let a_native = self.is_native_int_type_or_bool(a_type); + let b_native = self.is_native_int_type_or_bool(b_type); + if a_native && b_native { + if a_type != b_type { + b = self.context.new_cast(None, b, a_type); + } + self.context.new_binary_op(None, operation, a_type, a, b) + } + else { + assert!(!a_native && !b_native, "both types should either be native or non-native for or operation"); + let native_int_type = a_type.dyncast_array().expect("get element type"); + let values = [ + self.context.new_binary_op(None, operation, native_int_type, self.low(a), self.low(b)), + self.context.new_binary_op(None, operation, native_int_type, self.high(a), self.high(b)), + ]; + self.context.new_array_constructor(None, a_type, &values) + } + } + + pub fn gcc_or(&self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { + self.bitwise_operation(BinaryOp::BitwiseOr, a, b) + } + + // TODO(antoyo): can we use https://github.com/rust-lang/compiler-builtins/blob/master/src/int/mod.rs#L379 instead? + pub fn gcc_int_cast(&self, value: RValue<'gcc>, dest_typ: Type<'gcc>) -> RValue<'gcc> { + let value_type = value.get_type(); + if self.is_native_int_type_or_bool(dest_typ) && self.is_native_int_type_or_bool(value_type) { + self.context.new_cast(None, value, dest_typ) + } + else if self.is_native_int_type_or_bool(dest_typ) { + self.context.new_cast(None, self.low(value), dest_typ) + } + else if self.is_native_int_type_or_bool(value_type) { + let dest_element_type = dest_typ.dyncast_array().expect("get element type"); + + // NOTE: set the sign of the value. + let zero = self.context.new_rvalue_zero(value_type); + let is_negative = self.context.new_comparison(None, ComparisonOp::LessThan, value, zero); + let is_negative = self.gcc_int_cast(is_negative, dest_element_type); + let values = [ + self.context.new_cast(None, value, dest_element_type), + self.context.new_unary_op(None, UnaryOp::Minus, dest_element_type, is_negative), + ]; + self.context.new_array_constructor(None, dest_typ, &values) + } + else { + // Since u128 and i128 are the only types that can be unsupported, we know the type of + // value and the destination type have the same size, so a bitcast is fine. + self.context.new_bitcast(None, value, dest_typ) + } + } + + fn int_to_float_cast(&self, signed: bool, value: RValue<'gcc>, dest_typ: Type<'gcc>) -> RValue<'gcc> { + let value_type = value.get_type(); + if self.is_native_int_type_or_bool(value_type) { + return self.context.new_cast(None, value, dest_typ); + } + + let name_suffix = + match self.type_kind(dest_typ) { + TypeKind::Float => "tisf", + TypeKind::Double => "tidf", + kind => panic!("cannot cast a non-native integer to type {:?}", kind), + }; + let sign = + if signed { + "" + } + else { + "un" + }; + let func_name = format!("__float{}{}", sign, name_suffix); + let param = self.context.new_parameter(None, value_type, "n"); + let func = self.context.new_function(None, FunctionType::Extern, dest_typ, &[param], func_name, false); + self.context.new_call(None, func, &[value]) + } + + pub fn gcc_int_to_float_cast(&self, value: RValue<'gcc>, dest_typ: Type<'gcc>) -> RValue<'gcc> { + self.int_to_float_cast(true, value, dest_typ) + } + + pub fn gcc_uint_to_float_cast(&self, value: RValue<'gcc>, dest_typ: Type<'gcc>) -> RValue<'gcc> { + self.int_to_float_cast(false, value, dest_typ) + } + + fn float_to_int_cast(&self, signed: bool, value: RValue<'gcc>, dest_typ: Type<'gcc>) -> RValue<'gcc> { + let value_type = value.get_type(); + if self.is_native_int_type_or_bool(dest_typ) { + return self.context.new_cast(None, value, dest_typ); + } + + let name_suffix = + match self.type_kind(value_type) { + TypeKind::Float => "sfti", + TypeKind::Double => "dfti", + kind => panic!("cannot cast a {:?} to non-native integer", kind), + }; + let sign = + if signed { + "" + } + else { + "uns" + }; + let func_name = format!("__fix{}{}", sign, name_suffix); + let param = self.context.new_parameter(None, value_type, "n"); + let func = self.context.new_function(None, FunctionType::Extern, dest_typ, &[param], func_name, false); + self.context.new_call(None, func, &[value]) + } + + pub fn gcc_float_to_int_cast(&self, value: RValue<'gcc>, dest_typ: Type<'gcc>) -> RValue<'gcc> { + self.float_to_int_cast(true, value, dest_typ) + } + + pub fn gcc_float_to_uint_cast(&self, value: RValue<'gcc>, dest_typ: Type<'gcc>) -> RValue<'gcc> { + self.float_to_int_cast(false, value, dest_typ) + } + + fn high(&self, value: RValue<'gcc>) -> RValue<'gcc> { + self.context.new_array_access(None, value, self.context.new_rvalue_from_int(self.int_type, 1)) + .to_rvalue() + } + + fn low(&self, value: RValue<'gcc>) -> RValue<'gcc> { + self.context.new_array_access(None, value, self.context.new_rvalue_from_int(self.int_type, 0)) + .to_rvalue() + } + + fn from_low_high(&self, typ: Type<'gcc>, low: i64, high: i64) -> RValue<'gcc> { + let native_int_type = typ.dyncast_array().expect("get element type"); + let values = [ + self.context.new_rvalue_from_long(native_int_type, low), + self.context.new_rvalue_from_long(native_int_type, high), + ]; + self.context.new_array_constructor(None, typ, &values) + } +} diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index 572ac559d09d..7cd0f944f2f9 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -1,7 +1,7 @@ pub mod llvm; mod simd; -use gccjit::{ComparisonOp, Function, RValue, ToRValue, Type, UnaryOp}; +use gccjit::{ComparisonOp, Function, RValue, ToRValue, Type, UnaryOp, FunctionType}; use rustc_codegen_ssa::MemFlags; use rustc_codegen_ssa::base::wants_msvc_seh; use rustc_codegen_ssa::common::{IntPredicate, span_invalid_monomorphization_error}; @@ -175,11 +175,11 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { let arg = args[0].immediate(); let result = func.new_local(None, arg.get_type(), "zeros"); - let zero = self.cx.context.new_rvalue_zero(arg.get_type()); - let cond = self.cx.context.new_comparison(None, ComparisonOp::Equals, arg, zero); + let zero = self.cx.gcc_zero(arg.get_type()); + let cond = self.gcc_icmp(IntPredicate::IntEQ, arg, zero); self.llbb().end_with_conditional(None, cond, then_block, else_block); - let zero_result = self.cx.context.new_rvalue_from_long(arg.get_type(), width as i64); + let zero_result = self.cx.gcc_uint(arg.get_type(), width); then_block.add_assignment(None, result, zero_result); then_block.end_with_jump(None, after_block); @@ -195,8 +195,8 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { sym::cttz => self.count_trailing_zeroes(width, arg), _ => unreachable!(), }; - else_block.add_assignment(None, result, zeros); - else_block.end_with_jump(None, after_block); + self.llbb().add_assignment(None, result, zeros); + self.llbb().end_with_jump(None, after_block); // NOTE: since jumps were added in a place rustc does not // expect, the current blocks in the state need to be updated. @@ -217,17 +217,7 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { args[0].immediate() // byte swap a u8/i8 is just a no-op } else { - // TODO(antoyo): check if it's faster to use string literals and a - // match instead of format!. - let bswap = self.cx.context.get_builtin_function(&format!("__builtin_bswap{}", width)); - let mut arg = args[0].immediate(); - // FIXME(antoyo): this cast should not be necessary. Remove - // when having proper sized integer types. - let param_type = bswap.get_param(0).to_rvalue().get_type(); - if param_type != arg.get_type() { - arg = self.bitcast(arg, param_type); - } - self.cx.context.new_call(None, bswap, &[arg]) + self.gcc_bswap(args[0].immediate(), width) } }, sym::bitreverse => self.bit_reverse(width, args[0].immediate()), @@ -526,7 +516,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let value = if result_type.is_signed(self.cx) { - self.context.new_cast(None, value, typ) + self.gcc_int_cast(value, typ) } else { value @@ -673,30 +663,33 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { }, 128 => { // TODO(antoyo): find a more efficient implementation? - let sixty_four = self.context.new_rvalue_from_long(typ, 64); - let high = self.context.new_cast(None, value >> sixty_four, self.u64_type); - let low = self.context.new_cast(None, value, self.u64_type); + let sixty_four = self.gcc_int(typ, 64); + let right_shift = self.gcc_lshr(value, sixty_four); + let high = self.gcc_int_cast(right_shift, self.u64_type); + let low = self.gcc_int_cast(value, self.u64_type); let reversed_high = self.bit_reverse(64, high); let reversed_low = self.bit_reverse(64, low); - let new_low = self.context.new_cast(None, reversed_high, typ); - let new_high = self.context.new_cast(None, reversed_low, typ) << sixty_four; + let new_low = self.gcc_int_cast(reversed_high, typ); + let new_high = self.shl(self.gcc_int_cast(reversed_low, typ), sixty_four); - new_low | new_high + self.gcc_or(new_low, new_high) }, _ => { panic!("cannot bit reverse with width = {}", width); }, }; - self.context.new_cast(None, result, result_type) + self.gcc_int_cast(result, result_type) } - fn count_leading_zeroes(&self, width: u64, arg: RValue<'gcc>) -> RValue<'gcc> { + fn count_leading_zeroes(&mut self, width: u64, arg: RValue<'gcc>) -> RValue<'gcc> { // TODO(antoyo): use width? let arg_type = arg.get_type(); let count_leading_zeroes = + // TODO(antoyo): write a new function Type::is_compatible_with(&Type) and use it here + // instead of using is_uint(). if arg_type.is_uint(&self.cx) { "__builtin_clz" } @@ -712,9 +705,10 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let result = self.current_func() .new_local(None, array_type, "count_loading_zeroes_results"); - let sixty_four = self.context.new_rvalue_from_long(arg_type, 64); - let high = self.context.new_cast(None, arg >> sixty_four, self.u64_type); - let low = self.context.new_cast(None, arg, self.u64_type); + let sixty_four = self.const_uint(arg_type, 64); + let shift = self.lshr(arg, sixty_four); + let high = self.gcc_int_cast(shift, self.u64_type); + let low = self.gcc_int_cast(arg, self.u64_type); let zero = self.context.new_rvalue_zero(self.usize_type); let one = self.context.new_rvalue_one(self.usize_type); @@ -723,17 +717,18 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let clzll = self.context.get_builtin_function("__builtin_clzll"); let first_elem = self.context.new_array_access(None, result, zero); - let first_value = self.context.new_cast(None, self.context.new_call(None, clzll, &[high]), arg_type); + let first_value = self.gcc_int_cast(self.context.new_call(None, clzll, &[high]), arg_type); self.llbb() .add_assignment(None, first_elem, first_value); let second_elem = self.context.new_array_access(None, result, one); - let second_value = self.context.new_cast(None, self.context.new_call(None, clzll, &[low]), arg_type) + sixty_four; + let cast = self.gcc_int_cast(self.context.new_call(None, clzll, &[low]), arg_type); + let second_value = self.add(cast, sixty_four); self.llbb() .add_assignment(None, second_elem, second_value); let third_elem = self.context.new_array_access(None, result, two); - let third_value = self.context.new_rvalue_from_long(arg_type, 128); + let third_value = self.const_uint(arg_type, 128); self.llbb() .add_assignment(None, third_elem, third_value); @@ -749,13 +744,13 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let res = self.context.new_array_access(None, result, index); - return self.context.new_cast(None, res, arg_type); + return self.gcc_int_cast(res.to_rvalue(), arg_type); } else { - let count_leading_zeroes = self.context.get_builtin_function("__builtin_clz"); - let arg = self.context.new_cast(None, arg, self.uint_type); - let diff = self.int_width(self.uint_type) - self.int_width(arg_type); - let diff = self.context.new_rvalue_from_long(self.int_type, diff); + let count_leading_zeroes = self.context.get_builtin_function("__builtin_clzll"); + let arg = self.context.new_cast(None, arg, self.ulonglong_type); + let diff = self.ulonglong_type.get_size() as i64 - arg_type.get_size() as i64; + let diff = self.context.new_rvalue_from_long(self.int_type, diff * 8); let res = self.context.new_call(None, count_leading_zeroes, &[arg]) - diff; return self.context.new_cast(None, res, arg_type); }; @@ -764,18 +759,20 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { self.context.new_cast(None, res, arg_type) } - fn count_trailing_zeroes(&self, _width: u64, arg: RValue<'gcc>) -> RValue<'gcc> { + fn count_trailing_zeroes(&mut self, _width: u64, arg: RValue<'gcc>) -> RValue<'gcc> { let result_type = arg.get_type(); let arg = if result_type.is_signed(self.cx) { let new_type = result_type.to_unsigned(self.cx); - self.context.new_cast(None, arg, new_type) + self.gcc_int_cast(arg, new_type) } else { arg }; let arg_type = arg.get_type(); let (count_trailing_zeroes, expected_type) = + // TODO(antoyo): write a new function Type::is_compatible_with(&Type) and use it here + // instead of using is_uint(). if arg_type.is_uchar(&self.cx) || arg_type.is_ushort(&self.cx) || arg_type.is_uint(&self.cx) { // NOTE: we don't need to & 0xFF for uchar because the result is undefined on zero. ("__builtin_ctz", self.cx.uint_type) @@ -792,9 +789,10 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let result = self.current_func() .new_local(None, array_type, "count_loading_zeroes_results"); - let sixty_four = self.context.new_rvalue_from_long(arg_type, 64); - let high = self.context.new_cast(None, arg >> sixty_four, self.u64_type); - let low = self.context.new_cast(None, arg, self.u64_type); + let sixty_four = self.gcc_int(arg_type, 64); + let shift = self.gcc_lshr(arg, sixty_four); + let high = self.gcc_int_cast(shift, self.u64_type); + let low = self.gcc_int_cast(arg, self.u64_type); let zero = self.context.new_rvalue_zero(self.usize_type); let one = self.context.new_rvalue_one(self.usize_type); @@ -803,17 +801,17 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let ctzll = self.context.get_builtin_function("__builtin_ctzll"); let first_elem = self.context.new_array_access(None, result, zero); - let first_value = self.context.new_cast(None, self.context.new_call(None, ctzll, &[low]), arg_type); + let first_value = self.gcc_int_cast(self.context.new_call(None, ctzll, &[low]), arg_type); self.llbb() .add_assignment(None, first_elem, first_value); let second_elem = self.context.new_array_access(None, result, one); - let second_value = self.context.new_cast(None, self.context.new_call(None, ctzll, &[high]), arg_type) + sixty_four; + let second_value = self.gcc_add(self.gcc_int_cast(self.context.new_call(None, ctzll, &[high]), arg_type), sixty_four); self.llbb() .add_assignment(None, second_elem, second_value); let third_elem = self.context.new_array_access(None, result, two); - let third_value = self.context.new_rvalue_from_long(arg_type, 128); + let third_value = self.gcc_int(arg_type, 128); self.llbb() .add_assignment(None, third_elem, third_value); @@ -829,10 +827,20 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let res = self.context.new_array_access(None, result, index); - return self.context.new_cast(None, res, result_type); + return self.gcc_int_cast(res.to_rvalue(), result_type); } else { - unimplemented!("count_trailing_zeroes for {:?}", arg_type); + let count_trailing_zeroes = self.context.get_builtin_function("__builtin_ctzll"); + let arg_size = arg_type.get_size(); + let casted_arg = self.context.new_cast(None, arg, self.ulonglong_type); + let byte_diff = self.ulonglong_type.get_size() as i64 - arg_size as i64; + let diff = self.context.new_rvalue_from_long(self.int_type, byte_diff * 8); + let mask = self.context.new_rvalue_from_long(arg_type, -1); // To get the value with all bits set. + let masked = mask & self.context.new_unary_op(None, UnaryOp::BitwiseNegate, arg_type, arg); + let cond = self.context.new_comparison(None, ComparisonOp::Equals, masked, mask); + let diff = diff * self.context.new_cast(None, cond, self.int_type); + let res = self.context.new_call(None, count_trailing_zeroes, &[casted_arg]) - diff; + return self.context.new_cast(None, res, result_type); }; let count_trailing_zeroes = self.context.get_builtin_function(count_trailing_zeroes); let arg = @@ -846,18 +854,14 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { self.context.new_cast(None, res, result_type) } - fn int_width(&self, typ: Type<'gcc>) -> i64 { - self.cx.int_width(typ) as i64 - } - - fn pop_count(&self, value: RValue<'gcc>) -> RValue<'gcc> { + fn pop_count(&mut self, value: RValue<'gcc>) -> RValue<'gcc> { // TODO(antoyo): use the optimized version with fewer operations. let result_type = value.get_type(); let value_type = result_type.to_unsigned(self.cx); let value = if result_type.is_signed(self.cx) { - self.context.new_cast(None, value, value_type) + self.gcc_int_cast(value, value_type) } else { value @@ -867,13 +871,14 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { // TODO(antoyo): implement in the normal algorithm below to have a more efficient // implementation (that does not require a call to __popcountdi2). let popcount = self.context.get_builtin_function("__builtin_popcountll"); - let sixty_four = self.context.new_rvalue_from_long(value_type, 64); - let high = self.context.new_cast(None, value >> sixty_four, self.cx.ulonglong_type); + let sixty_four = self.gcc_int(value_type, 64); + let right_shift = self.gcc_lshr(value, sixty_four); + let high = self.gcc_int_cast(right_shift, self.cx.ulonglong_type); let high = self.context.new_call(None, popcount, &[high]); - let low = self.context.new_cast(None, value, self.cx.ulonglong_type); + let low = self.gcc_int_cast(value, self.cx.ulonglong_type); let low = self.context.new_call(None, popcount, &[low]); let res = high + low; - return self.context.new_cast(None, res, result_type); + return self.gcc_int_cast(res, result_type); } // First step. @@ -935,13 +940,14 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { // Algorithm from: https://blog.regehr.org/archives/1063 fn rotate_left(&mut self, value: RValue<'gcc>, shift: RValue<'gcc>, width: u64) -> RValue<'gcc> { - let max = self.context.new_rvalue_from_long(shift.get_type(), width as i64); - let shift = shift % max; + let max = self.const_uint(shift.get_type(), width); + let shift = self.urem(shift, max); let lhs = self.shl(value, shift); + let result_neg = self.neg(shift); let result_and = self.and( - self.context.new_unary_op(None, UnaryOp::Minus, shift.get_type(), shift), - self.context.new_rvalue_from_long(shift.get_type(), width as i64 - 1), + result_neg, + self.const_uint(shift.get_type(), width - 1), ); let rhs = self.lshr(value, result_and); self.or(lhs, rhs) @@ -949,13 +955,14 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { // Algorithm from: https://blog.regehr.org/archives/1063 fn rotate_right(&mut self, value: RValue<'gcc>, shift: RValue<'gcc>, width: u64) -> RValue<'gcc> { - let max = self.context.new_rvalue_from_long(shift.get_type(), width as i64); - let shift = shift % max; + let max = self.const_uint(shift.get_type(), width); + let shift = self.urem(shift, max); let lhs = self.lshr(value, shift); + let result_neg = self.neg(shift); let result_and = self.and( - self.context.new_unary_op(None, UnaryOp::Minus, shift.get_type(), shift), - self.context.new_rvalue_from_long(shift.get_type(), width as i64 - 1), + result_neg, + self.const_uint(shift.get_type(), width - 1), ); let rhs = self.shl(value, result_and); self.or(lhs, rhs) @@ -1015,31 +1022,52 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { fn saturating_sub(&mut self, lhs: RValue<'gcc>, rhs: RValue<'gcc>, signed: bool, width: u64) -> RValue<'gcc> { if signed { // Also based on algorithm from: https://stackoverflow.com/a/56531252/389119 - let func_name = - match width { - 8 => "__builtin_sub_overflow", - 16 => "__builtin_sub_overflow", - 32 => "__builtin_ssub_overflow", - 64 => "__builtin_ssubll_overflow", - 128 => "__builtin_sub_overflow", - _ => unreachable!(), - }; - let overflow_func = self.context.get_builtin_function(func_name); let result_type = lhs.get_type(); let func = self.current_func.borrow().expect("func"); let res = func.new_local(None, result_type, "saturating_diff"); - let overflow = self.overflow_call(overflow_func, &[lhs, rhs, res.get_address(None)], None); + let supports_native_type = self.is_native_int_type(result_type); + let overflow = + if supports_native_type { + let func_name = + match width { + 8 => "__builtin_sub_overflow", + 16 => "__builtin_sub_overflow", + 32 => "__builtin_ssub_overflow", + 64 => "__builtin_ssubll_overflow", + 128 => "__builtin_sub_overflow", + _ => unreachable!(), + }; + let overflow_func = self.context.get_builtin_function(func_name); + self.overflow_call(overflow_func, &[lhs, rhs, res.get_address(None)], None) + } + else { + let func_name = + match width { + 128 => "__rust_i128_subo", + _ => unreachable!(), + }; + let param_a = self.context.new_parameter(None, result_type, "a"); + let param_b = self.context.new_parameter(None, result_type, "b"); + let result_field = self.context.new_field(None, result_type, "result"); + let overflow_field = self.context.new_field(None, self.bool_type, "overflow"); + let return_type = self.context.new_struct_type(None, "result_overflow", &[result_field, overflow_field]); + let func = self.context.new_function(None, FunctionType::Extern, return_type.as_type(), &[param_a, param_b], func_name, false); + let result = self.context.new_call(None, func, &[lhs, rhs]); + let overflow = result.access_field(None, overflow_field); + let int_result = result.access_field(None, result_field); + self.llbb().add_assignment(None, res, int_result); + overflow + }; let then_block = func.new_block("then"); let after_block = func.new_block("after"); - let unsigned_type = self.context.new_int_type(width as i32 / 8, false); - let shifted = self.context.new_cast(None, lhs, unsigned_type) >> self.context.new_rvalue_from_int(unsigned_type, width as i32 - 1); - let uint_max = self.context.new_unary_op(None, UnaryOp::BitwiseNegate, unsigned_type, - self.context.new_rvalue_from_int(unsigned_type, 0) - ); - let int_max = uint_max >> self.context.new_rvalue_one(unsigned_type); - then_block.add_assignment(None, res, self.context.new_cast(None, shifted + int_max, result_type)); + // NOTE: convert the type to unsigned to have an unsigned shift. + let unsigned_type = result_type.to_unsigned(&self.cx); + let shifted = self.gcc_lshr(self.gcc_int_cast(lhs, unsigned_type), self.gcc_int(unsigned_type, width as i64 - 1)); + let uint_max = self.gcc_not(self.gcc_int(unsigned_type, 0)); + let int_max = self.gcc_lshr(uint_max, self.gcc_int(unsigned_type, 1)); + then_block.add_assignment(None, res, self.gcc_int_cast(self.gcc_add(shifted, int_max), result_type)); then_block.end_with_jump(None, after_block); self.llbb().end_with_conditional(None, overflow, then_block, after_block); diff --git a/src/lib.rs b/src/lib.rs index 9b62bf418377..ca283e1380c4 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -1,4 +1,5 @@ /* + * TODO(antoyo): implement equality in libgccjit based on https://zpz.github.io/blog/overloading-equality-operator-in-cpp-class-hierarchy/ (for type equality?) * TODO(antoyo): support #[inline] attributes. * TODO(antoyo): support LTO (gcc's equivalent to Thin LTO is enabled by -fwhopr: https://stackoverflow.com/questions/64954525/does-gcc-have-thin-lto). * @@ -21,6 +22,7 @@ extern crate rustc_middle; extern crate rustc_session; extern crate rustc_span; extern crate rustc_target; +extern crate tempfile; // This prevents duplicating functions and statics that are already part of the host rustc process. #[allow(unused_extern_crates)] @@ -40,15 +42,16 @@ mod context; mod coverageinfo; mod debuginfo; mod declare; +mod int; mod intrinsic; mod mono_item; mod type_; mod type_of; use std::any::Any; -use std::sync::Arc; +use std::sync::{Arc, Mutex}; -use gccjit::{Context, OptimizationLevel}; +use gccjit::{Context, OptimizationLevel, CType}; use rustc_ast::expand::allocator::AllocatorKind; use rustc_codegen_ssa::{CodegenResults, CompiledModule, ModuleCodegen}; use rustc_codegen_ssa::base::codegen_crate; @@ -65,6 +68,7 @@ use rustc_session::config::{Lto, OptLevel, OutputFilenames}; use rustc_session::Session; use rustc_span::Symbol; use rustc_span::fatal_error::FatalError; +use tempfile::TempDir; pub struct PrintOnPanic String>(pub F); @@ -77,13 +81,24 @@ impl String> Drop for PrintOnPanic { } #[derive(Clone)] -pub struct GccCodegenBackend; +pub struct GccCodegenBackend { + supports_128bit_integers: Arc>, +} impl CodegenBackend for GccCodegenBackend { fn init(&self, sess: &Session) { if sess.lto() != Lto::No { sess.warn("LTO is not supported. You may get a linker error."); } + + let temp_dir = TempDir::new().expect("cannot create temporary directory"); + let temp_file = temp_dir.into_path().join("result.asm"); + let check_context = Context::default(); + check_context.set_print_errors_to_stderr(false); + let _int128_ty = check_context.new_c_type(CType::UInt128t); + // NOTE: we cannot just call compile() as this would require other files than libgccjit.so. + check_context.compile_to_file(gccjit::OutputKind::Assembler, temp_file.to_str().expect("path to str")); + *self.supports_128bit_integers.lock().expect("lock") = check_context.get_last_error() == Ok(None); } fn codegen_crate<'tcx>(&self, tcx: TyCtxt<'tcx>, metadata: EncodedMetadata, need_metadata_module: bool) -> Box { @@ -129,7 +144,7 @@ impl ExtraBackendMethods for GccCodegenBackend { } fn compile_codegen_unit<'tcx>(&self, tcx: TyCtxt<'tcx>, cgu_name: Symbol) -> (ModuleCodegen, u64) { - base::compile_codegen_unit(tcx, cgu_name) + base::compile_codegen_unit(tcx, cgu_name, *self.supports_128bit_integers.lock().expect("lock")) } fn target_machine_factory(&self, _sess: &Session, _opt_level: OptLevel) -> TargetMachineFactoryFn { @@ -237,7 +252,9 @@ impl WriteBackendMethods for GccCodegenBackend { /// This is the entrypoint for a hot plugged rustc_codegen_gccjit #[no_mangle] pub fn __rustc_codegen_backend() -> Box { - Box::new(GccCodegenBackend) + Box::new(GccCodegenBackend { + supports_128bit_integers: Arc::new(Mutex::new(false)), + }) } fn to_gcc_opt_level(optlevel: Option) -> OptimizationLevel { diff --git a/src/type_.rs b/src/type_.rs index 28e2adc492bb..3c96cd6afc25 100644 --- a/src/type_.rs +++ b/src/type_.rs @@ -7,7 +7,6 @@ use rustc_middle::bug; use rustc_middle::ty::layout::TyAndLayout; use rustc_target::abi::{AddressSpace, Align, Integer, Size}; -use crate::common::TypeReflection; use crate::context::CodegenCx; use crate::type_of::LayoutGccExt; @@ -119,9 +118,15 @@ impl<'gcc, 'tcx> BaseTypeMethods<'tcx> for CodegenCx<'gcc, 'tcx> { } fn type_kind(&self, typ: Type<'gcc>) -> TypeKind { - if typ.is_integral() { + if self.is_int_type_or_bool(typ) { TypeKind::Integer } + else if typ == self.float_type { + TypeKind::Float + } + else if typ == self.double_type { + TypeKind::Double + } else if typ.dyncast_vector().is_some() { TypeKind::Vector } @@ -175,24 +180,7 @@ impl<'gcc, 'tcx> BaseTypeMethods<'tcx> for CodegenCx<'gcc, 'tcx> { } fn int_width(&self, typ: Type<'gcc>) -> u64 { - if typ.is_i8(self) || typ.is_u8(self) { - 8 - } - else if typ.is_i16(self) || typ.is_u16(self) { - 16 - } - else if typ.is_i32(self) || typ.is_u32(self) { - 32 - } - else if typ.is_i64(self) || typ.is_u64(self) { - 64 - } - else if typ.is_i128(self) || typ.is_u128(self) { - 128 - } - else { - panic!("Cannot get width of int type {:?}", typ); - } + self.gcc_int_width(typ) } fn val_ty(&self, value: RValue<'gcc>) -> Type<'gcc> { diff --git a/test.sh b/test.sh index 70bd86edcbe2..4f05013440b4 100755 --- a/test.sh +++ b/test.sh @@ -4,7 +4,7 @@ set -e -if [ -f ./gcc_path ]; then +if [ -f ./gcc_path ]; then export GCC_PATH=$(cat gcc_path) else echo 'Please put the path to your custom build of libgccjit in the file `gcc_path`, see Readme.md for details' @@ -14,14 +14,26 @@ fi export LD_LIBRARY_PATH="$GCC_PATH" export LIBRARY_PATH="$GCC_PATH" +features= + +if [[ "$1" == "--features" ]]; then + shift + features="--features $1" + shift +fi + if [[ "$1" == "--release" ]]; then export CHANNEL='release' - CARGO_INCREMENTAL=1 cargo rustc --release + CARGO_INCREMENTAL=1 cargo rustc --release $features shift else echo $LD_LIBRARY_PATH export CHANNEL='debug' - cargo rustc + cargo rustc $features +fi + +if [[ "$1" == "--build" ]]; then + exit fi source config.sh @@ -206,6 +218,14 @@ case $1 in clean_ui_tests ;; + "--std-tests") + std_tests + ;; + + "--build-sysroot") + build_sysroot + ;; + *) clean mini_tests diff --git a/tests/run/int.rs b/tests/run/int.rs new file mode 100644 index 000000000000..7a62fc7d1f78 --- /dev/null +++ b/tests/run/int.rs @@ -0,0 +1,151 @@ +// Compiler: +// +// Run-time: +// status: 0 + +#![feature(arbitrary_self_types, auto_traits, core_intrinsics, lang_items, start, intrinsics)] + +#![no_std] + +mod intrinsics { + extern "rust-intrinsic" { + pub fn abort() -> !; + } +} + +/* + * Core + */ + +mod libc { + #[link(name = "c")] + extern "C" { + pub fn puts(s: *const u8) -> i32; + } +} + +#[panic_handler] +fn panic_handler(_: &core::panic::PanicInfo) -> ! { + unsafe { + core::intrinsics::abort(); + } +} + +/* + * Code + */ + +#[start] +fn main(argc: isize, _argv: *const *const u8) -> isize { + let var = 134217856_u128; + let var2 = 10475372733397991552_u128; + let var3 = 193236519889708027473620326106273939584_u128; + let var4 = 123236519889708027473620326106273939584_u128; + let var5 = 153236519889708027473620326106273939584_u128; + let var6 = 18446744073709551616_i128; + let var7 = 170141183460469231731687303715884105728_u128; + + // Shifts. + assert_eq!(var << (argc as u128 - 1), var); + assert_eq!(var << argc as u128, 268435712); + assert_eq!(var << (argc + 32) as u128, 1152922604118474752); + assert_eq!(var << (argc + 48) as u128, 75557935783508361347072); + assert_eq!(var << (argc + 60) as u128, 309485304969250248077606912); + assert_eq!(var << (argc + 62) as u128, 1237941219877000992310427648); + assert_eq!(var << (argc + 63) as u128, 2475882439754001984620855296); + assert_eq!(var << (argc + 80) as u128, 324518863143436548128224745357312); + + assert_eq!(var2 << argc as u128, 20950745466795983104); + assert_eq!(var2 << (argc as u128 - 1), var2); + assert_eq!(var2 << (argc + 32) as u128, 89982766606709001335848566784); + assert_eq!(var2 << (argc + 48) as u128, 5897110592337281111546171672756224); + assert_eq!(var2 << (argc + 60) as u128, 24154564986213503432893119171609493504); + assert_eq!(var2 << (argc + 62) as u128, 96618259944854013731572476686437974016); + assert_eq!(var2 << (argc + 63) as u128, 193236519889708027463144953372875948032); + + assert_eq!(var3 << argc as u128, 46190672858477591483866044780779667712); + assert_eq!(var3 << (argc as u128 - 1), var3); + assert_eq!(var3 << (argc + 32) as u128, 21267668304951024224840338247585366016); + assert_eq!(var3 << (argc + 48) as u128, 1335125106377253154015353231953100800); + assert_eq!(var3 << (argc + 60) as u128, 24154564986213503432893119171609493504); + assert_eq!(var3 << (argc + 62) as u128, 96618259944854013731572476686437974016); + assert_eq!(var3 << (argc + 63) as u128, 193236519889708027463144953372875948032); + + assert_eq!(var >> (argc as u128 - 1), var); + assert_eq!(var >> argc as u128, 67108928); + assert_eq!(var >> (argc + 32) as u128, 0); + assert_eq!(var >> (argc + 48) as u128, 0); + assert_eq!(var >> (argc + 60) as u128, 0); + assert_eq!(var >> (argc + 62) as u128, 0); + assert_eq!(var >> (argc + 63) as u128, 0); + + assert_eq!(var2 >> argc as u128, 5237686366698995776); + assert_eq!(var2 >> (argc as u128 - 1), var2); + assert_eq!(var2 >> (argc + 32) as u128, 1219493888); + assert_eq!(var2 >> (argc + 48) as u128, 18608); + assert_eq!(var2 >> (argc + 60) as u128, 4); + assert_eq!(var2 >> (argc + 62) as u128, 1); + assert_eq!(var2 >> (argc + 63) as u128, 0); + + assert_eq!(var3 >> (argc as u128 - 1), var3); + assert_eq!(var3 >> argc as u128, 96618259944854013736810163053136969792); + assert_eq!(var3 >> (argc + 32) as u128, 22495691651677250335181635584); + assert_eq!(var3 >> (argc + 48) as u128, 343257013727985387194544); + assert_eq!(var3 >> (argc + 60) as u128, 83802981867183932420); + assert_eq!(var3 >> (argc + 62) as u128, 20950745466795983105); + assert_eq!(var3 >> (argc + 63) as u128, 10475372733397991552); + assert_eq!(var3 >> (argc + 80) as u128, 79920751444992); + + assert_eq!(var6 >> argc as u128, 9223372036854775808); + assert_eq!((var6 - 1) >> argc as u128, 9223372036854775807); + assert_eq!(var7 >> argc as u128, 85070591730234615865843651857942052864); + + // Casts + assert_eq!((var >> (argc + 32) as u128) as u64, 0); + assert_eq!((var >> argc as u128) as u64, 67108928); + + // Addition. + assert_eq!(var + argc as u128, 134217857); + + assert_eq!(var2 + argc as u128, 10475372733397991553); + assert_eq!(var2 + (var2 + argc as u128) as u128, 20950745466795983105); + + assert_eq!(var3 + argc as u128, 193236519889708027473620326106273939585); + + // Subtraction + assert_eq!(var - argc as u128, 134217855); + + assert_eq!(var2 - argc as u128, 10475372733397991551); + + assert_eq!(var3 - argc as u128, 193236519889708027473620326106273939583); + + // Multiplication + assert_eq!(var * (argc + 1) as u128, 268435712); + assert_eq!(var * (argc as u128 + var2), 1405982069077538020949770368); + + assert_eq!(var2 * (argc + 1) as u128, 20950745466795983104); + assert_eq!(var2 * (argc as u128 + var2), 109733433903618109003204073240861360256); + + assert_eq!(var3 * argc as u128, 193236519889708027473620326106273939584); + + assert_eq!(var4 * (argc + 1) as u128, 246473039779416054947240652212547879168); + + assert_eq!(var5 * (argc + 1) as u128, 306473039779416054947240652212547879168); + + // Division. + assert_eq!(var / (argc + 1) as u128, 67108928); + assert_eq!(var / (argc + 2) as u128, 44739285); + + assert_eq!(var2 / (argc + 1) as u128, 5237686366698995776); + assert_eq!(var2 / (argc + 2) as u128, 3491790911132663850); + + assert_eq!(var3 / (argc + 1) as u128, 96618259944854013736810163053136969792); + assert_eq!(var3 / (argc + 2) as u128, 64412173296569342491206775368757979861); + assert_eq!(var3 / (argc as u128 + var4), 1); + assert_eq!(var3 / (argc as u128 + var2), 18446744073709551615); + + assert_eq!(var4 / (argc + 1) as u128, 61618259944854013736810163053136969792); + assert_eq!(var4 / (argc + 2) as u128, 41078839963236009157873442035424646528); + + 0 +} From 9c3cce661f619e21534110755ece02e8d18d5d51 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 15 Jan 2022 11:13:35 -0500 Subject: [PATCH 022/356] Implement simd_neg --- src/intrinsic/simd.rs | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index aff27f71d91c..7d7811c87821 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -163,5 +163,26 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, simd_xor: Uint, Int => xor; } + macro_rules! arith_unary { + ($($name: ident: $($($p: ident),* => $call: ident),*;)*) => { + $(if name == sym::$name { + match in_elem.kind() { + $($(ty::$p(_))|* => { + return Ok(bx.$call(args[0].immediate())) + })* + _ => {}, + } + require!(false, + "unsupported operation on `{}` with element `{}`", + in_ty, + in_elem) + })* + } + } + + arith_unary! { + simd_neg: Int => neg, Float => fneg; + } + unimplemented!("simd {}", name); } From 7aaa87bcd24d82cf9ee50912d71ac304aeef88dc Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Sun, 30 Jan 2022 13:21:12 +0100 Subject: [PATCH 023/356] Rustup to rustc 1.60.0-nightly (a00e130da 2022-01-29) --- rust-toolchain | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rust-toolchain b/rust-toolchain index cab94c0b8cfa..bf316efc324b 100644 --- a/rust-toolchain +++ b/rust-toolchain @@ -1,3 +1,3 @@ [toolchain] -channel = "nightly-2021-12-30" +channel = "nightly-2022-01-30" components = ["rust-src", "rustc-dev", "llvm-tools-preview"] From 9c3a1235c5273e01b6e52ea5bbe5e047c7a97778 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Sun, 30 Jan 2022 13:38:27 +0100 Subject: [PATCH 024/356] Fix type_kind implementation --- src/type_.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/type_.rs b/src/type_.rs index 3c96cd6afc25..e95058085216 100644 --- a/src/type_.rs +++ b/src/type_.rs @@ -121,10 +121,10 @@ impl<'gcc, 'tcx> BaseTypeMethods<'tcx> for CodegenCx<'gcc, 'tcx> { if self.is_int_type_or_bool(typ) { TypeKind::Integer } - else if typ == self.float_type { + else if typ.is_compatible_with(self.float_type) { TypeKind::Float } - else if typ == self.double_type { + else if typ.is_compatible_with(self.double_type) { TypeKind::Double } else if typ.dyncast_vector().is_some() { From 5067ad9edcec36b3aa7e55f4e97e2389eb715e59 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Sun, 30 Jan 2022 13:39:41 +0100 Subject: [PATCH 025/356] Replace unimplemented with todo in apply_attrs_to_cleanup_callsite --- src/builder.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/builder.rs b/src/builder.rs index f047417d1445..78e765fbc86d 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1255,7 +1255,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn apply_attrs_to_cleanup_callsite(&mut self, _llret: RValue<'gcc>) { - unimplemented!(); + // TODO } fn set_span(&mut self, _span: Span) {} From 477d102697654e45d1a89e087eb3e0127aeb539d Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Tue, 1 Feb 2022 16:46:48 +0100 Subject: [PATCH 026/356] Move coretests to the 2021 edition --- patches/0022-core-Disable-not-compiling-tests.patch | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/patches/0022-core-Disable-not-compiling-tests.patch b/patches/0022-core-Disable-not-compiling-tests.patch index aae62a938b45..301b3f9bde4d 100644 --- a/patches/0022-core-Disable-not-compiling-tests.patch +++ b/patches/0022-core-Disable-not-compiling-tests.patch @@ -22,7 +22,7 @@ index 0000000..46fd999 +[package] +name = "core" +version = "0.0.0" -+edition = "2018" ++edition = "2021" + +[lib] +name = "coretests" From 4cdcf035a60c4adc8602cd61484c19846d621a25 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonah=20Br=C3=BCchert?= Date: Fri, 4 Feb 2022 02:06:46 +0100 Subject: [PATCH 027/356] README: Add compiler-rt cloning step --- Readme.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Readme.md b/Readme.md index 6e333f1b641a..27b30e0fd1b3 100644 --- a/Readme.md +++ b/Readme.md @@ -21,6 +21,8 @@ You can also use my [fork of gcc](https://github.com/antoyo/gcc) which already i ```bash $ git clone https://github.com/rust-lang/rustc_codegen_gcc.git $ cd rustc_codegen_gcc +$ git clone https://github.com/llvm/llvm-project llvm --depth 1 --single-branch +$ export RUST_COMPILER_RT_ROOT="$PWD/llvm/compiler-rt" $ ./prepare_build.sh # download and patch sysroot src $ ./build.sh --release ``` From d565f6005494532dc0907eb22b9217b139103ea2 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Fri, 25 Feb 2022 11:29:57 +0100 Subject: [PATCH 028/356] Rustup to rustc 1.61.0-nightly (4b043faba 2022-02-24) --- ...0024-core-Disable-portable-simd-test.patch | 220 +++++++++++++++++- rust-toolchain | 2 +- 2 files changed, 217 insertions(+), 5 deletions(-) diff --git a/patches/0024-core-Disable-portable-simd-test.patch b/patches/0024-core-Disable-portable-simd-test.patch index 8954f91021f4..4ffb24cd9a7a 100644 --- a/patches/0024-core-Disable-portable-simd-test.patch +++ b/patches/0024-core-Disable-portable-simd-test.patch @@ -7,18 +7,230 @@ Subject: [PATCH] [core] Disable portable-simd test library/core/tests/lib.rs | 1 - 1 file changed, 1 deletion(-) +diff --git a/library/core/src/lib.rs b/library/core/src/lib.rs +index aa1ad93..95fbf55 100644 +--- a/library/core/src/lib.rs ++++ b/library/core/src/lib.rs +@@ -398,25 +398,4 @@ pub mod arch { + } + } + +-// Pull in the `core_simd` crate directly into libcore. The contents of +-// `core_simd` are in a different repository: rust-lang/portable-simd. +-// +-// `core_simd` depends on libcore, but the contents of this module are +-// set up in such a way that directly pulling it here works such that the +-// crate uses this crate as its libcore. +-#[path = "../../portable-simd/crates/core_simd/src/mod.rs"] +-#[allow(missing_debug_implementations, dead_code, unsafe_op_in_unsafe_fn, unused_unsafe)] +-#[allow(rustdoc::bare_urls)] +-#[unstable(feature = "portable_simd", issue = "86656")] +-#[cfg(not(all(miri, doctest)))] // Miri does not support all SIMD intrinsics +-mod core_simd; +- +-#[doc = include_str!("../../portable-simd/crates/core_simd/src/core_simd_docs.md")] +-#[unstable(feature = "portable_simd", issue = "86656")] +-#[cfg(not(all(miri, doctest)))] // Miri does not support all SIMD intrinsics +-pub mod simd { +- #[unstable(feature = "portable_simd", issue = "86656")] +- pub use crate::core_simd::simd::*; +-} +- + include!("primitive_docs.rs"); +diff --git a/library/core/src/slice/mod.rs b/library/core/src/slice/mod.rs +index cd38c3a..ad632dc 100644 +--- a/library/core/src/slice/mod.rs ++++ b/library/core/src/slice/mod.rs +@@ -17,7 +17,6 @@ use crate::ptr; + use crate::result::Result; + use crate::result::Result::{Err, Ok}; + #[cfg(not(miri))] // Miri does not support all SIMD intrinsics +-use crate::simd::{self, Simd}; + use crate::slice; + + #[unstable( +@@ -3475,123 +3474,6 @@ impl [T] { + } + } + +- /// Split a slice into a prefix, a middle of aligned SIMD types, and a suffix. +- /// +- /// This is a safe wrapper around [`slice::align_to`], so has the same weak +- /// postconditions as that method. You're only assured that +- /// `self.len() == prefix.len() + middle.len() * LANES + suffix.len()`. +- /// +- /// Notably, all of the following are possible: +- /// - `prefix.len() >= LANES`. +- /// - `middle.is_empty()` despite `self.len() >= 3 * LANES`. +- /// - `suffix.len() >= LANES`. +- /// +- /// That said, this is a safe method, so if you're only writing safe code, +- /// then this can at most cause incorrect logic, not unsoundness. +- /// +- /// # Panics +- /// +- /// This will panic if the size of the SIMD type is different from +- /// `LANES` times that of the scalar. +- /// +- /// At the time of writing, the trait restrictions on `Simd` keeps +- /// that from ever happening, as only power-of-two numbers of lanes are +- /// supported. It's possible that, in the future, those restrictions might +- /// be lifted in a way that would make it possible to see panics from this +- /// method for something like `LANES == 3`. +- /// +- /// # Examples +- /// +- /// ``` +- /// #![feature(portable_simd)] +- /// +- /// let short = &[1, 2, 3]; +- /// let (prefix, middle, suffix) = short.as_simd::<4>(); +- /// assert_eq!(middle, []); // Not enough elements for anything in the middle +- /// +- /// // They might be split in any possible way between prefix and suffix +- /// let it = prefix.iter().chain(suffix).copied(); +- /// assert_eq!(it.collect::>(), vec![1, 2, 3]); +- /// +- /// fn basic_simd_sum(x: &[f32]) -> f32 { +- /// use std::ops::Add; +- /// use std::simd::f32x4; +- /// let (prefix, middle, suffix) = x.as_simd(); +- /// let sums = f32x4::from_array([ +- /// prefix.iter().copied().sum(), +- /// 0.0, +- /// 0.0, +- /// suffix.iter().copied().sum(), +- /// ]); +- /// let sums = middle.iter().copied().fold(sums, f32x4::add); +- /// sums.horizontal_sum() +- /// } +- /// +- /// let numbers: Vec = (1..101).map(|x| x as _).collect(); +- /// assert_eq!(basic_simd_sum(&numbers[1..99]), 4949.0); +- /// ``` +- #[unstable(feature = "portable_simd", issue = "86656")] +- #[cfg(not(miri))] // Miri does not support all SIMD intrinsics +- pub fn as_simd(&self) -> (&[T], &[Simd], &[T]) +- where +- Simd: AsRef<[T; LANES]>, +- T: simd::SimdElement, +- simd::LaneCount: simd::SupportedLaneCount, +- { +- // These are expected to always match, as vector types are laid out like +- // arrays per , but we +- // might as well double-check since it'll optimize away anyhow. +- assert_eq!(mem::size_of::>(), mem::size_of::<[T; LANES]>()); +- +- // SAFETY: The simd types have the same layout as arrays, just with +- // potentially-higher alignment, so the de-facto transmutes are sound. +- unsafe { self.align_to() } +- } +- +- /// Split a slice into a prefix, a middle of aligned SIMD types, and a suffix. +- /// +- /// This is a safe wrapper around [`slice::align_to_mut`], so has the same weak +- /// postconditions as that method. You're only assured that +- /// `self.len() == prefix.len() + middle.len() * LANES + suffix.len()`. +- /// +- /// Notably, all of the following are possible: +- /// - `prefix.len() >= LANES`. +- /// - `middle.is_empty()` despite `self.len() >= 3 * LANES`. +- /// - `suffix.len() >= LANES`. +- /// +- /// That said, this is a safe method, so if you're only writing safe code, +- /// then this can at most cause incorrect logic, not unsoundness. +- /// +- /// This is the mutable version of [`slice::as_simd`]; see that for examples. +- /// +- /// # Panics +- /// +- /// This will panic if the size of the SIMD type is different from +- /// `LANES` times that of the scalar. +- /// +- /// At the time of writing, the trait restrictions on `Simd` keeps +- /// that from ever happening, as only power-of-two numbers of lanes are +- /// supported. It's possible that, in the future, those restrictions might +- /// be lifted in a way that would make it possible to see panics from this +- /// method for something like `LANES == 3`. +- #[unstable(feature = "portable_simd", issue = "86656")] +- #[cfg(not(miri))] // Miri does not support all SIMD intrinsics +- pub fn as_simd_mut(&mut self) -> (&mut [T], &mut [Simd], &mut [T]) +- where +- Simd: AsMut<[T; LANES]>, +- T: simd::SimdElement, +- simd::LaneCount: simd::SupportedLaneCount, +- { +- // These are expected to always match, as vector types are laid out like +- // arrays per , but we +- // might as well double-check since it'll optimize away anyhow. +- assert_eq!(mem::size_of::>(), mem::size_of::<[T; LANES]>()); +- +- // SAFETY: The simd types have the same layout as arrays, just with +- // potentially-higher alignment, so the de-facto transmutes are sound. +- unsafe { self.align_to_mut() } +- } +- + /// Checks if the elements of this slice are sorted. + /// + /// That is, for each element `a` and its following element `b`, `a <= b` must hold. If the diff --git a/library/core/tests/lib.rs b/library/core/tests/lib.rs -index ec70034..7cd9e21 100644 +index 06c7be0..359e2e7 100644 --- a/library/core/tests/lib.rs +++ b/library/core/tests/lib.rs -@@ -121,7 +121,6 @@ mod pattern; - mod pin; +@@ -75,7 +75,6 @@ + #![feature(never_type)] + #![feature(unwrap_infallible)] + #![feature(result_into_ok_or_err)] +-#![feature(portable_simd)] + #![feature(ptr_metadata)] + #![feature(once_cell)] + #![feature(option_result_contains)] +@@ -127,7 +126,6 @@ mod pin; + mod pin_macro; mod ptr; mod result; -mod simd; mod slice; mod str; mod str_lossy; --- +diff --git a/library/std/src/lib.rs b/library/std/src/lib.rs +index 5dc586d..b6fc48f 100644 +--- a/library/std/src/lib.rs ++++ b/library/std/src/lib.rs +@@ -312,7 +312,6 @@ + #![feature(panic_can_unwind)] + #![feature(panic_unwind)] + #![feature(platform_intrinsics)] +-#![feature(portable_simd)] + #![feature(prelude_import)] + #![feature(ptr_as_uninit)] + #![feature(ptr_internals)] +@@ -508,25 +508,6 @@ pub mod time; + #[unstable(feature = "once_cell", issue = "74465")] + pub mod lazy; + +-// Pull in `std_float` crate into libstd. The contents of +-// `std_float` are in a different repository: rust-lang/portable-simd. +-#[path = "../../portable-simd/crates/std_float/src/lib.rs"] +-#[allow(missing_debug_implementations, dead_code, unsafe_op_in_unsafe_fn, unused_unsafe)] +-#[allow(rustdoc::bare_urls)] +-#[unstable(feature = "portable_simd", issue = "86656")] +-#[cfg(not(all(miri, doctest)))] // Miri does not support all SIMD intrinsics +-mod std_float; +- +-#[cfg(not(all(miri, doctest)))] // Miri does not support all SIMD intrinsics +-#[doc = include_str!("../../portable-simd/crates/core_simd/src/core_simd_docs.md")] +-#[unstable(feature = "portable_simd", issue = "86656")] +-pub mod simd { +- #[doc(inline)] +- pub use crate::std_float::StdFloat; +- #[doc(inline)] +- pub use core::simd::*; +-} +- + #[stable(feature = "futures_api", since = "1.36.0")] + pub mod task { + //! Types and Traits for working with asynchronous tasks. +-- 2.26.2.7.g19db9cfb68 diff --git a/rust-toolchain b/rust-toolchain index bf316efc324b..f2d80b78313d 100644 --- a/rust-toolchain +++ b/rust-toolchain @@ -1,3 +1,3 @@ [toolchain] -channel = "nightly-2022-01-30" +channel = "nightly-2022-02-25" components = ["rust-src", "rustc-dev", "llvm-tools-preview"] From ff6b398f1b8c4b09b716742d7050c6d3c1d7252f Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Fri, 25 Feb 2022 15:19:52 +0100 Subject: [PATCH 029/356] Use bx.switch_to_block where possible --- src/builder.rs | 9 +++------ src/int.rs | 6 ++---- src/intrinsic/mod.rs | 12 ++++-------- 3 files changed, 9 insertions(+), 18 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index c52ab12e56b2..f978ba3b7d05 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -116,8 +116,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { // NOTE: since jumps were added and compare_exchange doesn't expect this, the current blocks in the // state need to be updated. - self.block = Some(while_block); - *self.cx.current_block.borrow_mut() = Some(while_block); + self.switch_to_block(while_block); let comparison_operator = match operation { @@ -134,8 +133,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { // NOTE: since jumps were added in a place rustc does not expect, the current blocks in the // state need to be updated. - self.block = Some(after_block); - *self.cx.current_block.borrow_mut() = Some(after_block); + self.switch_to_block(after_block); return_value.to_rvalue() } @@ -1021,8 +1019,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { // NOTE: since jumps were added in a place rustc does not expect, the current blocks in the // state need to be updated. - self.block = Some(after_block); - *self.cx.current_block.borrow_mut() = Some(after_block); + self.switch_to_block(after_block); variable.to_rvalue() } diff --git a/src/int.rs b/src/int.rs index a1f28f3f8812..d2df9d2dcb62 100644 --- a/src/int.rs +++ b/src/int.rs @@ -148,8 +148,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { // NOTE: since jumps were added in a place rustc does not expect, the current block in the // state need to be updated. - self.block = Some(after_block); - *self.cx.current_block.borrow_mut() = Some(after_block); + self.switch_to_block(after_block); result.to_rvalue() } @@ -494,8 +493,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { // NOTE: since jumps were added in a place rustc does not expect, the current block in the // state need to be updated. - self.block = Some(after_block); - *self.cx.current_block.borrow_mut() = Some(after_block); + self.switch_to_block(after_block); result.to_rvalue() } diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index 7cd0f944f2f9..c91986a2b2c0 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -186,8 +186,7 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { // NOTE: since jumps were added in a place // count_leading_zeroes() does not expect, the current blocks // in the state need to be updated. - *self.current_block.borrow_mut() = Some(else_block); - self.block = Some(else_block); + self.switch_to_block(else_block); let zeros = match name { @@ -200,8 +199,7 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { // NOTE: since jumps were added in a place rustc does not // expect, the current blocks in the state need to be updated. - *self.current_block.borrow_mut() = Some(after_block); - self.block = Some(after_block); + self.switch_to_block(after_block); result.to_rvalue() } @@ -1003,8 +1001,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { // NOTE: since jumps were added in a place rustc does not // expect, the current blocks in the state need to be updated. - *self.current_block.borrow_mut() = Some(after_block); - self.block = Some(after_block); + self.switch_to_block(after_block); res.to_rvalue() } @@ -1074,8 +1071,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { // NOTE: since jumps were added in a place rustc does not // expect, the current blocks in the state need to be updated. - *self.current_block.borrow_mut() = Some(after_block); - self.block = Some(after_block); + self.switch_to_block(after_block); res.to_rvalue() } From b48ed38482bc2c12edf10e134c24cf9e51481557 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Fri, 25 Feb 2022 15:27:19 +0100 Subject: [PATCH 030/356] Make bx.block non-optional --- src/builder.rs | 62 ++++++++++++++++++++++---------------------------- 1 file changed, 27 insertions(+), 35 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index f978ba3b7d05..0d5b534a1a22 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -80,15 +80,15 @@ impl EnumClone for AtomicOrdering { pub struct Builder<'a: 'gcc, 'gcc, 'tcx> { pub cx: &'a CodegenCx<'gcc, 'tcx>, - pub block: Option>, + pub block: Block<'gcc>, stack_var_count: Cell, } impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { - fn with_cx(cx: &'a CodegenCx<'gcc, 'tcx>) -> Self { + fn with_cx(cx: &'a CodegenCx<'gcc, 'tcx>, block: Block<'gcc>) -> Self { Builder { cx, - block: None, + block, stack_var_count: Cell::new(0), } } @@ -243,7 +243,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { } pub fn current_func(&self) -> Function<'gcc> { - self.block.expect("block").get_function() + self.block.get_function() } fn function_call(&mut self, func: RValue<'gcc>, args: &[RValue<'gcc>], _funclet: Option<&Funclet>) -> RValue<'gcc> { @@ -254,17 +254,16 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { // gccjit requires to use the result of functions, even when it's not used. // That's why we assign the result to a local or call add_eval(). let return_type = func.get_return_type(); - let current_block = self.current_block.borrow().expect("block"); let void_type = self.context.new_type::<()>(); - let current_func = current_block.get_function(); + let current_func = self.block.get_function(); if return_type != void_type { unsafe { RETURN_VALUE_COUNT += 1 }; let result = current_func.new_local(None, return_type, &format!("returnValue{}", unsafe { RETURN_VALUE_COUNT })); - current_block.add_assignment(None, result, self.cx.context.new_call(None, func, &args)); + self.block.add_assignment(None, result, self.cx.context.new_call(None, func, &args)); result.to_rvalue() } else { - current_block.add_eval(None, self.cx.context.new_call(None, func, &args)); + self.block.add_eval(None, self.cx.context.new_call(None, func, &args)); // Return dummy value when not having return value. self.context.new_rvalue_from_long(self.isize_type, 0) } @@ -277,9 +276,8 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { // That's why we assign the result to a local or call add_eval(). let gcc_func = func_ptr.get_type().dyncast_function_ptr_type().expect("function ptr"); let mut return_type = gcc_func.get_return_type(); - let current_block = self.current_block.borrow().expect("block"); let void_type = self.context.new_type::<()>(); - let current_func = current_block.get_function(); + let current_func = self.block.get_function(); // FIXME(antoyo): As a temporary workaround for unsupported LLVM intrinsics. if gcc_func.get_param_count() == 0 && format!("{:?}", func_ptr) == "__builtin_ia32_pmovmskb128" { @@ -289,20 +287,20 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { if return_type != void_type { unsafe { RETURN_VALUE_COUNT += 1 }; let result = current_func.new_local(None, return_type, &format!("ptrReturnValue{}", unsafe { RETURN_VALUE_COUNT })); - current_block.add_assignment(None, result, self.cx.context.new_call_through_ptr(None, func_ptr, &args)); + self.block.add_assignment(None, result, self.cx.context.new_call_through_ptr(None, func_ptr, &args)); result.to_rvalue() } else { if gcc_func.get_param_count() == 0 { // FIXME(antoyo): As a temporary workaround for unsupported LLVM intrinsics. - current_block.add_eval(None, self.cx.context.new_call_through_ptr(None, func_ptr, &[])); + self.block.add_eval(None, self.cx.context.new_call_through_ptr(None, func_ptr, &[])); } else { - current_block.add_eval(None, self.cx.context.new_call_through_ptr(None, func_ptr, &args)); + self.block.add_eval(None, self.cx.context.new_call_through_ptr(None, func_ptr, &args)); } // Return dummy value when not having return value. let result = current_func.new_local(None, self.isize_type, "dummyValueThatShouldNeverBeUsed"); - current_block.add_assignment(None, result, self.context.new_rvalue_from_long(self.isize_type, 0)); + self.block.add_assignment(None, result, self.context.new_rvalue_from_long(self.isize_type, 0)); result.to_rvalue() } } @@ -311,12 +309,11 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { // gccjit requires to use the result of functions, even when it's not used. // That's why we assign the result to a local. let return_type = self.context.new_type::(); - let current_block = self.current_block.borrow().expect("block"); - let current_func = current_block.get_function(); + let current_func = self.block.get_function(); // TODO(antoyo): return the new_call() directly? Since the overflow function has no side-effects. unsafe { RETURN_VALUE_COUNT += 1 }; let result = current_func.new_local(None, return_type, &format!("overflowReturnValue{}", unsafe { RETURN_VALUE_COUNT })); - current_block.add_assignment(None, result, self.cx.context.new_call(None, func, &args)); + self.block.add_assignment(None, result, self.cx.context.new_call(None, func, &args)); result.to_rvalue() } } @@ -382,14 +379,13 @@ impl<'gcc, 'tcx> BackendTypes for Builder<'_, 'gcc, 'tcx> { impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { fn build(cx: &'a CodegenCx<'gcc, 'tcx>, block: Block<'gcc>) -> Self { - let mut bx = Builder::with_cx(cx); + let bx = Builder::with_cx(cx, block); *cx.current_block.borrow_mut() = Some(block); - bx.block = Some(block); bx } fn llbb(&self) -> Block<'gcc> { - self.block.expect("block") + self.block } fn append_block(cx: &'a CodegenCx<'gcc, 'tcx>, func: RValue<'gcc>, name: &str) -> Block<'gcc> { @@ -404,7 +400,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { fn switch_to_block(&mut self, block: Self::BasicBlock) { *self.cx.current_block.borrow_mut() = Some(block); - self.block = Some(block); + self.block = block; } fn ret_void(&mut self) { @@ -439,7 +435,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { let on_val = self.const_uint_big(typ, on_val); gcc_cases.push(self.context.new_case(on_val, on_val, dest)); } - self.block.expect("block").end_with_switch(None, value, default_block, &gcc_cases); + self.block.end_with_switch(None, value, default_block, &gcc_cases); } fn invoke(&mut self, _typ: Type<'gcc>, _func: RValue<'gcc>, _args: &[RValue<'gcc>], then: Block<'gcc>, catch: Block<'gcc>, _funclet: Option<&Funclet>) -> RValue<'gcc> { @@ -452,17 +448,16 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { fn unreachable(&mut self) { let func = self.context.get_builtin_function("__builtin_unreachable"); - let block = self.block.expect("block"); - block.add_eval(None, self.context.new_call(None, func, &[])); - let return_type = block.get_function().get_return_type(); + self.block.add_eval(None, self.context.new_call(None, func, &[])); + let return_type = self.block.get_function().get_return_type(); let void_type = self.context.new_type::<()>(); if return_type == void_type { - block.end_with_void_return(None) + self.block.end_with_void_return(None) } else { let return_value = self.current_func() .new_local(None, return_type, "unreachableReturn"); - block.end_with_return(None, return_value) + self.block.end_with_return(None, return_value) } } @@ -909,11 +904,11 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn ptrtoint(&mut self, value: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { - self.cx.ptrtoint(self.block.expect("block"), value, dest_ty) + self.cx.ptrtoint(self.block, value, dest_ty) } fn inttoptr(&mut self, value: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { - self.cx.inttoptr(self.block.expect("block"), value, dest_ty) + self.cx.inttoptr(self.block, value, dest_ty) } fn bitcast(&mut self, value: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { @@ -965,9 +960,8 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { let dst = self.pointercast(dst, self.type_i8p()); let src = self.pointercast(src, self.type_ptr_to(self.type_void())); let memcpy = self.context.get_builtin_function("memcpy"); - let block = self.block.expect("block"); // TODO(antoyo): handle aligns and is_volatile. - block.add_eval(None, self.context.new_call(None, memcpy, &[dst, src, size])); + self.block.add_eval(None, self.context.new_call(None, memcpy, &[dst, src, size])); } fn memmove(&mut self, dst: RValue<'gcc>, dst_align: Align, src: RValue<'gcc>, src_align: Align, size: RValue<'gcc>, flags: MemFlags) { @@ -984,20 +978,18 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { let src = self.pointercast(src, self.type_ptr_to(self.type_void())); let memmove = self.context.get_builtin_function("memmove"); - let block = self.block.expect("block"); // TODO(antoyo): handle is_volatile. - block.add_eval(None, self.context.new_call(None, memmove, &[dst, src, size])); + self.block.add_eval(None, self.context.new_call(None, memmove, &[dst, src, size])); } fn memset(&mut self, ptr: RValue<'gcc>, fill_byte: RValue<'gcc>, size: RValue<'gcc>, _align: Align, flags: MemFlags) { let _is_volatile = flags.contains(MemFlags::VOLATILE); let ptr = self.pointercast(ptr, self.type_i8p()); let memset = self.context.get_builtin_function("memset"); - let block = self.block.expect("block"); // TODO(antoyo): handle align and is_volatile. let fill_byte = self.context.new_cast(None, fill_byte, self.i32_type); let size = self.intcast(size, self.type_size_t(), false); - block.add_eval(None, self.context.new_call(None, memset, &[ptr, fill_byte, size])); + self.block.add_eval(None, self.context.new_call(None, memset, &[ptr, fill_byte, size])); } fn select(&mut self, cond: RValue<'gcc>, then_val: RValue<'gcc>, mut else_val: RValue<'gcc>) -> RValue<'gcc> { From 07afdb8c0d78e1a83757b87332f6c55004d65189 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Fri, 25 Feb 2022 15:36:08 +0100 Subject: [PATCH 031/356] Use bitcast for ptrtoint and inttoptr This works now --- src/builder.rs | 5 +++-- src/common.rs | 29 ++--------------------------- 2 files changed, 5 insertions(+), 29 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index 0d5b534a1a22..f5ee9db80a02 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -904,11 +904,12 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn ptrtoint(&mut self, value: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { - self.cx.ptrtoint(self.block, value, dest_ty) + let usize_value = self.cx.const_bitcast(value, self.cx.type_isize()); + self.intcast(usize_value, dest_ty, false) } fn inttoptr(&mut self, value: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { - self.cx.inttoptr(self.block, value, dest_ty) + self.cx.const_bitcast(value, dest_ty) } fn bitcast(&mut self, value: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { diff --git a/src/common.rs b/src/common.rs index 89a3dc052d83..840cbc70c340 100644 --- a/src/common.rs +++ b/src/common.rs @@ -1,5 +1,5 @@ use gccjit::LValue; -use gccjit::{Block, RValue, Type, ToRValue}; +use gccjit::{RValue, Type, ToRValue}; use rustc_codegen_ssa::mir::place::PlaceRef; use rustc_codegen_ssa::traits::{ BaseTypeMethods, @@ -45,27 +45,6 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { global // TODO(antoyo): set linkage. } - - pub fn inttoptr(&self, block: Block<'gcc>, value: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { - let func = block.get_function(); - let local = func.new_local(None, value.get_type(), "intLocal"); - block.add_assignment(None, local, value); - let value_address = local.get_address(None); - - let ptr = self.context.new_cast(None, value_address, dest_ty.make_pointer()); - ptr.dereference(None).to_rvalue() - } - - pub fn ptrtoint(&self, block: Block<'gcc>, value: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { - // TODO(antoyo): when libgccjit allow casting from pointer to int, remove this. - let func = block.get_function(); - let local = func.new_local(None, value.get_type(), "ptrLocal"); - block.add_assignment(None, local, value); - let ptr_address = local.get_address(None); - - let ptr = self.context.new_cast(None, ptr_address, dest_ty.make_pointer()); - ptr.dereference(None).to_rvalue() - } } pub fn bytes_in_context<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, bytes: &[u8]) -> RValue<'gcc> { @@ -202,11 +181,7 @@ impl<'gcc, 'tcx> ConstMethods<'tcx> for CodegenCx<'gcc, 'tcx> { } let value = self.const_uint_big(self.type_ix(bitsize), data); - if layout.value == Pointer { - self.inttoptr(self.current_block.borrow().expect("block"), value, ty) - } else { - self.const_bitcast(value, ty) - } + self.const_bitcast(value, ty) } Scalar::Ptr(ptr, _size) => { let (alloc_id, offset) = ptr.into_parts(); From 62e9b50f8d894cad16bf514241e1f65bdf582022 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Fri, 25 Feb 2022 15:38:23 +0100 Subject: [PATCH 032/356] Remove current_block field of CodegenCx This field often had the wrong value when using multiple builders at the same time. --- src/builder.rs | 5 +---- src/context.rs | 4 +--- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index f5ee9db80a02..0b673f3e91be 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -379,9 +379,7 @@ impl<'gcc, 'tcx> BackendTypes for Builder<'_, 'gcc, 'tcx> { impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { fn build(cx: &'a CodegenCx<'gcc, 'tcx>, block: Block<'gcc>) -> Self { - let bx = Builder::with_cx(cx, block); - *cx.current_block.borrow_mut() = Some(block); - bx + Builder::with_cx(cx, block) } fn llbb(&self) -> Block<'gcc> { @@ -399,7 +397,6 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn switch_to_block(&mut self, block: Self::BasicBlock) { - *self.cx.current_block.borrow_mut() = Some(block); self.block = block; } diff --git a/src/context.rs b/src/context.rs index 795966d81830..91259836f6d9 100644 --- a/src/context.rs +++ b/src/context.rs @@ -31,8 +31,7 @@ pub struct CodegenCx<'gcc, 'tcx> { pub codegen_unit: &'tcx CodegenUnit<'tcx>, pub context: &'gcc Context<'gcc>, - // TODO(antoyo): First set it to a dummy block to avoid using Option? - pub current_block: RefCell>>, + // TODO(bjorn3): First set it to a dummy function to avoid using Option? pub current_func: RefCell>>, pub normal_function_addresses: RefCell>>, @@ -177,7 +176,6 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { check_overflow, codegen_unit, context, - current_block: RefCell::new(None), current_func: RefCell::new(None), normal_function_addresses: Default::default(), functions: RefCell::new(functions), From a7c1c47c8344d9d567968866db7232713b6b8902 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Fri, 25 Feb 2022 17:25:32 +0100 Subject: [PATCH 033/356] Fix review comments --- src/builder.rs | 11 ++++++++--- src/intrinsic/mod.rs | 8 ++++---- 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index 0b673f3e91be..d3513ddde483 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -114,7 +114,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let after_block = func.new_block("after_while"); self.llbb().end_with_jump(None, while_block); - // NOTE: since jumps were added and compare_exchange doesn't expect this, the current blocks in the + // NOTE: since jumps were added and compare_exchange doesn't expect this, the current block in the // state need to be updated. self.switch_to_block(while_block); @@ -131,7 +131,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { while_block.end_with_conditional(None, cond, while_block, after_block); - // NOTE: since jumps were added in a place rustc does not expect, the current blocks in the + // NOTE: since jumps were added in a place rustc does not expect, the current block in the // state need to be updated. self.switch_to_block(after_block); @@ -906,6 +906,11 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn inttoptr(&mut self, value: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { + assert_eq!( + value.get_type(), + self.cx.type_isize(), + "cg_ssa currently only calls this function with an isize argument", + ); self.cx.const_bitcast(value, dest_ty) } @@ -1007,7 +1012,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { else_block.add_assignment(None, variable, else_val); else_block.end_with_jump(None, after_block); - // NOTE: since jumps were added in a place rustc does not expect, the current blocks in the + // NOTE: since jumps were added in a place rustc does not expect, the current block in the // state need to be updated. self.switch_to_block(after_block); diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index c91986a2b2c0..81f841e72cf7 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -184,7 +184,7 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { then_block.end_with_jump(None, after_block); // NOTE: since jumps were added in a place - // count_leading_zeroes() does not expect, the current blocks + // count_leading_zeroes() does not expect, the current block // in the state need to be updated. self.switch_to_block(else_block); @@ -198,7 +198,7 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { self.llbb().end_with_jump(None, after_block); // NOTE: since jumps were added in a place rustc does not - // expect, the current blocks in the state need to be updated. + // expect, the current block in the state need to be updated. self.switch_to_block(after_block); result.to_rvalue() @@ -1000,7 +1000,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { self.llbb().end_with_conditional(None, overflow, then_block, after_block); // NOTE: since jumps were added in a place rustc does not - // expect, the current blocks in the state need to be updated. + // expect, the current block in the state need to be updated. self.switch_to_block(after_block); res.to_rvalue() @@ -1070,7 +1070,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { self.llbb().end_with_conditional(None, overflow, then_block, after_block); // NOTE: since jumps were added in a place rustc does not - // expect, the current blocks in the state need to be updated. + // expect, the current block in the state need to be updated. self.switch_to_block(after_block); res.to_rvalue() From 3e35fab71e5b4fe3cc1aa5330c1fd9208ace0dd9 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Sat, 26 Feb 2022 09:41:37 +0100 Subject: [PATCH 034/356] Fix inttoptr --- src/builder.rs | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index d3513ddde483..580996fdefc8 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -906,12 +906,8 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn inttoptr(&mut self, value: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { - assert_eq!( - value.get_type(), - self.cx.type_isize(), - "cg_ssa currently only calls this function with an isize argument", - ); - self.cx.const_bitcast(value, dest_ty) + let usize_value = self.intcast(value, self.cx.type_isize(), false); + self.cx.const_bitcast(usize_value, dest_ty) } fn bitcast(&mut self, value: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { From 9d098424cd772ab067b0f8ecb67a7eadbe9d028c Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Sat, 26 Feb 2022 18:29:23 +0100 Subject: [PATCH 035/356] Add and change a TODO --- src/common.rs | 1 + src/context.rs | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/common.rs b/src/common.rs index 840cbc70c340..e36e5bb2382d 100644 --- a/src/common.rs +++ b/src/common.rs @@ -181,6 +181,7 @@ impl<'gcc, 'tcx> ConstMethods<'tcx> for CodegenCx<'gcc, 'tcx> { } let value = self.const_uint_big(self.type_ix(bitsize), data); + // TODO(bjorn3): assert size is correct self.const_bitcast(value, ty) } Scalar::Ptr(ptr, _size) => { diff --git a/src/context.rs b/src/context.rs index 91259836f6d9..d20356b12664 100644 --- a/src/context.rs +++ b/src/context.rs @@ -31,7 +31,7 @@ pub struct CodegenCx<'gcc, 'tcx> { pub codegen_unit: &'tcx CodegenUnit<'tcx>, pub context: &'gcc Context<'gcc>, - // TODO(bjorn3): First set it to a dummy function to avoid using Option? + // TODO(bjorn3): Can this field be removed? pub current_func: RefCell>>, pub normal_function_addresses: RefCell>>, From f7063174a4681b8194d7e2e48305d59ccf98b795 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Sat, 26 Feb 2022 10:13:56 +0100 Subject: [PATCH 036/356] Support -Cpanic=unwind without unwinding --- src/builder.rs | 15 ++++++++------- src/intrinsic/mod.rs | 4 +++- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index 580996fdefc8..f1c9d0a78170 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -435,12 +435,12 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { self.block.end_with_switch(None, value, default_block, &gcc_cases); } - fn invoke(&mut self, _typ: Type<'gcc>, _func: RValue<'gcc>, _args: &[RValue<'gcc>], then: Block<'gcc>, catch: Block<'gcc>, _funclet: Option<&Funclet>) -> RValue<'gcc> { - let condition = self.context.new_rvalue_from_int(self.bool_type, 0); + fn invoke(&mut self, typ: Type<'gcc>, func: RValue<'gcc>, args: &[RValue<'gcc>], then: Block<'gcc>, catch: Block<'gcc>, _funclet: Option<&Funclet>) -> RValue<'gcc> { + // TODO(bjorn3): Properly implement unwinding. + let call_site = self.call(typ, func, args, None); + let condition = self.context.new_rvalue_from_int(self.bool_type, 1); self.llbb().end_with_conditional(None, condition, then, catch); - self.context.new_rvalue_from_int(self.int_type, 0) - - // TODO(antoyo) + call_site } fn unreachable(&mut self) { @@ -1106,7 +1106,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn cleanup_landing_pad(&mut self, _ty: Type<'gcc>, _pers_fn: RValue<'gcc>) -> RValue<'gcc> { - let field1 = self.context.new_field(None, self.u8_type, "landing_pad_field_1"); + let field1 = self.context.new_field(None, self.u8_type.make_pointer(), "landing_pad_field_1"); let field2 = self.context.new_field(None, self.i32_type, "landing_pad_field_1"); let struct_type = self.context.new_struct_type(None, "landing_pad", &[field1, field2]); self.current_func().new_local(None, struct_type.as_type(), "landing_pad") @@ -1117,7 +1117,8 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn resume(&mut self, _exn: RValue<'gcc>) { - unimplemented!(); + // TODO(bjorn3): Properly implement unwinding. + self.unreachable(); } fn cleanup_pad(&mut self, _parent: Option>, _args: &[RValue<'gcc>]) -> Funclet { diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index 81f841e72cf7..5e3eef67df5a 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -1086,7 +1086,9 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { } fn try_intrinsic<'gcc, 'tcx>(bx: &mut Builder<'_, 'gcc, 'tcx>, try_func: RValue<'gcc>, data: RValue<'gcc>, _catch_func: RValue<'gcc>, dest: RValue<'gcc>) { - if bx.sess().panic_strategy() == PanicStrategy::Abort { + // NOTE: the `|| true` here is to use the panic=abort strategy with panic=unwind too + if bx.sess().panic_strategy() == PanicStrategy::Abort || true { + // TODO(bjorn3): Properly implement unwinding and remove the `|| true` once this is done. bx.call(bx.type_void(), try_func, &[data], None); // Return 0 unconditionally from the intrinsic call; // we can never unwind. From ac4baf3fd632100e68b5f8830a5c077005eeac23 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Sat, 26 Feb 2022 19:11:58 +0100 Subject: [PATCH 037/356] Allow unreachable blocks for now The cleanup blocks normally executed when unwinding are unreachable for now as unwinding is not yet implemented. --- Cargo.lock | 4 ++-- src/base.rs | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index d4c407b0974f..a4499d0ea8c6 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -41,7 +41,7 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" -source = "git+https://github.com/antoyo/gccjit.rs#cbb07c6601ba4246fc2967c4d770403c57192ca2" +source = "git+https://github.com/antoyo/gccjit.rs#b9f188d2ce2c7b12211e90903f1b2cf309785b85" dependencies = [ "gccjit_sys", ] @@ -49,7 +49,7 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" -source = "git+https://github.com/antoyo/gccjit.rs#cbb07c6601ba4246fc2967c4d770403c57192ca2" +source = "git+https://github.com/antoyo/gccjit.rs#b9f188d2ce2c7b12211e90903f1b2cf309785b85" dependencies = [ "libc 0.1.12", ] diff --git a/src/base.rs b/src/base.rs index 6808993182a0..f5aca35cdcbc 100644 --- a/src/base.rs +++ b/src/base.rs @@ -105,6 +105,9 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ context.set_keep_intermediates(true); } + // TODO(bjorn3): Remove once unwinding is properly implemented + context.set_allow_unreachable_blocks(true); + { let cx = CodegenCx::new(&context, cgu, tcx, supports_128bit_integers); From beb1767842fd06b2c3231bfddbd2b8a2406ea66a Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Sat, 26 Feb 2022 09:59:37 +0100 Subject: [PATCH 038/356] Don't export global allocs which are not statics They aren't be referenced outside of the current cgu anyway. This should make optimizations a bit more effective. --- src/consts.rs | 8 ++------ src/context.rs | 8 -------- src/declare.rs | 8 +++----- 3 files changed, 5 insertions(+), 19 deletions(-) diff --git a/src/consts.rs b/src/consts.rs index 5275667b864f..598bcdc31b6f 100644 --- a/src/consts.rs +++ b/src/consts.rs @@ -170,11 +170,9 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { match kind { Some(kind) if !self.tcx.sess.fewer_names() => { let name = self.generate_local_symbol_name(kind); - // TODO(antoyo): check if it's okay that TLS is off here. - // TODO(antoyo): check if it's okay that link_section is None here. + // TODO(antoyo): check if it's okay that no link_section is set. // TODO(antoyo): set alignment here as well. - let global = self.define_global(&name[..], self.val_ty(cv), false, None); - // TODO(antoyo): set linkage. + let global = self.declare_private_global(&name[..], self.val_ty(cv)); global } _ => { @@ -183,8 +181,6 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { global }, }; - // FIXME(antoyo): I think the name coming from generate_local_symbol_name() above cannot be used - // globally. global.global_set_initializer_rvalue(cv); // TODO(antoyo): set unnamed address. let rvalue = global.get_address(None); diff --git a/src/context.rs b/src/context.rs index d20356b12664..fa556b0b7f2f 100644 --- a/src/context.rs +++ b/src/context.rs @@ -18,7 +18,6 @@ use rustc_target::abi::{call::FnAbi, HasDataLayout, PointeeInfo, Size, TargetDat use rustc_target::spec::{HasTargetSpec, Target, TlsModel}; use crate::callee::get_fn; -use crate::declare::mangle_name; #[derive(Clone)] pub struct FuncSig<'gcc> { @@ -96,7 +95,6 @@ pub struct CodegenCx<'gcc, 'tcx> { /// A counter that is used for generating local symbol names local_gen_sym_counter: Cell, - pub global_gen_sym_counter: Cell, eh_personality: Cell>>, @@ -221,7 +219,6 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { struct_types: Default::default(), types_with_fields_to_set: Default::default(), local_gen_sym_counter: Cell::new(0), - global_gen_sym_counter: Cell::new(0), eh_personality: Cell::new(None), pointee_infos: Default::default(), structs_as_pointer: Default::default(), @@ -503,11 +500,6 @@ impl<'b, 'tcx> CodegenCx<'b, 'tcx> { } } -pub fn unit_name<'tcx>(codegen_unit: &CodegenUnit<'tcx>) -> String { - let name = &codegen_unit.name().to_string(); - mangle_name(&name.replace('-', "_")) -} - fn to_gcc_tls_mode(tls_model: TlsModel) -> gccjit::TlsModel { match tls_model { TlsModel::GeneralDynamic => gccjit::TlsModel::GlobalDynamic, diff --git a/src/declare.rs b/src/declare.rs index ec6f8ea4dde0..4bd7a17381d0 100644 --- a/src/declare.rs +++ b/src/declare.rs @@ -5,7 +5,7 @@ use rustc_span::Symbol; use rustc_target::abi::call::FnAbi; use crate::abi::FnAbiGccExt; -use crate::context::{CodegenCx, unit_name}; +use crate::context::CodegenCx; use crate::intrinsic::llvm; impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { @@ -27,10 +27,8 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { } pub fn declare_unnamed_global(&self, ty: Type<'gcc>) -> LValue<'gcc> { - let index = self.global_gen_sym_counter.get(); - self.global_gen_sym_counter.set(index + 1); - let name = format!("global_{}_{}", index, unit_name(&self.codegen_unit)); - self.context.new_global(None, GlobalKind::Exported, ty, &name) + let name = self.generate_local_symbol_name("global"); + self.context.new_global(None, GlobalKind::Internal, ty, &name) } pub fn declare_global_with_linkage(&self, name: &str, ty: Type<'gcc>, linkage: GlobalKind) -> LValue<'gcc> { From dcc0853a34325b0a928ce6cbbbf184423ceaff25 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 27 Feb 2022 13:46:57 -0500 Subject: [PATCH 039/356] Add support for on_stack parameters --- Cargo.lock | 4 ++-- src/abi.rs | 37 ++++++++++++++++++++++++++++--------- src/builder.rs | 25 +++++++++++++++---------- src/context.rs | 10 +++++++++- src/declare.rs | 3 ++- src/intrinsic/mod.rs | 10 +++++----- 6 files changed, 61 insertions(+), 28 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index a4499d0ea8c6..a1d9f2f5e382 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -41,7 +41,7 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" -source = "git+https://github.com/antoyo/gccjit.rs#b9f188d2ce2c7b12211e90903f1b2cf309785b85" +source = "git+https://github.com/antoyo/gccjit.rs#bdecdecfb8a02ec861a39a350f990faa33bd31c3" dependencies = [ "gccjit_sys", ] @@ -49,7 +49,7 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" -source = "git+https://github.com/antoyo/gccjit.rs#b9f188d2ce2c7b12211e90903f1b2cf309785b85" +source = "git+https://github.com/antoyo/gccjit.rs#bdecdecfb8a02ec861a39a350f990faa33bd31c3" dependencies = [ "libc 0.1.12", ] diff --git a/src/abi.rs b/src/abi.rs index a8b1e70e2bb8..2c796d0f69e5 100644 --- a/src/abi.rs +++ b/src/abi.rs @@ -1,5 +1,6 @@ -use gccjit::{ToRValue, Type}; +use gccjit::{ToLValue, ToRValue, Type}; use rustc_codegen_ssa::traits::{AbiBuilderMethods, BaseTypeMethods}; +use rustc_data_structures::stable_set::FxHashSet; use rustc_middle::bug; use rustc_middle::ty::Ty; use rustc_target::abi::call::{CastTarget, FnAbi, PassMode, Reg, RegKind}; @@ -15,9 +16,21 @@ impl<'a, 'gcc, 'tcx> AbiBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { } fn get_param(&mut self, index: usize) -> Self::Value { - self.cx.current_func.borrow().expect("current func") - .get_param(index as i32) - .to_rvalue() + let func = self.current_func(); + let param = func.get_param(index as i32); + let on_stack = + if let Some(on_stack_param_indices) = self.on_stack_function_params.borrow().get(&func) { + on_stack_param_indices.contains(&index) + } + else { + false + }; + if on_stack { + param.to_lvalue().get_address(None) + } + else { + param.to_rvalue() + } } } @@ -87,12 +100,13 @@ impl GccType for Reg { pub trait FnAbiGccExt<'gcc, 'tcx> { // TODO(antoyo): return a function pointer type instead? - fn gcc_type(&self, cx: &CodegenCx<'gcc, 'tcx>) -> (Type<'gcc>, Vec>, bool); + fn gcc_type(&self, cx: &CodegenCx<'gcc, 'tcx>) -> (Type<'gcc>, Vec>, bool, FxHashSet); fn ptr_to_gcc_type(&self, cx: &CodegenCx<'gcc, 'tcx>) -> Type<'gcc>; } impl<'gcc, 'tcx> FnAbiGccExt<'gcc, 'tcx> for FnAbi<'tcx, Ty<'tcx>> { - fn gcc_type(&self, cx: &CodegenCx<'gcc, 'tcx>) -> (Type<'gcc>, Vec>, bool) { + fn gcc_type(&self, cx: &CodegenCx<'gcc, 'tcx>) -> (Type<'gcc>, Vec>, bool, FxHashSet) { + let mut on_stack_param_indices = FxHashSet::default(); let args_capacity: usize = self.args.iter().map(|arg| if arg.pad.is_some() { 1 @@ -144,17 +158,22 @@ impl<'gcc, 'tcx> FnAbiGccExt<'gcc, 'tcx> for FnAbi<'tcx, Ty<'tcx>> { unimplemented!(); } PassMode::Cast(cast) => cast.gcc_type(cx), - PassMode::Indirect { extra_attrs: None, .. } => cx.type_ptr_to(arg.memory_ty(cx)), + PassMode::Indirect { extra_attrs: None, on_stack: true, .. } => { + on_stack_param_indices.insert(argument_tys.len()); + arg.memory_ty(cx) + }, + PassMode::Indirect { extra_attrs: None, on_stack: false, .. } => cx.type_ptr_to(arg.memory_ty(cx)), }; argument_tys.push(arg_ty); } - (return_ty, argument_tys, self.c_variadic) + (return_ty, argument_tys, self.c_variadic, on_stack_param_indices) } fn ptr_to_gcc_type(&self, cx: &CodegenCx<'gcc, 'tcx>) -> Type<'gcc> { - let (return_type, params, variadic) = self.gcc_type(cx); + let (return_type, params, variadic, on_stack_param_indices) = self.gcc_type(cx); let pointer_type = cx.context.new_function_pointer_type(None, return_type, ¶ms, variadic); + cx.on_stack_params.borrow_mut().insert(pointer_type.dyncast_function_ptr_type().expect("function ptr type"), on_stack_param_indices); pointer_type } } diff --git a/src/builder.rs b/src/builder.rs index f1c9d0a78170..4aa9b5341fe6 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -30,6 +30,7 @@ use rustc_codegen_ssa::traits::{ OverflowOp, StaticBuilderMethods, }; +use rustc_data_structures::stable_set::FxHashSet; use rustc_middle::ty::{ParamEnv, Ty, TyCtxt}; use rustc_middle::ty::layout::{FnAbiError, FnAbiOfHelpers, FnAbiRequest, HasParamEnv, HasTyCtxt, LayoutError, LayoutOfHelpers, TyAndLayout}; use rustc_span::Span; @@ -207,6 +208,11 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { param_types.push(param); } + let mut on_stack_param_indices = FxHashSet::default(); + if let Some(indices) = self.on_stack_params.borrow().get(&gcc_func) { + on_stack_param_indices = indices.clone(); + } + if all_args_match { return Cow::Borrowed(args); } @@ -215,10 +221,15 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { .into_iter() .zip(args.iter()) .enumerate() - .map(|(_i, (expected_ty, &actual_val))| { + .map(|(index, (expected_ty, &actual_val))| { let actual_ty = actual_val.get_type(); if expected_ty != actual_ty { - self.bitcast(actual_val, expected_ty) + if on_stack_param_indices.contains(&index) { + actual_val.dereference(None).to_rvalue() + } + else { + self.bitcast(actual_val, expected_ty) + } } else { actual_val @@ -946,14 +957,8 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } /* Miscellaneous instructions */ - fn memcpy(&mut self, dst: RValue<'gcc>, dst_align: Align, src: RValue<'gcc>, src_align: Align, size: RValue<'gcc>, flags: MemFlags) { - if flags.contains(MemFlags::NONTEMPORAL) { - // HACK(nox): This is inefficient but there is no nontemporal memcpy. - let val = self.load(src.get_type(), src, src_align); - let ptr = self.pointercast(dst, self.type_ptr_to(self.val_ty(val))); - self.store_with_flags(val, ptr, dst_align, flags); - return; - } + fn memcpy(&mut self, dst: RValue<'gcc>, _dst_align: Align, src: RValue<'gcc>, _src_align: Align, size: RValue<'gcc>, flags: MemFlags) { + assert!(!flags.contains(MemFlags::NONTEMPORAL), "non-temporal memcpy not supported"); let size = self.intcast(size, self.type_size_t(), false); let _is_volatile = flags.contains(MemFlags::VOLATILE); let dst = self.pointercast(dst, self.type_i8p()); diff --git a/src/context.rs b/src/context.rs index fa556b0b7f2f..d411ccdb8212 100644 --- a/src/context.rs +++ b/src/context.rs @@ -1,6 +1,6 @@ use std::cell::{Cell, RefCell}; -use gccjit::{Block, CType, Context, Function, FunctionType, LValue, RValue, Struct, Type}; +use gccjit::{Block, CType, Context, Function, FunctionPtrType, FunctionType, LValue, RValue, Struct, Type}; use rustc_codegen_ssa::base::wants_msvc_seh; use rustc_codegen_ssa::traits::{ BackendTypes, @@ -81,6 +81,12 @@ pub struct CodegenCx<'gcc, 'tcx> { /// Cache generated vtables pub vtables: RefCell, Option>), RValue<'gcc>>>, + // TODO(antoyo): improve the SSA API to not require those. + // Mapping from function pointer type to indexes of on stack parameters. + pub on_stack_params: RefCell, FxHashSet>>, + // Mapping from function to indexes of on stack parameters. + pub on_stack_function_params: RefCell, FxHashSet>>, + /// Cache of emitted const globals (value -> global) pub const_globals: RefCell, RValue<'gcc>>>, /// Map from the address of a global variable (rvalue) to the global variable itself (lvalue). @@ -208,6 +214,8 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { linkage: Cell::new(FunctionType::Internal), instances: Default::default(), function_instances: Default::default(), + on_stack_params: Default::default(), + on_stack_function_params: Default::default(), vtables: Default::default(), const_globals: Default::default(), global_lvalues: Default::default(), diff --git a/src/declare.rs b/src/declare.rs index 4bd7a17381d0..43017376916d 100644 --- a/src/declare.rs +++ b/src/declare.rs @@ -80,8 +80,9 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { } pub fn declare_fn(&self, name: &str, fn_abi: &FnAbi<'tcx, Ty<'tcx>>) -> RValue<'gcc> { - let (return_type, params, variadic) = fn_abi.gcc_type(self); + let (return_type, params, variadic, on_stack_param_indices) = fn_abi.gcc_type(self); let func = declare_raw_fn(self, name, () /*fn_abi.llvm_cconv()*/, return_type, ¶ms, variadic); + self.on_stack_function_params.borrow_mut().insert(func, on_stack_param_indices); // FIXME(antoyo): this is a wrong cast. That requires changing the compiler API. unsafe { std::mem::transmute(func) } } diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index 5e3eef67df5a..d4b1dd5ca16f 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -464,17 +464,17 @@ impl<'gcc, 'tcx> ArgAbiExt<'gcc, 'tcx> for ArgAbi<'tcx, Ty<'tcx>> { val.to_rvalue() }; match self.mode { - PassMode::Ignore => {} + PassMode::Ignore => {}, PassMode::Pair(..) => { OperandValue::Pair(next(), next()).store(bx, dst); - } + }, PassMode::Indirect { extra_attrs: Some(_), .. } => { OperandValue::Ref(next(), Some(next()), self.layout.align.abi).store(bx, dst); - } + }, PassMode::Direct(_) | PassMode::Indirect { extra_attrs: None, .. } | PassMode::Cast(_) => { let next_arg = next(); - self.store(bx, next_arg.to_rvalue(), dst); - } + self.store(bx, next_arg, dst); + }, } } } From 7c1f863d74cf8e2c1eb039a38e1d6e9d62b9f390 Mon Sep 17 00:00:00 2001 From: lightning1141 Date: Tue, 8 Mar 2022 11:40:28 +0800 Subject: [PATCH 040/356] Stop removing the llvm-asm tests in test.sh since they don't exist anymore --- test.sh | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/test.sh b/test.sh index ebe663a0b742..1a5b89d3704e 100755 --- a/test.sh +++ b/test.sh @@ -187,13 +187,12 @@ EOF git checkout -- src/test/ui/issues/auxiliary/issue-3136-a.rs # contains //~ERROR, but shouldn't be removed - rm -r src/test/ui/{abi*,extern/,llvm-asm/,panic-runtime/,panics/,unsized-locals/,proc-macro/,threads-sendsync/,thinlto/,simd*,borrowck/,test*,*lto*.rs} || true + rm -r src/test/ui/{abi*,extern/,panic-runtime/,panics/,unsized-locals/,proc-macro/,threads-sendsync/,thinlto/,simd*,borrowck/,test*,*lto*.rs} || true for test in $(rg --files-with-matches "catch_unwind|should_panic|thread|lto" src/test/ui); do rm $test done git checkout src/test/ui/type-alias-impl-trait/auxiliary/cross_crate_ice.rs git checkout src/test/ui/type-alias-impl-trait/auxiliary/cross_crate_ice2.rs - rm src/test/ui/llvm-asm/llvm-asm-in-out-operand.rs || true # TODO(antoyo): Enable back this test if I ever implement the llvm_asm! macro. RUSTC_ARGS="-Zpanic-abort-tests -Csymbol-mangling-version=v0 -Zcodegen-backend="$(pwd)"/../target/"$CHANNEL"/librustc_codegen_gcc."$dylib_ext" --sysroot "$(pwd)"/../build_sysroot/sysroot -Cpanic=abort" From 12f782edfaccc3914aef3c92c1302161015356aa Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Fri, 18 Mar 2022 23:31:02 -0400 Subject: [PATCH 041/356] Fix version of compiler_builtins to fix compilation failure --- build_sysroot/Cargo.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/build_sysroot/Cargo.toml b/build_sysroot/Cargo.toml index cfadf47cc3f8..05863471cb1e 100644 --- a/build_sysroot/Cargo.toml +++ b/build_sysroot/Cargo.toml @@ -5,7 +5,7 @@ version = "0.0.0" [dependencies] core = { path = "./sysroot_src/library/core" } -compiler_builtins = "0.1" +compiler_builtins = "=0.1.70" # TODO: update back to "0.1" when updating to latest nightly. alloc = { path = "./sysroot_src/library/alloc" } std = { path = "./sysroot_src/library/std", features = ["panic_unwind", "backtrace"] } test = { path = "./sysroot_src/library/test" } From be9789bf01b2f6b9a83a0b0b5817347426a69439 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Tue, 8 Mar 2022 17:05:32 -0500 Subject: [PATCH 042/356] Fix ice in box alloc --- example/mini_core.rs | 16 +++++++++++++--- src/type_of.rs | 4 +++- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/example/mini_core.rs b/example/mini_core.rs index 1067cee88148..d70df9051609 100644 --- a/example/mini_core.rs +++ b/example/mini_core.rs @@ -443,12 +443,22 @@ pub trait Deref { fn deref(&self) -> &Self::Target; } +pub trait Allocator { +} + +pub struct Global; + +impl Allocator for Global {} + #[lang = "owned_box"] -pub struct Box(*mut T); +pub struct Box< + T: ?Sized, + A: Allocator = Global, +>(*mut T, A); impl, U: ?Sized> CoerceUnsized> for Box {} -impl Drop for Box { +impl Drop for Box { fn drop(&mut self) { // drop is currently performed by compiler. } @@ -468,7 +478,7 @@ unsafe fn allocate(size: usize, _align: usize) -> *mut u8 { } #[lang = "box_free"] -unsafe fn box_free(ptr: *mut T) { +unsafe fn box_free(ptr: *mut T, alloc: A) { libc::free(ptr as *mut u8); } diff --git a/src/type_of.rs b/src/type_of.rs index 0ada20cad2c3..76a98adbf3c2 100644 --- a/src/type_of.rs +++ b/src/type_of.rs @@ -251,7 +251,9 @@ impl<'tcx> LayoutGccExt<'tcx> for TyAndLayout<'tcx> { ty::Ref(..) | ty::RawPtr(_) => { return self.field(cx, index).gcc_type(cx, true); } - ty::Adt(def, _) if def.is_box() => { + // only wide pointer boxes are handled as pointers + // thin pointer boxes with scalar allocators are handled by the general logic below + ty::Adt(def, substs) if def.is_box() && cx.layout_of(substs.type_at(1)).is_zst() => { let ptr_ty = cx.tcx.mk_mut_ptr(self.ty.boxed_ty()); return cx.layout_of(ptr_ty).scalar_pair_element_gcc_type(cx, index, immediate); } From 0fb350f37c71fc0fb9537dd0736449d0fffb8653 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 19 Mar 2022 12:15:26 -0400 Subject: [PATCH 043/356] Fix shift of unsigned integer by signed integer --- src/int.rs | 9 ++------- tests/run/int.rs | 2 ++ 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/src/int.rs b/src/int.rs index d2df9d2dcb62..c3ed71ff7303 100644 --- a/src/int.rs +++ b/src/int.rs @@ -68,14 +68,9 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let a_native = self.is_native_int_type(a_type); let b_native = self.is_native_int_type(b_type); if a_native && b_native { - // FIXME(antoyo): remove the casts when libgccjit can shift an unsigned number by an unsigned number. + // FIXME(antoyo): remove the casts when libgccjit can shift an unsigned number by a signed number. // TODO(antoyo): cast to unsigned to do a logical shift if that does not work. - if a_type.is_unsigned(self) && b_type.is_signed(self) { - let a = self.context.new_cast(None, a, b_type); - let result = a >> b; - self.context.new_cast(None, result, a_type) - } - else if a_type.is_signed(self) && b_type.is_unsigned(self) { + if a_type.is_signed(self) != b_type.is_signed(self) { let b = self.context.new_cast(None, b, a_type); a >> b } diff --git a/tests/run/int.rs b/tests/run/int.rs index 7a62fc7d1f78..49376012c40e 100644 --- a/tests/run/int.rs +++ b/tests/run/int.rs @@ -71,6 +71,8 @@ fn main(argc: isize, _argv: *const *const u8) -> isize { assert_eq!(var3 << (argc + 62) as u128, 96618259944854013731572476686437974016); assert_eq!(var3 << (argc + 63) as u128, 193236519889708027463144953372875948032); + assert_eq!((2220326408_u32 + argc as u32) >> (32 - 6), 33); + assert_eq!(var >> (argc as u128 - 1), var); assert_eq!(var >> argc as u128, 67108928); assert_eq!(var >> (argc + 32) as u128, 0); From 72306608e0995f01e069f230ec55486c816e2600 Mon Sep 17 00:00:00 2001 From: yvt Date: Wed, 23 Mar 2022 23:16:45 +0900 Subject: [PATCH 044/356] Add a simple argument parser to `build.sh` --- build.sh | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/build.sh b/build.sh index 8a621e12b04e..7e8a5ecd88ee 100755 --- a/build.sh +++ b/build.sh @@ -3,6 +3,21 @@ #set -x set -e +codegen_channel=debug + +while [[ $# -gt 0 ]]; do + case $1 in + --release) + codegen_channel=release + shift + ;; + *) + echo "Unknown option $1" + exit 1 + ;; + esac +done + if [ -f ./gcc_path ]; then export GCC_PATH=$(cat gcc_path) else @@ -21,7 +36,7 @@ if [[ "$1" == "--features" ]]; then shift fi -if [[ "$1" == "--release" ]]; then +if [[ "$codegen_channel" == "release" ]]; then export CHANNEL='release' CARGO_INCREMENTAL=1 cargo rustc --release $features else @@ -37,3 +52,4 @@ mkdir -p target/out/gccjit echo "[BUILD] sysroot" time ./build_sysroot/build_sysroot.sh $CHANNEL + From 842a5fba1ce9c82389f529ca88bb586749308f5c Mon Sep 17 00:00:00 2001 From: yvt Date: Wed, 23 Mar 2022 23:18:33 +0900 Subject: [PATCH 045/356] Add `--release-sysroot` flag to `build.sh` When this flag is present, `build.sh` will pass `--release` to `build_sysroot.sh`. --- build.sh | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/build.sh b/build.sh index 7e8a5ecd88ee..230ab7b6d42b 100755 --- a/build.sh +++ b/build.sh @@ -4,6 +4,7 @@ set -e codegen_channel=debug +sysroot_channel=debug while [[ $# -gt 0 ]]; do case $1 in @@ -11,6 +12,10 @@ while [[ $# -gt 0 ]]; do codegen_channel=release shift ;; + --release-sysroot) + sysroot_channel=release + shift + ;; *) echo "Unknown option $1" exit 1 @@ -51,5 +56,9 @@ rm -r target/out || true mkdir -p target/out/gccjit echo "[BUILD] sysroot" -time ./build_sysroot/build_sysroot.sh $CHANNEL +if [[ "$sysroot_channel" == "release" ]]; then + time ./build_sysroot/build_sysroot.sh --release +else + time ./build_sysroot/build_sysroot.sh +fi From 6faa6a28ba165ff225a4865604189f0b681cbd47 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Sat, 26 Mar 2022 14:12:44 +0100 Subject: [PATCH 046/356] Rustup to rustc 1.61.0-nightly (d53246fed 2022-03-25) --- example/mini_core.rs | 4 +++ ...0024-core-Disable-portable-simd-test.patch | 20 +++++--------- ...0028-core-Disable-long-running-tests.patch | 26 ++++++++++--------- rust-toolchain | 2 +- src/builder.rs | 2 +- src/lib.rs | 6 +++++ 6 files changed, 32 insertions(+), 28 deletions(-) diff --git a/example/mini_core.rs b/example/mini_core.rs index d70df9051609..a8435287d9fd 100644 --- a/example/mini_core.rs +++ b/example/mini_core.rs @@ -14,6 +14,9 @@ unsafe extern "C" fn _Unwind_Resume() { #[lang = "sized"] pub trait Sized {} +#[lang = "destruct"] +pub trait Destruct {} + #[lang = "unsize"] pub trait Unsize {} @@ -59,6 +62,7 @@ unsafe impl Copy for i16 {} unsafe impl Copy for i32 {} unsafe impl Copy for isize {} unsafe impl Copy for f32 {} +unsafe impl Copy for f64 {} unsafe impl Copy for char {} unsafe impl<'a, T: ?Sized> Copy for &'a T {} unsafe impl Copy for *const T {} diff --git a/patches/0024-core-Disable-portable-simd-test.patch b/patches/0024-core-Disable-portable-simd-test.patch index 4ffb24cd9a7a..03900ba101a9 100644 --- a/patches/0024-core-Disable-portable-simd-test.patch +++ b/patches/0024-core-Disable-portable-simd-test.patch @@ -11,7 +11,7 @@ diff --git a/library/core/src/lib.rs b/library/core/src/lib.rs index aa1ad93..95fbf55 100644 --- a/library/core/src/lib.rs +++ b/library/core/src/lib.rs -@@ -398,25 +398,4 @@ pub mod arch { +@@ -398,23 +398,4 @@ pub mod arch { } } @@ -25,12 +25,10 @@ index aa1ad93..95fbf55 100644 -#[allow(missing_debug_implementations, dead_code, unsafe_op_in_unsafe_fn, unused_unsafe)] -#[allow(rustdoc::bare_urls)] -#[unstable(feature = "portable_simd", issue = "86656")] --#[cfg(not(all(miri, doctest)))] // Miri does not support all SIMD intrinsics -mod core_simd; - -#[doc = include_str!("../../portable-simd/crates/core_simd/src/core_simd_docs.md")] -#[unstable(feature = "portable_simd", issue = "86656")] --#[cfg(not(all(miri, doctest)))] // Miri does not support all SIMD intrinsics -pub mod simd { - #[unstable(feature = "portable_simd", issue = "86656")] - pub use crate::core_simd::simd::*; @@ -41,15 +39,14 @@ diff --git a/library/core/src/slice/mod.rs b/library/core/src/slice/mod.rs index cd38c3a..ad632dc 100644 --- a/library/core/src/slice/mod.rs +++ b/library/core/src/slice/mod.rs -@@ -17,7 +17,6 @@ use crate::ptr; +@@ -17,6 +17,5 @@ use crate::ptr; use crate::result::Result; use crate::result::Result::{Err, Ok}; - #[cfg(not(miri))] // Miri does not support all SIMD intrinsics -use crate::simd::{self, Simd}; use crate::slice; #[unstable( -@@ -3475,123 +3474,6 @@ impl [T] { +@@ -3475,121 +3474,6 @@ impl [T] { } } @@ -102,14 +99,13 @@ index cd38c3a..ad632dc 100644 - /// suffix.iter().copied().sum(), - /// ]); - /// let sums = middle.iter().copied().fold(sums, f32x4::add); -- /// sums.horizontal_sum() +- /// sums.reduce_sum() - /// } - /// - /// let numbers: Vec = (1..101).map(|x| x as _).collect(); - /// assert_eq!(basic_simd_sum(&numbers[1..99]), 4949.0); - /// ``` - #[unstable(feature = "portable_simd", issue = "86656")] -- #[cfg(not(miri))] // Miri does not support all SIMD intrinsics - pub fn as_simd(&self) -> (&[T], &[Simd], &[T]) - where - Simd: AsRef<[T; LANES]>, @@ -153,7 +149,6 @@ index cd38c3a..ad632dc 100644 - /// be lifted in a way that would make it possible to see panics from this - /// method for something like `LANES == 3`. - #[unstable(feature = "portable_simd", issue = "86656")] -- #[cfg(not(miri))] // Miri does not support all SIMD intrinsics - pub fn as_simd_mut(&mut self) -> (&mut [T], &mut [Simd], &mut [T]) - where - Simd: AsMut<[T; LANES]>, @@ -197,15 +192,14 @@ diff --git a/library/std/src/lib.rs b/library/std/src/lib.rs index 5dc586d..b6fc48f 100644 --- a/library/std/src/lib.rs +++ b/library/std/src/lib.rs -@@ -312,7 +312,6 @@ +@@ -312,6 +312,5 @@ #![feature(panic_can_unwind)] #![feature(panic_unwind)] #![feature(platform_intrinsics)] -#![feature(portable_simd)] #![feature(prelude_import)] #![feature(ptr_as_uninit)] - #![feature(ptr_internals)] -@@ -508,25 +508,6 @@ pub mod time; +@@ -508,23 +508,6 @@ pub mod time; #[unstable(feature = "once_cell", issue = "74465")] pub mod lazy; @@ -215,10 +209,8 @@ index 5dc586d..b6fc48f 100644 -#[allow(missing_debug_implementations, dead_code, unsafe_op_in_unsafe_fn, unused_unsafe)] -#[allow(rustdoc::bare_urls)] -#[unstable(feature = "portable_simd", issue = "86656")] --#[cfg(not(all(miri, doctest)))] // Miri does not support all SIMD intrinsics -mod std_float; - --#[cfg(not(all(miri, doctest)))] // Miri does not support all SIMD intrinsics -#[doc = include_str!("../../portable-simd/crates/core_simd/src/core_simd_docs.md")] -#[unstable(feature = "portable_simd", issue = "86656")] -pub mod simd { diff --git a/patches/0028-core-Disable-long-running-tests.patch b/patches/0028-core-Disable-long-running-tests.patch index bf74a74c7c4b..dc1beae6d2e7 100644 --- a/patches/0028-core-Disable-long-running-tests.patch +++ b/patches/0028-core-Disable-long-running-tests.patch @@ -1,30 +1,32 @@ -From 0ffdd8eda8df364391c8ac6e1ce92c73ba9254d4 Mon Sep 17 00:00:00 2001 +From eb703e627e7a84f1cd8d0d87f0f69da1f0acf765 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Fri, 3 Dec 2021 12:16:30 +0100 Subject: [PATCH] Disable long running tests --- - library/core/tests/slice.rs | 3 +++ - 1 file changed, 3 insertions(+) + library/core/tests/slice.rs | 2 ++ + 1 file changed, 2 insertions(+) diff --git a/library/core/tests/slice.rs b/library/core/tests/slice.rs -index 2c8f00a..44847ee 100644 +index 8402833..84592e0 100644 --- a/library/core/tests/slice.rs +++ b/library/core/tests/slice.rs -@@ -2332,7 +2332,8 @@ macro_rules! empty_max_mut { - }; - } +@@ -2462,6 +2462,7 @@ take_tests! { + #[cfg(not(miri))] // unused in Miri + const EMPTY_MAX: &'static [()] = &[(); usize::MAX]; +/* - #[cfg(not(miri))] // Comparing usize::MAX many elements takes forever in Miri (and in rustc without optimizations) - take_tests! { - slice: &[(); usize::MAX], method: take, - (take_in_bounds_max_range_to, (..usize::MAX), Some(EMPTY_MAX), &[(); 0]), -@@ -2345,3 +2347,4 @@ take_tests! { + // can't be a constant due to const mutability rules + #[cfg(not(miri))] // unused in Miri + macro_rules! empty_max_mut { +@@ -2485,6 +2486,7 @@ take_tests! { (take_mut_oob_max_range_to_inclusive, (..=usize::MAX), None, empty_max_mut!()), (take_mut_in_bounds_max_range_from, (usize::MAX..), Some(&mut [] as _), empty_max_mut!()), } +*/ + + #[test] + fn test_slice_from_ptr_range() { -- 2.26.2.7.g19db9cfb68 diff --git a/rust-toolchain b/rust-toolchain index f2d80b78313d..db14ea2bebca 100644 --- a/rust-toolchain +++ b/rust-toolchain @@ -1,3 +1,3 @@ [toolchain] -channel = "nightly-2022-02-25" +channel = "nightly-2022-03-26" components = ["rust-src", "rustc-dev", "llvm-tools-preview"] diff --git a/src/builder.rs b/src/builder.rs index 94b1e2ce13a8..b2f46e92eccb 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1252,7 +1252,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn do_not_inline(&mut self, _llret: RValue<'gcc>) { - unimplemented!(); + // FIMXE(bjorn3): implement } fn set_span(&mut self, _span: Span) {} diff --git a/src/lib.rs b/src/lib.rs index 8e197ea31a8e..0647d8c28eea 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -64,6 +64,7 @@ use rustc_errors::{ErrorGuaranteed, Handler}; use rustc_metadata::EncodedMetadata; use rustc_middle::dep_graph::{WorkProduct, WorkProductId}; use rustc_middle::ty::TyCtxt; +use rustc_middle::ty::query::Providers; use rustc_session::config::{Lto, OptLevel, OutputFilenames}; use rustc_session::Session; use rustc_span::Symbol; @@ -101,6 +102,11 @@ impl CodegenBackend for GccCodegenBackend { *self.supports_128bit_integers.lock().expect("lock") = check_context.get_last_error() == Ok(None); } + fn provide(&self, providers: &mut Providers) { + // FIXME compute list of enabled features from cli flags + providers.global_backend_features = |_tcx, ()| vec![]; + } + fn codegen_crate<'tcx>(&self, tcx: TyCtxt<'tcx>, metadata: EncodedMetadata, need_metadata_module: bool) -> Box { let target_cpu = target_cpu(tcx.sess); let res = codegen_crate(self.clone(), tcx, target_cpu.to_string(), metadata, need_metadata_module); From edf33fe0a2fa322d1d372c22da75fc819f9049eb Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Sat, 26 Mar 2022 14:25:37 +0100 Subject: [PATCH 047/356] Add Destruct and Drop traits to static.rs --- tests/run/static.rs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tests/run/static.rs b/tests/run/static.rs index ab89f6aff4b5..294add968449 100644 --- a/tests/run/static.rs +++ b/tests/run/static.rs @@ -22,6 +22,12 @@ #[lang = "sized"] pub trait Sized {} +#[lang = "destruct"] +pub trait Destruct {} + +#[lang = "drop"] +pub trait Drop {} + #[lang = "copy"] trait Copy { } From 724473b330905771fb5950d3bd878e10d5a4fb63 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Sat, 26 Mar 2022 16:14:39 +0100 Subject: [PATCH 048/356] Fix compiletest compilation --- test.sh | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/test.sh b/test.sh index 1a5b89d3704e..1beeee136df3 100755 --- a/test.sh +++ b/test.sh @@ -165,6 +165,24 @@ function test_rustc() { git checkout $(rustc -V | cut -d' ' -f3 | tr -d '(') export RUSTFLAGS= + git apply - <( + cfg: Option<&str>, + ) -> test::TestDesc { + let mut ignore = false; + #[cfg(not(bootstrap))] +- let ignore_message: Option = None; ++ let ignore_message: Option<&str> = None; + let mut should_fail = false; + + let rustc_has_profiler_support = env::var_os("RUSTC_PROFILER_SUPPORT").is_some(); + +EOF + rm config.toml || true cat > config.toml < Date: Sat, 26 Mar 2022 17:27:06 +0100 Subject: [PATCH 049/356] Review comments --- build_sysroot/Cargo.toml | 2 +- src/lib.rs | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/build_sysroot/Cargo.toml b/build_sysroot/Cargo.toml index 05863471cb1e..cfadf47cc3f8 100644 --- a/build_sysroot/Cargo.toml +++ b/build_sysroot/Cargo.toml @@ -5,7 +5,7 @@ version = "0.0.0" [dependencies] core = { path = "./sysroot_src/library/core" } -compiler_builtins = "=0.1.70" # TODO: update back to "0.1" when updating to latest nightly. +compiler_builtins = "0.1" alloc = { path = "./sysroot_src/library/alloc" } std = { path = "./sysroot_src/library/std", features = ["panic_unwind", "backtrace"] } test = { path = "./sysroot_src/library/test" } diff --git a/src/lib.rs b/src/lib.rs index 0647d8c28eea..eac4a06226cf 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -103,7 +103,7 @@ impl CodegenBackend for GccCodegenBackend { } fn provide(&self, providers: &mut Providers) { - // FIXME compute list of enabled features from cli flags + // FIXME(antoyo) compute list of enabled features from cli flags providers.global_backend_features = |_tcx, ()| vec![]; } From 590bfc670a57973683d97eec104265a87363f418 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Sat, 26 Mar 2022 14:21:03 +0100 Subject: [PATCH 050/356] Don't pass --target in cargo.sh This was a workaround for compiling proc macros resulting in an abi incompatibility. By passing --target proc macros will be built by the llvm backend. This is no longer necessary as the abi incompatibility has since been fixed. --- cargo.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cargo.sh b/cargo.sh index 332f365ce0ce..e95564dccda0 100755 --- a/cargo.sh +++ b/cargo.sh @@ -20,4 +20,4 @@ fi cmd=$1 shift -RUSTDOCFLAGS="$RUSTFLAGS" cargo +${TOOLCHAIN} $cmd --target $TARGET_TRIPLE $@ +RUSTDOCFLAGS="$RUSTFLAGS" cargo +${TOOLCHAIN} $cmd $@ From 02970a6ca89e1288e823756ec992c9070b06baee Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 6 Feb 2022 17:04:24 -0500 Subject: [PATCH 051/356] Add support for target builtins --- .gitignore | 1 + Cargo.lock | 4 +- config.sh | 4 +- .../0002-rand-Disable-failing-test.patch | 32 ++ example/std_example.rs | 46 +-- ...0024-core-Disable-portable-simd-test.patch | 199 ---------- prepare.sh | 7 + rustc_patches/compile_test.patch | 14 + src/base.rs | 5 + src/builder.rs | 116 ++++-- src/common.rs | 19 + src/consts.rs | 14 +- src/context.rs | 4 +- src/int.rs | 18 +- src/intrinsic/llvm.rs | 122 +++++- src/intrinsic/simd.rs | 360 +++++++++++++++++- src/lib.rs | 14 +- src/type_.rs | 22 +- src/type_of.rs | 22 ++ test.sh | 91 ++--- 20 files changed, 778 insertions(+), 336 deletions(-) create mode 100644 crate_patches/0002-rand-Disable-failing-test.patch create mode 100644 rustc_patches/compile_test.patch diff --git a/.gitignore b/.gitignore index efda74b2633a..0b611d05b5c9 100644 --- a/.gitignore +++ b/.gitignore @@ -13,6 +13,7 @@ perf.data.old /rust /simple-raytracer /regex +/rand gimple* *asm res diff --git a/Cargo.lock b/Cargo.lock index a1d9f2f5e382..f66c98742695 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -41,7 +41,7 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" -source = "git+https://github.com/antoyo/gccjit.rs#bdecdecfb8a02ec861a39a350f990faa33bd31c3" +source = "git+https://github.com/antoyo/gccjit.rs#f24e1f49d99430941d8a747275b41c9a7930e049" dependencies = [ "gccjit_sys", ] @@ -49,7 +49,7 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" -source = "git+https://github.com/antoyo/gccjit.rs#bdecdecfb8a02ec861a39a350f990faa33bd31c3" +source = "git+https://github.com/antoyo/gccjit.rs#f24e1f49d99430941d8a747275b41c9a7930e049" dependencies = [ "libc 0.1.12", ] diff --git a/config.sh b/config.sh index a932c1c8372b..b25e215fb9ee 100644 --- a/config.sh +++ b/config.sh @@ -2,7 +2,7 @@ set -e export CARGO_INCREMENTAL=0 -if [ -f ./gcc_path ]; then +if [ -f ./gcc_path ]; then export GCC_PATH=$(cat gcc_path) else echo 'Please put the path to your custom build of libgccjit in the file `gcc_path`, see Readme.md for details' @@ -38,7 +38,7 @@ if [[ "$HOST_TRIPLE" != "$TARGET_TRIPLE" ]]; then fi fi -export RUSTFLAGS="$linker -Cpanic=abort -Csymbol-mangling-version=v0 -Cdebuginfo=2 -Clto=off -Zpanic-abort-tests -Zcodegen-backend=$(pwd)/target/${CHANNEL:-debug}/librustc_codegen_gcc.$dylib_ext --sysroot $(pwd)/build_sysroot/sysroot" +export RUSTFLAGS="$CG_RUSTFLAGS $linker -Cpanic=abort -Csymbol-mangling-version=v0 -Cdebuginfo=2 -Clto=off -Zpanic-abort-tests -Zcodegen-backend=$(pwd)/target/${CHANNEL:-debug}/librustc_codegen_gcc.$dylib_ext --sysroot $(pwd)/build_sysroot/sysroot" # FIXME(antoyo): remove once the atomic shim is gone if [[ `uname` == 'Darwin' ]]; then diff --git a/crate_patches/0002-rand-Disable-failing-test.patch b/crate_patches/0002-rand-Disable-failing-test.patch new file mode 100644 index 000000000000..449ca5f6e29c --- /dev/null +++ b/crate_patches/0002-rand-Disable-failing-test.patch @@ -0,0 +1,32 @@ +From a8fb97120d71252538b6b026695df40d02696bdb Mon Sep 17 00:00:00 2001 +From: bjorn3 +Date: Sat, 15 Aug 2020 20:04:38 +0200 +Subject: [PATCH] [rand] Disable failing test + +--- + src/distributions/uniform.rs | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/src/distributions/uniform.rs b/src/distributions/uniform.rs +index 480b859..c80bb6f 100644 +--- a/src/distributions/uniform.rs ++++ b/src/distributions/uniform.rs +@@ -1085,7 +1085,7 @@ mod tests { + _ => panic!("`UniformDurationMode` was not serialized/deserialized correctly") + } + } +- ++ + #[test] + #[cfg(feature = "serde1")] + fn test_uniform_serialization() { +@@ -1314,6 +1314,7 @@ mod tests { + not(target_arch = "wasm32"), + not(target_arch = "asmjs") + ))] ++ #[ignore] // FIXME + fn test_float_assertions() { + use super::SampleUniform; + use std::panic::catch_unwind; +-- +2.20.1 diff --git a/example/std_example.rs b/example/std_example.rs index eba0eb828960..722666f7e166 100644 --- a/example/std_example.rs +++ b/example/std_example.rs @@ -93,9 +93,9 @@ fn main() { println!("{:?}", std::intrinsics::caller_location()); - /*unsafe { + unsafe { test_simd(); - }*/ + } Box::pin(move |mut _task_context| { yield (); @@ -104,7 +104,7 @@ fn main() { println!("End"); } -/*#[target_feature(enable = "sse2")] +#[target_feature(enable = "sse2")] unsafe fn test_simd() { let x = _mm_setzero_si128(); let y = _mm_set1_epi16(7); @@ -112,7 +112,7 @@ unsafe fn test_simd() { let cmp_eq = _mm_cmpeq_epi8(y, y); let cmp_lt = _mm_cmplt_epi8(y, y); - /*assert_eq!(std::mem::transmute::<_, [u16; 8]>(or), [7, 7, 7, 7, 7, 7, 7, 7]); + assert_eq!(std::mem::transmute::<_, [u16; 8]>(or), [7, 7, 7, 7, 7, 7, 7, 7]); assert_eq!(std::mem::transmute::<_, [u16; 8]>(cmp_eq), [0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff]); assert_eq!(std::mem::transmute::<_, [u16; 8]>(cmp_lt), [0, 0, 0, 0, 0, 0, 0, 0]); @@ -124,14 +124,14 @@ unsafe fn test_simd() { test_mm_cvtepi8_epi16(); test_mm_cvtsi128_si64(); - // FIXME(#666) implement `#[rustc_arg_required_const(..)]` support - //test_mm_extract_epi8(); + test_mm_extract_epi8(); + test_mm_insert_epi16(); let mask1 = _mm_movemask_epi8(dbg!(_mm_setr_epi8(255u8 as i8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0))); - assert_eq!(mask1, 1);*/ -}*/ + assert_eq!(mask1, 1); +} -/*#[target_feature(enable = "sse2")] +#[target_feature(enable = "sse2")] unsafe fn test_mm_slli_si128() { #[rustfmt::skip] let a = _mm_setr_epi8( @@ -155,22 +155,9 @@ unsafe fn test_mm_slli_si128() { ); let r = _mm_slli_si128(a, 16); assert_eq_m128i(r, _mm_set1_epi8(0)); - - #[rustfmt::skip] - let a = _mm_setr_epi8( - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, - ); - let r = _mm_slli_si128(a, -1); - assert_eq_m128i(_mm_set1_epi8(0), r); - - #[rustfmt::skip] - let a = _mm_setr_epi8( - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, - ); - let r = _mm_slli_si128(a, -0x80000000); - assert_eq_m128i(r, _mm_set1_epi8(0)); } + #[target_feature(enable = "sse2")] unsafe fn test_mm_movemask_epi8() { #[rustfmt::skip] @@ -254,10 +241,19 @@ unsafe fn test_mm_extract_epi8() { 8, 9, 10, 11, 12, 13, 14, 15 ); let r1 = _mm_extract_epi8(a, 0); - let r2 = _mm_extract_epi8(a, 19); + let r2 = _mm_extract_epi8(a, 3); assert_eq!(r1, 0xFF); assert_eq!(r2, 3); -}*/ +} + +#[cfg(target_arch = "x86_64")] +#[target_feature(enable = "sse2")] +unsafe fn test_mm_insert_epi16() { + let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7); + let r = _mm_insert_epi16(a, 9, 0); + let e = _mm_setr_epi16(9, 1, 2, 3, 4, 5, 6, 7); + assert_eq_m128i(r, e); +} #[derive(PartialEq)] enum LoopState { diff --git a/patches/0024-core-Disable-portable-simd-test.patch b/patches/0024-core-Disable-portable-simd-test.patch index 03900ba101a9..d5fa1cec061d 100644 --- a/patches/0024-core-Disable-portable-simd-test.patch +++ b/patches/0024-core-Disable-portable-simd-test.patch @@ -7,167 +7,6 @@ Subject: [PATCH] [core] Disable portable-simd test library/core/tests/lib.rs | 1 - 1 file changed, 1 deletion(-) -diff --git a/library/core/src/lib.rs b/library/core/src/lib.rs -index aa1ad93..95fbf55 100644 ---- a/library/core/src/lib.rs -+++ b/library/core/src/lib.rs -@@ -398,23 +398,4 @@ pub mod arch { - } - } - --// Pull in the `core_simd` crate directly into libcore. The contents of --// `core_simd` are in a different repository: rust-lang/portable-simd. --// --// `core_simd` depends on libcore, but the contents of this module are --// set up in such a way that directly pulling it here works such that the --// crate uses this crate as its libcore. --#[path = "../../portable-simd/crates/core_simd/src/mod.rs"] --#[allow(missing_debug_implementations, dead_code, unsafe_op_in_unsafe_fn, unused_unsafe)] --#[allow(rustdoc::bare_urls)] --#[unstable(feature = "portable_simd", issue = "86656")] --mod core_simd; -- --#[doc = include_str!("../../portable-simd/crates/core_simd/src/core_simd_docs.md")] --#[unstable(feature = "portable_simd", issue = "86656")] --pub mod simd { -- #[unstable(feature = "portable_simd", issue = "86656")] -- pub use crate::core_simd::simd::*; --} -- - include!("primitive_docs.rs"); -diff --git a/library/core/src/slice/mod.rs b/library/core/src/slice/mod.rs -index cd38c3a..ad632dc 100644 ---- a/library/core/src/slice/mod.rs -+++ b/library/core/src/slice/mod.rs -@@ -17,6 +17,5 @@ use crate::ptr; - use crate::result::Result; - use crate::result::Result::{Err, Ok}; --use crate::simd::{self, Simd}; - use crate::slice; - - #[unstable( -@@ -3475,121 +3474,6 @@ impl [T] { - } - } - -- /// Split a slice into a prefix, a middle of aligned SIMD types, and a suffix. -- /// -- /// This is a safe wrapper around [`slice::align_to`], so has the same weak -- /// postconditions as that method. You're only assured that -- /// `self.len() == prefix.len() + middle.len() * LANES + suffix.len()`. -- /// -- /// Notably, all of the following are possible: -- /// - `prefix.len() >= LANES`. -- /// - `middle.is_empty()` despite `self.len() >= 3 * LANES`. -- /// - `suffix.len() >= LANES`. -- /// -- /// That said, this is a safe method, so if you're only writing safe code, -- /// then this can at most cause incorrect logic, not unsoundness. -- /// -- /// # Panics -- /// -- /// This will panic if the size of the SIMD type is different from -- /// `LANES` times that of the scalar. -- /// -- /// At the time of writing, the trait restrictions on `Simd` keeps -- /// that from ever happening, as only power-of-two numbers of lanes are -- /// supported. It's possible that, in the future, those restrictions might -- /// be lifted in a way that would make it possible to see panics from this -- /// method for something like `LANES == 3`. -- /// -- /// # Examples -- /// -- /// ``` -- /// #![feature(portable_simd)] -- /// -- /// let short = &[1, 2, 3]; -- /// let (prefix, middle, suffix) = short.as_simd::<4>(); -- /// assert_eq!(middle, []); // Not enough elements for anything in the middle -- /// -- /// // They might be split in any possible way between prefix and suffix -- /// let it = prefix.iter().chain(suffix).copied(); -- /// assert_eq!(it.collect::>(), vec![1, 2, 3]); -- /// -- /// fn basic_simd_sum(x: &[f32]) -> f32 { -- /// use std::ops::Add; -- /// use std::simd::f32x4; -- /// let (prefix, middle, suffix) = x.as_simd(); -- /// let sums = f32x4::from_array([ -- /// prefix.iter().copied().sum(), -- /// 0.0, -- /// 0.0, -- /// suffix.iter().copied().sum(), -- /// ]); -- /// let sums = middle.iter().copied().fold(sums, f32x4::add); -- /// sums.reduce_sum() -- /// } -- /// -- /// let numbers: Vec = (1..101).map(|x| x as _).collect(); -- /// assert_eq!(basic_simd_sum(&numbers[1..99]), 4949.0); -- /// ``` -- #[unstable(feature = "portable_simd", issue = "86656")] -- pub fn as_simd(&self) -> (&[T], &[Simd], &[T]) -- where -- Simd: AsRef<[T; LANES]>, -- T: simd::SimdElement, -- simd::LaneCount: simd::SupportedLaneCount, -- { -- // These are expected to always match, as vector types are laid out like -- // arrays per , but we -- // might as well double-check since it'll optimize away anyhow. -- assert_eq!(mem::size_of::>(), mem::size_of::<[T; LANES]>()); -- -- // SAFETY: The simd types have the same layout as arrays, just with -- // potentially-higher alignment, so the de-facto transmutes are sound. -- unsafe { self.align_to() } -- } -- -- /// Split a slice into a prefix, a middle of aligned SIMD types, and a suffix. -- /// -- /// This is a safe wrapper around [`slice::align_to_mut`], so has the same weak -- /// postconditions as that method. You're only assured that -- /// `self.len() == prefix.len() + middle.len() * LANES + suffix.len()`. -- /// -- /// Notably, all of the following are possible: -- /// - `prefix.len() >= LANES`. -- /// - `middle.is_empty()` despite `self.len() >= 3 * LANES`. -- /// - `suffix.len() >= LANES`. -- /// -- /// That said, this is a safe method, so if you're only writing safe code, -- /// then this can at most cause incorrect logic, not unsoundness. -- /// -- /// This is the mutable version of [`slice::as_simd`]; see that for examples. -- /// -- /// # Panics -- /// -- /// This will panic if the size of the SIMD type is different from -- /// `LANES` times that of the scalar. -- /// -- /// At the time of writing, the trait restrictions on `Simd` keeps -- /// that from ever happening, as only power-of-two numbers of lanes are -- /// supported. It's possible that, in the future, those restrictions might -- /// be lifted in a way that would make it possible to see panics from this -- /// method for something like `LANES == 3`. -- #[unstable(feature = "portable_simd", issue = "86656")] -- pub fn as_simd_mut(&mut self) -> (&mut [T], &mut [Simd], &mut [T]) -- where -- Simd: AsMut<[T; LANES]>, -- T: simd::SimdElement, -- simd::LaneCount: simd::SupportedLaneCount, -- { -- // These are expected to always match, as vector types are laid out like -- // arrays per , but we -- // might as well double-check since it'll optimize away anyhow. -- assert_eq!(mem::size_of::>(), mem::size_of::<[T; LANES]>()); -- -- // SAFETY: The simd types have the same layout as arrays, just with -- // potentially-higher alignment, so the de-facto transmutes are sound. -- unsafe { self.align_to_mut() } -- } -- - /// Checks if the elements of this slice are sorted. - /// - /// That is, for each element `a` and its following element `b`, `a <= b` must hold. If the diff --git a/library/core/tests/lib.rs b/library/core/tests/lib.rs index 06c7be0..359e2e7 100644 --- a/library/core/tests/lib.rs @@ -188,41 +27,3 @@ index 06c7be0..359e2e7 100644 mod slice; mod str; mod str_lossy; -diff --git a/library/std/src/lib.rs b/library/std/src/lib.rs -index 5dc586d..b6fc48f 100644 ---- a/library/std/src/lib.rs -+++ b/library/std/src/lib.rs -@@ -312,6 +312,5 @@ - #![feature(panic_can_unwind)] - #![feature(panic_unwind)] - #![feature(platform_intrinsics)] --#![feature(portable_simd)] - #![feature(prelude_import)] - #![feature(ptr_as_uninit)] -@@ -508,23 +508,6 @@ pub mod time; - #[unstable(feature = "once_cell", issue = "74465")] - pub mod lazy; - --// Pull in `std_float` crate into libstd. The contents of --// `std_float` are in a different repository: rust-lang/portable-simd. --#[path = "../../portable-simd/crates/std_float/src/lib.rs"] --#[allow(missing_debug_implementations, dead_code, unsafe_op_in_unsafe_fn, unused_unsafe)] --#[allow(rustdoc::bare_urls)] --#[unstable(feature = "portable_simd", issue = "86656")] --mod std_float; -- --#[doc = include_str!("../../portable-simd/crates/core_simd/src/core_simd_docs.md")] --#[unstable(feature = "portable_simd", issue = "86656")] --pub mod simd { -- #[doc(inline)] -- pub use crate::std_float::StdFloat; -- #[doc(inline)] -- pub use core::simd::*; --} -- - #[stable(feature = "futures_api", since = "1.36.0")] - pub mod task { - //! Types and Traits for working with asynchronous tasks. --- -2.26.2.7.g19db9cfb68 - diff --git a/prepare.sh b/prepare.sh index 503fa29b3626..d39f43f5e1b3 100755 --- a/prepare.sh +++ b/prepare.sh @@ -5,6 +5,13 @@ source prepare_build.sh cargo install hyperfine || echo "Skipping hyperfine install" +git clone https://github.com/rust-random/rand.git || echo "rust-random/rand has already been cloned" +pushd rand +git checkout -- . +git checkout 0f933f9c7176e53b2a3c7952ded484e1783f0bf1 +git am ../crate_patches/*-rand-*.patch +popd + git clone https://github.com/rust-lang/regex.git || echo "rust-lang/regex has already been cloned" pushd regex git checkout -- . diff --git a/rustc_patches/compile_test.patch b/rustc_patches/compile_test.patch new file mode 100644 index 000000000000..59143eac37b3 --- /dev/null +++ b/rustc_patches/compile_test.patch @@ -0,0 +1,14 @@ +diff --git a/src/tools/compiletest/src/header.rs b/src/tools/compiletest/src/header.rs +index 887d27fd6dca4..2c2239f2b83d1 100644 +--- a/src/tools/compiletest/src/header.rs ++++ b/src/tools/compiletest/src/header.rs +@@ -806,8 +806,8 @@ pub fn make_test_description( + cfg: Option<&str>, + ) -> test::TestDesc { + let mut ignore = false; + #[cfg(not(bootstrap))] +- let ignore_message: Option = None; ++ let ignore_message: Option<&str> = None; + let mut should_fail = false; + + let rustc_has_profiler_support = env::var_os("RUSTC_PROFILER_SUPPORT").is_some(); diff --git a/src/base.rs b/src/base.rs index f5aca35cdcbc..4ce5cdaccd3a 100644 --- a/src/base.rs +++ b/src/base.rs @@ -78,6 +78,11 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ let context = Context::default(); // TODO(antoyo): only set on x86 platforms. context.add_command_line_option("-masm=intel"); + // TODO(antoyo): only add the following cli argument if the feature is supported. + context.add_command_line_option("-mavx2"); + // FIXME(antoyo): the following causes an illegal instruction on vmovdqu64 in std_example on my CPU. + // Only add if the CPU supports it. + //context.add_command_line_option("-mavx512f"); for arg in &tcx.sess.opts.cg.llvm_args { context.add_command_line_option(arg); } diff --git a/src/builder.rs b/src/builder.rs index b2f46e92eccb..d53e1712dc8f 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -3,7 +3,6 @@ use std::cell::Cell; use std::convert::TryFrom; use std::ops::Deref; -use gccjit::FunctionType; use gccjit::{ BinaryOp, Block, @@ -224,10 +223,14 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { .map(|(index, (expected_ty, &actual_val))| { let actual_ty = actual_val.get_type(); if expected_ty != actual_ty { - if on_stack_param_indices.contains(&index) { + if !actual_ty.is_vector() && !expected_ty.is_vector() && actual_ty.is_integral() && expected_ty.is_integral() && actual_ty.get_size() != expected_ty.get_size() { + self.context.new_cast(None, actual_val, expected_ty) + } + else if on_stack_param_indices.contains(&index) { actual_val.dereference(None).to_rvalue() } else { + assert!(!((actual_ty.is_vector() && !expected_ty.is_vector()) || (!actual_ty.is_vector() && expected_ty.is_vector())), "{:?} ({}) -> {:?} ({}), index: {:?}[{}]", actual_ty, actual_ty.is_vector(), expected_ty, expected_ty.is_vector(), func_ptr, index); self.bitcast(actual_val, expected_ty) } } @@ -286,15 +289,10 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { // gccjit requires to use the result of functions, even when it's not used. // That's why we assign the result to a local or call add_eval(). let gcc_func = func_ptr.get_type().dyncast_function_ptr_type().expect("function ptr"); - let mut return_type = gcc_func.get_return_type(); + let return_type = gcc_func.get_return_type(); let void_type = self.context.new_type::<()>(); let current_func = self.block.get_function(); - // FIXME(antoyo): As a temporary workaround for unsupported LLVM intrinsics. - if gcc_func.get_param_count() == 0 && format!("{:?}", func_ptr) == "__builtin_ia32_pmovmskb128" { - return_type = self.int_type; - } - if return_type != void_type { unsafe { RETURN_VALUE_COUNT += 1 }; let result = current_func.new_local(None, return_type, &format!("ptrReturnValue{}", unsafe { RETURN_VALUE_COUNT })); @@ -302,13 +300,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { result.to_rvalue() } else { - if gcc_func.get_param_count() == 0 { - // FIXME(antoyo): As a temporary workaround for unsupported LLVM intrinsics. - self.block.add_eval(None, self.cx.context.new_call_through_ptr(None, func_ptr, &[])); - } - else { - self.block.add_eval(None, self.cx.context.new_call_through_ptr(None, func_ptr, &args)); - } + self.block.add_eval(None, self.cx.context.new_call_through_ptr(None, func_ptr, &args)); // Return dummy value when not having return value. let result = current_func.new_local(None, self.isize_type, "dummyValueThatShouldNeverBeUsed"); self.block.add_assignment(None, result, self.context.new_rvalue_from_long(self.isize_type, 0)); @@ -529,12 +521,12 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn frem(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { - if a.get_type() == self.cx.float_type { + if a.get_type().is_compatible_with(self.cx.float_type) { let fmodf = self.context.get_builtin_function("fmodf"); // FIXME(antoyo): this seems to produce the wrong result. return self.context.new_call(None, fmodf, &[a, b]); } - assert_eq!(a.get_type(), self.cx.double_type); + assert_eq!(a.get_type().unqualified(), self.cx.double_type); let fmod = self.context.get_builtin_function("fmod"); return self.context.new_call(None, fmod, &[a, b]); @@ -657,7 +649,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { // NOTE: instead of returning the dereference here, we have to assign it to a variable in // the current basic block. Otherwise, it could be used in another basic block, causing a // dereference after a drop, for instance. - // TODO(antoyo): handle align. + // TODO(antoyo): handle align of the load instruction. let deref = ptr.dereference(None).to_rvalue(); let value_type = deref.get_type(); unsafe { RETURN_VALUE_COUNT += 1 }; @@ -797,9 +789,16 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { self.store_with_flags(val, ptr, align, MemFlags::empty()) } - fn store_with_flags(&mut self, val: RValue<'gcc>, ptr: RValue<'gcc>, _align: Align, _flags: MemFlags) -> RValue<'gcc> { + fn store_with_flags(&mut self, val: RValue<'gcc>, ptr: RValue<'gcc>, align: Align, _flags: MemFlags) -> RValue<'gcc> { let ptr = self.check_store(val, ptr); - self.llbb().add_assignment(None, ptr.dereference(None), val); + let destination = ptr.dereference(None); + // NOTE: libgccjit does not support specifying the alignment on the assignment, so we cast + // to type so it gets the proper alignment. + let destination_type = destination.to_rvalue().get_type().unqualified(); + let aligned_type = destination_type.get_aligned(align.bytes()).make_pointer(); + let aligned_destination = self.cx.context.new_bitcast(None, ptr, aligned_type); + let aligned_destination = aligned_destination.dereference(None); + self.llbb().add_assignment(None, aligned_destination, val); // TODO(antoyo): handle align and flags. // NOTE: dummy value here since it's never used. FIXME(antoyo): API should not return a value here? self.cx.context.new_rvalue_zero(self.type_i32()) @@ -1288,14 +1287,75 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { pub fn shuffle_vector(&mut self, v1: RValue<'gcc>, v2: RValue<'gcc>, mask: RValue<'gcc>) -> RValue<'gcc> { - let return_type = v1.get_type(); - let params = [ - self.context.new_parameter(None, return_type, "v1"), - self.context.new_parameter(None, return_type, "v2"), - self.context.new_parameter(None, mask.get_type(), "mask"), - ]; - let shuffle = self.context.new_function(None, FunctionType::Extern, return_type, ¶ms, "_mm_shuffle_epi8", false); - self.context.new_call(None, shuffle, &[v1, v2, mask]) + let struct_type = mask.get_type().is_struct().expect("mask of struct type"); + + // TODO(antoyo): use a recursive unqualified() here. + let vector_type = v1.get_type().unqualified().dyncast_vector().expect("vector type"); + let element_type = vector_type.get_element_type(); + let vec_num_units = vector_type.get_num_units(); + + let mask_num_units = struct_type.get_field_count(); + let mut vector_elements = vec![]; + let mask_element_type = + if element_type.is_integral() { + element_type + } + else { + self.int_type + }; + for i in 0..mask_num_units { + let field = struct_type.get_field(i as i32); + vector_elements.push(self.context.new_cast(None, mask.access_field(None, field).to_rvalue(), mask_element_type)); + } + + // NOTE: the mask needs to be the same length as the input vectors, so add the missing + // elements in the mask if needed. + for _ in mask_num_units..vec_num_units { + vector_elements.push(self.context.new_rvalue_zero(mask_element_type)); + } + + let array_type = self.context.new_array_type(None, element_type, vec_num_units as i32); + let result_type = self.context.new_vector_type(element_type, mask_num_units as u64); + let (v1, v2) = + if vec_num_units < mask_num_units { + // NOTE: the mask needs to be the same length as the input vectors, so join the 2 + // vectors and create a dummy second vector. + let array = self.context.new_bitcast(None, v1, array_type); + let mut elements = vec![]; + for i in 0..vec_num_units { + elements.push(self.context.new_array_access(None, array, self.context.new_rvalue_from_int(self.int_type, i as i32)).to_rvalue()); + } + let array = self.context.new_bitcast(None, v2, array_type); + for i in 0..vec_num_units { + elements.push(self.context.new_array_access(None, array, self.context.new_rvalue_from_int(self.int_type, i as i32)).to_rvalue()); + } + let v1 = self.context.new_rvalue_from_vector(None, result_type, &elements); + let zero = self.context.new_rvalue_zero(element_type); + let v2 = self.context.new_rvalue_from_vector(None, result_type, &vec![zero; mask_num_units]); + (v1, v2) + } + else { + (v1, v2) + }; + + let new_mask_num_units = std::cmp::max(mask_num_units, vec_num_units); + let mask_type = self.context.new_vector_type(mask_element_type, new_mask_num_units as u64); + let mask = self.context.new_rvalue_from_vector(None, mask_type, &vector_elements); + let result = self.context.new_rvalue_vector_perm(None, v1, v2, mask); + + if vec_num_units != mask_num_units { + // NOTE: if padding was added, only select the number of elements of the masks to + // remove that padding in the result. + let mut elements = vec![]; + let array = self.context.new_bitcast(None, result, array_type); + for i in 0..mask_num_units { + elements.push(self.context.new_array_access(None, array, self.context.new_rvalue_from_int(self.int_type, i as i32)).to_rvalue()); + } + self.context.new_rvalue_from_vector(None, result_type, &elements) + } + else { + result + } } } diff --git a/src/common.rs b/src/common.rs index 61709dd92de7..703e20947fe8 100644 --- a/src/common.rs +++ b/src/common.rs @@ -322,6 +322,8 @@ pub trait TypeReflection<'gcc, 'tcx> { fn is_f32(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool; fn is_f64(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool; + + fn is_vector(&self) -> bool; } impl<'gcc, 'tcx> TypeReflection<'gcc, 'tcx> for Type<'gcc> { @@ -392,4 +394,21 @@ impl<'gcc, 'tcx> TypeReflection<'gcc, 'tcx> for Type<'gcc> { fn is_f64(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool { self.unqualified() == cx.context.new_type::() } + + fn is_vector(&self) -> bool { + let mut typ = self.clone(); + loop { + if typ.dyncast_vector().is_some() { + return true; + } + + let old_type = typ; + typ = typ.unqualified(); + if old_type == typ { + break; + } + } + + false + } } diff --git a/src/consts.rs b/src/consts.rs index de52f3ea2255..4350c00e94a7 100644 --- a/src/consts.rs +++ b/src/consts.rs @@ -25,7 +25,14 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { } } } - self.context.new_bitcast(None, value, typ) + // NOTE: since bitcast makes a value non-constant, don't bitcast if not necessary as some + // SIMD builtins require a constant value. + if value.get_type() != typ { + self.context.new_bitcast(None, value, typ) + } + else { + value + } } } @@ -171,8 +178,9 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { Some(kind) if !self.tcx.sess.fewer_names() => { let name = self.generate_local_symbol_name(kind); // TODO(antoyo): check if it's okay that no link_section is set. - // TODO(antoyo): set alignment here as well. - let global = self.declare_private_global(&name[..], self.val_ty(cv)); + + let typ = self.val_ty(cv).get_aligned(align.bytes()); + let global = self.declare_private_global(&name[..], typ); global } _ => { diff --git a/src/context.rs b/src/context.rs index 5e5b9e7e9b1b..83c4683a6683 100644 --- a/src/context.rs +++ b/src/context.rs @@ -269,11 +269,11 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { } pub fn is_native_int_type_or_bool(&self, typ: Type<'gcc>) -> bool { - self.is_native_int_type(typ) || typ == self.bool_type + self.is_native_int_type(typ) || typ.is_compatible_with(self.bool_type) } pub fn is_int_type_or_bool(&self, typ: Type<'gcc>) -> bool { - self.is_native_int_type(typ) || self.is_non_native_int_type(typ) || typ == self.bool_type + self.is_native_int_type(typ) || self.is_non_native_int_type(typ) || typ.is_compatible_with(self.bool_type) } pub fn sess(&self) -> &Session { diff --git a/src/int.rs b/src/int.rs index c3ed71ff7303..ed779d5d888d 100644 --- a/src/int.rs +++ b/src/int.rs @@ -153,8 +153,14 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let a_type = a.get_type(); let b_type = b.get_type(); if self.is_native_int_type_or_bool(a_type) && self.is_native_int_type_or_bool(b_type) { - if a.get_type() != b.get_type() { - b = self.context.new_cast(None, b, a.get_type()); + if a_type != b_type { + if a_type.is_vector() { + // Vector types need to be bitcast. + b = self.context.new_bitcast(None, b, a.get_type()); + } + else { + b = self.context.new_cast(None, b, a.get_type()); + } } self.context.new_binary_op(None, operation, a_type, a, b) } @@ -593,7 +599,10 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { let b_type = b.get_type(); let a_native = self.is_native_int_type_or_bool(a_type); let b_native = self.is_native_int_type_or_bool(b_type); - if a_native && b_native { + if a_type.is_vector() && b_type.is_vector() { + self.context.new_binary_op(None, operation, a_type, a, b) + } + else if a_native && b_native { if a_type != b_type { b = self.context.new_cast(None, b, a_type); } @@ -639,6 +648,9 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { else { // Since u128 and i128 are the only types that can be unsupported, we know the type of // value and the destination type have the same size, so a bitcast is fine. + + // TODO(antoyo): perhaps use __builtin_convertvector for vector casting. (This is elsewhere, + // though.) self.context.new_bitcast(None, value, dest_typ) } } diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index b074febc521e..1a2a352b5a3b 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -3,20 +3,122 @@ use gccjit::Function; use crate::context::CodegenCx; pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function<'gcc> { - let _gcc_name = + let gcc_name = match name { - "llvm.x86.xgetbv" => { - let gcc_name = "__builtin_trap"; - let func = cx.context.get_builtin_function(gcc_name); - cx.functions.borrow_mut().insert(gcc_name.to_string(), func); - return func; - }, + "llvm.x86.xgetbv" => "__builtin_ia32_xgetbv", // NOTE: this doc specifies the equivalent GCC builtins: http://huonw.github.io/llvmint/llvmint/x86/index.html + "llvm.x86.sse2.pmovmskb.128" => "__builtin_ia32_pmovmskb128", + "llvm.x86.avx2.pmovmskb" => "__builtin_ia32_pmovmskb256", "llvm.x86.sse2.cmp.pd" => "__builtin_ia32_cmppd", "llvm.x86.sse2.movmsk.pd" => "__builtin_ia32_movmskpd", - "llvm.x86.sse2.pmovmskb.128" => "__builtin_ia32_pmovmskb128", - _ => unimplemented!("unsupported LLVM intrinsic {}", name) + "llvm.x86.ssse3.pshuf.b.128" => "__builtin_ia32_pshufb128", + "llvm.x86.sse2.pause" => "__builtin_ia32_pause", + "llvm.x86.avx2.pshuf.b" => "__builtin_ia32_pshufb256", + "llvm.x86.avx2.pslli.d" => "__builtin_ia32_pslldi256", + "llvm.x86.avx2.psrli.d" => "__builtin_ia32_psrldi256", + "llvm.x86.avx.vzeroupper" => "__builtin_ia32_vzeroupper", + "llvm.x86.avx2.vperm2i128" => "__builtin_ia32_permti256", + "llvm.x86.avx2.psrli.w" => "__builtin_ia32_psrlwi256", + "llvm.x86.sse2.storeu.dq" => "__builtin_ia32_storedqu", + "llvm.x86.sse2.psrli.w" => "__builtin_ia32_psrlwi128", + "llvm.x86.avx2.pabs.d" => "__builtin_ia32_pabsd256", + "llvm.x86.sse2.psrli.q" => "__builtin_ia32_psrlqi128", + "llvm.x86.avx2.pabs.w" => "__builtin_ia32_pabsw256", + "llvm.x86.avx2.pblendvb" => "__builtin_ia32_pblendvb256", + "llvm.x86.avx2.pabs.b" => "__builtin_ia32_pabsb256", + "llvm.x86.avx2.psrli.q" => "__builtin_ia32_psrlqi256", + "llvm.x86.sse41.pblendvb" => "__builtin_ia32_pblendvb128", + "llvm.x86.avx2.pavg.w" => "__builtin_ia32_pavgw256", + "llvm.x86.avx2.pavg.b" => "__builtin_ia32_pavgb256", + "llvm.x86.avx2.phadd.w" => "__builtin_ia32_phaddw256", + "llvm.x86.avx2.phadd.d" => "__builtin_ia32_phaddd256", + "llvm.x86.avx2.phadd.sw" => "__builtin_ia32_phaddsw256", + "llvm.x86.avx2.phsub.w" => "__builtin_ia32_phsubw256", + "llvm.x86.avx2.phsub.d" => "__builtin_ia32_phsubd256", + "llvm.x86.avx2.phsub.sw" => "__builtin_ia32_phsubsw256", + "llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gatherd_d", + "llvm.x86.avx2.gather.d.d.256" => "__builtin_ia32_gatherd_d256", + "llvm.x86.avx2.gather.d.ps" => "__builtin_ia32_gatherd_ps", + "llvm.x86.avx2.gather.d.ps.256" => "__builtin_ia32_gatherd_ps256", + "llvm.x86.avx2.gather.d.q" => "__builtin_ia32_gatherd_q", + "llvm.x86.avx2.gather.d.q.256" => "__builtin_ia32_gatherd_q256", + "llvm.x86.avx2.gather.d.pd" => "__builtin_ia32_gatherd_pd", + "llvm.x86.avx2.gather.d.pd.256" => "__builtin_ia32_gatherd_pd256", + "llvm.x86.avx2.gather.q.d" => "__builtin_ia32_gatherq_d", + "llvm.x86.avx2.gather.q.d.256" => "__builtin_ia32_gatherq_d256", + "llvm.x86.avx2.gather.q.ps" => "__builtin_ia32_gatherq_ps", + "llvm.x86.avx2.gather.q.ps.256" => "__builtin_ia32_gatherq_ps256", + "llvm.x86.avx2.gather.q.q" => "__builtin_ia32_gatherq_q", + "llvm.x86.avx2.gather.q.q.256" => "__builtin_ia32_gatherq_q256", + "llvm.x86.avx2.gather.q.pd" => "__builtin_ia32_gatherq_pd", + "llvm.x86.avx2.gather.q.pd.256" => "__builtin_ia32_gatherq_pd256", + "llvm.x86.avx2.pmadd.wd" => "__builtin_ia32_pmaddwd256", + "llvm.x86.avx2.pmadd.ub.sw" => "__builtin_ia32_pmaddubsw256", + "llvm.x86.avx2.maskload.d" => "__builtin_ia32_maskloadd", + "llvm.x86.avx2.maskload.d.256" => "__builtin_ia32_maskloadd256", + "llvm.x86.avx2.maskload.q" => "__builtin_ia32_maskloadq", + "llvm.x86.avx2.maskload.q.256" => "__builtin_ia32_maskloadq256", + "llvm.x86.avx2.maskstore.d" => "__builtin_ia32_maskstored", + "llvm.x86.avx2.maskstore.d.256" => "__builtin_ia32_maskstored256", + "llvm.x86.avx2.maskstore.q" => "__builtin_ia32_maskstoreq", + "llvm.x86.avx2.maskstore.q.256" => "__builtin_ia32_maskstoreq256", + "llvm.x86.avx2.pmaxs.w" => "__builtin_ia32_pmaxsw256", + "llvm.x86.avx2.pmaxs.d" => "__builtin_ia32_pmaxsd256", + "llvm.x86.avx2.pmaxs.b" => "__builtin_ia32_pmaxsb256", + "llvm.x86.avx2.pmaxu.w" => "__builtin_ia32_pmaxuw256", + "llvm.x86.avx2.pmaxu.d" => "__builtin_ia32_pmaxud256", + "llvm.x86.avx2.pmaxu.b" => "__builtin_ia32_pmaxub256", + "llvm.x86.avx2.pmins.w" => "__builtin_ia32_pminsw256", + "llvm.x86.avx2.pmins.d" => "__builtin_ia32_pminsd256", + "llvm.x86.avx2.pmins.b" => "__builtin_ia32_pminsb256", + "llvm.x86.avx2.pminu.w" => "__builtin_ia32_pminuw256", + "llvm.x86.avx2.pminu.d" => "__builtin_ia32_pminud256", + "llvm.x86.avx2.pminu.b" => "__builtin_ia32_pminub256", + "llvm.x86.avx2.mpsadbw" => "__builtin_ia32_mpsadbw256", + "llvm.x86.avx2.pmul.dq" => "__builtin_ia32_pmuldq256", + "llvm.x86.avx2.pmulu.dq" => "__builtin_ia32_pmuludq256", + "llvm.x86.avx2.pmulh.w" => "__builtin_ia32_pmulhw256", + "llvm.x86.avx2.pmulhu.w" => "__builtin_ia32_pmulhuw256", + "llvm.x86.avx2.pmul.hr.sw" => "__builtin_ia32_pmulhrsw256", + "llvm.x86.avx2.packsswb" => "__builtin_ia32_packsswb256", + "llvm.x86.avx2.packssdw" => "__builtin_ia32_packssdw256", + "llvm.x86.avx2.packuswb" => "__builtin_ia32_packuswb256", + "llvm.x86.avx2.packusdw" => "__builtin_ia32_packusdw256", + "llvm.x86.avx2.permd" => "__builtin_ia32_permvarsi256", + "llvm.x86.avx2.permps" => "__builtin_ia32_permvarsf256", + "llvm.x86.avx2.psad.bw" => "__builtin_ia32_psadbw256", + "llvm.x86.avx2.psign.w" => "__builtin_ia32_psignw256", + "llvm.x86.avx2.psign.d" => "__builtin_ia32_psignd256", + "llvm.x86.avx2.psign.b" => "__builtin_ia32_psignb256", + "llvm.x86.avx2.psll.w" => "__builtin_ia32_psllw256", + "llvm.x86.avx2.psll.d" => "__builtin_ia32_pslld256", + "llvm.x86.avx2.psll.q" => "__builtin_ia32_psllq256", + "llvm.x86.avx2.pslli.w" => "__builtin_ia32_psllwi256", + "llvm.x86.avx2.pslli.q" => "__builtin_ia32_psllqi256", + "llvm.x86.avx2.psllv.d" => "__builtin_ia32_psllv4si", + "llvm.x86.avx2.psllv.d.256" => "__builtin_ia32_psllv8si", + "llvm.x86.avx2.psllv.q" => "__builtin_ia32_psllv2di", + "llvm.x86.avx2.psllv.q.256" => "__builtin_ia32_psllv4di", + "llvm.x86.avx2.psra.w" => "__builtin_ia32_psraw256", + "llvm.x86.avx2.psra.d" => "__builtin_ia32_psrad256", + "llvm.x86.avx2.psrai.w" => "__builtin_ia32_psrawi256", + "llvm.x86.avx2.psrai.d" => "__builtin_ia32_psradi256", + "llvm.x86.avx2.psrav.d" => "__builtin_ia32_psrav4si", + "llvm.x86.avx2.psrav.d.256" => "__builtin_ia32_psrav8si", + "llvm.x86.avx2.psrl.w" => "__builtin_ia32_psrlw256", + "llvm.x86.avx2.psrl.d" => "__builtin_ia32_psrld256", + "llvm.x86.avx2.psrl.q" => "__builtin_ia32_psrlq256", + "llvm.x86.avx2.psrlv.d" => "__builtin_ia32_psrlv4si", + "llvm.x86.avx2.psrlv.d.256" => "__builtin_ia32_psrlv8si", + "llvm.x86.avx2.psrlv.q" => "__builtin_ia32_psrlv2di", + "llvm.x86.avx2.psrlv.q.256" => "__builtin_ia32_psrlv4di", + "llvm.x86.sse.sqrt.ss" => "__builtin_ia32_sqrtss", + + "llvm.sqrt.v2f64" => "__builtin_ia32_sqrtpd", + _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), }; - unimplemented!(); + let func = cx.context.get_target_builtin_function(gcc_name); + cx.functions.borrow_mut().insert(gcc_name.to_string(), func); + func } diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index 7d7811c87821..11f1e7dd9993 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -1,4 +1,6 @@ -use gccjit::{RValue, Type}; +use std::cmp::Ordering; + +use gccjit::{RValue, Type, ToRValue}; use rustc_codegen_ssa::base::compare_simd_types; use rustc_codegen_ssa::common::{TypeKind, span_invalid_monomorphization_error}; use rustc_codegen_ssa::mir::operand::OperandRef; @@ -10,6 +12,7 @@ use rustc_middle::ty::{self, Ty}; use rustc_span::{Span, Symbol, sym}; use crate::builder::Builder; +use crate::intrinsic; pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, name: Symbol, callee_ty: Ty<'tcx>, args: &[OperandRef<'tcx, RValue<'gcc>>], ret_ty: Ty<'tcx>, llret_ty: Type<'gcc>, span: Span) -> Result, ()> { // macros for error handling: @@ -100,9 +103,27 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, } if let Some(stripped) = name_str.strip_prefix("simd_shuffle") { - let n: u64 = stripped.parse().unwrap_or_else(|_| { - span_bug!(span, "bad `simd_shuffle` instruction only caught in codegen?") - }); + let n: u64 = + if stripped.is_empty() { + // Make sure this is actually an array, since typeck only checks the length-suffixed + // version of this intrinsic. + match args[2].layout.ty.kind() { + ty::Array(ty, len) if matches!(ty.kind(), ty::Uint(ty::UintTy::U32)) => { + len.try_eval_usize(bx.cx.tcx, ty::ParamEnv::reveal_all()).unwrap_or_else(|| { + span_bug!(span, "could not evaluate shuffle index array length") + }) + } + _ => return_error!( + "simd_shuffle index must be an array of `u32`, got `{}`", + args[2].layout.ty + ), + } + } + else { + stripped.parse().unwrap_or_else(|_| { + span_bug!(span, "bad `simd_shuffle` instruction only caught in codegen?") + }) + }; require_simd!(ret_ty, "return"); @@ -133,6 +154,202 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, )); } + if name == sym::simd_insert { + require!( + in_elem == arg_tys[2], + "expected inserted type `{}` (element of input `{}`), found `{}`", + in_elem, + in_ty, + arg_tys[2] + ); + let vector = args[0].immediate(); + let index = args[1].immediate(); + let value = args[2].immediate(); + // TODO(antoyo): use a recursive unqualified() here. + let vector_type = vector.get_type().unqualified().dyncast_vector().expect("vector type"); + let element_type = vector_type.get_element_type(); + // NOTE: we cannot cast to an array and assign to its element here because the value might + // not be an l-value. So, call a builtin to set the element. + // TODO(antoyo): perhaps we could create a new vector or maybe there's a GIMPLE instruction for that? + let func_name = + match in_len { + 2 => { + if element_type == bx.i64_type { + "__builtin_ia32_vec_set_v2di" + } + else { + unimplemented!(); + } + }, + 4 => { + if element_type == bx.i32_type { + "__builtin_ia32_vec_set_v4si" + } + else { + unimplemented!(); + } + }, + 8 => { + if element_type == bx.i16_type { + "__builtin_ia32_vec_set_v8hi" + } + else { + unimplemented!(); + } + }, + _ => unimplemented!("Len: {}", in_len), + }; + let builtin = bx.context.get_target_builtin_function(func_name); + let param1_type = builtin.get_param(0).to_rvalue().get_type(); + let vector = + if vector.get_type() != param1_type { + bx.context.new_bitcast(None, vector, param1_type) + } + else { + vector + }; + let result = bx.context.new_call(None, builtin, &[vector, value, bx.context.new_cast(None, index, bx.int_type)]); + return Ok(bx.context.new_bitcast(None, result, vector.get_type())); + } + if name == sym::simd_extract { + require!( + ret_ty == in_elem, + "expected return type `{}` (element of input `{}`), found `{}`", + in_elem, + in_ty, + ret_ty + ); + let vector = args[0].immediate(); + return Ok(bx.context.new_vector_access(None, vector, args[1].immediate()).to_rvalue()); + } + + if name == sym::simd_cast { + require_simd!(ret_ty, "return"); + let (out_len, out_elem) = ret_ty.simd_size_and_type(bx.tcx()); + require!( + in_len == out_len, + "expected return type with length {} (same as input type `{}`), \ + found `{}` with length {}", + in_len, + in_ty, + ret_ty, + out_len + ); + // casting cares about nominal type, not just structural type + if in_elem == out_elem { + return Ok(args[0].immediate()); + } + + enum Style { + Float, + Int(/* is signed? */ bool), + Unsupported, + } + + let (in_style, in_width) = match in_elem.kind() { + // vectors of pointer-sized integers should've been + // disallowed before here, so this unwrap is safe. + ty::Int(i) => ( + Style::Int(true), + i.normalize(bx.tcx().sess.target.pointer_width).bit_width().unwrap(), + ), + ty::Uint(u) => ( + Style::Int(false), + u.normalize(bx.tcx().sess.target.pointer_width).bit_width().unwrap(), + ), + ty::Float(f) => (Style::Float, f.bit_width()), + _ => (Style::Unsupported, 0), + }; + let (out_style, out_width) = match out_elem.kind() { + ty::Int(i) => ( + Style::Int(true), + i.normalize(bx.tcx().sess.target.pointer_width).bit_width().unwrap(), + ), + ty::Uint(u) => ( + Style::Int(false), + u.normalize(bx.tcx().sess.target.pointer_width).bit_width().unwrap(), + ), + ty::Float(f) => (Style::Float, f.bit_width()), + _ => (Style::Unsupported, 0), + }; + + let extend = |in_type, out_type| { + let vector_type = bx.context.new_vector_type(out_type, 8); + let vector = args[0].immediate(); + let array_type = bx.context.new_array_type(None, in_type, 8); + let array = bx.context.new_bitcast(None, vector, array_type); + + let cast_vec_element = |index| { + let index = bx.context.new_rvalue_from_int(bx.int_type, index); + bx.context.new_cast(None, bx.context.new_array_access(None, array, index).to_rvalue(), out_type) + }; + + bx.context.new_rvalue_from_vector(None, vector_type, &[ + cast_vec_element(0), + cast_vec_element(1), + cast_vec_element(2), + cast_vec_element(3), + cast_vec_element(4), + cast_vec_element(5), + cast_vec_element(6), + cast_vec_element(7), + ]) + }; + + match (in_style, out_style) { + (Style::Int(in_is_signed), Style::Int(_)) => { + return Ok(match in_width.cmp(&out_width) { + Ordering::Greater => bx.trunc(args[0].immediate(), llret_ty), + Ordering::Equal => args[0].immediate(), + Ordering::Less => { + if in_is_signed { + match (in_width, out_width) { + // FIXME(antoyo): the function _mm_cvtepi8_epi16 should directly + // call an intrinsic equivalent to __builtin_ia32_pmovsxbw128 so that + // we can generate a call to it. + (8, 16) => extend(bx.i8_type, bx.i16_type), + (8, 32) => extend(bx.i8_type, bx.i32_type), + (8, 64) => extend(bx.i8_type, bx.i64_type), + (16, 32) => extend(bx.i16_type, bx.i32_type), + (32, 64) => extend(bx.i32_type, bx.i64_type), + (16, 64) => extend(bx.i16_type, bx.i64_type), + _ => unimplemented!("in: {}, out: {}", in_width, out_width), + } + } else { + match (in_width, out_width) { + (8, 16) => extend(bx.u8_type, bx.u16_type), + (8, 32) => extend(bx.u8_type, bx.u32_type), + (8, 64) => extend(bx.u8_type, bx.u64_type), + (16, 32) => extend(bx.u16_type, bx.u32_type), + (16, 64) => extend(bx.u16_type, bx.u64_type), + (32, 64) => extend(bx.u32_type, bx.u64_type), + _ => unimplemented!("in: {}, out: {}", in_width, out_width), + } + } + } + }); + } + (Style::Int(_), Style::Float) => { + unimplemented!(); + } + (Style::Float, Style::Int(_)) => { + unimplemented!(); + } + (Style::Float, Style::Float) => { + unimplemented!(); + } + _ => { /* Unsupported. Fallthrough. */ } + } + require!( + false, + "unsupported cast from `{}` with element `{}` to `{}` with element `{}`", + in_ty, + in_elem, + ret_ty, + out_elem + ); + } + macro_rules! arith_binary { ($($name: ident: $($($p: ident),* => $call: ident),*;)*) => { $(if name == sym::$name { @@ -150,6 +367,105 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, } } + fn simd_simple_float_intrinsic<'gcc, 'tcx>( + name: Symbol, + in_elem: Ty<'_>, + in_ty: Ty<'_>, + in_len: u64, + bx: &mut Builder<'_, 'gcc, 'tcx>, + span: Span, + args: &[OperandRef<'tcx, RValue<'gcc>>], + ) -> Result, ()> { + macro_rules! emit_error { + ($msg: tt) => { + emit_error!($msg, ) + }; + ($msg: tt, $($fmt: tt)*) => { + span_invalid_monomorphization_error( + bx.sess(), span, + &format!(concat!("invalid monomorphization of `{}` intrinsic: ", $msg), + name, $($fmt)*)); + } + } + macro_rules! return_error { + ($($fmt: tt)*) => { + { + emit_error!($($fmt)*); + return Err(()); + } + } + } + + let (elem_ty_str, elem_ty) = + if let ty::Float(f) = in_elem.kind() { + let elem_ty = bx.cx.type_float_from_ty(*f); + match f.bit_width() { + 32 => ("f32", elem_ty), + 64 => ("f64", elem_ty), + _ => { + return_error!( + "unsupported element type `{}` of floating-point vector `{}`", + f.name_str(), + in_ty + ); + } + } + } + else { + return_error!("`{}` is not a floating-point type", in_ty); + }; + + let vec_ty = bx.cx.type_vector(elem_ty, in_len); + + let (intr_name, fn_ty) = + match name { + sym::simd_ceil => ("ceil", bx.type_func(&[vec_ty], vec_ty)), + sym::simd_fabs => ("fabs", bx.type_func(&[vec_ty], vec_ty)), // TODO(antoyo): pand with 170141183420855150465331762880109871103 + sym::simd_fcos => ("cos", bx.type_func(&[vec_ty], vec_ty)), + sym::simd_fexp2 => ("exp2", bx.type_func(&[vec_ty], vec_ty)), + sym::simd_fexp => ("exp", bx.type_func(&[vec_ty], vec_ty)), + sym::simd_flog10 => ("log10", bx.type_func(&[vec_ty], vec_ty)), + sym::simd_flog2 => ("log2", bx.type_func(&[vec_ty], vec_ty)), + sym::simd_flog => ("log", bx.type_func(&[vec_ty], vec_ty)), + sym::simd_floor => ("floor", bx.type_func(&[vec_ty], vec_ty)), + sym::simd_fma => ("fma", bx.type_func(&[vec_ty, vec_ty, vec_ty], vec_ty)), + sym::simd_fpowi => ("powi", bx.type_func(&[vec_ty, bx.type_i32()], vec_ty)), + sym::simd_fpow => ("pow", bx.type_func(&[vec_ty, vec_ty], vec_ty)), + sym::simd_fsin => ("sin", bx.type_func(&[vec_ty], vec_ty)), + sym::simd_fsqrt => ("sqrt", bx.type_func(&[vec_ty], vec_ty)), + sym::simd_round => ("round", bx.type_func(&[vec_ty], vec_ty)), + sym::simd_trunc => ("trunc", bx.type_func(&[vec_ty], vec_ty)), + _ => return_error!("unrecognized intrinsic `{}`", name), + }; + let llvm_name = &format!("llvm.{0}.v{1}{2}", intr_name, in_len, elem_ty_str); + let function = intrinsic::llvm::intrinsic(llvm_name, &bx.cx); + let function: RValue<'gcc> = unsafe { std::mem::transmute(function) }; + let c = bx.call(fn_ty, function, &args.iter().map(|arg| arg.immediate()).collect::>(), None); + Ok(c) + } + + if std::matches!( + name, + sym::simd_ceil + | sym::simd_fabs + | sym::simd_fcos + | sym::simd_fexp2 + | sym::simd_fexp + | sym::simd_flog10 + | sym::simd_flog2 + | sym::simd_flog + | sym::simd_floor + | sym::simd_fma + | sym::simd_fpow + | sym::simd_fpowi + | sym::simd_fsin + | sym::simd_fsqrt + | sym::simd_round + | sym::simd_trunc + ) { + return simd_simple_float_intrinsic(name, in_elem, in_ty, in_len, bx, span, args); + } + arith_binary! { simd_add: Uint, Int => add, Float => fadd; simd_sub: Uint, Int => sub, Float => fsub; @@ -184,5 +500,41 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, simd_neg: Int => neg, Float => fneg; } + if name == sym::simd_saturating_add || name == sym::simd_saturating_sub { + let lhs = args[0].immediate(); + let rhs = args[1].immediate(); + let is_add = name == sym::simd_saturating_add; + let ptr_bits = bx.tcx().data_layout.pointer_size.bits() as _; + let (signed, elem_width, elem_ty) = match *in_elem.kind() { + ty::Int(i) => (true, i.bit_width().unwrap_or(ptr_bits), bx.cx.type_int_from_ty(i)), + ty::Uint(i) => (false, i.bit_width().unwrap_or(ptr_bits), bx.cx.type_uint_from_ty(i)), + _ => { + return_error!( + "expected element type `{}` of vector type `{}` \ + to be a signed or unsigned integer type", + arg_tys[0].simd_size_and_type(bx.tcx()).1, + arg_tys[0] + ); + } + }; + let builtin_name = + match (signed, is_add, in_len, elem_width) { + (true, true, 32, 8) => "__builtin_ia32_paddsb256", // TODO(antoyo): cast arguments to unsigned. + (false, true, 32, 8) => "__builtin_ia32_paddusb256", + (true, true, 16, 16) => "__builtin_ia32_paddsw256", + (false, true, 16, 16) => "__builtin_ia32_paddusw256", + (true, false, 16, 16) => "__builtin_ia32_psubsw256", + (false, false, 16, 16) => "__builtin_ia32_psubusw256", + (true, false, 32, 8) => "__builtin_ia32_psubsb256", + (false, false, 32, 8) => "__builtin_ia32_psubusb256", + _ => unimplemented!("signed: {}, is_add: {}, in_len: {}, elem_width: {}", signed, is_add, in_len, elem_width), + }; + let vec_ty = bx.cx.type_vector(elem_ty, in_len as u64); + + let func = bx.context.get_target_builtin_function(builtin_name); + let result = bx.context.new_call(None, func, &[lhs, rhs]); + return Ok(bx.context.new_bitcast(None, result, vec_ty)); + } + unimplemented!("simd {}", name); } diff --git a/src/lib.rs b/src/lib.rs index eac4a06226cf..a8029f0425a4 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -205,7 +205,7 @@ impl WriteBackendMethods for GccCodegenBackend { fn run_fat_lto(_cgcx: &CodegenContext, mut modules: Vec>, _cached_modules: Vec<(SerializedModule, WorkProduct)>) -> Result, FatalError> { // TODO(antoyo): implement LTO by sending -flto to libgccjit and adding the appropriate gcc linker plugins. // NOTE: implemented elsewhere. - // TODO: what is implemented elsewhere ^ ? + // TODO(antoyo): what is implemented elsewhere ^ ? let module = match modules.remove(0) { FatLTOInput::InMemory(module) => module, @@ -299,9 +299,17 @@ pub fn target_features(sess: &Session) -> Vec { if sess.is_nightly_build() || gate.is_none() { Some(feature) } else { None } }, ) - .filter(|_feature| { + .filter(|feature| { // TODO(antoyo): implement a way to get enabled feature in libgccjit. - false + // Probably using the equivalent of __builtin_cpu_supports. + feature.contains("sse") || feature.contains("avx") + /* + adx, aes, avx, avx2, avx512bf16, avx512bitalg, avx512bw, avx512cd, avx512dq, avx512er, avx512f, avx512gfni, + avx512ifma, avx512pf, avx512vaes, avx512vbmi, avx512vbmi2, avx512vl, avx512vnni, avx512vp2intersect, avx512vpclmulqdq, + avx512vpopcntdq, bmi1, bmi2, cmpxchg16b, ermsb, f16c, fma, fxsr, lzcnt, movbe, pclmulqdq, popcnt, rdrand, rdseed, rtm, + sha, sse, sse2, sse3, sse4.1, sse4.2, sse4a, ssse3, tbm, xsave, xsavec, xsaveopt, xsaves + */ + //false }) .map(|feature| Symbol::intern(feature)) .collect() diff --git a/src/type_.rs b/src/type_.rs index e95058085216..8a17d94da41f 100644 --- a/src/type_.rs +++ b/src/type_.rs @@ -3,10 +3,11 @@ use std::convert::TryInto; use gccjit::{RValue, Struct, Type}; use rustc_codegen_ssa::traits::{BaseTypeMethods, DerivedTypeMethods}; use rustc_codegen_ssa::common::TypeKind; -use rustc_middle::bug; +use rustc_middle::{bug, ty}; use rustc_middle::ty::layout::TyAndLayout; use rustc_target::abi::{AddressSpace, Align, Integer, Size}; +use crate::common::TypeReflection; use crate::context::CodegenCx; use crate::type_of::LayoutGccExt; @@ -60,6 +61,17 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { let ity = Integer::approximate_align(self, align); self.type_from_integer(ity) } + + pub fn type_vector(&self, ty: Type<'gcc>, len: u64) -> Type<'gcc> { + self.context.new_vector_type(ty, len) + } + + pub fn type_float_from_ty(&self, t: ty::FloatTy) -> Type<'gcc> { + match t { + ty::FloatTy::F32 => self.type_f32(), + ty::FloatTy::F64 => self.type_f64(), + } + } } impl<'gcc, 'tcx> BaseTypeMethods<'tcx> for CodegenCx<'gcc, 'tcx> { @@ -127,7 +139,7 @@ impl<'gcc, 'tcx> BaseTypeMethods<'tcx> for CodegenCx<'gcc, 'tcx> { else if typ.is_compatible_with(self.double_type) { TypeKind::Double } - else if typ.dyncast_vector().is_some() { + else if typ.is_vector() { TypeKind::Vector } else { @@ -141,7 +153,7 @@ impl<'gcc, 'tcx> BaseTypeMethods<'tcx> for CodegenCx<'gcc, 'tcx> { } fn type_ptr_to_ext(&self, ty: Type<'gcc>, _address_space: AddressSpace) -> Type<'gcc> { - // TODO(antoyo): use address_space + // TODO(antoyo): use address_space, perhaps with TYPE_ADDR_SPACE? ty.make_pointer() } @@ -167,10 +179,10 @@ impl<'gcc, 'tcx> BaseTypeMethods<'tcx> for CodegenCx<'gcc, 'tcx> { fn float_width(&self, typ: Type<'gcc>) -> usize { let f32 = self.context.new_type::(); let f64 = self.context.new_type::(); - if typ == f32 { + if typ.is_compatible_with(f32) { 32 } - else if typ == f64 { + else if typ.is_compatible_with(f64) { 64 } else { diff --git a/src/type_of.rs b/src/type_of.rs index ed8f0445ca3e..c6d6f91a7429 100644 --- a/src/type_of.rs +++ b/src/type_of.rs @@ -24,6 +24,28 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { I128 => self.type_u128(), } } + + pub fn type_int_from_ty(&self, t: ty::IntTy) -> Type<'gcc> { + match t { + ty::IntTy::Isize => self.type_isize(), + ty::IntTy::I8 => self.type_i8(), + ty::IntTy::I16 => self.type_i16(), + ty::IntTy::I32 => self.type_i32(), + ty::IntTy::I64 => self.type_i64(), + ty::IntTy::I128 => self.type_i128(), + } + } + + pub fn type_uint_from_ty(&self, t: ty::UintTy) -> Type<'gcc> { + match t { + ty::UintTy::Usize => self.type_isize(), + ty::UintTy::U8 => self.type_i8(), + ty::UintTy::U16 => self.type_i16(), + ty::UintTy::U32 => self.type_i32(), + ty::UintTy::U64 => self.type_i64(), + ty::UintTy::U128 => self.type_i128(), + } + } } pub fn uncached_gcc_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, layout: TyAndLayout<'tcx>, defer: &mut Option<(Struct<'gcc>, TyAndLayout<'tcx>)>) -> Type<'gcc> { diff --git a/test.sh b/test.sh index 1beeee136df3..1d2fbd0a24cf 100755 --- a/test.sh +++ b/test.sh @@ -97,25 +97,6 @@ function std_tests() { #echo "[BUILD] sysroot in release mode" #./build_sysroot/build_sysroot.sh --release -# TODO(antoyo): uncomment when it works. -#pushd simple-raytracer -#if [[ "$HOST_TRIPLE" = "$TARGET_TRIPLE" ]]; then - #echo "[BENCH COMPILE] ebobby/simple-raytracer" - #hyperfine --runs ${RUN_RUNS:-10} --warmup 1 --prepare "rm -r target/*/debug || true" \ - #"RUSTFLAGS='' cargo build --target $TARGET_TRIPLE" \ - #"../cargo.sh build" - - #echo "[BENCH RUN] ebobby/simple-raytracer" - #cp ./target/*/debug/main ./raytracer_cg_gccjit - #hyperfine --runs ${RUN_RUNS:-10} ./raytracer_cg_llvm ./raytracer_cg_gccjit -#else - #echo "[BENCH COMPILE] ebobby/simple-raytracer (skipped)" - #echo "[COMPILE] ebobby/simple-raytracer" - #../cargo.sh build - #echo "[BENCH RUN] ebobby/simple-raytracer (skipped)" -#fi -#popd - function test_libcore() { pushd build_sysroot/sysroot_src/library/core/tests echo "[TEST] libcore" @@ -124,19 +105,6 @@ function test_libcore() { popd } -# TODO(antoyo): uncomment when it works. -#pushd regex -#echo "[TEST] rust-lang/regex example shootout-regex-dna" -#../cargo.sh clean -## Make sure `[codegen mono items] start` doesn't poison the diff -#../cargo.sh build --example shootout-regex-dna -#cat examples/regexdna-input.txt | ../cargo.sh run --example shootout-regex-dna | grep -v "Spawned thread" > res.txt -#diff -u res.txt examples/regexdna-output.txt - -#echo "[TEST] rust-lang/regex tests" -#../cargo.sh test --tests -- --exclude-should-panic --test-threads 1 -Zunstable-options -#popd - #echo #echo "[BENCH COMPILE] mod_bench" @@ -153,6 +121,40 @@ function test_libcore() { #echo "[BENCH RUN] mod_bench" #hyperfine --runs ${RUN_RUNS:-10} ./target/out/mod_bench{,_inline} ./target/out/mod_bench_llvm_* +function extended_sysroot_tests() { + pushd rand + cargo clean + echo "[TEST] rust-random/rand" + ../cargo.sh test --workspace + popd + + #pushd simple-raytracer + #echo "[BENCH COMPILE] ebobby/simple-raytracer" + #hyperfine --runs "${RUN_RUNS:-10}" --warmup 1 --prepare "cargo clean" \ + #"RUSTC=rustc RUSTFLAGS='' cargo build" \ + #"../cargo.sh build" + + #echo "[BENCH RUN] ebobby/simple-raytracer" + #cp ./target/debug/main ./raytracer_cg_gcc + #hyperfine --runs "${RUN_RUNS:-10}" ./raytracer_cg_llvm ./raytracer_cg_gcc + #popd + + pushd regex + echo "[TEST] rust-lang/regex example shootout-regex-dna" + cargo clean + export CG_RUSTFLAGS="--cap-lints warn" # newer aho_corasick versions throw a deprecation warning + # Make sure `[codegen mono items] start` doesn't poison the diff + ../cargo.sh build --example shootout-regex-dna + cat examples/regexdna-input.txt \ + | ../cargo.sh run --example shootout-regex-dna \ + | grep -v "Spawned thread" > res.txt + diff -u res.txt examples/regexdna-output.txt + + echo "[TEST] rust-lang/regex tests" + ../cargo.sh test --tests -- --exclude-should-panic --test-threads 1 -Zunstable-options -q + popd +} + function test_rustc() { echo echo "[TEST] rust-lang/rust" @@ -165,23 +167,7 @@ function test_rustc() { git checkout $(rustc -V | cut -d' ' -f3 | tr -d '(') export RUSTFLAGS= - git apply - <( - cfg: Option<&str>, - ) -> test::TestDesc { - let mut ignore = false; - #[cfg(not(bootstrap))] -- let ignore_message: Option = None; -+ let ignore_message: Option<&str> = None; - let mut should_fail = false; - - let rustc_has_profiler_support = env::var_os("RUSTC_PROFILER_SUPPORT").is_some(); - -EOF + git apply ../rustc_patches/compile_test.patch || true rm config.toml || true @@ -205,7 +191,7 @@ EOF git checkout -- src/test/ui/issues/auxiliary/issue-3136-a.rs # contains //~ERROR, but shouldn't be removed - rm -r src/test/ui/{abi*,extern/,panic-runtime/,panics/,unsized-locals/,proc-macro/,threads-sendsync/,thinlto/,simd*,borrowck/,test*,*lto*.rs} || true + rm -r src/test/ui/{abi*,extern/,panic-runtime/,panics/,unsized-locals/,proc-macro/,threads-sendsync/,thinlto/,borrowck/,test*,*lto*.rs} || true for test in $(rg --files-with-matches "catch_unwind|should_panic|thread|lto" src/test/ui); do rm $test done @@ -239,6 +225,10 @@ case $1 in std_tests ;; + "--extended-tests") + extended_sysroot_tests + ;; + "--build-sysroot") build_sysroot ;; @@ -249,6 +239,7 @@ case $1 in build_sysroot std_tests test_libcore + extended_sysroot_tests test_rustc ;; esac From 267e5e1ea78138543c99330b784a5b013ee03064 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 6 Feb 2022 17:04:24 -0500 Subject: [PATCH 052/356] Add support for target builtins --- src/builder.rs | 4 ++++ src/int.rs | 4 ++-- src/intrinsic/simd.rs | 4 ++++ 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index d53e1712dc8f..a4616d8673ec 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -231,6 +231,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { } else { assert!(!((actual_ty.is_vector() && !expected_ty.is_vector()) || (!actual_ty.is_vector() && expected_ty.is_vector())), "{:?} ({}) -> {:?} ({}), index: {:?}[{}]", actual_ty, actual_ty.is_vector(), expected_ty, expected_ty.is_vector(), func_ptr, index); + // TODO(antoyo): perhaps use __builtin_convertvector for vector casting. self.bitcast(actual_val, expected_ty) } } @@ -1320,11 +1321,13 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { if vec_num_units < mask_num_units { // NOTE: the mask needs to be the same length as the input vectors, so join the 2 // vectors and create a dummy second vector. + // TODO(antoyo): switch to using new_vector_access. let array = self.context.new_bitcast(None, v1, array_type); let mut elements = vec![]; for i in 0..vec_num_units { elements.push(self.context.new_array_access(None, array, self.context.new_rvalue_from_int(self.int_type, i as i32)).to_rvalue()); } + // TODO(antoyo): switch to using new_vector_access. let array = self.context.new_bitcast(None, v2, array_type); for i in 0..vec_num_units { elements.push(self.context.new_array_access(None, array, self.context.new_rvalue_from_int(self.int_type, i as i32)).to_rvalue()); @@ -1347,6 +1350,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { // NOTE: if padding was added, only select the number of elements of the masks to // remove that padding in the result. let mut elements = vec![]; + // TODO(antoyo): switch to using new_vector_access. let array = self.context.new_bitcast(None, result, array_type); for i in 0..mask_num_units { elements.push(self.context.new_array_access(None, array, self.context.new_rvalue_from_int(self.int_type, i as i32)).to_rvalue()); diff --git a/src/int.rs b/src/int.rs index ed779d5d888d..0c5dab004668 100644 --- a/src/int.rs +++ b/src/int.rs @@ -156,6 +156,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { if a_type != b_type { if a_type.is_vector() { // Vector types need to be bitcast. + // TODO(antoyo): perhaps use __builtin_convertvector for vector casting. b = self.context.new_bitcast(None, b, a.get_type()); } else { @@ -649,8 +650,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { // Since u128 and i128 are the only types that can be unsupported, we know the type of // value and the destination type have the same size, so a bitcast is fine. - // TODO(antoyo): perhaps use __builtin_convertvector for vector casting. (This is elsewhere, - // though.) + // TODO(antoyo): perhaps use __builtin_convertvector for vector casting. self.context.new_bitcast(None, value, dest_typ) } } diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index 11f1e7dd9993..b8c6038896d8 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -203,12 +203,14 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let param1_type = builtin.get_param(0).to_rvalue().get_type(); let vector = if vector.get_type() != param1_type { + // TODO(antoyo): perhaps use __builtin_convertvector for vector casting. bx.context.new_bitcast(None, vector, param1_type) } else { vector }; let result = bx.context.new_call(None, builtin, &[vector, value, bx.context.new_cast(None, index, bx.int_type)]); + // TODO(antoyo): perhaps use __builtin_convertvector for vector casting. return Ok(bx.context.new_bitcast(None, result, vector.get_type())); } if name == sym::simd_extract { @@ -277,6 +279,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let vector_type = bx.context.new_vector_type(out_type, 8); let vector = args[0].immediate(); let array_type = bx.context.new_array_type(None, in_type, 8); + // TODO(antoyo): switch to using new_vector_access or __builtin_convertvector for vector casting. let array = bx.context.new_bitcast(None, vector, array_type); let cast_vec_element = |index| { @@ -533,6 +536,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let func = bx.context.get_target_builtin_function(builtin_name); let result = bx.context.new_call(None, func, &[lhs, rhs]); + // TODO(antoyo): perhaps use __builtin_convertvector for vector casting. return Ok(bx.context.new_bitcast(None, result, vec_ty)); } From 927eea3860330a52b4594bdad1a771499c8aee19 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Mon, 28 Mar 2022 21:23:17 -0400 Subject: [PATCH 053/356] Add support for packed struct --- src/type_.rs | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/type_.rs b/src/type_.rs index 8a17d94da41f..d65649ecfa3e 100644 --- a/src/type_.rs +++ b/src/type_.rs @@ -115,7 +115,7 @@ impl<'gcc, 'tcx> BaseTypeMethods<'tcx> for CodegenCx<'gcc, 'tcx> { self.context.new_function_pointer_type(None, return_type, params, false) } - fn type_struct(&self, fields: &[Type<'gcc>], _packed: bool) -> Type<'gcc> { + fn type_struct(&self, fields: &[Type<'gcc>], packed: bool) -> Type<'gcc> { let types = fields.to_vec(); if let Some(typ) = self.struct_types.borrow().get(fields) { return typ.clone(); @@ -123,8 +123,10 @@ impl<'gcc, 'tcx> BaseTypeMethods<'tcx> for CodegenCx<'gcc, 'tcx> { let fields: Vec<_> = fields.iter().enumerate() .map(|(index, field)| self.context.new_field(None, *field, &format!("field{}_TODO", index))) .collect(); - // TODO(antoyo): use packed. let typ = self.context.new_struct_type(None, "struct", &fields).as_type(); + if packed { + typ.set_packed(); + } self.struct_types.borrow_mut().insert(types, typ); typ } @@ -209,12 +211,14 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { self.type_array(self.type_from_integer(unit), size / unit_size) } - pub fn set_struct_body(&self, typ: Struct<'gcc>, fields: &[Type<'gcc>], _packed: bool) { - // TODO(antoyo): use packed. + pub fn set_struct_body(&self, typ: Struct<'gcc>, fields: &[Type<'gcc>], packed: bool) { let fields: Vec<_> = fields.iter().enumerate() .map(|(index, field)| self.context.new_field(None, *field, &format!("field_{}", index))) .collect(); typ.set_fields(None, &fields); + if packed { + typ.as_type().set_packed(); + } } pub fn type_named_struct(&self, name: &str) -> Struct<'gcc> { From 9bb797c2aef1a5175185f4c7d25fa23eaaeec326 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Sun, 27 Mar 2022 18:05:23 +0200 Subject: [PATCH 054/356] Add missing vendor intrinsics --- src/base.rs | 3 +++ src/intrinsic/llvm.rs | 14 ++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/src/base.rs b/src/base.rs index 4ce5cdaccd3a..d88fe9bca2ac 100644 --- a/src/base.rs +++ b/src/base.rs @@ -79,7 +79,10 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ // TODO(antoyo): only set on x86 platforms. context.add_command_line_option("-masm=intel"); // TODO(antoyo): only add the following cli argument if the feature is supported. + context.add_command_line_option("-msse2"); context.add_command_line_option("-mavx2"); + context.add_command_line_option("-msha"); + context.add_command_line_option("-mpclmul"); // FIXME(antoyo): the following causes an illegal instruction on vmovdqu64 in std_example on my CPU. // Only add if the CPU supports it. //context.add_command_line_option("-mavx512f"); diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 1a2a352b5a3b..7634c649bc34 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -16,6 +16,7 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.avx2.pshuf.b" => "__builtin_ia32_pshufb256", "llvm.x86.avx2.pslli.d" => "__builtin_ia32_pslldi256", "llvm.x86.avx2.psrli.d" => "__builtin_ia32_psrldi256", + "llvm.x86.sse2.pslli.q" => "__builtin_ia32_psllqi128", "llvm.x86.avx.vzeroupper" => "__builtin_ia32_vzeroupper", "llvm.x86.avx2.vperm2i128" => "__builtin_ia32_permti256", "llvm.x86.avx2.psrli.w" => "__builtin_ia32_psrlwi256", @@ -28,6 +29,11 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.avx2.pabs.b" => "__builtin_ia32_pabsb256", "llvm.x86.avx2.psrli.q" => "__builtin_ia32_psrlqi256", "llvm.x86.sse41.pblendvb" => "__builtin_ia32_pblendvb128", + "llvm.x86.sse41.pblendw" => "__builtin_ia32_pblendw128", + "llvm.x86.sse42.crc32.32.8" => "__builtin_ia32_crc32qi", + "llvm.x86.sse42.crc32.32.16" => "__builtin_ia32_crc32hi", + "llvm.x86.sse42.crc32.32.32" => "__builtin_ia32_crc32si", + "llvm.x86.sse42.crc32.64.64" => "__builtin_ia32_crc32di", "llvm.x86.avx2.pavg.w" => "__builtin_ia32_pavgw256", "llvm.x86.avx2.pavg.b" => "__builtin_ia32_pavgb256", "llvm.x86.avx2.phadd.w" => "__builtin_ia32_phaddw256", @@ -113,6 +119,14 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.avx2.psrlv.q" => "__builtin_ia32_psrlv2di", "llvm.x86.avx2.psrlv.q.256" => "__builtin_ia32_psrlv4di", "llvm.x86.sse.sqrt.ss" => "__builtin_ia32_sqrtss", + "llvm.x86.pclmulqdq" => "__builtin_ia32_pclmulqdq128", + "llvm.x86.sha1msg1" => "__builtin_ia32_sha1msg1", + "llvm.x86.sha1msg2" => "__builtin_ia32_sha1msg2", + "llvm.x86.sha1nexte" => "__builtin_ia32_sha1nexte", + "llvm.x86.sha1rnds4" => "__builtin_ia32_sha1rnds4", + "llvm.x86.sha256msg1" => "__builtin_ia32_sha256msg1", + "llvm.x86.sha256msg2" => "__builtin_ia32_sha256msg2", + "llvm.x86.sha256rnds2" => "__builtin_ia32_sha256rnds2", "llvm.sqrt.v2f64" => "__builtin_ia32_sqrtpd", _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), From 3970825b9272411c665bba95bc30894299c8520e Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Wed, 30 Mar 2022 16:20:58 +0200 Subject: [PATCH 055/356] Add intrinsic translation for x86 arch --- src/intrinsic/llvm.rs | 135 +------- src/intrinsic/x86.rs | 770 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 777 insertions(+), 128 deletions(-) create mode 100644 src/intrinsic/x86.rs diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 7634c649bc34..e6d8f78da603 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -3,134 +3,13 @@ use gccjit::Function; use crate::context::CodegenCx; pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function<'gcc> { - let gcc_name = - match name { - "llvm.x86.xgetbv" => "__builtin_ia32_xgetbv", - // NOTE: this doc specifies the equivalent GCC builtins: http://huonw.github.io/llvmint/llvmint/x86/index.html - "llvm.x86.sse2.pmovmskb.128" => "__builtin_ia32_pmovmskb128", - "llvm.x86.avx2.pmovmskb" => "__builtin_ia32_pmovmskb256", - "llvm.x86.sse2.cmp.pd" => "__builtin_ia32_cmppd", - "llvm.x86.sse2.movmsk.pd" => "__builtin_ia32_movmskpd", - "llvm.x86.ssse3.pshuf.b.128" => "__builtin_ia32_pshufb128", - "llvm.x86.sse2.pause" => "__builtin_ia32_pause", - "llvm.x86.avx2.pshuf.b" => "__builtin_ia32_pshufb256", - "llvm.x86.avx2.pslli.d" => "__builtin_ia32_pslldi256", - "llvm.x86.avx2.psrli.d" => "__builtin_ia32_psrldi256", - "llvm.x86.sse2.pslli.q" => "__builtin_ia32_psllqi128", - "llvm.x86.avx.vzeroupper" => "__builtin_ia32_vzeroupper", - "llvm.x86.avx2.vperm2i128" => "__builtin_ia32_permti256", - "llvm.x86.avx2.psrli.w" => "__builtin_ia32_psrlwi256", - "llvm.x86.sse2.storeu.dq" => "__builtin_ia32_storedqu", - "llvm.x86.sse2.psrli.w" => "__builtin_ia32_psrlwi128", - "llvm.x86.avx2.pabs.d" => "__builtin_ia32_pabsd256", - "llvm.x86.sse2.psrli.q" => "__builtin_ia32_psrlqi128", - "llvm.x86.avx2.pabs.w" => "__builtin_ia32_pabsw256", - "llvm.x86.avx2.pblendvb" => "__builtin_ia32_pblendvb256", - "llvm.x86.avx2.pabs.b" => "__builtin_ia32_pabsb256", - "llvm.x86.avx2.psrli.q" => "__builtin_ia32_psrlqi256", - "llvm.x86.sse41.pblendvb" => "__builtin_ia32_pblendvb128", - "llvm.x86.sse41.pblendw" => "__builtin_ia32_pblendw128", - "llvm.x86.sse42.crc32.32.8" => "__builtin_ia32_crc32qi", - "llvm.x86.sse42.crc32.32.16" => "__builtin_ia32_crc32hi", - "llvm.x86.sse42.crc32.32.32" => "__builtin_ia32_crc32si", - "llvm.x86.sse42.crc32.64.64" => "__builtin_ia32_crc32di", - "llvm.x86.avx2.pavg.w" => "__builtin_ia32_pavgw256", - "llvm.x86.avx2.pavg.b" => "__builtin_ia32_pavgb256", - "llvm.x86.avx2.phadd.w" => "__builtin_ia32_phaddw256", - "llvm.x86.avx2.phadd.d" => "__builtin_ia32_phaddd256", - "llvm.x86.avx2.phadd.sw" => "__builtin_ia32_phaddsw256", - "llvm.x86.avx2.phsub.w" => "__builtin_ia32_phsubw256", - "llvm.x86.avx2.phsub.d" => "__builtin_ia32_phsubd256", - "llvm.x86.avx2.phsub.sw" => "__builtin_ia32_phsubsw256", - "llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gatherd_d", - "llvm.x86.avx2.gather.d.d.256" => "__builtin_ia32_gatherd_d256", - "llvm.x86.avx2.gather.d.ps" => "__builtin_ia32_gatherd_ps", - "llvm.x86.avx2.gather.d.ps.256" => "__builtin_ia32_gatherd_ps256", - "llvm.x86.avx2.gather.d.q" => "__builtin_ia32_gatherd_q", - "llvm.x86.avx2.gather.d.q.256" => "__builtin_ia32_gatherd_q256", - "llvm.x86.avx2.gather.d.pd" => "__builtin_ia32_gatherd_pd", - "llvm.x86.avx2.gather.d.pd.256" => "__builtin_ia32_gatherd_pd256", - "llvm.x86.avx2.gather.q.d" => "__builtin_ia32_gatherq_d", - "llvm.x86.avx2.gather.q.d.256" => "__builtin_ia32_gatherq_d256", - "llvm.x86.avx2.gather.q.ps" => "__builtin_ia32_gatherq_ps", - "llvm.x86.avx2.gather.q.ps.256" => "__builtin_ia32_gatherq_ps256", - "llvm.x86.avx2.gather.q.q" => "__builtin_ia32_gatherq_q", - "llvm.x86.avx2.gather.q.q.256" => "__builtin_ia32_gatherq_q256", - "llvm.x86.avx2.gather.q.pd" => "__builtin_ia32_gatherq_pd", - "llvm.x86.avx2.gather.q.pd.256" => "__builtin_ia32_gatherq_pd256", - "llvm.x86.avx2.pmadd.wd" => "__builtin_ia32_pmaddwd256", - "llvm.x86.avx2.pmadd.ub.sw" => "__builtin_ia32_pmaddubsw256", - "llvm.x86.avx2.maskload.d" => "__builtin_ia32_maskloadd", - "llvm.x86.avx2.maskload.d.256" => "__builtin_ia32_maskloadd256", - "llvm.x86.avx2.maskload.q" => "__builtin_ia32_maskloadq", - "llvm.x86.avx2.maskload.q.256" => "__builtin_ia32_maskloadq256", - "llvm.x86.avx2.maskstore.d" => "__builtin_ia32_maskstored", - "llvm.x86.avx2.maskstore.d.256" => "__builtin_ia32_maskstored256", - "llvm.x86.avx2.maskstore.q" => "__builtin_ia32_maskstoreq", - "llvm.x86.avx2.maskstore.q.256" => "__builtin_ia32_maskstoreq256", - "llvm.x86.avx2.pmaxs.w" => "__builtin_ia32_pmaxsw256", - "llvm.x86.avx2.pmaxs.d" => "__builtin_ia32_pmaxsd256", - "llvm.x86.avx2.pmaxs.b" => "__builtin_ia32_pmaxsb256", - "llvm.x86.avx2.pmaxu.w" => "__builtin_ia32_pmaxuw256", - "llvm.x86.avx2.pmaxu.d" => "__builtin_ia32_pmaxud256", - "llvm.x86.avx2.pmaxu.b" => "__builtin_ia32_pmaxub256", - "llvm.x86.avx2.pmins.w" => "__builtin_ia32_pminsw256", - "llvm.x86.avx2.pmins.d" => "__builtin_ia32_pminsd256", - "llvm.x86.avx2.pmins.b" => "__builtin_ia32_pminsb256", - "llvm.x86.avx2.pminu.w" => "__builtin_ia32_pminuw256", - "llvm.x86.avx2.pminu.d" => "__builtin_ia32_pminud256", - "llvm.x86.avx2.pminu.b" => "__builtin_ia32_pminub256", - "llvm.x86.avx2.mpsadbw" => "__builtin_ia32_mpsadbw256", - "llvm.x86.avx2.pmul.dq" => "__builtin_ia32_pmuldq256", - "llvm.x86.avx2.pmulu.dq" => "__builtin_ia32_pmuludq256", - "llvm.x86.avx2.pmulh.w" => "__builtin_ia32_pmulhw256", - "llvm.x86.avx2.pmulhu.w" => "__builtin_ia32_pmulhuw256", - "llvm.x86.avx2.pmul.hr.sw" => "__builtin_ia32_pmulhrsw256", - "llvm.x86.avx2.packsswb" => "__builtin_ia32_packsswb256", - "llvm.x86.avx2.packssdw" => "__builtin_ia32_packssdw256", - "llvm.x86.avx2.packuswb" => "__builtin_ia32_packuswb256", - "llvm.x86.avx2.packusdw" => "__builtin_ia32_packusdw256", - "llvm.x86.avx2.permd" => "__builtin_ia32_permvarsi256", - "llvm.x86.avx2.permps" => "__builtin_ia32_permvarsf256", - "llvm.x86.avx2.psad.bw" => "__builtin_ia32_psadbw256", - "llvm.x86.avx2.psign.w" => "__builtin_ia32_psignw256", - "llvm.x86.avx2.psign.d" => "__builtin_ia32_psignd256", - "llvm.x86.avx2.psign.b" => "__builtin_ia32_psignb256", - "llvm.x86.avx2.psll.w" => "__builtin_ia32_psllw256", - "llvm.x86.avx2.psll.d" => "__builtin_ia32_pslld256", - "llvm.x86.avx2.psll.q" => "__builtin_ia32_psllq256", - "llvm.x86.avx2.pslli.w" => "__builtin_ia32_psllwi256", - "llvm.x86.avx2.pslli.q" => "__builtin_ia32_psllqi256", - "llvm.x86.avx2.psllv.d" => "__builtin_ia32_psllv4si", - "llvm.x86.avx2.psllv.d.256" => "__builtin_ia32_psllv8si", - "llvm.x86.avx2.psllv.q" => "__builtin_ia32_psllv2di", - "llvm.x86.avx2.psllv.q.256" => "__builtin_ia32_psllv4di", - "llvm.x86.avx2.psra.w" => "__builtin_ia32_psraw256", - "llvm.x86.avx2.psra.d" => "__builtin_ia32_psrad256", - "llvm.x86.avx2.psrai.w" => "__builtin_ia32_psrawi256", - "llvm.x86.avx2.psrai.d" => "__builtin_ia32_psradi256", - "llvm.x86.avx2.psrav.d" => "__builtin_ia32_psrav4si", - "llvm.x86.avx2.psrav.d.256" => "__builtin_ia32_psrav8si", - "llvm.x86.avx2.psrl.w" => "__builtin_ia32_psrlw256", - "llvm.x86.avx2.psrl.d" => "__builtin_ia32_psrld256", - "llvm.x86.avx2.psrl.q" => "__builtin_ia32_psrlq256", - "llvm.x86.avx2.psrlv.d" => "__builtin_ia32_psrlv4si", - "llvm.x86.avx2.psrlv.d.256" => "__builtin_ia32_psrlv8si", - "llvm.x86.avx2.psrlv.q" => "__builtin_ia32_psrlv2di", - "llvm.x86.avx2.psrlv.q.256" => "__builtin_ia32_psrlv4di", - "llvm.x86.sse.sqrt.ss" => "__builtin_ia32_sqrtss", - "llvm.x86.pclmulqdq" => "__builtin_ia32_pclmulqdq128", - "llvm.x86.sha1msg1" => "__builtin_ia32_sha1msg1", - "llvm.x86.sha1msg2" => "__builtin_ia32_sha1msg2", - "llvm.x86.sha1nexte" => "__builtin_ia32_sha1nexte", - "llvm.x86.sha1rnds4" => "__builtin_ia32_sha1rnds4", - "llvm.x86.sha256msg1" => "__builtin_ia32_sha256msg1", - "llvm.x86.sha256msg2" => "__builtin_ia32_sha256msg2", - "llvm.x86.sha256rnds2" => "__builtin_ia32_sha256rnds2", - - "llvm.sqrt.v2f64" => "__builtin_ia32_sqrtpd", - _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), - }; + let gcc_name = match name { + "llvm.x86.xgetbv" => "__builtin_ia32_xgetbv", + // NOTE: this doc specifies the equivalent GCC builtins: http://huonw.github.io/llvmint/llvmint/x86/index.html + "llvm.sqrt.v2f64" => "__builtin_ia32_sqrtpd", + // NOTE: this file is generated by https://github.com/GuillaumeGomez/llvmint/blob/master/generate_list.py + _ => include!("x86.rs"), + }; let func = cx.context.get_target_builtin_function(gcc_name); cx.functions.borrow_mut().insert(gcc_name.to_string(), func); diff --git a/src/intrinsic/x86.rs b/src/intrinsic/x86.rs new file mode 100644 index 000000000000..4918325e74c8 --- /dev/null +++ b/src/intrinsic/x86.rs @@ -0,0 +1,770 @@ +match name { +// x86 +"llvm.x86.addcarry.u32" => "__builtin_ia32_addcarry_u32", +"llvm.x86.addcarry.u64" => "__builtin_ia32_addcarry_u64", +"llvm.x86.addcarryx.u32" => "__builtin_ia32_addcarryx_u32", +"llvm.x86.addcarryx.u64" => "__builtin_ia32_addcarryx_u64", +"llvm.x86.aesni.aesdec" => "__builtin_ia32_aesdec128", +"llvm.x86.aesni.aesdeclast" => "__builtin_ia32_aesdeclast128", +"llvm.x86.aesni.aesenc" => "__builtin_ia32_aesenc128", +"llvm.x86.aesni.aesenclast" => "__builtin_ia32_aesenclast128", +"llvm.x86.aesni.aesimc" => "__builtin_ia32_aesimc128", +"llvm.x86.aesni.aeskeygenassist" => "__builtin_ia32_aeskeygenassist128", +"llvm.x86.avx.addsub.pd.256" => "__builtin_ia32_addsubpd256", +"llvm.x86.avx.addsub.ps.256" => "__builtin_ia32_addsubps256", +"llvm.x86.avx.blend.pd.256" => "__builtin_ia32_blendpd256", +"llvm.x86.avx.blend.ps.256" => "__builtin_ia32_blendps256", +"llvm.x86.avx.blendv.pd.256" => "__builtin_ia32_blendvpd256", +"llvm.x86.avx.blendv.ps.256" => "__builtin_ia32_blendvps256", +"llvm.x86.avx.cmp.pd.256" => "__builtin_ia32_cmppd256", +"llvm.x86.avx.cmp.ps.256" => "__builtin_ia32_cmpps256", +"llvm.x86.avx.cvt.pd2.ps.256" => "__builtin_ia32_cvtpd2ps256", +"llvm.x86.avx.cvt.pd2dq.256" => "__builtin_ia32_cvtpd2dq256", +"llvm.x86.avx.cvt.ps2.pd.256" => "__builtin_ia32_cvtps2pd256", +"llvm.x86.avx.cvt.ps2dq.256" => "__builtin_ia32_cvtps2dq256", +"llvm.x86.avx.cvtdq2.pd.256" => "__builtin_ia32_cvtdq2pd256", +"llvm.x86.avx.cvtdq2.ps.256" => "__builtin_ia32_cvtdq2ps256", +"llvm.x86.avx.cvtt.pd2dq.256" => "__builtin_ia32_cvttpd2dq256", +"llvm.x86.avx.cvtt.ps2dq.256" => "__builtin_ia32_cvttps2dq256", +"llvm.x86.avx.dp.ps.256" => "__builtin_ia32_dpps256", +"llvm.x86.avx.hadd.pd.256" => "__builtin_ia32_haddpd256", +"llvm.x86.avx.hadd.ps.256" => "__builtin_ia32_haddps256", +"llvm.x86.avx.hsub.pd.256" => "__builtin_ia32_hsubpd256", +"llvm.x86.avx.hsub.ps.256" => "__builtin_ia32_hsubps256", +"llvm.x86.avx.ldu.dq.256" => "__builtin_ia32_lddqu256", +"llvm.x86.avx.maskload.pd" => "__builtin_ia32_maskloadpd", +"llvm.x86.avx.maskload.pd.256" => "__builtin_ia32_maskloadpd256", +"llvm.x86.avx.maskload.ps" => "__builtin_ia32_maskloadps", +"llvm.x86.avx.maskload.ps.256" => "__builtin_ia32_maskloadps256", +"llvm.x86.avx.maskstore.pd" => "__builtin_ia32_maskstorepd", +"llvm.x86.avx.maskstore.pd.256" => "__builtin_ia32_maskstorepd256", +"llvm.x86.avx.maskstore.ps" => "__builtin_ia32_maskstoreps", +"llvm.x86.avx.maskstore.ps.256" => "__builtin_ia32_maskstoreps256", +"llvm.x86.avx.max.pd.256" => "__builtin_ia32_maxpd256", +"llvm.x86.avx.max.ps.256" => "__builtin_ia32_maxps256", +"llvm.x86.avx.min.pd.256" => "__builtin_ia32_minpd256", +"llvm.x86.avx.min.ps.256" => "__builtin_ia32_minps256", +"llvm.x86.avx.movmsk.pd.256" => "__builtin_ia32_movmskpd256", +"llvm.x86.avx.movmsk.ps.256" => "__builtin_ia32_movmskps256", +"llvm.x86.avx.ptestc.256" => "__builtin_ia32_ptestc256", +"llvm.x86.avx.ptestnzc.256" => "__builtin_ia32_ptestnzc256", +"llvm.x86.avx.ptestz.256" => "__builtin_ia32_ptestz256", +"llvm.x86.avx.rcp.ps.256" => "__builtin_ia32_rcpps256", +"llvm.x86.avx.round.pd.256" => "__builtin_ia32_roundpd256", +"llvm.x86.avx.round.ps.256" => "__builtin_ia32_roundps256", +"llvm.x86.avx.rsqrt.ps.256" => "__builtin_ia32_rsqrtps256", +"llvm.x86.avx.sqrt.pd.256" => "__builtin_ia32_sqrtpd256", +"llvm.x86.avx.sqrt.ps.256" => "__builtin_ia32_sqrtps256", +"llvm.x86.avx.storeu.dq.256" => "__builtin_ia32_storedqu256", +"llvm.x86.avx.storeu.pd.256" => "__builtin_ia32_storeupd256", +"llvm.x86.avx.storeu.ps.256" => "__builtin_ia32_storeups256", +"llvm.x86.avx.vbroadcastf128.pd.256" => "__builtin_ia32_vbroadcastf128_pd256", +"llvm.x86.avx.vbroadcastf128.ps.256" => "__builtin_ia32_vbroadcastf128_ps256", +"llvm.x86.avx.vextractf128.pd.256" => "__builtin_ia32_vextractf128_pd256", +"llvm.x86.avx.vextractf128.ps.256" => "__builtin_ia32_vextractf128_ps256", +"llvm.x86.avx.vextractf128.si.256" => "__builtin_ia32_vextractf128_si256", +"llvm.x86.avx.vinsertf128.pd.256" => "__builtin_ia32_vinsertf128_pd256", +"llvm.x86.avx.vinsertf128.ps.256" => "__builtin_ia32_vinsertf128_ps256", +"llvm.x86.avx.vinsertf128.si.256" => "__builtin_ia32_vinsertf128_si256", +"llvm.x86.avx.vperm2f128.pd.256" => "__builtin_ia32_vperm2f128_pd256", +"llvm.x86.avx.vperm2f128.ps.256" => "__builtin_ia32_vperm2f128_ps256", +"llvm.x86.avx.vperm2f128.si.256" => "__builtin_ia32_vperm2f128_si256", +"llvm.x86.avx.vpermilvar.pd" => "__builtin_ia32_vpermilvarpd", +"llvm.x86.avx.vpermilvar.pd.256" => "__builtin_ia32_vpermilvarpd256", +"llvm.x86.avx.vpermilvar.ps" => "__builtin_ia32_vpermilvarps", +"llvm.x86.avx.vpermilvar.ps.256" => "__builtin_ia32_vpermilvarps256", +"llvm.x86.avx.vtestc.pd" => "__builtin_ia32_vtestcpd", +"llvm.x86.avx.vtestc.pd.256" => "__builtin_ia32_vtestcpd256", +"llvm.x86.avx.vtestc.ps" => "__builtin_ia32_vtestcps", +"llvm.x86.avx.vtestc.ps.256" => "__builtin_ia32_vtestcps256", +"llvm.x86.avx.vtestnzc.pd" => "__builtin_ia32_vtestnzcpd", +"llvm.x86.avx.vtestnzc.pd.256" => "__builtin_ia32_vtestnzcpd256", +"llvm.x86.avx.vtestnzc.ps" => "__builtin_ia32_vtestnzcps", +"llvm.x86.avx.vtestnzc.ps.256" => "__builtin_ia32_vtestnzcps256", +"llvm.x86.avx.vtestz.pd" => "__builtin_ia32_vtestzpd", +"llvm.x86.avx.vtestz.pd.256" => "__builtin_ia32_vtestzpd256", +"llvm.x86.avx.vtestz.ps" => "__builtin_ia32_vtestzps", +"llvm.x86.avx.vtestz.ps.256" => "__builtin_ia32_vtestzps256", +"llvm.x86.avx.vzeroall" => "__builtin_ia32_vzeroall", +"llvm.x86.avx.vzeroupper" => "__builtin_ia32_vzeroupper", +"llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gatherd_d", +"llvm.x86.avx2.gather.d.d.256" => "__builtin_ia32_gatherd_d256", +"llvm.x86.avx2.gather.d.pd" => "__builtin_ia32_gatherd_pd", +"llvm.x86.avx2.gather.d.pd.256" => "__builtin_ia32_gatherd_pd256", +"llvm.x86.avx2.gather.d.ps" => "__builtin_ia32_gatherd_ps", +"llvm.x86.avx2.gather.d.ps.256" => "__builtin_ia32_gatherd_ps256", +"llvm.x86.avx2.gather.d.q" => "__builtin_ia32_gatherd_q", +"llvm.x86.avx2.gather.d.q.256" => "__builtin_ia32_gatherd_q256", +"llvm.x86.avx2.gather.q.d" => "__builtin_ia32_gatherq_d", +"llvm.x86.avx2.gather.q.d.256" => "__builtin_ia32_gatherq_d256", +"llvm.x86.avx2.gather.q.pd" => "__builtin_ia32_gatherq_pd", +"llvm.x86.avx2.gather.q.pd.256" => "__builtin_ia32_gatherq_pd256", +"llvm.x86.avx2.gather.q.ps" => "__builtin_ia32_gatherq_ps", +"llvm.x86.avx2.gather.q.ps.256" => "__builtin_ia32_gatherq_ps256", +"llvm.x86.avx2.gather.q.q" => "__builtin_ia32_gatherq_q", +"llvm.x86.avx2.gather.q.q.256" => "__builtin_ia32_gatherq_q256", +"llvm.x86.avx2.maskload.d" => "__builtin_ia32_maskloadd", +"llvm.x86.avx2.maskload.d.256" => "__builtin_ia32_maskloadd256", +"llvm.x86.avx2.maskload.q" => "__builtin_ia32_maskloadq", +"llvm.x86.avx2.maskload.q.256" => "__builtin_ia32_maskloadq256", +"llvm.x86.avx2.maskstore.d" => "__builtin_ia32_maskstored", +"llvm.x86.avx2.maskstore.d.256" => "__builtin_ia32_maskstored256", +"llvm.x86.avx2.maskstore.q" => "__builtin_ia32_maskstoreq", +"llvm.x86.avx2.maskstore.q.256" => "__builtin_ia32_maskstoreq256", +"llvm.x86.avx2.movntdqa" => "__builtin_ia32_movntdqa256", +"llvm.x86.avx2.mpsadbw" => "__builtin_ia32_mpsadbw256", +"llvm.x86.avx2.pabs.b" => "__builtin_ia32_pabsb256", +"llvm.x86.avx2.pabs.d" => "__builtin_ia32_pabsd256", +"llvm.x86.avx2.pabs.w" => "__builtin_ia32_pabsw256", +"llvm.x86.avx2.packssdw" => "__builtin_ia32_packssdw256", +"llvm.x86.avx2.packsswb" => "__builtin_ia32_packsswb256", +"llvm.x86.avx2.packusdw" => "__builtin_ia32_packusdw256", +"llvm.x86.avx2.packuswb" => "__builtin_ia32_packuswb256", +"llvm.x86.avx2.padds.b" => "__builtin_ia32_paddsb256", +"llvm.x86.avx2.padds.w" => "__builtin_ia32_paddsw256", +"llvm.x86.avx2.paddus.b" => "__builtin_ia32_paddusb256", +"llvm.x86.avx2.paddus.w" => "__builtin_ia32_paddusw256", +"llvm.x86.avx2.pavg.b" => "__builtin_ia32_pavgb256", +"llvm.x86.avx2.pavg.w" => "__builtin_ia32_pavgw256", +"llvm.x86.avx2.pblendd.128" => "__builtin_ia32_pblendd128", +"llvm.x86.avx2.pblendd.256" => "__builtin_ia32_pblendd256", +"llvm.x86.avx2.pblendvb" => "__builtin_ia32_pblendvb256", +"llvm.x86.avx2.pblendw" => "__builtin_ia32_pblendw256", +"llvm.x86.avx2.pbroadcastb.128" => "__builtin_ia32_pbroadcastb128", +"llvm.x86.avx2.pbroadcastb.256" => "__builtin_ia32_pbroadcastb256", +"llvm.x86.avx2.pbroadcastd.128" => "__builtin_ia32_pbroadcastd128", +"llvm.x86.avx2.pbroadcastd.256" => "__builtin_ia32_pbroadcastd256", +"llvm.x86.avx2.pbroadcastq.128" => "__builtin_ia32_pbroadcastq128", +"llvm.x86.avx2.pbroadcastq.256" => "__builtin_ia32_pbroadcastq256", +"llvm.x86.avx2.pbroadcastw.128" => "__builtin_ia32_pbroadcastw128", +"llvm.x86.avx2.pbroadcastw.256" => "__builtin_ia32_pbroadcastw256", +"llvm.x86.avx2.permd" => "__builtin_ia32_permvarsi256", +"llvm.x86.avx2.permps" => "__builtin_ia32_permvarsf256", +"llvm.x86.avx2.phadd.d" => "__builtin_ia32_phaddd256", +"llvm.x86.avx2.phadd.sw" => "__builtin_ia32_phaddsw256", +"llvm.x86.avx2.phadd.w" => "__builtin_ia32_phaddw256", +"llvm.x86.avx2.phsub.d" => "__builtin_ia32_phsubd256", +"llvm.x86.avx2.phsub.sw" => "__builtin_ia32_phsubsw256", +"llvm.x86.avx2.phsub.w" => "__builtin_ia32_phsubw256", +"llvm.x86.avx2.pmadd.ub.sw" => "__builtin_ia32_pmaddubsw256", +"llvm.x86.avx2.pmadd.wd" => "__builtin_ia32_pmaddwd256", +"llvm.x86.avx2.pmaxs.b" => "__builtin_ia32_pmaxsb256", +"llvm.x86.avx2.pmaxs.d" => "__builtin_ia32_pmaxsd256", +"llvm.x86.avx2.pmaxs.w" => "__builtin_ia32_pmaxsw256", +"llvm.x86.avx2.pmaxu.b" => "__builtin_ia32_pmaxub256", +"llvm.x86.avx2.pmaxu.d" => "__builtin_ia32_pmaxud256", +"llvm.x86.avx2.pmaxu.w" => "__builtin_ia32_pmaxuw256", +"llvm.x86.avx2.pmins.b" => "__builtin_ia32_pminsb256", +"llvm.x86.avx2.pmins.d" => "__builtin_ia32_pminsd256", +"llvm.x86.avx2.pmins.w" => "__builtin_ia32_pminsw256", +"llvm.x86.avx2.pminu.b" => "__builtin_ia32_pminub256", +"llvm.x86.avx2.pminu.d" => "__builtin_ia32_pminud256", +"llvm.x86.avx2.pminu.w" => "__builtin_ia32_pminuw256", +"llvm.x86.avx2.pmovmskb" => "__builtin_ia32_pmovmskb256", +"llvm.x86.avx2.pmovsxbd" => "__builtin_ia32_pmovsxbd256", +"llvm.x86.avx2.pmovsxbq" => "__builtin_ia32_pmovsxbq256", +"llvm.x86.avx2.pmovsxbw" => "__builtin_ia32_pmovsxbw256", +"llvm.x86.avx2.pmovsxdq" => "__builtin_ia32_pmovsxdq256", +"llvm.x86.avx2.pmovsxwd" => "__builtin_ia32_pmovsxwd256", +"llvm.x86.avx2.pmovsxwq" => "__builtin_ia32_pmovsxwq256", +"llvm.x86.avx2.pmovzxbd" => "__builtin_ia32_pmovzxbd256", +"llvm.x86.avx2.pmovzxbq" => "__builtin_ia32_pmovzxbq256", +"llvm.x86.avx2.pmovzxbw" => "__builtin_ia32_pmovzxbw256", +"llvm.x86.avx2.pmovzxdq" => "__builtin_ia32_pmovzxdq256", +"llvm.x86.avx2.pmovzxwd" => "__builtin_ia32_pmovzxwd256", +"llvm.x86.avx2.pmovzxwq" => "__builtin_ia32_pmovzxwq256", +"llvm.x86.avx2.pmul.dq" => "__builtin_ia32_pmuldq256", +"llvm.x86.avx2.pmul.hr.sw" => "__builtin_ia32_pmulhrsw256", +"llvm.x86.avx2.pmulh.w" => "__builtin_ia32_pmulhw256", +"llvm.x86.avx2.pmulhu.w" => "__builtin_ia32_pmulhuw256", +"llvm.x86.avx2.pmulu.dq" => "__builtin_ia32_pmuludq256", +"llvm.x86.avx2.psad.bw" => "__builtin_ia32_psadbw256", +"llvm.x86.avx2.pshuf.b" => "__builtin_ia32_pshufb256", +"llvm.x86.avx2.psign.b" => "__builtin_ia32_psignb256", +"llvm.x86.avx2.psign.d" => "__builtin_ia32_psignd256", +"llvm.x86.avx2.psign.w" => "__builtin_ia32_psignw256", +"llvm.x86.avx2.psll.d" => "__builtin_ia32_pslld256", +"llvm.x86.avx2.psll.dq" => "__builtin_ia32_pslldqi256", +"llvm.x86.avx2.psll.dq.bs" => "__builtin_ia32_pslldqi256_byteshift", +"llvm.x86.avx2.psll.q" => "__builtin_ia32_psllq256", +"llvm.x86.avx2.psll.w" => "__builtin_ia32_psllw256", +"llvm.x86.avx2.pslli.d" => "__builtin_ia32_pslldi256", +"llvm.x86.avx2.pslli.q" => "__builtin_ia32_psllqi256", +"llvm.x86.avx2.pslli.w" => "__builtin_ia32_psllwi256", +"llvm.x86.avx2.psllv.d" => "__builtin_ia32_psllv4si", +"llvm.x86.avx2.psllv.d.256" => "__builtin_ia32_psllv8si", +"llvm.x86.avx2.psllv.q" => "__builtin_ia32_psllv2di", +"llvm.x86.avx2.psllv.q.256" => "__builtin_ia32_psllv4di", +"llvm.x86.avx2.psra.d" => "__builtin_ia32_psrad256", +"llvm.x86.avx2.psra.w" => "__builtin_ia32_psraw256", +"llvm.x86.avx2.psrai.d" => "__builtin_ia32_psradi256", +"llvm.x86.avx2.psrai.w" => "__builtin_ia32_psrawi256", +"llvm.x86.avx2.psrav.d" => "__builtin_ia32_psrav4si", +"llvm.x86.avx2.psrav.d.256" => "__builtin_ia32_psrav8si", +"llvm.x86.avx2.psrl.d" => "__builtin_ia32_psrld256", +"llvm.x86.avx2.psrl.dq" => "__builtin_ia32_psrldqi256", +"llvm.x86.avx2.psrl.dq.bs" => "__builtin_ia32_psrldqi256_byteshift", +"llvm.x86.avx2.psrl.q" => "__builtin_ia32_psrlq256", +"llvm.x86.avx2.psrl.w" => "__builtin_ia32_psrlw256", +"llvm.x86.avx2.psrli.d" => "__builtin_ia32_psrldi256", +"llvm.x86.avx2.psrli.q" => "__builtin_ia32_psrlqi256", +"llvm.x86.avx2.psrli.w" => "__builtin_ia32_psrlwi256", +"llvm.x86.avx2.psrlv.d" => "__builtin_ia32_psrlv4si", +"llvm.x86.avx2.psrlv.d.256" => "__builtin_ia32_psrlv8si", +"llvm.x86.avx2.psrlv.q" => "__builtin_ia32_psrlv2di", +"llvm.x86.avx2.psrlv.q.256" => "__builtin_ia32_psrlv4di", +"llvm.x86.avx2.psubs.b" => "__builtin_ia32_psubsb256", +"llvm.x86.avx2.psubs.w" => "__builtin_ia32_psubsw256", +"llvm.x86.avx2.psubus.b" => "__builtin_ia32_psubusb256", +"llvm.x86.avx2.psubus.w" => "__builtin_ia32_psubusw256", +"llvm.x86.avx2.vbroadcast.sd.pd.256" => "__builtin_ia32_vbroadcastsd_pd256", +"llvm.x86.avx2.vbroadcast.ss.ps" => "__builtin_ia32_vbroadcastss_ps", +"llvm.x86.avx2.vbroadcast.ss.ps.256" => "__builtin_ia32_vbroadcastss_ps256", +"llvm.x86.avx2.vextracti128" => "__builtin_ia32_extract128i256", +"llvm.x86.avx2.vinserti128" => "__builtin_ia32_insert128i256", +"llvm.x86.avx2.vperm2i128" => "__builtin_ia32_permti256", +"llvm.x86.avx512.cvtsd2usi" => "__builtin_ia32_cvtsd2usi", +"llvm.x86.avx512.cvtsd2usi64" => "__builtin_ia32_cvtsd2usi64", +"llvm.x86.avx512.cvtss2usi" => "__builtin_ia32_cvtss2usi", +"llvm.x86.avx512.cvtss2usi64" => "__builtin_ia32_cvtss2usi64", +"llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_cvttsd2usi", +"llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_cvttsd2usi64", +"llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_cvttss2usi", +"llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_cvttss2usi64", +"llvm.x86.avx512.cvtusi2sd" => "__builtin_ia32_cvtusi2sd", +"llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss", +"llvm.x86.avx512.cvtusi642sd" => "__builtin_ia32_cvtusi642sd", +"llvm.x86.avx512.cvtusi642ss" => "__builtin_ia32_cvtusi642ss", +"llvm.x86.avx512.gather.dpd.512" => "__builtin_ia32_gathersiv8df", +"llvm.x86.avx512.gather.dpi.512" => "__builtin_ia32_gathersiv16si", +"llvm.x86.avx512.gather.dpq.512" => "__builtin_ia32_gathersiv8di", +"llvm.x86.avx512.gather.dps.512" => "__builtin_ia32_gathersiv16sf", +"llvm.x86.avx512.gather.qpd.512" => "__builtin_ia32_gatherdiv8df", +"llvm.x86.avx512.gather.qpi.512" => "__builtin_ia32_gatherdiv16si", +"llvm.x86.avx512.gather.qpq.512" => "__builtin_ia32_gatherdiv8di", +"llvm.x86.avx512.gather.qps.512" => "__builtin_ia32_gatherdiv16sf", +"llvm.x86.avx512.gatherpf.dpd.512" => "__builtin_ia32_gatherpfdpd", +"llvm.x86.avx512.gatherpf.dps.512" => "__builtin_ia32_gatherpfdps", +"llvm.x86.avx512.gatherpf.qpd.512" => "__builtin_ia32_gatherpfqpd", +"llvm.x86.avx512.gatherpf.qps.512" => "__builtin_ia32_gatherpfqps", +"llvm.x86.avx512.kand.w" => "__builtin_ia32_kandhi", +"llvm.x86.avx512.kandn.w" => "__builtin_ia32_kandnhi", +"llvm.x86.avx512.knot.w" => "__builtin_ia32_knothi", +"llvm.x86.avx512.kor.w" => "__builtin_ia32_korhi", +"llvm.x86.avx512.kortestc.w" => "__builtin_ia32_kortestchi", +"llvm.x86.avx512.kortestz.w" => "__builtin_ia32_kortestzhi", +"llvm.x86.avx512.kunpck.bw" => "__builtin_ia32_kunpckhi", +"llvm.x86.avx512.kxnor.w" => "__builtin_ia32_kxnorhi", +"llvm.x86.avx512.kxor.w" => "__builtin_ia32_kxorhi", +"llvm.x86.avx512.mask.blend.d.512" => "__builtin_ia32_blendmd_512_mask", +"llvm.x86.avx512.mask.blend.pd.512" => "__builtin_ia32_blendmpd_512_mask", +"llvm.x86.avx512.mask.blend.ps.512" => "__builtin_ia32_blendmps_512_mask", +"llvm.x86.avx512.mask.blend.q.512" => "__builtin_ia32_blendmq_512_mask", +"llvm.x86.avx512.mask.cmp.pd.512" => "__builtin_ia32_cmppd512_mask", +"llvm.x86.avx512.mask.cmp.ps.512" => "__builtin_ia32_cmpps512_mask", +"llvm.x86.avx512.mask.conflict.d.512" => "__builtin_ia32_vpconflictsi_512_mask", +"llvm.x86.avx512.mask.conflict.q.512" => "__builtin_ia32_vpconflictdi_512_mask", +"llvm.x86.avx512.mask.cvtdq2pd.512" => "__builtin_ia32_cvtdq2pd512_mask", +"llvm.x86.avx512.mask.cvtdq2ps.512" => "__builtin_ia32_cvtdq2ps512_mask", +"llvm.x86.avx512.mask.cvtpd2dq.512" => "__builtin_ia32_cvtpd2dq512_mask", +"llvm.x86.avx512.mask.cvtpd2ps.512" => "__builtin_ia32_cvtpd2ps512_mask", +"llvm.x86.avx512.mask.cvtpd2udq.512" => "__builtin_ia32_cvtpd2udq512_mask", +"llvm.x86.avx512.mask.cvtps2dq.512" => "__builtin_ia32_cvtps2dq512_mask", +"llvm.x86.avx512.mask.cvtps2udq.512" => "__builtin_ia32_cvtps2udq512_mask", +"llvm.x86.avx512.mask.cvttpd2dq.512" => "__builtin_ia32_cvttpd2dq512_mask", +"llvm.x86.avx512.mask.cvttpd2udq.512" => "__builtin_ia32_cvttpd2udq512_mask", +"llvm.x86.avx512.mask.cvttps2dq.512" => "__builtin_ia32_cvttps2dq512_mask", +"llvm.x86.avx512.mask.cvttps2udq.512" => "__builtin_ia32_cvttps2udq512_mask", +"llvm.x86.avx512.mask.cvtudq2pd.512" => "__builtin_ia32_cvtudq2pd512_mask", +"llvm.x86.avx512.mask.cvtudq2ps.512" => "__builtin_ia32_cvtudq2ps512_mask", +"llvm.x86.avx512.mask.loadu.d.512" => "__builtin_ia32_loaddqusi512_mask", +"llvm.x86.avx512.mask.loadu.pd.512" => "__builtin_ia32_loadupd512_mask", +"llvm.x86.avx512.mask.loadu.ps.512" => "__builtin_ia32_loadups512_mask", +"llvm.x86.avx512.mask.loadu.q.512" => "__builtin_ia32_loaddqudi512_mask", +"llvm.x86.avx512.mask.lzcnt.d.512" => "__builtin_ia32_vplzcntd_512_mask", +"llvm.x86.avx512.mask.lzcnt.q.512" => "__builtin_ia32_vplzcntq_512_mask", +"llvm.x86.avx512.mask.max.pd.512" => "__builtin_ia32_maxpd512_mask", +"llvm.x86.avx512.mask.max.ps.512" => "__builtin_ia32_maxps512_mask", +"llvm.x86.avx512.mask.min.pd.512" => "__builtin_ia32_minpd512_mask", +"llvm.x86.avx512.mask.min.ps.512" => "__builtin_ia32_minps512_mask", +"llvm.x86.avx512.mask.pabs.d.512" => "__builtin_ia32_pabsd512_mask", +"llvm.x86.avx512.mask.pabs.q.512" => "__builtin_ia32_pabsq512_mask", +"llvm.x86.avx512.mask.pand.d.512" => "__builtin_ia32_pandd512_mask", +"llvm.x86.avx512.mask.pand.q.512" => "__builtin_ia32_pandq512_mask", +"llvm.x86.avx512.mask.pbroadcast.d.gpr.512" => "__builtin_ia32_pbroadcastd512_gpr_mask", +"llvm.x86.avx512.mask.pbroadcast.q.gpr.512" => "__builtin_ia32_pbroadcastq512_gpr_mask", +"llvm.x86.avx512.mask.pbroadcast.q.mem.512" => "__builtin_ia32_pbroadcastq512_mem_mask", +"llvm.x86.avx512.mask.pcmpeq.b.128" => "__builtin_ia32_pcmpeqb128_mask", +"llvm.x86.avx512.mask.pcmpeq.b.256" => "__builtin_ia32_pcmpeqb256_mask", +"llvm.x86.avx512.mask.pcmpeq.b.512" => "__builtin_ia32_pcmpeqb512_mask", +"llvm.x86.avx512.mask.pcmpeq.d.128" => "__builtin_ia32_pcmpeqd128_mask", +"llvm.x86.avx512.mask.pcmpeq.d.256" => "__builtin_ia32_pcmpeqd256_mask", +"llvm.x86.avx512.mask.pcmpeq.d.512" => "__builtin_ia32_pcmpeqd512_mask", +"llvm.x86.avx512.mask.pcmpeq.q.128" => "__builtin_ia32_pcmpeqq128_mask", +"llvm.x86.avx512.mask.pcmpeq.q.256" => "__builtin_ia32_pcmpeqq256_mask", +"llvm.x86.avx512.mask.pcmpeq.q.512" => "__builtin_ia32_pcmpeqq512_mask", +"llvm.x86.avx512.mask.pcmpeq.w.128" => "__builtin_ia32_pcmpeqw128_mask", +"llvm.x86.avx512.mask.pcmpeq.w.256" => "__builtin_ia32_pcmpeqw256_mask", +"llvm.x86.avx512.mask.pcmpeq.w.512" => "__builtin_ia32_pcmpeqw512_mask", +"llvm.x86.avx512.mask.pcmpgt.b.128" => "__builtin_ia32_pcmpgtb128_mask", +"llvm.x86.avx512.mask.pcmpgt.b.256" => "__builtin_ia32_pcmpgtb256_mask", +"llvm.x86.avx512.mask.pcmpgt.b.512" => "__builtin_ia32_pcmpgtb512_mask", +"llvm.x86.avx512.mask.pcmpgt.d.128" => "__builtin_ia32_pcmpgtd128_mask", +"llvm.x86.avx512.mask.pcmpgt.d.256" => "__builtin_ia32_pcmpgtd256_mask", +"llvm.x86.avx512.mask.pcmpgt.d.512" => "__builtin_ia32_pcmpgtd512_mask", +"llvm.x86.avx512.mask.pcmpgt.q.128" => "__builtin_ia32_pcmpgtq128_mask", +"llvm.x86.avx512.mask.pcmpgt.q.256" => "__builtin_ia32_pcmpgtq256_mask", +"llvm.x86.avx512.mask.pcmpgt.q.512" => "__builtin_ia32_pcmpgtq512_mask", +"llvm.x86.avx512.mask.pcmpgt.w.128" => "__builtin_ia32_pcmpgtw128_mask", +"llvm.x86.avx512.mask.pcmpgt.w.256" => "__builtin_ia32_pcmpgtw256_mask", +"llvm.x86.avx512.mask.pcmpgt.w.512" => "__builtin_ia32_pcmpgtw512_mask", +"llvm.x86.avx512.mask.pmaxs.d.512" => "__builtin_ia32_pmaxsd512_mask", +"llvm.x86.avx512.mask.pmaxs.q.512" => "__builtin_ia32_pmaxsq512_mask", +"llvm.x86.avx512.mask.pmaxu.d.512" => "__builtin_ia32_pmaxud512_mask", +"llvm.x86.avx512.mask.pmaxu.q.512" => "__builtin_ia32_pmaxuq512_mask", +"llvm.x86.avx512.mask.pmins.d.512" => "__builtin_ia32_pminsd512_mask", +"llvm.x86.avx512.mask.pmins.q.512" => "__builtin_ia32_pminsq512_mask", +"llvm.x86.avx512.mask.pminu.d.512" => "__builtin_ia32_pminud512_mask", +"llvm.x86.avx512.mask.pminu.q.512" => "__builtin_ia32_pminuq512_mask", +"llvm.x86.avx512.mask.pmul.dq.512" => "__builtin_ia32_pmuldq512_mask", +"llvm.x86.avx512.mask.pmulu.dq.512" => "__builtin_ia32_pmuludq512_mask", +"llvm.x86.avx512.mask.ptestm.d.512" => "__builtin_ia32_ptestmd512", +"llvm.x86.avx512.mask.ptestm.q.512" => "__builtin_ia32_ptestmq512", +"llvm.x86.avx512.mask.rndscale.pd.512" => "__builtin_ia32_rndscalepd_mask", +"llvm.x86.avx512.mask.rndscale.ps.512" => "__builtin_ia32_rndscaleps_mask", +"llvm.x86.avx512.mask.store.ss" => "__builtin_ia32_storess_mask", +"llvm.x86.avx512.mask.storeu.d.512" => "__builtin_ia32_storedqusi512_mask", +"llvm.x86.avx512.mask.storeu.pd.512" => "__builtin_ia32_storeupd512_mask", +"llvm.x86.avx512.mask.storeu.ps.512" => "__builtin_ia32_storeups512_mask", +"llvm.x86.avx512.mask.storeu.q.512" => "__builtin_ia32_storedqudi512_mask", +"llvm.x86.avx512.mask.valign.d.512" => "__builtin_ia32_alignd512_mask", +"llvm.x86.avx512.mask.valign.q.512" => "__builtin_ia32_alignq512_mask", +"llvm.x86.avx512.mask.vcvtph2ps.512" => "__builtin_ia32_vcvtph2ps512_mask", +"llvm.x86.avx512.mask.vcvtps2ph.512" => "__builtin_ia32_vcvtps2ph512_mask", +"llvm.x86.avx512.mask.vpermt.d.512" => "__builtin_ia32_vpermt2vard512_mask", +"llvm.x86.avx512.mask.vpermt.pd.512" => "__builtin_ia32_vpermt2varpd512_mask", +"llvm.x86.avx512.mask.vpermt.ps.512" => "__builtin_ia32_vpermt2varps512_mask", +"llvm.x86.avx512.mask.vpermt.q.512" => "__builtin_ia32_vpermt2varq512_mask", +"llvm.x86.avx512.movntdqa" => "__builtin_ia32_movntdqa512", +"llvm.x86.avx512.pbroadcastd.512" => "__builtin_ia32_pbroadcastd512", +"llvm.x86.avx512.pbroadcastq.512" => "__builtin_ia32_pbroadcastq512", +"llvm.x86.avx512.pmovzxbd" => "__builtin_ia32_pmovzxbd512", +"llvm.x86.avx512.pmovzxbq" => "__builtin_ia32_pmovzxbq512", +"llvm.x86.avx512.pmovzxdq" => "__builtin_ia32_pmovzxdq512", +"llvm.x86.avx512.pmovzxwd" => "__builtin_ia32_pmovzxwd512", +"llvm.x86.avx512.pmovzxwq" => "__builtin_ia32_pmovzxwq512", +"llvm.x86.avx512.psll.dq" => "__builtin_ia32_pslldqi512", +"llvm.x86.avx512.psll.dq.bs" => "__builtin_ia32_pslldqi512_byteshift", +"llvm.x86.avx512.psrl.dq" => "__builtin_ia32_psrldqi512", +"llvm.x86.avx512.psrl.dq.bs" => "__builtin_ia32_psrldqi512_byteshift", +"llvm.x86.avx512.rcp14.pd.512" => "__builtin_ia32_rcp14pd512_mask", +"llvm.x86.avx512.rcp14.ps.512" => "__builtin_ia32_rcp14ps512_mask", +"llvm.x86.avx512.rcp14.sd" => "__builtin_ia32_rcp14sd_mask", +"llvm.x86.avx512.rcp14.ss" => "__builtin_ia32_rcp14ss_mask", +"llvm.x86.avx512.rcp28.pd" => "__builtin_ia32_rcp28pd_mask", +"llvm.x86.avx512.rcp28.ps" => "__builtin_ia32_rcp28ps_mask", +"llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_mask", +"llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_mask", +"llvm.x86.avx512.rndscale.sd" => "__builtin_ia32_rndscalesd", +"llvm.x86.avx512.rndscale.ss" => "__builtin_ia32_rndscaless", +"llvm.x86.avx512.rsqrt14.pd.512" => "__builtin_ia32_rsqrt14pd512_mask", +"llvm.x86.avx512.rsqrt14.ps.512" => "__builtin_ia32_rsqrt14ps512_mask", +"llvm.x86.avx512.rsqrt14.sd" => "__builtin_ia32_rsqrt14sd_mask", +"llvm.x86.avx512.rsqrt14.ss" => "__builtin_ia32_rsqrt14ss_mask", +"llvm.x86.avx512.rsqrt28.pd" => "__builtin_ia32_rsqrt28pd_mask", +"llvm.x86.avx512.rsqrt28.ps" => "__builtin_ia32_rsqrt28ps_mask", +"llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_mask", +"llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_mask", +"llvm.x86.avx512.scatter.dpd.512" => "__builtin_ia32_scattersiv8df", +"llvm.x86.avx512.scatter.dpi.512" => "__builtin_ia32_scattersiv16si", +"llvm.x86.avx512.scatter.dpq.512" => "__builtin_ia32_scattersiv8di", +"llvm.x86.avx512.scatter.dps.512" => "__builtin_ia32_scattersiv16sf", +"llvm.x86.avx512.scatter.qpd.512" => "__builtin_ia32_scatterdiv8df", +"llvm.x86.avx512.scatter.qpi.512" => "__builtin_ia32_scatterdiv16si", +"llvm.x86.avx512.scatter.qpq.512" => "__builtin_ia32_scatterdiv8di", +"llvm.x86.avx512.scatter.qps.512" => "__builtin_ia32_scatterdiv16sf", +"llvm.x86.avx512.scatterpf.dpd.512" => "__builtin_ia32_scatterpfdpd", +"llvm.x86.avx512.scatterpf.dps.512" => "__builtin_ia32_scatterpfdps", +"llvm.x86.avx512.scatterpf.qpd.512" => "__builtin_ia32_scatterpfqpd", +"llvm.x86.avx512.scatterpf.qps.512" => "__builtin_ia32_scatterpfqps", +"llvm.x86.avx512.sqrt.pd.512" => "__builtin_ia32_sqrtpd512_mask", +"llvm.x86.avx512.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask", +"llvm.x86.avx512.sqrt.sd" => "__builtin_ia32_sqrtrndsd", +"llvm.x86.avx512.sqrt.ss" => "__builtin_ia32_sqrtrndss", +"llvm.x86.avx512.vbroadcast.sd.512" => "__builtin_ia32_vbroadcastsd512", +"llvm.x86.avx512.vbroadcast.sd.pd.512" => "__builtin_ia32_vbroadcastsd_pd512", +"llvm.x86.avx512.vbroadcast.ss.512" => "__builtin_ia32_vbroadcastss512", +"llvm.x86.avx512.vbroadcast.ss.ps.512" => "__builtin_ia32_vbroadcastss_ps512", +"llvm.x86.bmi.bextr.32" => "__builtin_ia32_bextr_u32", +"llvm.x86.bmi.bextr.64" => "__builtin_ia32_bextr_u64", +"llvm.x86.bmi.bzhi.32" => "__builtin_ia32_bzhi_si", +"llvm.x86.bmi.bzhi.64" => "__builtin_ia32_bzhi_di", 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"__builtin_ia32_sha256rnds2", +"llvm.x86.sse.add.ss" => "__builtin_ia32_addss", +"llvm.x86.sse.cmp.ps" => "__builtin_ia32_cmpps", +"llvm.x86.sse.cmp.ss" => "__builtin_ia32_cmpss", +"llvm.x86.sse.comieq.ss" => "__builtin_ia32_comieq", +"llvm.x86.sse.comige.ss" => "__builtin_ia32_comige", +"llvm.x86.sse.comigt.ss" => "__builtin_ia32_comigt", +"llvm.x86.sse.comile.ss" => "__builtin_ia32_comile", +"llvm.x86.sse.comilt.ss" => "__builtin_ia32_comilt", +"llvm.x86.sse.comineq.ss" => "__builtin_ia32_comineq", +"llvm.x86.sse.cvtsi2ss" => "__builtin_ia32_cvtsi2ss", +"llvm.x86.sse.cvtsi642ss" => "__builtin_ia32_cvtsi642ss", +"llvm.x86.sse.cvtss2si" => "__builtin_ia32_cvtss2si", +"llvm.x86.sse.cvtss2si64" => "__builtin_ia32_cvtss2si64", +"llvm.x86.sse.cvttss2si" => "__builtin_ia32_cvttss2si", +"llvm.x86.sse.cvttss2si64" => "__builtin_ia32_cvttss2si64", +"llvm.x86.sse.div.ss" => "__builtin_ia32_divss", +"llvm.x86.sse.max.ps" => "__builtin_ia32_maxps", +"llvm.x86.sse.max.ss" => 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"__builtin_ia32_pmulhw128", +"llvm.x86.sse2.pmulhu.w" => "__builtin_ia32_pmulhuw128", +"llvm.x86.sse2.pmulu.dq" => "__builtin_ia32_pmuludq128", +"llvm.x86.sse2.psad.bw" => "__builtin_ia32_psadbw128", +"llvm.x86.sse2.pshuf.d" => "__builtin_ia32_pshufd", +"llvm.x86.sse2.pshufh.w" => "__builtin_ia32_pshufhw", +"llvm.x86.sse2.pshufl.w" => "__builtin_ia32_pshuflw", +"llvm.x86.sse2.psll.d" => "__builtin_ia32_pslld128", +"llvm.x86.sse2.psll.dq" => "__builtin_ia32_pslldqi128", +"llvm.x86.sse2.psll.dq.bs" => "__builtin_ia32_pslldqi128_byteshift", +"llvm.x86.sse2.psll.q" => "__builtin_ia32_psllq128", +"llvm.x86.sse2.psll.w" => "__builtin_ia32_psllw128", +"llvm.x86.sse2.pslli.d" => "__builtin_ia32_pslldi128", +"llvm.x86.sse2.pslli.q" => "__builtin_ia32_psllqi128", +"llvm.x86.sse2.pslli.w" => "__builtin_ia32_psllwi128", +"llvm.x86.sse2.psra.d" => "__builtin_ia32_psrad128", +"llvm.x86.sse2.psra.w" => "__builtin_ia32_psraw128", +"llvm.x86.sse2.psrai.d" => "__builtin_ia32_psradi128", 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"__builtin_ia32_storeupd", +"llvm.x86.sse2.sub.sd" => "__builtin_ia32_subsd", +"llvm.x86.sse2.ucomieq.sd" => "__builtin_ia32_ucomisdeq", +"llvm.x86.sse2.ucomige.sd" => "__builtin_ia32_ucomisdge", +"llvm.x86.sse2.ucomigt.sd" => "__builtin_ia32_ucomisdgt", +"llvm.x86.sse2.ucomile.sd" => "__builtin_ia32_ucomisdle", +"llvm.x86.sse2.ucomilt.sd" => "__builtin_ia32_ucomisdlt", +"llvm.x86.sse2.ucomineq.sd" => "__builtin_ia32_ucomisdneq", +"llvm.x86.sse3.addsub.pd" => "__builtin_ia32_addsubpd", +"llvm.x86.sse3.addsub.ps" => "__builtin_ia32_addsubps", +"llvm.x86.sse3.hadd.pd" => "__builtin_ia32_haddpd", +"llvm.x86.sse3.hadd.ps" => "__builtin_ia32_haddps", +"llvm.x86.sse3.hsub.pd" => "__builtin_ia32_hsubpd", +"llvm.x86.sse3.hsub.ps" => "__builtin_ia32_hsubps", +"llvm.x86.sse3.ldu.dq" => "__builtin_ia32_lddqu", +"llvm.x86.sse3.monitor" => "__builtin_ia32_monitor", +"llvm.x86.sse3.mwait" => "__builtin_ia32_mwait", +"llvm.x86.sse41.blendpd" => "__builtin_ia32_blendpd", +"llvm.x86.sse41.blendps" => "__builtin_ia32_blendps", +"llvm.x86.sse41.blendvpd" => "__builtin_ia32_blendvpd", +"llvm.x86.sse41.blendvps" => "__builtin_ia32_blendvps", +"llvm.x86.sse41.dppd" => "__builtin_ia32_dppd", +"llvm.x86.sse41.dpps" => "__builtin_ia32_dpps", +"llvm.x86.sse41.extractps" => "__builtin_ia32_extractps128", +"llvm.x86.sse41.insertps" => "__builtin_ia32_insertps128", +"llvm.x86.sse41.movntdqa" => "__builtin_ia32_movntdqa", +"llvm.x86.sse41.mpsadbw" => "__builtin_ia32_mpsadbw128", +"llvm.x86.sse41.packusdw" => "__builtin_ia32_packusdw128", +"llvm.x86.sse41.pblendvb" => "__builtin_ia32_pblendvb128", +"llvm.x86.sse41.pblendw" => "__builtin_ia32_pblendw128", +"llvm.x86.sse41.phminposuw" => "__builtin_ia32_phminposuw128", +"llvm.x86.sse41.pmaxsb" => "__builtin_ia32_pmaxsb128", +"llvm.x86.sse41.pmaxsd" => "__builtin_ia32_pmaxsd128", +"llvm.x86.sse41.pmaxud" => "__builtin_ia32_pmaxud128", +"llvm.x86.sse41.pmaxuw" => "__builtin_ia32_pmaxuw128", +"llvm.x86.sse41.pminsb" => "__builtin_ia32_pminsb128", +"llvm.x86.sse41.pminsd" => "__builtin_ia32_pminsd128", +"llvm.x86.sse41.pminud" => "__builtin_ia32_pminud128", +"llvm.x86.sse41.pminuw" => "__builtin_ia32_pminuw128", +"llvm.x86.sse41.pmovsxbd" => "__builtin_ia32_pmovsxbd128", +"llvm.x86.sse41.pmovsxbq" => "__builtin_ia32_pmovsxbq128", +"llvm.x86.sse41.pmovsxbw" => "__builtin_ia32_pmovsxbw128", +"llvm.x86.sse41.pmovsxdq" => "__builtin_ia32_pmovsxdq128", +"llvm.x86.sse41.pmovsxwd" => "__builtin_ia32_pmovsxwd128", +"llvm.x86.sse41.pmovsxwq" => "__builtin_ia32_pmovsxwq128", +"llvm.x86.sse41.pmovzxbd" => "__builtin_ia32_pmovzxbd128", +"llvm.x86.sse41.pmovzxbq" => "__builtin_ia32_pmovzxbq128", +"llvm.x86.sse41.pmovzxbw" => "__builtin_ia32_pmovzxbw128", +"llvm.x86.sse41.pmovzxdq" => "__builtin_ia32_pmovzxdq128", +"llvm.x86.sse41.pmovzxwd" => "__builtin_ia32_pmovzxwd128", +"llvm.x86.sse41.pmovzxwq" => "__builtin_ia32_pmovzxwq128", +"llvm.x86.sse41.pmuldq" => "__builtin_ia32_pmuldq128", +"llvm.x86.sse41.ptestc" => "__builtin_ia32_ptestc128", +"llvm.x86.sse41.ptestnzc" => "__builtin_ia32_ptestnzc128", +"llvm.x86.sse41.ptestz" => "__builtin_ia32_ptestz128", +"llvm.x86.sse41.round.pd" => "__builtin_ia32_roundpd", +"llvm.x86.sse41.round.ps" => "__builtin_ia32_roundps", +"llvm.x86.sse41.round.sd" => "__builtin_ia32_roundsd", +"llvm.x86.sse41.round.ss" => "__builtin_ia32_roundss", +"llvm.x86.sse42.crc32.32.16" => "__builtin_ia32_crc32hi", +"llvm.x86.sse42.crc32.32.32" => "__builtin_ia32_crc32si", +"llvm.x86.sse42.crc32.32.8" => "__builtin_ia32_crc32qi", +"llvm.x86.sse42.crc32.64.64" => "__builtin_ia32_crc32di", +"llvm.x86.sse42.pcmpestri128" => "__builtin_ia32_pcmpestri128", +"llvm.x86.sse42.pcmpestria128" => "__builtin_ia32_pcmpestria128", +"llvm.x86.sse42.pcmpestric128" => "__builtin_ia32_pcmpestric128", +"llvm.x86.sse42.pcmpestrio128" => "__builtin_ia32_pcmpestrio128", +"llvm.x86.sse42.pcmpestris128" => "__builtin_ia32_pcmpestris128", +"llvm.x86.sse42.pcmpestriz128" => "__builtin_ia32_pcmpestriz128", +"llvm.x86.sse42.pcmpestrm128" => "__builtin_ia32_pcmpestrm128", +"llvm.x86.sse42.pcmpistri128" => "__builtin_ia32_pcmpistri128", +"llvm.x86.sse42.pcmpistria128" => "__builtin_ia32_pcmpistria128", +"llvm.x86.sse42.pcmpistric128" => "__builtin_ia32_pcmpistric128", +"llvm.x86.sse42.pcmpistrio128" => "__builtin_ia32_pcmpistrio128", +"llvm.x86.sse42.pcmpistris128" => "__builtin_ia32_pcmpistris128", +"llvm.x86.sse42.pcmpistriz128" => "__builtin_ia32_pcmpistriz128", +"llvm.x86.sse42.pcmpistrm128" => "__builtin_ia32_pcmpistrm128", +"llvm.x86.sse4a.extrq" => "__builtin_ia32_extrq", +"llvm.x86.sse4a.extrqi" => "__builtin_ia32_extrqi", +"llvm.x86.sse4a.insertq" => "__builtin_ia32_insertq", +"llvm.x86.sse4a.insertqi" => "__builtin_ia32_insertqi", +"llvm.x86.sse4a.movnt.sd" => "__builtin_ia32_movntsd", +"llvm.x86.sse4a.movnt.ss" => "__builtin_ia32_movntss", +"llvm.x86.ssse3.pabs.b.128" => "__builtin_ia32_pabsb128", +"llvm.x86.ssse3.pabs.d.128" => "__builtin_ia32_pabsd128", +"llvm.x86.ssse3.pabs.w.128" => "__builtin_ia32_pabsw128", +"llvm.x86.ssse3.phadd.d.128" => "__builtin_ia32_phaddd128", +"llvm.x86.ssse3.phadd.sw.128" => "__builtin_ia32_phaddsw128", +"llvm.x86.ssse3.phadd.w.128" => "__builtin_ia32_phaddw128", +"llvm.x86.ssse3.phsub.d.128" => "__builtin_ia32_phsubd128", +"llvm.x86.ssse3.phsub.sw.128" => "__builtin_ia32_phsubsw128", +"llvm.x86.ssse3.phsub.w.128" => "__builtin_ia32_phsubw128", +"llvm.x86.ssse3.pmadd.ub.sw.128" => "__builtin_ia32_pmaddubsw128", +"llvm.x86.ssse3.pmul.hr.sw.128" => "__builtin_ia32_pmulhrsw128", +"llvm.x86.ssse3.pshuf.b.128" => "__builtin_ia32_pshufb128", +"llvm.x86.ssse3.psign.b.128" => "__builtin_ia32_psignb128", +"llvm.x86.ssse3.psign.d.128" => "__builtin_ia32_psignd128", +"llvm.x86.ssse3.psign.w.128" => "__builtin_ia32_psignw128", +"llvm.x86.subborrow.u32" => "__builtin_ia32_subborrow_u32", +"llvm.x86.subborrow.u64" => "__builtin_ia32_subborrow_u64", +"llvm.x86.tbm.bextri.u32" => "__builtin_ia32_bextri_u32", +"llvm.x86.tbm.bextri.u64" => "__builtin_ia32_bextri_u64", +"llvm.x86.vcvtph2ps.128" => "__builtin_ia32_vcvtph2ps", +"llvm.x86.vcvtph2ps.256" => "__builtin_ia32_vcvtph2ps256", +"llvm.x86.vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph", +"llvm.x86.vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256", +"llvm.x86.wrfsbase.32" => "__builtin_ia32_wrfsbase32", +"llvm.x86.wrfsbase.64" => "__builtin_ia32_wrfsbase64", +"llvm.x86.wrgsbase.32" => "__builtin_ia32_wrgsbase32", +"llvm.x86.wrgsbase.64" => "__builtin_ia32_wrgsbase64", +"llvm.x86.xabort" => "__builtin_ia32_xabort", +"llvm.x86.xbegin" => "__builtin_ia32_xbegin", +"llvm.x86.xend" => "__builtin_ia32_xend", +"llvm.x86.xop.vfrcz.pd" => "__builtin_ia32_vfrczpd", +"llvm.x86.xop.vfrcz.pd.256" => "__builtin_ia32_vfrczpd256", +"llvm.x86.xop.vfrcz.ps" => "__builtin_ia32_vfrczps", +"llvm.x86.xop.vfrcz.ps.256" => "__builtin_ia32_vfrczps256", +"llvm.x86.xop.vfrcz.sd" => "__builtin_ia32_vfrczsd", +"llvm.x86.xop.vfrcz.ss" => "__builtin_ia32_vfrczss", +"llvm.x86.xop.vpcmov" => "__builtin_ia32_vpcmov", +"llvm.x86.xop.vpcmov.256" => "__builtin_ia32_vpcmov_256", +"llvm.x86.xop.vpcomb" => "__builtin_ia32_vpcomb", +"llvm.x86.xop.vpcomd" => "__builtin_ia32_vpcomd", +"llvm.x86.xop.vpcomq" => "__builtin_ia32_vpcomq", +"llvm.x86.xop.vpcomub" => "__builtin_ia32_vpcomub", +"llvm.x86.xop.vpcomud" => "__builtin_ia32_vpcomud", +"llvm.x86.xop.vpcomuq" => "__builtin_ia32_vpcomuq", +"llvm.x86.xop.vpcomuw" => "__builtin_ia32_vpcomuw", +"llvm.x86.xop.vpcomw" => "__builtin_ia32_vpcomw", +"llvm.x86.xop.vpermil2pd" => "__builtin_ia32_vpermil2pd", +"llvm.x86.xop.vpermil2pd.256" => "__builtin_ia32_vpermil2pd256", +"llvm.x86.xop.vpermil2ps" => "__builtin_ia32_vpermil2ps", +"llvm.x86.xop.vpermil2ps.256" => "__builtin_ia32_vpermil2ps256", +"llvm.x86.xop.vphaddbd" => "__builtin_ia32_vphaddbd", +"llvm.x86.xop.vphaddbq" => "__builtin_ia32_vphaddbq", +"llvm.x86.xop.vphaddbw" => "__builtin_ia32_vphaddbw", +"llvm.x86.xop.vphadddq" => "__builtin_ia32_vphadddq", +"llvm.x86.xop.vphaddubd" => "__builtin_ia32_vphaddubd", +"llvm.x86.xop.vphaddubq" => "__builtin_ia32_vphaddubq", +"llvm.x86.xop.vphaddubw" => "__builtin_ia32_vphaddubw", +"llvm.x86.xop.vphaddudq" => "__builtin_ia32_vphaddudq", +"llvm.x86.xop.vphadduwd" => "__builtin_ia32_vphadduwd", +"llvm.x86.xop.vphadduwq" => "__builtin_ia32_vphadduwq", +"llvm.x86.xop.vphaddwd" => "__builtin_ia32_vphaddwd", +"llvm.x86.xop.vphaddwq" => "__builtin_ia32_vphaddwq", +"llvm.x86.xop.vphsubbw" => "__builtin_ia32_vphsubbw", +"llvm.x86.xop.vphsubdq" => "__builtin_ia32_vphsubdq", +"llvm.x86.xop.vphsubwd" => "__builtin_ia32_vphsubwd", +"llvm.x86.xop.vpmacsdd" => "__builtin_ia32_vpmacsdd", +"llvm.x86.xop.vpmacsdqh" => "__builtin_ia32_vpmacsdqh", +"llvm.x86.xop.vpmacsdql" => "__builtin_ia32_vpmacsdql", +"llvm.x86.xop.vpmacssdd" => "__builtin_ia32_vpmacssdd", +"llvm.x86.xop.vpmacssdqh" => "__builtin_ia32_vpmacssdqh", +"llvm.x86.xop.vpmacssdql" => "__builtin_ia32_vpmacssdql", +"llvm.x86.xop.vpmacsswd" => "__builtin_ia32_vpmacsswd", +"llvm.x86.xop.vpmacssww" => "__builtin_ia32_vpmacssww", +"llvm.x86.xop.vpmacswd" => "__builtin_ia32_vpmacswd", +"llvm.x86.xop.vpmacsww" => "__builtin_ia32_vpmacsww", +"llvm.x86.xop.vpmadcsswd" => "__builtin_ia32_vpmadcsswd", +"llvm.x86.xop.vpmadcswd" => "__builtin_ia32_vpmadcswd", +"llvm.x86.xop.vpperm" => "__builtin_ia32_vpperm", +"llvm.x86.xop.vprotb" => "__builtin_ia32_vprotb", +"llvm.x86.xop.vprotbi" => "__builtin_ia32_vprotbi", +"llvm.x86.xop.vprotd" => "__builtin_ia32_vprotd", +"llvm.x86.xop.vprotdi" => "__builtin_ia32_vprotdi", +"llvm.x86.xop.vprotq" => "__builtin_ia32_vprotq", +"llvm.x86.xop.vprotqi" => "__builtin_ia32_vprotqi", +"llvm.x86.xop.vprotw" => "__builtin_ia32_vprotw", +"llvm.x86.xop.vprotwi" => "__builtin_ia32_vprotwi", +"llvm.x86.xop.vpshab" => "__builtin_ia32_vpshab", +"llvm.x86.xop.vpshad" => "__builtin_ia32_vpshad", +"llvm.x86.xop.vpshaq" => "__builtin_ia32_vpshaq", +"llvm.x86.xop.vpshaw" => "__builtin_ia32_vpshaw", +"llvm.x86.xop.vpshlb" => "__builtin_ia32_vpshlb", +"llvm.x86.xop.vpshld" => "__builtin_ia32_vpshld", +"llvm.x86.xop.vpshlq" => "__builtin_ia32_vpshlq", +"llvm.x86.xop.vpshlw" => "__builtin_ia32_vpshlw", +"llvm.x86.xtest" => "__builtin_ia32_xtest", +_ => unimplemented!("***** unsupported LLVM intrinsic {}", name), +} From 68ac3a4b3b144fbea093dcafb9ed696fa65b6b18 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Wed, 30 Mar 2022 18:40:22 +0200 Subject: [PATCH 056/356] Generate all listed architectures from llvmint --- src/intrinsic/archs.rs | 2965 ++++++++++++++++++++++++++++++++++++++++ src/intrinsic/llvm.rs | 2 +- src/intrinsic/x86.rs | 770 ----------- 3 files changed, 2966 insertions(+), 771 deletions(-) create mode 100644 src/intrinsic/archs.rs delete mode 100644 src/intrinsic/x86.rs diff --git a/src/intrinsic/archs.rs b/src/intrinsic/archs.rs new file mode 100644 index 000000000000..0376e0afef95 --- /dev/null +++ b/src/intrinsic/archs.rs @@ -0,0 +1,2965 @@ +match name { + // ppc + "llvm.ppc.altivec.dss" => "__builtin_altivec_dss", + "llvm.ppc.altivec.dssall" => "__builtin_altivec_dssall", + "llvm.ppc.altivec.dst" => "__builtin_altivec_dst", + "llvm.ppc.altivec.dstst" => "__builtin_altivec_dstst", + "llvm.ppc.altivec.dststt" => "__builtin_altivec_dststt", + "llvm.ppc.altivec.dstt" => "__builtin_altivec_dstt", + "llvm.ppc.altivec.mfvscr" => "__builtin_altivec_mfvscr", + "llvm.ppc.altivec.mtvscr" => "__builtin_altivec_mtvscr", + "llvm.ppc.altivec.vaddcuw" => "__builtin_altivec_vaddcuw", + "llvm.ppc.altivec.vaddsbs" => "__builtin_altivec_vaddsbs", + "llvm.ppc.altivec.vaddshs" => "__builtin_altivec_vaddshs", + "llvm.ppc.altivec.vaddsws" => "__builtin_altivec_vaddsws", + "llvm.ppc.altivec.vaddubs" => "__builtin_altivec_vaddubs", + "llvm.ppc.altivec.vadduhs" => "__builtin_altivec_vadduhs", + "llvm.ppc.altivec.vadduws" => "__builtin_altivec_vadduws", + "llvm.ppc.altivec.vavgsb" => "__builtin_altivec_vavgsb", + "llvm.ppc.altivec.vavgsh" => "__builtin_altivec_vavgsh", + "llvm.ppc.altivec.vavgsw" => "__builtin_altivec_vavgsw", + "llvm.ppc.altivec.vavgub" => "__builtin_altivec_vavgub", + "llvm.ppc.altivec.vavguh" => "__builtin_altivec_vavguh", + "llvm.ppc.altivec.vavguw" => "__builtin_altivec_vavguw", + "llvm.ppc.altivec.vcfsx" => "__builtin_altivec_vcfsx", + "llvm.ppc.altivec.vcfux" => "__builtin_altivec_vcfux", + "llvm.ppc.altivec.vcmpbfp" => "__builtin_altivec_vcmpbfp", + "llvm.ppc.altivec.vcmpbfp.p" => "__builtin_altivec_vcmpbfp_p", + "llvm.ppc.altivec.vcmpeqfp" => "__builtin_altivec_vcmpeqfp", + "llvm.ppc.altivec.vcmpeqfp.p" => "__builtin_altivec_vcmpeqfp_p", + "llvm.ppc.altivec.vcmpequb" => "__builtin_altivec_vcmpequb", + "llvm.ppc.altivec.vcmpequb.p" => "__builtin_altivec_vcmpequb_p", + "llvm.ppc.altivec.vcmpequh" => "__builtin_altivec_vcmpequh", + "llvm.ppc.altivec.vcmpequh.p" => "__builtin_altivec_vcmpequh_p", + "llvm.ppc.altivec.vcmpequw" => "__builtin_altivec_vcmpequw", + "llvm.ppc.altivec.vcmpequw.p" => "__builtin_altivec_vcmpequw_p", + "llvm.ppc.altivec.vcmpgefp" => "__builtin_altivec_vcmpgefp", + "llvm.ppc.altivec.vcmpgefp.p" => "__builtin_altivec_vcmpgefp_p", + "llvm.ppc.altivec.vcmpgtfp" => "__builtin_altivec_vcmpgtfp", + "llvm.ppc.altivec.vcmpgtfp.p" => "__builtin_altivec_vcmpgtfp_p", + "llvm.ppc.altivec.vcmpgtsb" => "__builtin_altivec_vcmpgtsb", + "llvm.ppc.altivec.vcmpgtsb.p" => "__builtin_altivec_vcmpgtsb_p", + "llvm.ppc.altivec.vcmpgtsh" => "__builtin_altivec_vcmpgtsh", + "llvm.ppc.altivec.vcmpgtsh.p" => "__builtin_altivec_vcmpgtsh_p", + "llvm.ppc.altivec.vcmpgtsw" => "__builtin_altivec_vcmpgtsw", + "llvm.ppc.altivec.vcmpgtsw.p" => "__builtin_altivec_vcmpgtsw_p", + "llvm.ppc.altivec.vcmpgtub" => "__builtin_altivec_vcmpgtub", + "llvm.ppc.altivec.vcmpgtub.p" => "__builtin_altivec_vcmpgtub_p", + "llvm.ppc.altivec.vcmpgtuh" => "__builtin_altivec_vcmpgtuh", + "llvm.ppc.altivec.vcmpgtuh.p" => "__builtin_altivec_vcmpgtuh_p", + "llvm.ppc.altivec.vcmpgtuw" => "__builtin_altivec_vcmpgtuw", + "llvm.ppc.altivec.vcmpgtuw.p" => "__builtin_altivec_vcmpgtuw_p", + "llvm.ppc.altivec.vctsxs" => "__builtin_altivec_vctsxs", + "llvm.ppc.altivec.vctuxs" => "__builtin_altivec_vctuxs", + "llvm.ppc.altivec.vexptefp" => "__builtin_altivec_vexptefp", + "llvm.ppc.altivec.vlogefp" => "__builtin_altivec_vlogefp", + "llvm.ppc.altivec.vmaddfp" => "__builtin_altivec_vmaddfp", + "llvm.ppc.altivec.vmaxfp" => "__builtin_altivec_vmaxfp", + "llvm.ppc.altivec.vmaxsb" => "__builtin_altivec_vmaxsb", + "llvm.ppc.altivec.vmaxsh" => "__builtin_altivec_vmaxsh", + "llvm.ppc.altivec.vmaxsw" => "__builtin_altivec_vmaxsw", + "llvm.ppc.altivec.vmaxub" => "__builtin_altivec_vmaxub", + "llvm.ppc.altivec.vmaxuh" => "__builtin_altivec_vmaxuh", + "llvm.ppc.altivec.vmaxuw" => "__builtin_altivec_vmaxuw", + "llvm.ppc.altivec.vmhaddshs" => "__builtin_altivec_vmhaddshs", + "llvm.ppc.altivec.vmhraddshs" => "__builtin_altivec_vmhraddshs", + "llvm.ppc.altivec.vminfp" => "__builtin_altivec_vminfp", + "llvm.ppc.altivec.vminsb" => "__builtin_altivec_vminsb", + "llvm.ppc.altivec.vminsh" => "__builtin_altivec_vminsh", + "llvm.ppc.altivec.vminsw" => "__builtin_altivec_vminsw", + "llvm.ppc.altivec.vminub" => "__builtin_altivec_vminub", + "llvm.ppc.altivec.vminuh" => "__builtin_altivec_vminuh", + "llvm.ppc.altivec.vminuw" => "__builtin_altivec_vminuw", + "llvm.ppc.altivec.vmladduhm" => "__builtin_altivec_vmladduhm", + "llvm.ppc.altivec.vmsummbm" => "__builtin_altivec_vmsummbm", + "llvm.ppc.altivec.vmsumshm" => "__builtin_altivec_vmsumshm", + "llvm.ppc.altivec.vmsumshs" => "__builtin_altivec_vmsumshs", + "llvm.ppc.altivec.vmsumubm" => "__builtin_altivec_vmsumubm", + "llvm.ppc.altivec.vmsumuhm" => "__builtin_altivec_vmsumuhm", + "llvm.ppc.altivec.vmsumuhs" => "__builtin_altivec_vmsumuhs", + "llvm.ppc.altivec.vmulesb" => "__builtin_altivec_vmulesb", + "llvm.ppc.altivec.vmulesh" => "__builtin_altivec_vmulesh", + "llvm.ppc.altivec.vmuleub" => "__builtin_altivec_vmuleub", + "llvm.ppc.altivec.vmuleuh" => "__builtin_altivec_vmuleuh", + "llvm.ppc.altivec.vmulosb" => "__builtin_altivec_vmulosb", + "llvm.ppc.altivec.vmulosh" => "__builtin_altivec_vmulosh", + "llvm.ppc.altivec.vmuloub" => "__builtin_altivec_vmuloub", + "llvm.ppc.altivec.vmulouh" => "__builtin_altivec_vmulouh", + "llvm.ppc.altivec.vnmsubfp" => "__builtin_altivec_vnmsubfp", + "llvm.ppc.altivec.vperm" => "__builtin_altivec_vperm_4si", + "llvm.ppc.altivec.vpkpx" => "__builtin_altivec_vpkpx", + "llvm.ppc.altivec.vpkshss" => "__builtin_altivec_vpkshss", + "llvm.ppc.altivec.vpkshus" => "__builtin_altivec_vpkshus", + "llvm.ppc.altivec.vpkswss" => "__builtin_altivec_vpkswss", + "llvm.ppc.altivec.vpkswus" => "__builtin_altivec_vpkswus", + "llvm.ppc.altivec.vpkuhus" => "__builtin_altivec_vpkuhus", + "llvm.ppc.altivec.vpkuwus" => "__builtin_altivec_vpkuwus", + "llvm.ppc.altivec.vrefp" => "__builtin_altivec_vrefp", + "llvm.ppc.altivec.vrfim" => "__builtin_altivec_vrfim", + "llvm.ppc.altivec.vrfin" => "__builtin_altivec_vrfin", + "llvm.ppc.altivec.vrfip" => "__builtin_altivec_vrfip", + "llvm.ppc.altivec.vrfiz" => "__builtin_altivec_vrfiz", + "llvm.ppc.altivec.vrlb" => "__builtin_altivec_vrlb", + "llvm.ppc.altivec.vrlh" => "__builtin_altivec_vrlh", + "llvm.ppc.altivec.vrlw" => "__builtin_altivec_vrlw", + "llvm.ppc.altivec.vrsqrtefp" => "__builtin_altivec_vrsqrtefp", + "llvm.ppc.altivec.vsel" => "__builtin_altivec_vsel_4si", + "llvm.ppc.altivec.vsl" => "__builtin_altivec_vsl", + "llvm.ppc.altivec.vslb" => "__builtin_altivec_vslb", + "llvm.ppc.altivec.vslh" => "__builtin_altivec_vslh", + "llvm.ppc.altivec.vslo" => "__builtin_altivec_vslo", + "llvm.ppc.altivec.vslw" => "__builtin_altivec_vslw", + "llvm.ppc.altivec.vsr" => "__builtin_altivec_vsr", + "llvm.ppc.altivec.vsrab" => "__builtin_altivec_vsrab", + "llvm.ppc.altivec.vsrah" => "__builtin_altivec_vsrah", + "llvm.ppc.altivec.vsraw" => "__builtin_altivec_vsraw", + "llvm.ppc.altivec.vsrb" => "__builtin_altivec_vsrb", + "llvm.ppc.altivec.vsrh" => "__builtin_altivec_vsrh", + "llvm.ppc.altivec.vsro" => "__builtin_altivec_vsro", + "llvm.ppc.altivec.vsrw" => "__builtin_altivec_vsrw", + "llvm.ppc.altivec.vsubcuw" => "__builtin_altivec_vsubcuw", + "llvm.ppc.altivec.vsubsbs" => "__builtin_altivec_vsubsbs", + "llvm.ppc.altivec.vsubshs" => "__builtin_altivec_vsubshs", + "llvm.ppc.altivec.vsubsws" => "__builtin_altivec_vsubsws", + "llvm.ppc.altivec.vsububs" => "__builtin_altivec_vsububs", + "llvm.ppc.altivec.vsubuhs" => "__builtin_altivec_vsubuhs", + "llvm.ppc.altivec.vsubuws" => "__builtin_altivec_vsubuws", + "llvm.ppc.altivec.vsum2sws" => "__builtin_altivec_vsum2sws", + "llvm.ppc.altivec.vsum4sbs" => "__builtin_altivec_vsum4sbs", + "llvm.ppc.altivec.vsum4shs" => "__builtin_altivec_vsum4shs", + "llvm.ppc.altivec.vsum4ubs" => "__builtin_altivec_vsum4ubs", + "llvm.ppc.altivec.vsumsws" => "__builtin_altivec_vsumsws", + "llvm.ppc.altivec.vupkhpx" => "__builtin_altivec_vupkhpx", + "llvm.ppc.altivec.vupkhsb" => "__builtin_altivec_vupkhsb", + "llvm.ppc.altivec.vupkhsh" => "__builtin_altivec_vupkhsh", + "llvm.ppc.altivec.vupklpx" => "__builtin_altivec_vupklpx", + "llvm.ppc.altivec.vupklsb" => "__builtin_altivec_vupklsb", + "llvm.ppc.altivec.vupklsh" => "__builtin_altivec_vupklsh", + // hexagon + "llvm.hexagon.A2.abs" => "__builtin_HEXAGON_A2_abs", + "llvm.hexagon.A2.absp" => "__builtin_HEXAGON_A2_absp", + "llvm.hexagon.A2.abssat" => "__builtin_HEXAGON_A2_abssat", + "llvm.hexagon.A2.add" => "__builtin_HEXAGON_A2_add", + "llvm.hexagon.A2.addh.h16.hh" => "__builtin_HEXAGON_A2_addh_h16_hh", + "llvm.hexagon.A2.addh.h16.hl" => "__builtin_HEXAGON_A2_addh_h16_hl", + "llvm.hexagon.A2.addh.h16.lh" => "__builtin_HEXAGON_A2_addh_h16_lh", + "llvm.hexagon.A2.addh.h16.ll" => "__builtin_HEXAGON_A2_addh_h16_ll", + "llvm.hexagon.A2.addh.h16.sat.hh" => "__builtin_HEXAGON_A2_addh_h16_sat_hh", + "llvm.hexagon.A2.addh.h16.sat.hl" => "__builtin_HEXAGON_A2_addh_h16_sat_hl", + "llvm.hexagon.A2.addh.h16.sat.lh" => "__builtin_HEXAGON_A2_addh_h16_sat_lh", + "llvm.hexagon.A2.addh.h16.sat.ll" => "__builtin_HEXAGON_A2_addh_h16_sat_ll", + "llvm.hexagon.A2.addh.l16.hl" => "__builtin_HEXAGON_A2_addh_l16_hl", + "llvm.hexagon.A2.addh.l16.ll" => "__builtin_HEXAGON_A2_addh_l16_ll", + "llvm.hexagon.A2.addh.l16.sat.hl" => "__builtin_HEXAGON_A2_addh_l16_sat_hl", + "llvm.hexagon.A2.addh.l16.sat.ll" => "__builtin_HEXAGON_A2_addh_l16_sat_ll", + "llvm.hexagon.A2.addi" => "__builtin_HEXAGON_A2_addi", + "llvm.hexagon.A2.addp" => "__builtin_HEXAGON_A2_addp", + "llvm.hexagon.A2.addpsat" => "__builtin_HEXAGON_A2_addpsat", + "llvm.hexagon.A2.addsat" => "__builtin_HEXAGON_A2_addsat", + "llvm.hexagon.A2.addsp" => "__builtin_HEXAGON_A2_addsp", + "llvm.hexagon.A2.and" => "__builtin_HEXAGON_A2_and", + "llvm.hexagon.A2.andir" => "__builtin_HEXAGON_A2_andir", + "llvm.hexagon.A2.andp" => "__builtin_HEXAGON_A2_andp", + "llvm.hexagon.A2.aslh" => "__builtin_HEXAGON_A2_aslh", + "llvm.hexagon.A2.asrh" => "__builtin_HEXAGON_A2_asrh", + "llvm.hexagon.A2.combine.hh" => "__builtin_HEXAGON_A2_combine_hh", + "llvm.hexagon.A2.combine.hl" => "__builtin_HEXAGON_A2_combine_hl", + "llvm.hexagon.A2.combine.lh" => "__builtin_HEXAGON_A2_combine_lh", + "llvm.hexagon.A2.combine.ll" => "__builtin_HEXAGON_A2_combine_ll", + "llvm.hexagon.A2.combineii" => "__builtin_HEXAGON_A2_combineii", + "llvm.hexagon.A2.combinew" => "__builtin_HEXAGON_A2_combinew", + "llvm.hexagon.A2.max" => "__builtin_HEXAGON_A2_max", + "llvm.hexagon.A2.maxp" => "__builtin_HEXAGON_A2_maxp", + "llvm.hexagon.A2.maxu" => "__builtin_HEXAGON_A2_maxu", + "llvm.hexagon.A2.maxup" => "__builtin_HEXAGON_A2_maxup", + "llvm.hexagon.A2.min" => "__builtin_HEXAGON_A2_min", + "llvm.hexagon.A2.minp" => "__builtin_HEXAGON_A2_minp", + "llvm.hexagon.A2.minu" => "__builtin_HEXAGON_A2_minu", + "llvm.hexagon.A2.minup" => "__builtin_HEXAGON_A2_minup", + "llvm.hexagon.A2.neg" => "__builtin_HEXAGON_A2_neg", + "llvm.hexagon.A2.negp" => "__builtin_HEXAGON_A2_negp", + "llvm.hexagon.A2.negsat" => "__builtin_HEXAGON_A2_negsat", + "llvm.hexagon.A2.not" => "__builtin_HEXAGON_A2_not", + "llvm.hexagon.A2.notp" => "__builtin_HEXAGON_A2_notp", + "llvm.hexagon.A2.or" => "__builtin_HEXAGON_A2_or", + "llvm.hexagon.A2.orir" => "__builtin_HEXAGON_A2_orir", + "llvm.hexagon.A2.orp" => "__builtin_HEXAGON_A2_orp", + "llvm.hexagon.A2.roundsat" => "__builtin_HEXAGON_A2_roundsat", + "llvm.hexagon.A2.sat" => "__builtin_HEXAGON_A2_sat", + "llvm.hexagon.A2.satb" => "__builtin_HEXAGON_A2_satb", + "llvm.hexagon.A2.sath" => "__builtin_HEXAGON_A2_sath", + "llvm.hexagon.A2.satub" => "__builtin_HEXAGON_A2_satub", + "llvm.hexagon.A2.satuh" => "__builtin_HEXAGON_A2_satuh", + "llvm.hexagon.A2.sub" => "__builtin_HEXAGON_A2_sub", + "llvm.hexagon.A2.subh.h16.hh" => "__builtin_HEXAGON_A2_subh_h16_hh", + "llvm.hexagon.A2.subh.h16.hl" => "__builtin_HEXAGON_A2_subh_h16_hl", + "llvm.hexagon.A2.subh.h16.lh" => "__builtin_HEXAGON_A2_subh_h16_lh", + "llvm.hexagon.A2.subh.h16.ll" => "__builtin_HEXAGON_A2_subh_h16_ll", + "llvm.hexagon.A2.subh.h16.sat.hh" => "__builtin_HEXAGON_A2_subh_h16_sat_hh", + "llvm.hexagon.A2.subh.h16.sat.hl" => "__builtin_HEXAGON_A2_subh_h16_sat_hl", + "llvm.hexagon.A2.subh.h16.sat.lh" => "__builtin_HEXAGON_A2_subh_h16_sat_lh", + "llvm.hexagon.A2.subh.h16.sat.ll" => "__builtin_HEXAGON_A2_subh_h16_sat_ll", + "llvm.hexagon.A2.subh.l16.hl" => "__builtin_HEXAGON_A2_subh_l16_hl", + "llvm.hexagon.A2.subh.l16.ll" => "__builtin_HEXAGON_A2_subh_l16_ll", + "llvm.hexagon.A2.subh.l16.sat.hl" => "__builtin_HEXAGON_A2_subh_l16_sat_hl", + "llvm.hexagon.A2.subh.l16.sat.ll" => "__builtin_HEXAGON_A2_subh_l16_sat_ll", + "llvm.hexagon.A2.subp" => "__builtin_HEXAGON_A2_subp", + "llvm.hexagon.A2.subri" => "__builtin_HEXAGON_A2_subri", + "llvm.hexagon.A2.subsat" => "__builtin_HEXAGON_A2_subsat", + "llvm.hexagon.A2.svaddh" => "__builtin_HEXAGON_A2_svaddh", + "llvm.hexagon.A2.svaddhs" => "__builtin_HEXAGON_A2_svaddhs", + "llvm.hexagon.A2.svadduhs" => "__builtin_HEXAGON_A2_svadduhs", + "llvm.hexagon.A2.svavgh" => "__builtin_HEXAGON_A2_svavgh", + "llvm.hexagon.A2.svavghs" => "__builtin_HEXAGON_A2_svavghs", + "llvm.hexagon.A2.svnavgh" => "__builtin_HEXAGON_A2_svnavgh", + "llvm.hexagon.A2.svsubh" => "__builtin_HEXAGON_A2_svsubh", + "llvm.hexagon.A2.svsubhs" => "__builtin_HEXAGON_A2_svsubhs", + "llvm.hexagon.A2.svsubuhs" => "__builtin_HEXAGON_A2_svsubuhs", + "llvm.hexagon.A2.swiz" => "__builtin_HEXAGON_A2_swiz", + "llvm.hexagon.A2.sxtb" => "__builtin_HEXAGON_A2_sxtb", + "llvm.hexagon.A2.sxth" => "__builtin_HEXAGON_A2_sxth", + "llvm.hexagon.A2.sxtw" => "__builtin_HEXAGON_A2_sxtw", + "llvm.hexagon.A2.tfr" => "__builtin_HEXAGON_A2_tfr", + "llvm.hexagon.A2.tfrih" => "__builtin_HEXAGON_A2_tfrih", + "llvm.hexagon.A2.tfril" => "__builtin_HEXAGON_A2_tfril", + "llvm.hexagon.A2.tfrp" => "__builtin_HEXAGON_A2_tfrp", + "llvm.hexagon.A2.tfrpi" => "__builtin_HEXAGON_A2_tfrpi", + "llvm.hexagon.A2.tfrsi" => "__builtin_HEXAGON_A2_tfrsi", + "llvm.hexagon.A2.vabsh" => "__builtin_HEXAGON_A2_vabsh", + "llvm.hexagon.A2.vabshsat" => "__builtin_HEXAGON_A2_vabshsat", + "llvm.hexagon.A2.vabsw" => "__builtin_HEXAGON_A2_vabsw", + "llvm.hexagon.A2.vabswsat" => "__builtin_HEXAGON_A2_vabswsat", + "llvm.hexagon.A2.vaddb.map" => "__builtin_HEXAGON_A2_vaddb_map", + "llvm.hexagon.A2.vaddh" => "__builtin_HEXAGON_A2_vaddh", + "llvm.hexagon.A2.vaddhs" => "__builtin_HEXAGON_A2_vaddhs", + "llvm.hexagon.A2.vaddub" => "__builtin_HEXAGON_A2_vaddub", + "llvm.hexagon.A2.vaddubs" => "__builtin_HEXAGON_A2_vaddubs", + "llvm.hexagon.A2.vadduhs" => "__builtin_HEXAGON_A2_vadduhs", + "llvm.hexagon.A2.vaddw" => "__builtin_HEXAGON_A2_vaddw", + "llvm.hexagon.A2.vaddws" => "__builtin_HEXAGON_A2_vaddws", + "llvm.hexagon.A2.vavgh" => "__builtin_HEXAGON_A2_vavgh", + "llvm.hexagon.A2.vavghcr" => "__builtin_HEXAGON_A2_vavghcr", + "llvm.hexagon.A2.vavghr" => "__builtin_HEXAGON_A2_vavghr", + "llvm.hexagon.A2.vavgub" => "__builtin_HEXAGON_A2_vavgub", + "llvm.hexagon.A2.vavgubr" => "__builtin_HEXAGON_A2_vavgubr", + "llvm.hexagon.A2.vavguh" => "__builtin_HEXAGON_A2_vavguh", + "llvm.hexagon.A2.vavguhr" => "__builtin_HEXAGON_A2_vavguhr", + "llvm.hexagon.A2.vavguw" => "__builtin_HEXAGON_A2_vavguw", + "llvm.hexagon.A2.vavguwr" => "__builtin_HEXAGON_A2_vavguwr", + "llvm.hexagon.A2.vavgw" => "__builtin_HEXAGON_A2_vavgw", + "llvm.hexagon.A2.vavgwcr" => "__builtin_HEXAGON_A2_vavgwcr", + "llvm.hexagon.A2.vavgwr" => "__builtin_HEXAGON_A2_vavgwr", + "llvm.hexagon.A2.vcmpbeq" => "__builtin_HEXAGON_A2_vcmpbeq", + "llvm.hexagon.A2.vcmpbgtu" => "__builtin_HEXAGON_A2_vcmpbgtu", + "llvm.hexagon.A2.vcmpheq" => "__builtin_HEXAGON_A2_vcmpheq", + "llvm.hexagon.A2.vcmphgt" => "__builtin_HEXAGON_A2_vcmphgt", + "llvm.hexagon.A2.vcmphgtu" => "__builtin_HEXAGON_A2_vcmphgtu", + "llvm.hexagon.A2.vcmpweq" => "__builtin_HEXAGON_A2_vcmpweq", + "llvm.hexagon.A2.vcmpwgt" => "__builtin_HEXAGON_A2_vcmpwgt", + "llvm.hexagon.A2.vcmpwgtu" => "__builtin_HEXAGON_A2_vcmpwgtu", + "llvm.hexagon.A2.vconj" => "__builtin_HEXAGON_A2_vconj", + "llvm.hexagon.A2.vmaxb" => "__builtin_HEXAGON_A2_vmaxb", + "llvm.hexagon.A2.vmaxh" => "__builtin_HEXAGON_A2_vmaxh", + "llvm.hexagon.A2.vmaxub" => "__builtin_HEXAGON_A2_vmaxub", + "llvm.hexagon.A2.vmaxuh" => "__builtin_HEXAGON_A2_vmaxuh", + "llvm.hexagon.A2.vmaxuw" => "__builtin_HEXAGON_A2_vmaxuw", + "llvm.hexagon.A2.vmaxw" => "__builtin_HEXAGON_A2_vmaxw", + "llvm.hexagon.A2.vminb" => "__builtin_HEXAGON_A2_vminb", + "llvm.hexagon.A2.vminh" => "__builtin_HEXAGON_A2_vminh", + "llvm.hexagon.A2.vminub" => "__builtin_HEXAGON_A2_vminub", + "llvm.hexagon.A2.vminuh" => "__builtin_HEXAGON_A2_vminuh", + "llvm.hexagon.A2.vminuw" => "__builtin_HEXAGON_A2_vminuw", + "llvm.hexagon.A2.vminw" => "__builtin_HEXAGON_A2_vminw", + "llvm.hexagon.A2.vnavgh" => "__builtin_HEXAGON_A2_vnavgh", + "llvm.hexagon.A2.vnavghcr" => "__builtin_HEXAGON_A2_vnavghcr", + "llvm.hexagon.A2.vnavghr" => "__builtin_HEXAGON_A2_vnavghr", + "llvm.hexagon.A2.vnavgw" => "__builtin_HEXAGON_A2_vnavgw", + "llvm.hexagon.A2.vnavgwcr" => "__builtin_HEXAGON_A2_vnavgwcr", + "llvm.hexagon.A2.vnavgwr" => "__builtin_HEXAGON_A2_vnavgwr", + "llvm.hexagon.A2.vraddub" => "__builtin_HEXAGON_A2_vraddub", + "llvm.hexagon.A2.vraddub.acc" => "__builtin_HEXAGON_A2_vraddub_acc", + "llvm.hexagon.A2.vrsadub" => "__builtin_HEXAGON_A2_vrsadub", + "llvm.hexagon.A2.vrsadub.acc" => "__builtin_HEXAGON_A2_vrsadub_acc", + "llvm.hexagon.A2.vsubb.map" => "__builtin_HEXAGON_A2_vsubb_map", + "llvm.hexagon.A2.vsubh" => "__builtin_HEXAGON_A2_vsubh", + "llvm.hexagon.A2.vsubhs" => "__builtin_HEXAGON_A2_vsubhs", + "llvm.hexagon.A2.vsubub" => "__builtin_HEXAGON_A2_vsubub", + "llvm.hexagon.A2.vsububs" => "__builtin_HEXAGON_A2_vsububs", + "llvm.hexagon.A2.vsubuhs" => "__builtin_HEXAGON_A2_vsubuhs", + "llvm.hexagon.A2.vsubw" => "__builtin_HEXAGON_A2_vsubw", + "llvm.hexagon.A2.vsubws" => "__builtin_HEXAGON_A2_vsubws", + "llvm.hexagon.A2.xor" => "__builtin_HEXAGON_A2_xor", + "llvm.hexagon.A2.xorp" => "__builtin_HEXAGON_A2_xorp", + "llvm.hexagon.A2.zxtb" => "__builtin_HEXAGON_A2_zxtb", + "llvm.hexagon.A2.zxth" => "__builtin_HEXAGON_A2_zxth", + "llvm.hexagon.A4.andn" => "__builtin_HEXAGON_A4_andn", + "llvm.hexagon.A4.andnp" => "__builtin_HEXAGON_A4_andnp", + "llvm.hexagon.A4.bitsplit" => "__builtin_HEXAGON_A4_bitsplit", + "llvm.hexagon.A4.bitspliti" => "__builtin_HEXAGON_A4_bitspliti", + "llvm.hexagon.A4.boundscheck" => "__builtin_HEXAGON_A4_boundscheck", + "llvm.hexagon.A4.cmpbeq" => "__builtin_HEXAGON_A4_cmpbeq", + "llvm.hexagon.A4.cmpbeqi" => "__builtin_HEXAGON_A4_cmpbeqi", + "llvm.hexagon.A4.cmpbgt" => "__builtin_HEXAGON_A4_cmpbgt", + "llvm.hexagon.A4.cmpbgti" => "__builtin_HEXAGON_A4_cmpbgti", + "llvm.hexagon.A4.cmpbgtu" => "__builtin_HEXAGON_A4_cmpbgtu", + "llvm.hexagon.A4.cmpbgtui" => "__builtin_HEXAGON_A4_cmpbgtui", + "llvm.hexagon.A4.cmpheq" => "__builtin_HEXAGON_A4_cmpheq", + "llvm.hexagon.A4.cmpheqi" => "__builtin_HEXAGON_A4_cmpheqi", + "llvm.hexagon.A4.cmphgt" => "__builtin_HEXAGON_A4_cmphgt", + "llvm.hexagon.A4.cmphgti" => "__builtin_HEXAGON_A4_cmphgti", + "llvm.hexagon.A4.cmphgtu" => "__builtin_HEXAGON_A4_cmphgtu", + "llvm.hexagon.A4.cmphgtui" => "__builtin_HEXAGON_A4_cmphgtui", + "llvm.hexagon.A4.combineir" => "__builtin_HEXAGON_A4_combineir", + "llvm.hexagon.A4.combineri" => "__builtin_HEXAGON_A4_combineri", + "llvm.hexagon.A4.cround.ri" => "__builtin_HEXAGON_A4_cround_ri", + "llvm.hexagon.A4.cround.rr" => "__builtin_HEXAGON_A4_cround_rr", + "llvm.hexagon.A4.modwrapu" => "__builtin_HEXAGON_A4_modwrapu", + "llvm.hexagon.A4.orn" => "__builtin_HEXAGON_A4_orn", + "llvm.hexagon.A4.ornp" => "__builtin_HEXAGON_A4_ornp", + "llvm.hexagon.A4.rcmpeq" => "__builtin_HEXAGON_A4_rcmpeq", + "llvm.hexagon.A4.rcmpeqi" => "__builtin_HEXAGON_A4_rcmpeqi", + "llvm.hexagon.A4.rcmpneq" => "__builtin_HEXAGON_A4_rcmpneq", + "llvm.hexagon.A4.rcmpneqi" => "__builtin_HEXAGON_A4_rcmpneqi", + "llvm.hexagon.A4.round.ri" => "__builtin_HEXAGON_A4_round_ri", + "llvm.hexagon.A4.round.ri.sat" => "__builtin_HEXAGON_A4_round_ri_sat", + "llvm.hexagon.A4.round.rr" => "__builtin_HEXAGON_A4_round_rr", + "llvm.hexagon.A4.round.rr.sat" => "__builtin_HEXAGON_A4_round_rr_sat", + "llvm.hexagon.A4.tlbmatch" => "__builtin_HEXAGON_A4_tlbmatch", + "llvm.hexagon.A4.vcmpbeq.any" => "__builtin_HEXAGON_A4_vcmpbeq_any", + "llvm.hexagon.A4.vcmpbeqi" => "__builtin_HEXAGON_A4_vcmpbeqi", + "llvm.hexagon.A4.vcmpbgt" => "__builtin_HEXAGON_A4_vcmpbgt", + "llvm.hexagon.A4.vcmpbgti" => "__builtin_HEXAGON_A4_vcmpbgti", + "llvm.hexagon.A4.vcmpbgtui" => "__builtin_HEXAGON_A4_vcmpbgtui", + "llvm.hexagon.A4.vcmpheqi" => "__builtin_HEXAGON_A4_vcmpheqi", + "llvm.hexagon.A4.vcmphgti" => "__builtin_HEXAGON_A4_vcmphgti", + "llvm.hexagon.A4.vcmphgtui" => "__builtin_HEXAGON_A4_vcmphgtui", + "llvm.hexagon.A4.vcmpweqi" => "__builtin_HEXAGON_A4_vcmpweqi", + "llvm.hexagon.A4.vcmpwgti" => "__builtin_HEXAGON_A4_vcmpwgti", + "llvm.hexagon.A4.vcmpwgtui" => "__builtin_HEXAGON_A4_vcmpwgtui", + "llvm.hexagon.A4.vrmaxh" => "__builtin_HEXAGON_A4_vrmaxh", + "llvm.hexagon.A4.vrmaxuh" => "__builtin_HEXAGON_A4_vrmaxuh", + "llvm.hexagon.A4.vrmaxuw" => "__builtin_HEXAGON_A4_vrmaxuw", + "llvm.hexagon.A4.vrmaxw" => "__builtin_HEXAGON_A4_vrmaxw", + "llvm.hexagon.A4.vrminh" => "__builtin_HEXAGON_A4_vrminh", + "llvm.hexagon.A4.vrminuh" => "__builtin_HEXAGON_A4_vrminuh", + "llvm.hexagon.A4.vrminuw" => "__builtin_HEXAGON_A4_vrminuw", + "llvm.hexagon.A4.vrminw" => "__builtin_HEXAGON_A4_vrminw", + "llvm.hexagon.A5.vaddhubs" => "__builtin_HEXAGON_A5_vaddhubs", + "llvm.hexagon.C2.all8" => "__builtin_HEXAGON_C2_all8", + "llvm.hexagon.C2.and" => "__builtin_HEXAGON_C2_and", + "llvm.hexagon.C2.andn" => "__builtin_HEXAGON_C2_andn", + "llvm.hexagon.C2.any8" => "__builtin_HEXAGON_C2_any8", + "llvm.hexagon.C2.bitsclr" => "__builtin_HEXAGON_C2_bitsclr", + "llvm.hexagon.C2.bitsclri" => "__builtin_HEXAGON_C2_bitsclri", + "llvm.hexagon.C2.bitsset" => "__builtin_HEXAGON_C2_bitsset", + "llvm.hexagon.C2.cmpeq" => "__builtin_HEXAGON_C2_cmpeq", + "llvm.hexagon.C2.cmpeqi" => "__builtin_HEXAGON_C2_cmpeqi", + "llvm.hexagon.C2.cmpeqp" => "__builtin_HEXAGON_C2_cmpeqp", + "llvm.hexagon.C2.cmpgei" => "__builtin_HEXAGON_C2_cmpgei", + "llvm.hexagon.C2.cmpgeui" => "__builtin_HEXAGON_C2_cmpgeui", + "llvm.hexagon.C2.cmpgt" => "__builtin_HEXAGON_C2_cmpgt", + "llvm.hexagon.C2.cmpgti" => "__builtin_HEXAGON_C2_cmpgti", + "llvm.hexagon.C2.cmpgtp" => "__builtin_HEXAGON_C2_cmpgtp", + "llvm.hexagon.C2.cmpgtu" => "__builtin_HEXAGON_C2_cmpgtu", + "llvm.hexagon.C2.cmpgtui" => "__builtin_HEXAGON_C2_cmpgtui", + "llvm.hexagon.C2.cmpgtup" => "__builtin_HEXAGON_C2_cmpgtup", + "llvm.hexagon.C2.cmplt" => "__builtin_HEXAGON_C2_cmplt", + "llvm.hexagon.C2.cmpltu" => "__builtin_HEXAGON_C2_cmpltu", + "llvm.hexagon.C2.mask" => "__builtin_HEXAGON_C2_mask", + "llvm.hexagon.C2.mux" => "__builtin_HEXAGON_C2_mux", + "llvm.hexagon.C2.muxii" => "__builtin_HEXAGON_C2_muxii", + "llvm.hexagon.C2.muxir" => "__builtin_HEXAGON_C2_muxir", + "llvm.hexagon.C2.muxri" => "__builtin_HEXAGON_C2_muxri", + "llvm.hexagon.C2.not" => "__builtin_HEXAGON_C2_not", + "llvm.hexagon.C2.or" => "__builtin_HEXAGON_C2_or", + "llvm.hexagon.C2.orn" => "__builtin_HEXAGON_C2_orn", + "llvm.hexagon.C2.pxfer.map" => "__builtin_HEXAGON_C2_pxfer_map", + "llvm.hexagon.C2.tfrpr" => "__builtin_HEXAGON_C2_tfrpr", + "llvm.hexagon.C2.tfrrp" => "__builtin_HEXAGON_C2_tfrrp", + "llvm.hexagon.C2.vitpack" => "__builtin_HEXAGON_C2_vitpack", + "llvm.hexagon.C2.vmux" => "__builtin_HEXAGON_C2_vmux", + "llvm.hexagon.C2.xor" => "__builtin_HEXAGON_C2_xor", + "llvm.hexagon.C4.and.and" => "__builtin_HEXAGON_C4_and_and", + "llvm.hexagon.C4.and.andn" => "__builtin_HEXAGON_C4_and_andn", + "llvm.hexagon.C4.and.or" => "__builtin_HEXAGON_C4_and_or", + "llvm.hexagon.C4.and.orn" => "__builtin_HEXAGON_C4_and_orn", + "llvm.hexagon.C4.cmplte" => "__builtin_HEXAGON_C4_cmplte", + "llvm.hexagon.C4.cmpltei" => "__builtin_HEXAGON_C4_cmpltei", + "llvm.hexagon.C4.cmplteu" => "__builtin_HEXAGON_C4_cmplteu", + "llvm.hexagon.C4.cmplteui" => "__builtin_HEXAGON_C4_cmplteui", + "llvm.hexagon.C4.cmpneq" => "__builtin_HEXAGON_C4_cmpneq", + "llvm.hexagon.C4.cmpneqi" => "__builtin_HEXAGON_C4_cmpneqi", + "llvm.hexagon.C4.fastcorner9" => "__builtin_HEXAGON_C4_fastcorner9", + "llvm.hexagon.C4.fastcorner9.not" => "__builtin_HEXAGON_C4_fastcorner9_not", + "llvm.hexagon.C4.nbitsclr" => "__builtin_HEXAGON_C4_nbitsclr", + "llvm.hexagon.C4.nbitsclri" => "__builtin_HEXAGON_C4_nbitsclri", + "llvm.hexagon.C4.nbitsset" => "__builtin_HEXAGON_C4_nbitsset", + "llvm.hexagon.C4.or.and" => "__builtin_HEXAGON_C4_or_and", + "llvm.hexagon.C4.or.andn" => "__builtin_HEXAGON_C4_or_andn", + "llvm.hexagon.C4.or.or" => "__builtin_HEXAGON_C4_or_or", + "llvm.hexagon.C4.or.orn" => "__builtin_HEXAGON_C4_or_orn", + "llvm.hexagon.F2.conv.d2df" => "__builtin_HEXAGON_F2_conv_d2df", + "llvm.hexagon.F2.conv.d2sf" => "__builtin_HEXAGON_F2_conv_d2sf", + "llvm.hexagon.F2.conv.df2d" => "__builtin_HEXAGON_F2_conv_df2d", + "llvm.hexagon.F2.conv.df2d.chop" => "__builtin_HEXAGON_F2_conv_df2d_chop", + "llvm.hexagon.F2.conv.df2sf" => "__builtin_HEXAGON_F2_conv_df2sf", + "llvm.hexagon.F2.conv.df2ud" => "__builtin_HEXAGON_F2_conv_df2ud", + "llvm.hexagon.F2.conv.df2ud.chop" => "__builtin_HEXAGON_F2_conv_df2ud_chop", + "llvm.hexagon.F2.conv.df2uw" => "__builtin_HEXAGON_F2_conv_df2uw", + "llvm.hexagon.F2.conv.df2uw.chop" => "__builtin_HEXAGON_F2_conv_df2uw_chop", + "llvm.hexagon.F2.conv.df2w" => "__builtin_HEXAGON_F2_conv_df2w", + "llvm.hexagon.F2.conv.df2w.chop" => "__builtin_HEXAGON_F2_conv_df2w_chop", + "llvm.hexagon.F2.conv.sf2d" => "__builtin_HEXAGON_F2_conv_sf2d", + "llvm.hexagon.F2.conv.sf2d.chop" => "__builtin_HEXAGON_F2_conv_sf2d_chop", + "llvm.hexagon.F2.conv.sf2df" => "__builtin_HEXAGON_F2_conv_sf2df", + "llvm.hexagon.F2.conv.sf2ud" => "__builtin_HEXAGON_F2_conv_sf2ud", + "llvm.hexagon.F2.conv.sf2ud.chop" => "__builtin_HEXAGON_F2_conv_sf2ud_chop", + "llvm.hexagon.F2.conv.sf2uw" => "__builtin_HEXAGON_F2_conv_sf2uw", + "llvm.hexagon.F2.conv.sf2uw.chop" => "__builtin_HEXAGON_F2_conv_sf2uw_chop", + "llvm.hexagon.F2.conv.sf2w" => "__builtin_HEXAGON_F2_conv_sf2w", + "llvm.hexagon.F2.conv.sf2w.chop" => "__builtin_HEXAGON_F2_conv_sf2w_chop", + "llvm.hexagon.F2.conv.ud2df" => "__builtin_HEXAGON_F2_conv_ud2df", + "llvm.hexagon.F2.conv.ud2sf" => "__builtin_HEXAGON_F2_conv_ud2sf", + "llvm.hexagon.F2.conv.uw2df" => "__builtin_HEXAGON_F2_conv_uw2df", + "llvm.hexagon.F2.conv.uw2sf" => "__builtin_HEXAGON_F2_conv_uw2sf", + "llvm.hexagon.F2.conv.w2df" => "__builtin_HEXAGON_F2_conv_w2df", + "llvm.hexagon.F2.conv.w2sf" => "__builtin_HEXAGON_F2_conv_w2sf", + "llvm.hexagon.F2.dfadd" => "__builtin_HEXAGON_F2_dfadd", + "llvm.hexagon.F2.dfclass" => "__builtin_HEXAGON_F2_dfclass", + "llvm.hexagon.F2.dfcmpeq" => "__builtin_HEXAGON_F2_dfcmpeq", + "llvm.hexagon.F2.dfcmpge" => "__builtin_HEXAGON_F2_dfcmpge", + "llvm.hexagon.F2.dfcmpgt" => "__builtin_HEXAGON_F2_dfcmpgt", + "llvm.hexagon.F2.dfcmpuo" => "__builtin_HEXAGON_F2_dfcmpuo", + "llvm.hexagon.F2.dffixupd" => "__builtin_HEXAGON_F2_dffixupd", + "llvm.hexagon.F2.dffixupn" => "__builtin_HEXAGON_F2_dffixupn", + "llvm.hexagon.F2.dffixupr" => "__builtin_HEXAGON_F2_dffixupr", + "llvm.hexagon.F2.dffma" => "__builtin_HEXAGON_F2_dffma", + "llvm.hexagon.F2.dffma.lib" => "__builtin_HEXAGON_F2_dffma_lib", + "llvm.hexagon.F2.dffma.sc" => "__builtin_HEXAGON_F2_dffma_sc", + "llvm.hexagon.F2.dffms" => "__builtin_HEXAGON_F2_dffms", + "llvm.hexagon.F2.dffms.lib" => "__builtin_HEXAGON_F2_dffms_lib", + "llvm.hexagon.F2.dfimm.n" => "__builtin_HEXAGON_F2_dfimm_n", + "llvm.hexagon.F2.dfimm.p" => "__builtin_HEXAGON_F2_dfimm_p", + "llvm.hexagon.F2.dfmax" => "__builtin_HEXAGON_F2_dfmax", + "llvm.hexagon.F2.dfmin" => "__builtin_HEXAGON_F2_dfmin", + "llvm.hexagon.F2.dfmpy" => "__builtin_HEXAGON_F2_dfmpy", + "llvm.hexagon.F2.dfsub" => "__builtin_HEXAGON_F2_dfsub", + "llvm.hexagon.F2.sfadd" => "__builtin_HEXAGON_F2_sfadd", + "llvm.hexagon.F2.sfclass" => "__builtin_HEXAGON_F2_sfclass", + "llvm.hexagon.F2.sfcmpeq" => "__builtin_HEXAGON_F2_sfcmpeq", + "llvm.hexagon.F2.sfcmpge" => "__builtin_HEXAGON_F2_sfcmpge", + "llvm.hexagon.F2.sfcmpgt" => "__builtin_HEXAGON_F2_sfcmpgt", + "llvm.hexagon.F2.sfcmpuo" => "__builtin_HEXAGON_F2_sfcmpuo", + "llvm.hexagon.F2.sffixupd" => "__builtin_HEXAGON_F2_sffixupd", + "llvm.hexagon.F2.sffixupn" => "__builtin_HEXAGON_F2_sffixupn", + "llvm.hexagon.F2.sffixupr" => "__builtin_HEXAGON_F2_sffixupr", + "llvm.hexagon.F2.sffma" => "__builtin_HEXAGON_F2_sffma", + "llvm.hexagon.F2.sffma.lib" => "__builtin_HEXAGON_F2_sffma_lib", + "llvm.hexagon.F2.sffma.sc" => "__builtin_HEXAGON_F2_sffma_sc", + "llvm.hexagon.F2.sffms" => "__builtin_HEXAGON_F2_sffms", + "llvm.hexagon.F2.sffms.lib" => "__builtin_HEXAGON_F2_sffms_lib", + "llvm.hexagon.F2.sfimm.n" => "__builtin_HEXAGON_F2_sfimm_n", + "llvm.hexagon.F2.sfimm.p" => "__builtin_HEXAGON_F2_sfimm_p", + "llvm.hexagon.F2.sfmax" => "__builtin_HEXAGON_F2_sfmax", + "llvm.hexagon.F2.sfmin" => "__builtin_HEXAGON_F2_sfmin", + "llvm.hexagon.F2.sfmpy" => "__builtin_HEXAGON_F2_sfmpy", + "llvm.hexagon.F2.sfsub" => "__builtin_HEXAGON_F2_sfsub", + "llvm.hexagon.M2.acci" => "__builtin_HEXAGON_M2_acci", + "llvm.hexagon.M2.accii" => "__builtin_HEXAGON_M2_accii", + "llvm.hexagon.M2.cmaci.s0" => "__builtin_HEXAGON_M2_cmaci_s0", + "llvm.hexagon.M2.cmacr.s0" => "__builtin_HEXAGON_M2_cmacr_s0", + "llvm.hexagon.M2.cmacs.s0" => "__builtin_HEXAGON_M2_cmacs_s0", + "llvm.hexagon.M2.cmacs.s1" => "__builtin_HEXAGON_M2_cmacs_s1", + "llvm.hexagon.M2.cmacsc.s0" => "__builtin_HEXAGON_M2_cmacsc_s0", + "llvm.hexagon.M2.cmacsc.s1" => "__builtin_HEXAGON_M2_cmacsc_s1", + "llvm.hexagon.M2.cmpyi.s0" => "__builtin_HEXAGON_M2_cmpyi_s0", + "llvm.hexagon.M2.cmpyr.s0" => "__builtin_HEXAGON_M2_cmpyr_s0", + "llvm.hexagon.M2.cmpyrs.s0" => "__builtin_HEXAGON_M2_cmpyrs_s0", + "llvm.hexagon.M2.cmpyrs.s1" => "__builtin_HEXAGON_M2_cmpyrs_s1", + "llvm.hexagon.M2.cmpyrsc.s0" => "__builtin_HEXAGON_M2_cmpyrsc_s0", + "llvm.hexagon.M2.cmpyrsc.s1" => "__builtin_HEXAGON_M2_cmpyrsc_s1", + "llvm.hexagon.M2.cmpys.s0" => "__builtin_HEXAGON_M2_cmpys_s0", + "llvm.hexagon.M2.cmpys.s1" => "__builtin_HEXAGON_M2_cmpys_s1", + "llvm.hexagon.M2.cmpysc.s0" => "__builtin_HEXAGON_M2_cmpysc_s0", + "llvm.hexagon.M2.cmpysc.s1" => "__builtin_HEXAGON_M2_cmpysc_s1", + "llvm.hexagon.M2.cnacs.s0" => "__builtin_HEXAGON_M2_cnacs_s0", + "llvm.hexagon.M2.cnacs.s1" => "__builtin_HEXAGON_M2_cnacs_s1", + "llvm.hexagon.M2.cnacsc.s0" => "__builtin_HEXAGON_M2_cnacsc_s0", + "llvm.hexagon.M2.cnacsc.s1" => "__builtin_HEXAGON_M2_cnacsc_s1", + "llvm.hexagon.M2.dpmpyss.acc.s0" => "__builtin_HEXAGON_M2_dpmpyss_acc_s0", + "llvm.hexagon.M2.dpmpyss.nac.s0" => "__builtin_HEXAGON_M2_dpmpyss_nac_s0", + "llvm.hexagon.M2.dpmpyss.rnd.s0" => "__builtin_HEXAGON_M2_dpmpyss_rnd_s0", + "llvm.hexagon.M2.dpmpyss.s0" => "__builtin_HEXAGON_M2_dpmpyss_s0", + "llvm.hexagon.M2.dpmpyuu.acc.s0" => "__builtin_HEXAGON_M2_dpmpyuu_acc_s0", + "llvm.hexagon.M2.dpmpyuu.nac.s0" => "__builtin_HEXAGON_M2_dpmpyuu_nac_s0", + "llvm.hexagon.M2.dpmpyuu.s0" => "__builtin_HEXAGON_M2_dpmpyuu_s0", + "llvm.hexagon.M2.hmmpyh.rs1" => "__builtin_HEXAGON_M2_hmmpyh_rs1", + "llvm.hexagon.M2.hmmpyh.s1" => "__builtin_HEXAGON_M2_hmmpyh_s1", + "llvm.hexagon.M2.hmmpyl.rs1" => "__builtin_HEXAGON_M2_hmmpyl_rs1", + "llvm.hexagon.M2.hmmpyl.s1" => "__builtin_HEXAGON_M2_hmmpyl_s1", + "llvm.hexagon.M2.maci" => "__builtin_HEXAGON_M2_maci", + "llvm.hexagon.M2.macsin" => "__builtin_HEXAGON_M2_macsin", + "llvm.hexagon.M2.macsip" => "__builtin_HEXAGON_M2_macsip", + "llvm.hexagon.M2.mmachs.rs0" => "__builtin_HEXAGON_M2_mmachs_rs0", + "llvm.hexagon.M2.mmachs.rs1" => "__builtin_HEXAGON_M2_mmachs_rs1", + "llvm.hexagon.M2.mmachs.s0" => "__builtin_HEXAGON_M2_mmachs_s0", + "llvm.hexagon.M2.mmachs.s1" => "__builtin_HEXAGON_M2_mmachs_s1", + "llvm.hexagon.M2.mmacls.rs0" => "__builtin_HEXAGON_M2_mmacls_rs0", + "llvm.hexagon.M2.mmacls.rs1" => "__builtin_HEXAGON_M2_mmacls_rs1", + "llvm.hexagon.M2.mmacls.s0" => "__builtin_HEXAGON_M2_mmacls_s0", + "llvm.hexagon.M2.mmacls.s1" => "__builtin_HEXAGON_M2_mmacls_s1", + "llvm.hexagon.M2.mmacuhs.rs0" => "__builtin_HEXAGON_M2_mmacuhs_rs0", + "llvm.hexagon.M2.mmacuhs.rs1" => "__builtin_HEXAGON_M2_mmacuhs_rs1", + "llvm.hexagon.M2.mmacuhs.s0" => "__builtin_HEXAGON_M2_mmacuhs_s0", + "llvm.hexagon.M2.mmacuhs.s1" => "__builtin_HEXAGON_M2_mmacuhs_s1", + "llvm.hexagon.M2.mmaculs.rs0" => "__builtin_HEXAGON_M2_mmaculs_rs0", + "llvm.hexagon.M2.mmaculs.rs1" => "__builtin_HEXAGON_M2_mmaculs_rs1", + "llvm.hexagon.M2.mmaculs.s0" => "__builtin_HEXAGON_M2_mmaculs_s0", + "llvm.hexagon.M2.mmaculs.s1" => "__builtin_HEXAGON_M2_mmaculs_s1", + "llvm.hexagon.M2.mmpyh.rs0" => "__builtin_HEXAGON_M2_mmpyh_rs0", + "llvm.hexagon.M2.mmpyh.rs1" => "__builtin_HEXAGON_M2_mmpyh_rs1", + "llvm.hexagon.M2.mmpyh.s0" => "__builtin_HEXAGON_M2_mmpyh_s0", + "llvm.hexagon.M2.mmpyh.s1" => "__builtin_HEXAGON_M2_mmpyh_s1", + "llvm.hexagon.M2.mmpyl.rs0" => "__builtin_HEXAGON_M2_mmpyl_rs0", + "llvm.hexagon.M2.mmpyl.rs1" => "__builtin_HEXAGON_M2_mmpyl_rs1", + "llvm.hexagon.M2.mmpyl.s0" => "__builtin_HEXAGON_M2_mmpyl_s0", + "llvm.hexagon.M2.mmpyl.s1" => "__builtin_HEXAGON_M2_mmpyl_s1", + "llvm.hexagon.M2.mmpyuh.rs0" => "__builtin_HEXAGON_M2_mmpyuh_rs0", + "llvm.hexagon.M2.mmpyuh.rs1" => "__builtin_HEXAGON_M2_mmpyuh_rs1", + "llvm.hexagon.M2.mmpyuh.s0" => "__builtin_HEXAGON_M2_mmpyuh_s0", + "llvm.hexagon.M2.mmpyuh.s1" => "__builtin_HEXAGON_M2_mmpyuh_s1", + "llvm.hexagon.M2.mmpyul.rs0" => "__builtin_HEXAGON_M2_mmpyul_rs0", + "llvm.hexagon.M2.mmpyul.rs1" => "__builtin_HEXAGON_M2_mmpyul_rs1", + "llvm.hexagon.M2.mmpyul.s0" => "__builtin_HEXAGON_M2_mmpyul_s0", + "llvm.hexagon.M2.mmpyul.s1" => "__builtin_HEXAGON_M2_mmpyul_s1", + "llvm.hexagon.M2.mpy.acc.hh.s0" => "__builtin_HEXAGON_M2_mpy_acc_hh_s0", + "llvm.hexagon.M2.mpy.acc.hh.s1" => "__builtin_HEXAGON_M2_mpy_acc_hh_s1", + "llvm.hexagon.M2.mpy.acc.hl.s0" => "__builtin_HEXAGON_M2_mpy_acc_hl_s0", + "llvm.hexagon.M2.mpy.acc.hl.s1" => "__builtin_HEXAGON_M2_mpy_acc_hl_s1", + "llvm.hexagon.M2.mpy.acc.lh.s0" => "__builtin_HEXAGON_M2_mpy_acc_lh_s0", + "llvm.hexagon.M2.mpy.acc.lh.s1" => "__builtin_HEXAGON_M2_mpy_acc_lh_s1", + "llvm.hexagon.M2.mpy.acc.ll.s0" => "__builtin_HEXAGON_M2_mpy_acc_ll_s0", + "llvm.hexagon.M2.mpy.acc.ll.s1" => "__builtin_HEXAGON_M2_mpy_acc_ll_s1", + "llvm.hexagon.M2.mpy.acc.sat.hh.s0" => "__builtin_HEXAGON_M2_mpy_acc_sat_hh_s0", + "llvm.hexagon.M2.mpy.acc.sat.hh.s1" => "__builtin_HEXAGON_M2_mpy_acc_sat_hh_s1", + "llvm.hexagon.M2.mpy.acc.sat.hl.s0" => "__builtin_HEXAGON_M2_mpy_acc_sat_hl_s0", + "llvm.hexagon.M2.mpy.acc.sat.hl.s1" => "__builtin_HEXAGON_M2_mpy_acc_sat_hl_s1", + "llvm.hexagon.M2.mpy.acc.sat.lh.s0" => "__builtin_HEXAGON_M2_mpy_acc_sat_lh_s0", + "llvm.hexagon.M2.mpy.acc.sat.lh.s1" => "__builtin_HEXAGON_M2_mpy_acc_sat_lh_s1", + "llvm.hexagon.M2.mpy.acc.sat.ll.s0" => "__builtin_HEXAGON_M2_mpy_acc_sat_ll_s0", + "llvm.hexagon.M2.mpy.acc.sat.ll.s1" => "__builtin_HEXAGON_M2_mpy_acc_sat_ll_s1", + "llvm.hexagon.M2.mpy.hh.s0" => "__builtin_HEXAGON_M2_mpy_hh_s0", + "llvm.hexagon.M2.mpy.hh.s1" => "__builtin_HEXAGON_M2_mpy_hh_s1", + "llvm.hexagon.M2.mpy.hl.s0" => "__builtin_HEXAGON_M2_mpy_hl_s0", + "llvm.hexagon.M2.mpy.hl.s1" => "__builtin_HEXAGON_M2_mpy_hl_s1", + "llvm.hexagon.M2.mpy.lh.s0" => "__builtin_HEXAGON_M2_mpy_lh_s0", + "llvm.hexagon.M2.mpy.lh.s1" => "__builtin_HEXAGON_M2_mpy_lh_s1", + "llvm.hexagon.M2.mpy.ll.s0" => "__builtin_HEXAGON_M2_mpy_ll_s0", + "llvm.hexagon.M2.mpy.ll.s1" => "__builtin_HEXAGON_M2_mpy_ll_s1", + "llvm.hexagon.M2.mpy.nac.hh.s0" => "__builtin_HEXAGON_M2_mpy_nac_hh_s0", + "llvm.hexagon.M2.mpy.nac.hh.s1" => "__builtin_HEXAGON_M2_mpy_nac_hh_s1", + "llvm.hexagon.M2.mpy.nac.hl.s0" => "__builtin_HEXAGON_M2_mpy_nac_hl_s0", + "llvm.hexagon.M2.mpy.nac.hl.s1" => "__builtin_HEXAGON_M2_mpy_nac_hl_s1", + "llvm.hexagon.M2.mpy.nac.lh.s0" => "__builtin_HEXAGON_M2_mpy_nac_lh_s0", + "llvm.hexagon.M2.mpy.nac.lh.s1" => "__builtin_HEXAGON_M2_mpy_nac_lh_s1", + "llvm.hexagon.M2.mpy.nac.ll.s0" => "__builtin_HEXAGON_M2_mpy_nac_ll_s0", + "llvm.hexagon.M2.mpy.nac.ll.s1" => "__builtin_HEXAGON_M2_mpy_nac_ll_s1", + "llvm.hexagon.M2.mpy.nac.sat.hh.s0" => "__builtin_HEXAGON_M2_mpy_nac_sat_hh_s0", + "llvm.hexagon.M2.mpy.nac.sat.hh.s1" => "__builtin_HEXAGON_M2_mpy_nac_sat_hh_s1", + "llvm.hexagon.M2.mpy.nac.sat.hl.s0" => "__builtin_HEXAGON_M2_mpy_nac_sat_hl_s0", + "llvm.hexagon.M2.mpy.nac.sat.hl.s1" => "__builtin_HEXAGON_M2_mpy_nac_sat_hl_s1", + "llvm.hexagon.M2.mpy.nac.sat.lh.s0" => "__builtin_HEXAGON_M2_mpy_nac_sat_lh_s0", + "llvm.hexagon.M2.mpy.nac.sat.lh.s1" => "__builtin_HEXAGON_M2_mpy_nac_sat_lh_s1", + "llvm.hexagon.M2.mpy.nac.sat.ll.s0" => "__builtin_HEXAGON_M2_mpy_nac_sat_ll_s0", + "llvm.hexagon.M2.mpy.nac.sat.ll.s1" => "__builtin_HEXAGON_M2_mpy_nac_sat_ll_s1", + "llvm.hexagon.M2.mpy.rnd.hh.s0" => "__builtin_HEXAGON_M2_mpy_rnd_hh_s0", + "llvm.hexagon.M2.mpy.rnd.hh.s1" => "__builtin_HEXAGON_M2_mpy_rnd_hh_s1", + "llvm.hexagon.M2.mpy.rnd.hl.s0" => "__builtin_HEXAGON_M2_mpy_rnd_hl_s0", + "llvm.hexagon.M2.mpy.rnd.hl.s1" => "__builtin_HEXAGON_M2_mpy_rnd_hl_s1", + "llvm.hexagon.M2.mpy.rnd.lh.s0" => "__builtin_HEXAGON_M2_mpy_rnd_lh_s0", + "llvm.hexagon.M2.mpy.rnd.lh.s1" => "__builtin_HEXAGON_M2_mpy_rnd_lh_s1", + "llvm.hexagon.M2.mpy.rnd.ll.s0" => "__builtin_HEXAGON_M2_mpy_rnd_ll_s0", + "llvm.hexagon.M2.mpy.rnd.ll.s1" => "__builtin_HEXAGON_M2_mpy_rnd_ll_s1", + "llvm.hexagon.M2.mpy.sat.hh.s0" => "__builtin_HEXAGON_M2_mpy_sat_hh_s0", + "llvm.hexagon.M2.mpy.sat.hh.s1" => "__builtin_HEXAGON_M2_mpy_sat_hh_s1", + "llvm.hexagon.M2.mpy.sat.hl.s0" => "__builtin_HEXAGON_M2_mpy_sat_hl_s0", + "llvm.hexagon.M2.mpy.sat.hl.s1" => "__builtin_HEXAGON_M2_mpy_sat_hl_s1", + "llvm.hexagon.M2.mpy.sat.lh.s0" => "__builtin_HEXAGON_M2_mpy_sat_lh_s0", + "llvm.hexagon.M2.mpy.sat.lh.s1" => "__builtin_HEXAGON_M2_mpy_sat_lh_s1", + "llvm.hexagon.M2.mpy.sat.ll.s0" => "__builtin_HEXAGON_M2_mpy_sat_ll_s0", + "llvm.hexagon.M2.mpy.sat.ll.s1" => "__builtin_HEXAGON_M2_mpy_sat_ll_s1", + "llvm.hexagon.M2.mpy.sat.rnd.hh.s0" => "__builtin_HEXAGON_M2_mpy_sat_rnd_hh_s0", + "llvm.hexagon.M2.mpy.sat.rnd.hh.s1" => "__builtin_HEXAGON_M2_mpy_sat_rnd_hh_s1", + "llvm.hexagon.M2.mpy.sat.rnd.hl.s0" => "__builtin_HEXAGON_M2_mpy_sat_rnd_hl_s0", + "llvm.hexagon.M2.mpy.sat.rnd.hl.s1" => "__builtin_HEXAGON_M2_mpy_sat_rnd_hl_s1", + "llvm.hexagon.M2.mpy.sat.rnd.lh.s0" => "__builtin_HEXAGON_M2_mpy_sat_rnd_lh_s0", + "llvm.hexagon.M2.mpy.sat.rnd.lh.s1" => "__builtin_HEXAGON_M2_mpy_sat_rnd_lh_s1", + "llvm.hexagon.M2.mpy.sat.rnd.ll.s0" => "__builtin_HEXAGON_M2_mpy_sat_rnd_ll_s0", + "llvm.hexagon.M2.mpy.sat.rnd.ll.s1" => "__builtin_HEXAGON_M2_mpy_sat_rnd_ll_s1", + "llvm.hexagon.M2.mpy.up" => "__builtin_HEXAGON_M2_mpy_up", + "llvm.hexagon.M2.mpy.up.s1" => "__builtin_HEXAGON_M2_mpy_up_s1", + "llvm.hexagon.M2.mpy.up.s1.sat" => "__builtin_HEXAGON_M2_mpy_up_s1_sat", + "llvm.hexagon.M2.mpyd.acc.hh.s0" => "__builtin_HEXAGON_M2_mpyd_acc_hh_s0", + "llvm.hexagon.M2.mpyd.acc.hh.s1" => "__builtin_HEXAGON_M2_mpyd_acc_hh_s1", + "llvm.hexagon.M2.mpyd.acc.hl.s0" => "__builtin_HEXAGON_M2_mpyd_acc_hl_s0", + "llvm.hexagon.M2.mpyd.acc.hl.s1" => "__builtin_HEXAGON_M2_mpyd_acc_hl_s1", + "llvm.hexagon.M2.mpyd.acc.lh.s0" => "__builtin_HEXAGON_M2_mpyd_acc_lh_s0", + "llvm.hexagon.M2.mpyd.acc.lh.s1" => "__builtin_HEXAGON_M2_mpyd_acc_lh_s1", + "llvm.hexagon.M2.mpyd.acc.ll.s0" => "__builtin_HEXAGON_M2_mpyd_acc_ll_s0", + "llvm.hexagon.M2.mpyd.acc.ll.s1" => "__builtin_HEXAGON_M2_mpyd_acc_ll_s1", + "llvm.hexagon.M2.mpyd.hh.s0" => "__builtin_HEXAGON_M2_mpyd_hh_s0", + "llvm.hexagon.M2.mpyd.hh.s1" => "__builtin_HEXAGON_M2_mpyd_hh_s1", + "llvm.hexagon.M2.mpyd.hl.s0" => "__builtin_HEXAGON_M2_mpyd_hl_s0", + "llvm.hexagon.M2.mpyd.hl.s1" => "__builtin_HEXAGON_M2_mpyd_hl_s1", + "llvm.hexagon.M2.mpyd.lh.s0" => "__builtin_HEXAGON_M2_mpyd_lh_s0", + "llvm.hexagon.M2.mpyd.lh.s1" => "__builtin_HEXAGON_M2_mpyd_lh_s1", + "llvm.hexagon.M2.mpyd.ll.s0" => "__builtin_HEXAGON_M2_mpyd_ll_s0", + "llvm.hexagon.M2.mpyd.ll.s1" => "__builtin_HEXAGON_M2_mpyd_ll_s1", + "llvm.hexagon.M2.mpyd.nac.hh.s0" => "__builtin_HEXAGON_M2_mpyd_nac_hh_s0", + "llvm.hexagon.M2.mpyd.nac.hh.s1" => "__builtin_HEXAGON_M2_mpyd_nac_hh_s1", + "llvm.hexagon.M2.mpyd.nac.hl.s0" => "__builtin_HEXAGON_M2_mpyd_nac_hl_s0", + "llvm.hexagon.M2.mpyd.nac.hl.s1" => "__builtin_HEXAGON_M2_mpyd_nac_hl_s1", + "llvm.hexagon.M2.mpyd.nac.lh.s0" => "__builtin_HEXAGON_M2_mpyd_nac_lh_s0", + "llvm.hexagon.M2.mpyd.nac.lh.s1" => "__builtin_HEXAGON_M2_mpyd_nac_lh_s1", + "llvm.hexagon.M2.mpyd.nac.ll.s0" => "__builtin_HEXAGON_M2_mpyd_nac_ll_s0", + "llvm.hexagon.M2.mpyd.nac.ll.s1" => "__builtin_HEXAGON_M2_mpyd_nac_ll_s1", + "llvm.hexagon.M2.mpyd.rnd.hh.s0" => "__builtin_HEXAGON_M2_mpyd_rnd_hh_s0", + "llvm.hexagon.M2.mpyd.rnd.hh.s1" => "__builtin_HEXAGON_M2_mpyd_rnd_hh_s1", + "llvm.hexagon.M2.mpyd.rnd.hl.s0" => "__builtin_HEXAGON_M2_mpyd_rnd_hl_s0", + "llvm.hexagon.M2.mpyd.rnd.hl.s1" => "__builtin_HEXAGON_M2_mpyd_rnd_hl_s1", + "llvm.hexagon.M2.mpyd.rnd.lh.s0" => "__builtin_HEXAGON_M2_mpyd_rnd_lh_s0", + "llvm.hexagon.M2.mpyd.rnd.lh.s1" => "__builtin_HEXAGON_M2_mpyd_rnd_lh_s1", + "llvm.hexagon.M2.mpyd.rnd.ll.s0" => "__builtin_HEXAGON_M2_mpyd_rnd_ll_s0", + "llvm.hexagon.M2.mpyd.rnd.ll.s1" => "__builtin_HEXAGON_M2_mpyd_rnd_ll_s1", + "llvm.hexagon.M2.mpyi" => "__builtin_HEXAGON_M2_mpyi", + "llvm.hexagon.M2.mpysmi" => "__builtin_HEXAGON_M2_mpysmi", + "llvm.hexagon.M2.mpysu.up" => "__builtin_HEXAGON_M2_mpysu_up", + "llvm.hexagon.M2.mpyu.acc.hh.s0" => "__builtin_HEXAGON_M2_mpyu_acc_hh_s0", + "llvm.hexagon.M2.mpyu.acc.hh.s1" => "__builtin_HEXAGON_M2_mpyu_acc_hh_s1", + "llvm.hexagon.M2.mpyu.acc.hl.s0" => "__builtin_HEXAGON_M2_mpyu_acc_hl_s0", + "llvm.hexagon.M2.mpyu.acc.hl.s1" => "__builtin_HEXAGON_M2_mpyu_acc_hl_s1", + "llvm.hexagon.M2.mpyu.acc.lh.s0" => "__builtin_HEXAGON_M2_mpyu_acc_lh_s0", + "llvm.hexagon.M2.mpyu.acc.lh.s1" => "__builtin_HEXAGON_M2_mpyu_acc_lh_s1", + "llvm.hexagon.M2.mpyu.acc.ll.s0" => "__builtin_HEXAGON_M2_mpyu_acc_ll_s0", + "llvm.hexagon.M2.mpyu.acc.ll.s1" => "__builtin_HEXAGON_M2_mpyu_acc_ll_s1", + "llvm.hexagon.M2.mpyu.hh.s0" => "__builtin_HEXAGON_M2_mpyu_hh_s0", + "llvm.hexagon.M2.mpyu.hh.s1" => "__builtin_HEXAGON_M2_mpyu_hh_s1", + "llvm.hexagon.M2.mpyu.hl.s0" => "__builtin_HEXAGON_M2_mpyu_hl_s0", + "llvm.hexagon.M2.mpyu.hl.s1" => "__builtin_HEXAGON_M2_mpyu_hl_s1", + "llvm.hexagon.M2.mpyu.lh.s0" => "__builtin_HEXAGON_M2_mpyu_lh_s0", + "llvm.hexagon.M2.mpyu.lh.s1" => "__builtin_HEXAGON_M2_mpyu_lh_s1", + "llvm.hexagon.M2.mpyu.ll.s0" => "__builtin_HEXAGON_M2_mpyu_ll_s0", + "llvm.hexagon.M2.mpyu.ll.s1" => "__builtin_HEXAGON_M2_mpyu_ll_s1", + "llvm.hexagon.M2.mpyu.nac.hh.s0" => "__builtin_HEXAGON_M2_mpyu_nac_hh_s0", + "llvm.hexagon.M2.mpyu.nac.hh.s1" => "__builtin_HEXAGON_M2_mpyu_nac_hh_s1", + "llvm.hexagon.M2.mpyu.nac.hl.s0" => "__builtin_HEXAGON_M2_mpyu_nac_hl_s0", + "llvm.hexagon.M2.mpyu.nac.hl.s1" => "__builtin_HEXAGON_M2_mpyu_nac_hl_s1", + "llvm.hexagon.M2.mpyu.nac.lh.s0" => "__builtin_HEXAGON_M2_mpyu_nac_lh_s0", + "llvm.hexagon.M2.mpyu.nac.lh.s1" => "__builtin_HEXAGON_M2_mpyu_nac_lh_s1", + "llvm.hexagon.M2.mpyu.nac.ll.s0" => "__builtin_HEXAGON_M2_mpyu_nac_ll_s0", + "llvm.hexagon.M2.mpyu.nac.ll.s1" => "__builtin_HEXAGON_M2_mpyu_nac_ll_s1", + "llvm.hexagon.M2.mpyu.up" => "__builtin_HEXAGON_M2_mpyu_up", + "llvm.hexagon.M2.mpyud.acc.hh.s0" => "__builtin_HEXAGON_M2_mpyud_acc_hh_s0", + "llvm.hexagon.M2.mpyud.acc.hh.s1" => "__builtin_HEXAGON_M2_mpyud_acc_hh_s1", + "llvm.hexagon.M2.mpyud.acc.hl.s0" => "__builtin_HEXAGON_M2_mpyud_acc_hl_s0", + "llvm.hexagon.M2.mpyud.acc.hl.s1" => "__builtin_HEXAGON_M2_mpyud_acc_hl_s1", + "llvm.hexagon.M2.mpyud.acc.lh.s0" => "__builtin_HEXAGON_M2_mpyud_acc_lh_s0", + "llvm.hexagon.M2.mpyud.acc.lh.s1" => "__builtin_HEXAGON_M2_mpyud_acc_lh_s1", + "llvm.hexagon.M2.mpyud.acc.ll.s0" => "__builtin_HEXAGON_M2_mpyud_acc_ll_s0", + "llvm.hexagon.M2.mpyud.acc.ll.s1" => "__builtin_HEXAGON_M2_mpyud_acc_ll_s1", + "llvm.hexagon.M2.mpyud.hh.s0" => "__builtin_HEXAGON_M2_mpyud_hh_s0", + "llvm.hexagon.M2.mpyud.hh.s1" => "__builtin_HEXAGON_M2_mpyud_hh_s1", + "llvm.hexagon.M2.mpyud.hl.s0" => "__builtin_HEXAGON_M2_mpyud_hl_s0", + "llvm.hexagon.M2.mpyud.hl.s1" => "__builtin_HEXAGON_M2_mpyud_hl_s1", + "llvm.hexagon.M2.mpyud.lh.s0" => "__builtin_HEXAGON_M2_mpyud_lh_s0", + "llvm.hexagon.M2.mpyud.lh.s1" => "__builtin_HEXAGON_M2_mpyud_lh_s1", + "llvm.hexagon.M2.mpyud.ll.s0" => "__builtin_HEXAGON_M2_mpyud_ll_s0", + "llvm.hexagon.M2.mpyud.ll.s1" => "__builtin_HEXAGON_M2_mpyud_ll_s1", + "llvm.hexagon.M2.mpyud.nac.hh.s0" => "__builtin_HEXAGON_M2_mpyud_nac_hh_s0", + "llvm.hexagon.M2.mpyud.nac.hh.s1" => "__builtin_HEXAGON_M2_mpyud_nac_hh_s1", + "llvm.hexagon.M2.mpyud.nac.hl.s0" => "__builtin_HEXAGON_M2_mpyud_nac_hl_s0", + "llvm.hexagon.M2.mpyud.nac.hl.s1" => "__builtin_HEXAGON_M2_mpyud_nac_hl_s1", + "llvm.hexagon.M2.mpyud.nac.lh.s0" => "__builtin_HEXAGON_M2_mpyud_nac_lh_s0", + "llvm.hexagon.M2.mpyud.nac.lh.s1" => "__builtin_HEXAGON_M2_mpyud_nac_lh_s1", + "llvm.hexagon.M2.mpyud.nac.ll.s0" => "__builtin_HEXAGON_M2_mpyud_nac_ll_s0", + "llvm.hexagon.M2.mpyud.nac.ll.s1" => "__builtin_HEXAGON_M2_mpyud_nac_ll_s1", + "llvm.hexagon.M2.mpyui" => "__builtin_HEXAGON_M2_mpyui", + "llvm.hexagon.M2.nacci" => "__builtin_HEXAGON_M2_nacci", + "llvm.hexagon.M2.naccii" => "__builtin_HEXAGON_M2_naccii", + "llvm.hexagon.M2.subacc" => "__builtin_HEXAGON_M2_subacc", + "llvm.hexagon.M2.vabsdiffh" => "__builtin_HEXAGON_M2_vabsdiffh", + "llvm.hexagon.M2.vabsdiffw" => "__builtin_HEXAGON_M2_vabsdiffw", + "llvm.hexagon.M2.vcmac.s0.sat.i" => "__builtin_HEXAGON_M2_vcmac_s0_sat_i", + "llvm.hexagon.M2.vcmac.s0.sat.r" => "__builtin_HEXAGON_M2_vcmac_s0_sat_r", + "llvm.hexagon.M2.vcmpy.s0.sat.i" => "__builtin_HEXAGON_M2_vcmpy_s0_sat_i", + "llvm.hexagon.M2.vcmpy.s0.sat.r" => "__builtin_HEXAGON_M2_vcmpy_s0_sat_r", + "llvm.hexagon.M2.vcmpy.s1.sat.i" => "__builtin_HEXAGON_M2_vcmpy_s1_sat_i", + "llvm.hexagon.M2.vcmpy.s1.sat.r" => "__builtin_HEXAGON_M2_vcmpy_s1_sat_r", + "llvm.hexagon.M2.vdmacs.s0" => "__builtin_HEXAGON_M2_vdmacs_s0", + "llvm.hexagon.M2.vdmacs.s1" => "__builtin_HEXAGON_M2_vdmacs_s1", + "llvm.hexagon.M2.vdmpyrs.s0" => "__builtin_HEXAGON_M2_vdmpyrs_s0", + "llvm.hexagon.M2.vdmpyrs.s1" => "__builtin_HEXAGON_M2_vdmpyrs_s1", + "llvm.hexagon.M2.vdmpys.s0" => "__builtin_HEXAGON_M2_vdmpys_s0", + "llvm.hexagon.M2.vdmpys.s1" => "__builtin_HEXAGON_M2_vdmpys_s1", + "llvm.hexagon.M2.vmac2" => "__builtin_HEXAGON_M2_vmac2", + "llvm.hexagon.M2.vmac2es" => "__builtin_HEXAGON_M2_vmac2es", + "llvm.hexagon.M2.vmac2es.s0" => "__builtin_HEXAGON_M2_vmac2es_s0", + "llvm.hexagon.M2.vmac2es.s1" => "__builtin_HEXAGON_M2_vmac2es_s1", + "llvm.hexagon.M2.vmac2s.s0" => "__builtin_HEXAGON_M2_vmac2s_s0", + "llvm.hexagon.M2.vmac2s.s1" => "__builtin_HEXAGON_M2_vmac2s_s1", + "llvm.hexagon.M2.vmac2su.s0" => "__builtin_HEXAGON_M2_vmac2su_s0", + "llvm.hexagon.M2.vmac2su.s1" => "__builtin_HEXAGON_M2_vmac2su_s1", + "llvm.hexagon.M2.vmpy2es.s0" => "__builtin_HEXAGON_M2_vmpy2es_s0", + "llvm.hexagon.M2.vmpy2es.s1" => "__builtin_HEXAGON_M2_vmpy2es_s1", + "llvm.hexagon.M2.vmpy2s.s0" => "__builtin_HEXAGON_M2_vmpy2s_s0", + "llvm.hexagon.M2.vmpy2s.s0pack" => "__builtin_HEXAGON_M2_vmpy2s_s0pack", + "llvm.hexagon.M2.vmpy2s.s1" => "__builtin_HEXAGON_M2_vmpy2s_s1", + "llvm.hexagon.M2.vmpy2s.s1pack" => "__builtin_HEXAGON_M2_vmpy2s_s1pack", + "llvm.hexagon.M2.vmpy2su.s0" => "__builtin_HEXAGON_M2_vmpy2su_s0", + "llvm.hexagon.M2.vmpy2su.s1" => "__builtin_HEXAGON_M2_vmpy2su_s1", + "llvm.hexagon.M2.vraddh" => "__builtin_HEXAGON_M2_vraddh", + "llvm.hexagon.M2.vradduh" => "__builtin_HEXAGON_M2_vradduh", + "llvm.hexagon.M2.vrcmaci.s0" => "__builtin_HEXAGON_M2_vrcmaci_s0", + "llvm.hexagon.M2.vrcmaci.s0c" => "__builtin_HEXAGON_M2_vrcmaci_s0c", + "llvm.hexagon.M2.vrcmacr.s0" => "__builtin_HEXAGON_M2_vrcmacr_s0", + "llvm.hexagon.M2.vrcmacr.s0c" => "__builtin_HEXAGON_M2_vrcmacr_s0c", + "llvm.hexagon.M2.vrcmpyi.s0" => "__builtin_HEXAGON_M2_vrcmpyi_s0", + "llvm.hexagon.M2.vrcmpyi.s0c" => "__builtin_HEXAGON_M2_vrcmpyi_s0c", + "llvm.hexagon.M2.vrcmpyr.s0" => "__builtin_HEXAGON_M2_vrcmpyr_s0", + "llvm.hexagon.M2.vrcmpyr.s0c" => "__builtin_HEXAGON_M2_vrcmpyr_s0c", + "llvm.hexagon.M2.vrcmpys.acc.s1" => "__builtin_HEXAGON_M2_vrcmpys_acc_s1", + "llvm.hexagon.M2.vrcmpys.s1" => "__builtin_HEXAGON_M2_vrcmpys_s1", + "llvm.hexagon.M2.vrcmpys.s1rp" => "__builtin_HEXAGON_M2_vrcmpys_s1rp", + "llvm.hexagon.M2.vrmac.s0" => "__builtin_HEXAGON_M2_vrmac_s0", + "llvm.hexagon.M2.vrmpy.s0" => "__builtin_HEXAGON_M2_vrmpy_s0", + "llvm.hexagon.M2.xor.xacc" => "__builtin_HEXAGON_M2_xor_xacc", + "llvm.hexagon.M4.and.and" => "__builtin_HEXAGON_M4_and_and", + "llvm.hexagon.M4.and.andn" => "__builtin_HEXAGON_M4_and_andn", + "llvm.hexagon.M4.and.or" => "__builtin_HEXAGON_M4_and_or", + "llvm.hexagon.M4.and.xor" => "__builtin_HEXAGON_M4_and_xor", + "llvm.hexagon.M4.cmpyi.wh" => "__builtin_HEXAGON_M4_cmpyi_wh", + "llvm.hexagon.M4.cmpyi.whc" => "__builtin_HEXAGON_M4_cmpyi_whc", + "llvm.hexagon.M4.cmpyr.wh" => "__builtin_HEXAGON_M4_cmpyr_wh", + "llvm.hexagon.M4.cmpyr.whc" => "__builtin_HEXAGON_M4_cmpyr_whc", + "llvm.hexagon.M4.mac.up.s1.sat" => "__builtin_HEXAGON_M4_mac_up_s1_sat", + "llvm.hexagon.M4.mpyri.addi" => "__builtin_HEXAGON_M4_mpyri_addi", + "llvm.hexagon.M4.mpyri.addr" => "__builtin_HEXAGON_M4_mpyri_addr", + "llvm.hexagon.M4.mpyri.addr.u2" => "__builtin_HEXAGON_M4_mpyri_addr_u2", + "llvm.hexagon.M4.mpyrr.addi" => "__builtin_HEXAGON_M4_mpyrr_addi", + "llvm.hexagon.M4.mpyrr.addr" => "__builtin_HEXAGON_M4_mpyrr_addr", + "llvm.hexagon.M4.nac.up.s1.sat" => "__builtin_HEXAGON_M4_nac_up_s1_sat", + "llvm.hexagon.M4.or.and" => "__builtin_HEXAGON_M4_or_and", + "llvm.hexagon.M4.or.andn" => "__builtin_HEXAGON_M4_or_andn", + "llvm.hexagon.M4.or.or" => "__builtin_HEXAGON_M4_or_or", + "llvm.hexagon.M4.or.xor" => "__builtin_HEXAGON_M4_or_xor", + "llvm.hexagon.M4.pmpyw" => "__builtin_HEXAGON_M4_pmpyw", + "llvm.hexagon.M4.pmpyw.acc" => "__builtin_HEXAGON_M4_pmpyw_acc", + "llvm.hexagon.M4.vpmpyh" => "__builtin_HEXAGON_M4_vpmpyh", + "llvm.hexagon.M4.vpmpyh.acc" => "__builtin_HEXAGON_M4_vpmpyh_acc", + "llvm.hexagon.M4.vrmpyeh.acc.s0" => "__builtin_HEXAGON_M4_vrmpyeh_acc_s0", + "llvm.hexagon.M4.vrmpyeh.acc.s1" => "__builtin_HEXAGON_M4_vrmpyeh_acc_s1", + "llvm.hexagon.M4.vrmpyeh.s0" => "__builtin_HEXAGON_M4_vrmpyeh_s0", + "llvm.hexagon.M4.vrmpyeh.s1" => "__builtin_HEXAGON_M4_vrmpyeh_s1", + "llvm.hexagon.M4.vrmpyoh.acc.s0" => "__builtin_HEXAGON_M4_vrmpyoh_acc_s0", + "llvm.hexagon.M4.vrmpyoh.acc.s1" => "__builtin_HEXAGON_M4_vrmpyoh_acc_s1", + "llvm.hexagon.M4.vrmpyoh.s0" => "__builtin_HEXAGON_M4_vrmpyoh_s0", + "llvm.hexagon.M4.vrmpyoh.s1" => "__builtin_HEXAGON_M4_vrmpyoh_s1", + "llvm.hexagon.M4.xor.and" => "__builtin_HEXAGON_M4_xor_and", + "llvm.hexagon.M4.xor.andn" => "__builtin_HEXAGON_M4_xor_andn", + "llvm.hexagon.M4.xor.or" => "__builtin_HEXAGON_M4_xor_or", + "llvm.hexagon.M4.xor.xacc" => "__builtin_HEXAGON_M4_xor_xacc", + "llvm.hexagon.M5.vdmacbsu" => "__builtin_HEXAGON_M5_vdmacbsu", + "llvm.hexagon.M5.vdmpybsu" => "__builtin_HEXAGON_M5_vdmpybsu", + "llvm.hexagon.M5.vmacbsu" => "__builtin_HEXAGON_M5_vmacbsu", + "llvm.hexagon.M5.vmacbuu" => "__builtin_HEXAGON_M5_vmacbuu", + "llvm.hexagon.M5.vmpybsu" => "__builtin_HEXAGON_M5_vmpybsu", + "llvm.hexagon.M5.vmpybuu" => "__builtin_HEXAGON_M5_vmpybuu", + "llvm.hexagon.M5.vrmacbsu" => "__builtin_HEXAGON_M5_vrmacbsu", + "llvm.hexagon.M5.vrmacbuu" => "__builtin_HEXAGON_M5_vrmacbuu", + "llvm.hexagon.M5.vrmpybsu" => "__builtin_HEXAGON_M5_vrmpybsu", + "llvm.hexagon.M5.vrmpybuu" => "__builtin_HEXAGON_M5_vrmpybuu", + "llvm.hexagon.S2.addasl.rrri" => "__builtin_HEXAGON_S2_addasl_rrri", + "llvm.hexagon.S2.asl.i.p" => "__builtin_HEXAGON_S2_asl_i_p", + "llvm.hexagon.S2.asl.i.p.acc" => "__builtin_HEXAGON_S2_asl_i_p_acc", + "llvm.hexagon.S2.asl.i.p.and" => "__builtin_HEXAGON_S2_asl_i_p_and", + "llvm.hexagon.S2.asl.i.p.nac" => "__builtin_HEXAGON_S2_asl_i_p_nac", + "llvm.hexagon.S2.asl.i.p.or" => "__builtin_HEXAGON_S2_asl_i_p_or", + "llvm.hexagon.S2.asl.i.p.xacc" => "__builtin_HEXAGON_S2_asl_i_p_xacc", + "llvm.hexagon.S2.asl.i.r" => "__builtin_HEXAGON_S2_asl_i_r", + "llvm.hexagon.S2.asl.i.r.acc" => "__builtin_HEXAGON_S2_asl_i_r_acc", + "llvm.hexagon.S2.asl.i.r.and" => "__builtin_HEXAGON_S2_asl_i_r_and", + "llvm.hexagon.S2.asl.i.r.nac" => "__builtin_HEXAGON_S2_asl_i_r_nac", + "llvm.hexagon.S2.asl.i.r.or" => "__builtin_HEXAGON_S2_asl_i_r_or", + "llvm.hexagon.S2.asl.i.r.sat" => "__builtin_HEXAGON_S2_asl_i_r_sat", + "llvm.hexagon.S2.asl.i.r.xacc" => "__builtin_HEXAGON_S2_asl_i_r_xacc", + "llvm.hexagon.S2.asl.i.vh" => "__builtin_HEXAGON_S2_asl_i_vh", + "llvm.hexagon.S2.asl.i.vw" => "__builtin_HEXAGON_S2_asl_i_vw", + "llvm.hexagon.S2.asl.r.p" => "__builtin_HEXAGON_S2_asl_r_p", + "llvm.hexagon.S2.asl.r.p.acc" => "__builtin_HEXAGON_S2_asl_r_p_acc", + "llvm.hexagon.S2.asl.r.p.and" => "__builtin_HEXAGON_S2_asl_r_p_and", + "llvm.hexagon.S2.asl.r.p.nac" => "__builtin_HEXAGON_S2_asl_r_p_nac", + "llvm.hexagon.S2.asl.r.p.or" => "__builtin_HEXAGON_S2_asl_r_p_or", + "llvm.hexagon.S2.asl.r.p.xor" => "__builtin_HEXAGON_S2_asl_r_p_xor", + "llvm.hexagon.S2.asl.r.r" => "__builtin_HEXAGON_S2_asl_r_r", + "llvm.hexagon.S2.asl.r.r.acc" => "__builtin_HEXAGON_S2_asl_r_r_acc", + "llvm.hexagon.S2.asl.r.r.and" => "__builtin_HEXAGON_S2_asl_r_r_and", + "llvm.hexagon.S2.asl.r.r.nac" => "__builtin_HEXAGON_S2_asl_r_r_nac", + "llvm.hexagon.S2.asl.r.r.or" => "__builtin_HEXAGON_S2_asl_r_r_or", + "llvm.hexagon.S2.asl.r.r.sat" => "__builtin_HEXAGON_S2_asl_r_r_sat", + "llvm.hexagon.S2.asl.r.vh" => "__builtin_HEXAGON_S2_asl_r_vh", + "llvm.hexagon.S2.asl.r.vw" => "__builtin_HEXAGON_S2_asl_r_vw", + "llvm.hexagon.S2.asr.i.p" => "__builtin_HEXAGON_S2_asr_i_p", + "llvm.hexagon.S2.asr.i.p.acc" => "__builtin_HEXAGON_S2_asr_i_p_acc", + "llvm.hexagon.S2.asr.i.p.and" => "__builtin_HEXAGON_S2_asr_i_p_and", + "llvm.hexagon.S2.asr.i.p.nac" => "__builtin_HEXAGON_S2_asr_i_p_nac", + "llvm.hexagon.S2.asr.i.p.or" => "__builtin_HEXAGON_S2_asr_i_p_or", + "llvm.hexagon.S2.asr.i.p.rnd" => "__builtin_HEXAGON_S2_asr_i_p_rnd", + "llvm.hexagon.S2.asr.i.p.rnd.goodsyntax" => "__builtin_HEXAGON_S2_asr_i_p_rnd_goodsyntax", + "llvm.hexagon.S2.asr.i.r" => "__builtin_HEXAGON_S2_asr_i_r", + "llvm.hexagon.S2.asr.i.r.acc" => "__builtin_HEXAGON_S2_asr_i_r_acc", + "llvm.hexagon.S2.asr.i.r.and" => "__builtin_HEXAGON_S2_asr_i_r_and", + "llvm.hexagon.S2.asr.i.r.nac" => "__builtin_HEXAGON_S2_asr_i_r_nac", + "llvm.hexagon.S2.asr.i.r.or" => "__builtin_HEXAGON_S2_asr_i_r_or", + "llvm.hexagon.S2.asr.i.r.rnd" => "__builtin_HEXAGON_S2_asr_i_r_rnd", + "llvm.hexagon.S2.asr.i.r.rnd.goodsyntax" => "__builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax", + "llvm.hexagon.S2.asr.i.svw.trun" => "__builtin_HEXAGON_S2_asr_i_svw_trun", + "llvm.hexagon.S2.asr.i.vh" => "__builtin_HEXAGON_S2_asr_i_vh", + "llvm.hexagon.S2.asr.i.vw" => "__builtin_HEXAGON_S2_asr_i_vw", + "llvm.hexagon.S2.asr.r.p" => "__builtin_HEXAGON_S2_asr_r_p", + "llvm.hexagon.S2.asr.r.p.acc" => "__builtin_HEXAGON_S2_asr_r_p_acc", + "llvm.hexagon.S2.asr.r.p.and" => "__builtin_HEXAGON_S2_asr_r_p_and", + "llvm.hexagon.S2.asr.r.p.nac" => "__builtin_HEXAGON_S2_asr_r_p_nac", + "llvm.hexagon.S2.asr.r.p.or" => "__builtin_HEXAGON_S2_asr_r_p_or", + "llvm.hexagon.S2.asr.r.p.xor" => "__builtin_HEXAGON_S2_asr_r_p_xor", + "llvm.hexagon.S2.asr.r.r" => "__builtin_HEXAGON_S2_asr_r_r", + "llvm.hexagon.S2.asr.r.r.acc" => "__builtin_HEXAGON_S2_asr_r_r_acc", + "llvm.hexagon.S2.asr.r.r.and" => "__builtin_HEXAGON_S2_asr_r_r_and", + "llvm.hexagon.S2.asr.r.r.nac" => "__builtin_HEXAGON_S2_asr_r_r_nac", + "llvm.hexagon.S2.asr.r.r.or" => "__builtin_HEXAGON_S2_asr_r_r_or", + "llvm.hexagon.S2.asr.r.r.sat" => "__builtin_HEXAGON_S2_asr_r_r_sat", + "llvm.hexagon.S2.asr.r.svw.trun" => "__builtin_HEXAGON_S2_asr_r_svw_trun", + "llvm.hexagon.S2.asr.r.vh" => "__builtin_HEXAGON_S2_asr_r_vh", + "llvm.hexagon.S2.asr.r.vw" => "__builtin_HEXAGON_S2_asr_r_vw", + "llvm.hexagon.S2.brev" => "__builtin_HEXAGON_S2_brev", + "llvm.hexagon.S2.brevp" => "__builtin_HEXAGON_S2_brevp", + "llvm.hexagon.S2.cl0" => "__builtin_HEXAGON_S2_cl0", + "llvm.hexagon.S2.cl0p" => "__builtin_HEXAGON_S2_cl0p", + "llvm.hexagon.S2.cl1" => "__builtin_HEXAGON_S2_cl1", + "llvm.hexagon.S2.cl1p" => "__builtin_HEXAGON_S2_cl1p", + "llvm.hexagon.S2.clb" => "__builtin_HEXAGON_S2_clb", + "llvm.hexagon.S2.clbnorm" => "__builtin_HEXAGON_S2_clbnorm", + "llvm.hexagon.S2.clbp" => "__builtin_HEXAGON_S2_clbp", + "llvm.hexagon.S2.clrbit.i" => "__builtin_HEXAGON_S2_clrbit_i", + "llvm.hexagon.S2.clrbit.r" => "__builtin_HEXAGON_S2_clrbit_r", + "llvm.hexagon.S2.ct0" => "__builtin_HEXAGON_S2_ct0", + "llvm.hexagon.S2.ct0p" => "__builtin_HEXAGON_S2_ct0p", + "llvm.hexagon.S2.ct1" => "__builtin_HEXAGON_S2_ct1", + "llvm.hexagon.S2.ct1p" => "__builtin_HEXAGON_S2_ct1p", + "llvm.hexagon.S2.deinterleave" => "__builtin_HEXAGON_S2_deinterleave", + "llvm.hexagon.S2.extractu" => "__builtin_HEXAGON_S2_extractu", + "llvm.hexagon.S2.extractu.rp" => "__builtin_HEXAGON_S2_extractu_rp", + "llvm.hexagon.S2.extractup" => "__builtin_HEXAGON_S2_extractup", + "llvm.hexagon.S2.extractup.rp" => "__builtin_HEXAGON_S2_extractup_rp", + "llvm.hexagon.S2.insert" => "__builtin_HEXAGON_S2_insert", + "llvm.hexagon.S2.insert.rp" => "__builtin_HEXAGON_S2_insert_rp", + "llvm.hexagon.S2.insertp" => "__builtin_HEXAGON_S2_insertp", + "llvm.hexagon.S2.insertp.rp" => "__builtin_HEXAGON_S2_insertp_rp", + "llvm.hexagon.S2.interleave" => "__builtin_HEXAGON_S2_interleave", + "llvm.hexagon.S2.lfsp" => "__builtin_HEXAGON_S2_lfsp", + "llvm.hexagon.S2.lsl.r.p" => "__builtin_HEXAGON_S2_lsl_r_p", + "llvm.hexagon.S2.lsl.r.p.acc" => "__builtin_HEXAGON_S2_lsl_r_p_acc", + "llvm.hexagon.S2.lsl.r.p.and" => "__builtin_HEXAGON_S2_lsl_r_p_and", + "llvm.hexagon.S2.lsl.r.p.nac" => "__builtin_HEXAGON_S2_lsl_r_p_nac", + "llvm.hexagon.S2.lsl.r.p.or" => "__builtin_HEXAGON_S2_lsl_r_p_or", + "llvm.hexagon.S2.lsl.r.p.xor" => "__builtin_HEXAGON_S2_lsl_r_p_xor", + "llvm.hexagon.S2.lsl.r.r" => "__builtin_HEXAGON_S2_lsl_r_r", + "llvm.hexagon.S2.lsl.r.r.acc" => "__builtin_HEXAGON_S2_lsl_r_r_acc", + "llvm.hexagon.S2.lsl.r.r.and" => "__builtin_HEXAGON_S2_lsl_r_r_and", + "llvm.hexagon.S2.lsl.r.r.nac" => "__builtin_HEXAGON_S2_lsl_r_r_nac", + "llvm.hexagon.S2.lsl.r.r.or" => "__builtin_HEXAGON_S2_lsl_r_r_or", + "llvm.hexagon.S2.lsl.r.vh" => "__builtin_HEXAGON_S2_lsl_r_vh", + "llvm.hexagon.S2.lsl.r.vw" => "__builtin_HEXAGON_S2_lsl_r_vw", + "llvm.hexagon.S2.lsr.i.p" => "__builtin_HEXAGON_S2_lsr_i_p", + "llvm.hexagon.S2.lsr.i.p.acc" => "__builtin_HEXAGON_S2_lsr_i_p_acc", + "llvm.hexagon.S2.lsr.i.p.and" => "__builtin_HEXAGON_S2_lsr_i_p_and", + "llvm.hexagon.S2.lsr.i.p.nac" => "__builtin_HEXAGON_S2_lsr_i_p_nac", + "llvm.hexagon.S2.lsr.i.p.or" => "__builtin_HEXAGON_S2_lsr_i_p_or", + "llvm.hexagon.S2.lsr.i.p.xacc" => "__builtin_HEXAGON_S2_lsr_i_p_xacc", + "llvm.hexagon.S2.lsr.i.r" => "__builtin_HEXAGON_S2_lsr_i_r", + "llvm.hexagon.S2.lsr.i.r.acc" => "__builtin_HEXAGON_S2_lsr_i_r_acc", + "llvm.hexagon.S2.lsr.i.r.and" => "__builtin_HEXAGON_S2_lsr_i_r_and", + "llvm.hexagon.S2.lsr.i.r.nac" => "__builtin_HEXAGON_S2_lsr_i_r_nac", + "llvm.hexagon.S2.lsr.i.r.or" => "__builtin_HEXAGON_S2_lsr_i_r_or", + "llvm.hexagon.S2.lsr.i.r.xacc" => "__builtin_HEXAGON_S2_lsr_i_r_xacc", + "llvm.hexagon.S2.lsr.i.vh" => "__builtin_HEXAGON_S2_lsr_i_vh", + "llvm.hexagon.S2.lsr.i.vw" => "__builtin_HEXAGON_S2_lsr_i_vw", + "llvm.hexagon.S2.lsr.r.p" => "__builtin_HEXAGON_S2_lsr_r_p", + "llvm.hexagon.S2.lsr.r.p.acc" => "__builtin_HEXAGON_S2_lsr_r_p_acc", + "llvm.hexagon.S2.lsr.r.p.and" => "__builtin_HEXAGON_S2_lsr_r_p_and", + "llvm.hexagon.S2.lsr.r.p.nac" => "__builtin_HEXAGON_S2_lsr_r_p_nac", + "llvm.hexagon.S2.lsr.r.p.or" => "__builtin_HEXAGON_S2_lsr_r_p_or", + "llvm.hexagon.S2.lsr.r.p.xor" => "__builtin_HEXAGON_S2_lsr_r_p_xor", + "llvm.hexagon.S2.lsr.r.r" => "__builtin_HEXAGON_S2_lsr_r_r", + "llvm.hexagon.S2.lsr.r.r.acc" => "__builtin_HEXAGON_S2_lsr_r_r_acc", + "llvm.hexagon.S2.lsr.r.r.and" => "__builtin_HEXAGON_S2_lsr_r_r_and", + "llvm.hexagon.S2.lsr.r.r.nac" => "__builtin_HEXAGON_S2_lsr_r_r_nac", + "llvm.hexagon.S2.lsr.r.r.or" => "__builtin_HEXAGON_S2_lsr_r_r_or", + "llvm.hexagon.S2.lsr.r.vh" => "__builtin_HEXAGON_S2_lsr_r_vh", + "llvm.hexagon.S2.lsr.r.vw" => "__builtin_HEXAGON_S2_lsr_r_vw", + "llvm.hexagon.S2.packhl" => "__builtin_HEXAGON_S2_packhl", + "llvm.hexagon.S2.parityp" => "__builtin_HEXAGON_S2_parityp", + "llvm.hexagon.S2.setbit.i" => "__builtin_HEXAGON_S2_setbit_i", + "llvm.hexagon.S2.setbit.r" => "__builtin_HEXAGON_S2_setbit_r", + "llvm.hexagon.S2.shuffeb" => "__builtin_HEXAGON_S2_shuffeb", + "llvm.hexagon.S2.shuffeh" => "__builtin_HEXAGON_S2_shuffeh", + "llvm.hexagon.S2.shuffob" => "__builtin_HEXAGON_S2_shuffob", + "llvm.hexagon.S2.shuffoh" => "__builtin_HEXAGON_S2_shuffoh", + "llvm.hexagon.S2.svsathb" => "__builtin_HEXAGON_S2_svsathb", + "llvm.hexagon.S2.svsathub" => "__builtin_HEXAGON_S2_svsathub", + "llvm.hexagon.S2.tableidxb.goodsyntax" => "__builtin_HEXAGON_S2_tableidxb_goodsyntax", + "llvm.hexagon.S2.tableidxd.goodsyntax" => "__builtin_HEXAGON_S2_tableidxd_goodsyntax", + "llvm.hexagon.S2.tableidxh.goodsyntax" => "__builtin_HEXAGON_S2_tableidxh_goodsyntax", + "llvm.hexagon.S2.tableidxw.goodsyntax" => "__builtin_HEXAGON_S2_tableidxw_goodsyntax", + "llvm.hexagon.S2.togglebit.i" => "__builtin_HEXAGON_S2_togglebit_i", + "llvm.hexagon.S2.togglebit.r" => "__builtin_HEXAGON_S2_togglebit_r", + "llvm.hexagon.S2.tstbit.i" => "__builtin_HEXAGON_S2_tstbit_i", + "llvm.hexagon.S2.tstbit.r" => "__builtin_HEXAGON_S2_tstbit_r", + "llvm.hexagon.S2.valignib" => "__builtin_HEXAGON_S2_valignib", + "llvm.hexagon.S2.valignrb" => "__builtin_HEXAGON_S2_valignrb", + "llvm.hexagon.S2.vcnegh" => "__builtin_HEXAGON_S2_vcnegh", + "llvm.hexagon.S2.vcrotate" => "__builtin_HEXAGON_S2_vcrotate", + "llvm.hexagon.S2.vrcnegh" => "__builtin_HEXAGON_S2_vrcnegh", + "llvm.hexagon.S2.vrndpackwh" => "__builtin_HEXAGON_S2_vrndpackwh", + "llvm.hexagon.S2.vrndpackwhs" => "__builtin_HEXAGON_S2_vrndpackwhs", + "llvm.hexagon.S2.vsathb" => "__builtin_HEXAGON_S2_vsathb", + "llvm.hexagon.S2.vsathb.nopack" => "__builtin_HEXAGON_S2_vsathb_nopack", + "llvm.hexagon.S2.vsathub" => "__builtin_HEXAGON_S2_vsathub", + "llvm.hexagon.S2.vsathub.nopack" => "__builtin_HEXAGON_S2_vsathub_nopack", + "llvm.hexagon.S2.vsatwh" => "__builtin_HEXAGON_S2_vsatwh", + "llvm.hexagon.S2.vsatwh.nopack" => "__builtin_HEXAGON_S2_vsatwh_nopack", + "llvm.hexagon.S2.vsatwuh" => "__builtin_HEXAGON_S2_vsatwuh", + "llvm.hexagon.S2.vsatwuh.nopack" => "__builtin_HEXAGON_S2_vsatwuh_nopack", + "llvm.hexagon.S2.vsplatrb" => "__builtin_HEXAGON_S2_vsplatrb", + "llvm.hexagon.S2.vsplatrh" => "__builtin_HEXAGON_S2_vsplatrh", + "llvm.hexagon.S2.vspliceib" => "__builtin_HEXAGON_S2_vspliceib", + "llvm.hexagon.S2.vsplicerb" => "__builtin_HEXAGON_S2_vsplicerb", + "llvm.hexagon.S2.vsxtbh" => "__builtin_HEXAGON_S2_vsxtbh", + "llvm.hexagon.S2.vsxthw" => "__builtin_HEXAGON_S2_vsxthw", + "llvm.hexagon.S2.vtrunehb" => "__builtin_HEXAGON_S2_vtrunehb", + "llvm.hexagon.S2.vtrunewh" => "__builtin_HEXAGON_S2_vtrunewh", + "llvm.hexagon.S2.vtrunohb" => "__builtin_HEXAGON_S2_vtrunohb", + "llvm.hexagon.S2.vtrunowh" => "__builtin_HEXAGON_S2_vtrunowh", + "llvm.hexagon.S2.vzxtbh" => "__builtin_HEXAGON_S2_vzxtbh", + "llvm.hexagon.S2.vzxthw" => "__builtin_HEXAGON_S2_vzxthw", + "llvm.hexagon.S4.addaddi" => "__builtin_HEXAGON_S4_addaddi", + "llvm.hexagon.S4.addi.asl.ri" => "__builtin_HEXAGON_S4_addi_asl_ri", + "llvm.hexagon.S4.addi.lsr.ri" => "__builtin_HEXAGON_S4_addi_lsr_ri", + "llvm.hexagon.S4.andi.asl.ri" => "__builtin_HEXAGON_S4_andi_asl_ri", + "llvm.hexagon.S4.andi.lsr.ri" => "__builtin_HEXAGON_S4_andi_lsr_ri", + "llvm.hexagon.S4.clbaddi" => "__builtin_HEXAGON_S4_clbaddi", + "llvm.hexagon.S4.clbpaddi" => "__builtin_HEXAGON_S4_clbpaddi", + "llvm.hexagon.S4.clbpnorm" => "__builtin_HEXAGON_S4_clbpnorm", + "llvm.hexagon.S4.extract" => "__builtin_HEXAGON_S4_extract", + "llvm.hexagon.S4.extract.rp" => "__builtin_HEXAGON_S4_extract_rp", + "llvm.hexagon.S4.extractp" => "__builtin_HEXAGON_S4_extractp", + "llvm.hexagon.S4.extractp.rp" => "__builtin_HEXAGON_S4_extractp_rp", + "llvm.hexagon.S4.lsli" => "__builtin_HEXAGON_S4_lsli", + "llvm.hexagon.S4.ntstbit.i" => "__builtin_HEXAGON_S4_ntstbit_i", + "llvm.hexagon.S4.ntstbit.r" => "__builtin_HEXAGON_S4_ntstbit_r", + "llvm.hexagon.S4.or.andi" => "__builtin_HEXAGON_S4_or_andi", + "llvm.hexagon.S4.or.andix" => "__builtin_HEXAGON_S4_or_andix", + "llvm.hexagon.S4.or.ori" => "__builtin_HEXAGON_S4_or_ori", + "llvm.hexagon.S4.ori.asl.ri" => "__builtin_HEXAGON_S4_ori_asl_ri", + "llvm.hexagon.S4.ori.lsr.ri" => "__builtin_HEXAGON_S4_ori_lsr_ri", + "llvm.hexagon.S4.parity" => "__builtin_HEXAGON_S4_parity", + "llvm.hexagon.S4.subaddi" => "__builtin_HEXAGON_S4_subaddi", + "llvm.hexagon.S4.subi.asl.ri" => "__builtin_HEXAGON_S4_subi_asl_ri", + "llvm.hexagon.S4.subi.lsr.ri" => "__builtin_HEXAGON_S4_subi_lsr_ri", + "llvm.hexagon.S4.vrcrotate" => "__builtin_HEXAGON_S4_vrcrotate", + "llvm.hexagon.S4.vrcrotate.acc" => "__builtin_HEXAGON_S4_vrcrotate_acc", + "llvm.hexagon.S4.vxaddsubh" => "__builtin_HEXAGON_S4_vxaddsubh", + "llvm.hexagon.S4.vxaddsubhr" => "__builtin_HEXAGON_S4_vxaddsubhr", + "llvm.hexagon.S4.vxaddsubw" => "__builtin_HEXAGON_S4_vxaddsubw", + "llvm.hexagon.S4.vxsubaddh" => "__builtin_HEXAGON_S4_vxsubaddh", + "llvm.hexagon.S4.vxsubaddhr" => "__builtin_HEXAGON_S4_vxsubaddhr", + "llvm.hexagon.S4.vxsubaddw" => "__builtin_HEXAGON_S4_vxsubaddw", + "llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax" => "__builtin_HEXAGON_S5_asrhub_rnd_sat_goodsyntax", + "llvm.hexagon.S5.asrhub.sat" => "__builtin_HEXAGON_S5_asrhub_sat", + "llvm.hexagon.S5.popcountp" => "__builtin_HEXAGON_S5_popcountp", + "llvm.hexagon.S5.vasrhrnd.goodsyntax" => "__builtin_HEXAGON_S5_vasrhrnd_goodsyntax", + "llvm.hexagon.SI.to.SXTHI.asrh" => "__builtin_SI_to_SXTHI_asrh", + "llvm.hexagon.circ.ldd" => "__builtin_circ_ldd", + // aarch64 + "llvm.aarch64.dmb" => "__builtin_arm_dmb", + "llvm.aarch64.dsb" => "__builtin_arm_dsb", + "llvm.aarch64.isb" => "__builtin_arm_isb", + // nvvm + "llvm.nvvm.abs.i" => "__nvvm_abs_i", + "llvm.nvvm.abs.ll" => "__nvvm_abs_ll", + "llvm.nvvm.add.rm.d" => "__nvvm_add_rm_d", + "llvm.nvvm.add.rm.f" => "__nvvm_add_rm_f", + "llvm.nvvm.add.rm.ftz.f" => "__nvvm_add_rm_ftz_f", + "llvm.nvvm.add.rn.d" => "__nvvm_add_rn_d", + "llvm.nvvm.add.rn.f" => "__nvvm_add_rn_f", + "llvm.nvvm.add.rn.ftz.f" => "__nvvm_add_rn_ftz_f", + "llvm.nvvm.add.rp.d" => "__nvvm_add_rp_d", + "llvm.nvvm.add.rp.f" => "__nvvm_add_rp_f", + "llvm.nvvm.add.rp.ftz.f" => "__nvvm_add_rp_ftz_f", + "llvm.nvvm.add.rz.d" => "__nvvm_add_rz_d", + "llvm.nvvm.add.rz.f" => "__nvvm_add_rz_f", + "llvm.nvvm.add.rz.ftz.f" => "__nvvm_add_rz_ftz_f", + "llvm.nvvm.barrier0" => "__nvvm_bar0", + "llvm.nvvm.barrier0.and" => "__nvvm_bar0_and", + "llvm.nvvm.barrier0.or" => "__nvvm_bar0_or", + "llvm.nvvm.barrier0.popc" => "__nvvm_bar0_popc", + "llvm.nvvm.bitcast.d2ll" => "__nvvm_bitcast_d2ll", + "llvm.nvvm.bitcast.f2i" => "__nvvm_bitcast_f2i", + "llvm.nvvm.bitcast.i2f" => "__nvvm_bitcast_i2f", + "llvm.nvvm.bitcast.ll2d" => "__nvvm_bitcast_ll2d", + "llvm.nvvm.brev32" => "__nvvm_brev32", + "llvm.nvvm.brev64" => "__nvvm_brev64", + "llvm.nvvm.ceil.d" => "__nvvm_ceil_d", + "llvm.nvvm.ceil.f" => "__nvvm_ceil_f", + "llvm.nvvm.ceil.ftz.f" => "__nvvm_ceil_ftz_f", + "llvm.nvvm.clz.i" => "__nvvm_clz_i", + "llvm.nvvm.clz.ll" => "__nvvm_clz_ll", + "llvm.nvvm.cos.approx.f" => "__nvvm_cos_approx_f", + "llvm.nvvm.cos.approx.ftz.f" => "__nvvm_cos_approx_ftz_f", + "llvm.nvvm.d2f.rm" => "__nvvm_d2f_rm", + "llvm.nvvm.d2f.rm.ftz" => "__nvvm_d2f_rm_ftz", + "llvm.nvvm.d2f.rn" => "__nvvm_d2f_rn", + "llvm.nvvm.d2f.rn.ftz" => "__nvvm_d2f_rn_ftz", + "llvm.nvvm.d2f.rp" => "__nvvm_d2f_rp", + "llvm.nvvm.d2f.rp.ftz" => "__nvvm_d2f_rp_ftz", + "llvm.nvvm.d2f.rz" => "__nvvm_d2f_rz", + "llvm.nvvm.d2f.rz.ftz" => "__nvvm_d2f_rz_ftz", + "llvm.nvvm.d2i.hi" => "__nvvm_d2i_hi", + "llvm.nvvm.d2i.lo" => "__nvvm_d2i_lo", + "llvm.nvvm.d2i.rm" => "__nvvm_d2i_rm", + "llvm.nvvm.d2i.rn" => "__nvvm_d2i_rn", + "llvm.nvvm.d2i.rp" => "__nvvm_d2i_rp", + "llvm.nvvm.d2i.rz" => "__nvvm_d2i_rz", + "llvm.nvvm.d2ll.rm" => "__nvvm_d2ll_rm", + "llvm.nvvm.d2ll.rn" => "__nvvm_d2ll_rn", + "llvm.nvvm.d2ll.rp" => "__nvvm_d2ll_rp", + "llvm.nvvm.d2ll.rz" => "__nvvm_d2ll_rz", + "llvm.nvvm.d2ui.rm" => "__nvvm_d2ui_rm", + "llvm.nvvm.d2ui.rn" => "__nvvm_d2ui_rn", + "llvm.nvvm.d2ui.rp" => "__nvvm_d2ui_rp", + "llvm.nvvm.d2ui.rz" => "__nvvm_d2ui_rz", + "llvm.nvvm.d2ull.rm" => "__nvvm_d2ull_rm", + "llvm.nvvm.d2ull.rn" => "__nvvm_d2ull_rn", + "llvm.nvvm.d2ull.rp" => "__nvvm_d2ull_rp", + "llvm.nvvm.d2ull.rz" => "__nvvm_d2ull_rz", + "llvm.nvvm.div.approx.f" => "__nvvm_div_approx_f", + "llvm.nvvm.div.approx.ftz.f" => "__nvvm_div_approx_ftz_f", + "llvm.nvvm.div.rm.d" => "__nvvm_div_rm_d", + "llvm.nvvm.div.rm.f" => "__nvvm_div_rm_f", + "llvm.nvvm.div.rm.ftz.f" => "__nvvm_div_rm_ftz_f", + "llvm.nvvm.div.rn.d" => "__nvvm_div_rn_d", + "llvm.nvvm.div.rn.f" => "__nvvm_div_rn_f", + "llvm.nvvm.div.rn.ftz.f" => "__nvvm_div_rn_ftz_f", + "llvm.nvvm.div.rp.d" => "__nvvm_div_rp_d", + "llvm.nvvm.div.rp.f" => "__nvvm_div_rp_f", + "llvm.nvvm.div.rp.ftz.f" => "__nvvm_div_rp_ftz_f", + "llvm.nvvm.div.rz.d" => "__nvvm_div_rz_d", + "llvm.nvvm.div.rz.f" => "__nvvm_div_rz_f", + "llvm.nvvm.div.rz.ftz.f" => "__nvvm_div_rz_ftz_f", + "llvm.nvvm.ex2.approx.d" => "__nvvm_ex2_approx_d", + "llvm.nvvm.ex2.approx.f" => "__nvvm_ex2_approx_f", + "llvm.nvvm.ex2.approx.ftz.f" => "__nvvm_ex2_approx_ftz_f", + "llvm.nvvm.f2h.rn" => "__nvvm_f2h_rn", + "llvm.nvvm.f2h.rn.ftz" => "__nvvm_f2h_rn_ftz", + "llvm.nvvm.f2i.rm" => "__nvvm_f2i_rm", + "llvm.nvvm.f2i.rm.ftz" => "__nvvm_f2i_rm_ftz", + "llvm.nvvm.f2i.rn" => "__nvvm_f2i_rn", + "llvm.nvvm.f2i.rn.ftz" => "__nvvm_f2i_rn_ftz", + "llvm.nvvm.f2i.rp" => "__nvvm_f2i_rp", + "llvm.nvvm.f2i.rp.ftz" => "__nvvm_f2i_rp_ftz", + "llvm.nvvm.f2i.rz" => "__nvvm_f2i_rz", + "llvm.nvvm.f2i.rz.ftz" => "__nvvm_f2i_rz_ftz", + "llvm.nvvm.f2ll.rm" => "__nvvm_f2ll_rm", + "llvm.nvvm.f2ll.rm.ftz" => "__nvvm_f2ll_rm_ftz", + "llvm.nvvm.f2ll.rn" => "__nvvm_f2ll_rn", + "llvm.nvvm.f2ll.rn.ftz" => "__nvvm_f2ll_rn_ftz", + "llvm.nvvm.f2ll.rp" => "__nvvm_f2ll_rp", + "llvm.nvvm.f2ll.rp.ftz" => "__nvvm_f2ll_rp_ftz", + "llvm.nvvm.f2ll.rz" => "__nvvm_f2ll_rz", + "llvm.nvvm.f2ll.rz.ftz" => "__nvvm_f2ll_rz_ftz", + "llvm.nvvm.f2ui.rm" => "__nvvm_f2ui_rm", + "llvm.nvvm.f2ui.rm.ftz" => "__nvvm_f2ui_rm_ftz", + "llvm.nvvm.f2ui.rn" => "__nvvm_f2ui_rn", + "llvm.nvvm.f2ui.rn.ftz" => "__nvvm_f2ui_rn_ftz", + "llvm.nvvm.f2ui.rp" => "__nvvm_f2ui_rp", + "llvm.nvvm.f2ui.rp.ftz" => "__nvvm_f2ui_rp_ftz", + "llvm.nvvm.f2ui.rz" => "__nvvm_f2ui_rz", + "llvm.nvvm.f2ui.rz.ftz" => "__nvvm_f2ui_rz_ftz", + "llvm.nvvm.f2ull.rm" => "__nvvm_f2ull_rm", + "llvm.nvvm.f2ull.rm.ftz" => "__nvvm_f2ull_rm_ftz", + "llvm.nvvm.f2ull.rn" => "__nvvm_f2ull_rn", + "llvm.nvvm.f2ull.rn.ftz" => "__nvvm_f2ull_rn_ftz", + "llvm.nvvm.f2ull.rp" => "__nvvm_f2ull_rp", + "llvm.nvvm.f2ull.rp.ftz" => "__nvvm_f2ull_rp_ftz", + "llvm.nvvm.f2ull.rz" => "__nvvm_f2ull_rz", + "llvm.nvvm.f2ull.rz.ftz" => "__nvvm_f2ull_rz_ftz", + "llvm.nvvm.fabs.d" => "__nvvm_fabs_d", + "llvm.nvvm.fabs.f" => "__nvvm_fabs_f", + "llvm.nvvm.fabs.ftz.f" => "__nvvm_fabs_ftz_f", + "llvm.nvvm.floor.d" => "__nvvm_floor_d", + "llvm.nvvm.floor.f" => "__nvvm_floor_f", + "llvm.nvvm.floor.ftz.f" => "__nvvm_floor_ftz_f", + "llvm.nvvm.fma.rm.d" => "__nvvm_fma_rm_d", + "llvm.nvvm.fma.rm.f" => "__nvvm_fma_rm_f", + "llvm.nvvm.fma.rm.ftz.f" => "__nvvm_fma_rm_ftz_f", + "llvm.nvvm.fma.rn.d" => "__nvvm_fma_rn_d", + "llvm.nvvm.fma.rn.f" => "__nvvm_fma_rn_f", + "llvm.nvvm.fma.rn.ftz.f" => "__nvvm_fma_rn_ftz_f", + "llvm.nvvm.fma.rp.d" => "__nvvm_fma_rp_d", + "llvm.nvvm.fma.rp.f" => "__nvvm_fma_rp_f", + "llvm.nvvm.fma.rp.ftz.f" => "__nvvm_fma_rp_ftz_f", + "llvm.nvvm.fma.rz.d" => "__nvvm_fma_rz_d", + "llvm.nvvm.fma.rz.f" => "__nvvm_fma_rz_f", + "llvm.nvvm.fma.rz.ftz.f" => "__nvvm_fma_rz_ftz_f", + "llvm.nvvm.fmax.d" => "__nvvm_fmax_d", + "llvm.nvvm.fmax.f" => "__nvvm_fmax_f", + "llvm.nvvm.fmax.ftz.f" => "__nvvm_fmax_ftz_f", + "llvm.nvvm.fmin.d" => "__nvvm_fmin_d", + "llvm.nvvm.fmin.f" => "__nvvm_fmin_f", + "llvm.nvvm.fmin.ftz.f" => "__nvvm_fmin_ftz_f", + "llvm.nvvm.h2f" => "__nvvm_h2f", + "llvm.nvvm.i2d.rm" => "__nvvm_i2d_rm", + "llvm.nvvm.i2d.rn" => "__nvvm_i2d_rn", + "llvm.nvvm.i2d.rp" => "__nvvm_i2d_rp", + "llvm.nvvm.i2d.rz" => "__nvvm_i2d_rz", + "llvm.nvvm.i2f.rm" => "__nvvm_i2f_rm", + "llvm.nvvm.i2f.rn" => "__nvvm_i2f_rn", + "llvm.nvvm.i2f.rp" => "__nvvm_i2f_rp", + "llvm.nvvm.i2f.rz" => "__nvvm_i2f_rz", + "llvm.nvvm.isspacep.const" => "__nvvm_isspacep_const", + "llvm.nvvm.isspacep.global" => "__nvvm_isspacep_global", + "llvm.nvvm.isspacep.local" => "__nvvm_isspacep_local", + "llvm.nvvm.isspacep.shared" => "__nvvm_isspacep_shared", + "llvm.nvvm.istypep.sampler" => "__nvvm_istypep_sampler", + "llvm.nvvm.istypep.surface" => "__nvvm_istypep_surface", + "llvm.nvvm.istypep.texture" => "__nvvm_istypep_texture", + "llvm.nvvm.lg2.approx.d" => "__nvvm_lg2_approx_d", + "llvm.nvvm.lg2.approx.f" => "__nvvm_lg2_approx_f", + "llvm.nvvm.lg2.approx.ftz.f" => "__nvvm_lg2_approx_ftz_f", + "llvm.nvvm.ll2d.rm" => "__nvvm_ll2d_rm", + "llvm.nvvm.ll2d.rn" => "__nvvm_ll2d_rn", + "llvm.nvvm.ll2d.rp" => "__nvvm_ll2d_rp", + "llvm.nvvm.ll2d.rz" => "__nvvm_ll2d_rz", + "llvm.nvvm.ll2f.rm" => "__nvvm_ll2f_rm", + "llvm.nvvm.ll2f.rn" => "__nvvm_ll2f_rn", + "llvm.nvvm.ll2f.rp" => "__nvvm_ll2f_rp", + "llvm.nvvm.ll2f.rz" => "__nvvm_ll2f_rz", + "llvm.nvvm.lohi.i2d" => "__nvvm_lohi_i2d", + "llvm.nvvm.max.i" => "__nvvm_max_i", + "llvm.nvvm.max.ll" => "__nvvm_max_ll", + "llvm.nvvm.max.ui" => "__nvvm_max_ui", + "llvm.nvvm.max.ull" => "__nvvm_max_ull", + "llvm.nvvm.membar.cta" => "__nvvm_membar_cta", + "llvm.nvvm.membar.gl" => "__nvvm_membar_gl", + "llvm.nvvm.membar.sys" => "__nvvm_membar_sys", + "llvm.nvvm.min.i" => "__nvvm_min_i", + "llvm.nvvm.min.ll" => "__nvvm_min_ll", + "llvm.nvvm.min.ui" => "__nvvm_min_ui", + "llvm.nvvm.min.ull" => "__nvvm_min_ull", + "llvm.nvvm.mul.rm.d" => "__nvvm_mul_rm_d", + "llvm.nvvm.mul.rm.f" => "__nvvm_mul_rm_f", + "llvm.nvvm.mul.rm.ftz.f" => "__nvvm_mul_rm_ftz_f", + "llvm.nvvm.mul.rn.d" => "__nvvm_mul_rn_d", + "llvm.nvvm.mul.rn.f" => "__nvvm_mul_rn_f", + "llvm.nvvm.mul.rn.ftz.f" => "__nvvm_mul_rn_ftz_f", + "llvm.nvvm.mul.rp.d" => "__nvvm_mul_rp_d", + "llvm.nvvm.mul.rp.f" => "__nvvm_mul_rp_f", + "llvm.nvvm.mul.rp.ftz.f" => "__nvvm_mul_rp_ftz_f", + "llvm.nvvm.mul.rz.d" => "__nvvm_mul_rz_d", + "llvm.nvvm.mul.rz.f" => "__nvvm_mul_rz_f", + "llvm.nvvm.mul.rz.ftz.f" => "__nvvm_mul_rz_ftz_f", + "llvm.nvvm.mul24.i" => "__nvvm_mul24_i", + "llvm.nvvm.mul24.ui" => "__nvvm_mul24_ui", + "llvm.nvvm.mulhi.i" => "__nvvm_mulhi_i", + "llvm.nvvm.mulhi.ll" => "__nvvm_mulhi_ll", + "llvm.nvvm.mulhi.ui" => "__nvvm_mulhi_ui", + "llvm.nvvm.mulhi.ull" => "__nvvm_mulhi_ull", + "llvm.nvvm.popc.i" => "__nvvm_popc_i", + "llvm.nvvm.popc.ll" => "__nvvm_popc_ll", + "llvm.nvvm.prmt" => "__nvvm_prmt", + "llvm.nvvm.rcp.approx.ftz.d" => "__nvvm_rcp_approx_ftz_d", + "llvm.nvvm.rcp.rm.d" => "__nvvm_rcp_rm_d", + "llvm.nvvm.rcp.rm.f" => "__nvvm_rcp_rm_f", + "llvm.nvvm.rcp.rm.ftz.f" => "__nvvm_rcp_rm_ftz_f", + "llvm.nvvm.rcp.rn.d" => "__nvvm_rcp_rn_d", + "llvm.nvvm.rcp.rn.f" => "__nvvm_rcp_rn_f", + "llvm.nvvm.rcp.rn.ftz.f" => "__nvvm_rcp_rn_ftz_f", + "llvm.nvvm.rcp.rp.d" => "__nvvm_rcp_rp_d", + "llvm.nvvm.rcp.rp.f" => "__nvvm_rcp_rp_f", + "llvm.nvvm.rcp.rp.ftz.f" => "__nvvm_rcp_rp_ftz_f", + "llvm.nvvm.rcp.rz.d" => "__nvvm_rcp_rz_d", + "llvm.nvvm.rcp.rz.f" => "__nvvm_rcp_rz_f", + "llvm.nvvm.rcp.rz.ftz.f" => "__nvvm_rcp_rz_ftz_f", + "llvm.nvvm.read.ptx.sreg.ctaid.x" => "__nvvm_read_ptx_sreg_ctaid_x", + "llvm.nvvm.read.ptx.sreg.ctaid.y" => "__nvvm_read_ptx_sreg_ctaid_y", + "llvm.nvvm.read.ptx.sreg.ctaid.z" => "__nvvm_read_ptx_sreg_ctaid_z", + "llvm.nvvm.read.ptx.sreg.envreg0" => "__nvvm_read_ptx_sreg_envreg0", + "llvm.nvvm.read.ptx.sreg.envreg1" => "__nvvm_read_ptx_sreg_envreg1", + "llvm.nvvm.read.ptx.sreg.envreg10" => "__nvvm_read_ptx_sreg_envreg10", + "llvm.nvvm.read.ptx.sreg.envreg11" => "__nvvm_read_ptx_sreg_envreg11", + "llvm.nvvm.read.ptx.sreg.envreg12" => "__nvvm_read_ptx_sreg_envreg12", + "llvm.nvvm.read.ptx.sreg.envreg13" => "__nvvm_read_ptx_sreg_envreg13", + "llvm.nvvm.read.ptx.sreg.envreg14" => "__nvvm_read_ptx_sreg_envreg14", + "llvm.nvvm.read.ptx.sreg.envreg15" => "__nvvm_read_ptx_sreg_envreg15", + "llvm.nvvm.read.ptx.sreg.envreg16" => "__nvvm_read_ptx_sreg_envreg16", + "llvm.nvvm.read.ptx.sreg.envreg17" => "__nvvm_read_ptx_sreg_envreg17", + "llvm.nvvm.read.ptx.sreg.envreg18" => "__nvvm_read_ptx_sreg_envreg18", + "llvm.nvvm.read.ptx.sreg.envreg19" => "__nvvm_read_ptx_sreg_envreg19", + "llvm.nvvm.read.ptx.sreg.envreg2" => "__nvvm_read_ptx_sreg_envreg2", + "llvm.nvvm.read.ptx.sreg.envreg20" => "__nvvm_read_ptx_sreg_envreg20", + "llvm.nvvm.read.ptx.sreg.envreg21" => "__nvvm_read_ptx_sreg_envreg21", + "llvm.nvvm.read.ptx.sreg.envreg22" => "__nvvm_read_ptx_sreg_envreg22", + "llvm.nvvm.read.ptx.sreg.envreg23" => "__nvvm_read_ptx_sreg_envreg23", + "llvm.nvvm.read.ptx.sreg.envreg24" => "__nvvm_read_ptx_sreg_envreg24", + "llvm.nvvm.read.ptx.sreg.envreg25" => "__nvvm_read_ptx_sreg_envreg25", + "llvm.nvvm.read.ptx.sreg.envreg26" => "__nvvm_read_ptx_sreg_envreg26", + "llvm.nvvm.read.ptx.sreg.envreg27" => "__nvvm_read_ptx_sreg_envreg27", + "llvm.nvvm.read.ptx.sreg.envreg28" => "__nvvm_read_ptx_sreg_envreg28", + "llvm.nvvm.read.ptx.sreg.envreg29" => "__nvvm_read_ptx_sreg_envreg29", + "llvm.nvvm.read.ptx.sreg.envreg3" => "__nvvm_read_ptx_sreg_envreg3", + "llvm.nvvm.read.ptx.sreg.envreg30" => "__nvvm_read_ptx_sreg_envreg30", + "llvm.nvvm.read.ptx.sreg.envreg31" => "__nvvm_read_ptx_sreg_envreg31", + "llvm.nvvm.read.ptx.sreg.envreg4" => "__nvvm_read_ptx_sreg_envreg4", + "llvm.nvvm.read.ptx.sreg.envreg5" => "__nvvm_read_ptx_sreg_envreg5", + "llvm.nvvm.read.ptx.sreg.envreg6" => "__nvvm_read_ptx_sreg_envreg6", + "llvm.nvvm.read.ptx.sreg.envreg7" => "__nvvm_read_ptx_sreg_envreg7", + "llvm.nvvm.read.ptx.sreg.envreg8" => "__nvvm_read_ptx_sreg_envreg8", + "llvm.nvvm.read.ptx.sreg.envreg9" => "__nvvm_read_ptx_sreg_envreg9", + "llvm.nvvm.read.ptx.sreg.nctaid.x" => "__nvvm_read_ptx_sreg_nctaid_x", + "llvm.nvvm.read.ptx.sreg.nctaid.y" => "__nvvm_read_ptx_sreg_nctaid_y", + "llvm.nvvm.read.ptx.sreg.nctaid.z" => "__nvvm_read_ptx_sreg_nctaid_z", + "llvm.nvvm.read.ptx.sreg.ntid.x" => "__nvvm_read_ptx_sreg_ntid_x", + "llvm.nvvm.read.ptx.sreg.ntid.y" => "__nvvm_read_ptx_sreg_ntid_y", + "llvm.nvvm.read.ptx.sreg.ntid.z" => "__nvvm_read_ptx_sreg_ntid_z", + "llvm.nvvm.read.ptx.sreg.tid.x" => "__nvvm_read_ptx_sreg_tid_x", + "llvm.nvvm.read.ptx.sreg.tid.y" => "__nvvm_read_ptx_sreg_tid_y", + "llvm.nvvm.read.ptx.sreg.tid.z" => "__nvvm_read_ptx_sreg_tid_z", + "llvm.nvvm.read.ptx.sreg.warpsize" => "__nvvm_read_ptx_sreg_warpsize", + "llvm.nvvm.rotate.b32" => "__nvvm_rotate_b32", + "llvm.nvvm.rotate.b64" => "__nvvm_rotate_b64", + "llvm.nvvm.rotate.right.b64" => "__nvvm_rotate_right_b64", + "llvm.nvvm.round.d" => "__nvvm_round_d", + "llvm.nvvm.round.f" => "__nvvm_round_f", + "llvm.nvvm.round.ftz.f" => "__nvvm_round_ftz_f", + "llvm.nvvm.rsqrt.approx.d" => "__nvvm_rsqrt_approx_d", + "llvm.nvvm.rsqrt.approx.f" => "__nvvm_rsqrt_approx_f", + "llvm.nvvm.rsqrt.approx.ftz.f" => "__nvvm_rsqrt_approx_ftz_f", + "llvm.nvvm.sad.i" => "__nvvm_sad_i", + "llvm.nvvm.sad.ui" => "__nvvm_sad_ui", + "llvm.nvvm.saturate.d" => "__nvvm_saturate_d", + "llvm.nvvm.saturate.f" => "__nvvm_saturate_f", + "llvm.nvvm.saturate.ftz.f" => "__nvvm_saturate_ftz_f", + "llvm.nvvm.sin.approx.f" => "__nvvm_sin_approx_f", + "llvm.nvvm.sin.approx.ftz.f" => "__nvvm_sin_approx_ftz_f", + "llvm.nvvm.sqrt.approx.f" => "__nvvm_sqrt_approx_f", + "llvm.nvvm.sqrt.approx.ftz.f" => "__nvvm_sqrt_approx_ftz_f", + "llvm.nvvm.sqrt.f" => "__nvvm_sqrt_f", + "llvm.nvvm.sqrt.rm.d" => "__nvvm_sqrt_rm_d", + "llvm.nvvm.sqrt.rm.f" => "__nvvm_sqrt_rm_f", + "llvm.nvvm.sqrt.rm.ftz.f" => "__nvvm_sqrt_rm_ftz_f", + "llvm.nvvm.sqrt.rn.d" => "__nvvm_sqrt_rn_d", + "llvm.nvvm.sqrt.rn.f" => "__nvvm_sqrt_rn_f", + "llvm.nvvm.sqrt.rn.ftz.f" => "__nvvm_sqrt_rn_ftz_f", + "llvm.nvvm.sqrt.rp.d" => "__nvvm_sqrt_rp_d", + "llvm.nvvm.sqrt.rp.f" => "__nvvm_sqrt_rp_f", + "llvm.nvvm.sqrt.rp.ftz.f" => "__nvvm_sqrt_rp_ftz_f", + "llvm.nvvm.sqrt.rz.d" => "__nvvm_sqrt_rz_d", + "llvm.nvvm.sqrt.rz.f" => "__nvvm_sqrt_rz_f", + "llvm.nvvm.sqrt.rz.ftz.f" => "__nvvm_sqrt_rz_ftz_f", + "llvm.nvvm.suq.array.size" => "__nvvm_suq_array_size", + "llvm.nvvm.suq.channel.data.type" => "__nvvm_suq_channel_data_type", + "llvm.nvvm.suq.channel.order" => "__nvvm_suq_channel_order", + "llvm.nvvm.suq.depth" => "__nvvm_suq_depth", + "llvm.nvvm.suq.height" => "__nvvm_suq_height", + "llvm.nvvm.suq.width" => "__nvvm_suq_width", + "llvm.nvvm.sust.b.1d.array.i16.clamp" => "__nvvm_sust_b_1d_array_i16_clamp", + "llvm.nvvm.sust.b.1d.array.i16.trap" => "__nvvm_sust_b_1d_array_i16_trap", + "llvm.nvvm.sust.b.1d.array.i16.zero" => "__nvvm_sust_b_1d_array_i16_zero", + "llvm.nvvm.sust.b.1d.array.i32.clamp" => "__nvvm_sust_b_1d_array_i32_clamp", + "llvm.nvvm.sust.b.1d.array.i32.trap" => "__nvvm_sust_b_1d_array_i32_trap", + "llvm.nvvm.sust.b.1d.array.i32.zero" => "__nvvm_sust_b_1d_array_i32_zero", + "llvm.nvvm.sust.b.1d.array.i64.clamp" => "__nvvm_sust_b_1d_array_i64_clamp", + "llvm.nvvm.sust.b.1d.array.i64.trap" => "__nvvm_sust_b_1d_array_i64_trap", + "llvm.nvvm.sust.b.1d.array.i64.zero" => "__nvvm_sust_b_1d_array_i64_zero", + "llvm.nvvm.sust.b.1d.array.i8.clamp" => "__nvvm_sust_b_1d_array_i8_clamp", + "llvm.nvvm.sust.b.1d.array.i8.trap" => "__nvvm_sust_b_1d_array_i8_trap", + "llvm.nvvm.sust.b.1d.array.i8.zero" => "__nvvm_sust_b_1d_array_i8_zero", + "llvm.nvvm.sust.b.1d.array.v2i16.clamp" => "__nvvm_sust_b_1d_array_v2i16_clamp", + "llvm.nvvm.sust.b.1d.array.v2i16.trap" => "__nvvm_sust_b_1d_array_v2i16_trap", + "llvm.nvvm.sust.b.1d.array.v2i16.zero" => "__nvvm_sust_b_1d_array_v2i16_zero", + "llvm.nvvm.sust.b.1d.array.v2i32.clamp" => "__nvvm_sust_b_1d_array_v2i32_clamp", + "llvm.nvvm.sust.b.1d.array.v2i32.trap" => "__nvvm_sust_b_1d_array_v2i32_trap", + "llvm.nvvm.sust.b.1d.array.v2i32.zero" => "__nvvm_sust_b_1d_array_v2i32_zero", + "llvm.nvvm.sust.b.1d.array.v2i64.clamp" => "__nvvm_sust_b_1d_array_v2i64_clamp", + "llvm.nvvm.sust.b.1d.array.v2i64.trap" => "__nvvm_sust_b_1d_array_v2i64_trap", + "llvm.nvvm.sust.b.1d.array.v2i64.zero" => "__nvvm_sust_b_1d_array_v2i64_zero", + "llvm.nvvm.sust.b.1d.array.v2i8.clamp" => "__nvvm_sust_b_1d_array_v2i8_clamp", + "llvm.nvvm.sust.b.1d.array.v2i8.trap" => "__nvvm_sust_b_1d_array_v2i8_trap", + "llvm.nvvm.sust.b.1d.array.v2i8.zero" => "__nvvm_sust_b_1d_array_v2i8_zero", + "llvm.nvvm.sust.b.1d.array.v4i16.clamp" => "__nvvm_sust_b_1d_array_v4i16_clamp", + "llvm.nvvm.sust.b.1d.array.v4i16.trap" => "__nvvm_sust_b_1d_array_v4i16_trap", + "llvm.nvvm.sust.b.1d.array.v4i16.zero" => "__nvvm_sust_b_1d_array_v4i16_zero", + "llvm.nvvm.sust.b.1d.array.v4i32.clamp" => "__nvvm_sust_b_1d_array_v4i32_clamp", + "llvm.nvvm.sust.b.1d.array.v4i32.trap" => "__nvvm_sust_b_1d_array_v4i32_trap", + "llvm.nvvm.sust.b.1d.array.v4i32.zero" => "__nvvm_sust_b_1d_array_v4i32_zero", + "llvm.nvvm.sust.b.1d.array.v4i8.clamp" => "__nvvm_sust_b_1d_array_v4i8_clamp", + "llvm.nvvm.sust.b.1d.array.v4i8.trap" => "__nvvm_sust_b_1d_array_v4i8_trap", + "llvm.nvvm.sust.b.1d.array.v4i8.zero" => "__nvvm_sust_b_1d_array_v4i8_zero", + "llvm.nvvm.sust.b.1d.i16.clamp" => "__nvvm_sust_b_1d_i16_clamp", + "llvm.nvvm.sust.b.1d.i16.trap" => "__nvvm_sust_b_1d_i16_trap", + "llvm.nvvm.sust.b.1d.i16.zero" => "__nvvm_sust_b_1d_i16_zero", + "llvm.nvvm.sust.b.1d.i32.clamp" => "__nvvm_sust_b_1d_i32_clamp", + "llvm.nvvm.sust.b.1d.i32.trap" => "__nvvm_sust_b_1d_i32_trap", + "llvm.nvvm.sust.b.1d.i32.zero" => "__nvvm_sust_b_1d_i32_zero", + "llvm.nvvm.sust.b.1d.i64.clamp" => "__nvvm_sust_b_1d_i64_clamp", + "llvm.nvvm.sust.b.1d.i64.trap" => "__nvvm_sust_b_1d_i64_trap", + "llvm.nvvm.sust.b.1d.i64.zero" => "__nvvm_sust_b_1d_i64_zero", + "llvm.nvvm.sust.b.1d.i8.clamp" => "__nvvm_sust_b_1d_i8_clamp", + "llvm.nvvm.sust.b.1d.i8.trap" => "__nvvm_sust_b_1d_i8_trap", + "llvm.nvvm.sust.b.1d.i8.zero" => "__nvvm_sust_b_1d_i8_zero", + "llvm.nvvm.sust.b.1d.v2i16.clamp" => "__nvvm_sust_b_1d_v2i16_clamp", + "llvm.nvvm.sust.b.1d.v2i16.trap" => "__nvvm_sust_b_1d_v2i16_trap", + "llvm.nvvm.sust.b.1d.v2i16.zero" => "__nvvm_sust_b_1d_v2i16_zero", + "llvm.nvvm.sust.b.1d.v2i32.clamp" => "__nvvm_sust_b_1d_v2i32_clamp", + "llvm.nvvm.sust.b.1d.v2i32.trap" => "__nvvm_sust_b_1d_v2i32_trap", + "llvm.nvvm.sust.b.1d.v2i32.zero" => "__nvvm_sust_b_1d_v2i32_zero", + "llvm.nvvm.sust.b.1d.v2i64.clamp" => "__nvvm_sust_b_1d_v2i64_clamp", + "llvm.nvvm.sust.b.1d.v2i64.trap" => "__nvvm_sust_b_1d_v2i64_trap", + "llvm.nvvm.sust.b.1d.v2i64.zero" => "__nvvm_sust_b_1d_v2i64_zero", + "llvm.nvvm.sust.b.1d.v2i8.clamp" => "__nvvm_sust_b_1d_v2i8_clamp", + "llvm.nvvm.sust.b.1d.v2i8.trap" => "__nvvm_sust_b_1d_v2i8_trap", + "llvm.nvvm.sust.b.1d.v2i8.zero" => "__nvvm_sust_b_1d_v2i8_zero", + "llvm.nvvm.sust.b.1d.v4i16.clamp" => "__nvvm_sust_b_1d_v4i16_clamp", + "llvm.nvvm.sust.b.1d.v4i16.trap" => "__nvvm_sust_b_1d_v4i16_trap", + "llvm.nvvm.sust.b.1d.v4i16.zero" => "__nvvm_sust_b_1d_v4i16_zero", + "llvm.nvvm.sust.b.1d.v4i32.clamp" => "__nvvm_sust_b_1d_v4i32_clamp", + "llvm.nvvm.sust.b.1d.v4i32.trap" => "__nvvm_sust_b_1d_v4i32_trap", + "llvm.nvvm.sust.b.1d.v4i32.zero" => "__nvvm_sust_b_1d_v4i32_zero", + "llvm.nvvm.sust.b.1d.v4i8.clamp" => "__nvvm_sust_b_1d_v4i8_clamp", + "llvm.nvvm.sust.b.1d.v4i8.trap" => "__nvvm_sust_b_1d_v4i8_trap", + "llvm.nvvm.sust.b.1d.v4i8.zero" => "__nvvm_sust_b_1d_v4i8_zero", + "llvm.nvvm.sust.b.2d.array.i16.clamp" => "__nvvm_sust_b_2d_array_i16_clamp", + "llvm.nvvm.sust.b.2d.array.i16.trap" => "__nvvm_sust_b_2d_array_i16_trap", + "llvm.nvvm.sust.b.2d.array.i16.zero" => "__nvvm_sust_b_2d_array_i16_zero", + "llvm.nvvm.sust.b.2d.array.i32.clamp" => "__nvvm_sust_b_2d_array_i32_clamp", + "llvm.nvvm.sust.b.2d.array.i32.trap" => "__nvvm_sust_b_2d_array_i32_trap", + "llvm.nvvm.sust.b.2d.array.i32.zero" => "__nvvm_sust_b_2d_array_i32_zero", + "llvm.nvvm.sust.b.2d.array.i64.clamp" => "__nvvm_sust_b_2d_array_i64_clamp", + "llvm.nvvm.sust.b.2d.array.i64.trap" => "__nvvm_sust_b_2d_array_i64_trap", + "llvm.nvvm.sust.b.2d.array.i64.zero" => "__nvvm_sust_b_2d_array_i64_zero", + "llvm.nvvm.sust.b.2d.array.i8.clamp" => "__nvvm_sust_b_2d_array_i8_clamp", + "llvm.nvvm.sust.b.2d.array.i8.trap" => "__nvvm_sust_b_2d_array_i8_trap", + "llvm.nvvm.sust.b.2d.array.i8.zero" => "__nvvm_sust_b_2d_array_i8_zero", + "llvm.nvvm.sust.b.2d.array.v2i16.clamp" => "__nvvm_sust_b_2d_array_v2i16_clamp", + "llvm.nvvm.sust.b.2d.array.v2i16.trap" => "__nvvm_sust_b_2d_array_v2i16_trap", + "llvm.nvvm.sust.b.2d.array.v2i16.zero" => "__nvvm_sust_b_2d_array_v2i16_zero", + "llvm.nvvm.sust.b.2d.array.v2i32.clamp" => "__nvvm_sust_b_2d_array_v2i32_clamp", + "llvm.nvvm.sust.b.2d.array.v2i32.trap" => "__nvvm_sust_b_2d_array_v2i32_trap", + "llvm.nvvm.sust.b.2d.array.v2i32.zero" => "__nvvm_sust_b_2d_array_v2i32_zero", + "llvm.nvvm.sust.b.2d.array.v2i64.clamp" => "__nvvm_sust_b_2d_array_v2i64_clamp", + "llvm.nvvm.sust.b.2d.array.v2i64.trap" => "__nvvm_sust_b_2d_array_v2i64_trap", + "llvm.nvvm.sust.b.2d.array.v2i64.zero" => "__nvvm_sust_b_2d_array_v2i64_zero", + "llvm.nvvm.sust.b.2d.array.v2i8.clamp" => "__nvvm_sust_b_2d_array_v2i8_clamp", + "llvm.nvvm.sust.b.2d.array.v2i8.trap" => "__nvvm_sust_b_2d_array_v2i8_trap", + "llvm.nvvm.sust.b.2d.array.v2i8.zero" => "__nvvm_sust_b_2d_array_v2i8_zero", + "llvm.nvvm.sust.b.2d.array.v4i16.clamp" => "__nvvm_sust_b_2d_array_v4i16_clamp", + "llvm.nvvm.sust.b.2d.array.v4i16.trap" => "__nvvm_sust_b_2d_array_v4i16_trap", + "llvm.nvvm.sust.b.2d.array.v4i16.zero" => "__nvvm_sust_b_2d_array_v4i16_zero", + "llvm.nvvm.sust.b.2d.array.v4i32.clamp" => "__nvvm_sust_b_2d_array_v4i32_clamp", + "llvm.nvvm.sust.b.2d.array.v4i32.trap" => "__nvvm_sust_b_2d_array_v4i32_trap", + "llvm.nvvm.sust.b.2d.array.v4i32.zero" => "__nvvm_sust_b_2d_array_v4i32_zero", + "llvm.nvvm.sust.b.2d.array.v4i8.clamp" => "__nvvm_sust_b_2d_array_v4i8_clamp", + "llvm.nvvm.sust.b.2d.array.v4i8.trap" => "__nvvm_sust_b_2d_array_v4i8_trap", + "llvm.nvvm.sust.b.2d.array.v4i8.zero" => "__nvvm_sust_b_2d_array_v4i8_zero", + "llvm.nvvm.sust.b.2d.i16.clamp" => "__nvvm_sust_b_2d_i16_clamp", + "llvm.nvvm.sust.b.2d.i16.trap" => "__nvvm_sust_b_2d_i16_trap", + "llvm.nvvm.sust.b.2d.i16.zero" => "__nvvm_sust_b_2d_i16_zero", + "llvm.nvvm.sust.b.2d.i32.clamp" => "__nvvm_sust_b_2d_i32_clamp", + "llvm.nvvm.sust.b.2d.i32.trap" => "__nvvm_sust_b_2d_i32_trap", + "llvm.nvvm.sust.b.2d.i32.zero" => "__nvvm_sust_b_2d_i32_zero", + "llvm.nvvm.sust.b.2d.i64.clamp" => "__nvvm_sust_b_2d_i64_clamp", + "llvm.nvvm.sust.b.2d.i64.trap" => "__nvvm_sust_b_2d_i64_trap", + "llvm.nvvm.sust.b.2d.i64.zero" => "__nvvm_sust_b_2d_i64_zero", + "llvm.nvvm.sust.b.2d.i8.clamp" => "__nvvm_sust_b_2d_i8_clamp", + "llvm.nvvm.sust.b.2d.i8.trap" => "__nvvm_sust_b_2d_i8_trap", + "llvm.nvvm.sust.b.2d.i8.zero" => "__nvvm_sust_b_2d_i8_zero", + "llvm.nvvm.sust.b.2d.v2i16.clamp" => "__nvvm_sust_b_2d_v2i16_clamp", + "llvm.nvvm.sust.b.2d.v2i16.trap" => "__nvvm_sust_b_2d_v2i16_trap", + "llvm.nvvm.sust.b.2d.v2i16.zero" => "__nvvm_sust_b_2d_v2i16_zero", + "llvm.nvvm.sust.b.2d.v2i32.clamp" => "__nvvm_sust_b_2d_v2i32_clamp", + "llvm.nvvm.sust.b.2d.v2i32.trap" => "__nvvm_sust_b_2d_v2i32_trap", + "llvm.nvvm.sust.b.2d.v2i32.zero" => "__nvvm_sust_b_2d_v2i32_zero", + "llvm.nvvm.sust.b.2d.v2i64.clamp" => "__nvvm_sust_b_2d_v2i64_clamp", + "llvm.nvvm.sust.b.2d.v2i64.trap" => "__nvvm_sust_b_2d_v2i64_trap", + "llvm.nvvm.sust.b.2d.v2i64.zero" => "__nvvm_sust_b_2d_v2i64_zero", + "llvm.nvvm.sust.b.2d.v2i8.clamp" => "__nvvm_sust_b_2d_v2i8_clamp", + "llvm.nvvm.sust.b.2d.v2i8.trap" => "__nvvm_sust_b_2d_v2i8_trap", + "llvm.nvvm.sust.b.2d.v2i8.zero" => "__nvvm_sust_b_2d_v2i8_zero", + "llvm.nvvm.sust.b.2d.v4i16.clamp" => "__nvvm_sust_b_2d_v4i16_clamp", + "llvm.nvvm.sust.b.2d.v4i16.trap" => "__nvvm_sust_b_2d_v4i16_trap", + "llvm.nvvm.sust.b.2d.v4i16.zero" => "__nvvm_sust_b_2d_v4i16_zero", + "llvm.nvvm.sust.b.2d.v4i32.clamp" => "__nvvm_sust_b_2d_v4i32_clamp", + "llvm.nvvm.sust.b.2d.v4i32.trap" => "__nvvm_sust_b_2d_v4i32_trap", + "llvm.nvvm.sust.b.2d.v4i32.zero" => "__nvvm_sust_b_2d_v4i32_zero", + "llvm.nvvm.sust.b.2d.v4i8.clamp" => "__nvvm_sust_b_2d_v4i8_clamp", + "llvm.nvvm.sust.b.2d.v4i8.trap" => "__nvvm_sust_b_2d_v4i8_trap", + "llvm.nvvm.sust.b.2d.v4i8.zero" => "__nvvm_sust_b_2d_v4i8_zero", + "llvm.nvvm.sust.b.3d.i16.clamp" => "__nvvm_sust_b_3d_i16_clamp", + "llvm.nvvm.sust.b.3d.i16.trap" => "__nvvm_sust_b_3d_i16_trap", + "llvm.nvvm.sust.b.3d.i16.zero" => "__nvvm_sust_b_3d_i16_zero", + "llvm.nvvm.sust.b.3d.i32.clamp" => "__nvvm_sust_b_3d_i32_clamp", + "llvm.nvvm.sust.b.3d.i32.trap" => "__nvvm_sust_b_3d_i32_trap", + "llvm.nvvm.sust.b.3d.i32.zero" => "__nvvm_sust_b_3d_i32_zero", + "llvm.nvvm.sust.b.3d.i64.clamp" => "__nvvm_sust_b_3d_i64_clamp", + "llvm.nvvm.sust.b.3d.i64.trap" => "__nvvm_sust_b_3d_i64_trap", + "llvm.nvvm.sust.b.3d.i64.zero" => "__nvvm_sust_b_3d_i64_zero", + "llvm.nvvm.sust.b.3d.i8.clamp" => "__nvvm_sust_b_3d_i8_clamp", + "llvm.nvvm.sust.b.3d.i8.trap" => "__nvvm_sust_b_3d_i8_trap", + "llvm.nvvm.sust.b.3d.i8.zero" => "__nvvm_sust_b_3d_i8_zero", + "llvm.nvvm.sust.b.3d.v2i16.clamp" => "__nvvm_sust_b_3d_v2i16_clamp", + "llvm.nvvm.sust.b.3d.v2i16.trap" => "__nvvm_sust_b_3d_v2i16_trap", + "llvm.nvvm.sust.b.3d.v2i16.zero" => "__nvvm_sust_b_3d_v2i16_zero", + "llvm.nvvm.sust.b.3d.v2i32.clamp" => "__nvvm_sust_b_3d_v2i32_clamp", + "llvm.nvvm.sust.b.3d.v2i32.trap" => "__nvvm_sust_b_3d_v2i32_trap", + "llvm.nvvm.sust.b.3d.v2i32.zero" => "__nvvm_sust_b_3d_v2i32_zero", + "llvm.nvvm.sust.b.3d.v2i64.clamp" => "__nvvm_sust_b_3d_v2i64_clamp", + "llvm.nvvm.sust.b.3d.v2i64.trap" => "__nvvm_sust_b_3d_v2i64_trap", + "llvm.nvvm.sust.b.3d.v2i64.zero" => "__nvvm_sust_b_3d_v2i64_zero", + "llvm.nvvm.sust.b.3d.v2i8.clamp" => "__nvvm_sust_b_3d_v2i8_clamp", + "llvm.nvvm.sust.b.3d.v2i8.trap" => "__nvvm_sust_b_3d_v2i8_trap", + "llvm.nvvm.sust.b.3d.v2i8.zero" => "__nvvm_sust_b_3d_v2i8_zero", + "llvm.nvvm.sust.b.3d.v4i16.clamp" => "__nvvm_sust_b_3d_v4i16_clamp", + "llvm.nvvm.sust.b.3d.v4i16.trap" => "__nvvm_sust_b_3d_v4i16_trap", + "llvm.nvvm.sust.b.3d.v4i16.zero" => "__nvvm_sust_b_3d_v4i16_zero", + "llvm.nvvm.sust.b.3d.v4i32.clamp" => "__nvvm_sust_b_3d_v4i32_clamp", + "llvm.nvvm.sust.b.3d.v4i32.trap" => "__nvvm_sust_b_3d_v4i32_trap", + "llvm.nvvm.sust.b.3d.v4i32.zero" => "__nvvm_sust_b_3d_v4i32_zero", + "llvm.nvvm.sust.b.3d.v4i8.clamp" => "__nvvm_sust_b_3d_v4i8_clamp", + "llvm.nvvm.sust.b.3d.v4i8.trap" => "__nvvm_sust_b_3d_v4i8_trap", + "llvm.nvvm.sust.b.3d.v4i8.zero" => "__nvvm_sust_b_3d_v4i8_zero", + "llvm.nvvm.sust.p.1d.array.i16.trap" => "__nvvm_sust_p_1d_array_i16_trap", + "llvm.nvvm.sust.p.1d.array.i32.trap" => "__nvvm_sust_p_1d_array_i32_trap", + "llvm.nvvm.sust.p.1d.array.i8.trap" => "__nvvm_sust_p_1d_array_i8_trap", + "llvm.nvvm.sust.p.1d.array.v2i16.trap" => "__nvvm_sust_p_1d_array_v2i16_trap", + "llvm.nvvm.sust.p.1d.array.v2i32.trap" => "__nvvm_sust_p_1d_array_v2i32_trap", + "llvm.nvvm.sust.p.1d.array.v2i8.trap" => "__nvvm_sust_p_1d_array_v2i8_trap", + "llvm.nvvm.sust.p.1d.array.v4i16.trap" => "__nvvm_sust_p_1d_array_v4i16_trap", + "llvm.nvvm.sust.p.1d.array.v4i32.trap" => "__nvvm_sust_p_1d_array_v4i32_trap", + "llvm.nvvm.sust.p.1d.array.v4i8.trap" => "__nvvm_sust_p_1d_array_v4i8_trap", + "llvm.nvvm.sust.p.1d.i16.trap" => "__nvvm_sust_p_1d_i16_trap", + "llvm.nvvm.sust.p.1d.i32.trap" => "__nvvm_sust_p_1d_i32_trap", + "llvm.nvvm.sust.p.1d.i8.trap" => "__nvvm_sust_p_1d_i8_trap", + "llvm.nvvm.sust.p.1d.v2i16.trap" => "__nvvm_sust_p_1d_v2i16_trap", + "llvm.nvvm.sust.p.1d.v2i32.trap" => "__nvvm_sust_p_1d_v2i32_trap", + "llvm.nvvm.sust.p.1d.v2i8.trap" => "__nvvm_sust_p_1d_v2i8_trap", + "llvm.nvvm.sust.p.1d.v4i16.trap" => "__nvvm_sust_p_1d_v4i16_trap", + "llvm.nvvm.sust.p.1d.v4i32.trap" => "__nvvm_sust_p_1d_v4i32_trap", + "llvm.nvvm.sust.p.1d.v4i8.trap" => "__nvvm_sust_p_1d_v4i8_trap", + "llvm.nvvm.sust.p.2d.array.i16.trap" => "__nvvm_sust_p_2d_array_i16_trap", + "llvm.nvvm.sust.p.2d.array.i32.trap" => "__nvvm_sust_p_2d_array_i32_trap", + "llvm.nvvm.sust.p.2d.array.i8.trap" => "__nvvm_sust_p_2d_array_i8_trap", + "llvm.nvvm.sust.p.2d.array.v2i16.trap" => "__nvvm_sust_p_2d_array_v2i16_trap", + "llvm.nvvm.sust.p.2d.array.v2i32.trap" => "__nvvm_sust_p_2d_array_v2i32_trap", + "llvm.nvvm.sust.p.2d.array.v2i8.trap" => "__nvvm_sust_p_2d_array_v2i8_trap", + "llvm.nvvm.sust.p.2d.array.v4i16.trap" => "__nvvm_sust_p_2d_array_v4i16_trap", + "llvm.nvvm.sust.p.2d.array.v4i32.trap" => "__nvvm_sust_p_2d_array_v4i32_trap", + "llvm.nvvm.sust.p.2d.array.v4i8.trap" => "__nvvm_sust_p_2d_array_v4i8_trap", + "llvm.nvvm.sust.p.2d.i16.trap" => "__nvvm_sust_p_2d_i16_trap", + "llvm.nvvm.sust.p.2d.i32.trap" => "__nvvm_sust_p_2d_i32_trap", + "llvm.nvvm.sust.p.2d.i8.trap" => "__nvvm_sust_p_2d_i8_trap", + "llvm.nvvm.sust.p.2d.v2i16.trap" => "__nvvm_sust_p_2d_v2i16_trap", + "llvm.nvvm.sust.p.2d.v2i32.trap" => "__nvvm_sust_p_2d_v2i32_trap", + "llvm.nvvm.sust.p.2d.v2i8.trap" => "__nvvm_sust_p_2d_v2i8_trap", + "llvm.nvvm.sust.p.2d.v4i16.trap" => "__nvvm_sust_p_2d_v4i16_trap", + "llvm.nvvm.sust.p.2d.v4i32.trap" => "__nvvm_sust_p_2d_v4i32_trap", + "llvm.nvvm.sust.p.2d.v4i8.trap" => "__nvvm_sust_p_2d_v4i8_trap", + "llvm.nvvm.sust.p.3d.i16.trap" => "__nvvm_sust_p_3d_i16_trap", + "llvm.nvvm.sust.p.3d.i32.trap" => "__nvvm_sust_p_3d_i32_trap", + "llvm.nvvm.sust.p.3d.i8.trap" => "__nvvm_sust_p_3d_i8_trap", + "llvm.nvvm.sust.p.3d.v2i16.trap" => "__nvvm_sust_p_3d_v2i16_trap", + "llvm.nvvm.sust.p.3d.v2i32.trap" => "__nvvm_sust_p_3d_v2i32_trap", + "llvm.nvvm.sust.p.3d.v2i8.trap" => "__nvvm_sust_p_3d_v2i8_trap", + "llvm.nvvm.sust.p.3d.v4i16.trap" => "__nvvm_sust_p_3d_v4i16_trap", + "llvm.nvvm.sust.p.3d.v4i32.trap" => "__nvvm_sust_p_3d_v4i32_trap", + "llvm.nvvm.sust.p.3d.v4i8.trap" => "__nvvm_sust_p_3d_v4i8_trap", + "llvm.nvvm.swap.lo.hi.b64" => "__nvvm_swap_lo_hi_b64", + "llvm.nvvm.trunc.d" => "__nvvm_trunc_d", + "llvm.nvvm.trunc.f" => "__nvvm_trunc_f", + "llvm.nvvm.trunc.ftz.f" => "__nvvm_trunc_ftz_f", + "llvm.nvvm.txq.array.size" => "__nvvm_txq_array_size", + "llvm.nvvm.txq.channel.data.type" => "__nvvm_txq_channel_data_type", + "llvm.nvvm.txq.channel.order" => "__nvvm_txq_channel_order", + "llvm.nvvm.txq.depth" => "__nvvm_txq_depth", + "llvm.nvvm.txq.height" => "__nvvm_txq_height", + "llvm.nvvm.txq.num.mipmap.levels" => "__nvvm_txq_num_mipmap_levels", + "llvm.nvvm.txq.num.samples" => "__nvvm_txq_num_samples", + "llvm.nvvm.txq.width" => "__nvvm_txq_width", + "llvm.nvvm.ui2d.rm" => "__nvvm_ui2d_rm", + "llvm.nvvm.ui2d.rn" => "__nvvm_ui2d_rn", + "llvm.nvvm.ui2d.rp" => "__nvvm_ui2d_rp", + "llvm.nvvm.ui2d.rz" => "__nvvm_ui2d_rz", + "llvm.nvvm.ui2f.rm" => "__nvvm_ui2f_rm", + "llvm.nvvm.ui2f.rn" => "__nvvm_ui2f_rn", + "llvm.nvvm.ui2f.rp" => "__nvvm_ui2f_rp", + "llvm.nvvm.ui2f.rz" => "__nvvm_ui2f_rz", + "llvm.nvvm.ull2d.rm" => "__nvvm_ull2d_rm", + "llvm.nvvm.ull2d.rn" => "__nvvm_ull2d_rn", + "llvm.nvvm.ull2d.rp" => "__nvvm_ull2d_rp", + "llvm.nvvm.ull2d.rz" => "__nvvm_ull2d_rz", + "llvm.nvvm.ull2f.rm" => "__nvvm_ull2f_rm", + "llvm.nvvm.ull2f.rn" => "__nvvm_ull2f_rn", + "llvm.nvvm.ull2f.rp" => "__nvvm_ull2f_rp", + "llvm.nvvm.ull2f.rz" => "__nvvm_ull2f_rz", + // arm + "llvm.arm.cdp" => "__builtin_arm_cdp", + "llvm.arm.cdp2" => "__builtin_arm_cdp2", + "llvm.arm.dmb" => "__builtin_arm_dmb", + "llvm.arm.dsb" => "__builtin_arm_dsb", + "llvm.arm.get.fpscr" => "__builtin_arm_get_fpscr", + "llvm.arm.isb" => "__builtin_arm_isb", + "llvm.arm.mcr" => "__builtin_arm_mcr", + "llvm.arm.mcr2" => "__builtin_arm_mcr2", + "llvm.arm.mcrr" => "__builtin_arm_mcrr", + "llvm.arm.mcrr2" => "__builtin_arm_mcrr2", + "llvm.arm.mrc" => "__builtin_arm_mrc", + "llvm.arm.mrc2" => "__builtin_arm_mrc2", + "llvm.arm.qadd" => "__builtin_arm_qadd", + "llvm.arm.qsub" => "__builtin_arm_qsub", + "llvm.arm.set.fpscr" => "__builtin_arm_set_fpscr", + "llvm.arm.ssat" => "__builtin_arm_ssat", + "llvm.arm.thread.pointer" => "__builtin_thread_pointer", + "llvm.arm.usat" => "__builtin_arm_usat", + // x86 + "llvm.x86.addcarry.u32" => "__builtin_ia32_addcarry_u32", + "llvm.x86.addcarry.u64" => "__builtin_ia32_addcarry_u64", + "llvm.x86.addcarryx.u32" => "__builtin_ia32_addcarryx_u32", + "llvm.x86.addcarryx.u64" => "__builtin_ia32_addcarryx_u64", + "llvm.x86.aesni.aesdec" => "__builtin_ia32_aesdec128", + "llvm.x86.aesni.aesdeclast" => "__builtin_ia32_aesdeclast128", + "llvm.x86.aesni.aesenc" => "__builtin_ia32_aesenc128", + "llvm.x86.aesni.aesenclast" => "__builtin_ia32_aesenclast128", + "llvm.x86.aesni.aesimc" => "__builtin_ia32_aesimc128", + "llvm.x86.aesni.aeskeygenassist" => "__builtin_ia32_aeskeygenassist128", + "llvm.x86.avx.addsub.pd.256" => "__builtin_ia32_addsubpd256", + "llvm.x86.avx.addsub.ps.256" => "__builtin_ia32_addsubps256", + "llvm.x86.avx.blend.pd.256" => "__builtin_ia32_blendpd256", + "llvm.x86.avx.blend.ps.256" => "__builtin_ia32_blendps256", + "llvm.x86.avx.blendv.pd.256" => "__builtin_ia32_blendvpd256", + "llvm.x86.avx.blendv.ps.256" => "__builtin_ia32_blendvps256", + "llvm.x86.avx.cmp.pd.256" => "__builtin_ia32_cmppd256", + "llvm.x86.avx.cmp.ps.256" => "__builtin_ia32_cmpps256", + "llvm.x86.avx.cvt.pd2.ps.256" => "__builtin_ia32_cvtpd2ps256", + "llvm.x86.avx.cvt.pd2dq.256" => "__builtin_ia32_cvtpd2dq256", + "llvm.x86.avx.cvt.ps2.pd.256" => "__builtin_ia32_cvtps2pd256", + "llvm.x86.avx.cvt.ps2dq.256" => "__builtin_ia32_cvtps2dq256", + "llvm.x86.avx.cvtdq2.pd.256" => "__builtin_ia32_cvtdq2pd256", + "llvm.x86.avx.cvtdq2.ps.256" => "__builtin_ia32_cvtdq2ps256", + "llvm.x86.avx.cvtt.pd2dq.256" => "__builtin_ia32_cvttpd2dq256", + "llvm.x86.avx.cvtt.ps2dq.256" => "__builtin_ia32_cvttps2dq256", + "llvm.x86.avx.dp.ps.256" => "__builtin_ia32_dpps256", + "llvm.x86.avx.hadd.pd.256" => "__builtin_ia32_haddpd256", + "llvm.x86.avx.hadd.ps.256" => "__builtin_ia32_haddps256", + "llvm.x86.avx.hsub.pd.256" => "__builtin_ia32_hsubpd256", + "llvm.x86.avx.hsub.ps.256" => "__builtin_ia32_hsubps256", + "llvm.x86.avx.ldu.dq.256" => "__builtin_ia32_lddqu256", + "llvm.x86.avx.maskload.pd" => "__builtin_ia32_maskloadpd", + "llvm.x86.avx.maskload.pd.256" => "__builtin_ia32_maskloadpd256", + "llvm.x86.avx.maskload.ps" => "__builtin_ia32_maskloadps", + "llvm.x86.avx.maskload.ps.256" => "__builtin_ia32_maskloadps256", + "llvm.x86.avx.maskstore.pd" => "__builtin_ia32_maskstorepd", + "llvm.x86.avx.maskstore.pd.256" => "__builtin_ia32_maskstorepd256", + "llvm.x86.avx.maskstore.ps" => "__builtin_ia32_maskstoreps", + "llvm.x86.avx.maskstore.ps.256" => "__builtin_ia32_maskstoreps256", + "llvm.x86.avx.max.pd.256" => "__builtin_ia32_maxpd256", + "llvm.x86.avx.max.ps.256" => "__builtin_ia32_maxps256", + "llvm.x86.avx.min.pd.256" => "__builtin_ia32_minpd256", + "llvm.x86.avx.min.ps.256" => "__builtin_ia32_minps256", + "llvm.x86.avx.movmsk.pd.256" => "__builtin_ia32_movmskpd256", + "llvm.x86.avx.movmsk.ps.256" => "__builtin_ia32_movmskps256", + "llvm.x86.avx.ptestc.256" => "__builtin_ia32_ptestc256", + "llvm.x86.avx.ptestnzc.256" => "__builtin_ia32_ptestnzc256", + "llvm.x86.avx.ptestz.256" => "__builtin_ia32_ptestz256", + "llvm.x86.avx.rcp.ps.256" => "__builtin_ia32_rcpps256", + "llvm.x86.avx.round.pd.256" => "__builtin_ia32_roundpd256", + "llvm.x86.avx.round.ps.256" => "__builtin_ia32_roundps256", + "llvm.x86.avx.rsqrt.ps.256" => "__builtin_ia32_rsqrtps256", + "llvm.x86.avx.sqrt.pd.256" => "__builtin_ia32_sqrtpd256", + "llvm.x86.avx.sqrt.ps.256" => "__builtin_ia32_sqrtps256", + "llvm.x86.avx.storeu.dq.256" => "__builtin_ia32_storedqu256", + "llvm.x86.avx.storeu.pd.256" => "__builtin_ia32_storeupd256", + "llvm.x86.avx.storeu.ps.256" => "__builtin_ia32_storeups256", + "llvm.x86.avx.vbroadcastf128.pd.256" => "__builtin_ia32_vbroadcastf128_pd256", + "llvm.x86.avx.vbroadcastf128.ps.256" => "__builtin_ia32_vbroadcastf128_ps256", + "llvm.x86.avx.vextractf128.pd.256" => "__builtin_ia32_vextractf128_pd256", + "llvm.x86.avx.vextractf128.ps.256" => "__builtin_ia32_vextractf128_ps256", + "llvm.x86.avx.vextractf128.si.256" => "__builtin_ia32_vextractf128_si256", + "llvm.x86.avx.vinsertf128.pd.256" => "__builtin_ia32_vinsertf128_pd256", + "llvm.x86.avx.vinsertf128.ps.256" => "__builtin_ia32_vinsertf128_ps256", + "llvm.x86.avx.vinsertf128.si.256" => "__builtin_ia32_vinsertf128_si256", + "llvm.x86.avx.vperm2f128.pd.256" => "__builtin_ia32_vperm2f128_pd256", + "llvm.x86.avx.vperm2f128.ps.256" => "__builtin_ia32_vperm2f128_ps256", + "llvm.x86.avx.vperm2f128.si.256" => "__builtin_ia32_vperm2f128_si256", + "llvm.x86.avx.vpermilvar.pd" => "__builtin_ia32_vpermilvarpd", + "llvm.x86.avx.vpermilvar.pd.256" => "__builtin_ia32_vpermilvarpd256", + "llvm.x86.avx.vpermilvar.ps" => "__builtin_ia32_vpermilvarps", + "llvm.x86.avx.vpermilvar.ps.256" => "__builtin_ia32_vpermilvarps256", + "llvm.x86.avx.vtestc.pd" => "__builtin_ia32_vtestcpd", + "llvm.x86.avx.vtestc.pd.256" => "__builtin_ia32_vtestcpd256", + "llvm.x86.avx.vtestc.ps" => "__builtin_ia32_vtestcps", + "llvm.x86.avx.vtestc.ps.256" => "__builtin_ia32_vtestcps256", + "llvm.x86.avx.vtestnzc.pd" => "__builtin_ia32_vtestnzcpd", + "llvm.x86.avx.vtestnzc.pd.256" => "__builtin_ia32_vtestnzcpd256", + "llvm.x86.avx.vtestnzc.ps" => "__builtin_ia32_vtestnzcps", + "llvm.x86.avx.vtestnzc.ps.256" => "__builtin_ia32_vtestnzcps256", + "llvm.x86.avx.vtestz.pd" => "__builtin_ia32_vtestzpd", + "llvm.x86.avx.vtestz.pd.256" => "__builtin_ia32_vtestzpd256", + "llvm.x86.avx.vtestz.ps" => "__builtin_ia32_vtestzps", + "llvm.x86.avx.vtestz.ps.256" => "__builtin_ia32_vtestzps256", + "llvm.x86.avx.vzeroall" => "__builtin_ia32_vzeroall", + "llvm.x86.avx.vzeroupper" => "__builtin_ia32_vzeroupper", + "llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gatherd_d", + "llvm.x86.avx2.gather.d.d.256" => "__builtin_ia32_gatherd_d256", + "llvm.x86.avx2.gather.d.pd" => "__builtin_ia32_gatherd_pd", + "llvm.x86.avx2.gather.d.pd.256" => "__builtin_ia32_gatherd_pd256", + "llvm.x86.avx2.gather.d.ps" => "__builtin_ia32_gatherd_ps", + "llvm.x86.avx2.gather.d.ps.256" => "__builtin_ia32_gatherd_ps256", + "llvm.x86.avx2.gather.d.q" => "__builtin_ia32_gatherd_q", + "llvm.x86.avx2.gather.d.q.256" => "__builtin_ia32_gatherd_q256", + "llvm.x86.avx2.gather.q.d" => "__builtin_ia32_gatherq_d", + "llvm.x86.avx2.gather.q.d.256" => "__builtin_ia32_gatherq_d256", + "llvm.x86.avx2.gather.q.pd" => "__builtin_ia32_gatherq_pd", + "llvm.x86.avx2.gather.q.pd.256" => "__builtin_ia32_gatherq_pd256", + "llvm.x86.avx2.gather.q.ps" => "__builtin_ia32_gatherq_ps", + "llvm.x86.avx2.gather.q.ps.256" => "__builtin_ia32_gatherq_ps256", + "llvm.x86.avx2.gather.q.q" => "__builtin_ia32_gatherq_q", + "llvm.x86.avx2.gather.q.q.256" => "__builtin_ia32_gatherq_q256", + "llvm.x86.avx2.maskload.d" => "__builtin_ia32_maskloadd", + "llvm.x86.avx2.maskload.d.256" => "__builtin_ia32_maskloadd256", + "llvm.x86.avx2.maskload.q" => "__builtin_ia32_maskloadq", + "llvm.x86.avx2.maskload.q.256" => "__builtin_ia32_maskloadq256", + "llvm.x86.avx2.maskstore.d" => "__builtin_ia32_maskstored", + "llvm.x86.avx2.maskstore.d.256" => "__builtin_ia32_maskstored256", + "llvm.x86.avx2.maskstore.q" => "__builtin_ia32_maskstoreq", + "llvm.x86.avx2.maskstore.q.256" => "__builtin_ia32_maskstoreq256", + "llvm.x86.avx2.movntdqa" => "__builtin_ia32_movntdqa256", + "llvm.x86.avx2.mpsadbw" => "__builtin_ia32_mpsadbw256", + "llvm.x86.avx2.pabs.b" => "__builtin_ia32_pabsb256", + "llvm.x86.avx2.pabs.d" => "__builtin_ia32_pabsd256", + "llvm.x86.avx2.pabs.w" => "__builtin_ia32_pabsw256", + "llvm.x86.avx2.packssdw" => "__builtin_ia32_packssdw256", + "llvm.x86.avx2.packsswb" => "__builtin_ia32_packsswb256", + "llvm.x86.avx2.packusdw" => "__builtin_ia32_packusdw256", + "llvm.x86.avx2.packuswb" => "__builtin_ia32_packuswb256", + "llvm.x86.avx2.padds.b" => "__builtin_ia32_paddsb256", + "llvm.x86.avx2.padds.w" => "__builtin_ia32_paddsw256", + "llvm.x86.avx2.paddus.b" => "__builtin_ia32_paddusb256", + "llvm.x86.avx2.paddus.w" => "__builtin_ia32_paddusw256", + "llvm.x86.avx2.pavg.b" => "__builtin_ia32_pavgb256", + "llvm.x86.avx2.pavg.w" => "__builtin_ia32_pavgw256", + "llvm.x86.avx2.pblendd.128" => "__builtin_ia32_pblendd128", + "llvm.x86.avx2.pblendd.256" => "__builtin_ia32_pblendd256", + "llvm.x86.avx2.pblendvb" => "__builtin_ia32_pblendvb256", + "llvm.x86.avx2.pblendw" => "__builtin_ia32_pblendw256", + "llvm.x86.avx2.pbroadcastb.128" => "__builtin_ia32_pbroadcastb128", + "llvm.x86.avx2.pbroadcastb.256" => "__builtin_ia32_pbroadcastb256", + "llvm.x86.avx2.pbroadcastd.128" => "__builtin_ia32_pbroadcastd128", + "llvm.x86.avx2.pbroadcastd.256" => "__builtin_ia32_pbroadcastd256", + "llvm.x86.avx2.pbroadcastq.128" => "__builtin_ia32_pbroadcastq128", + "llvm.x86.avx2.pbroadcastq.256" => "__builtin_ia32_pbroadcastq256", + "llvm.x86.avx2.pbroadcastw.128" => "__builtin_ia32_pbroadcastw128", + "llvm.x86.avx2.pbroadcastw.256" => "__builtin_ia32_pbroadcastw256", + "llvm.x86.avx2.permd" => "__builtin_ia32_permvarsi256", + "llvm.x86.avx2.permps" => "__builtin_ia32_permvarsf256", + "llvm.x86.avx2.phadd.d" => "__builtin_ia32_phaddd256", + "llvm.x86.avx2.phadd.sw" => "__builtin_ia32_phaddsw256", + "llvm.x86.avx2.phadd.w" => "__builtin_ia32_phaddw256", + "llvm.x86.avx2.phsub.d" => "__builtin_ia32_phsubd256", + "llvm.x86.avx2.phsub.sw" => "__builtin_ia32_phsubsw256", + "llvm.x86.avx2.phsub.w" => "__builtin_ia32_phsubw256", + "llvm.x86.avx2.pmadd.ub.sw" => "__builtin_ia32_pmaddubsw256", + "llvm.x86.avx2.pmadd.wd" => "__builtin_ia32_pmaddwd256", + "llvm.x86.avx2.pmaxs.b" => "__builtin_ia32_pmaxsb256", + "llvm.x86.avx2.pmaxs.d" => "__builtin_ia32_pmaxsd256", + "llvm.x86.avx2.pmaxs.w" => "__builtin_ia32_pmaxsw256", + "llvm.x86.avx2.pmaxu.b" => "__builtin_ia32_pmaxub256", + "llvm.x86.avx2.pmaxu.d" => "__builtin_ia32_pmaxud256", + "llvm.x86.avx2.pmaxu.w" => "__builtin_ia32_pmaxuw256", + "llvm.x86.avx2.pmins.b" => "__builtin_ia32_pminsb256", + "llvm.x86.avx2.pmins.d" => "__builtin_ia32_pminsd256", + "llvm.x86.avx2.pmins.w" => "__builtin_ia32_pminsw256", + "llvm.x86.avx2.pminu.b" => "__builtin_ia32_pminub256", + "llvm.x86.avx2.pminu.d" => "__builtin_ia32_pminud256", + "llvm.x86.avx2.pminu.w" => "__builtin_ia32_pminuw256", + "llvm.x86.avx2.pmovmskb" => "__builtin_ia32_pmovmskb256", + "llvm.x86.avx2.pmovsxbd" => "__builtin_ia32_pmovsxbd256", + "llvm.x86.avx2.pmovsxbq" => "__builtin_ia32_pmovsxbq256", + "llvm.x86.avx2.pmovsxbw" => "__builtin_ia32_pmovsxbw256", + "llvm.x86.avx2.pmovsxdq" => "__builtin_ia32_pmovsxdq256", + "llvm.x86.avx2.pmovsxwd" => "__builtin_ia32_pmovsxwd256", + "llvm.x86.avx2.pmovsxwq" => "__builtin_ia32_pmovsxwq256", + "llvm.x86.avx2.pmovzxbd" => "__builtin_ia32_pmovzxbd256", + "llvm.x86.avx2.pmovzxbq" => "__builtin_ia32_pmovzxbq256", + "llvm.x86.avx2.pmovzxbw" => "__builtin_ia32_pmovzxbw256", + "llvm.x86.avx2.pmovzxdq" => "__builtin_ia32_pmovzxdq256", + "llvm.x86.avx2.pmovzxwd" => "__builtin_ia32_pmovzxwd256", + "llvm.x86.avx2.pmovzxwq" => "__builtin_ia32_pmovzxwq256", + "llvm.x86.avx2.pmul.dq" => "__builtin_ia32_pmuldq256", + "llvm.x86.avx2.pmul.hr.sw" => "__builtin_ia32_pmulhrsw256", + "llvm.x86.avx2.pmulh.w" => "__builtin_ia32_pmulhw256", + "llvm.x86.avx2.pmulhu.w" => "__builtin_ia32_pmulhuw256", + "llvm.x86.avx2.pmulu.dq" => "__builtin_ia32_pmuludq256", + "llvm.x86.avx2.psad.bw" => "__builtin_ia32_psadbw256", + "llvm.x86.avx2.pshuf.b" => "__builtin_ia32_pshufb256", + "llvm.x86.avx2.psign.b" => "__builtin_ia32_psignb256", + "llvm.x86.avx2.psign.d" => "__builtin_ia32_psignd256", + "llvm.x86.avx2.psign.w" => "__builtin_ia32_psignw256", + "llvm.x86.avx2.psll.d" => "__builtin_ia32_pslld256", + "llvm.x86.avx2.psll.dq" => "__builtin_ia32_pslldqi256", + "llvm.x86.avx2.psll.dq.bs" => "__builtin_ia32_pslldqi256_byteshift", + "llvm.x86.avx2.psll.q" => "__builtin_ia32_psllq256", + "llvm.x86.avx2.psll.w" => "__builtin_ia32_psllw256", + "llvm.x86.avx2.pslli.d" => "__builtin_ia32_pslldi256", + "llvm.x86.avx2.pslli.q" => "__builtin_ia32_psllqi256", + "llvm.x86.avx2.pslli.w" => "__builtin_ia32_psllwi256", + "llvm.x86.avx2.psllv.d" => "__builtin_ia32_psllv4si", + "llvm.x86.avx2.psllv.d.256" => "__builtin_ia32_psllv8si", + "llvm.x86.avx2.psllv.q" => "__builtin_ia32_psllv2di", + "llvm.x86.avx2.psllv.q.256" => "__builtin_ia32_psllv4di", + "llvm.x86.avx2.psra.d" => "__builtin_ia32_psrad256", + "llvm.x86.avx2.psra.w" => "__builtin_ia32_psraw256", + "llvm.x86.avx2.psrai.d" => "__builtin_ia32_psradi256", + "llvm.x86.avx2.psrai.w" => "__builtin_ia32_psrawi256", + "llvm.x86.avx2.psrav.d" => "__builtin_ia32_psrav4si", + "llvm.x86.avx2.psrav.d.256" => "__builtin_ia32_psrav8si", + "llvm.x86.avx2.psrl.d" => "__builtin_ia32_psrld256", + "llvm.x86.avx2.psrl.dq" => "__builtin_ia32_psrldqi256", + "llvm.x86.avx2.psrl.dq.bs" => "__builtin_ia32_psrldqi256_byteshift", + "llvm.x86.avx2.psrl.q" => "__builtin_ia32_psrlq256", + "llvm.x86.avx2.psrl.w" => "__builtin_ia32_psrlw256", + "llvm.x86.avx2.psrli.d" => "__builtin_ia32_psrldi256", + "llvm.x86.avx2.psrli.q" => "__builtin_ia32_psrlqi256", + "llvm.x86.avx2.psrli.w" => "__builtin_ia32_psrlwi256", + "llvm.x86.avx2.psrlv.d" => "__builtin_ia32_psrlv4si", + "llvm.x86.avx2.psrlv.d.256" => "__builtin_ia32_psrlv8si", + "llvm.x86.avx2.psrlv.q" => "__builtin_ia32_psrlv2di", + "llvm.x86.avx2.psrlv.q.256" => "__builtin_ia32_psrlv4di", + "llvm.x86.avx2.psubs.b" => "__builtin_ia32_psubsb256", + "llvm.x86.avx2.psubs.w" => "__builtin_ia32_psubsw256", + "llvm.x86.avx2.psubus.b" => "__builtin_ia32_psubusb256", + "llvm.x86.avx2.psubus.w" => "__builtin_ia32_psubusw256", + "llvm.x86.avx2.vbroadcast.sd.pd.256" => "__builtin_ia32_vbroadcastsd_pd256", + "llvm.x86.avx2.vbroadcast.ss.ps" => "__builtin_ia32_vbroadcastss_ps", + "llvm.x86.avx2.vbroadcast.ss.ps.256" => "__builtin_ia32_vbroadcastss_ps256", + "llvm.x86.avx2.vextracti128" => "__builtin_ia32_extract128i256", + "llvm.x86.avx2.vinserti128" => "__builtin_ia32_insert128i256", + "llvm.x86.avx2.vperm2i128" => "__builtin_ia32_permti256", + "llvm.x86.avx512.cvtsd2usi" => "__builtin_ia32_cvtsd2usi", + "llvm.x86.avx512.cvtsd2usi64" => "__builtin_ia32_cvtsd2usi64", + "llvm.x86.avx512.cvtss2usi" => "__builtin_ia32_cvtss2usi", + "llvm.x86.avx512.cvtss2usi64" => "__builtin_ia32_cvtss2usi64", + "llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_cvttsd2usi", + "llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_cvttsd2usi64", + "llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_cvttss2usi", + "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_cvttss2usi64", + "llvm.x86.avx512.cvtusi2sd" => "__builtin_ia32_cvtusi2sd", + "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss", + "llvm.x86.avx512.cvtusi642sd" => "__builtin_ia32_cvtusi642sd", + "llvm.x86.avx512.cvtusi642ss" => "__builtin_ia32_cvtusi642ss", + "llvm.x86.avx512.gather.dpd.512" => "__builtin_ia32_gathersiv8df", + "llvm.x86.avx512.gather.dpi.512" => "__builtin_ia32_gathersiv16si", + "llvm.x86.avx512.gather.dpq.512" => "__builtin_ia32_gathersiv8di", + "llvm.x86.avx512.gather.dps.512" => "__builtin_ia32_gathersiv16sf", + "llvm.x86.avx512.gather.qpd.512" => "__builtin_ia32_gatherdiv8df", + "llvm.x86.avx512.gather.qpi.512" => "__builtin_ia32_gatherdiv16si", + "llvm.x86.avx512.gather.qpq.512" => "__builtin_ia32_gatherdiv8di", + "llvm.x86.avx512.gather.qps.512" => "__builtin_ia32_gatherdiv16sf", + "llvm.x86.avx512.gatherpf.dpd.512" => "__builtin_ia32_gatherpfdpd", + "llvm.x86.avx512.gatherpf.dps.512" => "__builtin_ia32_gatherpfdps", + "llvm.x86.avx512.gatherpf.qpd.512" => "__builtin_ia32_gatherpfqpd", + "llvm.x86.avx512.gatherpf.qps.512" => "__builtin_ia32_gatherpfqps", + "llvm.x86.avx512.kand.w" => "__builtin_ia32_kandhi", + "llvm.x86.avx512.kandn.w" => "__builtin_ia32_kandnhi", + "llvm.x86.avx512.knot.w" => "__builtin_ia32_knothi", + "llvm.x86.avx512.kor.w" => "__builtin_ia32_korhi", + "llvm.x86.avx512.kortestc.w" => "__builtin_ia32_kortestchi", + "llvm.x86.avx512.kortestz.w" => "__builtin_ia32_kortestzhi", + "llvm.x86.avx512.kunpck.bw" => "__builtin_ia32_kunpckhi", + "llvm.x86.avx512.kxnor.w" => "__builtin_ia32_kxnorhi", + "llvm.x86.avx512.kxor.w" => "__builtin_ia32_kxorhi", + "llvm.x86.avx512.mask.blend.d.512" => "__builtin_ia32_blendmd_512_mask", + "llvm.x86.avx512.mask.blend.pd.512" => "__builtin_ia32_blendmpd_512_mask", + "llvm.x86.avx512.mask.blend.ps.512" => "__builtin_ia32_blendmps_512_mask", + "llvm.x86.avx512.mask.blend.q.512" => "__builtin_ia32_blendmq_512_mask", + "llvm.x86.avx512.mask.cmp.pd.512" => "__builtin_ia32_cmppd512_mask", + "llvm.x86.avx512.mask.cmp.ps.512" => "__builtin_ia32_cmpps512_mask", + "llvm.x86.avx512.mask.conflict.d.512" => "__builtin_ia32_vpconflictsi_512_mask", + "llvm.x86.avx512.mask.conflict.q.512" => "__builtin_ia32_vpconflictdi_512_mask", + "llvm.x86.avx512.mask.cvtdq2pd.512" => "__builtin_ia32_cvtdq2pd512_mask", + "llvm.x86.avx512.mask.cvtdq2ps.512" => "__builtin_ia32_cvtdq2ps512_mask", + "llvm.x86.avx512.mask.cvtpd2dq.512" => "__builtin_ia32_cvtpd2dq512_mask", + "llvm.x86.avx512.mask.cvtpd2ps.512" => "__builtin_ia32_cvtpd2ps512_mask", + "llvm.x86.avx512.mask.cvtpd2udq.512" => "__builtin_ia32_cvtpd2udq512_mask", + "llvm.x86.avx512.mask.cvtps2dq.512" => "__builtin_ia32_cvtps2dq512_mask", + "llvm.x86.avx512.mask.cvtps2udq.512" => "__builtin_ia32_cvtps2udq512_mask", + "llvm.x86.avx512.mask.cvttpd2dq.512" => "__builtin_ia32_cvttpd2dq512_mask", + "llvm.x86.avx512.mask.cvttpd2udq.512" => "__builtin_ia32_cvttpd2udq512_mask", + "llvm.x86.avx512.mask.cvttps2dq.512" => "__builtin_ia32_cvttps2dq512_mask", + "llvm.x86.avx512.mask.cvttps2udq.512" => "__builtin_ia32_cvttps2udq512_mask", + "llvm.x86.avx512.mask.cvtudq2pd.512" => "__builtin_ia32_cvtudq2pd512_mask", + "llvm.x86.avx512.mask.cvtudq2ps.512" => "__builtin_ia32_cvtudq2ps512_mask", + "llvm.x86.avx512.mask.loadu.d.512" => "__builtin_ia32_loaddqusi512_mask", + "llvm.x86.avx512.mask.loadu.pd.512" => "__builtin_ia32_loadupd512_mask", + "llvm.x86.avx512.mask.loadu.ps.512" => "__builtin_ia32_loadups512_mask", + "llvm.x86.avx512.mask.loadu.q.512" => "__builtin_ia32_loaddqudi512_mask", + "llvm.x86.avx512.mask.lzcnt.d.512" => "__builtin_ia32_vplzcntd_512_mask", + "llvm.x86.avx512.mask.lzcnt.q.512" => "__builtin_ia32_vplzcntq_512_mask", + "llvm.x86.avx512.mask.max.pd.512" => "__builtin_ia32_maxpd512_mask", + "llvm.x86.avx512.mask.max.ps.512" => "__builtin_ia32_maxps512_mask", + "llvm.x86.avx512.mask.min.pd.512" => "__builtin_ia32_minpd512_mask", + "llvm.x86.avx512.mask.min.ps.512" => "__builtin_ia32_minps512_mask", + "llvm.x86.avx512.mask.pabs.d.512" => "__builtin_ia32_pabsd512_mask", + "llvm.x86.avx512.mask.pabs.q.512" => "__builtin_ia32_pabsq512_mask", + "llvm.x86.avx512.mask.pand.d.512" => "__builtin_ia32_pandd512_mask", + "llvm.x86.avx512.mask.pand.q.512" => "__builtin_ia32_pandq512_mask", + "llvm.x86.avx512.mask.pbroadcast.d.gpr.512" => "__builtin_ia32_pbroadcastd512_gpr_mask", + "llvm.x86.avx512.mask.pbroadcast.q.gpr.512" => "__builtin_ia32_pbroadcastq512_gpr_mask", + "llvm.x86.avx512.mask.pbroadcast.q.mem.512" => "__builtin_ia32_pbroadcastq512_mem_mask", + "llvm.x86.avx512.mask.pcmpeq.b.128" => "__builtin_ia32_pcmpeqb128_mask", + "llvm.x86.avx512.mask.pcmpeq.b.256" => "__builtin_ia32_pcmpeqb256_mask", + "llvm.x86.avx512.mask.pcmpeq.b.512" => "__builtin_ia32_pcmpeqb512_mask", + "llvm.x86.avx512.mask.pcmpeq.d.128" => "__builtin_ia32_pcmpeqd128_mask", + "llvm.x86.avx512.mask.pcmpeq.d.256" => "__builtin_ia32_pcmpeqd256_mask", + "llvm.x86.avx512.mask.pcmpeq.d.512" => "__builtin_ia32_pcmpeqd512_mask", + "llvm.x86.avx512.mask.pcmpeq.q.128" => "__builtin_ia32_pcmpeqq128_mask", + "llvm.x86.avx512.mask.pcmpeq.q.256" => "__builtin_ia32_pcmpeqq256_mask", + "llvm.x86.avx512.mask.pcmpeq.q.512" => "__builtin_ia32_pcmpeqq512_mask", + "llvm.x86.avx512.mask.pcmpeq.w.128" => "__builtin_ia32_pcmpeqw128_mask", + "llvm.x86.avx512.mask.pcmpeq.w.256" => "__builtin_ia32_pcmpeqw256_mask", + "llvm.x86.avx512.mask.pcmpeq.w.512" => "__builtin_ia32_pcmpeqw512_mask", + "llvm.x86.avx512.mask.pcmpgt.b.128" => "__builtin_ia32_pcmpgtb128_mask", + "llvm.x86.avx512.mask.pcmpgt.b.256" => "__builtin_ia32_pcmpgtb256_mask", + "llvm.x86.avx512.mask.pcmpgt.b.512" => "__builtin_ia32_pcmpgtb512_mask", + "llvm.x86.avx512.mask.pcmpgt.d.128" => "__builtin_ia32_pcmpgtd128_mask", + "llvm.x86.avx512.mask.pcmpgt.d.256" => "__builtin_ia32_pcmpgtd256_mask", + "llvm.x86.avx512.mask.pcmpgt.d.512" => "__builtin_ia32_pcmpgtd512_mask", + "llvm.x86.avx512.mask.pcmpgt.q.128" => "__builtin_ia32_pcmpgtq128_mask", + "llvm.x86.avx512.mask.pcmpgt.q.256" => "__builtin_ia32_pcmpgtq256_mask", + "llvm.x86.avx512.mask.pcmpgt.q.512" => "__builtin_ia32_pcmpgtq512_mask", + "llvm.x86.avx512.mask.pcmpgt.w.128" => "__builtin_ia32_pcmpgtw128_mask", + "llvm.x86.avx512.mask.pcmpgt.w.256" => "__builtin_ia32_pcmpgtw256_mask", + "llvm.x86.avx512.mask.pcmpgt.w.512" => "__builtin_ia32_pcmpgtw512_mask", + "llvm.x86.avx512.mask.pmaxs.d.512" => "__builtin_ia32_pmaxsd512_mask", + "llvm.x86.avx512.mask.pmaxs.q.512" => "__builtin_ia32_pmaxsq512_mask", + "llvm.x86.avx512.mask.pmaxu.d.512" => "__builtin_ia32_pmaxud512_mask", + "llvm.x86.avx512.mask.pmaxu.q.512" => "__builtin_ia32_pmaxuq512_mask", + "llvm.x86.avx512.mask.pmins.d.512" => "__builtin_ia32_pminsd512_mask", + "llvm.x86.avx512.mask.pmins.q.512" => "__builtin_ia32_pminsq512_mask", + "llvm.x86.avx512.mask.pminu.d.512" => "__builtin_ia32_pminud512_mask", + "llvm.x86.avx512.mask.pminu.q.512" => "__builtin_ia32_pminuq512_mask", + "llvm.x86.avx512.mask.pmul.dq.512" => "__builtin_ia32_pmuldq512_mask", + "llvm.x86.avx512.mask.pmulu.dq.512" => "__builtin_ia32_pmuludq512_mask", + "llvm.x86.avx512.mask.ptestm.d.512" => "__builtin_ia32_ptestmd512", + "llvm.x86.avx512.mask.ptestm.q.512" => "__builtin_ia32_ptestmq512", + "llvm.x86.avx512.mask.rndscale.pd.512" => "__builtin_ia32_rndscalepd_mask", + "llvm.x86.avx512.mask.rndscale.ps.512" => "__builtin_ia32_rndscaleps_mask", + "llvm.x86.avx512.mask.store.ss" => "__builtin_ia32_storess_mask", + "llvm.x86.avx512.mask.storeu.d.512" => "__builtin_ia32_storedqusi512_mask", + "llvm.x86.avx512.mask.storeu.pd.512" => "__builtin_ia32_storeupd512_mask", + "llvm.x86.avx512.mask.storeu.ps.512" => "__builtin_ia32_storeups512_mask", + "llvm.x86.avx512.mask.storeu.q.512" => "__builtin_ia32_storedqudi512_mask", + "llvm.x86.avx512.mask.valign.d.512" => "__builtin_ia32_alignd512_mask", + "llvm.x86.avx512.mask.valign.q.512" => "__builtin_ia32_alignq512_mask", + "llvm.x86.avx512.mask.vcvtph2ps.512" => "__builtin_ia32_vcvtph2ps512_mask", + "llvm.x86.avx512.mask.vcvtps2ph.512" => "__builtin_ia32_vcvtps2ph512_mask", + "llvm.x86.avx512.mask.vpermt.d.512" => "__builtin_ia32_vpermt2vard512_mask", + "llvm.x86.avx512.mask.vpermt.pd.512" => "__builtin_ia32_vpermt2varpd512_mask", + "llvm.x86.avx512.mask.vpermt.ps.512" => "__builtin_ia32_vpermt2varps512_mask", + "llvm.x86.avx512.mask.vpermt.q.512" => "__builtin_ia32_vpermt2varq512_mask", + "llvm.x86.avx512.movntdqa" => "__builtin_ia32_movntdqa512", + "llvm.x86.avx512.pbroadcastd.512" => "__builtin_ia32_pbroadcastd512", + "llvm.x86.avx512.pbroadcastq.512" => "__builtin_ia32_pbroadcastq512", + "llvm.x86.avx512.pmovzxbd" => "__builtin_ia32_pmovzxbd512", + "llvm.x86.avx512.pmovzxbq" => "__builtin_ia32_pmovzxbq512", + "llvm.x86.avx512.pmovzxdq" => "__builtin_ia32_pmovzxdq512", + "llvm.x86.avx512.pmovzxwd" => "__builtin_ia32_pmovzxwd512", + "llvm.x86.avx512.pmovzxwq" => "__builtin_ia32_pmovzxwq512", + "llvm.x86.avx512.psll.dq" => "__builtin_ia32_pslldqi512", + "llvm.x86.avx512.psll.dq.bs" => "__builtin_ia32_pslldqi512_byteshift", + "llvm.x86.avx512.psrl.dq" => "__builtin_ia32_psrldqi512", + "llvm.x86.avx512.psrl.dq.bs" => "__builtin_ia32_psrldqi512_byteshift", + "llvm.x86.avx512.rcp14.pd.512" => "__builtin_ia32_rcp14pd512_mask", + "llvm.x86.avx512.rcp14.ps.512" => "__builtin_ia32_rcp14ps512_mask", + "llvm.x86.avx512.rcp14.sd" => "__builtin_ia32_rcp14sd_mask", + "llvm.x86.avx512.rcp14.ss" => "__builtin_ia32_rcp14ss_mask", + "llvm.x86.avx512.rcp28.pd" => "__builtin_ia32_rcp28pd_mask", + "llvm.x86.avx512.rcp28.ps" => "__builtin_ia32_rcp28ps_mask", + "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_mask", + "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_mask", + "llvm.x86.avx512.rndscale.sd" => "__builtin_ia32_rndscalesd", + "llvm.x86.avx512.rndscale.ss" => "__builtin_ia32_rndscaless", + "llvm.x86.avx512.rsqrt14.pd.512" => "__builtin_ia32_rsqrt14pd512_mask", + "llvm.x86.avx512.rsqrt14.ps.512" => "__builtin_ia32_rsqrt14ps512_mask", + "llvm.x86.avx512.rsqrt14.sd" => "__builtin_ia32_rsqrt14sd_mask", + "llvm.x86.avx512.rsqrt14.ss" => "__builtin_ia32_rsqrt14ss_mask", + "llvm.x86.avx512.rsqrt28.pd" => "__builtin_ia32_rsqrt28pd_mask", + "llvm.x86.avx512.rsqrt28.ps" => "__builtin_ia32_rsqrt28ps_mask", + "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_mask", + "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_mask", + "llvm.x86.avx512.scatter.dpd.512" => "__builtin_ia32_scattersiv8df", + "llvm.x86.avx512.scatter.dpi.512" => "__builtin_ia32_scattersiv16si", + "llvm.x86.avx512.scatter.dpq.512" => "__builtin_ia32_scattersiv8di", + "llvm.x86.avx512.scatter.dps.512" => "__builtin_ia32_scattersiv16sf", + "llvm.x86.avx512.scatter.qpd.512" => "__builtin_ia32_scatterdiv8df", + "llvm.x86.avx512.scatter.qpi.512" => "__builtin_ia32_scatterdiv16si", + "llvm.x86.avx512.scatter.qpq.512" => "__builtin_ia32_scatterdiv8di", + "llvm.x86.avx512.scatter.qps.512" => "__builtin_ia32_scatterdiv16sf", + "llvm.x86.avx512.scatterpf.dpd.512" => "__builtin_ia32_scatterpfdpd", + "llvm.x86.avx512.scatterpf.dps.512" => "__builtin_ia32_scatterpfdps", + "llvm.x86.avx512.scatterpf.qpd.512" => "__builtin_ia32_scatterpfqpd", + "llvm.x86.avx512.scatterpf.qps.512" => "__builtin_ia32_scatterpfqps", + "llvm.x86.avx512.sqrt.pd.512" => "__builtin_ia32_sqrtpd512_mask", + "llvm.x86.avx512.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask", + "llvm.x86.avx512.sqrt.sd" => "__builtin_ia32_sqrtrndsd", + "llvm.x86.avx512.sqrt.ss" => "__builtin_ia32_sqrtrndss", + "llvm.x86.avx512.vbroadcast.sd.512" => "__builtin_ia32_vbroadcastsd512", + "llvm.x86.avx512.vbroadcast.sd.pd.512" => "__builtin_ia32_vbroadcastsd_pd512", + "llvm.x86.avx512.vbroadcast.ss.512" => "__builtin_ia32_vbroadcastss512", + "llvm.x86.avx512.vbroadcast.ss.ps.512" => "__builtin_ia32_vbroadcastss_ps512", + "llvm.x86.bmi.bextr.32" => "__builtin_ia32_bextr_u32", + "llvm.x86.bmi.bextr.64" => "__builtin_ia32_bextr_u64", + "llvm.x86.bmi.bzhi.32" => "__builtin_ia32_bzhi_si", + "llvm.x86.bmi.bzhi.64" => "__builtin_ia32_bzhi_di", + "llvm.x86.bmi.pdep.32" => "__builtin_ia32_pdep_si", + "llvm.x86.bmi.pdep.64" => "__builtin_ia32_pdep_di", + "llvm.x86.bmi.pext.32" => "__builtin_ia32_pext_si", + "llvm.x86.bmi.pext.64" => "__builtin_ia32_pext_di", + "llvm.x86.fma.mask.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask", + "llvm.x86.fma.mask.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask", + "llvm.x86.fma.mask.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask", + "llvm.x86.fma.mask.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask", + "llvm.x86.fma.mask.vfmsub.pd.512" => "__builtin_ia32_vfmsubpd512_mask", + "llvm.x86.fma.mask.vfmsub.ps.512" => "__builtin_ia32_vfmsubps512_mask", + "llvm.x86.fma.mask.vfmsubadd.pd.512" => "__builtin_ia32_vfmsubaddpd512_mask", + "llvm.x86.fma.mask.vfmsubadd.ps.512" => "__builtin_ia32_vfmsubaddps512_mask", + "llvm.x86.fma.mask.vfnmadd.pd.512" => "__builtin_ia32_vfnmaddpd512_mask", + "llvm.x86.fma.mask.vfnmadd.ps.512" => "__builtin_ia32_vfnmaddps512_mask", + "llvm.x86.fma.mask.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask", + "llvm.x86.fma.mask.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask", + "llvm.x86.fma.vfmadd.pd" => "__builtin_ia32_vfmaddpd", + "llvm.x86.fma.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256", + "llvm.x86.fma.vfmadd.ps" => "__builtin_ia32_vfmaddps", + "llvm.x86.fma.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256", + "llvm.x86.fma.vfmadd.sd" => "__builtin_ia32_vfmaddsd", + "llvm.x86.fma.vfmadd.ss" => "__builtin_ia32_vfmaddss", + "llvm.x86.fma.vfmaddsub.pd" => "__builtin_ia32_vfmaddsubpd", + "llvm.x86.fma.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256", + "llvm.x86.fma.vfmaddsub.ps" => "__builtin_ia32_vfmaddsubps", + "llvm.x86.fma.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256", + "llvm.x86.fma.vfmsub.pd" => "__builtin_ia32_vfmsubpd", + "llvm.x86.fma.vfmsub.pd.256" => "__builtin_ia32_vfmsubpd256", + "llvm.x86.fma.vfmsub.ps" => "__builtin_ia32_vfmsubps", + "llvm.x86.fma.vfmsub.ps.256" => "__builtin_ia32_vfmsubps256", + "llvm.x86.fma.vfmsub.sd" => "__builtin_ia32_vfmsubsd", + "llvm.x86.fma.vfmsub.ss" => "__builtin_ia32_vfmsubss", + "llvm.x86.fma.vfmsubadd.pd" => "__builtin_ia32_vfmsubaddpd", + "llvm.x86.fma.vfmsubadd.pd.256" => "__builtin_ia32_vfmsubaddpd256", + "llvm.x86.fma.vfmsubadd.ps" => "__builtin_ia32_vfmsubaddps", + "llvm.x86.fma.vfmsubadd.ps.256" => "__builtin_ia32_vfmsubaddps256", + "llvm.x86.fma.vfnmadd.pd" => "__builtin_ia32_vfnmaddpd", + "llvm.x86.fma.vfnmadd.pd.256" => "__builtin_ia32_vfnmaddpd256", + "llvm.x86.fma.vfnmadd.ps" => "__builtin_ia32_vfnmaddps", + "llvm.x86.fma.vfnmadd.ps.256" => "__builtin_ia32_vfnmaddps256", + "llvm.x86.fma.vfnmadd.sd" => "__builtin_ia32_vfnmaddsd", + "llvm.x86.fma.vfnmadd.ss" => "__builtin_ia32_vfnmaddss", + "llvm.x86.fma.vfnmsub.pd" => "__builtin_ia32_vfnmsubpd", + "llvm.x86.fma.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256", + "llvm.x86.fma.vfnmsub.ps" => "__builtin_ia32_vfnmsubps", + "llvm.x86.fma.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256", + "llvm.x86.fma.vfnmsub.sd" => "__builtin_ia32_vfnmsubsd", + "llvm.x86.fma.vfnmsub.ss" => "__builtin_ia32_vfnmsubss", + "llvm.x86.mmx.emms" => "__builtin_ia32_emms", + "llvm.x86.mmx.femms" => "__builtin_ia32_femms", + "llvm.x86.pclmulqdq" => "__builtin_ia32_pclmulqdq128", + "llvm.x86.rdfsbase.32" => "__builtin_ia32_rdfsbase32", + "llvm.x86.rdfsbase.64" => "__builtin_ia32_rdfsbase64", + "llvm.x86.rdgsbase.32" => "__builtin_ia32_rdgsbase32", + "llvm.x86.rdgsbase.64" => "__builtin_ia32_rdgsbase64", + "llvm.x86.rdpmc" => "__builtin_ia32_rdpmc", + "llvm.x86.rdtsc" => "__builtin_ia32_rdtsc", + "llvm.x86.rdtscp" => "__builtin_ia32_rdtscp", + "llvm.x86.sha1msg1" => "__builtin_ia32_sha1msg1", + "llvm.x86.sha1msg2" => "__builtin_ia32_sha1msg2", + "llvm.x86.sha1nexte" => "__builtin_ia32_sha1nexte", + "llvm.x86.sha1rnds4" => "__builtin_ia32_sha1rnds4", + "llvm.x86.sha256msg1" => "__builtin_ia32_sha256msg1", + "llvm.x86.sha256msg2" => "__builtin_ia32_sha256msg2", + "llvm.x86.sha256rnds2" => "__builtin_ia32_sha256rnds2", + "llvm.x86.sse.add.ss" => "__builtin_ia32_addss", + "llvm.x86.sse.cmp.ps" => "__builtin_ia32_cmpps", + "llvm.x86.sse.cmp.ss" => "__builtin_ia32_cmpss", + "llvm.x86.sse.comieq.ss" => "__builtin_ia32_comieq", + "llvm.x86.sse.comige.ss" => "__builtin_ia32_comige", + "llvm.x86.sse.comigt.ss" => "__builtin_ia32_comigt", + "llvm.x86.sse.comile.ss" => "__builtin_ia32_comile", + "llvm.x86.sse.comilt.ss" => "__builtin_ia32_comilt", + "llvm.x86.sse.comineq.ss" => "__builtin_ia32_comineq", + "llvm.x86.sse.cvtsi2ss" => "__builtin_ia32_cvtsi2ss", + "llvm.x86.sse.cvtsi642ss" => "__builtin_ia32_cvtsi642ss", + "llvm.x86.sse.cvtss2si" => "__builtin_ia32_cvtss2si", + "llvm.x86.sse.cvtss2si64" => "__builtin_ia32_cvtss2si64", + "llvm.x86.sse.cvttss2si" => "__builtin_ia32_cvttss2si", + "llvm.x86.sse.cvttss2si64" => "__builtin_ia32_cvttss2si64", + "llvm.x86.sse.div.ss" => "__builtin_ia32_divss", + "llvm.x86.sse.max.ps" => "__builtin_ia32_maxps", + "llvm.x86.sse.max.ss" => "__builtin_ia32_maxss", + "llvm.x86.sse.min.ps" => "__builtin_ia32_minps", + "llvm.x86.sse.min.ss" => "__builtin_ia32_minss", + "llvm.x86.sse.movmsk.ps" => "__builtin_ia32_movmskps", + "llvm.x86.sse.mul.ss" => "__builtin_ia32_mulss", + "llvm.x86.sse.rcp.ps" => "__builtin_ia32_rcpps", + "llvm.x86.sse.rcp.ss" => "__builtin_ia32_rcpss", + "llvm.x86.sse.rsqrt.ps" => "__builtin_ia32_rsqrtps", + "llvm.x86.sse.rsqrt.ss" => "__builtin_ia32_rsqrtss", + "llvm.x86.sse.sfence" => "__builtin_ia32_sfence", + "llvm.x86.sse.sqrt.ps" => "__builtin_ia32_sqrtps", + "llvm.x86.sse.sqrt.ss" => "__builtin_ia32_sqrtss", + "llvm.x86.sse.storeu.ps" => "__builtin_ia32_storeups", + "llvm.x86.sse.sub.ss" => "__builtin_ia32_subss", + "llvm.x86.sse.ucomieq.ss" => "__builtin_ia32_ucomieq", + "llvm.x86.sse.ucomige.ss" => "__builtin_ia32_ucomige", + "llvm.x86.sse.ucomigt.ss" => "__builtin_ia32_ucomigt", + "llvm.x86.sse.ucomile.ss" => "__builtin_ia32_ucomile", + "llvm.x86.sse.ucomilt.ss" => "__builtin_ia32_ucomilt", + "llvm.x86.sse.ucomineq.ss" => "__builtin_ia32_ucomineq", + "llvm.x86.sse2.add.sd" => "__builtin_ia32_addsd", + "llvm.x86.sse2.clflush" => "__builtin_ia32_clflush", + "llvm.x86.sse2.cmp.pd" => "__builtin_ia32_cmppd", + "llvm.x86.sse2.cmp.sd" => "__builtin_ia32_cmpsd", + "llvm.x86.sse2.comieq.sd" => "__builtin_ia32_comisdeq", + "llvm.x86.sse2.comige.sd" => "__builtin_ia32_comisdge", + "llvm.x86.sse2.comigt.sd" => "__builtin_ia32_comisdgt", + "llvm.x86.sse2.comile.sd" => "__builtin_ia32_comisdle", + "llvm.x86.sse2.comilt.sd" => "__builtin_ia32_comisdlt", + "llvm.x86.sse2.comineq.sd" => "__builtin_ia32_comisdneq", + "llvm.x86.sse2.cvtdq2pd" => "__builtin_ia32_cvtdq2pd", + "llvm.x86.sse2.cvtdq2ps" => "__builtin_ia32_cvtdq2ps", + "llvm.x86.sse2.cvtpd2dq" => "__builtin_ia32_cvtpd2dq", + "llvm.x86.sse2.cvtpd2ps" => "__builtin_ia32_cvtpd2ps", + "llvm.x86.sse2.cvtps2dq" => "__builtin_ia32_cvtps2dq", + "llvm.x86.sse2.cvtps2pd" => "__builtin_ia32_cvtps2pd", + "llvm.x86.sse2.cvtsd2si" => "__builtin_ia32_cvtsd2si", + "llvm.x86.sse2.cvtsd2si64" => "__builtin_ia32_cvtsd2si64", + "llvm.x86.sse2.cvtsd2ss" => "__builtin_ia32_cvtsd2ss", + "llvm.x86.sse2.cvtsi2sd" => "__builtin_ia32_cvtsi2sd", + "llvm.x86.sse2.cvtsi642sd" => "__builtin_ia32_cvtsi642sd", + "llvm.x86.sse2.cvtss2sd" => "__builtin_ia32_cvtss2sd", + "llvm.x86.sse2.cvttpd2dq" => "__builtin_ia32_cvttpd2dq", + "llvm.x86.sse2.cvttps2dq" => "__builtin_ia32_cvttps2dq", + "llvm.x86.sse2.cvttsd2si" => "__builtin_ia32_cvttsd2si", + "llvm.x86.sse2.cvttsd2si64" => "__builtin_ia32_cvttsd2si64", + "llvm.x86.sse2.div.sd" => "__builtin_ia32_divsd", + "llvm.x86.sse2.lfence" => "__builtin_ia32_lfence", + "llvm.x86.sse2.maskmov.dqu" => "__builtin_ia32_maskmovdqu", + "llvm.x86.sse2.max.pd" => "__builtin_ia32_maxpd", + "llvm.x86.sse2.max.sd" => "__builtin_ia32_maxsd", + "llvm.x86.sse2.mfence" => "__builtin_ia32_mfence", + "llvm.x86.sse2.min.pd" => "__builtin_ia32_minpd", + "llvm.x86.sse2.min.sd" => "__builtin_ia32_minsd", + "llvm.x86.sse2.movmsk.pd" => "__builtin_ia32_movmskpd", + "llvm.x86.sse2.mul.sd" => "__builtin_ia32_mulsd", + "llvm.x86.sse2.packssdw.128" => "__builtin_ia32_packssdw128", + "llvm.x86.sse2.packsswb.128" => "__builtin_ia32_packsswb128", + "llvm.x86.sse2.packuswb.128" => "__builtin_ia32_packuswb128", + "llvm.x86.sse2.padds.b" => "__builtin_ia32_paddsb128", + "llvm.x86.sse2.padds.w" => "__builtin_ia32_paddsw128", + "llvm.x86.sse2.paddus.b" => "__builtin_ia32_paddusb128", + "llvm.x86.sse2.paddus.w" => "__builtin_ia32_paddusw128", + "llvm.x86.sse2.pause" => "__builtin_ia32_pause", + "llvm.x86.sse2.pavg.b" => "__builtin_ia32_pavgb128", + "llvm.x86.sse2.pavg.w" => "__builtin_ia32_pavgw128", + "llvm.x86.sse2.pmadd.wd" => "__builtin_ia32_pmaddwd128", + "llvm.x86.sse2.pmaxs.w" => "__builtin_ia32_pmaxsw128", + "llvm.x86.sse2.pmaxu.b" => "__builtin_ia32_pmaxub128", + "llvm.x86.sse2.pmins.w" => "__builtin_ia32_pminsw128", + "llvm.x86.sse2.pminu.b" => "__builtin_ia32_pminub128", + "llvm.x86.sse2.pmovmskb.128" => "__builtin_ia32_pmovmskb128", + "llvm.x86.sse2.pmulh.w" => "__builtin_ia32_pmulhw128", + "llvm.x86.sse2.pmulhu.w" => "__builtin_ia32_pmulhuw128", + "llvm.x86.sse2.pmulu.dq" => "__builtin_ia32_pmuludq128", + "llvm.x86.sse2.psad.bw" => "__builtin_ia32_psadbw128", + "llvm.x86.sse2.pshuf.d" => "__builtin_ia32_pshufd", + "llvm.x86.sse2.pshufh.w" => "__builtin_ia32_pshufhw", + "llvm.x86.sse2.pshufl.w" => "__builtin_ia32_pshuflw", + "llvm.x86.sse2.psll.d" => "__builtin_ia32_pslld128", + "llvm.x86.sse2.psll.dq" => "__builtin_ia32_pslldqi128", + "llvm.x86.sse2.psll.dq.bs" => "__builtin_ia32_pslldqi128_byteshift", + "llvm.x86.sse2.psll.q" => "__builtin_ia32_psllq128", + "llvm.x86.sse2.psll.w" => "__builtin_ia32_psllw128", + "llvm.x86.sse2.pslli.d" => "__builtin_ia32_pslldi128", + "llvm.x86.sse2.pslli.q" => "__builtin_ia32_psllqi128", + "llvm.x86.sse2.pslli.w" => "__builtin_ia32_psllwi128", + "llvm.x86.sse2.psra.d" => "__builtin_ia32_psrad128", + "llvm.x86.sse2.psra.w" => "__builtin_ia32_psraw128", + "llvm.x86.sse2.psrai.d" => "__builtin_ia32_psradi128", + "llvm.x86.sse2.psrai.w" => "__builtin_ia32_psrawi128", + "llvm.x86.sse2.psrl.d" => "__builtin_ia32_psrld128", + "llvm.x86.sse2.psrl.dq" => "__builtin_ia32_psrldqi128", + "llvm.x86.sse2.psrl.dq.bs" => "__builtin_ia32_psrldqi128_byteshift", + "llvm.x86.sse2.psrl.q" => "__builtin_ia32_psrlq128", + "llvm.x86.sse2.psrl.w" => "__builtin_ia32_psrlw128", + "llvm.x86.sse2.psrli.d" => "__builtin_ia32_psrldi128", + "llvm.x86.sse2.psrli.q" => "__builtin_ia32_psrlqi128", + "llvm.x86.sse2.psrli.w" => "__builtin_ia32_psrlwi128", + "llvm.x86.sse2.psubs.b" => "__builtin_ia32_psubsb128", + "llvm.x86.sse2.psubs.w" => "__builtin_ia32_psubsw128", + "llvm.x86.sse2.psubus.b" => "__builtin_ia32_psubusb128", + "llvm.x86.sse2.psubus.w" => "__builtin_ia32_psubusw128", + "llvm.x86.sse2.sqrt.pd" => "__builtin_ia32_sqrtpd", + "llvm.x86.sse2.sqrt.sd" => "__builtin_ia32_sqrtsd", + "llvm.x86.sse2.storel.dq" => "__builtin_ia32_storelv4si", + "llvm.x86.sse2.storeu.dq" => "__builtin_ia32_storedqu", + "llvm.x86.sse2.storeu.pd" => "__builtin_ia32_storeupd", + "llvm.x86.sse2.sub.sd" => "__builtin_ia32_subsd", + "llvm.x86.sse2.ucomieq.sd" => "__builtin_ia32_ucomisdeq", + "llvm.x86.sse2.ucomige.sd" => "__builtin_ia32_ucomisdge", + "llvm.x86.sse2.ucomigt.sd" => "__builtin_ia32_ucomisdgt", + "llvm.x86.sse2.ucomile.sd" => "__builtin_ia32_ucomisdle", + "llvm.x86.sse2.ucomilt.sd" => "__builtin_ia32_ucomisdlt", + "llvm.x86.sse2.ucomineq.sd" => "__builtin_ia32_ucomisdneq", + "llvm.x86.sse3.addsub.pd" => "__builtin_ia32_addsubpd", + "llvm.x86.sse3.addsub.ps" => "__builtin_ia32_addsubps", + "llvm.x86.sse3.hadd.pd" => "__builtin_ia32_haddpd", + "llvm.x86.sse3.hadd.ps" => "__builtin_ia32_haddps", + "llvm.x86.sse3.hsub.pd" => "__builtin_ia32_hsubpd", + "llvm.x86.sse3.hsub.ps" => "__builtin_ia32_hsubps", + "llvm.x86.sse3.ldu.dq" => "__builtin_ia32_lddqu", + "llvm.x86.sse3.monitor" => "__builtin_ia32_monitor", + "llvm.x86.sse3.mwait" => "__builtin_ia32_mwait", + "llvm.x86.sse41.blendpd" => "__builtin_ia32_blendpd", + "llvm.x86.sse41.blendps" => "__builtin_ia32_blendps", + "llvm.x86.sse41.blendvpd" => "__builtin_ia32_blendvpd", + "llvm.x86.sse41.blendvps" => "__builtin_ia32_blendvps", + "llvm.x86.sse41.dppd" => "__builtin_ia32_dppd", + "llvm.x86.sse41.dpps" => "__builtin_ia32_dpps", + "llvm.x86.sse41.extractps" => "__builtin_ia32_extractps128", + "llvm.x86.sse41.insertps" => "__builtin_ia32_insertps128", + "llvm.x86.sse41.movntdqa" => "__builtin_ia32_movntdqa", + "llvm.x86.sse41.mpsadbw" => "__builtin_ia32_mpsadbw128", + "llvm.x86.sse41.packusdw" => "__builtin_ia32_packusdw128", + "llvm.x86.sse41.pblendvb" => "__builtin_ia32_pblendvb128", + "llvm.x86.sse41.pblendw" => "__builtin_ia32_pblendw128", + "llvm.x86.sse41.phminposuw" => "__builtin_ia32_phminposuw128", + "llvm.x86.sse41.pmaxsb" => "__builtin_ia32_pmaxsb128", + "llvm.x86.sse41.pmaxsd" => "__builtin_ia32_pmaxsd128", + "llvm.x86.sse41.pmaxud" => "__builtin_ia32_pmaxud128", + "llvm.x86.sse41.pmaxuw" => "__builtin_ia32_pmaxuw128", + "llvm.x86.sse41.pminsb" => "__builtin_ia32_pminsb128", + "llvm.x86.sse41.pminsd" => "__builtin_ia32_pminsd128", + "llvm.x86.sse41.pminud" => "__builtin_ia32_pminud128", + "llvm.x86.sse41.pminuw" => "__builtin_ia32_pminuw128", + "llvm.x86.sse41.pmovsxbd" => "__builtin_ia32_pmovsxbd128", + "llvm.x86.sse41.pmovsxbq" => "__builtin_ia32_pmovsxbq128", + "llvm.x86.sse41.pmovsxbw" => "__builtin_ia32_pmovsxbw128", + "llvm.x86.sse41.pmovsxdq" => "__builtin_ia32_pmovsxdq128", + "llvm.x86.sse41.pmovsxwd" => "__builtin_ia32_pmovsxwd128", + "llvm.x86.sse41.pmovsxwq" => "__builtin_ia32_pmovsxwq128", + "llvm.x86.sse41.pmovzxbd" => "__builtin_ia32_pmovzxbd128", + "llvm.x86.sse41.pmovzxbq" => "__builtin_ia32_pmovzxbq128", + "llvm.x86.sse41.pmovzxbw" => "__builtin_ia32_pmovzxbw128", + "llvm.x86.sse41.pmovzxdq" => "__builtin_ia32_pmovzxdq128", + "llvm.x86.sse41.pmovzxwd" => "__builtin_ia32_pmovzxwd128", + "llvm.x86.sse41.pmovzxwq" => "__builtin_ia32_pmovzxwq128", + "llvm.x86.sse41.pmuldq" => "__builtin_ia32_pmuldq128", + "llvm.x86.sse41.ptestc" => "__builtin_ia32_ptestc128", + "llvm.x86.sse41.ptestnzc" => "__builtin_ia32_ptestnzc128", + "llvm.x86.sse41.ptestz" => "__builtin_ia32_ptestz128", + "llvm.x86.sse41.round.pd" => "__builtin_ia32_roundpd", + "llvm.x86.sse41.round.ps" => "__builtin_ia32_roundps", + "llvm.x86.sse41.round.sd" => "__builtin_ia32_roundsd", + "llvm.x86.sse41.round.ss" => "__builtin_ia32_roundss", + "llvm.x86.sse42.crc32.32.16" => "__builtin_ia32_crc32hi", + "llvm.x86.sse42.crc32.32.32" => "__builtin_ia32_crc32si", + "llvm.x86.sse42.crc32.32.8" => "__builtin_ia32_crc32qi", + "llvm.x86.sse42.crc32.64.64" => "__builtin_ia32_crc32di", + "llvm.x86.sse42.pcmpestri128" => "__builtin_ia32_pcmpestri128", + "llvm.x86.sse42.pcmpestria128" => "__builtin_ia32_pcmpestria128", + "llvm.x86.sse42.pcmpestric128" => "__builtin_ia32_pcmpestric128", + "llvm.x86.sse42.pcmpestrio128" => "__builtin_ia32_pcmpestrio128", + "llvm.x86.sse42.pcmpestris128" => "__builtin_ia32_pcmpestris128", + "llvm.x86.sse42.pcmpestriz128" => "__builtin_ia32_pcmpestriz128", + "llvm.x86.sse42.pcmpestrm128" => "__builtin_ia32_pcmpestrm128", + "llvm.x86.sse42.pcmpistri128" => "__builtin_ia32_pcmpistri128", + "llvm.x86.sse42.pcmpistria128" => "__builtin_ia32_pcmpistria128", + "llvm.x86.sse42.pcmpistric128" => "__builtin_ia32_pcmpistric128", + "llvm.x86.sse42.pcmpistrio128" => "__builtin_ia32_pcmpistrio128", + "llvm.x86.sse42.pcmpistris128" => "__builtin_ia32_pcmpistris128", + "llvm.x86.sse42.pcmpistriz128" => "__builtin_ia32_pcmpistriz128", + "llvm.x86.sse42.pcmpistrm128" => "__builtin_ia32_pcmpistrm128", + "llvm.x86.sse4a.extrq" => "__builtin_ia32_extrq", + "llvm.x86.sse4a.extrqi" => "__builtin_ia32_extrqi", + "llvm.x86.sse4a.insertq" => "__builtin_ia32_insertq", + "llvm.x86.sse4a.insertqi" => "__builtin_ia32_insertqi", + "llvm.x86.sse4a.movnt.sd" => "__builtin_ia32_movntsd", + "llvm.x86.sse4a.movnt.ss" => "__builtin_ia32_movntss", + "llvm.x86.ssse3.pabs.b.128" => "__builtin_ia32_pabsb128", + "llvm.x86.ssse3.pabs.d.128" => "__builtin_ia32_pabsd128", + "llvm.x86.ssse3.pabs.w.128" => "__builtin_ia32_pabsw128", + "llvm.x86.ssse3.phadd.d.128" => "__builtin_ia32_phaddd128", + "llvm.x86.ssse3.phadd.sw.128" => "__builtin_ia32_phaddsw128", + "llvm.x86.ssse3.phadd.w.128" => "__builtin_ia32_phaddw128", + "llvm.x86.ssse3.phsub.d.128" => "__builtin_ia32_phsubd128", + "llvm.x86.ssse3.phsub.sw.128" => "__builtin_ia32_phsubsw128", + "llvm.x86.ssse3.phsub.w.128" => "__builtin_ia32_phsubw128", + "llvm.x86.ssse3.pmadd.ub.sw.128" => "__builtin_ia32_pmaddubsw128", + "llvm.x86.ssse3.pmul.hr.sw.128" => "__builtin_ia32_pmulhrsw128", + "llvm.x86.ssse3.pshuf.b.128" => "__builtin_ia32_pshufb128", + "llvm.x86.ssse3.psign.b.128" => "__builtin_ia32_psignb128", + "llvm.x86.ssse3.psign.d.128" => "__builtin_ia32_psignd128", + "llvm.x86.ssse3.psign.w.128" => "__builtin_ia32_psignw128", + "llvm.x86.subborrow.u32" => "__builtin_ia32_subborrow_u32", + "llvm.x86.subborrow.u64" => "__builtin_ia32_subborrow_u64", + "llvm.x86.tbm.bextri.u32" => "__builtin_ia32_bextri_u32", + "llvm.x86.tbm.bextri.u64" => "__builtin_ia32_bextri_u64", + "llvm.x86.vcvtph2ps.128" => "__builtin_ia32_vcvtph2ps", + "llvm.x86.vcvtph2ps.256" => "__builtin_ia32_vcvtph2ps256", + "llvm.x86.vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph", + "llvm.x86.vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256", + "llvm.x86.wrfsbase.32" => "__builtin_ia32_wrfsbase32", + "llvm.x86.wrfsbase.64" => "__builtin_ia32_wrfsbase64", + "llvm.x86.wrgsbase.32" => "__builtin_ia32_wrgsbase32", + "llvm.x86.wrgsbase.64" => "__builtin_ia32_wrgsbase64", + "llvm.x86.xabort" => "__builtin_ia32_xabort", + "llvm.x86.xbegin" => "__builtin_ia32_xbegin", + "llvm.x86.xend" => "__builtin_ia32_xend", + "llvm.x86.xop.vfrcz.pd" => "__builtin_ia32_vfrczpd", + "llvm.x86.xop.vfrcz.pd.256" => "__builtin_ia32_vfrczpd256", + "llvm.x86.xop.vfrcz.ps" => "__builtin_ia32_vfrczps", + "llvm.x86.xop.vfrcz.ps.256" => "__builtin_ia32_vfrczps256", + "llvm.x86.xop.vfrcz.sd" => "__builtin_ia32_vfrczsd", + "llvm.x86.xop.vfrcz.ss" => "__builtin_ia32_vfrczss", + "llvm.x86.xop.vpcmov" => "__builtin_ia32_vpcmov", + "llvm.x86.xop.vpcmov.256" => "__builtin_ia32_vpcmov_256", + "llvm.x86.xop.vpcomb" => "__builtin_ia32_vpcomb", + "llvm.x86.xop.vpcomd" => "__builtin_ia32_vpcomd", + "llvm.x86.xop.vpcomq" => "__builtin_ia32_vpcomq", + "llvm.x86.xop.vpcomub" => "__builtin_ia32_vpcomub", + "llvm.x86.xop.vpcomud" => "__builtin_ia32_vpcomud", + "llvm.x86.xop.vpcomuq" => "__builtin_ia32_vpcomuq", + "llvm.x86.xop.vpcomuw" => "__builtin_ia32_vpcomuw", + "llvm.x86.xop.vpcomw" => "__builtin_ia32_vpcomw", + "llvm.x86.xop.vpermil2pd" => "__builtin_ia32_vpermil2pd", + "llvm.x86.xop.vpermil2pd.256" => "__builtin_ia32_vpermil2pd256", + "llvm.x86.xop.vpermil2ps" => "__builtin_ia32_vpermil2ps", + "llvm.x86.xop.vpermil2ps.256" => "__builtin_ia32_vpermil2ps256", + "llvm.x86.xop.vphaddbd" => "__builtin_ia32_vphaddbd", + "llvm.x86.xop.vphaddbq" => "__builtin_ia32_vphaddbq", + "llvm.x86.xop.vphaddbw" => "__builtin_ia32_vphaddbw", + "llvm.x86.xop.vphadddq" => "__builtin_ia32_vphadddq", + "llvm.x86.xop.vphaddubd" => "__builtin_ia32_vphaddubd", + "llvm.x86.xop.vphaddubq" => "__builtin_ia32_vphaddubq", + "llvm.x86.xop.vphaddubw" => "__builtin_ia32_vphaddubw", + "llvm.x86.xop.vphaddudq" => "__builtin_ia32_vphaddudq", + "llvm.x86.xop.vphadduwd" => "__builtin_ia32_vphadduwd", + "llvm.x86.xop.vphadduwq" => "__builtin_ia32_vphadduwq", + "llvm.x86.xop.vphaddwd" => "__builtin_ia32_vphaddwd", + "llvm.x86.xop.vphaddwq" => "__builtin_ia32_vphaddwq", + "llvm.x86.xop.vphsubbw" => "__builtin_ia32_vphsubbw", + "llvm.x86.xop.vphsubdq" => "__builtin_ia32_vphsubdq", + "llvm.x86.xop.vphsubwd" => "__builtin_ia32_vphsubwd", + "llvm.x86.xop.vpmacsdd" => "__builtin_ia32_vpmacsdd", + "llvm.x86.xop.vpmacsdqh" => "__builtin_ia32_vpmacsdqh", + "llvm.x86.xop.vpmacsdql" => "__builtin_ia32_vpmacsdql", + "llvm.x86.xop.vpmacssdd" => "__builtin_ia32_vpmacssdd", + "llvm.x86.xop.vpmacssdqh" => "__builtin_ia32_vpmacssdqh", + "llvm.x86.xop.vpmacssdql" => "__builtin_ia32_vpmacssdql", + "llvm.x86.xop.vpmacsswd" => "__builtin_ia32_vpmacsswd", + "llvm.x86.xop.vpmacssww" => "__builtin_ia32_vpmacssww", + "llvm.x86.xop.vpmacswd" => "__builtin_ia32_vpmacswd", + "llvm.x86.xop.vpmacsww" => "__builtin_ia32_vpmacsww", + "llvm.x86.xop.vpmadcsswd" => "__builtin_ia32_vpmadcsswd", + "llvm.x86.xop.vpmadcswd" => "__builtin_ia32_vpmadcswd", + "llvm.x86.xop.vpperm" => "__builtin_ia32_vpperm", + "llvm.x86.xop.vprotb" => "__builtin_ia32_vprotb", + "llvm.x86.xop.vprotbi" => "__builtin_ia32_vprotbi", + "llvm.x86.xop.vprotd" => "__builtin_ia32_vprotd", + "llvm.x86.xop.vprotdi" => "__builtin_ia32_vprotdi", + "llvm.x86.xop.vprotq" => "__builtin_ia32_vprotq", + "llvm.x86.xop.vprotqi" => "__builtin_ia32_vprotqi", + "llvm.x86.xop.vprotw" => "__builtin_ia32_vprotw", + "llvm.x86.xop.vprotwi" => "__builtin_ia32_vprotwi", + "llvm.x86.xop.vpshab" => "__builtin_ia32_vpshab", + "llvm.x86.xop.vpshad" => "__builtin_ia32_vpshad", + "llvm.x86.xop.vpshaq" => "__builtin_ia32_vpshaq", + "llvm.x86.xop.vpshaw" => "__builtin_ia32_vpshaw", + "llvm.x86.xop.vpshlb" => "__builtin_ia32_vpshlb", + "llvm.x86.xop.vpshld" => "__builtin_ia32_vpshld", + "llvm.x86.xop.vpshlq" => "__builtin_ia32_vpshlq", + "llvm.x86.xop.vpshlw" => "__builtin_ia32_vpshlw", + "llvm.x86.xtest" => "__builtin_ia32_xtest", + // AMDGPU + "llvm.AMDGPU.div.fixup.f32" => "__builtin_amdgpu_div_fixup", + "llvm.AMDGPU.div.fixup.f64" => "__builtin_amdgpu_div_fixup", + "llvm.AMDGPU.div.fixup.v2f64" => "__builtin_amdgpu_div_fixup", + "llvm.AMDGPU.div.fixup.v4f32" => "__builtin_amdgpu_div_fixup", + "llvm.AMDGPU.div.fmas.f32" => "__builtin_amdgpu_div_fmas", + "llvm.AMDGPU.div.fmas.f64" => "__builtin_amdgpu_div_fmas", + "llvm.AMDGPU.div.fmas.v2f64" => "__builtin_amdgpu_div_fmas", + "llvm.AMDGPU.div.fmas.v4f32" => "__builtin_amdgpu_div_fmas", + "llvm.AMDGPU.ldexp.f32" => "__builtin_amdgpu_ldexp", + "llvm.AMDGPU.ldexp.f64" => "__builtin_amdgpu_ldexp", + "llvm.AMDGPU.ldexp.v2f64" => "__builtin_amdgpu_ldexp", + "llvm.AMDGPU.ldexp.v4f32" => "__builtin_amdgpu_ldexp", + "llvm.AMDGPU.rcp.f32" => "__builtin_amdgpu_rcp", + "llvm.AMDGPU.rcp.f64" => "__builtin_amdgpu_rcp", + "llvm.AMDGPU.rcp.v2f64" => "__builtin_amdgpu_rcp", + "llvm.AMDGPU.rcp.v4f32" => "__builtin_amdgpu_rcp", + "llvm.AMDGPU.rsq.clamped.f32" => "__builtin_amdgpu_rsq_clamped", + "llvm.AMDGPU.rsq.clamped.f64" => "__builtin_amdgpu_rsq_clamped", + "llvm.AMDGPU.rsq.clamped.v2f64" => "__builtin_amdgpu_rsq_clamped", + "llvm.AMDGPU.rsq.clamped.v4f32" => "__builtin_amdgpu_rsq_clamped", + "llvm.AMDGPU.rsq.f32" => "__builtin_amdgpu_rsq", + "llvm.AMDGPU.rsq.f64" => "__builtin_amdgpu_rsq", + "llvm.AMDGPU.rsq.v2f64" => "__builtin_amdgpu_rsq", + "llvm.AMDGPU.rsq.v4f32" => "__builtin_amdgpu_rsq", + "llvm.AMDGPU.trig.preop.f32" => "__builtin_amdgpu_trig_preop", + "llvm.AMDGPU.trig.preop.f64" => "__builtin_amdgpu_trig_preop", + "llvm.AMDGPU.trig.preop.v2f64" => "__builtin_amdgpu_trig_preop", + "llvm.AMDGPU.trig.preop.v4f32" => "__builtin_amdgpu_trig_preop", + // mips + "llvm.mips.add.a.b" => "__builtin_msa_add_a_b", + "llvm.mips.add.a.d" => "__builtin_msa_add_a_d", + "llvm.mips.add.a.h" => "__builtin_msa_add_a_h", + "llvm.mips.add.a.w" => "__builtin_msa_add_a_w", + "llvm.mips.adds.a.b" => "__builtin_msa_adds_a_b", + "llvm.mips.adds.a.d" => "__builtin_msa_adds_a_d", + "llvm.mips.adds.a.h" => "__builtin_msa_adds_a_h", + "llvm.mips.adds.a.w" => "__builtin_msa_adds_a_w", + "llvm.mips.adds.s.b" => "__builtin_msa_adds_s_b", + "llvm.mips.adds.s.d" => "__builtin_msa_adds_s_d", + "llvm.mips.adds.s.h" => "__builtin_msa_adds_s_h", + "llvm.mips.adds.s.w" => "__builtin_msa_adds_s_w", + "llvm.mips.adds.u.b" => "__builtin_msa_adds_u_b", + "llvm.mips.adds.u.d" => "__builtin_msa_adds_u_d", + "llvm.mips.adds.u.h" => "__builtin_msa_adds_u_h", + "llvm.mips.adds.u.w" => "__builtin_msa_adds_u_w", + "llvm.mips.addsc" => "__builtin_mips_addsc", + "llvm.mips.addu.ph" => "__builtin_mips_addu_ph", + "llvm.mips.addu.qb" => "__builtin_mips_addu_qb", + "llvm.mips.addu.s.ph" => "__builtin_mips_addu_s_ph", + "llvm.mips.addu.s.qb" => "__builtin_mips_addu_s_qb", + "llvm.mips.adduh.qb" => "__builtin_mips_adduh_qb", + "llvm.mips.adduh.r.qb" => "__builtin_mips_adduh_r_qb", + "llvm.mips.addv.b" => "__builtin_msa_addv_b", + "llvm.mips.addv.d" => "__builtin_msa_addv_d", + "llvm.mips.addv.h" => "__builtin_msa_addv_h", + "llvm.mips.addv.w" => "__builtin_msa_addv_w", + "llvm.mips.addvi.b" => "__builtin_msa_addvi_b", + "llvm.mips.addvi.d" => "__builtin_msa_addvi_d", + "llvm.mips.addvi.h" => "__builtin_msa_addvi_h", + "llvm.mips.addvi.w" => "__builtin_msa_addvi_w", + "llvm.mips.addwc" => "__builtin_mips_addwc", + "llvm.mips.and.v" => "__builtin_msa_and_v", + "llvm.mips.andi.b" => "__builtin_msa_andi_b", + "llvm.mips.append" => "__builtin_mips_append", + "llvm.mips.asub.s.b" => "__builtin_msa_asub_s_b", + "llvm.mips.asub.s.d" => "__builtin_msa_asub_s_d", + "llvm.mips.asub.s.h" => "__builtin_msa_asub_s_h", + "llvm.mips.asub.s.w" => "__builtin_msa_asub_s_w", + "llvm.mips.asub.u.b" => "__builtin_msa_asub_u_b", + "llvm.mips.asub.u.d" => "__builtin_msa_asub_u_d", + "llvm.mips.asub.u.h" => "__builtin_msa_asub_u_h", + "llvm.mips.asub.u.w" => "__builtin_msa_asub_u_w", + "llvm.mips.ave.s.b" => "__builtin_msa_ave_s_b", + "llvm.mips.ave.s.d" => "__builtin_msa_ave_s_d", + "llvm.mips.ave.s.h" => "__builtin_msa_ave_s_h", + "llvm.mips.ave.s.w" => "__builtin_msa_ave_s_w", + "llvm.mips.ave.u.b" => "__builtin_msa_ave_u_b", + "llvm.mips.ave.u.d" => "__builtin_msa_ave_u_d", + "llvm.mips.ave.u.h" => "__builtin_msa_ave_u_h", + "llvm.mips.ave.u.w" => "__builtin_msa_ave_u_w", + "llvm.mips.aver.s.b" => "__builtin_msa_aver_s_b", + "llvm.mips.aver.s.d" => "__builtin_msa_aver_s_d", + "llvm.mips.aver.s.h" => "__builtin_msa_aver_s_h", + "llvm.mips.aver.s.w" => "__builtin_msa_aver_s_w", + "llvm.mips.aver.u.b" => "__builtin_msa_aver_u_b", + "llvm.mips.aver.u.d" => "__builtin_msa_aver_u_d", + "llvm.mips.aver.u.h" => "__builtin_msa_aver_u_h", + "llvm.mips.aver.u.w" => "__builtin_msa_aver_u_w", + "llvm.mips.balign" => "__builtin_mips_balign", + "llvm.mips.bclr.b" => "__builtin_msa_bclr_b", + "llvm.mips.bclr.d" => "__builtin_msa_bclr_d", + "llvm.mips.bclr.h" => "__builtin_msa_bclr_h", + "llvm.mips.bclr.w" => "__builtin_msa_bclr_w", + "llvm.mips.bclri.b" => "__builtin_msa_bclri_b", + "llvm.mips.bclri.d" => "__builtin_msa_bclri_d", + "llvm.mips.bclri.h" => "__builtin_msa_bclri_h", + "llvm.mips.bclri.w" => "__builtin_msa_bclri_w", + "llvm.mips.binsl.b" => "__builtin_msa_binsl_b", + "llvm.mips.binsl.d" => "__builtin_msa_binsl_d", + "llvm.mips.binsl.h" => "__builtin_msa_binsl_h", + "llvm.mips.binsl.w" => "__builtin_msa_binsl_w", + "llvm.mips.binsli.b" => "__builtin_msa_binsli_b", + "llvm.mips.binsli.d" => "__builtin_msa_binsli_d", + "llvm.mips.binsli.h" => "__builtin_msa_binsli_h", + "llvm.mips.binsli.w" => "__builtin_msa_binsli_w", + "llvm.mips.binsr.b" => "__builtin_msa_binsr_b", + "llvm.mips.binsr.d" => "__builtin_msa_binsr_d", + "llvm.mips.binsr.h" => "__builtin_msa_binsr_h", + "llvm.mips.binsr.w" => "__builtin_msa_binsr_w", + "llvm.mips.binsri.b" => "__builtin_msa_binsri_b", + "llvm.mips.binsri.d" => "__builtin_msa_binsri_d", + "llvm.mips.binsri.h" => "__builtin_msa_binsri_h", + "llvm.mips.binsri.w" => "__builtin_msa_binsri_w", + "llvm.mips.bitrev" => "__builtin_mips_bitrev", + "llvm.mips.bmnz.v" => "__builtin_msa_bmnz_v", + "llvm.mips.bmnzi.b" => "__builtin_msa_bmnzi_b", + "llvm.mips.bmz.v" => "__builtin_msa_bmz_v", + "llvm.mips.bmzi.b" => "__builtin_msa_bmzi_b", + "llvm.mips.bneg.b" => "__builtin_msa_bneg_b", + "llvm.mips.bneg.d" => "__builtin_msa_bneg_d", + "llvm.mips.bneg.h" => "__builtin_msa_bneg_h", + "llvm.mips.bneg.w" => "__builtin_msa_bneg_w", + "llvm.mips.bnegi.b" => "__builtin_msa_bnegi_b", + "llvm.mips.bnegi.d" => "__builtin_msa_bnegi_d", + "llvm.mips.bnegi.h" => "__builtin_msa_bnegi_h", + "llvm.mips.bnegi.w" => "__builtin_msa_bnegi_w", + "llvm.mips.bnz.b" => "__builtin_msa_bnz_b", + "llvm.mips.bnz.d" => "__builtin_msa_bnz_d", + "llvm.mips.bnz.h" => "__builtin_msa_bnz_h", + "llvm.mips.bnz.v" => "__builtin_msa_bnz_v", + "llvm.mips.bnz.w" => "__builtin_msa_bnz_w", + "llvm.mips.bposge32" => "__builtin_mips_bposge32", + "llvm.mips.bsel.v" => "__builtin_msa_bsel_v", + "llvm.mips.bseli.b" => "__builtin_msa_bseli_b", + "llvm.mips.bset.b" => "__builtin_msa_bset_b", + "llvm.mips.bset.d" => "__builtin_msa_bset_d", + "llvm.mips.bset.h" => "__builtin_msa_bset_h", + "llvm.mips.bset.w" => "__builtin_msa_bset_w", + "llvm.mips.bseti.b" => "__builtin_msa_bseti_b", + "llvm.mips.bseti.d" => "__builtin_msa_bseti_d", + "llvm.mips.bseti.h" => "__builtin_msa_bseti_h", + "llvm.mips.bseti.w" => "__builtin_msa_bseti_w", + "llvm.mips.bz.b" => "__builtin_msa_bz_b", + "llvm.mips.bz.d" => "__builtin_msa_bz_d", + "llvm.mips.bz.h" => "__builtin_msa_bz_h", + "llvm.mips.bz.v" => "__builtin_msa_bz_v", + "llvm.mips.bz.w" => "__builtin_msa_bz_w", + "llvm.mips.ceq.b" => "__builtin_msa_ceq_b", + "llvm.mips.ceq.d" => "__builtin_msa_ceq_d", + "llvm.mips.ceq.h" => "__builtin_msa_ceq_h", + "llvm.mips.ceq.w" => "__builtin_msa_ceq_w", + "llvm.mips.ceqi.b" => "__builtin_msa_ceqi_b", + "llvm.mips.ceqi.d" => "__builtin_msa_ceqi_d", + "llvm.mips.ceqi.h" => "__builtin_msa_ceqi_h", + "llvm.mips.ceqi.w" => "__builtin_msa_ceqi_w", + "llvm.mips.cfcmsa" => "__builtin_msa_cfcmsa", + "llvm.mips.cle.s.b" => "__builtin_msa_cle_s_b", + "llvm.mips.cle.s.d" => "__builtin_msa_cle_s_d", + "llvm.mips.cle.s.h" => "__builtin_msa_cle_s_h", + "llvm.mips.cle.s.w" => "__builtin_msa_cle_s_w", + "llvm.mips.cle.u.b" => "__builtin_msa_cle_u_b", + "llvm.mips.cle.u.d" => "__builtin_msa_cle_u_d", + "llvm.mips.cle.u.h" => "__builtin_msa_cle_u_h", + "llvm.mips.cle.u.w" => "__builtin_msa_cle_u_w", + "llvm.mips.clei.s.b" => "__builtin_msa_clei_s_b", + "llvm.mips.clei.s.d" => "__builtin_msa_clei_s_d", + "llvm.mips.clei.s.h" => "__builtin_msa_clei_s_h", + "llvm.mips.clei.s.w" => "__builtin_msa_clei_s_w", + "llvm.mips.clei.u.b" => "__builtin_msa_clei_u_b", + "llvm.mips.clei.u.d" => "__builtin_msa_clei_u_d", + "llvm.mips.clei.u.h" => "__builtin_msa_clei_u_h", + "llvm.mips.clei.u.w" => "__builtin_msa_clei_u_w", + "llvm.mips.clt.s.b" => "__builtin_msa_clt_s_b", + "llvm.mips.clt.s.d" => "__builtin_msa_clt_s_d", + "llvm.mips.clt.s.h" => "__builtin_msa_clt_s_h", + "llvm.mips.clt.s.w" => "__builtin_msa_clt_s_w", + "llvm.mips.clt.u.b" => "__builtin_msa_clt_u_b", + "llvm.mips.clt.u.d" => "__builtin_msa_clt_u_d", + "llvm.mips.clt.u.h" => "__builtin_msa_clt_u_h", + "llvm.mips.clt.u.w" => "__builtin_msa_clt_u_w", + "llvm.mips.clti.s.b" => "__builtin_msa_clti_s_b", + "llvm.mips.clti.s.d" => "__builtin_msa_clti_s_d", + "llvm.mips.clti.s.h" => "__builtin_msa_clti_s_h", + "llvm.mips.clti.s.w" => "__builtin_msa_clti_s_w", + "llvm.mips.clti.u.b" => "__builtin_msa_clti_u_b", + "llvm.mips.clti.u.d" => "__builtin_msa_clti_u_d", + "llvm.mips.clti.u.h" => "__builtin_msa_clti_u_h", + "llvm.mips.clti.u.w" => "__builtin_msa_clti_u_w", + "llvm.mips.cmpgdu.eq.qb" => "__builtin_mips_cmpgdu_eq_qb", + "llvm.mips.cmpgdu.le.qb" => "__builtin_mips_cmpgdu_le_qb", + "llvm.mips.cmpgdu.lt.qb" => "__builtin_mips_cmpgdu_lt_qb", + "llvm.mips.cmpgu.eq.qb" => "__builtin_mips_cmpgu_eq_qb", + "llvm.mips.cmpgu.le.qb" => "__builtin_mips_cmpgu_le_qb", + "llvm.mips.cmpgu.lt.qb" => "__builtin_mips_cmpgu_lt_qb", + "llvm.mips.cmpu.eq.qb" => "__builtin_mips_cmpu_eq_qb", + "llvm.mips.cmpu.le.qb" => "__builtin_mips_cmpu_le_qb", + "llvm.mips.cmpu.lt.qb" => "__builtin_mips_cmpu_lt_qb", + "llvm.mips.copy.s.b" => "__builtin_msa_copy_s_b", + "llvm.mips.copy.s.d" => "__builtin_msa_copy_s_d", + "llvm.mips.copy.s.h" => "__builtin_msa_copy_s_h", + "llvm.mips.copy.s.w" => "__builtin_msa_copy_s_w", + "llvm.mips.copy.u.b" => "__builtin_msa_copy_u_b", + "llvm.mips.copy.u.d" => "__builtin_msa_copy_u_d", + "llvm.mips.copy.u.h" => "__builtin_msa_copy_u_h", + "llvm.mips.copy.u.w" => "__builtin_msa_copy_u_w", + "llvm.mips.ctcmsa" => "__builtin_msa_ctcmsa", + "llvm.mips.div.s.b" => "__builtin_msa_div_s_b", + "llvm.mips.div.s.d" => "__builtin_msa_div_s_d", + "llvm.mips.div.s.h" => "__builtin_msa_div_s_h", + "llvm.mips.div.s.w" => "__builtin_msa_div_s_w", + "llvm.mips.div.u.b" => "__builtin_msa_div_u_b", + "llvm.mips.div.u.d" => "__builtin_msa_div_u_d", + "llvm.mips.div.u.h" => "__builtin_msa_div_u_h", + "llvm.mips.div.u.w" => "__builtin_msa_div_u_w", + "llvm.mips.dlsa" => "__builtin_mips_dlsa", + "llvm.mips.dotp.s.d" => "__builtin_msa_dotp_s_d", + "llvm.mips.dotp.s.h" => "__builtin_msa_dotp_s_h", + "llvm.mips.dotp.s.w" => "__builtin_msa_dotp_s_w", + "llvm.mips.dotp.u.d" => "__builtin_msa_dotp_u_d", + "llvm.mips.dotp.u.h" => "__builtin_msa_dotp_u_h", + "llvm.mips.dotp.u.w" => "__builtin_msa_dotp_u_w", + "llvm.mips.dpa.w.ph" => "__builtin_mips_dpa_w_ph", + "llvm.mips.dpadd.s.d" => "__builtin_msa_dpadd_s_d", + "llvm.mips.dpadd.s.h" => "__builtin_msa_dpadd_s_h", + "llvm.mips.dpadd.s.w" => "__builtin_msa_dpadd_s_w", + "llvm.mips.dpadd.u.d" => "__builtin_msa_dpadd_u_d", + "llvm.mips.dpadd.u.h" => "__builtin_msa_dpadd_u_h", + "llvm.mips.dpadd.u.w" => "__builtin_msa_dpadd_u_w", + "llvm.mips.dpau.h.qbl" => "__builtin_mips_dpau_h_qbl", + "llvm.mips.dpau.h.qbr" => "__builtin_mips_dpau_h_qbr", + "llvm.mips.dpax.w.ph" => "__builtin_mips_dpax_w_ph", + "llvm.mips.dps.w.ph" => "__builtin_mips_dps_w_ph", + "llvm.mips.dpsu.h.qbl" => "__builtin_mips_dpsu_h_qbl", + "llvm.mips.dpsu.h.qbr" => "__builtin_mips_dpsu_h_qbr", + "llvm.mips.dpsub.s.d" => "__builtin_msa_dpsub_s_d", + "llvm.mips.dpsub.s.h" => "__builtin_msa_dpsub_s_h", + "llvm.mips.dpsub.s.w" => "__builtin_msa_dpsub_s_w", + "llvm.mips.dpsub.u.d" => "__builtin_msa_dpsub_u_d", + "llvm.mips.dpsub.u.h" => "__builtin_msa_dpsub_u_h", + "llvm.mips.dpsub.u.w" => "__builtin_msa_dpsub_u_w", + "llvm.mips.dpsx.w.ph" => "__builtin_mips_dpsx_w_ph", + "llvm.mips.extp" => "__builtin_mips_extp", + "llvm.mips.extpdp" => "__builtin_mips_extpdp", + "llvm.mips.extr.r.w" => "__builtin_mips_extr_r_w", + "llvm.mips.extr.rs.w" => "__builtin_mips_extr_rs_w", + "llvm.mips.extr.s.h" => "__builtin_mips_extr_s_h", + "llvm.mips.extr.w" => "__builtin_mips_extr_w", + "llvm.mips.fadd.d" => "__builtin_msa_fadd_d", + "llvm.mips.fadd.w" => "__builtin_msa_fadd_w", + "llvm.mips.fcaf.d" => "__builtin_msa_fcaf_d", + "llvm.mips.fcaf.w" => "__builtin_msa_fcaf_w", + "llvm.mips.fceq.d" => "__builtin_msa_fceq_d", + "llvm.mips.fceq.w" => "__builtin_msa_fceq_w", + "llvm.mips.fclass.d" => "__builtin_msa_fclass_d", + "llvm.mips.fclass.w" => "__builtin_msa_fclass_w", + "llvm.mips.fcle.d" => "__builtin_msa_fcle_d", + "llvm.mips.fcle.w" => "__builtin_msa_fcle_w", + "llvm.mips.fclt.d" => "__builtin_msa_fclt_d", + "llvm.mips.fclt.w" => "__builtin_msa_fclt_w", + "llvm.mips.fcne.d" => "__builtin_msa_fcne_d", + "llvm.mips.fcne.w" => "__builtin_msa_fcne_w", + "llvm.mips.fcor.d" => "__builtin_msa_fcor_d", + "llvm.mips.fcor.w" => "__builtin_msa_fcor_w", + "llvm.mips.fcueq.d" => "__builtin_msa_fcueq_d", + "llvm.mips.fcueq.w" => "__builtin_msa_fcueq_w", + "llvm.mips.fcule.d" => "__builtin_msa_fcule_d", + "llvm.mips.fcule.w" => "__builtin_msa_fcule_w", + "llvm.mips.fcult.d" => "__builtin_msa_fcult_d", + "llvm.mips.fcult.w" => "__builtin_msa_fcult_w", + "llvm.mips.fcun.d" => "__builtin_msa_fcun_d", + "llvm.mips.fcun.w" => "__builtin_msa_fcun_w", + "llvm.mips.fcune.d" => "__builtin_msa_fcune_d", + "llvm.mips.fcune.w" => "__builtin_msa_fcune_w", + "llvm.mips.fdiv.d" => "__builtin_msa_fdiv_d", + "llvm.mips.fdiv.w" => "__builtin_msa_fdiv_w", + "llvm.mips.fexdo.w" => "__builtin_msa_fexdo_w", + "llvm.mips.fexp2.d" => "__builtin_msa_fexp2_d", + "llvm.mips.fexp2.w" => "__builtin_msa_fexp2_w", + "llvm.mips.fexupl.d" => "__builtin_msa_fexupl_d", + "llvm.mips.fexupr.d" => "__builtin_msa_fexupr_d", + "llvm.mips.ffint.s.d" => "__builtin_msa_ffint_s_d", + "llvm.mips.ffint.s.w" => "__builtin_msa_ffint_s_w", + "llvm.mips.ffint.u.d" => "__builtin_msa_ffint_u_d", + "llvm.mips.ffint.u.w" => "__builtin_msa_ffint_u_w", + "llvm.mips.ffql.d" => "__builtin_msa_ffql_d", + "llvm.mips.ffql.w" => "__builtin_msa_ffql_w", + "llvm.mips.ffqr.d" => "__builtin_msa_ffqr_d", + "llvm.mips.ffqr.w" => "__builtin_msa_ffqr_w", + "llvm.mips.fill.b" => "__builtin_msa_fill_b", + "llvm.mips.fill.d" => "__builtin_msa_fill_d", + "llvm.mips.fill.h" => "__builtin_msa_fill_h", + "llvm.mips.fill.w" => "__builtin_msa_fill_w", + "llvm.mips.flog2.d" => "__builtin_msa_flog2_d", + "llvm.mips.flog2.w" => "__builtin_msa_flog2_w", + "llvm.mips.fmadd.d" => "__builtin_msa_fmadd_d", + "llvm.mips.fmadd.w" => "__builtin_msa_fmadd_w", + "llvm.mips.fmax.a.d" => "__builtin_msa_fmax_a_d", + "llvm.mips.fmax.a.w" => "__builtin_msa_fmax_a_w", + "llvm.mips.fmax.d" => "__builtin_msa_fmax_d", + "llvm.mips.fmax.w" => "__builtin_msa_fmax_w", + "llvm.mips.fmin.a.d" => "__builtin_msa_fmin_a_d", + "llvm.mips.fmin.a.w" => "__builtin_msa_fmin_a_w", + "llvm.mips.fmin.d" => "__builtin_msa_fmin_d", + "llvm.mips.fmin.w" => "__builtin_msa_fmin_w", + "llvm.mips.fmsub.d" => "__builtin_msa_fmsub_d", + "llvm.mips.fmsub.w" => "__builtin_msa_fmsub_w", + "llvm.mips.fmul.d" => "__builtin_msa_fmul_d", + "llvm.mips.fmul.w" => "__builtin_msa_fmul_w", + "llvm.mips.frcp.d" => "__builtin_msa_frcp_d", + "llvm.mips.frcp.w" => "__builtin_msa_frcp_w", + "llvm.mips.frint.d" => "__builtin_msa_frint_d", + "llvm.mips.frint.w" => "__builtin_msa_frint_w", + "llvm.mips.frsqrt.d" => "__builtin_msa_frsqrt_d", + "llvm.mips.frsqrt.w" => "__builtin_msa_frsqrt_w", + "llvm.mips.fsaf.d" => "__builtin_msa_fsaf_d", + "llvm.mips.fsaf.w" => "__builtin_msa_fsaf_w", + "llvm.mips.fseq.d" => "__builtin_msa_fseq_d", + "llvm.mips.fseq.w" => "__builtin_msa_fseq_w", + "llvm.mips.fsle.d" => "__builtin_msa_fsle_d", + "llvm.mips.fsle.w" => "__builtin_msa_fsle_w", + "llvm.mips.fslt.d" => "__builtin_msa_fslt_d", + "llvm.mips.fslt.w" => "__builtin_msa_fslt_w", + "llvm.mips.fsne.d" => "__builtin_msa_fsne_d", + "llvm.mips.fsne.w" => "__builtin_msa_fsne_w", + "llvm.mips.fsor.d" => "__builtin_msa_fsor_d", + "llvm.mips.fsor.w" => "__builtin_msa_fsor_w", + "llvm.mips.fsqrt.d" => "__builtin_msa_fsqrt_d", + "llvm.mips.fsqrt.w" => "__builtin_msa_fsqrt_w", + "llvm.mips.fsub.d" => "__builtin_msa_fsub_d", + "llvm.mips.fsub.w" => "__builtin_msa_fsub_w", + "llvm.mips.fsueq.d" => "__builtin_msa_fsueq_d", + "llvm.mips.fsueq.w" => "__builtin_msa_fsueq_w", + "llvm.mips.fsule.d" => "__builtin_msa_fsule_d", + "llvm.mips.fsule.w" => "__builtin_msa_fsule_w", + "llvm.mips.fsult.d" => "__builtin_msa_fsult_d", + "llvm.mips.fsult.w" => "__builtin_msa_fsult_w", + "llvm.mips.fsun.d" => "__builtin_msa_fsun_d", + "llvm.mips.fsun.w" => "__builtin_msa_fsun_w", + "llvm.mips.fsune.d" => "__builtin_msa_fsune_d", + "llvm.mips.fsune.w" => "__builtin_msa_fsune_w", + "llvm.mips.ftint.s.d" => "__builtin_msa_ftint_s_d", + "llvm.mips.ftint.s.w" => "__builtin_msa_ftint_s_w", + "llvm.mips.ftint.u.d" => "__builtin_msa_ftint_u_d", + "llvm.mips.ftint.u.w" => "__builtin_msa_ftint_u_w", + "llvm.mips.ftq.h" => "__builtin_msa_ftq_h", + "llvm.mips.ftq.w" => "__builtin_msa_ftq_w", + "llvm.mips.ftrunc.s.d" => "__builtin_msa_ftrunc_s_d", + "llvm.mips.ftrunc.s.w" => "__builtin_msa_ftrunc_s_w", + "llvm.mips.ftrunc.u.d" => "__builtin_msa_ftrunc_u_d", + "llvm.mips.ftrunc.u.w" => "__builtin_msa_ftrunc_u_w", + "llvm.mips.hadd.s.d" => "__builtin_msa_hadd_s_d", + "llvm.mips.hadd.s.h" => "__builtin_msa_hadd_s_h", + "llvm.mips.hadd.s.w" => "__builtin_msa_hadd_s_w", + "llvm.mips.hadd.u.d" => "__builtin_msa_hadd_u_d", + "llvm.mips.hadd.u.h" => "__builtin_msa_hadd_u_h", + "llvm.mips.hadd.u.w" => "__builtin_msa_hadd_u_w", + "llvm.mips.hsub.s.d" => "__builtin_msa_hsub_s_d", + "llvm.mips.hsub.s.h" => "__builtin_msa_hsub_s_h", + "llvm.mips.hsub.s.w" => "__builtin_msa_hsub_s_w", + "llvm.mips.hsub.u.d" => "__builtin_msa_hsub_u_d", + "llvm.mips.hsub.u.h" => "__builtin_msa_hsub_u_h", + "llvm.mips.hsub.u.w" => "__builtin_msa_hsub_u_w", + "llvm.mips.ilvev.b" => "__builtin_msa_ilvev_b", + "llvm.mips.ilvev.d" => "__builtin_msa_ilvev_d", + "llvm.mips.ilvev.h" => "__builtin_msa_ilvev_h", + "llvm.mips.ilvev.w" => "__builtin_msa_ilvev_w", + "llvm.mips.ilvl.b" => "__builtin_msa_ilvl_b", + "llvm.mips.ilvl.d" => "__builtin_msa_ilvl_d", + "llvm.mips.ilvl.h" => "__builtin_msa_ilvl_h", + "llvm.mips.ilvl.w" => "__builtin_msa_ilvl_w", + "llvm.mips.ilvod.b" => "__builtin_msa_ilvod_b", + "llvm.mips.ilvod.d" => "__builtin_msa_ilvod_d", + "llvm.mips.ilvod.h" => "__builtin_msa_ilvod_h", + "llvm.mips.ilvod.w" => "__builtin_msa_ilvod_w", + "llvm.mips.ilvr.b" => "__builtin_msa_ilvr_b", + "llvm.mips.ilvr.d" => "__builtin_msa_ilvr_d", + "llvm.mips.ilvr.h" => "__builtin_msa_ilvr_h", + "llvm.mips.ilvr.w" => "__builtin_msa_ilvr_w", + "llvm.mips.insert.b" => "__builtin_msa_insert_b", + "llvm.mips.insert.d" => "__builtin_msa_insert_d", + "llvm.mips.insert.h" => "__builtin_msa_insert_h", + "llvm.mips.insert.w" => "__builtin_msa_insert_w", + "llvm.mips.insv" => "__builtin_mips_insv", + "llvm.mips.insve.b" => "__builtin_msa_insve_b", + "llvm.mips.insve.d" => "__builtin_msa_insve_d", + "llvm.mips.insve.h" => "__builtin_msa_insve_h", + "llvm.mips.insve.w" => "__builtin_msa_insve_w", + "llvm.mips.lbux" => "__builtin_mips_lbux", + "llvm.mips.ld.b" => "__builtin_msa_ld_b", + "llvm.mips.ld.d" => "__builtin_msa_ld_d", + "llvm.mips.ld.h" => "__builtin_msa_ld_h", + "llvm.mips.ld.w" => "__builtin_msa_ld_w", + "llvm.mips.ldi.b" => "__builtin_msa_ldi_b", + "llvm.mips.ldi.d" => "__builtin_msa_ldi_d", + "llvm.mips.ldi.h" => "__builtin_msa_ldi_h", + "llvm.mips.ldi.w" => "__builtin_msa_ldi_w", + "llvm.mips.lhx" => "__builtin_mips_lhx", + "llvm.mips.lsa" => "__builtin_mips_lsa", + "llvm.mips.lwx" => "__builtin_mips_lwx", + "llvm.mips.madd" => "__builtin_mips_madd", + "llvm.mips.madd.q.h" => "__builtin_msa_madd_q_h", + "llvm.mips.madd.q.w" => "__builtin_msa_madd_q_w", + "llvm.mips.maddr.q.h" => "__builtin_msa_maddr_q_h", + "llvm.mips.maddr.q.w" => "__builtin_msa_maddr_q_w", + "llvm.mips.maddu" => "__builtin_mips_maddu", + "llvm.mips.maddv.b" => "__builtin_msa_maddv_b", + "llvm.mips.maddv.d" => "__builtin_msa_maddv_d", + "llvm.mips.maddv.h" => "__builtin_msa_maddv_h", + "llvm.mips.maddv.w" => "__builtin_msa_maddv_w", + "llvm.mips.max.a.b" => "__builtin_msa_max_a_b", + "llvm.mips.max.a.d" => "__builtin_msa_max_a_d", + "llvm.mips.max.a.h" => "__builtin_msa_max_a_h", + "llvm.mips.max.a.w" => "__builtin_msa_max_a_w", + "llvm.mips.max.s.b" => "__builtin_msa_max_s_b", + "llvm.mips.max.s.d" => "__builtin_msa_max_s_d", + "llvm.mips.max.s.h" => "__builtin_msa_max_s_h", + "llvm.mips.max.s.w" => "__builtin_msa_max_s_w", + "llvm.mips.max.u.b" => "__builtin_msa_max_u_b", + "llvm.mips.max.u.d" => "__builtin_msa_max_u_d", + "llvm.mips.max.u.h" => "__builtin_msa_max_u_h", + "llvm.mips.max.u.w" => "__builtin_msa_max_u_w", + "llvm.mips.maxi.s.b" => "__builtin_msa_maxi_s_b", + "llvm.mips.maxi.s.d" => "__builtin_msa_maxi_s_d", + "llvm.mips.maxi.s.h" => "__builtin_msa_maxi_s_h", + "llvm.mips.maxi.s.w" => "__builtin_msa_maxi_s_w", + "llvm.mips.maxi.u.b" => "__builtin_msa_maxi_u_b", + "llvm.mips.maxi.u.d" => "__builtin_msa_maxi_u_d", + "llvm.mips.maxi.u.h" => "__builtin_msa_maxi_u_h", + "llvm.mips.maxi.u.w" => "__builtin_msa_maxi_u_w", + "llvm.mips.min.a.b" => "__builtin_msa_min_a_b", + "llvm.mips.min.a.d" => "__builtin_msa_min_a_d", + "llvm.mips.min.a.h" => "__builtin_msa_min_a_h", + "llvm.mips.min.a.w" => "__builtin_msa_min_a_w", + "llvm.mips.min.s.b" => "__builtin_msa_min_s_b", + "llvm.mips.min.s.d" => "__builtin_msa_min_s_d", + "llvm.mips.min.s.h" => "__builtin_msa_min_s_h", + "llvm.mips.min.s.w" => "__builtin_msa_min_s_w", + "llvm.mips.min.u.b" => "__builtin_msa_min_u_b", + "llvm.mips.min.u.d" => "__builtin_msa_min_u_d", + "llvm.mips.min.u.h" => "__builtin_msa_min_u_h", + "llvm.mips.min.u.w" => "__builtin_msa_min_u_w", + "llvm.mips.mini.s.b" => "__builtin_msa_mini_s_b", + "llvm.mips.mini.s.d" => "__builtin_msa_mini_s_d", + "llvm.mips.mini.s.h" => "__builtin_msa_mini_s_h", + "llvm.mips.mini.s.w" => "__builtin_msa_mini_s_w", + "llvm.mips.mini.u.b" => "__builtin_msa_mini_u_b", + "llvm.mips.mini.u.d" => "__builtin_msa_mini_u_d", + "llvm.mips.mini.u.h" => "__builtin_msa_mini_u_h", + "llvm.mips.mini.u.w" => "__builtin_msa_mini_u_w", + "llvm.mips.mod.s.b" => "__builtin_msa_mod_s_b", + "llvm.mips.mod.s.d" => "__builtin_msa_mod_s_d", + "llvm.mips.mod.s.h" => "__builtin_msa_mod_s_h", + "llvm.mips.mod.s.w" => "__builtin_msa_mod_s_w", + "llvm.mips.mod.u.b" => "__builtin_msa_mod_u_b", + "llvm.mips.mod.u.d" => "__builtin_msa_mod_u_d", + "llvm.mips.mod.u.h" => "__builtin_msa_mod_u_h", + "llvm.mips.mod.u.w" => "__builtin_msa_mod_u_w", + "llvm.mips.modsub" => "__builtin_mips_modsub", + "llvm.mips.move.v" => "__builtin_msa_move_v", + "llvm.mips.msub" => "__builtin_mips_msub", + "llvm.mips.msub.q.h" => "__builtin_msa_msub_q_h", + "llvm.mips.msub.q.w" => "__builtin_msa_msub_q_w", + "llvm.mips.msubr.q.h" => "__builtin_msa_msubr_q_h", + "llvm.mips.msubr.q.w" => "__builtin_msa_msubr_q_w", + "llvm.mips.msubu" => "__builtin_mips_msubu", + "llvm.mips.msubv.b" => "__builtin_msa_msubv_b", + "llvm.mips.msubv.d" => "__builtin_msa_msubv_d", + "llvm.mips.msubv.h" => "__builtin_msa_msubv_h", + "llvm.mips.msubv.w" => "__builtin_msa_msubv_w", + "llvm.mips.mthlip" => "__builtin_mips_mthlip", + "llvm.mips.mul.ph" => "__builtin_mips_mul_ph", + "llvm.mips.mul.q.h" => "__builtin_msa_mul_q_h", + "llvm.mips.mul.q.w" => "__builtin_msa_mul_q_w", + "llvm.mips.mul.s.ph" => "__builtin_mips_mul_s_ph", + "llvm.mips.mulr.q.h" => "__builtin_msa_mulr_q_h", + "llvm.mips.mulr.q.w" => "__builtin_msa_mulr_q_w", + "llvm.mips.mulsa.w.ph" => "__builtin_mips_mulsa_w_ph", + "llvm.mips.mult" => "__builtin_mips_mult", + "llvm.mips.multu" => "__builtin_mips_multu", + "llvm.mips.mulv.b" => "__builtin_msa_mulv_b", + "llvm.mips.mulv.d" => "__builtin_msa_mulv_d", + "llvm.mips.mulv.h" => "__builtin_msa_mulv_h", + "llvm.mips.mulv.w" => "__builtin_msa_mulv_w", + "llvm.mips.nloc.b" => "__builtin_msa_nloc_b", + "llvm.mips.nloc.d" => "__builtin_msa_nloc_d", + "llvm.mips.nloc.h" => "__builtin_msa_nloc_h", + "llvm.mips.nloc.w" => "__builtin_msa_nloc_w", + "llvm.mips.nlzc.b" => "__builtin_msa_nlzc_b", + "llvm.mips.nlzc.d" => "__builtin_msa_nlzc_d", + "llvm.mips.nlzc.h" => "__builtin_msa_nlzc_h", + "llvm.mips.nlzc.w" => "__builtin_msa_nlzc_w", + "llvm.mips.nor.v" => "__builtin_msa_nor_v", + "llvm.mips.nori.b" => "__builtin_msa_nori_b", + "llvm.mips.or.v" => "__builtin_msa_or_v", + "llvm.mips.ori.b" => "__builtin_msa_ori_b", + "llvm.mips.pckev.b" => "__builtin_msa_pckev_b", + "llvm.mips.pckev.d" => "__builtin_msa_pckev_d", + "llvm.mips.pckev.h" => "__builtin_msa_pckev_h", + "llvm.mips.pckev.w" => "__builtin_msa_pckev_w", + "llvm.mips.pckod.b" => "__builtin_msa_pckod_b", + "llvm.mips.pckod.d" => "__builtin_msa_pckod_d", + "llvm.mips.pckod.h" => "__builtin_msa_pckod_h", + "llvm.mips.pckod.w" => "__builtin_msa_pckod_w", + "llvm.mips.pcnt.b" => "__builtin_msa_pcnt_b", + "llvm.mips.pcnt.d" => "__builtin_msa_pcnt_d", + "llvm.mips.pcnt.h" => "__builtin_msa_pcnt_h", + "llvm.mips.pcnt.w" => "__builtin_msa_pcnt_w", + "llvm.mips.pick.qb" => "__builtin_mips_pick_qb", + "llvm.mips.precr.qb.ph" => "__builtin_mips_precr_qb_ph", + "llvm.mips.precr.sra.ph.w" => "__builtin_mips_precr_sra_ph_w", + "llvm.mips.precr.sra.r.ph.w" => "__builtin_mips_precr_sra_r_ph_w", + "llvm.mips.prepend" => "__builtin_mips_prepend", + "llvm.mips.raddu.w.qb" => "__builtin_mips_raddu_w_qb", + "llvm.mips.rddsp" => "__builtin_mips_rddsp", + "llvm.mips.repl.qb" => "__builtin_mips_repl_qb", + "llvm.mips.sat.s.b" => "__builtin_msa_sat_s_b", + "llvm.mips.sat.s.d" => "__builtin_msa_sat_s_d", + "llvm.mips.sat.s.h" => "__builtin_msa_sat_s_h", + "llvm.mips.sat.s.w" => "__builtin_msa_sat_s_w", + "llvm.mips.sat.u.b" => "__builtin_msa_sat_u_b", + "llvm.mips.sat.u.d" => "__builtin_msa_sat_u_d", + "llvm.mips.sat.u.h" => "__builtin_msa_sat_u_h", + "llvm.mips.sat.u.w" => "__builtin_msa_sat_u_w", + "llvm.mips.shf.b" => "__builtin_msa_shf_b", + "llvm.mips.shf.h" => "__builtin_msa_shf_h", + "llvm.mips.shf.w" => "__builtin_msa_shf_w", + "llvm.mips.shilo" => "__builtin_mips_shilo", + "llvm.mips.shll.qb" => "__builtin_mips_shll_qb", + "llvm.mips.shra.qb" => "__builtin_mips_shra_qb", + "llvm.mips.shra.r.qb" => "__builtin_mips_shra_r_qb", + "llvm.mips.shrl.ph" => "__builtin_mips_shrl_ph", + "llvm.mips.shrl.qb" => "__builtin_mips_shrl_qb", + "llvm.mips.sld.b" => "__builtin_msa_sld_b", + "llvm.mips.sld.d" => "__builtin_msa_sld_d", + "llvm.mips.sld.h" => "__builtin_msa_sld_h", + "llvm.mips.sld.w" => "__builtin_msa_sld_w", + "llvm.mips.sldi.b" => "__builtin_msa_sldi_b", + "llvm.mips.sldi.d" => "__builtin_msa_sldi_d", + "llvm.mips.sldi.h" => "__builtin_msa_sldi_h", + "llvm.mips.sldi.w" => "__builtin_msa_sldi_w", + "llvm.mips.sll.b" => "__builtin_msa_sll_b", + "llvm.mips.sll.d" => "__builtin_msa_sll_d", + "llvm.mips.sll.h" => "__builtin_msa_sll_h", + "llvm.mips.sll.w" => "__builtin_msa_sll_w", + "llvm.mips.slli.b" => "__builtin_msa_slli_b", + "llvm.mips.slli.d" => "__builtin_msa_slli_d", + "llvm.mips.slli.h" => "__builtin_msa_slli_h", + "llvm.mips.slli.w" => "__builtin_msa_slli_w", + "llvm.mips.splat.b" => "__builtin_msa_splat_b", + "llvm.mips.splat.d" => "__builtin_msa_splat_d", + "llvm.mips.splat.h" => "__builtin_msa_splat_h", + "llvm.mips.splat.w" => "__builtin_msa_splat_w", + "llvm.mips.splati.b" => "__builtin_msa_splati_b", + "llvm.mips.splati.d" => "__builtin_msa_splati_d", + "llvm.mips.splati.h" => "__builtin_msa_splati_h", + "llvm.mips.splati.w" => "__builtin_msa_splati_w", + "llvm.mips.sra.b" => "__builtin_msa_sra_b", + "llvm.mips.sra.d" => "__builtin_msa_sra_d", + "llvm.mips.sra.h" => "__builtin_msa_sra_h", + "llvm.mips.sra.w" => "__builtin_msa_sra_w", + "llvm.mips.srai.b" => "__builtin_msa_srai_b", + "llvm.mips.srai.d" => "__builtin_msa_srai_d", + "llvm.mips.srai.h" => "__builtin_msa_srai_h", + "llvm.mips.srai.w" => "__builtin_msa_srai_w", + "llvm.mips.srar.b" => "__builtin_msa_srar_b", + "llvm.mips.srar.d" => "__builtin_msa_srar_d", + "llvm.mips.srar.h" => "__builtin_msa_srar_h", + "llvm.mips.srar.w" => "__builtin_msa_srar_w", + "llvm.mips.srari.b" => "__builtin_msa_srari_b", + "llvm.mips.srari.d" => "__builtin_msa_srari_d", + "llvm.mips.srari.h" => "__builtin_msa_srari_h", + "llvm.mips.srari.w" => "__builtin_msa_srari_w", + "llvm.mips.srl.b" => "__builtin_msa_srl_b", + "llvm.mips.srl.d" => "__builtin_msa_srl_d", + "llvm.mips.srl.h" => "__builtin_msa_srl_h", + "llvm.mips.srl.w" => "__builtin_msa_srl_w", + "llvm.mips.srli.b" => "__builtin_msa_srli_b", + "llvm.mips.srli.d" => "__builtin_msa_srli_d", + "llvm.mips.srli.h" => "__builtin_msa_srli_h", + "llvm.mips.srli.w" => "__builtin_msa_srli_w", + "llvm.mips.srlr.b" => "__builtin_msa_srlr_b", + "llvm.mips.srlr.d" => "__builtin_msa_srlr_d", + "llvm.mips.srlr.h" => "__builtin_msa_srlr_h", + "llvm.mips.srlr.w" => "__builtin_msa_srlr_w", + "llvm.mips.srlri.b" => "__builtin_msa_srlri_b", + "llvm.mips.srlri.d" => "__builtin_msa_srlri_d", + "llvm.mips.srlri.h" => "__builtin_msa_srlri_h", + "llvm.mips.srlri.w" => "__builtin_msa_srlri_w", + "llvm.mips.st.b" => "__builtin_msa_st_b", + "llvm.mips.st.d" => "__builtin_msa_st_d", + "llvm.mips.st.h" => "__builtin_msa_st_h", + "llvm.mips.st.w" => "__builtin_msa_st_w", + "llvm.mips.subs.s.b" => "__builtin_msa_subs_s_b", + "llvm.mips.subs.s.d" => "__builtin_msa_subs_s_d", + "llvm.mips.subs.s.h" => "__builtin_msa_subs_s_h", + "llvm.mips.subs.s.w" => "__builtin_msa_subs_s_w", + "llvm.mips.subs.u.b" => "__builtin_msa_subs_u_b", + "llvm.mips.subs.u.d" => "__builtin_msa_subs_u_d", + "llvm.mips.subs.u.h" => "__builtin_msa_subs_u_h", + "llvm.mips.subs.u.w" => "__builtin_msa_subs_u_w", + "llvm.mips.subsus.u.b" => "__builtin_msa_subsus_u_b", + "llvm.mips.subsus.u.d" => "__builtin_msa_subsus_u_d", + "llvm.mips.subsus.u.h" => "__builtin_msa_subsus_u_h", + "llvm.mips.subsus.u.w" => "__builtin_msa_subsus_u_w", + "llvm.mips.subsuu.s.b" => "__builtin_msa_subsuu_s_b", + "llvm.mips.subsuu.s.d" => "__builtin_msa_subsuu_s_d", + "llvm.mips.subsuu.s.h" => "__builtin_msa_subsuu_s_h", + "llvm.mips.subsuu.s.w" => "__builtin_msa_subsuu_s_w", + "llvm.mips.subu.ph" => "__builtin_mips_subu_ph", + "llvm.mips.subu.qb" => "__builtin_mips_subu_qb", + "llvm.mips.subu.s.ph" => "__builtin_mips_subu_s_ph", + "llvm.mips.subu.s.qb" => "__builtin_mips_subu_s_qb", + "llvm.mips.subuh.qb" => "__builtin_mips_subuh_qb", + "llvm.mips.subuh.r.qb" => "__builtin_mips_subuh_r_qb", + "llvm.mips.subv.b" => "__builtin_msa_subv_b", + "llvm.mips.subv.d" => "__builtin_msa_subv_d", + "llvm.mips.subv.h" => "__builtin_msa_subv_h", + "llvm.mips.subv.w" => "__builtin_msa_subv_w", + "llvm.mips.subvi.b" => "__builtin_msa_subvi_b", + "llvm.mips.subvi.d" => "__builtin_msa_subvi_d", + "llvm.mips.subvi.h" => "__builtin_msa_subvi_h", + "llvm.mips.subvi.w" => "__builtin_msa_subvi_w", + "llvm.mips.vshf.b" => "__builtin_msa_vshf_b", + "llvm.mips.vshf.d" => "__builtin_msa_vshf_d", + "llvm.mips.vshf.h" => "__builtin_msa_vshf_h", + "llvm.mips.vshf.w" => "__builtin_msa_vshf_w", + "llvm.mips.wrdsp" => "__builtin_mips_wrdsp", + "llvm.mips.xor.v" => "__builtin_msa_xor_v", + "llvm.mips.xori.b" => "__builtin_msa_xori_b", + // xcore + "llvm.xcore.bitrev" => "__builtin_bitrev", + "llvm.xcore.getid" => "__builtin_getid", + "llvm.xcore.getps" => "__builtin_getps", + "llvm.xcore.setps" => "__builtin_setps", + // ptx + "llvm.ptx.bar.sync" => "__builtin_ptx_bar_sync", + "llvm.ptx.read.clock" => "__builtin_ptx_read_clock", + "llvm.ptx.read.clock64" => "__builtin_ptx_read_clock64", + "llvm.ptx.read.gridid" => "__builtin_ptx_read_gridid", + "llvm.ptx.read.laneid" => "__builtin_ptx_read_laneid", + "llvm.ptx.read.lanemask.eq" => "__builtin_ptx_read_lanemask_eq", + "llvm.ptx.read.lanemask.ge" => "__builtin_ptx_read_lanemask_ge", + "llvm.ptx.read.lanemask.gt" => "__builtin_ptx_read_lanemask_gt", + "llvm.ptx.read.lanemask.le" => "__builtin_ptx_read_lanemask_le", + "llvm.ptx.read.lanemask.lt" => "__builtin_ptx_read_lanemask_lt", + "llvm.ptx.read.nsmid" => "__builtin_ptx_read_nsmid", + "llvm.ptx.read.nwarpid" => "__builtin_ptx_read_nwarpid", + "llvm.ptx.read.pm0" => "__builtin_ptx_read_pm0", + "llvm.ptx.read.pm1" => "__builtin_ptx_read_pm1", + "llvm.ptx.read.pm2" => "__builtin_ptx_read_pm2", + "llvm.ptx.read.pm3" => "__builtin_ptx_read_pm3", + "llvm.ptx.read.smid" => "__builtin_ptx_read_smid", + "llvm.ptx.read.warpid" => "__builtin_ptx_read_warpid", + // cuda + "llvm.cuda.syncthreads" => "__syncthreads", +_ => unimplemented!("***** unsupported LLVM intrinsic {}", name), +} diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index e6d8f78da603..bc8e99428eda 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -8,7 +8,7 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function // NOTE: this doc specifies the equivalent GCC builtins: http://huonw.github.io/llvmint/llvmint/x86/index.html "llvm.sqrt.v2f64" => "__builtin_ia32_sqrtpd", // NOTE: this file is generated by https://github.com/GuillaumeGomez/llvmint/blob/master/generate_list.py - _ => include!("x86.rs"), + _ => include!("archs.rs"), }; let func = cx.context.get_target_builtin_function(gcc_name); diff --git a/src/intrinsic/x86.rs b/src/intrinsic/x86.rs deleted file mode 100644 index 4918325e74c8..000000000000 --- a/src/intrinsic/x86.rs +++ /dev/null @@ -1,770 +0,0 @@ -match name { -// x86 -"llvm.x86.addcarry.u32" => "__builtin_ia32_addcarry_u32", -"llvm.x86.addcarry.u64" => "__builtin_ia32_addcarry_u64", -"llvm.x86.addcarryx.u32" => "__builtin_ia32_addcarryx_u32", -"llvm.x86.addcarryx.u64" => "__builtin_ia32_addcarryx_u64", -"llvm.x86.aesni.aesdec" => "__builtin_ia32_aesdec128", -"llvm.x86.aesni.aesdeclast" => "__builtin_ia32_aesdeclast128", -"llvm.x86.aesni.aesenc" => "__builtin_ia32_aesenc128", -"llvm.x86.aesni.aesenclast" => "__builtin_ia32_aesenclast128", -"llvm.x86.aesni.aesimc" => "__builtin_ia32_aesimc128", -"llvm.x86.aesni.aeskeygenassist" => "__builtin_ia32_aeskeygenassist128", -"llvm.x86.avx.addsub.pd.256" => "__builtin_ia32_addsubpd256", -"llvm.x86.avx.addsub.ps.256" => "__builtin_ia32_addsubps256", -"llvm.x86.avx.blend.pd.256" => "__builtin_ia32_blendpd256", -"llvm.x86.avx.blend.ps.256" => "__builtin_ia32_blendps256", -"llvm.x86.avx.blendv.pd.256" => "__builtin_ia32_blendvpd256", -"llvm.x86.avx.blendv.ps.256" => "__builtin_ia32_blendvps256", -"llvm.x86.avx.cmp.pd.256" => "__builtin_ia32_cmppd256", -"llvm.x86.avx.cmp.ps.256" => "__builtin_ia32_cmpps256", -"llvm.x86.avx.cvt.pd2.ps.256" => "__builtin_ia32_cvtpd2ps256", -"llvm.x86.avx.cvt.pd2dq.256" => "__builtin_ia32_cvtpd2dq256", -"llvm.x86.avx.cvt.ps2.pd.256" => "__builtin_ia32_cvtps2pd256", -"llvm.x86.avx.cvt.ps2dq.256" => "__builtin_ia32_cvtps2dq256", -"llvm.x86.avx.cvtdq2.pd.256" => "__builtin_ia32_cvtdq2pd256", -"llvm.x86.avx.cvtdq2.ps.256" => "__builtin_ia32_cvtdq2ps256", -"llvm.x86.avx.cvtt.pd2dq.256" => "__builtin_ia32_cvttpd2dq256", -"llvm.x86.avx.cvtt.ps2dq.256" => "__builtin_ia32_cvttps2dq256", -"llvm.x86.avx.dp.ps.256" => "__builtin_ia32_dpps256", -"llvm.x86.avx.hadd.pd.256" => "__builtin_ia32_haddpd256", -"llvm.x86.avx.hadd.ps.256" => "__builtin_ia32_haddps256", -"llvm.x86.avx.hsub.pd.256" => "__builtin_ia32_hsubpd256", -"llvm.x86.avx.hsub.ps.256" => "__builtin_ia32_hsubps256", -"llvm.x86.avx.ldu.dq.256" => "__builtin_ia32_lddqu256", -"llvm.x86.avx.maskload.pd" => "__builtin_ia32_maskloadpd", -"llvm.x86.avx.maskload.pd.256" => "__builtin_ia32_maskloadpd256", -"llvm.x86.avx.maskload.ps" => "__builtin_ia32_maskloadps", -"llvm.x86.avx.maskload.ps.256" => "__builtin_ia32_maskloadps256", -"llvm.x86.avx.maskstore.pd" => "__builtin_ia32_maskstorepd", -"llvm.x86.avx.maskstore.pd.256" => "__builtin_ia32_maskstorepd256", -"llvm.x86.avx.maskstore.ps" => "__builtin_ia32_maskstoreps", -"llvm.x86.avx.maskstore.ps.256" => "__builtin_ia32_maskstoreps256", -"llvm.x86.avx.max.pd.256" => "__builtin_ia32_maxpd256", -"llvm.x86.avx.max.ps.256" => "__builtin_ia32_maxps256", -"llvm.x86.avx.min.pd.256" => "__builtin_ia32_minpd256", -"llvm.x86.avx.min.ps.256" => "__builtin_ia32_minps256", -"llvm.x86.avx.movmsk.pd.256" => "__builtin_ia32_movmskpd256", -"llvm.x86.avx.movmsk.ps.256" => "__builtin_ia32_movmskps256", -"llvm.x86.avx.ptestc.256" => "__builtin_ia32_ptestc256", -"llvm.x86.avx.ptestnzc.256" => "__builtin_ia32_ptestnzc256", -"llvm.x86.avx.ptestz.256" => "__builtin_ia32_ptestz256", -"llvm.x86.avx.rcp.ps.256" => "__builtin_ia32_rcpps256", -"llvm.x86.avx.round.pd.256" => "__builtin_ia32_roundpd256", -"llvm.x86.avx.round.ps.256" => "__builtin_ia32_roundps256", -"llvm.x86.avx.rsqrt.ps.256" => "__builtin_ia32_rsqrtps256", -"llvm.x86.avx.sqrt.pd.256" => "__builtin_ia32_sqrtpd256", -"llvm.x86.avx.sqrt.ps.256" => "__builtin_ia32_sqrtps256", -"llvm.x86.avx.storeu.dq.256" => "__builtin_ia32_storedqu256", -"llvm.x86.avx.storeu.pd.256" => "__builtin_ia32_storeupd256", -"llvm.x86.avx.storeu.ps.256" => "__builtin_ia32_storeups256", -"llvm.x86.avx.vbroadcastf128.pd.256" => "__builtin_ia32_vbroadcastf128_pd256", -"llvm.x86.avx.vbroadcastf128.ps.256" => "__builtin_ia32_vbroadcastf128_ps256", -"llvm.x86.avx.vextractf128.pd.256" => "__builtin_ia32_vextractf128_pd256", -"llvm.x86.avx.vextractf128.ps.256" => "__builtin_ia32_vextractf128_ps256", -"llvm.x86.avx.vextractf128.si.256" => "__builtin_ia32_vextractf128_si256", -"llvm.x86.avx.vinsertf128.pd.256" => "__builtin_ia32_vinsertf128_pd256", -"llvm.x86.avx.vinsertf128.ps.256" => "__builtin_ia32_vinsertf128_ps256", -"llvm.x86.avx.vinsertf128.si.256" => "__builtin_ia32_vinsertf128_si256", -"llvm.x86.avx.vperm2f128.pd.256" => "__builtin_ia32_vperm2f128_pd256", -"llvm.x86.avx.vperm2f128.ps.256" => "__builtin_ia32_vperm2f128_ps256", -"llvm.x86.avx.vperm2f128.si.256" => "__builtin_ia32_vperm2f128_si256", -"llvm.x86.avx.vpermilvar.pd" => "__builtin_ia32_vpermilvarpd", -"llvm.x86.avx.vpermilvar.pd.256" => "__builtin_ia32_vpermilvarpd256", -"llvm.x86.avx.vpermilvar.ps" => "__builtin_ia32_vpermilvarps", -"llvm.x86.avx.vpermilvar.ps.256" => "__builtin_ia32_vpermilvarps256", -"llvm.x86.avx.vtestc.pd" => "__builtin_ia32_vtestcpd", -"llvm.x86.avx.vtestc.pd.256" => "__builtin_ia32_vtestcpd256", -"llvm.x86.avx.vtestc.ps" => "__builtin_ia32_vtestcps", -"llvm.x86.avx.vtestc.ps.256" => "__builtin_ia32_vtestcps256", -"llvm.x86.avx.vtestnzc.pd" => "__builtin_ia32_vtestnzcpd", -"llvm.x86.avx.vtestnzc.pd.256" => "__builtin_ia32_vtestnzcpd256", -"llvm.x86.avx.vtestnzc.ps" => "__builtin_ia32_vtestnzcps", -"llvm.x86.avx.vtestnzc.ps.256" => "__builtin_ia32_vtestnzcps256", -"llvm.x86.avx.vtestz.pd" => "__builtin_ia32_vtestzpd", -"llvm.x86.avx.vtestz.pd.256" => "__builtin_ia32_vtestzpd256", -"llvm.x86.avx.vtestz.ps" => "__builtin_ia32_vtestzps", -"llvm.x86.avx.vtestz.ps.256" => "__builtin_ia32_vtestzps256", -"llvm.x86.avx.vzeroall" => "__builtin_ia32_vzeroall", -"llvm.x86.avx.vzeroupper" => "__builtin_ia32_vzeroupper", -"llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gatherd_d", -"llvm.x86.avx2.gather.d.d.256" => "__builtin_ia32_gatherd_d256", -"llvm.x86.avx2.gather.d.pd" => "__builtin_ia32_gatherd_pd", -"llvm.x86.avx2.gather.d.pd.256" => "__builtin_ia32_gatherd_pd256", -"llvm.x86.avx2.gather.d.ps" => "__builtin_ia32_gatherd_ps", -"llvm.x86.avx2.gather.d.ps.256" => "__builtin_ia32_gatherd_ps256", -"llvm.x86.avx2.gather.d.q" => "__builtin_ia32_gatherd_q", -"llvm.x86.avx2.gather.d.q.256" => "__builtin_ia32_gatherd_q256", -"llvm.x86.avx2.gather.q.d" => "__builtin_ia32_gatherq_d", -"llvm.x86.avx2.gather.q.d.256" => "__builtin_ia32_gatherq_d256", -"llvm.x86.avx2.gather.q.pd" => "__builtin_ia32_gatherq_pd", -"llvm.x86.avx2.gather.q.pd.256" => "__builtin_ia32_gatherq_pd256", -"llvm.x86.avx2.gather.q.ps" => "__builtin_ia32_gatherq_ps", -"llvm.x86.avx2.gather.q.ps.256" => "__builtin_ia32_gatherq_ps256", -"llvm.x86.avx2.gather.q.q" => "__builtin_ia32_gatherq_q", -"llvm.x86.avx2.gather.q.q.256" => "__builtin_ia32_gatherq_q256", -"llvm.x86.avx2.maskload.d" => "__builtin_ia32_maskloadd", -"llvm.x86.avx2.maskload.d.256" => "__builtin_ia32_maskloadd256", -"llvm.x86.avx2.maskload.q" => "__builtin_ia32_maskloadq", -"llvm.x86.avx2.maskload.q.256" => "__builtin_ia32_maskloadq256", -"llvm.x86.avx2.maskstore.d" => "__builtin_ia32_maskstored", -"llvm.x86.avx2.maskstore.d.256" => "__builtin_ia32_maskstored256", -"llvm.x86.avx2.maskstore.q" => "__builtin_ia32_maskstoreq", -"llvm.x86.avx2.maskstore.q.256" => "__builtin_ia32_maskstoreq256", -"llvm.x86.avx2.movntdqa" => "__builtin_ia32_movntdqa256", -"llvm.x86.avx2.mpsadbw" => "__builtin_ia32_mpsadbw256", -"llvm.x86.avx2.pabs.b" => "__builtin_ia32_pabsb256", -"llvm.x86.avx2.pabs.d" => "__builtin_ia32_pabsd256", -"llvm.x86.avx2.pabs.w" => "__builtin_ia32_pabsw256", -"llvm.x86.avx2.packssdw" => "__builtin_ia32_packssdw256", -"llvm.x86.avx2.packsswb" => "__builtin_ia32_packsswb256", -"llvm.x86.avx2.packusdw" => "__builtin_ia32_packusdw256", -"llvm.x86.avx2.packuswb" => "__builtin_ia32_packuswb256", -"llvm.x86.avx2.padds.b" => "__builtin_ia32_paddsb256", -"llvm.x86.avx2.padds.w" => "__builtin_ia32_paddsw256", -"llvm.x86.avx2.paddus.b" => "__builtin_ia32_paddusb256", -"llvm.x86.avx2.paddus.w" => "__builtin_ia32_paddusw256", -"llvm.x86.avx2.pavg.b" => "__builtin_ia32_pavgb256", -"llvm.x86.avx2.pavg.w" => "__builtin_ia32_pavgw256", -"llvm.x86.avx2.pblendd.128" => "__builtin_ia32_pblendd128", -"llvm.x86.avx2.pblendd.256" => "__builtin_ia32_pblendd256", -"llvm.x86.avx2.pblendvb" => "__builtin_ia32_pblendvb256", -"llvm.x86.avx2.pblendw" => "__builtin_ia32_pblendw256", -"llvm.x86.avx2.pbroadcastb.128" => "__builtin_ia32_pbroadcastb128", -"llvm.x86.avx2.pbroadcastb.256" => "__builtin_ia32_pbroadcastb256", -"llvm.x86.avx2.pbroadcastd.128" => "__builtin_ia32_pbroadcastd128", -"llvm.x86.avx2.pbroadcastd.256" => "__builtin_ia32_pbroadcastd256", -"llvm.x86.avx2.pbroadcastq.128" => "__builtin_ia32_pbroadcastq128", -"llvm.x86.avx2.pbroadcastq.256" => "__builtin_ia32_pbroadcastq256", -"llvm.x86.avx2.pbroadcastw.128" => "__builtin_ia32_pbroadcastw128", -"llvm.x86.avx2.pbroadcastw.256" => "__builtin_ia32_pbroadcastw256", -"llvm.x86.avx2.permd" => "__builtin_ia32_permvarsi256", -"llvm.x86.avx2.permps" => "__builtin_ia32_permvarsf256", -"llvm.x86.avx2.phadd.d" => "__builtin_ia32_phaddd256", -"llvm.x86.avx2.phadd.sw" => "__builtin_ia32_phaddsw256", -"llvm.x86.avx2.phadd.w" => "__builtin_ia32_phaddw256", -"llvm.x86.avx2.phsub.d" => "__builtin_ia32_phsubd256", -"llvm.x86.avx2.phsub.sw" => "__builtin_ia32_phsubsw256", -"llvm.x86.avx2.phsub.w" => "__builtin_ia32_phsubw256", -"llvm.x86.avx2.pmadd.ub.sw" => "__builtin_ia32_pmaddubsw256", -"llvm.x86.avx2.pmadd.wd" => "__builtin_ia32_pmaddwd256", -"llvm.x86.avx2.pmaxs.b" => "__builtin_ia32_pmaxsb256", -"llvm.x86.avx2.pmaxs.d" => "__builtin_ia32_pmaxsd256", -"llvm.x86.avx2.pmaxs.w" => "__builtin_ia32_pmaxsw256", -"llvm.x86.avx2.pmaxu.b" => "__builtin_ia32_pmaxub256", -"llvm.x86.avx2.pmaxu.d" => "__builtin_ia32_pmaxud256", -"llvm.x86.avx2.pmaxu.w" => "__builtin_ia32_pmaxuw256", -"llvm.x86.avx2.pmins.b" => "__builtin_ia32_pminsb256", -"llvm.x86.avx2.pmins.d" => "__builtin_ia32_pminsd256", -"llvm.x86.avx2.pmins.w" => "__builtin_ia32_pminsw256", -"llvm.x86.avx2.pminu.b" => "__builtin_ia32_pminub256", -"llvm.x86.avx2.pminu.d" => "__builtin_ia32_pminud256", -"llvm.x86.avx2.pminu.w" => "__builtin_ia32_pminuw256", -"llvm.x86.avx2.pmovmskb" => "__builtin_ia32_pmovmskb256", -"llvm.x86.avx2.pmovsxbd" => "__builtin_ia32_pmovsxbd256", -"llvm.x86.avx2.pmovsxbq" => "__builtin_ia32_pmovsxbq256", -"llvm.x86.avx2.pmovsxbw" => "__builtin_ia32_pmovsxbw256", -"llvm.x86.avx2.pmovsxdq" => "__builtin_ia32_pmovsxdq256", -"llvm.x86.avx2.pmovsxwd" => "__builtin_ia32_pmovsxwd256", -"llvm.x86.avx2.pmovsxwq" => "__builtin_ia32_pmovsxwq256", -"llvm.x86.avx2.pmovzxbd" => "__builtin_ia32_pmovzxbd256", -"llvm.x86.avx2.pmovzxbq" => "__builtin_ia32_pmovzxbq256", -"llvm.x86.avx2.pmovzxbw" => "__builtin_ia32_pmovzxbw256", -"llvm.x86.avx2.pmovzxdq" => "__builtin_ia32_pmovzxdq256", -"llvm.x86.avx2.pmovzxwd" => "__builtin_ia32_pmovzxwd256", -"llvm.x86.avx2.pmovzxwq" => "__builtin_ia32_pmovzxwq256", -"llvm.x86.avx2.pmul.dq" => "__builtin_ia32_pmuldq256", -"llvm.x86.avx2.pmul.hr.sw" => "__builtin_ia32_pmulhrsw256", -"llvm.x86.avx2.pmulh.w" => "__builtin_ia32_pmulhw256", -"llvm.x86.avx2.pmulhu.w" => "__builtin_ia32_pmulhuw256", -"llvm.x86.avx2.pmulu.dq" => "__builtin_ia32_pmuludq256", -"llvm.x86.avx2.psad.bw" => "__builtin_ia32_psadbw256", -"llvm.x86.avx2.pshuf.b" => "__builtin_ia32_pshufb256", -"llvm.x86.avx2.psign.b" => "__builtin_ia32_psignb256", -"llvm.x86.avx2.psign.d" => "__builtin_ia32_psignd256", -"llvm.x86.avx2.psign.w" => "__builtin_ia32_psignw256", -"llvm.x86.avx2.psll.d" => "__builtin_ia32_pslld256", -"llvm.x86.avx2.psll.dq" => "__builtin_ia32_pslldqi256", -"llvm.x86.avx2.psll.dq.bs" => "__builtin_ia32_pslldqi256_byteshift", -"llvm.x86.avx2.psll.q" => "__builtin_ia32_psllq256", -"llvm.x86.avx2.psll.w" => "__builtin_ia32_psllw256", -"llvm.x86.avx2.pslli.d" => "__builtin_ia32_pslldi256", -"llvm.x86.avx2.pslli.q" => "__builtin_ia32_psllqi256", -"llvm.x86.avx2.pslli.w" => "__builtin_ia32_psllwi256", -"llvm.x86.avx2.psllv.d" => "__builtin_ia32_psllv4si", -"llvm.x86.avx2.psllv.d.256" => "__builtin_ia32_psllv8si", -"llvm.x86.avx2.psllv.q" => "__builtin_ia32_psllv2di", -"llvm.x86.avx2.psllv.q.256" => "__builtin_ia32_psllv4di", -"llvm.x86.avx2.psra.d" => "__builtin_ia32_psrad256", -"llvm.x86.avx2.psra.w" => "__builtin_ia32_psraw256", -"llvm.x86.avx2.psrai.d" => "__builtin_ia32_psradi256", -"llvm.x86.avx2.psrai.w" => "__builtin_ia32_psrawi256", -"llvm.x86.avx2.psrav.d" => "__builtin_ia32_psrav4si", -"llvm.x86.avx2.psrav.d.256" => "__builtin_ia32_psrav8si", -"llvm.x86.avx2.psrl.d" => "__builtin_ia32_psrld256", -"llvm.x86.avx2.psrl.dq" => "__builtin_ia32_psrldqi256", -"llvm.x86.avx2.psrl.dq.bs" => "__builtin_ia32_psrldqi256_byteshift", -"llvm.x86.avx2.psrl.q" => "__builtin_ia32_psrlq256", -"llvm.x86.avx2.psrl.w" => "__builtin_ia32_psrlw256", -"llvm.x86.avx2.psrli.d" => "__builtin_ia32_psrldi256", -"llvm.x86.avx2.psrli.q" => "__builtin_ia32_psrlqi256", -"llvm.x86.avx2.psrli.w" => "__builtin_ia32_psrlwi256", -"llvm.x86.avx2.psrlv.d" => "__builtin_ia32_psrlv4si", -"llvm.x86.avx2.psrlv.d.256" => "__builtin_ia32_psrlv8si", -"llvm.x86.avx2.psrlv.q" => "__builtin_ia32_psrlv2di", -"llvm.x86.avx2.psrlv.q.256" => "__builtin_ia32_psrlv4di", -"llvm.x86.avx2.psubs.b" => "__builtin_ia32_psubsb256", -"llvm.x86.avx2.psubs.w" => "__builtin_ia32_psubsw256", -"llvm.x86.avx2.psubus.b" => "__builtin_ia32_psubusb256", -"llvm.x86.avx2.psubus.w" => "__builtin_ia32_psubusw256", -"llvm.x86.avx2.vbroadcast.sd.pd.256" => "__builtin_ia32_vbroadcastsd_pd256", -"llvm.x86.avx2.vbroadcast.ss.ps" => "__builtin_ia32_vbroadcastss_ps", -"llvm.x86.avx2.vbroadcast.ss.ps.256" => "__builtin_ia32_vbroadcastss_ps256", -"llvm.x86.avx2.vextracti128" => "__builtin_ia32_extract128i256", -"llvm.x86.avx2.vinserti128" => "__builtin_ia32_insert128i256", -"llvm.x86.avx2.vperm2i128" => "__builtin_ia32_permti256", -"llvm.x86.avx512.cvtsd2usi" => "__builtin_ia32_cvtsd2usi", -"llvm.x86.avx512.cvtsd2usi64" => "__builtin_ia32_cvtsd2usi64", -"llvm.x86.avx512.cvtss2usi" => "__builtin_ia32_cvtss2usi", -"llvm.x86.avx512.cvtss2usi64" => "__builtin_ia32_cvtss2usi64", -"llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_cvttsd2usi", -"llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_cvttsd2usi64", -"llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_cvttss2usi", -"llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_cvttss2usi64", -"llvm.x86.avx512.cvtusi2sd" => "__builtin_ia32_cvtusi2sd", -"llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss", -"llvm.x86.avx512.cvtusi642sd" => "__builtin_ia32_cvtusi642sd", -"llvm.x86.avx512.cvtusi642ss" => "__builtin_ia32_cvtusi642ss", -"llvm.x86.avx512.gather.dpd.512" => "__builtin_ia32_gathersiv8df", -"llvm.x86.avx512.gather.dpi.512" => "__builtin_ia32_gathersiv16si", -"llvm.x86.avx512.gather.dpq.512" => "__builtin_ia32_gathersiv8di", -"llvm.x86.avx512.gather.dps.512" => "__builtin_ia32_gathersiv16sf", -"llvm.x86.avx512.gather.qpd.512" => "__builtin_ia32_gatherdiv8df", -"llvm.x86.avx512.gather.qpi.512" => "__builtin_ia32_gatherdiv16si", -"llvm.x86.avx512.gather.qpq.512" => "__builtin_ia32_gatherdiv8di", -"llvm.x86.avx512.gather.qps.512" => "__builtin_ia32_gatherdiv16sf", -"llvm.x86.avx512.gatherpf.dpd.512" => "__builtin_ia32_gatherpfdpd", -"llvm.x86.avx512.gatherpf.dps.512" => "__builtin_ia32_gatherpfdps", -"llvm.x86.avx512.gatherpf.qpd.512" => "__builtin_ia32_gatherpfqpd", -"llvm.x86.avx512.gatherpf.qps.512" => "__builtin_ia32_gatherpfqps", -"llvm.x86.avx512.kand.w" => "__builtin_ia32_kandhi", -"llvm.x86.avx512.kandn.w" => "__builtin_ia32_kandnhi", -"llvm.x86.avx512.knot.w" => "__builtin_ia32_knothi", -"llvm.x86.avx512.kor.w" => "__builtin_ia32_korhi", -"llvm.x86.avx512.kortestc.w" => "__builtin_ia32_kortestchi", -"llvm.x86.avx512.kortestz.w" => "__builtin_ia32_kortestzhi", -"llvm.x86.avx512.kunpck.bw" => "__builtin_ia32_kunpckhi", -"llvm.x86.avx512.kxnor.w" => "__builtin_ia32_kxnorhi", -"llvm.x86.avx512.kxor.w" => "__builtin_ia32_kxorhi", -"llvm.x86.avx512.mask.blend.d.512" => "__builtin_ia32_blendmd_512_mask", -"llvm.x86.avx512.mask.blend.pd.512" => "__builtin_ia32_blendmpd_512_mask", -"llvm.x86.avx512.mask.blend.ps.512" => "__builtin_ia32_blendmps_512_mask", -"llvm.x86.avx512.mask.blend.q.512" => "__builtin_ia32_blendmq_512_mask", -"llvm.x86.avx512.mask.cmp.pd.512" => "__builtin_ia32_cmppd512_mask", -"llvm.x86.avx512.mask.cmp.ps.512" => "__builtin_ia32_cmpps512_mask", -"llvm.x86.avx512.mask.conflict.d.512" => "__builtin_ia32_vpconflictsi_512_mask", -"llvm.x86.avx512.mask.conflict.q.512" => "__builtin_ia32_vpconflictdi_512_mask", -"llvm.x86.avx512.mask.cvtdq2pd.512" => "__builtin_ia32_cvtdq2pd512_mask", -"llvm.x86.avx512.mask.cvtdq2ps.512" => "__builtin_ia32_cvtdq2ps512_mask", -"llvm.x86.avx512.mask.cvtpd2dq.512" => "__builtin_ia32_cvtpd2dq512_mask", -"llvm.x86.avx512.mask.cvtpd2ps.512" => "__builtin_ia32_cvtpd2ps512_mask", -"llvm.x86.avx512.mask.cvtpd2udq.512" => "__builtin_ia32_cvtpd2udq512_mask", -"llvm.x86.avx512.mask.cvtps2dq.512" => "__builtin_ia32_cvtps2dq512_mask", -"llvm.x86.avx512.mask.cvtps2udq.512" => "__builtin_ia32_cvtps2udq512_mask", -"llvm.x86.avx512.mask.cvttpd2dq.512" => "__builtin_ia32_cvttpd2dq512_mask", -"llvm.x86.avx512.mask.cvttpd2udq.512" => "__builtin_ia32_cvttpd2udq512_mask", -"llvm.x86.avx512.mask.cvttps2dq.512" => "__builtin_ia32_cvttps2dq512_mask", -"llvm.x86.avx512.mask.cvttps2udq.512" => "__builtin_ia32_cvttps2udq512_mask", -"llvm.x86.avx512.mask.cvtudq2pd.512" => "__builtin_ia32_cvtudq2pd512_mask", -"llvm.x86.avx512.mask.cvtudq2ps.512" => "__builtin_ia32_cvtudq2ps512_mask", -"llvm.x86.avx512.mask.loadu.d.512" => "__builtin_ia32_loaddqusi512_mask", -"llvm.x86.avx512.mask.loadu.pd.512" => "__builtin_ia32_loadupd512_mask", -"llvm.x86.avx512.mask.loadu.ps.512" => "__builtin_ia32_loadups512_mask", -"llvm.x86.avx512.mask.loadu.q.512" => "__builtin_ia32_loaddqudi512_mask", -"llvm.x86.avx512.mask.lzcnt.d.512" => "__builtin_ia32_vplzcntd_512_mask", -"llvm.x86.avx512.mask.lzcnt.q.512" => "__builtin_ia32_vplzcntq_512_mask", -"llvm.x86.avx512.mask.max.pd.512" => "__builtin_ia32_maxpd512_mask", -"llvm.x86.avx512.mask.max.ps.512" => "__builtin_ia32_maxps512_mask", -"llvm.x86.avx512.mask.min.pd.512" => "__builtin_ia32_minpd512_mask", -"llvm.x86.avx512.mask.min.ps.512" => "__builtin_ia32_minps512_mask", -"llvm.x86.avx512.mask.pabs.d.512" => "__builtin_ia32_pabsd512_mask", -"llvm.x86.avx512.mask.pabs.q.512" => "__builtin_ia32_pabsq512_mask", -"llvm.x86.avx512.mask.pand.d.512" => "__builtin_ia32_pandd512_mask", -"llvm.x86.avx512.mask.pand.q.512" => "__builtin_ia32_pandq512_mask", -"llvm.x86.avx512.mask.pbroadcast.d.gpr.512" => "__builtin_ia32_pbroadcastd512_gpr_mask", -"llvm.x86.avx512.mask.pbroadcast.q.gpr.512" => "__builtin_ia32_pbroadcastq512_gpr_mask", -"llvm.x86.avx512.mask.pbroadcast.q.mem.512" => "__builtin_ia32_pbroadcastq512_mem_mask", -"llvm.x86.avx512.mask.pcmpeq.b.128" => "__builtin_ia32_pcmpeqb128_mask", -"llvm.x86.avx512.mask.pcmpeq.b.256" => "__builtin_ia32_pcmpeqb256_mask", -"llvm.x86.avx512.mask.pcmpeq.b.512" => "__builtin_ia32_pcmpeqb512_mask", -"llvm.x86.avx512.mask.pcmpeq.d.128" => "__builtin_ia32_pcmpeqd128_mask", -"llvm.x86.avx512.mask.pcmpeq.d.256" => "__builtin_ia32_pcmpeqd256_mask", -"llvm.x86.avx512.mask.pcmpeq.d.512" => "__builtin_ia32_pcmpeqd512_mask", -"llvm.x86.avx512.mask.pcmpeq.q.128" => "__builtin_ia32_pcmpeqq128_mask", -"llvm.x86.avx512.mask.pcmpeq.q.256" => "__builtin_ia32_pcmpeqq256_mask", -"llvm.x86.avx512.mask.pcmpeq.q.512" => "__builtin_ia32_pcmpeqq512_mask", -"llvm.x86.avx512.mask.pcmpeq.w.128" => "__builtin_ia32_pcmpeqw128_mask", -"llvm.x86.avx512.mask.pcmpeq.w.256" => "__builtin_ia32_pcmpeqw256_mask", -"llvm.x86.avx512.mask.pcmpeq.w.512" => "__builtin_ia32_pcmpeqw512_mask", -"llvm.x86.avx512.mask.pcmpgt.b.128" => "__builtin_ia32_pcmpgtb128_mask", -"llvm.x86.avx512.mask.pcmpgt.b.256" => "__builtin_ia32_pcmpgtb256_mask", -"llvm.x86.avx512.mask.pcmpgt.b.512" => "__builtin_ia32_pcmpgtb512_mask", -"llvm.x86.avx512.mask.pcmpgt.d.128" => "__builtin_ia32_pcmpgtd128_mask", -"llvm.x86.avx512.mask.pcmpgt.d.256" => "__builtin_ia32_pcmpgtd256_mask", -"llvm.x86.avx512.mask.pcmpgt.d.512" => "__builtin_ia32_pcmpgtd512_mask", -"llvm.x86.avx512.mask.pcmpgt.q.128" => "__builtin_ia32_pcmpgtq128_mask", -"llvm.x86.avx512.mask.pcmpgt.q.256" => "__builtin_ia32_pcmpgtq256_mask", -"llvm.x86.avx512.mask.pcmpgt.q.512" => "__builtin_ia32_pcmpgtq512_mask", -"llvm.x86.avx512.mask.pcmpgt.w.128" => "__builtin_ia32_pcmpgtw128_mask", -"llvm.x86.avx512.mask.pcmpgt.w.256" => "__builtin_ia32_pcmpgtw256_mask", -"llvm.x86.avx512.mask.pcmpgt.w.512" => "__builtin_ia32_pcmpgtw512_mask", -"llvm.x86.avx512.mask.pmaxs.d.512" => "__builtin_ia32_pmaxsd512_mask", -"llvm.x86.avx512.mask.pmaxs.q.512" => "__builtin_ia32_pmaxsq512_mask", -"llvm.x86.avx512.mask.pmaxu.d.512" => "__builtin_ia32_pmaxud512_mask", -"llvm.x86.avx512.mask.pmaxu.q.512" => "__builtin_ia32_pmaxuq512_mask", -"llvm.x86.avx512.mask.pmins.d.512" => "__builtin_ia32_pminsd512_mask", -"llvm.x86.avx512.mask.pmins.q.512" => "__builtin_ia32_pminsq512_mask", -"llvm.x86.avx512.mask.pminu.d.512" => "__builtin_ia32_pminud512_mask", -"llvm.x86.avx512.mask.pminu.q.512" => "__builtin_ia32_pminuq512_mask", -"llvm.x86.avx512.mask.pmul.dq.512" => "__builtin_ia32_pmuldq512_mask", -"llvm.x86.avx512.mask.pmulu.dq.512" => "__builtin_ia32_pmuludq512_mask", -"llvm.x86.avx512.mask.ptestm.d.512" => "__builtin_ia32_ptestmd512", -"llvm.x86.avx512.mask.ptestm.q.512" => "__builtin_ia32_ptestmq512", -"llvm.x86.avx512.mask.rndscale.pd.512" => "__builtin_ia32_rndscalepd_mask", -"llvm.x86.avx512.mask.rndscale.ps.512" => "__builtin_ia32_rndscaleps_mask", -"llvm.x86.avx512.mask.store.ss" => "__builtin_ia32_storess_mask", -"llvm.x86.avx512.mask.storeu.d.512" => "__builtin_ia32_storedqusi512_mask", -"llvm.x86.avx512.mask.storeu.pd.512" => "__builtin_ia32_storeupd512_mask", -"llvm.x86.avx512.mask.storeu.ps.512" => "__builtin_ia32_storeups512_mask", -"llvm.x86.avx512.mask.storeu.q.512" => "__builtin_ia32_storedqudi512_mask", -"llvm.x86.avx512.mask.valign.d.512" => "__builtin_ia32_alignd512_mask", -"llvm.x86.avx512.mask.valign.q.512" => "__builtin_ia32_alignq512_mask", -"llvm.x86.avx512.mask.vcvtph2ps.512" => "__builtin_ia32_vcvtph2ps512_mask", -"llvm.x86.avx512.mask.vcvtps2ph.512" => "__builtin_ia32_vcvtps2ph512_mask", -"llvm.x86.avx512.mask.vpermt.d.512" => "__builtin_ia32_vpermt2vard512_mask", -"llvm.x86.avx512.mask.vpermt.pd.512" => "__builtin_ia32_vpermt2varpd512_mask", -"llvm.x86.avx512.mask.vpermt.ps.512" => "__builtin_ia32_vpermt2varps512_mask", -"llvm.x86.avx512.mask.vpermt.q.512" => "__builtin_ia32_vpermt2varq512_mask", -"llvm.x86.avx512.movntdqa" => "__builtin_ia32_movntdqa512", -"llvm.x86.avx512.pbroadcastd.512" => "__builtin_ia32_pbroadcastd512", -"llvm.x86.avx512.pbroadcastq.512" => "__builtin_ia32_pbroadcastq512", -"llvm.x86.avx512.pmovzxbd" => "__builtin_ia32_pmovzxbd512", -"llvm.x86.avx512.pmovzxbq" => "__builtin_ia32_pmovzxbq512", -"llvm.x86.avx512.pmovzxdq" => "__builtin_ia32_pmovzxdq512", -"llvm.x86.avx512.pmovzxwd" => "__builtin_ia32_pmovzxwd512", -"llvm.x86.avx512.pmovzxwq" => "__builtin_ia32_pmovzxwq512", -"llvm.x86.avx512.psll.dq" => "__builtin_ia32_pslldqi512", -"llvm.x86.avx512.psll.dq.bs" => "__builtin_ia32_pslldqi512_byteshift", -"llvm.x86.avx512.psrl.dq" => "__builtin_ia32_psrldqi512", -"llvm.x86.avx512.psrl.dq.bs" => "__builtin_ia32_psrldqi512_byteshift", -"llvm.x86.avx512.rcp14.pd.512" => "__builtin_ia32_rcp14pd512_mask", -"llvm.x86.avx512.rcp14.ps.512" => "__builtin_ia32_rcp14ps512_mask", -"llvm.x86.avx512.rcp14.sd" => "__builtin_ia32_rcp14sd_mask", -"llvm.x86.avx512.rcp14.ss" => "__builtin_ia32_rcp14ss_mask", -"llvm.x86.avx512.rcp28.pd" => "__builtin_ia32_rcp28pd_mask", -"llvm.x86.avx512.rcp28.ps" => "__builtin_ia32_rcp28ps_mask", -"llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_mask", -"llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_mask", -"llvm.x86.avx512.rndscale.sd" => "__builtin_ia32_rndscalesd", -"llvm.x86.avx512.rndscale.ss" => "__builtin_ia32_rndscaless", -"llvm.x86.avx512.rsqrt14.pd.512" => "__builtin_ia32_rsqrt14pd512_mask", -"llvm.x86.avx512.rsqrt14.ps.512" => "__builtin_ia32_rsqrt14ps512_mask", -"llvm.x86.avx512.rsqrt14.sd" => "__builtin_ia32_rsqrt14sd_mask", -"llvm.x86.avx512.rsqrt14.ss" => "__builtin_ia32_rsqrt14ss_mask", -"llvm.x86.avx512.rsqrt28.pd" => "__builtin_ia32_rsqrt28pd_mask", -"llvm.x86.avx512.rsqrt28.ps" => "__builtin_ia32_rsqrt28ps_mask", -"llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_mask", -"llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_mask", -"llvm.x86.avx512.scatter.dpd.512" => "__builtin_ia32_scattersiv8df", -"llvm.x86.avx512.scatter.dpi.512" => "__builtin_ia32_scattersiv16si", -"llvm.x86.avx512.scatter.dpq.512" => "__builtin_ia32_scattersiv8di", -"llvm.x86.avx512.scatter.dps.512" => "__builtin_ia32_scattersiv16sf", -"llvm.x86.avx512.scatter.qpd.512" => "__builtin_ia32_scatterdiv8df", -"llvm.x86.avx512.scatter.qpi.512" => "__builtin_ia32_scatterdiv16si", -"llvm.x86.avx512.scatter.qpq.512" => "__builtin_ia32_scatterdiv8di", -"llvm.x86.avx512.scatter.qps.512" => "__builtin_ia32_scatterdiv16sf", -"llvm.x86.avx512.scatterpf.dpd.512" => "__builtin_ia32_scatterpfdpd", -"llvm.x86.avx512.scatterpf.dps.512" => "__builtin_ia32_scatterpfdps", -"llvm.x86.avx512.scatterpf.qpd.512" => "__builtin_ia32_scatterpfqpd", -"llvm.x86.avx512.scatterpf.qps.512" => "__builtin_ia32_scatterpfqps", -"llvm.x86.avx512.sqrt.pd.512" => "__builtin_ia32_sqrtpd512_mask", -"llvm.x86.avx512.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask", -"llvm.x86.avx512.sqrt.sd" => "__builtin_ia32_sqrtrndsd", -"llvm.x86.avx512.sqrt.ss" => "__builtin_ia32_sqrtrndss", -"llvm.x86.avx512.vbroadcast.sd.512" => "__builtin_ia32_vbroadcastsd512", -"llvm.x86.avx512.vbroadcast.sd.pd.512" => "__builtin_ia32_vbroadcastsd_pd512", -"llvm.x86.avx512.vbroadcast.ss.512" => "__builtin_ia32_vbroadcastss512", -"llvm.x86.avx512.vbroadcast.ss.ps.512" => "__builtin_ia32_vbroadcastss_ps512", -"llvm.x86.bmi.bextr.32" => "__builtin_ia32_bextr_u32", -"llvm.x86.bmi.bextr.64" => "__builtin_ia32_bextr_u64", -"llvm.x86.bmi.bzhi.32" => "__builtin_ia32_bzhi_si", -"llvm.x86.bmi.bzhi.64" => "__builtin_ia32_bzhi_di", -"llvm.x86.bmi.pdep.32" => "__builtin_ia32_pdep_si", -"llvm.x86.bmi.pdep.64" => "__builtin_ia32_pdep_di", -"llvm.x86.bmi.pext.32" => "__builtin_ia32_pext_si", -"llvm.x86.bmi.pext.64" => "__builtin_ia32_pext_di", -"llvm.x86.fma.mask.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask", -"llvm.x86.fma.mask.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask", -"llvm.x86.fma.mask.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask", -"llvm.x86.fma.mask.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask", -"llvm.x86.fma.mask.vfmsub.pd.512" => "__builtin_ia32_vfmsubpd512_mask", -"llvm.x86.fma.mask.vfmsub.ps.512" => "__builtin_ia32_vfmsubps512_mask", -"llvm.x86.fma.mask.vfmsubadd.pd.512" => "__builtin_ia32_vfmsubaddpd512_mask", -"llvm.x86.fma.mask.vfmsubadd.ps.512" => "__builtin_ia32_vfmsubaddps512_mask", -"llvm.x86.fma.mask.vfnmadd.pd.512" => "__builtin_ia32_vfnmaddpd512_mask", -"llvm.x86.fma.mask.vfnmadd.ps.512" => "__builtin_ia32_vfnmaddps512_mask", -"llvm.x86.fma.mask.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask", -"llvm.x86.fma.mask.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask", -"llvm.x86.fma.vfmadd.pd" => "__builtin_ia32_vfmaddpd", -"llvm.x86.fma.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256", -"llvm.x86.fma.vfmadd.ps" => "__builtin_ia32_vfmaddps", -"llvm.x86.fma.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256", -"llvm.x86.fma.vfmadd.sd" => "__builtin_ia32_vfmaddsd", -"llvm.x86.fma.vfmadd.ss" => "__builtin_ia32_vfmaddss", -"llvm.x86.fma.vfmaddsub.pd" => "__builtin_ia32_vfmaddsubpd", -"llvm.x86.fma.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256", -"llvm.x86.fma.vfmaddsub.ps" => "__builtin_ia32_vfmaddsubps", -"llvm.x86.fma.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256", -"llvm.x86.fma.vfmsub.pd" => "__builtin_ia32_vfmsubpd", -"llvm.x86.fma.vfmsub.pd.256" => "__builtin_ia32_vfmsubpd256", -"llvm.x86.fma.vfmsub.ps" => "__builtin_ia32_vfmsubps", -"llvm.x86.fma.vfmsub.ps.256" => "__builtin_ia32_vfmsubps256", -"llvm.x86.fma.vfmsub.sd" => "__builtin_ia32_vfmsubsd", -"llvm.x86.fma.vfmsub.ss" => "__builtin_ia32_vfmsubss", -"llvm.x86.fma.vfmsubadd.pd" => "__builtin_ia32_vfmsubaddpd", -"llvm.x86.fma.vfmsubadd.pd.256" => "__builtin_ia32_vfmsubaddpd256", -"llvm.x86.fma.vfmsubadd.ps" => "__builtin_ia32_vfmsubaddps", -"llvm.x86.fma.vfmsubadd.ps.256" => "__builtin_ia32_vfmsubaddps256", -"llvm.x86.fma.vfnmadd.pd" => "__builtin_ia32_vfnmaddpd", -"llvm.x86.fma.vfnmadd.pd.256" => "__builtin_ia32_vfnmaddpd256", -"llvm.x86.fma.vfnmadd.ps" => "__builtin_ia32_vfnmaddps", -"llvm.x86.fma.vfnmadd.ps.256" => "__builtin_ia32_vfnmaddps256", -"llvm.x86.fma.vfnmadd.sd" => "__builtin_ia32_vfnmaddsd", -"llvm.x86.fma.vfnmadd.ss" => "__builtin_ia32_vfnmaddss", -"llvm.x86.fma.vfnmsub.pd" => "__builtin_ia32_vfnmsubpd", -"llvm.x86.fma.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256", -"llvm.x86.fma.vfnmsub.ps" => "__builtin_ia32_vfnmsubps", -"llvm.x86.fma.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256", -"llvm.x86.fma.vfnmsub.sd" => "__builtin_ia32_vfnmsubsd", -"llvm.x86.fma.vfnmsub.ss" => "__builtin_ia32_vfnmsubss", -"llvm.x86.mmx.emms" => "__builtin_ia32_emms", -"llvm.x86.mmx.femms" => "__builtin_ia32_femms", -"llvm.x86.pclmulqdq" => "__builtin_ia32_pclmulqdq128", -"llvm.x86.rdfsbase.32" => "__builtin_ia32_rdfsbase32", -"llvm.x86.rdfsbase.64" => "__builtin_ia32_rdfsbase64", -"llvm.x86.rdgsbase.32" => "__builtin_ia32_rdgsbase32", -"llvm.x86.rdgsbase.64" => "__builtin_ia32_rdgsbase64", -"llvm.x86.rdpmc" => "__builtin_ia32_rdpmc", -"llvm.x86.rdtsc" => "__builtin_ia32_rdtsc", -"llvm.x86.rdtscp" => "__builtin_ia32_rdtscp", -"llvm.x86.sha1msg1" => "__builtin_ia32_sha1msg1", -"llvm.x86.sha1msg2" => "__builtin_ia32_sha1msg2", -"llvm.x86.sha1nexte" => "__builtin_ia32_sha1nexte", -"llvm.x86.sha1rnds4" => "__builtin_ia32_sha1rnds4", -"llvm.x86.sha256msg1" => "__builtin_ia32_sha256msg1", -"llvm.x86.sha256msg2" => "__builtin_ia32_sha256msg2", -"llvm.x86.sha256rnds2" => "__builtin_ia32_sha256rnds2", -"llvm.x86.sse.add.ss" => "__builtin_ia32_addss", -"llvm.x86.sse.cmp.ps" => "__builtin_ia32_cmpps", -"llvm.x86.sse.cmp.ss" => "__builtin_ia32_cmpss", -"llvm.x86.sse.comieq.ss" => "__builtin_ia32_comieq", -"llvm.x86.sse.comige.ss" => "__builtin_ia32_comige", -"llvm.x86.sse.comigt.ss" => "__builtin_ia32_comigt", -"llvm.x86.sse.comile.ss" => "__builtin_ia32_comile", -"llvm.x86.sse.comilt.ss" => "__builtin_ia32_comilt", -"llvm.x86.sse.comineq.ss" => "__builtin_ia32_comineq", -"llvm.x86.sse.cvtsi2ss" => "__builtin_ia32_cvtsi2ss", -"llvm.x86.sse.cvtsi642ss" => "__builtin_ia32_cvtsi642ss", -"llvm.x86.sse.cvtss2si" => "__builtin_ia32_cvtss2si", -"llvm.x86.sse.cvtss2si64" => "__builtin_ia32_cvtss2si64", -"llvm.x86.sse.cvttss2si" => "__builtin_ia32_cvttss2si", -"llvm.x86.sse.cvttss2si64" => "__builtin_ia32_cvttss2si64", -"llvm.x86.sse.div.ss" => "__builtin_ia32_divss", -"llvm.x86.sse.max.ps" => "__builtin_ia32_maxps", -"llvm.x86.sse.max.ss" => "__builtin_ia32_maxss", -"llvm.x86.sse.min.ps" => "__builtin_ia32_minps", -"llvm.x86.sse.min.ss" => "__builtin_ia32_minss", -"llvm.x86.sse.movmsk.ps" => "__builtin_ia32_movmskps", -"llvm.x86.sse.mul.ss" => "__builtin_ia32_mulss", -"llvm.x86.sse.rcp.ps" => "__builtin_ia32_rcpps", -"llvm.x86.sse.rcp.ss" => "__builtin_ia32_rcpss", -"llvm.x86.sse.rsqrt.ps" => "__builtin_ia32_rsqrtps", -"llvm.x86.sse.rsqrt.ss" => "__builtin_ia32_rsqrtss", -"llvm.x86.sse.sfence" => "__builtin_ia32_sfence", -"llvm.x86.sse.sqrt.ps" => "__builtin_ia32_sqrtps", -"llvm.x86.sse.sqrt.ss" => "__builtin_ia32_sqrtss", -"llvm.x86.sse.storeu.ps" => "__builtin_ia32_storeups", -"llvm.x86.sse.sub.ss" => "__builtin_ia32_subss", -"llvm.x86.sse.ucomieq.ss" => "__builtin_ia32_ucomieq", -"llvm.x86.sse.ucomige.ss" => "__builtin_ia32_ucomige", -"llvm.x86.sse.ucomigt.ss" => "__builtin_ia32_ucomigt", -"llvm.x86.sse.ucomile.ss" => "__builtin_ia32_ucomile", -"llvm.x86.sse.ucomilt.ss" => "__builtin_ia32_ucomilt", -"llvm.x86.sse.ucomineq.ss" => "__builtin_ia32_ucomineq", -"llvm.x86.sse2.add.sd" => "__builtin_ia32_addsd", -"llvm.x86.sse2.clflush" => "__builtin_ia32_clflush", -"llvm.x86.sse2.cmp.pd" => "__builtin_ia32_cmppd", -"llvm.x86.sse2.cmp.sd" => "__builtin_ia32_cmpsd", -"llvm.x86.sse2.comieq.sd" => "__builtin_ia32_comisdeq", -"llvm.x86.sse2.comige.sd" => "__builtin_ia32_comisdge", -"llvm.x86.sse2.comigt.sd" => "__builtin_ia32_comisdgt", -"llvm.x86.sse2.comile.sd" => "__builtin_ia32_comisdle", -"llvm.x86.sse2.comilt.sd" => "__builtin_ia32_comisdlt", -"llvm.x86.sse2.comineq.sd" => "__builtin_ia32_comisdneq", -"llvm.x86.sse2.cvtdq2pd" => "__builtin_ia32_cvtdq2pd", -"llvm.x86.sse2.cvtdq2ps" => "__builtin_ia32_cvtdq2ps", -"llvm.x86.sse2.cvtpd2dq" => "__builtin_ia32_cvtpd2dq", -"llvm.x86.sse2.cvtpd2ps" => "__builtin_ia32_cvtpd2ps", -"llvm.x86.sse2.cvtps2dq" => "__builtin_ia32_cvtps2dq", -"llvm.x86.sse2.cvtps2pd" => "__builtin_ia32_cvtps2pd", -"llvm.x86.sse2.cvtsd2si" => "__builtin_ia32_cvtsd2si", -"llvm.x86.sse2.cvtsd2si64" => "__builtin_ia32_cvtsd2si64", -"llvm.x86.sse2.cvtsd2ss" => "__builtin_ia32_cvtsd2ss", -"llvm.x86.sse2.cvtsi2sd" => "__builtin_ia32_cvtsi2sd", -"llvm.x86.sse2.cvtsi642sd" => "__builtin_ia32_cvtsi642sd", -"llvm.x86.sse2.cvtss2sd" => "__builtin_ia32_cvtss2sd", -"llvm.x86.sse2.cvttpd2dq" => "__builtin_ia32_cvttpd2dq", -"llvm.x86.sse2.cvttps2dq" => "__builtin_ia32_cvttps2dq", -"llvm.x86.sse2.cvttsd2si" => "__builtin_ia32_cvttsd2si", -"llvm.x86.sse2.cvttsd2si64" => "__builtin_ia32_cvttsd2si64", -"llvm.x86.sse2.div.sd" => "__builtin_ia32_divsd", -"llvm.x86.sse2.lfence" => "__builtin_ia32_lfence", -"llvm.x86.sse2.maskmov.dqu" => "__builtin_ia32_maskmovdqu", -"llvm.x86.sse2.max.pd" => "__builtin_ia32_maxpd", -"llvm.x86.sse2.max.sd" => "__builtin_ia32_maxsd", -"llvm.x86.sse2.mfence" => "__builtin_ia32_mfence", -"llvm.x86.sse2.min.pd" => "__builtin_ia32_minpd", -"llvm.x86.sse2.min.sd" => "__builtin_ia32_minsd", -"llvm.x86.sse2.movmsk.pd" => "__builtin_ia32_movmskpd", -"llvm.x86.sse2.mul.sd" => "__builtin_ia32_mulsd", -"llvm.x86.sse2.packssdw.128" => "__builtin_ia32_packssdw128", -"llvm.x86.sse2.packsswb.128" => "__builtin_ia32_packsswb128", -"llvm.x86.sse2.packuswb.128" => "__builtin_ia32_packuswb128", -"llvm.x86.sse2.padds.b" => "__builtin_ia32_paddsb128", -"llvm.x86.sse2.padds.w" => "__builtin_ia32_paddsw128", -"llvm.x86.sse2.paddus.b" => "__builtin_ia32_paddusb128", -"llvm.x86.sse2.paddus.w" => "__builtin_ia32_paddusw128", -"llvm.x86.sse2.pause" => "__builtin_ia32_pause", -"llvm.x86.sse2.pavg.b" => "__builtin_ia32_pavgb128", -"llvm.x86.sse2.pavg.w" => "__builtin_ia32_pavgw128", -"llvm.x86.sse2.pmadd.wd" => "__builtin_ia32_pmaddwd128", -"llvm.x86.sse2.pmaxs.w" => "__builtin_ia32_pmaxsw128", -"llvm.x86.sse2.pmaxu.b" => "__builtin_ia32_pmaxub128", -"llvm.x86.sse2.pmins.w" => "__builtin_ia32_pminsw128", -"llvm.x86.sse2.pminu.b" => "__builtin_ia32_pminub128", -"llvm.x86.sse2.pmovmskb.128" => "__builtin_ia32_pmovmskb128", -"llvm.x86.sse2.pmulh.w" => "__builtin_ia32_pmulhw128", -"llvm.x86.sse2.pmulhu.w" => "__builtin_ia32_pmulhuw128", -"llvm.x86.sse2.pmulu.dq" => "__builtin_ia32_pmuludq128", -"llvm.x86.sse2.psad.bw" => "__builtin_ia32_psadbw128", -"llvm.x86.sse2.pshuf.d" => "__builtin_ia32_pshufd", -"llvm.x86.sse2.pshufh.w" => "__builtin_ia32_pshufhw", -"llvm.x86.sse2.pshufl.w" => "__builtin_ia32_pshuflw", -"llvm.x86.sse2.psll.d" => "__builtin_ia32_pslld128", -"llvm.x86.sse2.psll.dq" => "__builtin_ia32_pslldqi128", -"llvm.x86.sse2.psll.dq.bs" => "__builtin_ia32_pslldqi128_byteshift", -"llvm.x86.sse2.psll.q" => "__builtin_ia32_psllq128", -"llvm.x86.sse2.psll.w" => "__builtin_ia32_psllw128", -"llvm.x86.sse2.pslli.d" => "__builtin_ia32_pslldi128", -"llvm.x86.sse2.pslli.q" => "__builtin_ia32_psllqi128", -"llvm.x86.sse2.pslli.w" => "__builtin_ia32_psllwi128", -"llvm.x86.sse2.psra.d" => "__builtin_ia32_psrad128", -"llvm.x86.sse2.psra.w" => "__builtin_ia32_psraw128", -"llvm.x86.sse2.psrai.d" => "__builtin_ia32_psradi128", -"llvm.x86.sse2.psrai.w" => "__builtin_ia32_psrawi128", -"llvm.x86.sse2.psrl.d" => "__builtin_ia32_psrld128", -"llvm.x86.sse2.psrl.dq" => "__builtin_ia32_psrldqi128", -"llvm.x86.sse2.psrl.dq.bs" => "__builtin_ia32_psrldqi128_byteshift", -"llvm.x86.sse2.psrl.q" => "__builtin_ia32_psrlq128", -"llvm.x86.sse2.psrl.w" => "__builtin_ia32_psrlw128", -"llvm.x86.sse2.psrli.d" => "__builtin_ia32_psrldi128", -"llvm.x86.sse2.psrli.q" => "__builtin_ia32_psrlqi128", -"llvm.x86.sse2.psrli.w" => "__builtin_ia32_psrlwi128", -"llvm.x86.sse2.psubs.b" => "__builtin_ia32_psubsb128", -"llvm.x86.sse2.psubs.w" => "__builtin_ia32_psubsw128", -"llvm.x86.sse2.psubus.b" => "__builtin_ia32_psubusb128", -"llvm.x86.sse2.psubus.w" => "__builtin_ia32_psubusw128", -"llvm.x86.sse2.sqrt.pd" => "__builtin_ia32_sqrtpd", -"llvm.x86.sse2.sqrt.sd" => "__builtin_ia32_sqrtsd", -"llvm.x86.sse2.storel.dq" => "__builtin_ia32_storelv4si", -"llvm.x86.sse2.storeu.dq" => "__builtin_ia32_storedqu", -"llvm.x86.sse2.storeu.pd" => "__builtin_ia32_storeupd", -"llvm.x86.sse2.sub.sd" => "__builtin_ia32_subsd", -"llvm.x86.sse2.ucomieq.sd" => "__builtin_ia32_ucomisdeq", -"llvm.x86.sse2.ucomige.sd" => "__builtin_ia32_ucomisdge", -"llvm.x86.sse2.ucomigt.sd" => "__builtin_ia32_ucomisdgt", -"llvm.x86.sse2.ucomile.sd" => "__builtin_ia32_ucomisdle", -"llvm.x86.sse2.ucomilt.sd" => "__builtin_ia32_ucomisdlt", -"llvm.x86.sse2.ucomineq.sd" => "__builtin_ia32_ucomisdneq", -"llvm.x86.sse3.addsub.pd" => "__builtin_ia32_addsubpd", -"llvm.x86.sse3.addsub.ps" => "__builtin_ia32_addsubps", -"llvm.x86.sse3.hadd.pd" => "__builtin_ia32_haddpd", -"llvm.x86.sse3.hadd.ps" => "__builtin_ia32_haddps", -"llvm.x86.sse3.hsub.pd" => "__builtin_ia32_hsubpd", -"llvm.x86.sse3.hsub.ps" => "__builtin_ia32_hsubps", -"llvm.x86.sse3.ldu.dq" => "__builtin_ia32_lddqu", -"llvm.x86.sse3.monitor" => "__builtin_ia32_monitor", -"llvm.x86.sse3.mwait" => "__builtin_ia32_mwait", -"llvm.x86.sse41.blendpd" => "__builtin_ia32_blendpd", -"llvm.x86.sse41.blendps" => "__builtin_ia32_blendps", -"llvm.x86.sse41.blendvpd" => "__builtin_ia32_blendvpd", -"llvm.x86.sse41.blendvps" => "__builtin_ia32_blendvps", -"llvm.x86.sse41.dppd" => "__builtin_ia32_dppd", -"llvm.x86.sse41.dpps" => "__builtin_ia32_dpps", -"llvm.x86.sse41.extractps" => "__builtin_ia32_extractps128", -"llvm.x86.sse41.insertps" => "__builtin_ia32_insertps128", -"llvm.x86.sse41.movntdqa" => "__builtin_ia32_movntdqa", -"llvm.x86.sse41.mpsadbw" => "__builtin_ia32_mpsadbw128", -"llvm.x86.sse41.packusdw" => "__builtin_ia32_packusdw128", -"llvm.x86.sse41.pblendvb" => "__builtin_ia32_pblendvb128", -"llvm.x86.sse41.pblendw" => "__builtin_ia32_pblendw128", -"llvm.x86.sse41.phminposuw" => "__builtin_ia32_phminposuw128", -"llvm.x86.sse41.pmaxsb" => "__builtin_ia32_pmaxsb128", -"llvm.x86.sse41.pmaxsd" => "__builtin_ia32_pmaxsd128", -"llvm.x86.sse41.pmaxud" => "__builtin_ia32_pmaxud128", -"llvm.x86.sse41.pmaxuw" => "__builtin_ia32_pmaxuw128", -"llvm.x86.sse41.pminsb" => "__builtin_ia32_pminsb128", -"llvm.x86.sse41.pminsd" => "__builtin_ia32_pminsd128", -"llvm.x86.sse41.pminud" => "__builtin_ia32_pminud128", -"llvm.x86.sse41.pminuw" => "__builtin_ia32_pminuw128", -"llvm.x86.sse41.pmovsxbd" => "__builtin_ia32_pmovsxbd128", -"llvm.x86.sse41.pmovsxbq" => "__builtin_ia32_pmovsxbq128", -"llvm.x86.sse41.pmovsxbw" => "__builtin_ia32_pmovsxbw128", -"llvm.x86.sse41.pmovsxdq" => "__builtin_ia32_pmovsxdq128", -"llvm.x86.sse41.pmovsxwd" => "__builtin_ia32_pmovsxwd128", -"llvm.x86.sse41.pmovsxwq" => "__builtin_ia32_pmovsxwq128", -"llvm.x86.sse41.pmovzxbd" => "__builtin_ia32_pmovzxbd128", -"llvm.x86.sse41.pmovzxbq" => "__builtin_ia32_pmovzxbq128", -"llvm.x86.sse41.pmovzxbw" => "__builtin_ia32_pmovzxbw128", -"llvm.x86.sse41.pmovzxdq" => "__builtin_ia32_pmovzxdq128", -"llvm.x86.sse41.pmovzxwd" => "__builtin_ia32_pmovzxwd128", -"llvm.x86.sse41.pmovzxwq" => "__builtin_ia32_pmovzxwq128", -"llvm.x86.sse41.pmuldq" => "__builtin_ia32_pmuldq128", -"llvm.x86.sse41.ptestc" => "__builtin_ia32_ptestc128", -"llvm.x86.sse41.ptestnzc" => "__builtin_ia32_ptestnzc128", -"llvm.x86.sse41.ptestz" => "__builtin_ia32_ptestz128", -"llvm.x86.sse41.round.pd" => "__builtin_ia32_roundpd", -"llvm.x86.sse41.round.ps" => "__builtin_ia32_roundps", -"llvm.x86.sse41.round.sd" => "__builtin_ia32_roundsd", -"llvm.x86.sse41.round.ss" => "__builtin_ia32_roundss", -"llvm.x86.sse42.crc32.32.16" => "__builtin_ia32_crc32hi", -"llvm.x86.sse42.crc32.32.32" => "__builtin_ia32_crc32si", -"llvm.x86.sse42.crc32.32.8" => "__builtin_ia32_crc32qi", -"llvm.x86.sse42.crc32.64.64" => "__builtin_ia32_crc32di", -"llvm.x86.sse42.pcmpestri128" => "__builtin_ia32_pcmpestri128", -"llvm.x86.sse42.pcmpestria128" => "__builtin_ia32_pcmpestria128", -"llvm.x86.sse42.pcmpestric128" => "__builtin_ia32_pcmpestric128", -"llvm.x86.sse42.pcmpestrio128" => "__builtin_ia32_pcmpestrio128", -"llvm.x86.sse42.pcmpestris128" => "__builtin_ia32_pcmpestris128", -"llvm.x86.sse42.pcmpestriz128" => "__builtin_ia32_pcmpestriz128", -"llvm.x86.sse42.pcmpestrm128" => "__builtin_ia32_pcmpestrm128", -"llvm.x86.sse42.pcmpistri128" => "__builtin_ia32_pcmpistri128", -"llvm.x86.sse42.pcmpistria128" => "__builtin_ia32_pcmpistria128", -"llvm.x86.sse42.pcmpistric128" => "__builtin_ia32_pcmpistric128", -"llvm.x86.sse42.pcmpistrio128" => "__builtin_ia32_pcmpistrio128", -"llvm.x86.sse42.pcmpistris128" => "__builtin_ia32_pcmpistris128", -"llvm.x86.sse42.pcmpistriz128" => "__builtin_ia32_pcmpistriz128", -"llvm.x86.sse42.pcmpistrm128" => "__builtin_ia32_pcmpistrm128", -"llvm.x86.sse4a.extrq" => "__builtin_ia32_extrq", -"llvm.x86.sse4a.extrqi" => "__builtin_ia32_extrqi", -"llvm.x86.sse4a.insertq" => "__builtin_ia32_insertq", -"llvm.x86.sse4a.insertqi" => "__builtin_ia32_insertqi", -"llvm.x86.sse4a.movnt.sd" => "__builtin_ia32_movntsd", -"llvm.x86.sse4a.movnt.ss" => "__builtin_ia32_movntss", -"llvm.x86.ssse3.pabs.b.128" => "__builtin_ia32_pabsb128", -"llvm.x86.ssse3.pabs.d.128" => "__builtin_ia32_pabsd128", -"llvm.x86.ssse3.pabs.w.128" => "__builtin_ia32_pabsw128", -"llvm.x86.ssse3.phadd.d.128" => "__builtin_ia32_phaddd128", -"llvm.x86.ssse3.phadd.sw.128" => "__builtin_ia32_phaddsw128", -"llvm.x86.ssse3.phadd.w.128" => "__builtin_ia32_phaddw128", -"llvm.x86.ssse3.phsub.d.128" => "__builtin_ia32_phsubd128", -"llvm.x86.ssse3.phsub.sw.128" => "__builtin_ia32_phsubsw128", -"llvm.x86.ssse3.phsub.w.128" => "__builtin_ia32_phsubw128", -"llvm.x86.ssse3.pmadd.ub.sw.128" => "__builtin_ia32_pmaddubsw128", -"llvm.x86.ssse3.pmul.hr.sw.128" => "__builtin_ia32_pmulhrsw128", -"llvm.x86.ssse3.pshuf.b.128" => "__builtin_ia32_pshufb128", -"llvm.x86.ssse3.psign.b.128" => "__builtin_ia32_psignb128", -"llvm.x86.ssse3.psign.d.128" => "__builtin_ia32_psignd128", -"llvm.x86.ssse3.psign.w.128" => "__builtin_ia32_psignw128", -"llvm.x86.subborrow.u32" => "__builtin_ia32_subborrow_u32", -"llvm.x86.subborrow.u64" => "__builtin_ia32_subborrow_u64", -"llvm.x86.tbm.bextri.u32" => "__builtin_ia32_bextri_u32", -"llvm.x86.tbm.bextri.u64" => "__builtin_ia32_bextri_u64", -"llvm.x86.vcvtph2ps.128" => "__builtin_ia32_vcvtph2ps", -"llvm.x86.vcvtph2ps.256" => "__builtin_ia32_vcvtph2ps256", -"llvm.x86.vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph", -"llvm.x86.vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256", -"llvm.x86.wrfsbase.32" => "__builtin_ia32_wrfsbase32", -"llvm.x86.wrfsbase.64" => "__builtin_ia32_wrfsbase64", -"llvm.x86.wrgsbase.32" => "__builtin_ia32_wrgsbase32", -"llvm.x86.wrgsbase.64" => "__builtin_ia32_wrgsbase64", -"llvm.x86.xabort" => "__builtin_ia32_xabort", -"llvm.x86.xbegin" => "__builtin_ia32_xbegin", -"llvm.x86.xend" => "__builtin_ia32_xend", -"llvm.x86.xop.vfrcz.pd" => "__builtin_ia32_vfrczpd", -"llvm.x86.xop.vfrcz.pd.256" => "__builtin_ia32_vfrczpd256", -"llvm.x86.xop.vfrcz.ps" => "__builtin_ia32_vfrczps", -"llvm.x86.xop.vfrcz.ps.256" => "__builtin_ia32_vfrczps256", -"llvm.x86.xop.vfrcz.sd" => "__builtin_ia32_vfrczsd", -"llvm.x86.xop.vfrcz.ss" => "__builtin_ia32_vfrczss", -"llvm.x86.xop.vpcmov" => "__builtin_ia32_vpcmov", -"llvm.x86.xop.vpcmov.256" => "__builtin_ia32_vpcmov_256", -"llvm.x86.xop.vpcomb" => "__builtin_ia32_vpcomb", -"llvm.x86.xop.vpcomd" => "__builtin_ia32_vpcomd", -"llvm.x86.xop.vpcomq" => "__builtin_ia32_vpcomq", -"llvm.x86.xop.vpcomub" => "__builtin_ia32_vpcomub", -"llvm.x86.xop.vpcomud" => "__builtin_ia32_vpcomud", -"llvm.x86.xop.vpcomuq" => "__builtin_ia32_vpcomuq", -"llvm.x86.xop.vpcomuw" => "__builtin_ia32_vpcomuw", -"llvm.x86.xop.vpcomw" => "__builtin_ia32_vpcomw", -"llvm.x86.xop.vpermil2pd" => "__builtin_ia32_vpermil2pd", -"llvm.x86.xop.vpermil2pd.256" => "__builtin_ia32_vpermil2pd256", -"llvm.x86.xop.vpermil2ps" => "__builtin_ia32_vpermil2ps", -"llvm.x86.xop.vpermil2ps.256" => "__builtin_ia32_vpermil2ps256", -"llvm.x86.xop.vphaddbd" => "__builtin_ia32_vphaddbd", -"llvm.x86.xop.vphaddbq" => "__builtin_ia32_vphaddbq", -"llvm.x86.xop.vphaddbw" => "__builtin_ia32_vphaddbw", -"llvm.x86.xop.vphadddq" => "__builtin_ia32_vphadddq", -"llvm.x86.xop.vphaddubd" => "__builtin_ia32_vphaddubd", -"llvm.x86.xop.vphaddubq" => "__builtin_ia32_vphaddubq", -"llvm.x86.xop.vphaddubw" => "__builtin_ia32_vphaddubw", -"llvm.x86.xop.vphaddudq" => "__builtin_ia32_vphaddudq", -"llvm.x86.xop.vphadduwd" => "__builtin_ia32_vphadduwd", -"llvm.x86.xop.vphadduwq" => "__builtin_ia32_vphadduwq", -"llvm.x86.xop.vphaddwd" => "__builtin_ia32_vphaddwd", -"llvm.x86.xop.vphaddwq" => "__builtin_ia32_vphaddwq", -"llvm.x86.xop.vphsubbw" => "__builtin_ia32_vphsubbw", -"llvm.x86.xop.vphsubdq" => "__builtin_ia32_vphsubdq", -"llvm.x86.xop.vphsubwd" => "__builtin_ia32_vphsubwd", -"llvm.x86.xop.vpmacsdd" => "__builtin_ia32_vpmacsdd", -"llvm.x86.xop.vpmacsdqh" => "__builtin_ia32_vpmacsdqh", -"llvm.x86.xop.vpmacsdql" => "__builtin_ia32_vpmacsdql", -"llvm.x86.xop.vpmacssdd" => "__builtin_ia32_vpmacssdd", -"llvm.x86.xop.vpmacssdqh" => "__builtin_ia32_vpmacssdqh", -"llvm.x86.xop.vpmacssdql" => "__builtin_ia32_vpmacssdql", -"llvm.x86.xop.vpmacsswd" => "__builtin_ia32_vpmacsswd", -"llvm.x86.xop.vpmacssww" => "__builtin_ia32_vpmacssww", -"llvm.x86.xop.vpmacswd" => "__builtin_ia32_vpmacswd", -"llvm.x86.xop.vpmacsww" => "__builtin_ia32_vpmacsww", -"llvm.x86.xop.vpmadcsswd" => "__builtin_ia32_vpmadcsswd", -"llvm.x86.xop.vpmadcswd" => "__builtin_ia32_vpmadcswd", -"llvm.x86.xop.vpperm" => "__builtin_ia32_vpperm", -"llvm.x86.xop.vprotb" => "__builtin_ia32_vprotb", -"llvm.x86.xop.vprotbi" => "__builtin_ia32_vprotbi", -"llvm.x86.xop.vprotd" => "__builtin_ia32_vprotd", -"llvm.x86.xop.vprotdi" => "__builtin_ia32_vprotdi", -"llvm.x86.xop.vprotq" => "__builtin_ia32_vprotq", -"llvm.x86.xop.vprotqi" => "__builtin_ia32_vprotqi", -"llvm.x86.xop.vprotw" => "__builtin_ia32_vprotw", -"llvm.x86.xop.vprotwi" => "__builtin_ia32_vprotwi", -"llvm.x86.xop.vpshab" => "__builtin_ia32_vpshab", -"llvm.x86.xop.vpshad" => "__builtin_ia32_vpshad", -"llvm.x86.xop.vpshaq" => "__builtin_ia32_vpshaq", -"llvm.x86.xop.vpshaw" => "__builtin_ia32_vpshaw", -"llvm.x86.xop.vpshlb" => "__builtin_ia32_vpshlb", -"llvm.x86.xop.vpshld" => "__builtin_ia32_vpshld", -"llvm.x86.xop.vpshlq" => "__builtin_ia32_vpshlq", -"llvm.x86.xop.vpshlw" => "__builtin_ia32_vpshlw", -"llvm.x86.xtest" => "__builtin_ia32_xtest", -_ => unimplemented!("***** unsupported LLVM intrinsic {}", name), -} From ef1a6d7c23757fec36ee3b353710f56241bbd34b Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Wed, 30 Mar 2022 23:34:05 -0400 Subject: [PATCH 057/356] Fix error related to var tracking assignments --- src/base.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/base.rs b/src/base.rs index d88fe9bca2ac..e4ecbd46f0c4 100644 --- a/src/base.rs +++ b/src/base.rs @@ -89,6 +89,8 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ for arg in &tcx.sess.opts.cg.llvm_args { context.add_command_line_option(arg); } + // NOTE: This is needed to compile the file src/intrinsic/archs.rs during a bootstrap of rustc. + context.add_command_line_option("-fno-var-tracking-assignments"); // NOTE: an optimization (https://github.com/rust-lang/rustc_codegen_gcc/issues/53). context.add_command_line_option("-fno-semantic-interposition"); // NOTE: Rust relies on LLVM not doing TBAA (https://github.com/rust-lang/unsafe-code-guidelines/issues/292). From 035ac03521cd65bd9b5daf1128a0a3f67b939478 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Wed, 30 Mar 2022 20:49:22 +0200 Subject: [PATCH 058/356] Add intrinsics not bound to a specific arch --- src/intrinsic/archs.rs | 1622 ++++++++++++++++++++-------------------- 1 file changed, 811 insertions(+), 811 deletions(-) diff --git a/src/intrinsic/archs.rs b/src/intrinsic/archs.rs index 0376e0afef95..ef8a54f3530b 100644 --- a/src/intrinsic/archs.rs +++ b/src/intrinsic/archs.rs @@ -1,140 +1,58 @@ match name { - // ppc - "llvm.ppc.altivec.dss" => "__builtin_altivec_dss", - "llvm.ppc.altivec.dssall" => "__builtin_altivec_dssall", - "llvm.ppc.altivec.dst" => "__builtin_altivec_dst", - "llvm.ppc.altivec.dstst" => "__builtin_altivec_dstst", - "llvm.ppc.altivec.dststt" => "__builtin_altivec_dststt", - "llvm.ppc.altivec.dstt" => "__builtin_altivec_dstt", - "llvm.ppc.altivec.mfvscr" => "__builtin_altivec_mfvscr", - "llvm.ppc.altivec.mtvscr" => "__builtin_altivec_mtvscr", - "llvm.ppc.altivec.vaddcuw" => "__builtin_altivec_vaddcuw", - "llvm.ppc.altivec.vaddsbs" => "__builtin_altivec_vaddsbs", - "llvm.ppc.altivec.vaddshs" => "__builtin_altivec_vaddshs", - "llvm.ppc.altivec.vaddsws" => "__builtin_altivec_vaddsws", - "llvm.ppc.altivec.vaddubs" => "__builtin_altivec_vaddubs", - "llvm.ppc.altivec.vadduhs" => "__builtin_altivec_vadduhs", - "llvm.ppc.altivec.vadduws" => "__builtin_altivec_vadduws", - "llvm.ppc.altivec.vavgsb" => "__builtin_altivec_vavgsb", - "llvm.ppc.altivec.vavgsh" => "__builtin_altivec_vavgsh", - "llvm.ppc.altivec.vavgsw" => "__builtin_altivec_vavgsw", - "llvm.ppc.altivec.vavgub" => "__builtin_altivec_vavgub", - "llvm.ppc.altivec.vavguh" => "__builtin_altivec_vavguh", - "llvm.ppc.altivec.vavguw" => "__builtin_altivec_vavguw", - "llvm.ppc.altivec.vcfsx" => "__builtin_altivec_vcfsx", - "llvm.ppc.altivec.vcfux" => "__builtin_altivec_vcfux", - "llvm.ppc.altivec.vcmpbfp" => "__builtin_altivec_vcmpbfp", - "llvm.ppc.altivec.vcmpbfp.p" => "__builtin_altivec_vcmpbfp_p", - "llvm.ppc.altivec.vcmpeqfp" => "__builtin_altivec_vcmpeqfp", - "llvm.ppc.altivec.vcmpeqfp.p" => "__builtin_altivec_vcmpeqfp_p", - "llvm.ppc.altivec.vcmpequb" => "__builtin_altivec_vcmpequb", - "llvm.ppc.altivec.vcmpequb.p" => "__builtin_altivec_vcmpequb_p", - "llvm.ppc.altivec.vcmpequh" => "__builtin_altivec_vcmpequh", - "llvm.ppc.altivec.vcmpequh.p" => "__builtin_altivec_vcmpequh_p", - "llvm.ppc.altivec.vcmpequw" => "__builtin_altivec_vcmpequw", - "llvm.ppc.altivec.vcmpequw.p" => "__builtin_altivec_vcmpequw_p", - "llvm.ppc.altivec.vcmpgefp" => "__builtin_altivec_vcmpgefp", - "llvm.ppc.altivec.vcmpgefp.p" => "__builtin_altivec_vcmpgefp_p", - "llvm.ppc.altivec.vcmpgtfp" => "__builtin_altivec_vcmpgtfp", - "llvm.ppc.altivec.vcmpgtfp.p" => "__builtin_altivec_vcmpgtfp_p", - "llvm.ppc.altivec.vcmpgtsb" => "__builtin_altivec_vcmpgtsb", - "llvm.ppc.altivec.vcmpgtsb.p" => "__builtin_altivec_vcmpgtsb_p", - "llvm.ppc.altivec.vcmpgtsh" => "__builtin_altivec_vcmpgtsh", - "llvm.ppc.altivec.vcmpgtsh.p" => "__builtin_altivec_vcmpgtsh_p", - "llvm.ppc.altivec.vcmpgtsw" => "__builtin_altivec_vcmpgtsw", - "llvm.ppc.altivec.vcmpgtsw.p" => "__builtin_altivec_vcmpgtsw_p", - "llvm.ppc.altivec.vcmpgtub" => "__builtin_altivec_vcmpgtub", - "llvm.ppc.altivec.vcmpgtub.p" => "__builtin_altivec_vcmpgtub_p", - "llvm.ppc.altivec.vcmpgtuh" => "__builtin_altivec_vcmpgtuh", - "llvm.ppc.altivec.vcmpgtuh.p" => "__builtin_altivec_vcmpgtuh_p", - "llvm.ppc.altivec.vcmpgtuw" => "__builtin_altivec_vcmpgtuw", - "llvm.ppc.altivec.vcmpgtuw.p" => "__builtin_altivec_vcmpgtuw_p", - "llvm.ppc.altivec.vctsxs" => "__builtin_altivec_vctsxs", - "llvm.ppc.altivec.vctuxs" => "__builtin_altivec_vctuxs", - "llvm.ppc.altivec.vexptefp" => "__builtin_altivec_vexptefp", - "llvm.ppc.altivec.vlogefp" => "__builtin_altivec_vlogefp", - "llvm.ppc.altivec.vmaddfp" => "__builtin_altivec_vmaddfp", - "llvm.ppc.altivec.vmaxfp" => "__builtin_altivec_vmaxfp", - "llvm.ppc.altivec.vmaxsb" => "__builtin_altivec_vmaxsb", - "llvm.ppc.altivec.vmaxsh" => "__builtin_altivec_vmaxsh", - "llvm.ppc.altivec.vmaxsw" => "__builtin_altivec_vmaxsw", - "llvm.ppc.altivec.vmaxub" => "__builtin_altivec_vmaxub", - "llvm.ppc.altivec.vmaxuh" => "__builtin_altivec_vmaxuh", - "llvm.ppc.altivec.vmaxuw" => "__builtin_altivec_vmaxuw", - "llvm.ppc.altivec.vmhaddshs" => "__builtin_altivec_vmhaddshs", - "llvm.ppc.altivec.vmhraddshs" => "__builtin_altivec_vmhraddshs", - "llvm.ppc.altivec.vminfp" => "__builtin_altivec_vminfp", - "llvm.ppc.altivec.vminsb" => "__builtin_altivec_vminsb", - "llvm.ppc.altivec.vminsh" => "__builtin_altivec_vminsh", - "llvm.ppc.altivec.vminsw" => "__builtin_altivec_vminsw", - "llvm.ppc.altivec.vminub" => "__builtin_altivec_vminub", - "llvm.ppc.altivec.vminuh" => "__builtin_altivec_vminuh", - "llvm.ppc.altivec.vminuw" => "__builtin_altivec_vminuw", - "llvm.ppc.altivec.vmladduhm" => "__builtin_altivec_vmladduhm", - "llvm.ppc.altivec.vmsummbm" => "__builtin_altivec_vmsummbm", - "llvm.ppc.altivec.vmsumshm" => "__builtin_altivec_vmsumshm", - "llvm.ppc.altivec.vmsumshs" => "__builtin_altivec_vmsumshs", - "llvm.ppc.altivec.vmsumubm" => "__builtin_altivec_vmsumubm", - "llvm.ppc.altivec.vmsumuhm" => "__builtin_altivec_vmsumuhm", - "llvm.ppc.altivec.vmsumuhs" => "__builtin_altivec_vmsumuhs", - "llvm.ppc.altivec.vmulesb" => "__builtin_altivec_vmulesb", - "llvm.ppc.altivec.vmulesh" => "__builtin_altivec_vmulesh", - "llvm.ppc.altivec.vmuleub" => "__builtin_altivec_vmuleub", - "llvm.ppc.altivec.vmuleuh" => "__builtin_altivec_vmuleuh", - "llvm.ppc.altivec.vmulosb" => "__builtin_altivec_vmulosb", - "llvm.ppc.altivec.vmulosh" => "__builtin_altivec_vmulosh", - "llvm.ppc.altivec.vmuloub" => "__builtin_altivec_vmuloub", - "llvm.ppc.altivec.vmulouh" => "__builtin_altivec_vmulouh", - "llvm.ppc.altivec.vnmsubfp" => "__builtin_altivec_vnmsubfp", - "llvm.ppc.altivec.vperm" => "__builtin_altivec_vperm_4si", - "llvm.ppc.altivec.vpkpx" => "__builtin_altivec_vpkpx", - "llvm.ppc.altivec.vpkshss" => "__builtin_altivec_vpkshss", - "llvm.ppc.altivec.vpkshus" => "__builtin_altivec_vpkshus", - "llvm.ppc.altivec.vpkswss" => "__builtin_altivec_vpkswss", - "llvm.ppc.altivec.vpkswus" => "__builtin_altivec_vpkswus", - "llvm.ppc.altivec.vpkuhus" => "__builtin_altivec_vpkuhus", - "llvm.ppc.altivec.vpkuwus" => "__builtin_altivec_vpkuwus", - "llvm.ppc.altivec.vrefp" => "__builtin_altivec_vrefp", - "llvm.ppc.altivec.vrfim" => "__builtin_altivec_vrfim", - "llvm.ppc.altivec.vrfin" => "__builtin_altivec_vrfin", - "llvm.ppc.altivec.vrfip" => "__builtin_altivec_vrfip", - "llvm.ppc.altivec.vrfiz" => "__builtin_altivec_vrfiz", - "llvm.ppc.altivec.vrlb" => "__builtin_altivec_vrlb", - "llvm.ppc.altivec.vrlh" => "__builtin_altivec_vrlh", - "llvm.ppc.altivec.vrlw" => "__builtin_altivec_vrlw", - "llvm.ppc.altivec.vrsqrtefp" => "__builtin_altivec_vrsqrtefp", - "llvm.ppc.altivec.vsel" => "__builtin_altivec_vsel_4si", - "llvm.ppc.altivec.vsl" => "__builtin_altivec_vsl", - "llvm.ppc.altivec.vslb" => "__builtin_altivec_vslb", - "llvm.ppc.altivec.vslh" => "__builtin_altivec_vslh", - "llvm.ppc.altivec.vslo" => "__builtin_altivec_vslo", - "llvm.ppc.altivec.vslw" => "__builtin_altivec_vslw", - "llvm.ppc.altivec.vsr" => "__builtin_altivec_vsr", - "llvm.ppc.altivec.vsrab" => "__builtin_altivec_vsrab", - "llvm.ppc.altivec.vsrah" => "__builtin_altivec_vsrah", - "llvm.ppc.altivec.vsraw" => "__builtin_altivec_vsraw", - "llvm.ppc.altivec.vsrb" => "__builtin_altivec_vsrb", - "llvm.ppc.altivec.vsrh" => "__builtin_altivec_vsrh", - "llvm.ppc.altivec.vsro" => "__builtin_altivec_vsro", - "llvm.ppc.altivec.vsrw" => "__builtin_altivec_vsrw", - "llvm.ppc.altivec.vsubcuw" => "__builtin_altivec_vsubcuw", - "llvm.ppc.altivec.vsubsbs" => "__builtin_altivec_vsubsbs", - "llvm.ppc.altivec.vsubshs" => "__builtin_altivec_vsubshs", - "llvm.ppc.altivec.vsubsws" => "__builtin_altivec_vsubsws", - "llvm.ppc.altivec.vsububs" => "__builtin_altivec_vsububs", - "llvm.ppc.altivec.vsubuhs" => "__builtin_altivec_vsubuhs", - "llvm.ppc.altivec.vsubuws" => "__builtin_altivec_vsubuws", - "llvm.ppc.altivec.vsum2sws" => "__builtin_altivec_vsum2sws", - "llvm.ppc.altivec.vsum4sbs" => "__builtin_altivec_vsum4sbs", - "llvm.ppc.altivec.vsum4shs" => "__builtin_altivec_vsum4shs", - "llvm.ppc.altivec.vsum4ubs" => "__builtin_altivec_vsum4ubs", - "llvm.ppc.altivec.vsumsws" => "__builtin_altivec_vsumsws", - "llvm.ppc.altivec.vupkhpx" => "__builtin_altivec_vupkhpx", - "llvm.ppc.altivec.vupkhsb" => "__builtin_altivec_vupkhsb", - "llvm.ppc.altivec.vupkhsh" => "__builtin_altivec_vupkhsh", - "llvm.ppc.altivec.vupklpx" => "__builtin_altivec_vupklpx", - "llvm.ppc.altivec.vupklsb" => "__builtin_altivec_vupklsb", - "llvm.ppc.altivec.vupklsh" => "__builtin_altivec_vupklsh", + // AMDGPU + "llvm.AMDGPU.div.fixup.f32" => "__builtin_amdgpu_div_fixup", + "llvm.AMDGPU.div.fixup.f64" => "__builtin_amdgpu_div_fixup", + "llvm.AMDGPU.div.fixup.v2f64" => "__builtin_amdgpu_div_fixup", + "llvm.AMDGPU.div.fixup.v4f32" => "__builtin_amdgpu_div_fixup", + "llvm.AMDGPU.div.fmas.f32" => "__builtin_amdgpu_div_fmas", + "llvm.AMDGPU.div.fmas.f64" => "__builtin_amdgpu_div_fmas", + "llvm.AMDGPU.div.fmas.v2f64" => "__builtin_amdgpu_div_fmas", + "llvm.AMDGPU.div.fmas.v4f32" => "__builtin_amdgpu_div_fmas", + "llvm.AMDGPU.ldexp.f32" => "__builtin_amdgpu_ldexp", + "llvm.AMDGPU.ldexp.f64" => "__builtin_amdgpu_ldexp", + "llvm.AMDGPU.ldexp.v2f64" => "__builtin_amdgpu_ldexp", + "llvm.AMDGPU.ldexp.v4f32" => "__builtin_amdgpu_ldexp", + "llvm.AMDGPU.rcp.f32" => "__builtin_amdgpu_rcp", + "llvm.AMDGPU.rcp.f64" => "__builtin_amdgpu_rcp", + "llvm.AMDGPU.rcp.v2f64" => "__builtin_amdgpu_rcp", + "llvm.AMDGPU.rcp.v4f32" => "__builtin_amdgpu_rcp", + "llvm.AMDGPU.rsq.clamped.f32" => "__builtin_amdgpu_rsq_clamped", + "llvm.AMDGPU.rsq.clamped.f64" => "__builtin_amdgpu_rsq_clamped", + "llvm.AMDGPU.rsq.clamped.v2f64" => "__builtin_amdgpu_rsq_clamped", + "llvm.AMDGPU.rsq.clamped.v4f32" => "__builtin_amdgpu_rsq_clamped", + "llvm.AMDGPU.rsq.f32" => "__builtin_amdgpu_rsq", + "llvm.AMDGPU.rsq.f64" => "__builtin_amdgpu_rsq", + "llvm.AMDGPU.rsq.v2f64" => "__builtin_amdgpu_rsq", + "llvm.AMDGPU.rsq.v4f32" => "__builtin_amdgpu_rsq", + "llvm.AMDGPU.trig.preop.f32" => "__builtin_amdgpu_trig_preop", + "llvm.AMDGPU.trig.preop.f64" => "__builtin_amdgpu_trig_preop", + "llvm.AMDGPU.trig.preop.v2f64" => "__builtin_amdgpu_trig_preop", + "llvm.AMDGPU.trig.preop.v4f32" => "__builtin_amdgpu_trig_preop", + // aarch64 + "llvm.aarch64.dmb" => "__builtin_arm_dmb", + "llvm.aarch64.dsb" => "__builtin_arm_dsb", + "llvm.aarch64.isb" => "__builtin_arm_isb", + // arm + "llvm.arm.cdp" => "__builtin_arm_cdp", + "llvm.arm.cdp2" => "__builtin_arm_cdp2", + "llvm.arm.dmb" => "__builtin_arm_dmb", + "llvm.arm.dsb" => "__builtin_arm_dsb", + "llvm.arm.get.fpscr" => "__builtin_arm_get_fpscr", + "llvm.arm.isb" => "__builtin_arm_isb", + "llvm.arm.mcr" => "__builtin_arm_mcr", + "llvm.arm.mcr2" => "__builtin_arm_mcr2", + "llvm.arm.mcrr" => "__builtin_arm_mcrr", + "llvm.arm.mcrr2" => "__builtin_arm_mcrr2", + "llvm.arm.mrc" => "__builtin_arm_mrc", + "llvm.arm.mrc2" => "__builtin_arm_mrc2", + "llvm.arm.qadd" => "__builtin_arm_qadd", + "llvm.arm.qsub" => "__builtin_arm_qsub", + "llvm.arm.set.fpscr" => "__builtin_arm_set_fpscr", + "llvm.arm.ssat" => "__builtin_arm_ssat", + "llvm.arm.thread.pointer" => "__builtin_thread_pointer", + "llvm.arm.usat" => "__builtin_arm_usat", + // cuda + "llvm.cuda.syncthreads" => "__syncthreads", // hexagon "llvm.hexagon.A2.abs" => "__builtin_HEXAGON_A2_abs", "llvm.hexagon.A2.absp" => "__builtin_HEXAGON_A2_absp", @@ -989,10 +907,607 @@ match name { "llvm.hexagon.S5.vasrhrnd.goodsyntax" => "__builtin_HEXAGON_S5_vasrhrnd_goodsyntax", "llvm.hexagon.SI.to.SXTHI.asrh" => "__builtin_SI_to_SXTHI_asrh", "llvm.hexagon.circ.ldd" => "__builtin_circ_ldd", - // aarch64 - "llvm.aarch64.dmb" => "__builtin_arm_dmb", - "llvm.aarch64.dsb" => "__builtin_arm_dsb", - "llvm.aarch64.isb" => "__builtin_arm_isb", + // mips + "llvm.mips.add.a.b" => "__builtin_msa_add_a_b", + "llvm.mips.add.a.d" => "__builtin_msa_add_a_d", + "llvm.mips.add.a.h" => "__builtin_msa_add_a_h", + "llvm.mips.add.a.w" => "__builtin_msa_add_a_w", + "llvm.mips.adds.a.b" => "__builtin_msa_adds_a_b", + "llvm.mips.adds.a.d" => "__builtin_msa_adds_a_d", + "llvm.mips.adds.a.h" => "__builtin_msa_adds_a_h", + "llvm.mips.adds.a.w" => "__builtin_msa_adds_a_w", + "llvm.mips.adds.s.b" => "__builtin_msa_adds_s_b", + "llvm.mips.adds.s.d" => "__builtin_msa_adds_s_d", + "llvm.mips.adds.s.h" => "__builtin_msa_adds_s_h", + "llvm.mips.adds.s.w" => "__builtin_msa_adds_s_w", + "llvm.mips.adds.u.b" => "__builtin_msa_adds_u_b", + "llvm.mips.adds.u.d" => "__builtin_msa_adds_u_d", + "llvm.mips.adds.u.h" => "__builtin_msa_adds_u_h", + "llvm.mips.adds.u.w" => "__builtin_msa_adds_u_w", + "llvm.mips.addsc" => "__builtin_mips_addsc", + "llvm.mips.addu.ph" => "__builtin_mips_addu_ph", + "llvm.mips.addu.qb" => "__builtin_mips_addu_qb", + "llvm.mips.addu.s.ph" => "__builtin_mips_addu_s_ph", + "llvm.mips.addu.s.qb" => "__builtin_mips_addu_s_qb", + "llvm.mips.adduh.qb" => "__builtin_mips_adduh_qb", + "llvm.mips.adduh.r.qb" => "__builtin_mips_adduh_r_qb", + "llvm.mips.addv.b" => "__builtin_msa_addv_b", + "llvm.mips.addv.d" => "__builtin_msa_addv_d", + "llvm.mips.addv.h" => "__builtin_msa_addv_h", + "llvm.mips.addv.w" => "__builtin_msa_addv_w", + "llvm.mips.addvi.b" => "__builtin_msa_addvi_b", + "llvm.mips.addvi.d" => "__builtin_msa_addvi_d", + "llvm.mips.addvi.h" => "__builtin_msa_addvi_h", + "llvm.mips.addvi.w" => "__builtin_msa_addvi_w", + "llvm.mips.addwc" => "__builtin_mips_addwc", + "llvm.mips.and.v" => "__builtin_msa_and_v", + "llvm.mips.andi.b" => "__builtin_msa_andi_b", + "llvm.mips.append" => "__builtin_mips_append", + "llvm.mips.asub.s.b" => "__builtin_msa_asub_s_b", + "llvm.mips.asub.s.d" => "__builtin_msa_asub_s_d", + "llvm.mips.asub.s.h" => "__builtin_msa_asub_s_h", + "llvm.mips.asub.s.w" => "__builtin_msa_asub_s_w", + "llvm.mips.asub.u.b" => "__builtin_msa_asub_u_b", + "llvm.mips.asub.u.d" => "__builtin_msa_asub_u_d", + "llvm.mips.asub.u.h" => "__builtin_msa_asub_u_h", + "llvm.mips.asub.u.w" => "__builtin_msa_asub_u_w", + "llvm.mips.ave.s.b" => "__builtin_msa_ave_s_b", + "llvm.mips.ave.s.d" => "__builtin_msa_ave_s_d", + "llvm.mips.ave.s.h" => "__builtin_msa_ave_s_h", + "llvm.mips.ave.s.w" => "__builtin_msa_ave_s_w", + "llvm.mips.ave.u.b" => "__builtin_msa_ave_u_b", + "llvm.mips.ave.u.d" => "__builtin_msa_ave_u_d", + "llvm.mips.ave.u.h" => "__builtin_msa_ave_u_h", + "llvm.mips.ave.u.w" => "__builtin_msa_ave_u_w", + "llvm.mips.aver.s.b" => "__builtin_msa_aver_s_b", + "llvm.mips.aver.s.d" => "__builtin_msa_aver_s_d", + "llvm.mips.aver.s.h" => "__builtin_msa_aver_s_h", + "llvm.mips.aver.s.w" => "__builtin_msa_aver_s_w", + "llvm.mips.aver.u.b" => "__builtin_msa_aver_u_b", + "llvm.mips.aver.u.d" => "__builtin_msa_aver_u_d", + "llvm.mips.aver.u.h" => "__builtin_msa_aver_u_h", + "llvm.mips.aver.u.w" => "__builtin_msa_aver_u_w", + "llvm.mips.balign" => "__builtin_mips_balign", + "llvm.mips.bclr.b" => "__builtin_msa_bclr_b", + "llvm.mips.bclr.d" => "__builtin_msa_bclr_d", + "llvm.mips.bclr.h" => "__builtin_msa_bclr_h", + "llvm.mips.bclr.w" => "__builtin_msa_bclr_w", + "llvm.mips.bclri.b" => "__builtin_msa_bclri_b", + "llvm.mips.bclri.d" => "__builtin_msa_bclri_d", + "llvm.mips.bclri.h" => "__builtin_msa_bclri_h", + "llvm.mips.bclri.w" => "__builtin_msa_bclri_w", + "llvm.mips.binsl.b" => "__builtin_msa_binsl_b", + "llvm.mips.binsl.d" => "__builtin_msa_binsl_d", + "llvm.mips.binsl.h" => "__builtin_msa_binsl_h", + "llvm.mips.binsl.w" => "__builtin_msa_binsl_w", + "llvm.mips.binsli.b" => "__builtin_msa_binsli_b", + "llvm.mips.binsli.d" => "__builtin_msa_binsli_d", + "llvm.mips.binsli.h" => "__builtin_msa_binsli_h", + "llvm.mips.binsli.w" => "__builtin_msa_binsli_w", + "llvm.mips.binsr.b" => "__builtin_msa_binsr_b", + "llvm.mips.binsr.d" => "__builtin_msa_binsr_d", + "llvm.mips.binsr.h" => "__builtin_msa_binsr_h", + "llvm.mips.binsr.w" => "__builtin_msa_binsr_w", + "llvm.mips.binsri.b" => "__builtin_msa_binsri_b", + "llvm.mips.binsri.d" => "__builtin_msa_binsri_d", + "llvm.mips.binsri.h" => "__builtin_msa_binsri_h", + "llvm.mips.binsri.w" => "__builtin_msa_binsri_w", + "llvm.mips.bitrev" => "__builtin_mips_bitrev", + "llvm.mips.bmnz.v" => "__builtin_msa_bmnz_v", + "llvm.mips.bmnzi.b" => "__builtin_msa_bmnzi_b", + "llvm.mips.bmz.v" => "__builtin_msa_bmz_v", + "llvm.mips.bmzi.b" => "__builtin_msa_bmzi_b", + "llvm.mips.bneg.b" => "__builtin_msa_bneg_b", + "llvm.mips.bneg.d" => "__builtin_msa_bneg_d", + "llvm.mips.bneg.h" => "__builtin_msa_bneg_h", + "llvm.mips.bneg.w" => "__builtin_msa_bneg_w", + "llvm.mips.bnegi.b" => "__builtin_msa_bnegi_b", + "llvm.mips.bnegi.d" => "__builtin_msa_bnegi_d", + "llvm.mips.bnegi.h" => "__builtin_msa_bnegi_h", + "llvm.mips.bnegi.w" => "__builtin_msa_bnegi_w", + "llvm.mips.bnz.b" => "__builtin_msa_bnz_b", + "llvm.mips.bnz.d" => "__builtin_msa_bnz_d", + "llvm.mips.bnz.h" => "__builtin_msa_bnz_h", + "llvm.mips.bnz.v" => "__builtin_msa_bnz_v", + "llvm.mips.bnz.w" => "__builtin_msa_bnz_w", + "llvm.mips.bposge32" => "__builtin_mips_bposge32", + "llvm.mips.bsel.v" => "__builtin_msa_bsel_v", + "llvm.mips.bseli.b" => "__builtin_msa_bseli_b", + "llvm.mips.bset.b" => "__builtin_msa_bset_b", + "llvm.mips.bset.d" => "__builtin_msa_bset_d", + "llvm.mips.bset.h" => "__builtin_msa_bset_h", + "llvm.mips.bset.w" => "__builtin_msa_bset_w", + "llvm.mips.bseti.b" => "__builtin_msa_bseti_b", + "llvm.mips.bseti.d" => "__builtin_msa_bseti_d", + "llvm.mips.bseti.h" => "__builtin_msa_bseti_h", + "llvm.mips.bseti.w" => "__builtin_msa_bseti_w", + "llvm.mips.bz.b" => "__builtin_msa_bz_b", + "llvm.mips.bz.d" => "__builtin_msa_bz_d", + "llvm.mips.bz.h" => "__builtin_msa_bz_h", + "llvm.mips.bz.v" => "__builtin_msa_bz_v", + "llvm.mips.bz.w" => "__builtin_msa_bz_w", + "llvm.mips.ceq.b" => "__builtin_msa_ceq_b", + "llvm.mips.ceq.d" => "__builtin_msa_ceq_d", + "llvm.mips.ceq.h" => "__builtin_msa_ceq_h", + "llvm.mips.ceq.w" => "__builtin_msa_ceq_w", + "llvm.mips.ceqi.b" => "__builtin_msa_ceqi_b", + "llvm.mips.ceqi.d" => "__builtin_msa_ceqi_d", + "llvm.mips.ceqi.h" => "__builtin_msa_ceqi_h", + "llvm.mips.ceqi.w" => "__builtin_msa_ceqi_w", + "llvm.mips.cfcmsa" => "__builtin_msa_cfcmsa", + "llvm.mips.cle.s.b" => "__builtin_msa_cle_s_b", + "llvm.mips.cle.s.d" => "__builtin_msa_cle_s_d", + "llvm.mips.cle.s.h" => "__builtin_msa_cle_s_h", + "llvm.mips.cle.s.w" => "__builtin_msa_cle_s_w", + "llvm.mips.cle.u.b" => "__builtin_msa_cle_u_b", + "llvm.mips.cle.u.d" => "__builtin_msa_cle_u_d", + "llvm.mips.cle.u.h" => "__builtin_msa_cle_u_h", + "llvm.mips.cle.u.w" => "__builtin_msa_cle_u_w", + "llvm.mips.clei.s.b" => "__builtin_msa_clei_s_b", + "llvm.mips.clei.s.d" => "__builtin_msa_clei_s_d", + "llvm.mips.clei.s.h" => "__builtin_msa_clei_s_h", + "llvm.mips.clei.s.w" => "__builtin_msa_clei_s_w", + "llvm.mips.clei.u.b" => "__builtin_msa_clei_u_b", + "llvm.mips.clei.u.d" => "__builtin_msa_clei_u_d", + "llvm.mips.clei.u.h" => "__builtin_msa_clei_u_h", + "llvm.mips.clei.u.w" => "__builtin_msa_clei_u_w", + "llvm.mips.clt.s.b" => "__builtin_msa_clt_s_b", + "llvm.mips.clt.s.d" => "__builtin_msa_clt_s_d", + "llvm.mips.clt.s.h" => "__builtin_msa_clt_s_h", + "llvm.mips.clt.s.w" => "__builtin_msa_clt_s_w", + "llvm.mips.clt.u.b" => "__builtin_msa_clt_u_b", + "llvm.mips.clt.u.d" => "__builtin_msa_clt_u_d", + "llvm.mips.clt.u.h" => "__builtin_msa_clt_u_h", + "llvm.mips.clt.u.w" => "__builtin_msa_clt_u_w", + "llvm.mips.clti.s.b" => "__builtin_msa_clti_s_b", + "llvm.mips.clti.s.d" => "__builtin_msa_clti_s_d", + "llvm.mips.clti.s.h" => "__builtin_msa_clti_s_h", + "llvm.mips.clti.s.w" => "__builtin_msa_clti_s_w", + "llvm.mips.clti.u.b" => "__builtin_msa_clti_u_b", + "llvm.mips.clti.u.d" => "__builtin_msa_clti_u_d", + "llvm.mips.clti.u.h" => "__builtin_msa_clti_u_h", + "llvm.mips.clti.u.w" => "__builtin_msa_clti_u_w", + "llvm.mips.cmpgdu.eq.qb" => "__builtin_mips_cmpgdu_eq_qb", + "llvm.mips.cmpgdu.le.qb" => "__builtin_mips_cmpgdu_le_qb", + "llvm.mips.cmpgdu.lt.qb" => "__builtin_mips_cmpgdu_lt_qb", + "llvm.mips.cmpgu.eq.qb" => "__builtin_mips_cmpgu_eq_qb", + "llvm.mips.cmpgu.le.qb" => "__builtin_mips_cmpgu_le_qb", + "llvm.mips.cmpgu.lt.qb" => "__builtin_mips_cmpgu_lt_qb", + "llvm.mips.cmpu.eq.qb" => "__builtin_mips_cmpu_eq_qb", + "llvm.mips.cmpu.le.qb" => "__builtin_mips_cmpu_le_qb", + "llvm.mips.cmpu.lt.qb" => "__builtin_mips_cmpu_lt_qb", + "llvm.mips.copy.s.b" => "__builtin_msa_copy_s_b", + "llvm.mips.copy.s.d" => "__builtin_msa_copy_s_d", + "llvm.mips.copy.s.h" => "__builtin_msa_copy_s_h", + "llvm.mips.copy.s.w" => "__builtin_msa_copy_s_w", + "llvm.mips.copy.u.b" => "__builtin_msa_copy_u_b", + "llvm.mips.copy.u.d" => "__builtin_msa_copy_u_d", + "llvm.mips.copy.u.h" => "__builtin_msa_copy_u_h", + "llvm.mips.copy.u.w" => "__builtin_msa_copy_u_w", + "llvm.mips.ctcmsa" => "__builtin_msa_ctcmsa", + "llvm.mips.div.s.b" => "__builtin_msa_div_s_b", + "llvm.mips.div.s.d" => "__builtin_msa_div_s_d", + "llvm.mips.div.s.h" => "__builtin_msa_div_s_h", + "llvm.mips.div.s.w" => "__builtin_msa_div_s_w", + "llvm.mips.div.u.b" => "__builtin_msa_div_u_b", + "llvm.mips.div.u.d" => "__builtin_msa_div_u_d", + "llvm.mips.div.u.h" => "__builtin_msa_div_u_h", + "llvm.mips.div.u.w" => "__builtin_msa_div_u_w", + "llvm.mips.dlsa" => "__builtin_mips_dlsa", + "llvm.mips.dotp.s.d" => "__builtin_msa_dotp_s_d", + "llvm.mips.dotp.s.h" => "__builtin_msa_dotp_s_h", + "llvm.mips.dotp.s.w" => "__builtin_msa_dotp_s_w", + "llvm.mips.dotp.u.d" => "__builtin_msa_dotp_u_d", + "llvm.mips.dotp.u.h" => "__builtin_msa_dotp_u_h", + "llvm.mips.dotp.u.w" => "__builtin_msa_dotp_u_w", + "llvm.mips.dpa.w.ph" => "__builtin_mips_dpa_w_ph", + "llvm.mips.dpadd.s.d" => "__builtin_msa_dpadd_s_d", + "llvm.mips.dpadd.s.h" => "__builtin_msa_dpadd_s_h", + "llvm.mips.dpadd.s.w" => "__builtin_msa_dpadd_s_w", + "llvm.mips.dpadd.u.d" => "__builtin_msa_dpadd_u_d", + "llvm.mips.dpadd.u.h" => "__builtin_msa_dpadd_u_h", + "llvm.mips.dpadd.u.w" => "__builtin_msa_dpadd_u_w", + "llvm.mips.dpau.h.qbl" => "__builtin_mips_dpau_h_qbl", + "llvm.mips.dpau.h.qbr" => "__builtin_mips_dpau_h_qbr", + "llvm.mips.dpax.w.ph" => "__builtin_mips_dpax_w_ph", + "llvm.mips.dps.w.ph" => "__builtin_mips_dps_w_ph", + "llvm.mips.dpsu.h.qbl" => "__builtin_mips_dpsu_h_qbl", + "llvm.mips.dpsu.h.qbr" => "__builtin_mips_dpsu_h_qbr", + "llvm.mips.dpsub.s.d" => "__builtin_msa_dpsub_s_d", + "llvm.mips.dpsub.s.h" => "__builtin_msa_dpsub_s_h", + "llvm.mips.dpsub.s.w" => "__builtin_msa_dpsub_s_w", + "llvm.mips.dpsub.u.d" => "__builtin_msa_dpsub_u_d", + "llvm.mips.dpsub.u.h" => "__builtin_msa_dpsub_u_h", + "llvm.mips.dpsub.u.w" => "__builtin_msa_dpsub_u_w", + "llvm.mips.dpsx.w.ph" => "__builtin_mips_dpsx_w_ph", + "llvm.mips.extp" => "__builtin_mips_extp", + "llvm.mips.extpdp" => "__builtin_mips_extpdp", + "llvm.mips.extr.r.w" => "__builtin_mips_extr_r_w", + "llvm.mips.extr.rs.w" => "__builtin_mips_extr_rs_w", + "llvm.mips.extr.s.h" => "__builtin_mips_extr_s_h", + "llvm.mips.extr.w" => "__builtin_mips_extr_w", + "llvm.mips.fadd.d" => "__builtin_msa_fadd_d", + "llvm.mips.fadd.w" => "__builtin_msa_fadd_w", + "llvm.mips.fcaf.d" => "__builtin_msa_fcaf_d", + "llvm.mips.fcaf.w" => "__builtin_msa_fcaf_w", + "llvm.mips.fceq.d" => "__builtin_msa_fceq_d", + "llvm.mips.fceq.w" => "__builtin_msa_fceq_w", + "llvm.mips.fclass.d" => "__builtin_msa_fclass_d", + "llvm.mips.fclass.w" => "__builtin_msa_fclass_w", + "llvm.mips.fcle.d" => "__builtin_msa_fcle_d", + "llvm.mips.fcle.w" => "__builtin_msa_fcle_w", + "llvm.mips.fclt.d" => "__builtin_msa_fclt_d", + "llvm.mips.fclt.w" => "__builtin_msa_fclt_w", + "llvm.mips.fcne.d" => "__builtin_msa_fcne_d", + "llvm.mips.fcne.w" => "__builtin_msa_fcne_w", + "llvm.mips.fcor.d" => "__builtin_msa_fcor_d", + "llvm.mips.fcor.w" => "__builtin_msa_fcor_w", + "llvm.mips.fcueq.d" => "__builtin_msa_fcueq_d", + "llvm.mips.fcueq.w" => "__builtin_msa_fcueq_w", + "llvm.mips.fcule.d" => "__builtin_msa_fcule_d", + "llvm.mips.fcule.w" => "__builtin_msa_fcule_w", + "llvm.mips.fcult.d" => "__builtin_msa_fcult_d", + "llvm.mips.fcult.w" => "__builtin_msa_fcult_w", + "llvm.mips.fcun.d" => "__builtin_msa_fcun_d", + "llvm.mips.fcun.w" => "__builtin_msa_fcun_w", + "llvm.mips.fcune.d" => "__builtin_msa_fcune_d", + "llvm.mips.fcune.w" => "__builtin_msa_fcune_w", + "llvm.mips.fdiv.d" => "__builtin_msa_fdiv_d", + "llvm.mips.fdiv.w" => "__builtin_msa_fdiv_w", + "llvm.mips.fexdo.w" => "__builtin_msa_fexdo_w", + "llvm.mips.fexp2.d" => "__builtin_msa_fexp2_d", + "llvm.mips.fexp2.w" => "__builtin_msa_fexp2_w", + "llvm.mips.fexupl.d" => "__builtin_msa_fexupl_d", + "llvm.mips.fexupr.d" => "__builtin_msa_fexupr_d", + "llvm.mips.ffint.s.d" => "__builtin_msa_ffint_s_d", + "llvm.mips.ffint.s.w" => "__builtin_msa_ffint_s_w", + "llvm.mips.ffint.u.d" => "__builtin_msa_ffint_u_d", + "llvm.mips.ffint.u.w" => "__builtin_msa_ffint_u_w", + "llvm.mips.ffql.d" => "__builtin_msa_ffql_d", + "llvm.mips.ffql.w" => "__builtin_msa_ffql_w", + "llvm.mips.ffqr.d" => "__builtin_msa_ffqr_d", + "llvm.mips.ffqr.w" => "__builtin_msa_ffqr_w", + "llvm.mips.fill.b" => "__builtin_msa_fill_b", + "llvm.mips.fill.d" => "__builtin_msa_fill_d", + "llvm.mips.fill.h" => "__builtin_msa_fill_h", + "llvm.mips.fill.w" => "__builtin_msa_fill_w", + "llvm.mips.flog2.d" => "__builtin_msa_flog2_d", + "llvm.mips.flog2.w" => "__builtin_msa_flog2_w", + "llvm.mips.fmadd.d" => "__builtin_msa_fmadd_d", + "llvm.mips.fmadd.w" => "__builtin_msa_fmadd_w", + "llvm.mips.fmax.a.d" => "__builtin_msa_fmax_a_d", + "llvm.mips.fmax.a.w" => "__builtin_msa_fmax_a_w", + "llvm.mips.fmax.d" => "__builtin_msa_fmax_d", + "llvm.mips.fmax.w" => "__builtin_msa_fmax_w", + "llvm.mips.fmin.a.d" => "__builtin_msa_fmin_a_d", + "llvm.mips.fmin.a.w" => "__builtin_msa_fmin_a_w", + "llvm.mips.fmin.d" => "__builtin_msa_fmin_d", + "llvm.mips.fmin.w" => "__builtin_msa_fmin_w", + "llvm.mips.fmsub.d" => "__builtin_msa_fmsub_d", + "llvm.mips.fmsub.w" => "__builtin_msa_fmsub_w", + "llvm.mips.fmul.d" => "__builtin_msa_fmul_d", + "llvm.mips.fmul.w" => "__builtin_msa_fmul_w", + "llvm.mips.frcp.d" => "__builtin_msa_frcp_d", + "llvm.mips.frcp.w" => "__builtin_msa_frcp_w", + "llvm.mips.frint.d" => "__builtin_msa_frint_d", + "llvm.mips.frint.w" => "__builtin_msa_frint_w", + "llvm.mips.frsqrt.d" => "__builtin_msa_frsqrt_d", + "llvm.mips.frsqrt.w" => "__builtin_msa_frsqrt_w", + "llvm.mips.fsaf.d" => "__builtin_msa_fsaf_d", + "llvm.mips.fsaf.w" => "__builtin_msa_fsaf_w", + "llvm.mips.fseq.d" => "__builtin_msa_fseq_d", + "llvm.mips.fseq.w" => "__builtin_msa_fseq_w", + "llvm.mips.fsle.d" => "__builtin_msa_fsle_d", + "llvm.mips.fsle.w" => "__builtin_msa_fsle_w", + "llvm.mips.fslt.d" => "__builtin_msa_fslt_d", + "llvm.mips.fslt.w" => "__builtin_msa_fslt_w", + "llvm.mips.fsne.d" => "__builtin_msa_fsne_d", + "llvm.mips.fsne.w" => "__builtin_msa_fsne_w", + "llvm.mips.fsor.d" => "__builtin_msa_fsor_d", + "llvm.mips.fsor.w" => "__builtin_msa_fsor_w", + "llvm.mips.fsqrt.d" => "__builtin_msa_fsqrt_d", + "llvm.mips.fsqrt.w" => "__builtin_msa_fsqrt_w", + "llvm.mips.fsub.d" => "__builtin_msa_fsub_d", + "llvm.mips.fsub.w" => "__builtin_msa_fsub_w", + "llvm.mips.fsueq.d" => "__builtin_msa_fsueq_d", + "llvm.mips.fsueq.w" => "__builtin_msa_fsueq_w", + "llvm.mips.fsule.d" => "__builtin_msa_fsule_d", + "llvm.mips.fsule.w" => "__builtin_msa_fsule_w", + "llvm.mips.fsult.d" => "__builtin_msa_fsult_d", + "llvm.mips.fsult.w" => "__builtin_msa_fsult_w", + "llvm.mips.fsun.d" => "__builtin_msa_fsun_d", + "llvm.mips.fsun.w" => "__builtin_msa_fsun_w", + "llvm.mips.fsune.d" => "__builtin_msa_fsune_d", + "llvm.mips.fsune.w" => "__builtin_msa_fsune_w", + "llvm.mips.ftint.s.d" => "__builtin_msa_ftint_s_d", + "llvm.mips.ftint.s.w" => "__builtin_msa_ftint_s_w", + "llvm.mips.ftint.u.d" => "__builtin_msa_ftint_u_d", + "llvm.mips.ftint.u.w" => "__builtin_msa_ftint_u_w", + "llvm.mips.ftq.h" => "__builtin_msa_ftq_h", + "llvm.mips.ftq.w" => "__builtin_msa_ftq_w", + "llvm.mips.ftrunc.s.d" => "__builtin_msa_ftrunc_s_d", + "llvm.mips.ftrunc.s.w" => "__builtin_msa_ftrunc_s_w", + "llvm.mips.ftrunc.u.d" => "__builtin_msa_ftrunc_u_d", + "llvm.mips.ftrunc.u.w" => "__builtin_msa_ftrunc_u_w", + "llvm.mips.hadd.s.d" => "__builtin_msa_hadd_s_d", + "llvm.mips.hadd.s.h" => "__builtin_msa_hadd_s_h", + "llvm.mips.hadd.s.w" => "__builtin_msa_hadd_s_w", + "llvm.mips.hadd.u.d" => "__builtin_msa_hadd_u_d", + "llvm.mips.hadd.u.h" => "__builtin_msa_hadd_u_h", + "llvm.mips.hadd.u.w" => "__builtin_msa_hadd_u_w", + "llvm.mips.hsub.s.d" => "__builtin_msa_hsub_s_d", + "llvm.mips.hsub.s.h" => "__builtin_msa_hsub_s_h", + "llvm.mips.hsub.s.w" => "__builtin_msa_hsub_s_w", + "llvm.mips.hsub.u.d" => "__builtin_msa_hsub_u_d", + "llvm.mips.hsub.u.h" => "__builtin_msa_hsub_u_h", + "llvm.mips.hsub.u.w" => "__builtin_msa_hsub_u_w", + "llvm.mips.ilvev.b" => "__builtin_msa_ilvev_b", + "llvm.mips.ilvev.d" => "__builtin_msa_ilvev_d", + "llvm.mips.ilvev.h" => "__builtin_msa_ilvev_h", + "llvm.mips.ilvev.w" => "__builtin_msa_ilvev_w", + "llvm.mips.ilvl.b" => "__builtin_msa_ilvl_b", + "llvm.mips.ilvl.d" => "__builtin_msa_ilvl_d", + "llvm.mips.ilvl.h" => "__builtin_msa_ilvl_h", + "llvm.mips.ilvl.w" => "__builtin_msa_ilvl_w", + "llvm.mips.ilvod.b" => "__builtin_msa_ilvod_b", + "llvm.mips.ilvod.d" => "__builtin_msa_ilvod_d", + "llvm.mips.ilvod.h" => "__builtin_msa_ilvod_h", + "llvm.mips.ilvod.w" => "__builtin_msa_ilvod_w", + "llvm.mips.ilvr.b" => "__builtin_msa_ilvr_b", + "llvm.mips.ilvr.d" => "__builtin_msa_ilvr_d", + "llvm.mips.ilvr.h" => "__builtin_msa_ilvr_h", + "llvm.mips.ilvr.w" => "__builtin_msa_ilvr_w", + "llvm.mips.insert.b" => "__builtin_msa_insert_b", + "llvm.mips.insert.d" => "__builtin_msa_insert_d", + "llvm.mips.insert.h" => "__builtin_msa_insert_h", + "llvm.mips.insert.w" => "__builtin_msa_insert_w", + "llvm.mips.insv" => "__builtin_mips_insv", + "llvm.mips.insve.b" => "__builtin_msa_insve_b", + "llvm.mips.insve.d" => "__builtin_msa_insve_d", + "llvm.mips.insve.h" => "__builtin_msa_insve_h", + "llvm.mips.insve.w" => "__builtin_msa_insve_w", + "llvm.mips.lbux" => "__builtin_mips_lbux", + "llvm.mips.ld.b" => "__builtin_msa_ld_b", + "llvm.mips.ld.d" => "__builtin_msa_ld_d", + "llvm.mips.ld.h" => "__builtin_msa_ld_h", + "llvm.mips.ld.w" => "__builtin_msa_ld_w", + "llvm.mips.ldi.b" => "__builtin_msa_ldi_b", + "llvm.mips.ldi.d" => "__builtin_msa_ldi_d", + "llvm.mips.ldi.h" => "__builtin_msa_ldi_h", + "llvm.mips.ldi.w" => "__builtin_msa_ldi_w", + "llvm.mips.lhx" => "__builtin_mips_lhx", + "llvm.mips.lsa" => "__builtin_mips_lsa", + "llvm.mips.lwx" => "__builtin_mips_lwx", + "llvm.mips.madd" => "__builtin_mips_madd", + "llvm.mips.madd.q.h" => "__builtin_msa_madd_q_h", + "llvm.mips.madd.q.w" => "__builtin_msa_madd_q_w", + "llvm.mips.maddr.q.h" => "__builtin_msa_maddr_q_h", + "llvm.mips.maddr.q.w" => "__builtin_msa_maddr_q_w", + "llvm.mips.maddu" => "__builtin_mips_maddu", + "llvm.mips.maddv.b" => "__builtin_msa_maddv_b", + "llvm.mips.maddv.d" => "__builtin_msa_maddv_d", + "llvm.mips.maddv.h" => "__builtin_msa_maddv_h", + "llvm.mips.maddv.w" => "__builtin_msa_maddv_w", + "llvm.mips.max.a.b" => "__builtin_msa_max_a_b", + "llvm.mips.max.a.d" => "__builtin_msa_max_a_d", + "llvm.mips.max.a.h" => "__builtin_msa_max_a_h", + "llvm.mips.max.a.w" => "__builtin_msa_max_a_w", + "llvm.mips.max.s.b" => "__builtin_msa_max_s_b", + "llvm.mips.max.s.d" => "__builtin_msa_max_s_d", + "llvm.mips.max.s.h" => "__builtin_msa_max_s_h", + "llvm.mips.max.s.w" => "__builtin_msa_max_s_w", + "llvm.mips.max.u.b" => "__builtin_msa_max_u_b", + "llvm.mips.max.u.d" => "__builtin_msa_max_u_d", + "llvm.mips.max.u.h" => "__builtin_msa_max_u_h", + "llvm.mips.max.u.w" => "__builtin_msa_max_u_w", + "llvm.mips.maxi.s.b" => "__builtin_msa_maxi_s_b", + "llvm.mips.maxi.s.d" => "__builtin_msa_maxi_s_d", + "llvm.mips.maxi.s.h" => "__builtin_msa_maxi_s_h", + "llvm.mips.maxi.s.w" => "__builtin_msa_maxi_s_w", + "llvm.mips.maxi.u.b" => "__builtin_msa_maxi_u_b", + "llvm.mips.maxi.u.d" => "__builtin_msa_maxi_u_d", + "llvm.mips.maxi.u.h" => "__builtin_msa_maxi_u_h", + "llvm.mips.maxi.u.w" => "__builtin_msa_maxi_u_w", + "llvm.mips.min.a.b" => "__builtin_msa_min_a_b", + "llvm.mips.min.a.d" => "__builtin_msa_min_a_d", + "llvm.mips.min.a.h" => "__builtin_msa_min_a_h", + "llvm.mips.min.a.w" => "__builtin_msa_min_a_w", + "llvm.mips.min.s.b" => "__builtin_msa_min_s_b", + "llvm.mips.min.s.d" => "__builtin_msa_min_s_d", + "llvm.mips.min.s.h" => "__builtin_msa_min_s_h", + "llvm.mips.min.s.w" => "__builtin_msa_min_s_w", + "llvm.mips.min.u.b" => "__builtin_msa_min_u_b", + "llvm.mips.min.u.d" => "__builtin_msa_min_u_d", + "llvm.mips.min.u.h" => "__builtin_msa_min_u_h", + "llvm.mips.min.u.w" => "__builtin_msa_min_u_w", + "llvm.mips.mini.s.b" => "__builtin_msa_mini_s_b", + "llvm.mips.mini.s.d" => "__builtin_msa_mini_s_d", + "llvm.mips.mini.s.h" => "__builtin_msa_mini_s_h", + "llvm.mips.mini.s.w" => "__builtin_msa_mini_s_w", + "llvm.mips.mini.u.b" => "__builtin_msa_mini_u_b", + "llvm.mips.mini.u.d" => "__builtin_msa_mini_u_d", + "llvm.mips.mini.u.h" => "__builtin_msa_mini_u_h", + "llvm.mips.mini.u.w" => "__builtin_msa_mini_u_w", + "llvm.mips.mod.s.b" => "__builtin_msa_mod_s_b", + "llvm.mips.mod.s.d" => "__builtin_msa_mod_s_d", + "llvm.mips.mod.s.h" => "__builtin_msa_mod_s_h", + "llvm.mips.mod.s.w" => "__builtin_msa_mod_s_w", + "llvm.mips.mod.u.b" => "__builtin_msa_mod_u_b", + "llvm.mips.mod.u.d" => "__builtin_msa_mod_u_d", + "llvm.mips.mod.u.h" => "__builtin_msa_mod_u_h", + "llvm.mips.mod.u.w" => "__builtin_msa_mod_u_w", + "llvm.mips.modsub" => "__builtin_mips_modsub", + "llvm.mips.move.v" => "__builtin_msa_move_v", + "llvm.mips.msub" => "__builtin_mips_msub", + "llvm.mips.msub.q.h" => "__builtin_msa_msub_q_h", + "llvm.mips.msub.q.w" => "__builtin_msa_msub_q_w", + "llvm.mips.msubr.q.h" => "__builtin_msa_msubr_q_h", + "llvm.mips.msubr.q.w" => "__builtin_msa_msubr_q_w", + "llvm.mips.msubu" => "__builtin_mips_msubu", + "llvm.mips.msubv.b" => "__builtin_msa_msubv_b", + "llvm.mips.msubv.d" => "__builtin_msa_msubv_d", + "llvm.mips.msubv.h" => "__builtin_msa_msubv_h", + "llvm.mips.msubv.w" => "__builtin_msa_msubv_w", + "llvm.mips.mthlip" => "__builtin_mips_mthlip", + "llvm.mips.mul.ph" => "__builtin_mips_mul_ph", + "llvm.mips.mul.q.h" => "__builtin_msa_mul_q_h", + "llvm.mips.mul.q.w" => "__builtin_msa_mul_q_w", + "llvm.mips.mul.s.ph" => "__builtin_mips_mul_s_ph", + "llvm.mips.mulr.q.h" => "__builtin_msa_mulr_q_h", + "llvm.mips.mulr.q.w" => "__builtin_msa_mulr_q_w", + "llvm.mips.mulsa.w.ph" => "__builtin_mips_mulsa_w_ph", + "llvm.mips.mult" => "__builtin_mips_mult", + "llvm.mips.multu" => "__builtin_mips_multu", + "llvm.mips.mulv.b" => "__builtin_msa_mulv_b", + "llvm.mips.mulv.d" => "__builtin_msa_mulv_d", + "llvm.mips.mulv.h" => "__builtin_msa_mulv_h", + "llvm.mips.mulv.w" => "__builtin_msa_mulv_w", + "llvm.mips.nloc.b" => "__builtin_msa_nloc_b", + "llvm.mips.nloc.d" => "__builtin_msa_nloc_d", + "llvm.mips.nloc.h" => "__builtin_msa_nloc_h", + "llvm.mips.nloc.w" => "__builtin_msa_nloc_w", + "llvm.mips.nlzc.b" => "__builtin_msa_nlzc_b", + "llvm.mips.nlzc.d" => "__builtin_msa_nlzc_d", + "llvm.mips.nlzc.h" => "__builtin_msa_nlzc_h", + "llvm.mips.nlzc.w" => "__builtin_msa_nlzc_w", + "llvm.mips.nor.v" => "__builtin_msa_nor_v", + "llvm.mips.nori.b" => "__builtin_msa_nori_b", + "llvm.mips.or.v" => "__builtin_msa_or_v", + "llvm.mips.ori.b" => "__builtin_msa_ori_b", + "llvm.mips.pckev.b" => "__builtin_msa_pckev_b", + "llvm.mips.pckev.d" => "__builtin_msa_pckev_d", + "llvm.mips.pckev.h" => "__builtin_msa_pckev_h", + "llvm.mips.pckev.w" => "__builtin_msa_pckev_w", + "llvm.mips.pckod.b" => "__builtin_msa_pckod_b", + "llvm.mips.pckod.d" => "__builtin_msa_pckod_d", + "llvm.mips.pckod.h" => "__builtin_msa_pckod_h", + "llvm.mips.pckod.w" => "__builtin_msa_pckod_w", + "llvm.mips.pcnt.b" => "__builtin_msa_pcnt_b", + "llvm.mips.pcnt.d" => "__builtin_msa_pcnt_d", + "llvm.mips.pcnt.h" => "__builtin_msa_pcnt_h", + "llvm.mips.pcnt.w" => "__builtin_msa_pcnt_w", + "llvm.mips.pick.qb" => "__builtin_mips_pick_qb", + "llvm.mips.precr.qb.ph" => "__builtin_mips_precr_qb_ph", + "llvm.mips.precr.sra.ph.w" => "__builtin_mips_precr_sra_ph_w", + "llvm.mips.precr.sra.r.ph.w" => "__builtin_mips_precr_sra_r_ph_w", + "llvm.mips.prepend" => "__builtin_mips_prepend", + "llvm.mips.raddu.w.qb" => "__builtin_mips_raddu_w_qb", + "llvm.mips.rddsp" => "__builtin_mips_rddsp", + "llvm.mips.repl.qb" => "__builtin_mips_repl_qb", + "llvm.mips.sat.s.b" => "__builtin_msa_sat_s_b", + "llvm.mips.sat.s.d" => "__builtin_msa_sat_s_d", + "llvm.mips.sat.s.h" => "__builtin_msa_sat_s_h", + "llvm.mips.sat.s.w" => "__builtin_msa_sat_s_w", + "llvm.mips.sat.u.b" => "__builtin_msa_sat_u_b", + "llvm.mips.sat.u.d" => "__builtin_msa_sat_u_d", + "llvm.mips.sat.u.h" => "__builtin_msa_sat_u_h", + "llvm.mips.sat.u.w" => "__builtin_msa_sat_u_w", + "llvm.mips.shf.b" => "__builtin_msa_shf_b", + "llvm.mips.shf.h" => "__builtin_msa_shf_h", + "llvm.mips.shf.w" => "__builtin_msa_shf_w", + "llvm.mips.shilo" => "__builtin_mips_shilo", + "llvm.mips.shll.qb" => "__builtin_mips_shll_qb", + "llvm.mips.shra.qb" => "__builtin_mips_shra_qb", + "llvm.mips.shra.r.qb" => "__builtin_mips_shra_r_qb", + "llvm.mips.shrl.ph" => "__builtin_mips_shrl_ph", + "llvm.mips.shrl.qb" => "__builtin_mips_shrl_qb", + "llvm.mips.sld.b" => "__builtin_msa_sld_b", + "llvm.mips.sld.d" => "__builtin_msa_sld_d", + "llvm.mips.sld.h" => "__builtin_msa_sld_h", + "llvm.mips.sld.w" => "__builtin_msa_sld_w", + "llvm.mips.sldi.b" => "__builtin_msa_sldi_b", + "llvm.mips.sldi.d" => "__builtin_msa_sldi_d", + "llvm.mips.sldi.h" => "__builtin_msa_sldi_h", + "llvm.mips.sldi.w" => "__builtin_msa_sldi_w", + "llvm.mips.sll.b" => "__builtin_msa_sll_b", + "llvm.mips.sll.d" => "__builtin_msa_sll_d", + "llvm.mips.sll.h" => "__builtin_msa_sll_h", + "llvm.mips.sll.w" => "__builtin_msa_sll_w", + "llvm.mips.slli.b" => "__builtin_msa_slli_b", + "llvm.mips.slli.d" => "__builtin_msa_slli_d", + "llvm.mips.slli.h" => "__builtin_msa_slli_h", + "llvm.mips.slli.w" => "__builtin_msa_slli_w", + "llvm.mips.splat.b" => "__builtin_msa_splat_b", + "llvm.mips.splat.d" => "__builtin_msa_splat_d", + "llvm.mips.splat.h" => "__builtin_msa_splat_h", + "llvm.mips.splat.w" => "__builtin_msa_splat_w", + "llvm.mips.splati.b" => "__builtin_msa_splati_b", + "llvm.mips.splati.d" => "__builtin_msa_splati_d", + "llvm.mips.splati.h" => "__builtin_msa_splati_h", + "llvm.mips.splati.w" => "__builtin_msa_splati_w", + "llvm.mips.sra.b" => "__builtin_msa_sra_b", + "llvm.mips.sra.d" => "__builtin_msa_sra_d", + "llvm.mips.sra.h" => "__builtin_msa_sra_h", + "llvm.mips.sra.w" => "__builtin_msa_sra_w", + "llvm.mips.srai.b" => "__builtin_msa_srai_b", + "llvm.mips.srai.d" => "__builtin_msa_srai_d", + "llvm.mips.srai.h" => "__builtin_msa_srai_h", + "llvm.mips.srai.w" => "__builtin_msa_srai_w", + "llvm.mips.srar.b" => "__builtin_msa_srar_b", + "llvm.mips.srar.d" => "__builtin_msa_srar_d", + "llvm.mips.srar.h" => "__builtin_msa_srar_h", + "llvm.mips.srar.w" => "__builtin_msa_srar_w", + "llvm.mips.srari.b" => "__builtin_msa_srari_b", + "llvm.mips.srari.d" => "__builtin_msa_srari_d", + "llvm.mips.srari.h" => "__builtin_msa_srari_h", + "llvm.mips.srari.w" => "__builtin_msa_srari_w", + "llvm.mips.srl.b" => "__builtin_msa_srl_b", + "llvm.mips.srl.d" => "__builtin_msa_srl_d", + "llvm.mips.srl.h" => "__builtin_msa_srl_h", + "llvm.mips.srl.w" => "__builtin_msa_srl_w", + "llvm.mips.srli.b" => "__builtin_msa_srli_b", + "llvm.mips.srli.d" => "__builtin_msa_srli_d", + "llvm.mips.srli.h" => "__builtin_msa_srli_h", + "llvm.mips.srli.w" => "__builtin_msa_srli_w", + "llvm.mips.srlr.b" => "__builtin_msa_srlr_b", + "llvm.mips.srlr.d" => "__builtin_msa_srlr_d", + "llvm.mips.srlr.h" => "__builtin_msa_srlr_h", + "llvm.mips.srlr.w" => "__builtin_msa_srlr_w", + "llvm.mips.srlri.b" => "__builtin_msa_srlri_b", + "llvm.mips.srlri.d" => "__builtin_msa_srlri_d", + "llvm.mips.srlri.h" => "__builtin_msa_srlri_h", + "llvm.mips.srlri.w" => "__builtin_msa_srlri_w", + "llvm.mips.st.b" => "__builtin_msa_st_b", + "llvm.mips.st.d" => "__builtin_msa_st_d", + "llvm.mips.st.h" => "__builtin_msa_st_h", + "llvm.mips.st.w" => "__builtin_msa_st_w", + "llvm.mips.subs.s.b" => "__builtin_msa_subs_s_b", + "llvm.mips.subs.s.d" => "__builtin_msa_subs_s_d", + "llvm.mips.subs.s.h" => "__builtin_msa_subs_s_h", + "llvm.mips.subs.s.w" => "__builtin_msa_subs_s_w", + "llvm.mips.subs.u.b" => "__builtin_msa_subs_u_b", + "llvm.mips.subs.u.d" => "__builtin_msa_subs_u_d", + "llvm.mips.subs.u.h" => "__builtin_msa_subs_u_h", + "llvm.mips.subs.u.w" => "__builtin_msa_subs_u_w", + "llvm.mips.subsus.u.b" => "__builtin_msa_subsus_u_b", + "llvm.mips.subsus.u.d" => "__builtin_msa_subsus_u_d", + "llvm.mips.subsus.u.h" => "__builtin_msa_subsus_u_h", + "llvm.mips.subsus.u.w" => "__builtin_msa_subsus_u_w", + "llvm.mips.subsuu.s.b" => "__builtin_msa_subsuu_s_b", + "llvm.mips.subsuu.s.d" => "__builtin_msa_subsuu_s_d", + "llvm.mips.subsuu.s.h" => "__builtin_msa_subsuu_s_h", + "llvm.mips.subsuu.s.w" => "__builtin_msa_subsuu_s_w", + "llvm.mips.subu.ph" => "__builtin_mips_subu_ph", + "llvm.mips.subu.qb" => "__builtin_mips_subu_qb", + "llvm.mips.subu.s.ph" => "__builtin_mips_subu_s_ph", + "llvm.mips.subu.s.qb" => "__builtin_mips_subu_s_qb", + "llvm.mips.subuh.qb" => "__builtin_mips_subuh_qb", + "llvm.mips.subuh.r.qb" => "__builtin_mips_subuh_r_qb", + "llvm.mips.subv.b" => "__builtin_msa_subv_b", + "llvm.mips.subv.d" => "__builtin_msa_subv_d", + "llvm.mips.subv.h" => "__builtin_msa_subv_h", + "llvm.mips.subv.w" => "__builtin_msa_subv_w", + "llvm.mips.subvi.b" => "__builtin_msa_subvi_b", + "llvm.mips.subvi.d" => "__builtin_msa_subvi_d", + "llvm.mips.subvi.h" => "__builtin_msa_subvi_h", + "llvm.mips.subvi.w" => "__builtin_msa_subvi_w", + "llvm.mips.vshf.b" => "__builtin_msa_vshf_b", + "llvm.mips.vshf.d" => "__builtin_msa_vshf_d", + "llvm.mips.vshf.h" => "__builtin_msa_vshf_h", + "llvm.mips.vshf.w" => "__builtin_msa_vshf_w", + "llvm.mips.wrdsp" => "__builtin_mips_wrdsp", + "llvm.mips.xor.v" => "__builtin_msa_xor_v", + "llvm.mips.xori.b" => "__builtin_msa_xori_b", // nvvm "llvm.nvvm.abs.i" => "__nvvm_abs_i", "llvm.nvvm.abs.ll" => "__nvvm_abs_ll", @@ -1519,25 +2034,161 @@ match name { "llvm.nvvm.ull2f.rn" => "__nvvm_ull2f_rn", "llvm.nvvm.ull2f.rp" => "__nvvm_ull2f_rp", "llvm.nvvm.ull2f.rz" => "__nvvm_ull2f_rz", - // arm - "llvm.arm.cdp" => "__builtin_arm_cdp", - "llvm.arm.cdp2" => "__builtin_arm_cdp2", - "llvm.arm.dmb" => "__builtin_arm_dmb", - "llvm.arm.dsb" => "__builtin_arm_dsb", - "llvm.arm.get.fpscr" => "__builtin_arm_get_fpscr", - "llvm.arm.isb" => "__builtin_arm_isb", - "llvm.arm.mcr" => "__builtin_arm_mcr", - "llvm.arm.mcr2" => "__builtin_arm_mcr2", - "llvm.arm.mcrr" => "__builtin_arm_mcrr", - "llvm.arm.mcrr2" => "__builtin_arm_mcrr2", - "llvm.arm.mrc" => "__builtin_arm_mrc", - "llvm.arm.mrc2" => "__builtin_arm_mrc2", - "llvm.arm.qadd" => "__builtin_arm_qadd", - "llvm.arm.qsub" => "__builtin_arm_qsub", - "llvm.arm.set.fpscr" => "__builtin_arm_set_fpscr", - "llvm.arm.ssat" => "__builtin_arm_ssat", - "llvm.arm.thread.pointer" => "__builtin_thread_pointer", - "llvm.arm.usat" => "__builtin_arm_usat", + // ppc + "llvm.ppc.altivec.dss" => "__builtin_altivec_dss", + "llvm.ppc.altivec.dssall" => "__builtin_altivec_dssall", + "llvm.ppc.altivec.dst" => "__builtin_altivec_dst", + "llvm.ppc.altivec.dstst" => "__builtin_altivec_dstst", + "llvm.ppc.altivec.dststt" => "__builtin_altivec_dststt", + "llvm.ppc.altivec.dstt" => "__builtin_altivec_dstt", + "llvm.ppc.altivec.mfvscr" => "__builtin_altivec_mfvscr", + "llvm.ppc.altivec.mtvscr" => "__builtin_altivec_mtvscr", + "llvm.ppc.altivec.vaddcuw" => "__builtin_altivec_vaddcuw", + "llvm.ppc.altivec.vaddsbs" => "__builtin_altivec_vaddsbs", + "llvm.ppc.altivec.vaddshs" => "__builtin_altivec_vaddshs", + "llvm.ppc.altivec.vaddsws" => "__builtin_altivec_vaddsws", + "llvm.ppc.altivec.vaddubs" => "__builtin_altivec_vaddubs", + "llvm.ppc.altivec.vadduhs" => "__builtin_altivec_vadduhs", + "llvm.ppc.altivec.vadduws" => "__builtin_altivec_vadduws", + "llvm.ppc.altivec.vavgsb" => "__builtin_altivec_vavgsb", + "llvm.ppc.altivec.vavgsh" => "__builtin_altivec_vavgsh", + "llvm.ppc.altivec.vavgsw" => "__builtin_altivec_vavgsw", + "llvm.ppc.altivec.vavgub" => "__builtin_altivec_vavgub", + "llvm.ppc.altivec.vavguh" => "__builtin_altivec_vavguh", + "llvm.ppc.altivec.vavguw" => "__builtin_altivec_vavguw", + "llvm.ppc.altivec.vcfsx" => "__builtin_altivec_vcfsx", + "llvm.ppc.altivec.vcfux" => "__builtin_altivec_vcfux", + "llvm.ppc.altivec.vcmpbfp" => "__builtin_altivec_vcmpbfp", + "llvm.ppc.altivec.vcmpbfp.p" => "__builtin_altivec_vcmpbfp_p", + "llvm.ppc.altivec.vcmpeqfp" => "__builtin_altivec_vcmpeqfp", + "llvm.ppc.altivec.vcmpeqfp.p" => "__builtin_altivec_vcmpeqfp_p", + "llvm.ppc.altivec.vcmpequb" => "__builtin_altivec_vcmpequb", + "llvm.ppc.altivec.vcmpequb.p" => "__builtin_altivec_vcmpequb_p", + "llvm.ppc.altivec.vcmpequh" => "__builtin_altivec_vcmpequh", + "llvm.ppc.altivec.vcmpequh.p" => "__builtin_altivec_vcmpequh_p", + "llvm.ppc.altivec.vcmpequw" => "__builtin_altivec_vcmpequw", + "llvm.ppc.altivec.vcmpequw.p" => "__builtin_altivec_vcmpequw_p", + "llvm.ppc.altivec.vcmpgefp" => "__builtin_altivec_vcmpgefp", + "llvm.ppc.altivec.vcmpgefp.p" => "__builtin_altivec_vcmpgefp_p", + "llvm.ppc.altivec.vcmpgtfp" => "__builtin_altivec_vcmpgtfp", + "llvm.ppc.altivec.vcmpgtfp.p" => "__builtin_altivec_vcmpgtfp_p", + "llvm.ppc.altivec.vcmpgtsb" => "__builtin_altivec_vcmpgtsb", + "llvm.ppc.altivec.vcmpgtsb.p" => "__builtin_altivec_vcmpgtsb_p", + "llvm.ppc.altivec.vcmpgtsh" => "__builtin_altivec_vcmpgtsh", + "llvm.ppc.altivec.vcmpgtsh.p" => "__builtin_altivec_vcmpgtsh_p", + "llvm.ppc.altivec.vcmpgtsw" => "__builtin_altivec_vcmpgtsw", + "llvm.ppc.altivec.vcmpgtsw.p" => "__builtin_altivec_vcmpgtsw_p", + "llvm.ppc.altivec.vcmpgtub" => "__builtin_altivec_vcmpgtub", + "llvm.ppc.altivec.vcmpgtub.p" => "__builtin_altivec_vcmpgtub_p", + "llvm.ppc.altivec.vcmpgtuh" => "__builtin_altivec_vcmpgtuh", + "llvm.ppc.altivec.vcmpgtuh.p" => "__builtin_altivec_vcmpgtuh_p", + "llvm.ppc.altivec.vcmpgtuw" => "__builtin_altivec_vcmpgtuw", + "llvm.ppc.altivec.vcmpgtuw.p" => "__builtin_altivec_vcmpgtuw_p", + "llvm.ppc.altivec.vctsxs" => "__builtin_altivec_vctsxs", + "llvm.ppc.altivec.vctuxs" => "__builtin_altivec_vctuxs", + "llvm.ppc.altivec.vexptefp" => "__builtin_altivec_vexptefp", + "llvm.ppc.altivec.vlogefp" => "__builtin_altivec_vlogefp", + "llvm.ppc.altivec.vmaddfp" => "__builtin_altivec_vmaddfp", + "llvm.ppc.altivec.vmaxfp" => "__builtin_altivec_vmaxfp", + "llvm.ppc.altivec.vmaxsb" => "__builtin_altivec_vmaxsb", + "llvm.ppc.altivec.vmaxsh" => "__builtin_altivec_vmaxsh", + "llvm.ppc.altivec.vmaxsw" => "__builtin_altivec_vmaxsw", + "llvm.ppc.altivec.vmaxub" => "__builtin_altivec_vmaxub", + "llvm.ppc.altivec.vmaxuh" => "__builtin_altivec_vmaxuh", + "llvm.ppc.altivec.vmaxuw" => "__builtin_altivec_vmaxuw", + "llvm.ppc.altivec.vmhaddshs" => "__builtin_altivec_vmhaddshs", + "llvm.ppc.altivec.vmhraddshs" => "__builtin_altivec_vmhraddshs", + "llvm.ppc.altivec.vminfp" => "__builtin_altivec_vminfp", + "llvm.ppc.altivec.vminsb" => "__builtin_altivec_vminsb", + "llvm.ppc.altivec.vminsh" => "__builtin_altivec_vminsh", + "llvm.ppc.altivec.vminsw" => "__builtin_altivec_vminsw", + "llvm.ppc.altivec.vminub" => "__builtin_altivec_vminub", + "llvm.ppc.altivec.vminuh" => "__builtin_altivec_vminuh", + "llvm.ppc.altivec.vminuw" => "__builtin_altivec_vminuw", + "llvm.ppc.altivec.vmladduhm" => "__builtin_altivec_vmladduhm", + "llvm.ppc.altivec.vmsummbm" => "__builtin_altivec_vmsummbm", + "llvm.ppc.altivec.vmsumshm" => "__builtin_altivec_vmsumshm", + "llvm.ppc.altivec.vmsumshs" => "__builtin_altivec_vmsumshs", + "llvm.ppc.altivec.vmsumubm" => "__builtin_altivec_vmsumubm", + "llvm.ppc.altivec.vmsumuhm" => "__builtin_altivec_vmsumuhm", + "llvm.ppc.altivec.vmsumuhs" => "__builtin_altivec_vmsumuhs", + "llvm.ppc.altivec.vmulesb" => "__builtin_altivec_vmulesb", + "llvm.ppc.altivec.vmulesh" => "__builtin_altivec_vmulesh", + "llvm.ppc.altivec.vmuleub" => "__builtin_altivec_vmuleub", + "llvm.ppc.altivec.vmuleuh" => "__builtin_altivec_vmuleuh", + "llvm.ppc.altivec.vmulosb" => "__builtin_altivec_vmulosb", + "llvm.ppc.altivec.vmulosh" => "__builtin_altivec_vmulosh", + "llvm.ppc.altivec.vmuloub" => "__builtin_altivec_vmuloub", + "llvm.ppc.altivec.vmulouh" => "__builtin_altivec_vmulouh", + "llvm.ppc.altivec.vnmsubfp" => "__builtin_altivec_vnmsubfp", + "llvm.ppc.altivec.vperm" => "__builtin_altivec_vperm_4si", + "llvm.ppc.altivec.vpkpx" => "__builtin_altivec_vpkpx", + "llvm.ppc.altivec.vpkshss" => "__builtin_altivec_vpkshss", + "llvm.ppc.altivec.vpkshus" => "__builtin_altivec_vpkshus", + "llvm.ppc.altivec.vpkswss" => "__builtin_altivec_vpkswss", + "llvm.ppc.altivec.vpkswus" => "__builtin_altivec_vpkswus", + "llvm.ppc.altivec.vpkuhus" => "__builtin_altivec_vpkuhus", + "llvm.ppc.altivec.vpkuwus" => "__builtin_altivec_vpkuwus", + "llvm.ppc.altivec.vrefp" => "__builtin_altivec_vrefp", + "llvm.ppc.altivec.vrfim" => "__builtin_altivec_vrfim", + "llvm.ppc.altivec.vrfin" => "__builtin_altivec_vrfin", + "llvm.ppc.altivec.vrfip" => "__builtin_altivec_vrfip", + "llvm.ppc.altivec.vrfiz" => "__builtin_altivec_vrfiz", + "llvm.ppc.altivec.vrlb" => "__builtin_altivec_vrlb", + "llvm.ppc.altivec.vrlh" => "__builtin_altivec_vrlh", + "llvm.ppc.altivec.vrlw" => "__builtin_altivec_vrlw", + "llvm.ppc.altivec.vrsqrtefp" => "__builtin_altivec_vrsqrtefp", + "llvm.ppc.altivec.vsel" => "__builtin_altivec_vsel_4si", + "llvm.ppc.altivec.vsl" => "__builtin_altivec_vsl", + "llvm.ppc.altivec.vslb" => "__builtin_altivec_vslb", + "llvm.ppc.altivec.vslh" => "__builtin_altivec_vslh", + "llvm.ppc.altivec.vslo" => "__builtin_altivec_vslo", + "llvm.ppc.altivec.vslw" => "__builtin_altivec_vslw", + "llvm.ppc.altivec.vsr" => "__builtin_altivec_vsr", + "llvm.ppc.altivec.vsrab" => "__builtin_altivec_vsrab", + "llvm.ppc.altivec.vsrah" => "__builtin_altivec_vsrah", + "llvm.ppc.altivec.vsraw" => "__builtin_altivec_vsraw", + "llvm.ppc.altivec.vsrb" => "__builtin_altivec_vsrb", + "llvm.ppc.altivec.vsrh" => "__builtin_altivec_vsrh", + "llvm.ppc.altivec.vsro" => "__builtin_altivec_vsro", + "llvm.ppc.altivec.vsrw" => "__builtin_altivec_vsrw", + "llvm.ppc.altivec.vsubcuw" => "__builtin_altivec_vsubcuw", + "llvm.ppc.altivec.vsubsbs" => "__builtin_altivec_vsubsbs", + "llvm.ppc.altivec.vsubshs" => "__builtin_altivec_vsubshs", + "llvm.ppc.altivec.vsubsws" => "__builtin_altivec_vsubsws", + "llvm.ppc.altivec.vsububs" => "__builtin_altivec_vsububs", + "llvm.ppc.altivec.vsubuhs" => "__builtin_altivec_vsubuhs", + "llvm.ppc.altivec.vsubuws" => "__builtin_altivec_vsubuws", + "llvm.ppc.altivec.vsum2sws" => "__builtin_altivec_vsum2sws", + "llvm.ppc.altivec.vsum4sbs" => "__builtin_altivec_vsum4sbs", + "llvm.ppc.altivec.vsum4shs" => "__builtin_altivec_vsum4shs", + "llvm.ppc.altivec.vsum4ubs" => "__builtin_altivec_vsum4ubs", + "llvm.ppc.altivec.vsumsws" => "__builtin_altivec_vsumsws", + "llvm.ppc.altivec.vupkhpx" => "__builtin_altivec_vupkhpx", + "llvm.ppc.altivec.vupkhsb" => "__builtin_altivec_vupkhsb", + "llvm.ppc.altivec.vupkhsh" => "__builtin_altivec_vupkhsh", + "llvm.ppc.altivec.vupklpx" => "__builtin_altivec_vupklpx", + "llvm.ppc.altivec.vupklsb" => "__builtin_altivec_vupklsb", + "llvm.ppc.altivec.vupklsh" => "__builtin_altivec_vupklsh", + // ptx + "llvm.ptx.bar.sync" => "__builtin_ptx_bar_sync", + "llvm.ptx.read.clock" => "__builtin_ptx_read_clock", + "llvm.ptx.read.clock64" => "__builtin_ptx_read_clock64", + "llvm.ptx.read.gridid" => "__builtin_ptx_read_gridid", + "llvm.ptx.read.laneid" => "__builtin_ptx_read_laneid", + "llvm.ptx.read.lanemask.eq" => "__builtin_ptx_read_lanemask_eq", + "llvm.ptx.read.lanemask.ge" => "__builtin_ptx_read_lanemask_ge", + "llvm.ptx.read.lanemask.gt" => "__builtin_ptx_read_lanemask_gt", + "llvm.ptx.read.lanemask.le" => "__builtin_ptx_read_lanemask_le", + "llvm.ptx.read.lanemask.lt" => "__builtin_ptx_read_lanemask_lt", + "llvm.ptx.read.nsmid" => "__builtin_ptx_read_nsmid", + "llvm.ptx.read.nwarpid" => "__builtin_ptx_read_nwarpid", + "llvm.ptx.read.pm0" => "__builtin_ptx_read_pm0", + "llvm.ptx.read.pm1" => "__builtin_ptx_read_pm1", + "llvm.ptx.read.pm2" => "__builtin_ptx_read_pm2", + "llvm.ptx.read.pm3" => "__builtin_ptx_read_pm3", + "llvm.ptx.read.smid" => "__builtin_ptx_read_smid", + "llvm.ptx.read.warpid" => "__builtin_ptx_read_warpid", // x86 "llvm.x86.addcarry.u32" => "__builtin_ia32_addcarry_u32", "llvm.x86.addcarry.u64" => "__builtin_ia32_addcarry_u64", @@ -2305,661 +2956,10 @@ match name { "llvm.x86.xop.vpshlq" => "__builtin_ia32_vpshlq", "llvm.x86.xop.vpshlw" => "__builtin_ia32_vpshlw", "llvm.x86.xtest" => "__builtin_ia32_xtest", - // AMDGPU - "llvm.AMDGPU.div.fixup.f32" => "__builtin_amdgpu_div_fixup", - "llvm.AMDGPU.div.fixup.f64" => "__builtin_amdgpu_div_fixup", - "llvm.AMDGPU.div.fixup.v2f64" => "__builtin_amdgpu_div_fixup", - "llvm.AMDGPU.div.fixup.v4f32" => "__builtin_amdgpu_div_fixup", - "llvm.AMDGPU.div.fmas.f32" => "__builtin_amdgpu_div_fmas", - "llvm.AMDGPU.div.fmas.f64" => "__builtin_amdgpu_div_fmas", - "llvm.AMDGPU.div.fmas.v2f64" => "__builtin_amdgpu_div_fmas", - "llvm.AMDGPU.div.fmas.v4f32" => "__builtin_amdgpu_div_fmas", - "llvm.AMDGPU.ldexp.f32" => "__builtin_amdgpu_ldexp", - "llvm.AMDGPU.ldexp.f64" => "__builtin_amdgpu_ldexp", - "llvm.AMDGPU.ldexp.v2f64" => "__builtin_amdgpu_ldexp", - "llvm.AMDGPU.ldexp.v4f32" => "__builtin_amdgpu_ldexp", - "llvm.AMDGPU.rcp.f32" => "__builtin_amdgpu_rcp", - "llvm.AMDGPU.rcp.f64" => "__builtin_amdgpu_rcp", - "llvm.AMDGPU.rcp.v2f64" => "__builtin_amdgpu_rcp", - "llvm.AMDGPU.rcp.v4f32" => "__builtin_amdgpu_rcp", - "llvm.AMDGPU.rsq.clamped.f32" => "__builtin_amdgpu_rsq_clamped", - "llvm.AMDGPU.rsq.clamped.f64" => "__builtin_amdgpu_rsq_clamped", - "llvm.AMDGPU.rsq.clamped.v2f64" => "__builtin_amdgpu_rsq_clamped", - "llvm.AMDGPU.rsq.clamped.v4f32" => "__builtin_amdgpu_rsq_clamped", - "llvm.AMDGPU.rsq.f32" => "__builtin_amdgpu_rsq", - "llvm.AMDGPU.rsq.f64" => "__builtin_amdgpu_rsq", - "llvm.AMDGPU.rsq.v2f64" => "__builtin_amdgpu_rsq", - "llvm.AMDGPU.rsq.v4f32" => "__builtin_amdgpu_rsq", - "llvm.AMDGPU.trig.preop.f32" => "__builtin_amdgpu_trig_preop", - "llvm.AMDGPU.trig.preop.f64" => "__builtin_amdgpu_trig_preop", - "llvm.AMDGPU.trig.preop.v2f64" => "__builtin_amdgpu_trig_preop", - "llvm.AMDGPU.trig.preop.v4f32" => "__builtin_amdgpu_trig_preop", - // mips - "llvm.mips.add.a.b" => "__builtin_msa_add_a_b", - "llvm.mips.add.a.d" => "__builtin_msa_add_a_d", - "llvm.mips.add.a.h" => "__builtin_msa_add_a_h", - "llvm.mips.add.a.w" => "__builtin_msa_add_a_w", - "llvm.mips.adds.a.b" => "__builtin_msa_adds_a_b", - "llvm.mips.adds.a.d" => "__builtin_msa_adds_a_d", - "llvm.mips.adds.a.h" => "__builtin_msa_adds_a_h", - "llvm.mips.adds.a.w" => "__builtin_msa_adds_a_w", - "llvm.mips.adds.s.b" => "__builtin_msa_adds_s_b", - "llvm.mips.adds.s.d" => "__builtin_msa_adds_s_d", - "llvm.mips.adds.s.h" => "__builtin_msa_adds_s_h", - "llvm.mips.adds.s.w" => "__builtin_msa_adds_s_w", - "llvm.mips.adds.u.b" => "__builtin_msa_adds_u_b", - "llvm.mips.adds.u.d" => "__builtin_msa_adds_u_d", - "llvm.mips.adds.u.h" => "__builtin_msa_adds_u_h", - "llvm.mips.adds.u.w" => "__builtin_msa_adds_u_w", - "llvm.mips.addsc" => "__builtin_mips_addsc", - "llvm.mips.addu.ph" => "__builtin_mips_addu_ph", - "llvm.mips.addu.qb" => "__builtin_mips_addu_qb", - "llvm.mips.addu.s.ph" => "__builtin_mips_addu_s_ph", - "llvm.mips.addu.s.qb" => "__builtin_mips_addu_s_qb", - "llvm.mips.adduh.qb" => "__builtin_mips_adduh_qb", - "llvm.mips.adduh.r.qb" => "__builtin_mips_adduh_r_qb", - "llvm.mips.addv.b" => "__builtin_msa_addv_b", - "llvm.mips.addv.d" => "__builtin_msa_addv_d", - "llvm.mips.addv.h" => "__builtin_msa_addv_h", - "llvm.mips.addv.w" => "__builtin_msa_addv_w", - "llvm.mips.addvi.b" => "__builtin_msa_addvi_b", - "llvm.mips.addvi.d" => "__builtin_msa_addvi_d", - "llvm.mips.addvi.h" => "__builtin_msa_addvi_h", - "llvm.mips.addvi.w" => "__builtin_msa_addvi_w", - "llvm.mips.addwc" => "__builtin_mips_addwc", - "llvm.mips.and.v" => "__builtin_msa_and_v", - "llvm.mips.andi.b" => "__builtin_msa_andi_b", - "llvm.mips.append" => "__builtin_mips_append", - "llvm.mips.asub.s.b" => "__builtin_msa_asub_s_b", - "llvm.mips.asub.s.d" => "__builtin_msa_asub_s_d", - "llvm.mips.asub.s.h" => "__builtin_msa_asub_s_h", - "llvm.mips.asub.s.w" => "__builtin_msa_asub_s_w", - "llvm.mips.asub.u.b" => "__builtin_msa_asub_u_b", - "llvm.mips.asub.u.d" => "__builtin_msa_asub_u_d", - "llvm.mips.asub.u.h" => "__builtin_msa_asub_u_h", - "llvm.mips.asub.u.w" => "__builtin_msa_asub_u_w", - "llvm.mips.ave.s.b" => "__builtin_msa_ave_s_b", - "llvm.mips.ave.s.d" => "__builtin_msa_ave_s_d", - "llvm.mips.ave.s.h" => "__builtin_msa_ave_s_h", - "llvm.mips.ave.s.w" => "__builtin_msa_ave_s_w", - "llvm.mips.ave.u.b" => "__builtin_msa_ave_u_b", - "llvm.mips.ave.u.d" => "__builtin_msa_ave_u_d", - "llvm.mips.ave.u.h" => "__builtin_msa_ave_u_h", - "llvm.mips.ave.u.w" => "__builtin_msa_ave_u_w", - "llvm.mips.aver.s.b" => "__builtin_msa_aver_s_b", - "llvm.mips.aver.s.d" => "__builtin_msa_aver_s_d", - "llvm.mips.aver.s.h" => "__builtin_msa_aver_s_h", - "llvm.mips.aver.s.w" => "__builtin_msa_aver_s_w", - "llvm.mips.aver.u.b" => "__builtin_msa_aver_u_b", - "llvm.mips.aver.u.d" => "__builtin_msa_aver_u_d", - "llvm.mips.aver.u.h" => "__builtin_msa_aver_u_h", - "llvm.mips.aver.u.w" => "__builtin_msa_aver_u_w", - "llvm.mips.balign" => "__builtin_mips_balign", - "llvm.mips.bclr.b" => "__builtin_msa_bclr_b", - "llvm.mips.bclr.d" => "__builtin_msa_bclr_d", - "llvm.mips.bclr.h" => "__builtin_msa_bclr_h", - "llvm.mips.bclr.w" => "__builtin_msa_bclr_w", - "llvm.mips.bclri.b" => "__builtin_msa_bclri_b", - "llvm.mips.bclri.d" => "__builtin_msa_bclri_d", - "llvm.mips.bclri.h" => "__builtin_msa_bclri_h", - "llvm.mips.bclri.w" => "__builtin_msa_bclri_w", - "llvm.mips.binsl.b" => "__builtin_msa_binsl_b", - "llvm.mips.binsl.d" => "__builtin_msa_binsl_d", - "llvm.mips.binsl.h" => "__builtin_msa_binsl_h", - "llvm.mips.binsl.w" => "__builtin_msa_binsl_w", - "llvm.mips.binsli.b" => "__builtin_msa_binsli_b", - "llvm.mips.binsli.d" => "__builtin_msa_binsli_d", - "llvm.mips.binsli.h" => "__builtin_msa_binsli_h", - "llvm.mips.binsli.w" => "__builtin_msa_binsli_w", - "llvm.mips.binsr.b" => "__builtin_msa_binsr_b", - "llvm.mips.binsr.d" => "__builtin_msa_binsr_d", - "llvm.mips.binsr.h" => "__builtin_msa_binsr_h", - "llvm.mips.binsr.w" => "__builtin_msa_binsr_w", - "llvm.mips.binsri.b" => "__builtin_msa_binsri_b", - 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"__builtin_msa_bnz_w", - "llvm.mips.bposge32" => "__builtin_mips_bposge32", - "llvm.mips.bsel.v" => "__builtin_msa_bsel_v", - "llvm.mips.bseli.b" => "__builtin_msa_bseli_b", - "llvm.mips.bset.b" => "__builtin_msa_bset_b", - "llvm.mips.bset.d" => "__builtin_msa_bset_d", - "llvm.mips.bset.h" => "__builtin_msa_bset_h", - "llvm.mips.bset.w" => "__builtin_msa_bset_w", - "llvm.mips.bseti.b" => "__builtin_msa_bseti_b", - "llvm.mips.bseti.d" => "__builtin_msa_bseti_d", - "llvm.mips.bseti.h" => "__builtin_msa_bseti_h", - "llvm.mips.bseti.w" => "__builtin_msa_bseti_w", - "llvm.mips.bz.b" => "__builtin_msa_bz_b", - "llvm.mips.bz.d" => "__builtin_msa_bz_d", - "llvm.mips.bz.h" => "__builtin_msa_bz_h", - "llvm.mips.bz.v" => "__builtin_msa_bz_v", - "llvm.mips.bz.w" => "__builtin_msa_bz_w", - "llvm.mips.ceq.b" => "__builtin_msa_ceq_b", - "llvm.mips.ceq.d" => "__builtin_msa_ceq_d", - "llvm.mips.ceq.h" => "__builtin_msa_ceq_h", - "llvm.mips.ceq.w" => "__builtin_msa_ceq_w", - "llvm.mips.ceqi.b" => "__builtin_msa_ceqi_b", - "llvm.mips.ceqi.d" => "__builtin_msa_ceqi_d", - "llvm.mips.ceqi.h" => "__builtin_msa_ceqi_h", - "llvm.mips.ceqi.w" => "__builtin_msa_ceqi_w", - "llvm.mips.cfcmsa" => "__builtin_msa_cfcmsa", - "llvm.mips.cle.s.b" => "__builtin_msa_cle_s_b", - "llvm.mips.cle.s.d" => "__builtin_msa_cle_s_d", - "llvm.mips.cle.s.h" => "__builtin_msa_cle_s_h", - "llvm.mips.cle.s.w" => "__builtin_msa_cle_s_w", - "llvm.mips.cle.u.b" => "__builtin_msa_cle_u_b", - "llvm.mips.cle.u.d" => "__builtin_msa_cle_u_d", - "llvm.mips.cle.u.h" => "__builtin_msa_cle_u_h", - "llvm.mips.cle.u.w" => "__builtin_msa_cle_u_w", - "llvm.mips.clei.s.b" => "__builtin_msa_clei_s_b", - "llvm.mips.clei.s.d" => "__builtin_msa_clei_s_d", - "llvm.mips.clei.s.h" => "__builtin_msa_clei_s_h", - "llvm.mips.clei.s.w" => "__builtin_msa_clei_s_w", - "llvm.mips.clei.u.b" => "__builtin_msa_clei_u_b", - "llvm.mips.clei.u.d" => "__builtin_msa_clei_u_d", - "llvm.mips.clei.u.h" => "__builtin_msa_clei_u_h", - "llvm.mips.clei.u.w" => "__builtin_msa_clei_u_w", - "llvm.mips.clt.s.b" => "__builtin_msa_clt_s_b", - "llvm.mips.clt.s.d" => "__builtin_msa_clt_s_d", - "llvm.mips.clt.s.h" => "__builtin_msa_clt_s_h", - "llvm.mips.clt.s.w" => "__builtin_msa_clt_s_w", - "llvm.mips.clt.u.b" => "__builtin_msa_clt_u_b", - "llvm.mips.clt.u.d" => "__builtin_msa_clt_u_d", - "llvm.mips.clt.u.h" => "__builtin_msa_clt_u_h", - "llvm.mips.clt.u.w" => "__builtin_msa_clt_u_w", - "llvm.mips.clti.s.b" => "__builtin_msa_clti_s_b", - "llvm.mips.clti.s.d" => "__builtin_msa_clti_s_d", - "llvm.mips.clti.s.h" => "__builtin_msa_clti_s_h", - "llvm.mips.clti.s.w" => "__builtin_msa_clti_s_w", - "llvm.mips.clti.u.b" => "__builtin_msa_clti_u_b", - "llvm.mips.clti.u.d" => "__builtin_msa_clti_u_d", - "llvm.mips.clti.u.h" => "__builtin_msa_clti_u_h", - "llvm.mips.clti.u.w" => "__builtin_msa_clti_u_w", - "llvm.mips.cmpgdu.eq.qb" => "__builtin_mips_cmpgdu_eq_qb", - "llvm.mips.cmpgdu.le.qb" => "__builtin_mips_cmpgdu_le_qb", - "llvm.mips.cmpgdu.lt.qb" => "__builtin_mips_cmpgdu_lt_qb", - "llvm.mips.cmpgu.eq.qb" => "__builtin_mips_cmpgu_eq_qb", - "llvm.mips.cmpgu.le.qb" => "__builtin_mips_cmpgu_le_qb", - "llvm.mips.cmpgu.lt.qb" => "__builtin_mips_cmpgu_lt_qb", - "llvm.mips.cmpu.eq.qb" => "__builtin_mips_cmpu_eq_qb", - "llvm.mips.cmpu.le.qb" => "__builtin_mips_cmpu_le_qb", - "llvm.mips.cmpu.lt.qb" => "__builtin_mips_cmpu_lt_qb", - "llvm.mips.copy.s.b" => "__builtin_msa_copy_s_b", - "llvm.mips.copy.s.d" => "__builtin_msa_copy_s_d", - "llvm.mips.copy.s.h" => "__builtin_msa_copy_s_h", - "llvm.mips.copy.s.w" => "__builtin_msa_copy_s_w", - "llvm.mips.copy.u.b" => "__builtin_msa_copy_u_b", - "llvm.mips.copy.u.d" => "__builtin_msa_copy_u_d", - "llvm.mips.copy.u.h" => "__builtin_msa_copy_u_h", - "llvm.mips.copy.u.w" => "__builtin_msa_copy_u_w", - "llvm.mips.ctcmsa" => "__builtin_msa_ctcmsa", - "llvm.mips.div.s.b" => "__builtin_msa_div_s_b", - "llvm.mips.div.s.d" => "__builtin_msa_div_s_d", - "llvm.mips.div.s.h" => "__builtin_msa_div_s_h", - "llvm.mips.div.s.w" => "__builtin_msa_div_s_w", - "llvm.mips.div.u.b" => "__builtin_msa_div_u_b", - "llvm.mips.div.u.d" => "__builtin_msa_div_u_d", - "llvm.mips.div.u.h" => "__builtin_msa_div_u_h", - "llvm.mips.div.u.w" => "__builtin_msa_div_u_w", - "llvm.mips.dlsa" => "__builtin_mips_dlsa", - "llvm.mips.dotp.s.d" => "__builtin_msa_dotp_s_d", - "llvm.mips.dotp.s.h" => "__builtin_msa_dotp_s_h", - "llvm.mips.dotp.s.w" => "__builtin_msa_dotp_s_w", - "llvm.mips.dotp.u.d" => "__builtin_msa_dotp_u_d", - "llvm.mips.dotp.u.h" => "__builtin_msa_dotp_u_h", - "llvm.mips.dotp.u.w" => "__builtin_msa_dotp_u_w", - "llvm.mips.dpa.w.ph" => "__builtin_mips_dpa_w_ph", - "llvm.mips.dpadd.s.d" => "__builtin_msa_dpadd_s_d", - "llvm.mips.dpadd.s.h" => "__builtin_msa_dpadd_s_h", - "llvm.mips.dpadd.s.w" => "__builtin_msa_dpadd_s_w", - "llvm.mips.dpadd.u.d" => "__builtin_msa_dpadd_u_d", - "llvm.mips.dpadd.u.h" => "__builtin_msa_dpadd_u_h", - "llvm.mips.dpadd.u.w" => "__builtin_msa_dpadd_u_w", - "llvm.mips.dpau.h.qbl" => "__builtin_mips_dpau_h_qbl", - "llvm.mips.dpau.h.qbr" => "__builtin_mips_dpau_h_qbr", - "llvm.mips.dpax.w.ph" => "__builtin_mips_dpax_w_ph", - "llvm.mips.dps.w.ph" => "__builtin_mips_dps_w_ph", - "llvm.mips.dpsu.h.qbl" => "__builtin_mips_dpsu_h_qbl", - "llvm.mips.dpsu.h.qbr" => "__builtin_mips_dpsu_h_qbr", - "llvm.mips.dpsub.s.d" => "__builtin_msa_dpsub_s_d", - "llvm.mips.dpsub.s.h" => "__builtin_msa_dpsub_s_h", - "llvm.mips.dpsub.s.w" => "__builtin_msa_dpsub_s_w", - "llvm.mips.dpsub.u.d" => "__builtin_msa_dpsub_u_d", - "llvm.mips.dpsub.u.h" => "__builtin_msa_dpsub_u_h", - "llvm.mips.dpsub.u.w" => "__builtin_msa_dpsub_u_w", - "llvm.mips.dpsx.w.ph" => "__builtin_mips_dpsx_w_ph", - "llvm.mips.extp" => "__builtin_mips_extp", - "llvm.mips.extpdp" => "__builtin_mips_extpdp", - "llvm.mips.extr.r.w" => "__builtin_mips_extr_r_w", - "llvm.mips.extr.rs.w" => "__builtin_mips_extr_rs_w", - "llvm.mips.extr.s.h" => "__builtin_mips_extr_s_h", - "llvm.mips.extr.w" => "__builtin_mips_extr_w", - "llvm.mips.fadd.d" => "__builtin_msa_fadd_d", - "llvm.mips.fadd.w" => "__builtin_msa_fadd_w", - "llvm.mips.fcaf.d" => "__builtin_msa_fcaf_d", - "llvm.mips.fcaf.w" => "__builtin_msa_fcaf_w", - "llvm.mips.fceq.d" => "__builtin_msa_fceq_d", - "llvm.mips.fceq.w" => "__builtin_msa_fceq_w", - "llvm.mips.fclass.d" => "__builtin_msa_fclass_d", - "llvm.mips.fclass.w" => "__builtin_msa_fclass_w", - "llvm.mips.fcle.d" => "__builtin_msa_fcle_d", - "llvm.mips.fcle.w" => "__builtin_msa_fcle_w", - "llvm.mips.fclt.d" => "__builtin_msa_fclt_d", - "llvm.mips.fclt.w" => "__builtin_msa_fclt_w", - "llvm.mips.fcne.d" => "__builtin_msa_fcne_d", - "llvm.mips.fcne.w" => "__builtin_msa_fcne_w", - "llvm.mips.fcor.d" => "__builtin_msa_fcor_d", - "llvm.mips.fcor.w" => "__builtin_msa_fcor_w", - "llvm.mips.fcueq.d" => "__builtin_msa_fcueq_d", - "llvm.mips.fcueq.w" => "__builtin_msa_fcueq_w", - "llvm.mips.fcule.d" => "__builtin_msa_fcule_d", - "llvm.mips.fcule.w" => "__builtin_msa_fcule_w", - "llvm.mips.fcult.d" => "__builtin_msa_fcult_d", - "llvm.mips.fcult.w" => "__builtin_msa_fcult_w", - "llvm.mips.fcun.d" => "__builtin_msa_fcun_d", - "llvm.mips.fcun.w" => "__builtin_msa_fcun_w", - "llvm.mips.fcune.d" => "__builtin_msa_fcune_d", - "llvm.mips.fcune.w" => "__builtin_msa_fcune_w", - "llvm.mips.fdiv.d" => "__builtin_msa_fdiv_d", - "llvm.mips.fdiv.w" => "__builtin_msa_fdiv_w", - "llvm.mips.fexdo.w" => "__builtin_msa_fexdo_w", - "llvm.mips.fexp2.d" => "__builtin_msa_fexp2_d", - "llvm.mips.fexp2.w" => "__builtin_msa_fexp2_w", - "llvm.mips.fexupl.d" => "__builtin_msa_fexupl_d", - "llvm.mips.fexupr.d" => "__builtin_msa_fexupr_d", - "llvm.mips.ffint.s.d" => "__builtin_msa_ffint_s_d", - "llvm.mips.ffint.s.w" => "__builtin_msa_ffint_s_w", - "llvm.mips.ffint.u.d" => "__builtin_msa_ffint_u_d", - "llvm.mips.ffint.u.w" => "__builtin_msa_ffint_u_w", - "llvm.mips.ffql.d" => "__builtin_msa_ffql_d", - "llvm.mips.ffql.w" => "__builtin_msa_ffql_w", - "llvm.mips.ffqr.d" => "__builtin_msa_ffqr_d", - "llvm.mips.ffqr.w" => "__builtin_msa_ffqr_w", - "llvm.mips.fill.b" => "__builtin_msa_fill_b", - "llvm.mips.fill.d" => "__builtin_msa_fill_d", - "llvm.mips.fill.h" => "__builtin_msa_fill_h", - "llvm.mips.fill.w" => "__builtin_msa_fill_w", - "llvm.mips.flog2.d" => "__builtin_msa_flog2_d", - "llvm.mips.flog2.w" => "__builtin_msa_flog2_w", - "llvm.mips.fmadd.d" => "__builtin_msa_fmadd_d", - "llvm.mips.fmadd.w" => "__builtin_msa_fmadd_w", - "llvm.mips.fmax.a.d" => "__builtin_msa_fmax_a_d", - "llvm.mips.fmax.a.w" => "__builtin_msa_fmax_a_w", - "llvm.mips.fmax.d" => "__builtin_msa_fmax_d", - "llvm.mips.fmax.w" => "__builtin_msa_fmax_w", - "llvm.mips.fmin.a.d" => "__builtin_msa_fmin_a_d", - "llvm.mips.fmin.a.w" => "__builtin_msa_fmin_a_w", - "llvm.mips.fmin.d" => "__builtin_msa_fmin_d", - "llvm.mips.fmin.w" => "__builtin_msa_fmin_w", - "llvm.mips.fmsub.d" => "__builtin_msa_fmsub_d", - "llvm.mips.fmsub.w" => "__builtin_msa_fmsub_w", - "llvm.mips.fmul.d" => "__builtin_msa_fmul_d", - "llvm.mips.fmul.w" => "__builtin_msa_fmul_w", - "llvm.mips.frcp.d" => "__builtin_msa_frcp_d", - "llvm.mips.frcp.w" => "__builtin_msa_frcp_w", - "llvm.mips.frint.d" => "__builtin_msa_frint_d", - "llvm.mips.frint.w" => "__builtin_msa_frint_w", - "llvm.mips.frsqrt.d" => "__builtin_msa_frsqrt_d", - "llvm.mips.frsqrt.w" => "__builtin_msa_frsqrt_w", - "llvm.mips.fsaf.d" => "__builtin_msa_fsaf_d", - "llvm.mips.fsaf.w" => "__builtin_msa_fsaf_w", - "llvm.mips.fseq.d" => "__builtin_msa_fseq_d", - "llvm.mips.fseq.w" => "__builtin_msa_fseq_w", - "llvm.mips.fsle.d" => "__builtin_msa_fsle_d", - "llvm.mips.fsle.w" => "__builtin_msa_fsle_w", - "llvm.mips.fslt.d" => "__builtin_msa_fslt_d", - "llvm.mips.fslt.w" => "__builtin_msa_fslt_w", - "llvm.mips.fsne.d" => "__builtin_msa_fsne_d", - "llvm.mips.fsne.w" => "__builtin_msa_fsne_w", - "llvm.mips.fsor.d" => "__builtin_msa_fsor_d", - "llvm.mips.fsor.w" => "__builtin_msa_fsor_w", - "llvm.mips.fsqrt.d" => "__builtin_msa_fsqrt_d", - "llvm.mips.fsqrt.w" => "__builtin_msa_fsqrt_w", - "llvm.mips.fsub.d" => "__builtin_msa_fsub_d", - "llvm.mips.fsub.w" => "__builtin_msa_fsub_w", - "llvm.mips.fsueq.d" => "__builtin_msa_fsueq_d", - "llvm.mips.fsueq.w" => "__builtin_msa_fsueq_w", - "llvm.mips.fsule.d" => "__builtin_msa_fsule_d", - "llvm.mips.fsule.w" => "__builtin_msa_fsule_w", - "llvm.mips.fsult.d" => "__builtin_msa_fsult_d", - "llvm.mips.fsult.w" => "__builtin_msa_fsult_w", - "llvm.mips.fsun.d" => "__builtin_msa_fsun_d", - "llvm.mips.fsun.w" => "__builtin_msa_fsun_w", - "llvm.mips.fsune.d" => "__builtin_msa_fsune_d", - "llvm.mips.fsune.w" => "__builtin_msa_fsune_w", - "llvm.mips.ftint.s.d" => "__builtin_msa_ftint_s_d", - "llvm.mips.ftint.s.w" => "__builtin_msa_ftint_s_w", - "llvm.mips.ftint.u.d" => "__builtin_msa_ftint_u_d", - "llvm.mips.ftint.u.w" => "__builtin_msa_ftint_u_w", - "llvm.mips.ftq.h" => "__builtin_msa_ftq_h", - "llvm.mips.ftq.w" => "__builtin_msa_ftq_w", - "llvm.mips.ftrunc.s.d" => "__builtin_msa_ftrunc_s_d", - "llvm.mips.ftrunc.s.w" => "__builtin_msa_ftrunc_s_w", - "llvm.mips.ftrunc.u.d" => "__builtin_msa_ftrunc_u_d", - "llvm.mips.ftrunc.u.w" => "__builtin_msa_ftrunc_u_w", - "llvm.mips.hadd.s.d" => "__builtin_msa_hadd_s_d", - "llvm.mips.hadd.s.h" => "__builtin_msa_hadd_s_h", - "llvm.mips.hadd.s.w" => "__builtin_msa_hadd_s_w", - "llvm.mips.hadd.u.d" => "__builtin_msa_hadd_u_d", - "llvm.mips.hadd.u.h" => "__builtin_msa_hadd_u_h", - "llvm.mips.hadd.u.w" => "__builtin_msa_hadd_u_w", - "llvm.mips.hsub.s.d" => "__builtin_msa_hsub_s_d", - "llvm.mips.hsub.s.h" => "__builtin_msa_hsub_s_h", - "llvm.mips.hsub.s.w" => "__builtin_msa_hsub_s_w", - "llvm.mips.hsub.u.d" => "__builtin_msa_hsub_u_d", - "llvm.mips.hsub.u.h" => "__builtin_msa_hsub_u_h", - "llvm.mips.hsub.u.w" => "__builtin_msa_hsub_u_w", - "llvm.mips.ilvev.b" => "__builtin_msa_ilvev_b", - "llvm.mips.ilvev.d" => "__builtin_msa_ilvev_d", - "llvm.mips.ilvev.h" => "__builtin_msa_ilvev_h", - "llvm.mips.ilvev.w" => "__builtin_msa_ilvev_w", - "llvm.mips.ilvl.b" => "__builtin_msa_ilvl_b", - "llvm.mips.ilvl.d" => "__builtin_msa_ilvl_d", - "llvm.mips.ilvl.h" => "__builtin_msa_ilvl_h", - "llvm.mips.ilvl.w" => "__builtin_msa_ilvl_w", - "llvm.mips.ilvod.b" => "__builtin_msa_ilvod_b", - "llvm.mips.ilvod.d" => "__builtin_msa_ilvod_d", - "llvm.mips.ilvod.h" => "__builtin_msa_ilvod_h", - "llvm.mips.ilvod.w" => "__builtin_msa_ilvod_w", - "llvm.mips.ilvr.b" => "__builtin_msa_ilvr_b", - "llvm.mips.ilvr.d" => "__builtin_msa_ilvr_d", - "llvm.mips.ilvr.h" => "__builtin_msa_ilvr_h", - "llvm.mips.ilvr.w" => "__builtin_msa_ilvr_w", - "llvm.mips.insert.b" => "__builtin_msa_insert_b", - "llvm.mips.insert.d" => "__builtin_msa_insert_d", - "llvm.mips.insert.h" => "__builtin_msa_insert_h", - "llvm.mips.insert.w" => "__builtin_msa_insert_w", - "llvm.mips.insv" => "__builtin_mips_insv", - "llvm.mips.insve.b" => "__builtin_msa_insve_b", - "llvm.mips.insve.d" => "__builtin_msa_insve_d", - "llvm.mips.insve.h" => "__builtin_msa_insve_h", - "llvm.mips.insve.w" => "__builtin_msa_insve_w", - "llvm.mips.lbux" => "__builtin_mips_lbux", - "llvm.mips.ld.b" => "__builtin_msa_ld_b", - "llvm.mips.ld.d" => "__builtin_msa_ld_d", - "llvm.mips.ld.h" => "__builtin_msa_ld_h", - "llvm.mips.ld.w" => "__builtin_msa_ld_w", - "llvm.mips.ldi.b" => "__builtin_msa_ldi_b", - "llvm.mips.ldi.d" => "__builtin_msa_ldi_d", - "llvm.mips.ldi.h" => "__builtin_msa_ldi_h", - "llvm.mips.ldi.w" => "__builtin_msa_ldi_w", - "llvm.mips.lhx" => "__builtin_mips_lhx", - "llvm.mips.lsa" => "__builtin_mips_lsa", - "llvm.mips.lwx" => "__builtin_mips_lwx", - "llvm.mips.madd" => "__builtin_mips_madd", - "llvm.mips.madd.q.h" => "__builtin_msa_madd_q_h", - "llvm.mips.madd.q.w" => "__builtin_msa_madd_q_w", - "llvm.mips.maddr.q.h" => "__builtin_msa_maddr_q_h", - "llvm.mips.maddr.q.w" => "__builtin_msa_maddr_q_w", - "llvm.mips.maddu" => "__builtin_mips_maddu", - "llvm.mips.maddv.b" => "__builtin_msa_maddv_b", - "llvm.mips.maddv.d" => "__builtin_msa_maddv_d", - "llvm.mips.maddv.h" => "__builtin_msa_maddv_h", - "llvm.mips.maddv.w" => "__builtin_msa_maddv_w", - "llvm.mips.max.a.b" => "__builtin_msa_max_a_b", - "llvm.mips.max.a.d" => "__builtin_msa_max_a_d", - "llvm.mips.max.a.h" => "__builtin_msa_max_a_h", - "llvm.mips.max.a.w" => "__builtin_msa_max_a_w", - "llvm.mips.max.s.b" => "__builtin_msa_max_s_b", - "llvm.mips.max.s.d" => "__builtin_msa_max_s_d", - "llvm.mips.max.s.h" => "__builtin_msa_max_s_h", - "llvm.mips.max.s.w" => "__builtin_msa_max_s_w", - "llvm.mips.max.u.b" => "__builtin_msa_max_u_b", - "llvm.mips.max.u.d" => "__builtin_msa_max_u_d", - "llvm.mips.max.u.h" => "__builtin_msa_max_u_h", - "llvm.mips.max.u.w" => "__builtin_msa_max_u_w", - "llvm.mips.maxi.s.b" => "__builtin_msa_maxi_s_b", - "llvm.mips.maxi.s.d" => "__builtin_msa_maxi_s_d", - "llvm.mips.maxi.s.h" => "__builtin_msa_maxi_s_h", - "llvm.mips.maxi.s.w" => "__builtin_msa_maxi_s_w", - "llvm.mips.maxi.u.b" => "__builtin_msa_maxi_u_b", - "llvm.mips.maxi.u.d" => "__builtin_msa_maxi_u_d", - "llvm.mips.maxi.u.h" => "__builtin_msa_maxi_u_h", - "llvm.mips.maxi.u.w" => "__builtin_msa_maxi_u_w", - "llvm.mips.min.a.b" => "__builtin_msa_min_a_b", - "llvm.mips.min.a.d" => "__builtin_msa_min_a_d", - "llvm.mips.min.a.h" => "__builtin_msa_min_a_h", - "llvm.mips.min.a.w" => "__builtin_msa_min_a_w", - "llvm.mips.min.s.b" => "__builtin_msa_min_s_b", - "llvm.mips.min.s.d" => "__builtin_msa_min_s_d", - "llvm.mips.min.s.h" => "__builtin_msa_min_s_h", - "llvm.mips.min.s.w" => "__builtin_msa_min_s_w", - "llvm.mips.min.u.b" => "__builtin_msa_min_u_b", - "llvm.mips.min.u.d" => "__builtin_msa_min_u_d", - "llvm.mips.min.u.h" => "__builtin_msa_min_u_h", - "llvm.mips.min.u.w" => "__builtin_msa_min_u_w", - "llvm.mips.mini.s.b" => "__builtin_msa_mini_s_b", - "llvm.mips.mini.s.d" => "__builtin_msa_mini_s_d", - "llvm.mips.mini.s.h" => "__builtin_msa_mini_s_h", - "llvm.mips.mini.s.w" => "__builtin_msa_mini_s_w", - "llvm.mips.mini.u.b" => "__builtin_msa_mini_u_b", - "llvm.mips.mini.u.d" => "__builtin_msa_mini_u_d", - "llvm.mips.mini.u.h" => "__builtin_msa_mini_u_h", - "llvm.mips.mini.u.w" => "__builtin_msa_mini_u_w", - "llvm.mips.mod.s.b" => "__builtin_msa_mod_s_b", - "llvm.mips.mod.s.d" => "__builtin_msa_mod_s_d", - "llvm.mips.mod.s.h" => "__builtin_msa_mod_s_h", - "llvm.mips.mod.s.w" => "__builtin_msa_mod_s_w", - "llvm.mips.mod.u.b" => "__builtin_msa_mod_u_b", - "llvm.mips.mod.u.d" => "__builtin_msa_mod_u_d", - "llvm.mips.mod.u.h" => "__builtin_msa_mod_u_h", - "llvm.mips.mod.u.w" => "__builtin_msa_mod_u_w", - "llvm.mips.modsub" => "__builtin_mips_modsub", - "llvm.mips.move.v" => "__builtin_msa_move_v", - "llvm.mips.msub" => "__builtin_mips_msub", - "llvm.mips.msub.q.h" => "__builtin_msa_msub_q_h", - "llvm.mips.msub.q.w" => "__builtin_msa_msub_q_w", - "llvm.mips.msubr.q.h" => "__builtin_msa_msubr_q_h", - "llvm.mips.msubr.q.w" => "__builtin_msa_msubr_q_w", - "llvm.mips.msubu" => "__builtin_mips_msubu", - "llvm.mips.msubv.b" => "__builtin_msa_msubv_b", - "llvm.mips.msubv.d" => "__builtin_msa_msubv_d", - "llvm.mips.msubv.h" => "__builtin_msa_msubv_h", - "llvm.mips.msubv.w" => "__builtin_msa_msubv_w", - "llvm.mips.mthlip" => "__builtin_mips_mthlip", - "llvm.mips.mul.ph" => "__builtin_mips_mul_ph", - "llvm.mips.mul.q.h" => "__builtin_msa_mul_q_h", - "llvm.mips.mul.q.w" => "__builtin_msa_mul_q_w", - "llvm.mips.mul.s.ph" => "__builtin_mips_mul_s_ph", - "llvm.mips.mulr.q.h" => "__builtin_msa_mulr_q_h", - "llvm.mips.mulr.q.w" => "__builtin_msa_mulr_q_w", - "llvm.mips.mulsa.w.ph" => "__builtin_mips_mulsa_w_ph", - "llvm.mips.mult" => "__builtin_mips_mult", - "llvm.mips.multu" => "__builtin_mips_multu", - "llvm.mips.mulv.b" => "__builtin_msa_mulv_b", - "llvm.mips.mulv.d" => "__builtin_msa_mulv_d", - "llvm.mips.mulv.h" => "__builtin_msa_mulv_h", - "llvm.mips.mulv.w" => "__builtin_msa_mulv_w", - "llvm.mips.nloc.b" => "__builtin_msa_nloc_b", - "llvm.mips.nloc.d" => "__builtin_msa_nloc_d", - "llvm.mips.nloc.h" => "__builtin_msa_nloc_h", - "llvm.mips.nloc.w" => "__builtin_msa_nloc_w", - "llvm.mips.nlzc.b" => "__builtin_msa_nlzc_b", - "llvm.mips.nlzc.d" => "__builtin_msa_nlzc_d", - "llvm.mips.nlzc.h" => "__builtin_msa_nlzc_h", - "llvm.mips.nlzc.w" => "__builtin_msa_nlzc_w", - "llvm.mips.nor.v" => "__builtin_msa_nor_v", - "llvm.mips.nori.b" => "__builtin_msa_nori_b", - "llvm.mips.or.v" => "__builtin_msa_or_v", - "llvm.mips.ori.b" => "__builtin_msa_ori_b", - "llvm.mips.pckev.b" => "__builtin_msa_pckev_b", - "llvm.mips.pckev.d" => "__builtin_msa_pckev_d", - "llvm.mips.pckev.h" => "__builtin_msa_pckev_h", - "llvm.mips.pckev.w" => "__builtin_msa_pckev_w", - "llvm.mips.pckod.b" => "__builtin_msa_pckod_b", - "llvm.mips.pckod.d" => "__builtin_msa_pckod_d", - "llvm.mips.pckod.h" => "__builtin_msa_pckod_h", - "llvm.mips.pckod.w" => "__builtin_msa_pckod_w", - "llvm.mips.pcnt.b" => "__builtin_msa_pcnt_b", - "llvm.mips.pcnt.d" => "__builtin_msa_pcnt_d", - "llvm.mips.pcnt.h" => "__builtin_msa_pcnt_h", - "llvm.mips.pcnt.w" => "__builtin_msa_pcnt_w", - "llvm.mips.pick.qb" => "__builtin_mips_pick_qb", - "llvm.mips.precr.qb.ph" => "__builtin_mips_precr_qb_ph", - "llvm.mips.precr.sra.ph.w" => "__builtin_mips_precr_sra_ph_w", - "llvm.mips.precr.sra.r.ph.w" => "__builtin_mips_precr_sra_r_ph_w", - "llvm.mips.prepend" => "__builtin_mips_prepend", - "llvm.mips.raddu.w.qb" => "__builtin_mips_raddu_w_qb", - "llvm.mips.rddsp" => "__builtin_mips_rddsp", - "llvm.mips.repl.qb" => "__builtin_mips_repl_qb", - "llvm.mips.sat.s.b" => "__builtin_msa_sat_s_b", - "llvm.mips.sat.s.d" => "__builtin_msa_sat_s_d", - "llvm.mips.sat.s.h" => "__builtin_msa_sat_s_h", - "llvm.mips.sat.s.w" => "__builtin_msa_sat_s_w", - "llvm.mips.sat.u.b" => "__builtin_msa_sat_u_b", - "llvm.mips.sat.u.d" => "__builtin_msa_sat_u_d", - "llvm.mips.sat.u.h" => "__builtin_msa_sat_u_h", - "llvm.mips.sat.u.w" => "__builtin_msa_sat_u_w", - "llvm.mips.shf.b" => "__builtin_msa_shf_b", - "llvm.mips.shf.h" => "__builtin_msa_shf_h", - "llvm.mips.shf.w" => "__builtin_msa_shf_w", - "llvm.mips.shilo" => "__builtin_mips_shilo", - "llvm.mips.shll.qb" => "__builtin_mips_shll_qb", - "llvm.mips.shra.qb" => "__builtin_mips_shra_qb", - "llvm.mips.shra.r.qb" => "__builtin_mips_shra_r_qb", - "llvm.mips.shrl.ph" => "__builtin_mips_shrl_ph", - "llvm.mips.shrl.qb" => "__builtin_mips_shrl_qb", - "llvm.mips.sld.b" => "__builtin_msa_sld_b", - "llvm.mips.sld.d" => "__builtin_msa_sld_d", - "llvm.mips.sld.h" => "__builtin_msa_sld_h", - "llvm.mips.sld.w" => "__builtin_msa_sld_w", - "llvm.mips.sldi.b" => "__builtin_msa_sldi_b", - "llvm.mips.sldi.d" => "__builtin_msa_sldi_d", - "llvm.mips.sldi.h" => "__builtin_msa_sldi_h", - "llvm.mips.sldi.w" => "__builtin_msa_sldi_w", - "llvm.mips.sll.b" => "__builtin_msa_sll_b", - "llvm.mips.sll.d" => "__builtin_msa_sll_d", - "llvm.mips.sll.h" => "__builtin_msa_sll_h", - "llvm.mips.sll.w" => "__builtin_msa_sll_w", - "llvm.mips.slli.b" => "__builtin_msa_slli_b", - "llvm.mips.slli.d" => "__builtin_msa_slli_d", - "llvm.mips.slli.h" => "__builtin_msa_slli_h", - "llvm.mips.slli.w" => "__builtin_msa_slli_w", - "llvm.mips.splat.b" => "__builtin_msa_splat_b", - "llvm.mips.splat.d" => "__builtin_msa_splat_d", - "llvm.mips.splat.h" => "__builtin_msa_splat_h", - "llvm.mips.splat.w" => "__builtin_msa_splat_w", - "llvm.mips.splati.b" => "__builtin_msa_splati_b", - "llvm.mips.splati.d" => "__builtin_msa_splati_d", - "llvm.mips.splati.h" => "__builtin_msa_splati_h", - "llvm.mips.splati.w" => "__builtin_msa_splati_w", - "llvm.mips.sra.b" => "__builtin_msa_sra_b", - "llvm.mips.sra.d" => "__builtin_msa_sra_d", - "llvm.mips.sra.h" => "__builtin_msa_sra_h", - "llvm.mips.sra.w" => "__builtin_msa_sra_w", - "llvm.mips.srai.b" => "__builtin_msa_srai_b", - "llvm.mips.srai.d" => "__builtin_msa_srai_d", - "llvm.mips.srai.h" => "__builtin_msa_srai_h", - "llvm.mips.srai.w" => "__builtin_msa_srai_w", - "llvm.mips.srar.b" => "__builtin_msa_srar_b", - "llvm.mips.srar.d" => "__builtin_msa_srar_d", - "llvm.mips.srar.h" => "__builtin_msa_srar_h", - "llvm.mips.srar.w" => "__builtin_msa_srar_w", - "llvm.mips.srari.b" => "__builtin_msa_srari_b", - "llvm.mips.srari.d" => "__builtin_msa_srari_d", - "llvm.mips.srari.h" => "__builtin_msa_srari_h", - "llvm.mips.srari.w" => "__builtin_msa_srari_w", - "llvm.mips.srl.b" => "__builtin_msa_srl_b", - "llvm.mips.srl.d" => "__builtin_msa_srl_d", - "llvm.mips.srl.h" => "__builtin_msa_srl_h", - "llvm.mips.srl.w" => "__builtin_msa_srl_w", - "llvm.mips.srli.b" => "__builtin_msa_srli_b", - "llvm.mips.srli.d" => "__builtin_msa_srli_d", - "llvm.mips.srli.h" => "__builtin_msa_srli_h", - "llvm.mips.srli.w" => "__builtin_msa_srli_w", - "llvm.mips.srlr.b" => "__builtin_msa_srlr_b", - "llvm.mips.srlr.d" => "__builtin_msa_srlr_d", - "llvm.mips.srlr.h" => "__builtin_msa_srlr_h", - "llvm.mips.srlr.w" => "__builtin_msa_srlr_w", - "llvm.mips.srlri.b" => "__builtin_msa_srlri_b", - "llvm.mips.srlri.d" => "__builtin_msa_srlri_d", - "llvm.mips.srlri.h" => "__builtin_msa_srlri_h", - "llvm.mips.srlri.w" => "__builtin_msa_srlri_w", - "llvm.mips.st.b" => "__builtin_msa_st_b", - "llvm.mips.st.d" => "__builtin_msa_st_d", - "llvm.mips.st.h" => "__builtin_msa_st_h", - "llvm.mips.st.w" => "__builtin_msa_st_w", - "llvm.mips.subs.s.b" => "__builtin_msa_subs_s_b", - "llvm.mips.subs.s.d" => "__builtin_msa_subs_s_d", - "llvm.mips.subs.s.h" => "__builtin_msa_subs_s_h", - "llvm.mips.subs.s.w" => "__builtin_msa_subs_s_w", - "llvm.mips.subs.u.b" => "__builtin_msa_subs_u_b", - "llvm.mips.subs.u.d" => "__builtin_msa_subs_u_d", - "llvm.mips.subs.u.h" => "__builtin_msa_subs_u_h", - "llvm.mips.subs.u.w" => "__builtin_msa_subs_u_w", - "llvm.mips.subsus.u.b" => "__builtin_msa_subsus_u_b", - "llvm.mips.subsus.u.d" => "__builtin_msa_subsus_u_d", - "llvm.mips.subsus.u.h" => "__builtin_msa_subsus_u_h", - "llvm.mips.subsus.u.w" => "__builtin_msa_subsus_u_w", - "llvm.mips.subsuu.s.b" => "__builtin_msa_subsuu_s_b", - "llvm.mips.subsuu.s.d" => "__builtin_msa_subsuu_s_d", - "llvm.mips.subsuu.s.h" => "__builtin_msa_subsuu_s_h", - "llvm.mips.subsuu.s.w" => "__builtin_msa_subsuu_s_w", - "llvm.mips.subu.ph" => "__builtin_mips_subu_ph", - "llvm.mips.subu.qb" => "__builtin_mips_subu_qb", - "llvm.mips.subu.s.ph" => "__builtin_mips_subu_s_ph", - "llvm.mips.subu.s.qb" => "__builtin_mips_subu_s_qb", - "llvm.mips.subuh.qb" => "__builtin_mips_subuh_qb", - "llvm.mips.subuh.r.qb" => "__builtin_mips_subuh_r_qb", - "llvm.mips.subv.b" => "__builtin_msa_subv_b", - "llvm.mips.subv.d" => "__builtin_msa_subv_d", - "llvm.mips.subv.h" => "__builtin_msa_subv_h", - "llvm.mips.subv.w" => "__builtin_msa_subv_w", - "llvm.mips.subvi.b" => "__builtin_msa_subvi_b", - "llvm.mips.subvi.d" => "__builtin_msa_subvi_d", - "llvm.mips.subvi.h" => "__builtin_msa_subvi_h", - "llvm.mips.subvi.w" => "__builtin_msa_subvi_w", - "llvm.mips.vshf.b" => "__builtin_msa_vshf_b", - "llvm.mips.vshf.d" => "__builtin_msa_vshf_d", - "llvm.mips.vshf.h" => "__builtin_msa_vshf_h", - "llvm.mips.vshf.w" => "__builtin_msa_vshf_w", - "llvm.mips.wrdsp" => "__builtin_mips_wrdsp", - "llvm.mips.xor.v" => "__builtin_msa_xor_v", - "llvm.mips.xori.b" => "__builtin_msa_xori_b", // xcore "llvm.xcore.bitrev" => "__builtin_bitrev", "llvm.xcore.getid" => "__builtin_getid", "llvm.xcore.getps" => "__builtin_getps", "llvm.xcore.setps" => "__builtin_setps", - // ptx - "llvm.ptx.bar.sync" => "__builtin_ptx_bar_sync", - "llvm.ptx.read.clock" => "__builtin_ptx_read_clock", - "llvm.ptx.read.clock64" => "__builtin_ptx_read_clock64", - "llvm.ptx.read.gridid" => "__builtin_ptx_read_gridid", - "llvm.ptx.read.laneid" => "__builtin_ptx_read_laneid", - "llvm.ptx.read.lanemask.eq" => "__builtin_ptx_read_lanemask_eq", - "llvm.ptx.read.lanemask.ge" => "__builtin_ptx_read_lanemask_ge", - "llvm.ptx.read.lanemask.gt" => "__builtin_ptx_read_lanemask_gt", - "llvm.ptx.read.lanemask.le" => "__builtin_ptx_read_lanemask_le", - "llvm.ptx.read.lanemask.lt" => "__builtin_ptx_read_lanemask_lt", - "llvm.ptx.read.nsmid" => "__builtin_ptx_read_nsmid", - "llvm.ptx.read.nwarpid" => "__builtin_ptx_read_nwarpid", - "llvm.ptx.read.pm0" => "__builtin_ptx_read_pm0", - "llvm.ptx.read.pm1" => "__builtin_ptx_read_pm1", - "llvm.ptx.read.pm2" => "__builtin_ptx_read_pm2", - "llvm.ptx.read.pm3" => "__builtin_ptx_read_pm3", - "llvm.ptx.read.smid" => "__builtin_ptx_read_smid", - "llvm.ptx.read.warpid" => "__builtin_ptx_read_warpid", - // cuda - "llvm.cuda.syncthreads" => "__syncthreads", -_ => unimplemented!("***** unsupported LLVM intrinsic {}", name), + _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), } From 56983cf3c6367f13fb94f6ada05537156f513e6c Mon Sep 17 00:00:00 2001 From: yvt Date: Fri, 1 Apr 2022 12:55:00 +0900 Subject: [PATCH 059/356] test: Remove redundant code from `tests/run/int.rs` --- tests/run/int.rs | 23 ++--------------------- 1 file changed, 2 insertions(+), 21 deletions(-) diff --git a/tests/run/int.rs b/tests/run/int.rs index 49376012c40e..7139b8d4f5dc 100644 --- a/tests/run/int.rs +++ b/tests/run/int.rs @@ -3,32 +3,13 @@ // Run-time: // status: 0 -#![feature(arbitrary_self_types, auto_traits, core_intrinsics, lang_items, start, intrinsics)] +#![feature(core_intrinsics, start)] #![no_std] -mod intrinsics { - extern "rust-intrinsic" { - pub fn abort() -> !; - } -} - -/* - * Core - */ - -mod libc { - #[link(name = "c")] - extern "C" { - pub fn puts(s: *const u8) -> i32; - } -} - #[panic_handler] fn panic_handler(_: &core::panic::PanicInfo) -> ! { - unsafe { - core::intrinsics::abort(); - } + core::intrinsics::abort(); } /* From 837a4467bc98471d5619e76cc47eac3b9a471d28 Mon Sep 17 00:00:00 2001 From: yvt Date: Wed, 6 Apr 2022 01:25:13 +0900 Subject: [PATCH 060/356] test: Test more integer types and checked arithmetic in `tests/run/int.rs` --- tests/run/int.rs | 389 ++++++++++++++++++++++++++++++++++++----------- 1 file changed, 300 insertions(+), 89 deletions(-) diff --git a/tests/run/int.rs b/tests/run/int.rs index 7139b8d4f5dc..8d2db9096f73 100644 --- a/tests/run/int.rs +++ b/tests/run/int.rs @@ -3,7 +3,7 @@ // Run-time: // status: 0 -#![feature(core_intrinsics, start)] +#![feature(bench_black_box, core_intrinsics, start)] #![no_std] @@ -17,118 +17,329 @@ fn panic_handler(_: &core::panic::PanicInfo) -> ! { */ #[start] -fn main(argc: isize, _argv: *const *const u8) -> isize { - let var = 134217856_u128; - let var2 = 10475372733397991552_u128; - let var3 = 193236519889708027473620326106273939584_u128; - let var4 = 123236519889708027473620326106273939584_u128; - let var5 = 153236519889708027473620326106273939584_u128; - let var6 = 18446744073709551616_i128; - let var7 = 170141183460469231731687303715884105728_u128; +fn main(_argc: isize, _argv: *const *const u8) -> isize { + let one: isize = core::hint::black_box(1); - // Shifts. - assert_eq!(var << (argc as u128 - 1), var); - assert_eq!(var << argc as u128, 268435712); - assert_eq!(var << (argc + 32) as u128, 1152922604118474752); - assert_eq!(var << (argc + 48) as u128, 75557935783508361347072); - assert_eq!(var << (argc + 60) as u128, 309485304969250248077606912); - assert_eq!(var << (argc + 62) as u128, 1237941219877000992310427648); - assert_eq!(var << (argc + 63) as u128, 2475882439754001984620855296); - assert_eq!(var << (argc + 80) as u128, 324518863143436548128224745357312); + macro_rules! check { + ($ty:ty, $expr:expr) => { + { + const EXPECTED: $ty = { + #[allow(non_upper_case_globals)] + #[allow(dead_code)] + const one: isize = 1; + $expr + }; + assert_eq!($expr, EXPECTED); + } + }; + } - assert_eq!(var2 << argc as u128, 20950745466795983104); - assert_eq!(var2 << (argc as u128 - 1), var2); - assert_eq!(var2 << (argc + 32) as u128, 89982766606709001335848566784); - assert_eq!(var2 << (argc + 48) as u128, 5897110592337281111546171672756224); - assert_eq!(var2 << (argc + 60) as u128, 24154564986213503432893119171609493504); - assert_eq!(var2 << (argc + 62) as u128, 96618259944854013731572476686437974016); - assert_eq!(var2 << (argc + 63) as u128, 193236519889708027463144953372875948032); + check!(u32, (2220326408_u32 + one as u32) >> (32 - 6)); - assert_eq!(var3 << argc as u128, 46190672858477591483866044780779667712); - assert_eq!(var3 << (argc as u128 - 1), var3); - assert_eq!(var3 << (argc + 32) as u128, 21267668304951024224840338247585366016); - assert_eq!(var3 << (argc + 48) as u128, 1335125106377253154015353231953100800); - assert_eq!(var3 << (argc + 60) as u128, 24154564986213503432893119171609493504); - assert_eq!(var3 << (argc + 62) as u128, 96618259944854013731572476686437974016); - assert_eq!(var3 << (argc + 63) as u128, 193236519889708027463144953372875948032); + /// Generate `check!` tests for integer types at least as wide as 128 bits. + macro_rules! check_ops128 { + () => { + check_ops64!(); - assert_eq!((2220326408_u32 + argc as u32) >> (32 - 6), 33); + // Shifts. + check!(T, VAL1 << (one + 63) as T); + check!(T, VAL1 << (one + 80) as T); + check!(T, VAL3 << (one + 62) as T); + check!(T, VAL3 << (one + 63) as T); - assert_eq!(var >> (argc as u128 - 1), var); - assert_eq!(var >> argc as u128, 67108928); - assert_eq!(var >> (argc + 32) as u128, 0); - assert_eq!(var >> (argc + 48) as u128, 0); - assert_eq!(var >> (argc + 60) as u128, 0); - assert_eq!(var >> (argc + 62) as u128, 0); - assert_eq!(var >> (argc + 63) as u128, 0); + check!(T, VAL1 >> (one + 63) as T); + check!(T, VAL2 >> (one + 63) as T); + check!(T, VAL3 >> (one + 63) as T); + check!(T, VAL3 >> (one + 80) as T); + }; + } - assert_eq!(var2 >> argc as u128, 5237686366698995776); - assert_eq!(var2 >> (argc as u128 - 1), var2); - assert_eq!(var2 >> (argc + 32) as u128, 1219493888); - assert_eq!(var2 >> (argc + 48) as u128, 18608); - assert_eq!(var2 >> (argc + 60) as u128, 4); - assert_eq!(var2 >> (argc + 62) as u128, 1); - assert_eq!(var2 >> (argc + 63) as u128, 0); + /// Generate `check!` tests for integer types at least as wide as 64 bits. + macro_rules! check_ops64 { + () => { + check_ops32!(); - assert_eq!(var3 >> (argc as u128 - 1), var3); - assert_eq!(var3 >> argc as u128, 96618259944854013736810163053136969792); - assert_eq!(var3 >> (argc + 32) as u128, 22495691651677250335181635584); - assert_eq!(var3 >> (argc + 48) as u128, 343257013727985387194544); - assert_eq!(var3 >> (argc + 60) as u128, 83802981867183932420); - assert_eq!(var3 >> (argc + 62) as u128, 20950745466795983105); - assert_eq!(var3 >> (argc + 63) as u128, 10475372733397991552); - assert_eq!(var3 >> (argc + 80) as u128, 79920751444992); + // Shifts. + check!(T, VAL2 << (one + 32) as T); + check!(T, VAL2 << (one + 48) as T); + check!(T, VAL2 << (one + 60) as T); + check!(T, VAL2 << (one + 62) as T); - assert_eq!(var6 >> argc as u128, 9223372036854775808); - assert_eq!((var6 - 1) >> argc as u128, 9223372036854775807); - assert_eq!(var7 >> argc as u128, 85070591730234615865843651857942052864); + check!(T, VAL3 << (one + 32) as T); + check!(T, VAL3 << (one + 48) as T); + check!(T, VAL3 << (one + 60) as T); - // Casts - assert_eq!((var >> (argc + 32) as u128) as u64, 0); - assert_eq!((var >> argc as u128) as u64, 67108928); + check!(T, VAL1 >> (one + 32) as T); + check!(T, VAL1 >> (one + 48) as T); + check!(T, VAL1 >> (one + 60) as T); + check!(T, VAL1 >> (one + 62) as T); - // Addition. - assert_eq!(var + argc as u128, 134217857); + check!(T, VAL2 >> (one + 32) as T); + check!(T, VAL2 >> (one + 48) as T); + check!(T, VAL2 >> (one + 60) as T); + check!(T, VAL2 >> (one + 62) as T); - assert_eq!(var2 + argc as u128, 10475372733397991553); - assert_eq!(var2 + (var2 + argc as u128) as u128, 20950745466795983105); + check!(T, VAL3 >> (one + 32) as T); + check!(T, VAL3 >> (one + 48) as T); + check!(T, VAL3 >> (one + 60) as T); + check!(T, VAL3 >> (one + 62) as T); + }; + } - assert_eq!(var3 + argc as u128, 193236519889708027473620326106273939585); + /// Generate `check!` tests for integer types at least as wide as 32 bits. + macro_rules! check_ops32 { + () => { + // Shifts. + check!(T, VAL2 << one as T); + check!(T, VAL2 << (one as T - 1)); - // Subtraction - assert_eq!(var - argc as u128, 134217855); + check!(T, VAL3 << one as T); + check!(T, VAL3 << (one as T - 1)); - assert_eq!(var2 - argc as u128, 10475372733397991551); + check!(T, VAL1.wrapping_shl(one as u32 - 1)); + check!(T, VAL1.wrapping_shl(one as u32)); + check!(T, VAL1.wrapping_shl((one + 32) as u32)); + check!(T, VAL1.wrapping_shl((one + 48) as u32)); + check!(T, VAL1.wrapping_shl((one + 60) as u32)); + check!(T, VAL1.wrapping_shl((one + 62) as u32)); + check!(T, VAL1.wrapping_shl((one + 63) as u32)); + check!(T, VAL1.wrapping_shl((one + 80) as u32)); - assert_eq!(var3 - argc as u128, 193236519889708027473620326106273939583); + check!(Option, VAL1.checked_shl(one as u32 - 1)); + check!(Option, VAL1.checked_shl(one as u32)); + check!(Option, VAL1.checked_shl((one + 32) as u32)); + check!(Option, VAL1.checked_shl((one + 48) as u32)); + check!(Option, VAL1.checked_shl((one + 60) as u32)); + check!(Option, VAL1.checked_shl((one + 62) as u32)); + check!(Option, VAL1.checked_shl((one + 63) as u32)); + check!(Option, VAL1.checked_shl((one + 80) as u32)); - // Multiplication - assert_eq!(var * (argc + 1) as u128, 268435712); - assert_eq!(var * (argc as u128 + var2), 1405982069077538020949770368); + check!(T, VAL1 >> (one as T - 1)); + check!(T, VAL1 >> one as T); - assert_eq!(var2 * (argc + 1) as u128, 20950745466795983104); - assert_eq!(var2 * (argc as u128 + var2), 109733433903618109003204073240861360256); + check!(T, VAL2 >> one as T); + check!(T, VAL2 >> (one as T - 1)); - assert_eq!(var3 * argc as u128, 193236519889708027473620326106273939584); + check!(T, VAL3 >> (one as T - 1)); + check!(T, VAL3 >> one as T); - assert_eq!(var4 * (argc + 1) as u128, 246473039779416054947240652212547879168); + check!(T, VAL1.wrapping_shr(one as u32 - 1)); + check!(T, VAL1.wrapping_shr(one as u32)); + check!(T, VAL1.wrapping_shr((one + 32) as u32)); + check!(T, VAL1.wrapping_shr((one + 48) as u32)); + check!(T, VAL1.wrapping_shr((one + 60) as u32)); + check!(T, VAL1.wrapping_shr((one + 62) as u32)); + check!(T, VAL1.wrapping_shr((one + 63) as u32)); + check!(T, VAL1.wrapping_shr((one + 80) as u32)); - assert_eq!(var5 * (argc + 1) as u128, 306473039779416054947240652212547879168); + check!(Option, VAL1.checked_shr(one as u32 - 1)); + check!(Option, VAL1.checked_shr(one as u32)); + check!(Option, VAL1.checked_shr((one + 32) as u32)); + check!(Option, VAL1.checked_shr((one + 48) as u32)); + check!(Option, VAL1.checked_shr((one + 60) as u32)); + check!(Option, VAL1.checked_shr((one + 62) as u32)); + check!(Option, VAL1.checked_shr((one + 63) as u32)); + check!(Option, VAL1.checked_shr((one + 80) as u32)); - // Division. - assert_eq!(var / (argc + 1) as u128, 67108928); - assert_eq!(var / (argc + 2) as u128, 44739285); + // Casts + check!(u64, (VAL1 >> one as T) as u64); - assert_eq!(var2 / (argc + 1) as u128, 5237686366698995776); - assert_eq!(var2 / (argc + 2) as u128, 3491790911132663850); + // Addition. + check!(T, VAL1 + one as T); + check!(T, VAL2 + one as T); + check!(T, VAL2 + (VAL2 + one as T) as T); + check!(T, VAL3 + one as T); - assert_eq!(var3 / (argc + 1) as u128, 96618259944854013736810163053136969792); - assert_eq!(var3 / (argc + 2) as u128, 64412173296569342491206775368757979861); - assert_eq!(var3 / (argc as u128 + var4), 1); - assert_eq!(var3 / (argc as u128 + var2), 18446744073709551615); + check!(Option, VAL1.checked_add(one as T)); + check!(Option, VAL2.checked_add(one as T)); + check!(Option, VAL2.checked_add((VAL2 + one as T) as T)); + check!(Option, VAL3.checked_add(T::MAX)); + check!(Option, VAL3.checked_add(T::MIN)); - assert_eq!(var4 / (argc + 1) as u128, 61618259944854013736810163053136969792); - assert_eq!(var4 / (argc + 2) as u128, 41078839963236009157873442035424646528); + check!(T, VAL1.wrapping_add(one as T)); + check!(T, VAL2.wrapping_add(one as T)); + check!(T, VAL2.wrapping_add((VAL2 + one as T) as T)); + check!(T, VAL3.wrapping_add(T::MAX)); + check!(T, VAL3.wrapping_add(T::MIN)); + + check!((T, bool), VAL1.overflowing_add(one as T)); + check!((T, bool), VAL2.overflowing_add(one as T)); + check!((T, bool), VAL2.overflowing_add((VAL2 + one as T) as T)); + check!((T, bool), VAL3.overflowing_add(T::MAX)); + check!((T, bool), VAL3.overflowing_add(T::MIN)); + + check!(T, VAL1.saturating_add(one as T)); + check!(T, VAL2.saturating_add(one as T)); + check!(T, VAL2.saturating_add((VAL2 + one as T) as T)); + check!(T, VAL3.saturating_add(T::MAX)); + check!(T, VAL3.saturating_add(T::MIN)); + + // Subtraction + check!(T, VAL1 - one as T); + check!(T, VAL2 - one as T); + check!(T, VAL3 - one as T); + + check!(Option, VAL1.checked_sub(one as T)); + check!(Option, VAL2.checked_sub(one as T)); + check!(Option, VAL2.checked_sub((VAL2 + one as T) as T)); + check!(Option, VAL3.checked_sub(T::MAX)); + check!(Option, VAL3.checked_sub(T::MIN)); + + check!(T, VAL1.wrapping_sub(one as T)); + check!(T, VAL2.wrapping_sub(one as T)); + check!(T, VAL2.wrapping_sub((VAL2 + one as T) as T)); + check!(T, VAL3.wrapping_sub(T::MAX)); + check!(T, VAL3.wrapping_sub(T::MIN)); + + check!((T, bool), VAL1.overflowing_sub(one as T)); + check!((T, bool), VAL2.overflowing_sub(one as T)); + check!((T, bool), VAL2.overflowing_sub((VAL2 + one as T) as T)); + check!((T, bool), VAL3.overflowing_sub(T::MAX)); + check!((T, bool), VAL3.overflowing_sub(T::MIN)); + + check!(T, VAL1.saturating_sub(one as T)); + check!(T, VAL2.saturating_sub(one as T)); + check!(T, VAL2.saturating_sub((VAL2 + one as T) as T)); + check!(T, VAL3.saturating_sub(T::MAX)); + check!(T, VAL3.saturating_sub(T::MIN)); + + // Multiplication + check!(T, VAL1 * (one + 1) as T); + check!(T, VAL1 * (one as T + VAL2)); + check!(T, VAL2 * (one + 1) as T); + check!(T, VAL2 * (one as T + VAL2)); + check!(T, VAL3 * one as T); + check!(T, VAL4 * (one + 1) as T); + check!(T, VAL5 * (one + 1) as T); + + check!(Option, VAL1.checked_mul((one + 1) as T)); + check!(Option, VAL1.checked_mul((one as T + VAL2))); + check!(Option, VAL3.checked_mul(VAL3)); + check!(Option, VAL4.checked_mul((one + 1) as T)); + check!(Option, VAL5.checked_mul((one + 1) as T)); + + check!(T, VAL1.wrapping_mul((one + 1) as T)); + check!(T, VAL1.wrapping_mul((one as T + VAL2))); + check!(T, VAL3.wrapping_mul(VAL3)); + check!(T, VAL4.wrapping_mul((one + 1) as T)); + check!(T, VAL5.wrapping_mul((one + 1) as T)); + + check!((T, bool), VAL1.overflowing_mul((one + 1) as T)); + check!((T, bool), VAL1.overflowing_mul((one as T + VAL2))); + check!((T, bool), VAL3.overflowing_mul(VAL3)); + check!((T, bool), VAL4.overflowing_mul((one + 1) as T)); + check!((T, bool), VAL5.overflowing_mul((one + 1) as T)); + + check!(T, VAL1.saturating_mul((one + 1) as T)); + check!(T, VAL1.saturating_mul((one as T + VAL2))); + check!(T, VAL3.saturating_mul(VAL3)); + check!(T, VAL4.saturating_mul((one + 1) as T)); + check!(T, VAL5.saturating_mul((one + 1) as T)); + + // Division. + check!(T, VAL1 / (one + 1) as T); + check!(T, VAL1 / (one + 2) as T); + + check!(T, VAL2 / (one + 1) as T); + check!(T, VAL2 / (one + 2) as T); + + check!(T, VAL3 / (one + 1) as T); + check!(T, VAL3 / (one + 2) as T); + check!(T, VAL3 / (one as T + VAL4)); + check!(T, VAL3 / (one as T + VAL2)); + + check!(T, VAL4 / (one + 1) as T); + check!(T, VAL4 / (one + 2) as T); + + check!(Option, VAL1.checked_div((one + 1) as T)); + check!(Option, VAL1.checked_div((one as T + VAL2))); + check!(Option, VAL3.checked_div(VAL3)); + check!(Option, VAL4.checked_div((one + 1) as T)); + check!(Option, VAL5.checked_div((one + 1) as T)); + check!(Option, (T::MIN).checked_div((0 as T).wrapping_sub(one as T))); + check!(Option, VAL5.checked_div((one - 1) as T)); // var5 / 0 + + check!(T, VAL1.wrapping_div((one + 1) as T)); + check!(T, VAL1.wrapping_div((one as T + VAL2))); + check!(T, VAL3.wrapping_div(VAL3)); + check!(T, VAL4.wrapping_div((one + 1) as T)); + check!(T, VAL5.wrapping_div((one + 1) as T)); + check!(T, (T::MIN).wrapping_div((0 as T).wrapping_sub(one as T))); + + check!((T, bool), VAL1.overflowing_div((one + 1) as T)); + check!((T, bool), VAL1.overflowing_div((one as T + VAL2))); + check!((T, bool), VAL3.overflowing_div(VAL3)); + check!((T, bool), VAL4.overflowing_div((one + 1) as T)); + check!((T, bool), VAL5.overflowing_div((one + 1) as T)); + check!((T, bool), (T::MIN).overflowing_div((0 as T).wrapping_sub(one as T))); + + check!(T, VAL1.saturating_div((one + 1) as T)); + check!(T, VAL1.saturating_div((one as T + VAL2))); + check!(T, VAL3.saturating_div(VAL3)); + check!(T, VAL4.saturating_div((one + 1) as T)); + check!(T, VAL5.saturating_div((one + 1) as T)); + check!(T, (T::MIN).saturating_div((0 as T).wrapping_sub(one as T))); + }; + } + + { + type T = u32; + const VAL1: T = 14162_u32; + const VAL2: T = 14556_u32; + const VAL3: T = 323656954_u32; + const VAL4: T = 2023651954_u32; + const VAL5: T = 1323651954_u32; + check_ops32!(); + } + + { + type T = i32; + const VAL1: T = 13456_i32; + const VAL2: T = 10475_i32; + const VAL3: T = 923653954_i32; + const VAL4: T = 993198738_i32; + const VAL5: T = 1023653954_i32; + check_ops32!(); + } + + { + type T = u64; + const VAL1: T = 134217856_u64; + const VAL2: T = 104753732_u64; + const VAL3: T = 12323651988970863954_u64; + const VAL4: T = 7323651988970863954_u64; + const VAL5: T = 8323651988970863954_u64; + check_ops64!(); + } + + { + type T = i64; + const VAL1: T = 134217856_i64; + const VAL2: T = 104753732_i64; + const VAL3: T = 6323651988970863954_i64; + const VAL4: T = 2323651988970863954_i64; + const VAL5: T = 3323651988970863954_i64; + check_ops64!(); + } + + { + type T = u128; + const VAL1: T = 134217856_u128; + const VAL2: T = 10475372733397991552_u128; + const VAL3: T = 193236519889708027473620326106273939584_u128; + const VAL4: T = 123236519889708027473620326106273939584_u128; + const VAL5: T = 153236519889708027473620326106273939584_u128; + check_ops128!(); + } + { + type T = i128; + const VAL1: T = 134217856_i128; + const VAL2: T = 10475372733397991552_i128; + const VAL3: T = 83236519889708027473620326106273939584_i128; + const VAL4: T = 63236519889708027473620326106273939584_i128; + const VAL5: T = 73236519889708027473620326106273939584_i128; + check_ops128!(); + } 0 } From 00677e51596f89325551e99c2d30bd39ae381e0c Mon Sep 17 00:00:00 2001 From: yvt Date: Fri, 1 Apr 2022 13:54:51 +0900 Subject: [PATCH 061/356] Implement `saturating_{add, sub}` for non-native integer types Updates their unsigned code paths to use the `Builder::gcc_` methods that automatically lower non-native integer operations to native ones. Also updates the signed code path of `saturating_add` to support non- native integer types. That of `saturating_sub` already supports this, so no major changes have been made. --- src/intrinsic/mod.rs | 92 +++++++++++++++++++++++++++----------------- 1 file changed, 57 insertions(+), 35 deletions(-) diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index 08e584a46f33..84395e967636 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -967,34 +967,55 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { } fn saturating_add(&mut self, lhs: RValue<'gcc>, rhs: RValue<'gcc>, signed: bool, width: u64) -> RValue<'gcc> { - let func = self.current_func.borrow().expect("func"); - + let result_type = lhs.get_type(); if signed { - // Algorithm from: https://stackoverflow.com/a/56531252/389119 - let after_block = func.new_block("after"); - let func_name = - match width { - 8 => "__builtin_add_overflow", - 16 => "__builtin_add_overflow", - 32 => "__builtin_sadd_overflow", - 64 => "__builtin_saddll_overflow", - 128 => "__builtin_add_overflow", - _ => unreachable!(), - }; - let overflow_func = self.context.get_builtin_function(func_name); - let result_type = lhs.get_type(); + // Based on algorithm from: https://stackoverflow.com/a/56531252/389119 + let func = self.current_func.borrow().expect("func"); let res = func.new_local(None, result_type, "saturating_sum"); - let overflow = self.overflow_call(overflow_func, &[lhs, rhs, res.get_address(None)], None); + let supports_native_type = self.is_native_int_type(result_type); + let overflow = + if supports_native_type { + let func_name = + match width { + 8 => "__builtin_add_overflow", + 16 => "__builtin_add_overflow", + 32 => "__builtin_sadd_overflow", + 64 => "__builtin_saddll_overflow", + 128 => "__builtin_add_overflow", + _ => unreachable!(), + }; + let overflow_func = self.context.get_builtin_function(func_name); + self.overflow_call(overflow_func, &[lhs, rhs, res.get_address(None)], None) + } + else { + let func_name = + match width { + 128 => "__rust_i128_addo", + _ => unreachable!(), + }; + let param_a = self.context.new_parameter(None, result_type, "a"); + let param_b = self.context.new_parameter(None, result_type, "b"); + let result_field = self.context.new_field(None, result_type, "result"); + let overflow_field = self.context.new_field(None, self.bool_type, "overflow"); + let return_type = self.context.new_struct_type(None, "result_overflow", &[result_field, overflow_field]); + let func = self.context.new_function(None, FunctionType::Extern, return_type.as_type(), &[param_a, param_b], func_name, false); + let result = self.context.new_call(None, func, &[lhs, rhs]); + let overflow = result.access_field(None, overflow_field); + let int_result = result.access_field(None, result_field); + self.llbb().add_assignment(None, res, int_result); + overflow + }; let then_block = func.new_block("then"); + let after_block = func.new_block("after"); - let unsigned_type = self.context.new_int_type(width as i32 / 8, false); - let shifted = self.context.new_cast(None, lhs, unsigned_type) >> self.context.new_rvalue_from_int(unsigned_type, width as i32 - 1); - let uint_max = self.context.new_unary_op(None, UnaryOp::BitwiseNegate, unsigned_type, - self.context.new_rvalue_from_int(unsigned_type, 0) - ); - let int_max = uint_max >> self.context.new_rvalue_one(unsigned_type); - then_block.add_assignment(None, res, self.context.new_cast(None, shifted + int_max, result_type)); + // Return `result_type`'s maximum or minimum value on overflow + // NOTE: convert the type to unsigned to have an unsigned shift. + let unsigned_type = result_type.to_unsigned(&self.cx); + let shifted = self.gcc_lshr(self.gcc_int_cast(lhs, unsigned_type), self.gcc_int(unsigned_type, width as i64 - 1)); + let uint_max = self.gcc_not(self.gcc_int(unsigned_type, 0)); + let int_max = self.gcc_lshr(uint_max, self.gcc_int(unsigned_type, 1)); + then_block.add_assignment(None, res, self.gcc_int_cast(self.gcc_add(shifted, int_max), result_type)); then_block.end_with_jump(None, after_block); self.llbb().end_with_conditional(None, overflow, then_block, after_block); @@ -1006,20 +1027,20 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { res.to_rvalue() } else { + assert!(!signed); // Algorithm from: http://locklessinc.com/articles/sat_arithmetic/ - let res = lhs + rhs; - let res_type = res.get_type(); - let cond = self.context.new_comparison(None, ComparisonOp::LessThan, res, lhs); - let value = self.context.new_unary_op(None, UnaryOp::Minus, res_type, self.context.new_cast(None, cond, res_type)); - res | value + let res = self.gcc_add(lhs, rhs); + let cond = self.gcc_icmp(IntPredicate::IntULT, res, lhs); + let value = self.gcc_neg(self.gcc_int_cast(cond, result_type)); + self.gcc_or(res, value) } } // Algorithm from: https://locklessinc.com/articles/sat_arithmetic/ fn saturating_sub(&mut self, lhs: RValue<'gcc>, rhs: RValue<'gcc>, signed: bool, width: u64) -> RValue<'gcc> { + let result_type = lhs.get_type(); if signed { - // Also based on algorithm from: https://stackoverflow.com/a/56531252/389119 - let result_type = lhs.get_type(); + // Based on algorithm from: https://stackoverflow.com/a/56531252/389119 let func = self.current_func.borrow().expect("func"); let res = func.new_local(None, result_type, "saturating_diff"); let supports_native_type = self.is_native_int_type(result_type); @@ -1059,6 +1080,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let then_block = func.new_block("then"); let after_block = func.new_block("after"); + // Return `result_type`'s maximum or minimum value on overflow // NOTE: convert the type to unsigned to have an unsigned shift. let unsigned_type = result_type.to_unsigned(&self.cx); let shifted = self.gcc_lshr(self.gcc_int_cast(lhs, unsigned_type), self.gcc_int(unsigned_type, width as i64 - 1)); @@ -1076,11 +1098,11 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { res.to_rvalue() } else { - let res = lhs - rhs; - let comparison = self.context.new_comparison(None, ComparisonOp::LessThanEquals, res, lhs); - let comparison = self.context.new_cast(None, comparison, lhs.get_type()); - let unary_op = self.context.new_unary_op(None, UnaryOp::Minus, comparison.get_type(), comparison); - self.and(res, unary_op) + assert!(!signed); + let res = self.gcc_sub(lhs, rhs); + let comparison = self.gcc_icmp(IntPredicate::IntULE, res, lhs); + let value = self.gcc_neg(self.gcc_int_cast(comparison, result_type)); + self.gcc_and(res, value) } } } From 5061e3ad163a75e81ed7b69e2113b5db135bc51a Mon Sep 17 00:00:00 2001 From: yvt Date: Wed, 6 Apr 2022 21:49:54 +0900 Subject: [PATCH 062/356] Remove redundant assertions --- src/intrinsic/mod.rs | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index 84395e967636..d885bc8bf1fe 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -1027,7 +1027,6 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { res.to_rvalue() } else { - assert!(!signed); // Algorithm from: http://locklessinc.com/articles/sat_arithmetic/ let res = self.gcc_add(lhs, rhs); let cond = self.gcc_icmp(IntPredicate::IntULT, res, lhs); @@ -1098,7 +1097,6 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { res.to_rvalue() } else { - assert!(!signed); let res = self.gcc_sub(lhs, rhs); let comparison = self.gcc_icmp(IntPredicate::IntULE, res, lhs); let value = self.gcc_neg(self.gcc_int_cast(comparison, result_type)); From a7a09d556ab222f3b24d76defe1d2b2f99aa2c6f Mon Sep 17 00:00:00 2001 From: yvt Date: Wed, 6 Apr 2022 22:07:02 +0900 Subject: [PATCH 063/356] Wrap numbers with `black_box` in-line, remove `one` --- tests/run/int.rs | 323 +++++++++++++++++++++++------------------------ 1 file changed, 159 insertions(+), 164 deletions(-) diff --git a/tests/run/int.rs b/tests/run/int.rs index 8d2db9096f73..2b90e4ae8d82 100644 --- a/tests/run/int.rs +++ b/tests/run/int.rs @@ -3,7 +3,7 @@ // Run-time: // status: 0 -#![feature(bench_black_box, core_intrinsics, start)] +#![feature(bench_black_box, const_black_box, core_intrinsics, start)] #![no_std] @@ -18,23 +18,18 @@ fn panic_handler(_: &core::panic::PanicInfo) -> ! { #[start] fn main(_argc: isize, _argv: *const *const u8) -> isize { - let one: isize = core::hint::black_box(1); + use core::hint::black_box; macro_rules! check { ($ty:ty, $expr:expr) => { { - const EXPECTED: $ty = { - #[allow(non_upper_case_globals)] - #[allow(dead_code)] - const one: isize = 1; - $expr - }; + const EXPECTED: $ty = $expr; assert_eq!($expr, EXPECTED); } }; } - check!(u32, (2220326408_u32 + one as u32) >> (32 - 6)); + check!(u32, (2220326408_u32 + black_box(1)) >> (32 - 6)); /// Generate `check!` tests for integer types at least as wide as 128 bits. macro_rules! check_ops128 { @@ -42,15 +37,15 @@ fn main(_argc: isize, _argv: *const *const u8) -> isize { check_ops64!(); // Shifts. - check!(T, VAL1 << (one + 63) as T); - check!(T, VAL1 << (one + 80) as T); - check!(T, VAL3 << (one + 62) as T); - check!(T, VAL3 << (one + 63) as T); + check!(T, VAL1 << black_box(64)); + check!(T, VAL1 << black_box(81)); + check!(T, VAL3 << black_box(63)); + check!(T, VAL3 << black_box(64)); - check!(T, VAL1 >> (one + 63) as T); - check!(T, VAL2 >> (one + 63) as T); - check!(T, VAL3 >> (one + 63) as T); - check!(T, VAL3 >> (one + 80) as T); + check!(T, VAL1 >> black_box(64)); + check!(T, VAL2 >> black_box(64)); + check!(T, VAL3 >> black_box(64)); + check!(T, VAL3 >> black_box(81)); }; } @@ -60,29 +55,29 @@ fn main(_argc: isize, _argv: *const *const u8) -> isize { check_ops32!(); // Shifts. - check!(T, VAL2 << (one + 32) as T); - check!(T, VAL2 << (one + 48) as T); - check!(T, VAL2 << (one + 60) as T); - check!(T, VAL2 << (one + 62) as T); + check!(T, VAL2 << black_box(33)); + check!(T, VAL2 << black_box(49)); + check!(T, VAL2 << black_box(61)); + check!(T, VAL2 << black_box(63)); - check!(T, VAL3 << (one + 32) as T); - check!(T, VAL3 << (one + 48) as T); - check!(T, VAL3 << (one + 60) as T); + check!(T, VAL3 << black_box(33)); + check!(T, VAL3 << black_box(49)); + check!(T, VAL3 << black_box(61)); - check!(T, VAL1 >> (one + 32) as T); - check!(T, VAL1 >> (one + 48) as T); - check!(T, VAL1 >> (one + 60) as T); - check!(T, VAL1 >> (one + 62) as T); + check!(T, VAL1 >> black_box(33)); + check!(T, VAL1 >> black_box(49)); + check!(T, VAL1 >> black_box(61)); + check!(T, VAL1 >> black_box(63)); - check!(T, VAL2 >> (one + 32) as T); - check!(T, VAL2 >> (one + 48) as T); - check!(T, VAL2 >> (one + 60) as T); - check!(T, VAL2 >> (one + 62) as T); + check!(T, VAL2 >> black_box(33)); + check!(T, VAL2 >> black_box(49)); + check!(T, VAL2 >> black_box(61)); + check!(T, VAL2 >> black_box(63)); - check!(T, VAL3 >> (one + 32) as T); - check!(T, VAL3 >> (one + 48) as T); - check!(T, VAL3 >> (one + 60) as T); - check!(T, VAL3 >> (one + 62) as T); + check!(T, VAL3 >> black_box(33)); + check!(T, VAL3 >> black_box(49)); + check!(T, VAL3 >> black_box(61)); + check!(T, VAL3 >> black_box(63)); }; } @@ -90,195 +85,195 @@ fn main(_argc: isize, _argv: *const *const u8) -> isize { macro_rules! check_ops32 { () => { // Shifts. - check!(T, VAL2 << one as T); - check!(T, VAL2 << (one as T - 1)); + check!(T, VAL2 << black_box(1)); + check!(T, VAL2 << black_box(0)); - check!(T, VAL3 << one as T); - check!(T, VAL3 << (one as T - 1)); + check!(T, VAL3 << black_box(1)); + check!(T, VAL3 << black_box(0)); - check!(T, VAL1.wrapping_shl(one as u32 - 1)); - check!(T, VAL1.wrapping_shl(one as u32)); - check!(T, VAL1.wrapping_shl((one + 32) as u32)); - check!(T, VAL1.wrapping_shl((one + 48) as u32)); - check!(T, VAL1.wrapping_shl((one + 60) as u32)); - check!(T, VAL1.wrapping_shl((one + 62) as u32)); - check!(T, VAL1.wrapping_shl((one + 63) as u32)); - check!(T, VAL1.wrapping_shl((one + 80) as u32)); + check!(T, VAL1.wrapping_shl(black_box(0))); + check!(T, VAL1.wrapping_shl(black_box(1))); + check!(T, VAL1.wrapping_shl(black_box(33))); + check!(T, VAL1.wrapping_shl(black_box(49))); + check!(T, VAL1.wrapping_shl(black_box(61))); + check!(T, VAL1.wrapping_shl(black_box(63))); + check!(T, VAL1.wrapping_shl(black_box(64))); + check!(T, VAL1.wrapping_shl(black_box(81))); - check!(Option, VAL1.checked_shl(one as u32 - 1)); - check!(Option, VAL1.checked_shl(one as u32)); - check!(Option, VAL1.checked_shl((one + 32) as u32)); - check!(Option, VAL1.checked_shl((one + 48) as u32)); - check!(Option, VAL1.checked_shl((one + 60) as u32)); - check!(Option, VAL1.checked_shl((one + 62) as u32)); - check!(Option, VAL1.checked_shl((one + 63) as u32)); - check!(Option, VAL1.checked_shl((one + 80) as u32)); + check!(Option, VAL1.checked_shl(black_box(0))); + check!(Option, VAL1.checked_shl(black_box(1))); + check!(Option, VAL1.checked_shl(black_box(33))); + check!(Option, VAL1.checked_shl(black_box(49))); + check!(Option, VAL1.checked_shl(black_box(61))); + check!(Option, VAL1.checked_shl(black_box(63))); + check!(Option, VAL1.checked_shl(black_box(64))); + check!(Option, VAL1.checked_shl(black_box(81))); - check!(T, VAL1 >> (one as T - 1)); - check!(T, VAL1 >> one as T); + check!(T, VAL1 >> black_box(0)); + check!(T, VAL1 >> black_box(1)); - check!(T, VAL2 >> one as T); - check!(T, VAL2 >> (one as T - 1)); + check!(T, VAL2 >> black_box(1)); + check!(T, VAL2 >> black_box(0)); - check!(T, VAL3 >> (one as T - 1)); - check!(T, VAL3 >> one as T); + check!(T, VAL3 >> black_box(0)); + check!(T, VAL3 >> black_box(1)); - check!(T, VAL1.wrapping_shr(one as u32 - 1)); - check!(T, VAL1.wrapping_shr(one as u32)); - check!(T, VAL1.wrapping_shr((one + 32) as u32)); - check!(T, VAL1.wrapping_shr((one + 48) as u32)); - check!(T, VAL1.wrapping_shr((one + 60) as u32)); - check!(T, VAL1.wrapping_shr((one + 62) as u32)); - check!(T, VAL1.wrapping_shr((one + 63) as u32)); - check!(T, VAL1.wrapping_shr((one + 80) as u32)); + check!(T, VAL1.wrapping_shr(black_box(0))); + check!(T, VAL1.wrapping_shr(black_box(1))); + check!(T, VAL1.wrapping_shr(black_box(33))); + check!(T, VAL1.wrapping_shr(black_box(49))); + check!(T, VAL1.wrapping_shr(black_box(61))); + check!(T, VAL1.wrapping_shr(black_box(63))); + check!(T, VAL1.wrapping_shr(black_box(64))); + check!(T, VAL1.wrapping_shr(black_box(81))); - check!(Option, VAL1.checked_shr(one as u32 - 1)); - check!(Option, VAL1.checked_shr(one as u32)); - check!(Option, VAL1.checked_shr((one + 32) as u32)); - check!(Option, VAL1.checked_shr((one + 48) as u32)); - check!(Option, VAL1.checked_shr((one + 60) as u32)); - check!(Option, VAL1.checked_shr((one + 62) as u32)); - check!(Option, VAL1.checked_shr((one + 63) as u32)); - check!(Option, VAL1.checked_shr((one + 80) as u32)); + check!(Option, VAL1.checked_shr(black_box(0))); + check!(Option, VAL1.checked_shr(black_box(1))); + check!(Option, VAL1.checked_shr(black_box(33))); + check!(Option, VAL1.checked_shr(black_box(49))); + check!(Option, VAL1.checked_shr(black_box(61))); + check!(Option, VAL1.checked_shr(black_box(63))); + check!(Option, VAL1.checked_shr(black_box(64))); + check!(Option, VAL1.checked_shr(black_box(81))); // Casts - check!(u64, (VAL1 >> one as T) as u64); + check!(u64, (VAL1 >> black_box(1)) as u64); // Addition. - check!(T, VAL1 + one as T); - check!(T, VAL2 + one as T); - check!(T, VAL2 + (VAL2 + one as T) as T); - check!(T, VAL3 + one as T); + check!(T, VAL1 + black_box(1)); + check!(T, VAL2 + black_box(1)); + check!(T, VAL2 + (VAL2 + black_box(1))); + check!(T, VAL3 + black_box(1)); - check!(Option, VAL1.checked_add(one as T)); - check!(Option, VAL2.checked_add(one as T)); - check!(Option, VAL2.checked_add((VAL2 + one as T) as T)); + check!(Option, VAL1.checked_add(black_box(1))); + check!(Option, VAL2.checked_add(black_box(1))); + check!(Option, VAL2.checked_add(VAL2 + black_box(1))); check!(Option, VAL3.checked_add(T::MAX)); check!(Option, VAL3.checked_add(T::MIN)); - check!(T, VAL1.wrapping_add(one as T)); - check!(T, VAL2.wrapping_add(one as T)); - check!(T, VAL2.wrapping_add((VAL2 + one as T) as T)); + check!(T, VAL1.wrapping_add(black_box(1))); + check!(T, VAL2.wrapping_add(black_box(1))); + check!(T, VAL2.wrapping_add(VAL2 + black_box(1))); check!(T, VAL3.wrapping_add(T::MAX)); check!(T, VAL3.wrapping_add(T::MIN)); - check!((T, bool), VAL1.overflowing_add(one as T)); - check!((T, bool), VAL2.overflowing_add(one as T)); - check!((T, bool), VAL2.overflowing_add((VAL2 + one as T) as T)); + check!((T, bool), VAL1.overflowing_add(black_box(1))); + check!((T, bool), VAL2.overflowing_add(black_box(1))); + check!((T, bool), VAL2.overflowing_add(VAL2 + black_box(1))); check!((T, bool), VAL3.overflowing_add(T::MAX)); check!((T, bool), VAL3.overflowing_add(T::MIN)); - check!(T, VAL1.saturating_add(one as T)); - check!(T, VAL2.saturating_add(one as T)); - check!(T, VAL2.saturating_add((VAL2 + one as T) as T)); + check!(T, VAL1.saturating_add(black_box(1))); + check!(T, VAL2.saturating_add(black_box(1))); + check!(T, VAL2.saturating_add(VAL2 + black_box(1))); check!(T, VAL3.saturating_add(T::MAX)); check!(T, VAL3.saturating_add(T::MIN)); // Subtraction - check!(T, VAL1 - one as T); - check!(T, VAL2 - one as T); - check!(T, VAL3 - one as T); + check!(T, VAL1 - black_box(1)); + check!(T, VAL2 - black_box(1)); + check!(T, VAL3 - black_box(1)); - check!(Option, VAL1.checked_sub(one as T)); - check!(Option, VAL2.checked_sub(one as T)); - check!(Option, VAL2.checked_sub((VAL2 + one as T) as T)); + check!(Option, VAL1.checked_sub(black_box(1))); + check!(Option, VAL2.checked_sub(black_box(1))); + check!(Option, VAL2.checked_sub(VAL2 + black_box(1))); check!(Option, VAL3.checked_sub(T::MAX)); check!(Option, VAL3.checked_sub(T::MIN)); - check!(T, VAL1.wrapping_sub(one as T)); - check!(T, VAL2.wrapping_sub(one as T)); - check!(T, VAL2.wrapping_sub((VAL2 + one as T) as T)); + check!(T, VAL1.wrapping_sub(black_box(1))); + check!(T, VAL2.wrapping_sub(black_box(1))); + check!(T, VAL2.wrapping_sub(VAL2 + black_box(1))); check!(T, VAL3.wrapping_sub(T::MAX)); check!(T, VAL3.wrapping_sub(T::MIN)); - check!((T, bool), VAL1.overflowing_sub(one as T)); - check!((T, bool), VAL2.overflowing_sub(one as T)); - check!((T, bool), VAL2.overflowing_sub((VAL2 + one as T) as T)); + check!((T, bool), VAL1.overflowing_sub(black_box(1))); + check!((T, bool), VAL2.overflowing_sub(black_box(1))); + check!((T, bool), VAL2.overflowing_sub(VAL2 + black_box(1))); check!((T, bool), VAL3.overflowing_sub(T::MAX)); check!((T, bool), VAL3.overflowing_sub(T::MIN)); - check!(T, VAL1.saturating_sub(one as T)); - check!(T, VAL2.saturating_sub(one as T)); - check!(T, VAL2.saturating_sub((VAL2 + one as T) as T)); + check!(T, VAL1.saturating_sub(black_box(1))); + check!(T, VAL2.saturating_sub(black_box(1))); + check!(T, VAL2.saturating_sub(VAL2 + black_box(1))); check!(T, VAL3.saturating_sub(T::MAX)); check!(T, VAL3.saturating_sub(T::MIN)); // Multiplication - check!(T, VAL1 * (one + 1) as T); - check!(T, VAL1 * (one as T + VAL2)); - check!(T, VAL2 * (one + 1) as T); - check!(T, VAL2 * (one as T + VAL2)); - check!(T, VAL3 * one as T); - check!(T, VAL4 * (one + 1) as T); - check!(T, VAL5 * (one + 1) as T); + check!(T, VAL1 * black_box(2)); + check!(T, VAL1 * (black_box(1) + VAL2)); + check!(T, VAL2 * black_box(2)); + check!(T, VAL2 * (black_box(1) + VAL2)); + check!(T, VAL3 * black_box(1)); + check!(T, VAL4 * black_box(2)); + check!(T, VAL5 * black_box(2)); - check!(Option, VAL1.checked_mul((one + 1) as T)); - check!(Option, VAL1.checked_mul((one as T + VAL2))); + check!(Option, VAL1.checked_mul(black_box(2))); + check!(Option, VAL1.checked_mul(black_box(1) + VAL2)); check!(Option, VAL3.checked_mul(VAL3)); - check!(Option, VAL4.checked_mul((one + 1) as T)); - check!(Option, VAL5.checked_mul((one + 1) as T)); + check!(Option, VAL4.checked_mul(black_box(2))); + check!(Option, VAL5.checked_mul(black_box(2))); - check!(T, VAL1.wrapping_mul((one + 1) as T)); - check!(T, VAL1.wrapping_mul((one as T + VAL2))); + check!(T, VAL1.wrapping_mul(black_box(2))); + check!(T, VAL1.wrapping_mul((black_box(1) + VAL2))); check!(T, VAL3.wrapping_mul(VAL3)); - check!(T, VAL4.wrapping_mul((one + 1) as T)); - check!(T, VAL5.wrapping_mul((one + 1) as T)); + check!(T, VAL4.wrapping_mul(black_box(2))); + check!(T, VAL5.wrapping_mul(black_box(2))); - check!((T, bool), VAL1.overflowing_mul((one + 1) as T)); - check!((T, bool), VAL1.overflowing_mul((one as T + VAL2))); + check!((T, bool), VAL1.overflowing_mul(black_box(2))); + check!((T, bool), VAL1.overflowing_mul(black_box(1) + VAL2)); check!((T, bool), VAL3.overflowing_mul(VAL3)); - check!((T, bool), VAL4.overflowing_mul((one + 1) as T)); - check!((T, bool), VAL5.overflowing_mul((one + 1) as T)); + check!((T, bool), VAL4.overflowing_mul(black_box(2))); + check!((T, bool), VAL5.overflowing_mul(black_box(2))); - check!(T, VAL1.saturating_mul((one + 1) as T)); - check!(T, VAL1.saturating_mul((one as T + VAL2))); + check!(T, VAL1.saturating_mul(black_box(2))); + check!(T, VAL1.saturating_mul(black_box(1) + VAL2)); check!(T, VAL3.saturating_mul(VAL3)); - check!(T, VAL4.saturating_mul((one + 1) as T)); - check!(T, VAL5.saturating_mul((one + 1) as T)); + check!(T, VAL4.saturating_mul(black_box(2))); + check!(T, VAL5.saturating_mul(black_box(2))); // Division. - check!(T, VAL1 / (one + 1) as T); - check!(T, VAL1 / (one + 2) as T); + check!(T, VAL1 / black_box(2)); + check!(T, VAL1 / black_box(3)); - check!(T, VAL2 / (one + 1) as T); - check!(T, VAL2 / (one + 2) as T); + check!(T, VAL2 / black_box(2)); + check!(T, VAL2 / black_box(3)); - check!(T, VAL3 / (one + 1) as T); - check!(T, VAL3 / (one + 2) as T); - check!(T, VAL3 / (one as T + VAL4)); - check!(T, VAL3 / (one as T + VAL2)); + check!(T, VAL3 / black_box(2)); + check!(T, VAL3 / black_box(3)); + check!(T, VAL3 / (black_box(1) + VAL4)); + check!(T, VAL3 / (black_box(1) + VAL2)); - check!(T, VAL4 / (one + 1) as T); - check!(T, VAL4 / (one + 2) as T); + check!(T, VAL4 / black_box(2)); + check!(T, VAL4 / black_box(3)); - check!(Option, VAL1.checked_div((one + 1) as T)); - check!(Option, VAL1.checked_div((one as T + VAL2))); + check!(Option, VAL1.checked_div(black_box(2))); + check!(Option, VAL1.checked_div(black_box(1) + VAL2)); check!(Option, VAL3.checked_div(VAL3)); - check!(Option, VAL4.checked_div((one + 1) as T)); - check!(Option, VAL5.checked_div((one + 1) as T)); - check!(Option, (T::MIN).checked_div((0 as T).wrapping_sub(one as T))); - check!(Option, VAL5.checked_div((one - 1) as T)); // var5 / 0 + check!(Option, VAL4.checked_div(black_box(2))); + check!(Option, VAL5.checked_div(black_box(2))); + check!(Option, (T::MIN).checked_div(black_box(0 as T).wrapping_sub(1))); + check!(Option, VAL5.checked_div(black_box(0))); // var5 / 0 - check!(T, VAL1.wrapping_div((one + 1) as T)); - check!(T, VAL1.wrapping_div((one as T + VAL2))); + check!(T, VAL1.wrapping_div(black_box(2))); + check!(T, VAL1.wrapping_div(black_box(1) + VAL2)); check!(T, VAL3.wrapping_div(VAL3)); - check!(T, VAL4.wrapping_div((one + 1) as T)); - check!(T, VAL5.wrapping_div((one + 1) as T)); - check!(T, (T::MIN).wrapping_div((0 as T).wrapping_sub(one as T))); + check!(T, VAL4.wrapping_div(black_box(2))); + check!(T, VAL5.wrapping_div(black_box(2))); + check!(T, (T::MIN).wrapping_div(black_box(0 as T).wrapping_sub(1))); - check!((T, bool), VAL1.overflowing_div((one + 1) as T)); - check!((T, bool), VAL1.overflowing_div((one as T + VAL2))); + check!((T, bool), VAL1.overflowing_div(black_box(2))); + check!((T, bool), VAL1.overflowing_div(black_box(1) + VAL2)); check!((T, bool), VAL3.overflowing_div(VAL3)); - check!((T, bool), VAL4.overflowing_div((one + 1) as T)); - check!((T, bool), VAL5.overflowing_div((one + 1) as T)); - check!((T, bool), (T::MIN).overflowing_div((0 as T).wrapping_sub(one as T))); + check!((T, bool), VAL4.overflowing_div(black_box(2))); + check!((T, bool), VAL5.overflowing_div(black_box(2))); + check!((T, bool), (T::MIN).overflowing_div(black_box(0 as T).wrapping_sub(1))); - check!(T, VAL1.saturating_div((one + 1) as T)); - check!(T, VAL1.saturating_div((one as T + VAL2))); + check!(T, VAL1.saturating_div(black_box(2))); + check!(T, VAL1.saturating_div((black_box(1) + VAL2))); check!(T, VAL3.saturating_div(VAL3)); - check!(T, VAL4.saturating_div((one + 1) as T)); - check!(T, VAL5.saturating_div((one + 1) as T)); - check!(T, (T::MIN).saturating_div((0 as T).wrapping_sub(one as T))); + check!(T, VAL4.saturating_div(black_box(2))); + check!(T, VAL5.saturating_div(black_box(2))); + check!(T, (T::MIN).saturating_div((0 as T).wrapping_sub(black_box(1)))); }; } From 4d7de811991aef0484ac0c31fcdfef9a97d91fbb Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Wed, 13 Apr 2022 17:51:39 -0400 Subject: [PATCH 064/356] Add feature for future libgccjit 12 release --- .github/workflows/ci.yml | 24 +++++++- Cargo.lock | 4 +- Cargo.toml | 4 ++ build.sh | 23 ++++--- example/std_example.rs | 14 ++++- src/builder.rs | 15 +++++ src/intrinsic/llvm.rs | 14 +++++ src/intrinsic/simd.rs | 4 ++ src/lib.rs | 11 +++- src/type_.rs | 2 + src/type_of.rs | 2 + test.sh | 129 ++++++++++++++++++++++++++------------- 12 files changed, 186 insertions(+), 60 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 337837c40bfb..8ebdabe82610 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -11,7 +11,7 @@ jobs: strategy: fail-fast: false matrix: - libgccjit_version: ["libgccjit.so", "libgccjit_without_int128.so"] + libgccjit_version: ["libgccjit.so", "libgccjit_without_int128.so", "libgccjit12.so"] steps: - uses: actions/checkout@v2 @@ -78,12 +78,21 @@ jobs: key: ${{ runner.os }}-cargo-build-target-${{ hashFiles('rust-toolchain') }} - name: Build + if: matrix.libgccjit_version != 'libgccjit12.so' run: | ./prepare_build.sh ./build.sh cargo test ./clean_all.sh + - name: Build + if: matrix.libgccjit_version == 'libgccjit12.so' + run: | + ./prepare_build.sh + ./build.sh --no-default-features + cargo test --no-default-features + ./clean_all.sh + - name: Prepare dependencies run: | git config --global user.email "user@example.com" @@ -98,6 +107,7 @@ jobs: args: --release - name: Test + if: matrix.libgccjit_version != 'libgccjit12.so' run: | # Enable backtraces for easier debugging export RUST_BACKTRACE=1 @@ -107,3 +117,15 @@ jobs: export RUN_RUNS=2 ./test.sh --release + + - name: Test + if: matrix.libgccjit_version == 'libgccjit12.so' + run: | + # Enable backtraces for easier debugging + export RUST_BACKTRACE=1 + + # Reduce amount of benchmark runs as they are slow + export COMPILE_RUNS=2 + export RUN_RUNS=2 + + ./test.sh --release --no-default-features diff --git a/Cargo.lock b/Cargo.lock index f66c98742695..c5315e2392ef 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -41,7 +41,7 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" -source = "git+https://github.com/antoyo/gccjit.rs#f24e1f49d99430941d8a747275b41c9a7930e049" +source = "git+https://github.com/antoyo/gccjit.rs#6c2af0cf733a26740f01a7c679afc20431165a54" dependencies = [ "gccjit_sys", ] @@ -49,7 +49,7 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" -source = "git+https://github.com/antoyo/gccjit.rs#f24e1f49d99430941d8a747275b41c9a7930e049" +source = "git+https://github.com/antoyo/gccjit.rs#6c2af0cf733a26740f01a7c679afc20431165a54" dependencies = [ "libc 0.1.12", ] diff --git a/Cargo.toml b/Cargo.toml index 21f0bfbf69d7..86278b469830 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -13,6 +13,10 @@ name = "lang_tests" path = "tests/lib.rs" harness = false +[features] +default = ["master"] +master = ["gccjit/master"] + [dependencies] gccjit = { git = "https://github.com/antoyo/gccjit.rs" } diff --git a/build.sh b/build.sh index 230ab7b6d42b..44eb240715c7 100755 --- a/build.sh +++ b/build.sh @@ -6,6 +6,8 @@ set -e codegen_channel=debug sysroot_channel=debug +flags= + while [[ $# -gt 0 ]]; do case $1 in --release) @@ -16,6 +18,15 @@ while [[ $# -gt 0 ]]; do sysroot_channel=release shift ;; + --no-default-features) + flags="$flags --no-default-features" + shift + ;; + --features) + shift + flags="$flags --features $1" + shift + ;; *) echo "Unknown option $1" exit 1 @@ -33,21 +44,13 @@ fi export LD_LIBRARY_PATH="$GCC_PATH" export LIBRARY_PATH="$GCC_PATH" -features= - -if [[ "$1" == "--features" ]]; then - shift - features="--features $1" - shift -fi - if [[ "$codegen_channel" == "release" ]]; then export CHANNEL='release' - CARGO_INCREMENTAL=1 cargo rustc --release $features + CARGO_INCREMENTAL=1 cargo rustc --release $flags else echo $LD_LIBRARY_PATH export CHANNEL='debug' - cargo rustc $features + cargo rustc $flags fi source config.sh diff --git a/example/std_example.rs b/example/std_example.rs index 722666f7e166..31069058aea3 100644 --- a/example/std_example.rs +++ b/example/std_example.rs @@ -93,6 +93,7 @@ fn main() { println!("{:?}", std::intrinsics::caller_location()); + #[cfg(feature="master")] unsafe { test_simd(); } @@ -104,6 +105,7 @@ fn main() { println!("End"); } +#[cfg(feature="master")] #[target_feature(enable = "sse2")] unsafe fn test_simd() { let x = _mm_setzero_si128(); @@ -131,6 +133,7 @@ unsafe fn test_simd() { assert_eq!(mask1, 1); } +#[cfg(feature="master")] #[target_feature(enable = "sse2")] unsafe fn test_mm_slli_si128() { #[rustfmt::skip] @@ -158,6 +161,7 @@ unsafe fn test_mm_slli_si128() { } +#[cfg(feature="master")] #[target_feature(enable = "sse2")] unsafe fn test_mm_movemask_epi8() { #[rustfmt::skip] @@ -171,6 +175,7 @@ unsafe fn test_mm_movemask_epi8() { assert_eq!(r, 0b10100100_00100101); } +#[cfg(feature="master")] #[target_feature(enable = "avx2")] unsafe fn test_mm256_movemask_epi8() { let a = _mm256_set1_epi8(-1); @@ -179,6 +184,7 @@ unsafe fn test_mm256_movemask_epi8() { assert_eq!(r, e); } +#[cfg(feature="master")] #[target_feature(enable = "sse2")] unsafe fn test_mm_add_epi8() { let a = _mm_setr_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); @@ -194,6 +200,7 @@ unsafe fn test_mm_add_epi8() { assert_eq_m128i(r, e); } +#[cfg(feature="master")] #[target_feature(enable = "sse2")] unsafe fn test_mm_add_pd() { let a = _mm_setr_pd(1.0, 2.0); @@ -202,12 +209,14 @@ unsafe fn test_mm_add_pd() { assert_eq_m128d(r, _mm_setr_pd(6.0, 12.0)); } +#[cfg(feature="master")] fn assert_eq_m128i(x: std::arch::x86_64::__m128i, y: std::arch::x86_64::__m128i) { unsafe { assert_eq!(std::mem::transmute::<_, [u8; 16]>(x), std::mem::transmute::<_, [u8; 16]>(y)); } } +#[cfg(feature="master")] #[target_feature(enable = "sse2")] pub unsafe fn assert_eq_m128d(a: __m128d, b: __m128d) { if _mm_movemask_pd(_mm_cmpeq_pd(a, b)) != 0b11 { @@ -215,12 +224,14 @@ pub unsafe fn assert_eq_m128d(a: __m128d, b: __m128d) { } } +#[cfg(feature="master")] #[target_feature(enable = "sse2")] unsafe fn test_mm_cvtsi128_si64() { let r = _mm_cvtsi128_si64(std::mem::transmute::<[i64; 2], _>([5, 0])); assert_eq!(r, 5); } +#[cfg(feature="master")] #[target_feature(enable = "sse4.1")] unsafe fn test_mm_cvtepi8_epi16() { let a = _mm_set1_epi8(10); @@ -233,6 +244,7 @@ unsafe fn test_mm_cvtepi8_epi16() { assert_eq_m128i(r, e); } +#[cfg(feature="master")] #[target_feature(enable = "sse4.1")] unsafe fn test_mm_extract_epi8() { #[rustfmt::skip] @@ -246,7 +258,7 @@ unsafe fn test_mm_extract_epi8() { assert_eq!(r2, 3); } -#[cfg(target_arch = "x86_64")] +#[cfg(all(feature="master", target_arch = "x86_64"))] #[target_feature(enable = "sse2")] unsafe fn test_mm_insert_epi16() { let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7); diff --git a/src/builder.rs b/src/builder.rs index a4616d8673ec..6f24abaea8ae 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -301,6 +301,15 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { result.to_rvalue() } else { + #[cfg(not(feature="master"))] + if gcc_func.get_param_count() == 0 { + // FIXME(antoyo): As a temporary workaround for unsupported LLVM intrinsics. + self.block.add_eval(None, self.cx.context.new_call_through_ptr(None, func_ptr, &[])); + } + else { + self.block.add_eval(None, self.cx.context.new_call_through_ptr(None, func_ptr, &args)); + } + #[cfg(feature="master")] self.block.add_eval(None, self.cx.context.new_call_through_ptr(None, func_ptr, &args)); // Return dummy value when not having return value. let result = current_func.new_local(None, self.isize_type, "dummyValueThatShouldNeverBeUsed"); @@ -1287,6 +1296,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { + #[cfg(feature="master")] pub fn shuffle_vector(&mut self, v1: RValue<'gcc>, v2: RValue<'gcc>, mask: RValue<'gcc>) -> RValue<'gcc> { let struct_type = mask.get_type().is_struct().expect("mask of struct type"); @@ -1361,6 +1371,11 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { result } } + + #[cfg(not(feature="master"))] + pub fn shuffle_vector(&mut self, _v1: RValue<'gcc>, _v2: RValue<'gcc>, _mask: RValue<'gcc>) -> RValue<'gcc> { + unimplemented!(); + } } impl<'a, 'gcc, 'tcx> StaticBuilderMethods for Builder<'a, 'gcc, 'tcx> { diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index bc8e99428eda..4b41b0ba6e78 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -2,6 +2,20 @@ use gccjit::Function; use crate::context::CodegenCx; +#[cfg(not(feature="master"))] +pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function<'gcc> { + match name { + "llvm.x86.xgetbv" => { + let gcc_name = "__builtin_trap"; + let func = cx.context.get_builtin_function(gcc_name); + cx.functions.borrow_mut().insert(gcc_name.to_string(), func); + return func; + }, + _ => unimplemented!("unsupported LLVM intrinsic {}", name), + } +} + +#[cfg(feature="master")] pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function<'gcc> { let gcc_name = match name { "llvm.x86.xgetbv" => "__builtin_ia32_xgetbv", diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index b8c6038896d8..f1167bc3a3b6 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -154,6 +154,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, )); } + #[cfg(feature="master")] if name == sym::simd_insert { require!( in_elem == arg_tys[2], @@ -213,6 +214,8 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, // TODO(antoyo): perhaps use __builtin_convertvector for vector casting. return Ok(bx.context.new_bitcast(None, result, vector.get_type())); } + + #[cfg(feature="master")] if name == sym::simd_extract { require!( ret_ty == in_elem, @@ -503,6 +506,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, simd_neg: Int => neg, Float => fneg; } + #[cfg(feature="master")] if name == sym::simd_saturating_add || name == sym::simd_saturating_sub { let lhs = args[0].immediate(); let rhs = args[1].immediate(); diff --git a/src/lib.rs b/src/lib.rs index a8029f0425a4..31d3a5ab299a 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -299,10 +299,17 @@ pub fn target_features(sess: &Session) -> Vec { if sess.is_nightly_build() || gate.is_none() { Some(feature) } else { None } }, ) - .filter(|feature| { + .filter(|_feature| { // TODO(antoyo): implement a way to get enabled feature in libgccjit. // Probably using the equivalent of __builtin_cpu_supports. - feature.contains("sse") || feature.contains("avx") + #[cfg(feature="master")] + { + _feature.contains("sse") || _feature.contains("avx") + } + #[cfg(not(feature="master"))] + { + false + } /* adx, aes, avx, avx2, avx512bf16, avx512bitalg, avx512bw, avx512cd, avx512dq, avx512er, avx512f, avx512gfni, avx512ifma, avx512pf, avx512vaes, avx512vbmi, avx512vbmi2, avx512vl, avx512vnni, avx512vp2intersect, avx512vpclmulqdq, diff --git a/src/type_.rs b/src/type_.rs index d65649ecfa3e..db2b5ea8ab20 100644 --- a/src/type_.rs +++ b/src/type_.rs @@ -125,6 +125,7 @@ impl<'gcc, 'tcx> BaseTypeMethods<'tcx> for CodegenCx<'gcc, 'tcx> { .collect(); let typ = self.context.new_struct_type(None, "struct", &fields).as_type(); if packed { + #[cfg(feature="master")] typ.set_packed(); } self.struct_types.borrow_mut().insert(types, typ); @@ -217,6 +218,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { .collect(); typ.set_fields(None, &fields); if packed { + #[cfg(feature="master")] typ.as_type().set_packed(); } } diff --git a/src/type_of.rs b/src/type_of.rs index c6d6f91a7429..adcae9c16c37 100644 --- a/src/type_of.rs +++ b/src/type_of.rs @@ -25,6 +25,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { } } + #[cfg(feature="master")] pub fn type_int_from_ty(&self, t: ty::IntTy) -> Type<'gcc> { match t { ty::IntTy::Isize => self.type_isize(), @@ -36,6 +37,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { } } + #[cfg(feature="master")] pub fn type_uint_from_ty(&self, t: ty::UintTy) -> Type<'gcc> { match t { ty::UintTy::Usize => self.type_isize(), diff --git a/test.sh b/test.sh index 1d2fbd0a24cf..5a8e4f9c0ad5 100755 --- a/test.sh +++ b/test.sh @@ -14,22 +14,79 @@ fi export LD_LIBRARY_PATH="$GCC_PATH" export LIBRARY_PATH="$GCC_PATH" -features= +flags= +gcc_master_branch=1 +channel="debug" +func=all -if [[ "$1" == "--features" ]]; then - shift - features="--features $1" - shift -fi +while [[ $# -gt 0 ]]; do + case $1 in + --release) + codegen_channel=release + shift + ;; + --release-sysroot) + sysroot_channel=release + shift + ;; + --no-default-features) + gcc_master_branch=0 + flags="$flags --no-default-features" + shift + ;; + --features) + shift + flags="$flags --features $1" + shift + ;; + --release) + channel="release" + shift + ;; + "--test-rustc") + func=test_rustc + shift + ;; -if [[ "$1" == "--release" ]]; then + "--test-libcore") + func=test_libcore + shift + ;; + + "--clean-ui-tests") + func=clean_ui_tests + shift + ;; + + "--std-tests") + func=std_tests + shift + ;; + + "--extended-tests") + func=extended_sysroot_tests + shift + ;; + + "--build-sysroot") + func=build_sysroot + shift + ;; + *) + echo "Unknown option $1" + exit 1 + ;; + esac +done + +if [[ $channel == "release" ]]; then export CHANNEL='release' - CARGO_INCREMENTAL=1 cargo rustc --release $features + CARGO_INCREMENTAL=1 cargo rustc --release $flags shift else echo $LD_LIBRARY_PATH export CHANNEL='debug' - cargo rustc $features + cargo rustc $flags fi if [[ "$1" == "--build" ]]; then @@ -78,7 +135,11 @@ function std_tests() { $RUN_WRAPPER ./target/out/dst_field_align || (echo $?; false) echo "[AOT] std_example" - $RUSTC example/std_example.rs --crate-type bin --target $TARGET_TRIPLE + std_flags="--cfg feature=\"master\"" + if (( $gcc_master_branch == 0 )); then + std_flags="" + fi + $RUSTC example/std_example.rs --crate-type bin --target $TARGET_TRIPLE $std_flags $RUN_WRAPPER ./target/out/std_example --target $TARGET_TRIPLE echo "[AOT] subslice-patterns-const-eval" @@ -122,6 +183,10 @@ function test_libcore() { #hyperfine --runs ${RUN_RUNS:-10} ./target/out/mod_bench{,_inline} ./target/out/mod_bench_llvm_* function extended_sysroot_tests() { + if (( $gcc_master_branch == 0 )); then + return + fi + pushd rand cargo clean echo "[TEST] rust-random/rand" @@ -208,38 +273,14 @@ function clean_ui_tests() { find rust/build/x86_64-unknown-linux-gnu/test/ui/ -name stamp -exec rm -rf {} \; } -case $1 in - "--test-rustc") - test_rustc - ;; +function all() { + clean + mini_tests + build_sysroot + std_tests + test_libcore + extended_sysroot_tests + test_rustc +} - "--test-libcore") - test_libcore - ;; - - "--clean-ui-tests") - clean_ui_tests - ;; - - "--std-tests") - std_tests - ;; - - "--extended-tests") - extended_sysroot_tests - ;; - - "--build-sysroot") - build_sysroot - ;; - - *) - clean - mini_tests - build_sysroot - std_tests - test_libcore - extended_sysroot_tests - test_rustc - ;; -esac +$func From 330127599aae8e75c233bd360b472487ce127bac Mon Sep 17 00:00:00 2001 From: MikaelUrankar Date: Thu, 14 Apr 2022 14:12:06 +0200 Subject: [PATCH 065/356] Don't assume /bin/bash is available on every system. --- build.sh | 2 +- build_sysroot/build_sysroot.sh | 2 +- build_sysroot/prepare_sysroot_src.sh | 2 +- cargo.sh | 2 +- clean_all.sh | 2 +- prepare.sh | 2 +- prepare_build.sh | 2 +- rustup.sh | 2 +- test.sh | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/build.sh b/build.sh index 230ab7b6d42b..ba48c2e41fa3 100755 --- a/build.sh +++ b/build.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash #set -x set -e diff --git a/build_sysroot/build_sysroot.sh b/build_sysroot/build_sysroot.sh index a965ca971a07..f293192a099d 100755 --- a/build_sysroot/build_sysroot.sh +++ b/build_sysroot/build_sysroot.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash # Requires the CHANNEL env var to be set to `debug` or `release.` diff --git a/build_sysroot/prepare_sysroot_src.sh b/build_sysroot/prepare_sysroot_src.sh index 071e7ed1f85d..56768bbf1d01 100755 --- a/build_sysroot/prepare_sysroot_src.sh +++ b/build_sysroot/prepare_sysroot_src.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -e cd $(dirname "$0") diff --git a/cargo.sh b/cargo.sh index e95564dccda0..16e49b20423c 100755 --- a/cargo.sh +++ b/cargo.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash if [ -z $CHANNEL ]; then export CHANNEL='debug' diff --git a/clean_all.sh b/clean_all.sh index a77d1486fe28..efa6454f26de 100755 --- a/clean_all.sh +++ b/clean_all.sh @@ -1,4 +1,4 @@ -#!/bin/bash --verbose +#!/usr/bin/env bash --verbose set -e rm -rf target/ build_sysroot/{sysroot/,sysroot_src/,target/,Cargo.lock} perf.data{,.old} diff --git a/prepare.sh b/prepare.sh index d39f43f5e1b3..42bbc4f23b93 100755 --- a/prepare.sh +++ b/prepare.sh @@ -1,4 +1,4 @@ -#!/bin/bash --verbose +#!/usr/bin/env bash --verbose set -e source prepare_build.sh diff --git a/prepare_build.sh b/prepare_build.sh index 3896775a0b9d..7bd13ef0175b 100755 --- a/prepare_build.sh +++ b/prepare_build.sh @@ -1,4 +1,4 @@ -#!/bin/bash --verbose +#!/usr/bin/env bash --verbose set -e ./build_sysroot/prepare_sysroot_src.sh diff --git a/rustup.sh b/rustup.sh index 01ce5bb78be0..7edb5558604a 100755 --- a/rustup.sh +++ b/rustup.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -e diff --git a/test.sh b/test.sh index 1d2fbd0a24cf..5c5978b0bfc5 100755 --- a/test.sh +++ b/test.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash # TODO(antoyo): rewrite to cargo-make (or just) or something like that to only rebuild the sysroot when needed? From f92779512dd3c4613a7e6d0c9eb578ba5a0ec91c Mon Sep 17 00:00:00 2001 From: Mikael Urankar Date: Fri, 15 Apr 2022 09:58:09 +0200 Subject: [PATCH 066/356] Add set -v as we can't pass command line argument with /usr/bin/env --- clean_all.sh | 3 ++- prepare.sh | 3 ++- prepare_build.sh | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/clean_all.sh b/clean_all.sh index efa6454f26de..782bd3e5058c 100755 --- a/clean_all.sh +++ b/clean_all.sh @@ -1,5 +1,6 @@ -#!/usr/bin/env bash --verbose +#!/usr/bin/env bash set -e +set -v rm -rf target/ build_sysroot/{sysroot/,sysroot_src/,target/,Cargo.lock} perf.data{,.old} rm -rf regex/ simple-raytracer/ diff --git a/prepare.sh b/prepare.sh index 42bbc4f23b93..e98f24c6e128 100755 --- a/prepare.sh +++ b/prepare.sh @@ -1,5 +1,6 @@ -#!/usr/bin/env bash --verbose +#!/usr/bin/env bash set -e +set -v source prepare_build.sh diff --git a/prepare_build.sh b/prepare_build.sh index 7bd13ef0175b..8194360da4ba 100755 --- a/prepare_build.sh +++ b/prepare_build.sh @@ -1,4 +1,5 @@ -#!/usr/bin/env bash --verbose +#!/usr/bin/env bash set -e +set -v ./build_sysroot/prepare_sysroot_src.sh From 889c402258e063c6ad4db9a340cbd78f8e5d668c Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 23 Apr 2022 10:48:12 -0400 Subject: [PATCH 067/356] Fix test.sh --build --- test.sh | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/test.sh b/test.sh index 897649e7adb7..8b390f95a4b9 100755 --- a/test.sh +++ b/test.sh @@ -18,6 +18,7 @@ flags= gcc_master_branch=1 channel="debug" func=all +build_only=0 while [[ $# -gt 0 ]]; do case $1 in @@ -72,6 +73,10 @@ while [[ $# -gt 0 ]]; do func=build_sysroot shift ;; + "--build") + build_only=1 + shift + ;; *) echo "Unknown option $1" exit 1 @@ -89,7 +94,7 @@ else cargo rustc $flags fi -if [[ "$1" == "--build" ]]; then +if (( $build_only == 1 )); then exit fi From a0742bdd063192bb6af37d9bdcac4a43b09fb975 Mon Sep 17 00:00:00 2001 From: yvt Date: Sun, 27 Mar 2022 20:48:33 +0900 Subject: [PATCH 068/356] Don't emit `.intel_syntax` for non-x86 targets --- src/asm.rs | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/src/asm.rs b/src/asm.rs index 8a74c4c07e0c..2d41fe425844 100644 --- a/src/asm.rs +++ b/src/asm.rs @@ -116,7 +116,6 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { let asm_arch = self.tcx.sess.asm_arch.unwrap(); let is_x86 = matches!(asm_arch, InlineAsmArch::X86 | InlineAsmArch::X86_64); let att_dialect = is_x86 && options.contains(InlineAsmOptions::ATT_SYNTAX); - let intel_dialect = is_x86 && !options.contains(InlineAsmOptions::ATT_SYNTAX); // GCC index of an output operand equals its position in the array let mut outputs = vec![]; @@ -354,7 +353,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { // 3. Build the template string let mut template_str = String::with_capacity(estimate_template_length(template, constants_len, att_dialect)); - if !intel_dialect { + if att_dialect { template_str.push_str(ATT_SYNTAX_INS); } @@ -436,7 +435,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { } } - if !intel_dialect { + if att_dialect { template_str.push_str(INTEL_SYNTAX_INS); } @@ -661,8 +660,8 @@ impl<'gcc, 'tcx> AsmMethods for CodegenCx<'gcc, 'tcx> { let asm_arch = self.tcx.sess.asm_arch.unwrap(); // Default to Intel syntax on x86 - let intel_syntax = matches!(asm_arch, InlineAsmArch::X86 | InlineAsmArch::X86_64) - && !options.contains(InlineAsmOptions::ATT_SYNTAX); + let att_dialect = matches!(asm_arch, InlineAsmArch::X86 | InlineAsmArch::X86_64) + && options.contains(InlineAsmOptions::ATT_SYNTAX); // Build the template string let mut template_str = String::new(); @@ -696,11 +695,11 @@ impl<'gcc, 'tcx> AsmMethods for CodegenCx<'gcc, 'tcx> { } let template_str = - if intel_syntax { - format!("{}\n\t.intel_syntax noprefix", template_str) + if att_dialect { + format!(".att_syntax\n\t{}\n\t.intel_syntax noprefix", template_str) } else { - format!(".att_syntax\n\t{}\n\t.intel_syntax noprefix", template_str) + template_str }; // NOTE: seems like gcc will put the asm in the wrong section, so set it to .text manually. let template_str = format!(".pushsection .text\n{}\n.popsection", template_str); From 5d25b8fc45f66cdd1b19c87cce38eda86141dcf8 Mon Sep 17 00:00:00 2001 From: yvt Date: Sat, 23 Apr 2022 23:39:27 +0900 Subject: [PATCH 069/356] Convert inline assembly `sym` operands into GCC input operands This commit updates `::codegen_inline_asm` to convert `sym` operands into `"X" (&func_or_static)` input operands to indicate the dependency on the referenced symbols and prevent them from being eliminated. We follow the suit of the LLVM codegen with a mixture of its differing techniques for `asm!` and `global_asm!`. The codegen module generates input operands for the `sym` operands (as in `asm!` in cg_llvm). However, the codegen module replaces all placeholders with mangled symbol names before passing the assembly template string to the backend (as in `global_asm!` in cg_llvm), which means these input operands are never referenced in the final assembly template string. Unlike the LLVM codegen, the input operand constraint must be `X` instead of `s`. If the `s` constraint is used, GCC will employ checks to make sure that the operand can really be represented by a simple symbolic constant, thus rejecting symbols requiring GOT, etc. to resolve. Such checks are unnecessary for Rust `sym` as it's up to programmers to handle such complex cases, e.g., by manually appending GOT addressing modifiers to the substituted symbol names. Using the `X` constraint doesn't seem to generate any extra code, so this will not compromise the property of naked functions. --- src/asm.rs | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/src/asm.rs b/src/asm.rs index 8a74c4c07e0c..053a6c595e97 100644 --- a/src/asm.rs +++ b/src/asm.rs @@ -13,6 +13,7 @@ use std::borrow::Cow; use crate::builder::Builder; use crate::context::CodegenCx; use crate::type_of::LayoutGccExt; +use crate::callee::get_fn; // Rust asm! and GCC Extended Asm semantics differ substantially. @@ -343,9 +344,24 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { // processed in the previous pass } - InlineAsmOperandRef::Const { .. } - | InlineAsmOperandRef::SymFn { .. } - | InlineAsmOperandRef::SymStatic { .. } => { + InlineAsmOperandRef::SymFn { instance } => { + inputs.push(AsmInOperand { + constraint: "X".into(), + rust_idx, + val: self.cx.rvalue_as_function(get_fn(self.cx, instance)) + .get_address(None), + }); + } + + InlineAsmOperandRef::SymStatic { def_id } => { + inputs.push(AsmInOperand { + constraint: "X".into(), + rust_idx, + val: self.cx.get_static(def_id).get_address(None), + }); + } + + InlineAsmOperandRef::Const { .. } => { // processed in the previous pass } } From 63ffdfdd1776afa2e82bbd3d2ff8ff7b7f0d5b67 Mon Sep 17 00:00:00 2001 From: yvt Date: Mon, 25 Apr 2022 21:19:42 +0900 Subject: [PATCH 070/356] Add compilation tests with optimization enabled Introduces a new variant of `tests/lib.rs` that compiles the source files in `tests/run` with `-Copt-level=3`. --- Cargo.toml | 8 ++++++-- tests/{lib.rs => lang_tests_common.rs} | 20 +++++++++++++++++++- tests/lang_tests_debug.rs | 5 +++++ tests/lang_tests_release.rs | 5 +++++ tests/run/int_overflow.rs | 17 ++++++++++++++--- 5 files changed, 49 insertions(+), 6 deletions(-) rename tests/{lib.rs => lang_tests_common.rs} (77%) create mode 100644 tests/lang_tests_debug.rs create mode 100644 tests/lang_tests_release.rs diff --git a/Cargo.toml b/Cargo.toml index 86278b469830..211d19a8dc89 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -9,8 +9,12 @@ license = "MIT OR Apache-2.0" crate-type = ["dylib"] [[test]] -name = "lang_tests" -path = "tests/lib.rs" +name = "lang_tests_debug" +path = "tests/lang_tests_debug.rs" +harness = false +[[test]] +name = "lang_tests_release" +path = "tests/lang_tests_release.rs" harness = false [features] diff --git a/tests/lib.rs b/tests/lang_tests_common.rs similarity index 77% rename from tests/lib.rs rename to tests/lang_tests_common.rs index 8ee35b30bc8e..8e378177e245 100644 --- a/tests/lib.rs +++ b/tests/lang_tests_common.rs @@ -1,3 +1,4 @@ +//! The common code for `tests/lang_tests_*.rs` use std::{ env::{self, current_dir}, path::PathBuf, @@ -7,7 +8,15 @@ use std::{ use lang_tester::LangTester; use tempfile::TempDir; -fn main() { +/// Controls the compile options (e.g., optimization level) used to compile +/// test code. +#[allow(dead_code)] // Each test crate picks one variant +pub enum Profile { + Debug, + Release, +} + +pub fn main_inner(profile: Profile) { let tempdir = TempDir::new().expect("temp dir"); let current_dir = current_dir().expect("current dir"); let current_dir = current_dir.to_str().expect("current dir").to_string(); @@ -42,6 +51,15 @@ fn main() { "-o", exe.to_str().expect("to_str"), path.to_str().expect("to_str"), ]); + match profile { + Profile::Debug => {} + Profile::Release => { + compiler.args(&[ + "-C", "opt-level=3", + "-C", "lto=no", + ]); + } + } // Test command 2: run `tempdir/x`. let runtime = Command::new(exe); vec![("Compiler", compiler), ("Run-time", runtime)] diff --git a/tests/lang_tests_debug.rs b/tests/lang_tests_debug.rs new file mode 100644 index 000000000000..96bd74883ff0 --- /dev/null +++ b/tests/lang_tests_debug.rs @@ -0,0 +1,5 @@ +mod lang_tests_common; + +fn main() { + lang_tests_common::main_inner(lang_tests_common::Profile::Debug); +} diff --git a/tests/lang_tests_release.rs b/tests/lang_tests_release.rs new file mode 100644 index 000000000000..35d5d60c33ee --- /dev/null +++ b/tests/lang_tests_release.rs @@ -0,0 +1,5 @@ +mod lang_tests_common; + +fn main() { + lang_tests_common::main_inner(lang_tests_common::Profile::Release); +} diff --git a/tests/run/int_overflow.rs b/tests/run/int_overflow.rs index 6477b8398280..ea2c5add962a 100644 --- a/tests/run/int_overflow.rs +++ b/tests/run/int_overflow.rs @@ -1,7 +1,7 @@ // Compiler: // // Run-time: -// stdout: Panicking +// stdout: Success // status: signal #![allow(unused_attributes)] @@ -64,7 +64,9 @@ mod intrinsics { #[no_mangle] pub fn panic(_msg: &str) -> ! { unsafe { - libc::puts("Panicking\0" as *const str as *const u8); + // Panicking is expected iff overflow checking is enabled. + #[cfg(debug_assertions)] + libc::puts("Success\0" as *const str as *const u8); libc::fflush(libc::stdout); intrinsics::abort(); } @@ -124,6 +126,15 @@ impl Add for isize { #[start] fn main(mut argc: isize, _argv: *const *const u8) -> isize { let int = 9223372036854775807isize; - let int = int + argc; + let int = int + argc; // overflow + + // If overflow checking is disabled, we should reach here. + #[cfg(not(debug_assertions))] + unsafe { + libc::puts("Success\0" as *const str as *const u8); + libc::fflush(libc::stdout); + intrinsics::abort(); + } + int } From dc8da94d56435f95547ac02cf634dea223668a78 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Fri, 29 Apr 2022 23:17:44 -0400 Subject: [PATCH 071/356] Add rustfmt config to disable formatting --- .rustfmt.toml | 1 + 1 file changed, 1 insertion(+) create mode 100644 .rustfmt.toml diff --git a/.rustfmt.toml b/.rustfmt.toml new file mode 100644 index 000000000000..c7ad93bafe36 --- /dev/null +++ b/.rustfmt.toml @@ -0,0 +1 @@ +disable_all_formatting = true From a225f0a66b83b79e62d679568675adea284bfe21 Mon Sep 17 00:00:00 2001 From: yvt Date: Tue, 3 May 2022 13:53:10 +0900 Subject: [PATCH 072/356] Pass a pointee type to `::load` when calling it ourselves The parameter name isn't very descriptive, but it actually supposed to take a pointee type. When calling it ourselves, we've been passing a *pointer* type, which made it impossible to make any meaningful uses of this parameter in the method implementation. This commit intends to rectify that. --- src/builder.rs | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index 6f24abaea8ae..4cc5eef9dad4 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -652,7 +652,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { unimplemented!(); } - fn load(&mut self, _ty: Type<'gcc>, ptr: RValue<'gcc>, _align: Align) -> RValue<'gcc> { + fn load(&mut self, _pointee_ty: Type<'gcc>, ptr: RValue<'gcc>, _align: Align) -> RValue<'gcc> { // TODO(antoyo): use ty. let block = self.llbb(); let function = block.get_function(); @@ -715,7 +715,11 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { OperandValue::Ref(place.llval, Some(llextra), place.align) } else if place.layout.is_gcc_immediate() { - let load = self.load(place.llval.get_type(), place.llval, place.align); + let load = self.load( + place.layout.gcc_type(self, false), + place.llval, + place.align, + ); if let abi::Abi::Scalar(ref scalar) = place.layout.abi { scalar_load_metadata(self, load, scalar); } @@ -727,7 +731,8 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { let mut load = |i, scalar: &abi::Scalar, align| { let llptr = self.struct_gep(pair_type, place.llval, i as u64); - let load = self.load(llptr.get_type(), llptr, align); + let llty = place.layout.scalar_pair_element_gcc_type(self, i, false); + let load = self.load(llty, llptr, align); scalar_load_metadata(self, load, scalar); if scalar.is_bool() { self.trunc(load, self.type_i1()) } else { load } }; @@ -980,7 +985,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { fn memmove(&mut self, dst: RValue<'gcc>, dst_align: Align, src: RValue<'gcc>, src_align: Align, size: RValue<'gcc>, flags: MemFlags) { if flags.contains(MemFlags::NONTEMPORAL) { // HACK(nox): This is inefficient but there is no nontemporal memmove. - let val = self.load(src.get_type(), src, src_align); + let val = self.load(src.get_type().get_pointee().expect("get_pointee"), src, src_align); let ptr = self.pointercast(dst, self.type_ptr_to(self.val_ty(val))); self.store_with_flags(val, ptr, dst_align, flags); return; From 351c68367425c4e292394ae5c7137b6e45de0916 Mon Sep 17 00:00:00 2001 From: yvt Date: Mon, 2 May 2022 11:00:07 +0900 Subject: [PATCH 073/356] Use the given pointee type in `::load` This commit updates this method implementation to return an `RValue` of the given pointee type. While this parameter does not seem to have much significance at the moment, it will likely become important as cg_llvm and cg_ssa migrate to LLVM opaque pointers and get rid of pointercasts. --- src/builder.rs | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index 4cc5eef9dad4..9a5cf785a1f5 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -652,18 +652,17 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { unimplemented!(); } - fn load(&mut self, _pointee_ty: Type<'gcc>, ptr: RValue<'gcc>, _align: Align) -> RValue<'gcc> { - // TODO(antoyo): use ty. + fn load(&mut self, pointee_ty: Type<'gcc>, ptr: RValue<'gcc>, _align: Align) -> RValue<'gcc> { let block = self.llbb(); let function = block.get_function(); // NOTE: instead of returning the dereference here, we have to assign it to a variable in // the current basic block. Otherwise, it could be used in another basic block, causing a // dereference after a drop, for instance. // TODO(antoyo): handle align of the load instruction. + let ptr = self.context.new_cast(None, ptr, pointee_ty.make_pointer()); let deref = ptr.dereference(None).to_rvalue(); - let value_type = deref.get_type(); unsafe { RETURN_VALUE_COUNT += 1 }; - let loaded_value = function.new_local(None, value_type, &format!("loadedValue{}", unsafe { RETURN_VALUE_COUNT })); + let loaded_value = function.new_local(None, pointee_ty, &format!("loadedValue{}", unsafe { RETURN_VALUE_COUNT })); block.add_assignment(None, loaded_value, deref); loaded_value.to_rvalue() } From af9149a1c6b9f69137951fd385d912a8ddbb7c84 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Tue, 3 May 2022 18:59:04 +0200 Subject: [PATCH 074/356] Add tool to generate intrinsics conversion automatically --- .gitignore | 1 + tools/generate_intrinsics.py | 119 +++++++++++++++++++++++++++++++++++ 2 files changed, 120 insertions(+) create mode 100644 tools/generate_intrinsics.py diff --git a/.gitignore b/.gitignore index 0b611d05b5c9..ba11981a5e3c 100644 --- a/.gitignore +++ b/.gitignore @@ -20,3 +20,4 @@ res test-backend gcc_path benchmarks +tools/llvm-project diff --git a/tools/generate_intrinsics.py b/tools/generate_intrinsics.py new file mode 100644 index 000000000000..587db3679ef4 --- /dev/null +++ b/tools/generate_intrinsics.py @@ -0,0 +1,119 @@ +import os +import re +import sys +import subprocess +from os import walk + + +LLVM_PATH = llvm_path = os.path.join( + os.path.dirname(os.path.abspath(__file__)), + "llvm-project", +) + +def run_command(command, cwd=None): + p = subprocess.Popen(command, cwd=cwd) + if p.wait() != 0: + print("command `{}` failed...".format(" ".join(command))) + sys.exit(1) + + +def clone_llvm_repository(): + if os.path.exists(LLVM_PATH): + while True: + choice = input("There is already a llvm-project folder, do you want to update it? [y/N]") + if choice == "" or choice.lower() == "n": + print("Skipping repository update.") + return + elif choice.lower() == "y": + print("Updating repository...") + run_command(["git", "pull", "origin"], cwd="llvm-project") + return + else: + print("Didn't understand answer...") + print("Cloning LLVM repository...") + run_command(["git", "clone", "https://github.com/llvm/llvm-project", "--depth", "1", LLVM_PATH]) + + +def extract_instrinsics(intrinsics, file): + print("Extracting intrinsics from `{}`...".format(file)) + with open(file, "r", encoding="utf8") as f: + content = f.read() + + lines = content.splitlines() + pos = 0 + current_arch = None + while pos < len(lines): + line = lines[pos].strip() + if line.startswith("let TargetPrefix ="): + current_arch = line.split('"')[1].strip() + if len(current_arch) == 0: + current_arch = None + elif current_arch is None: + pass + elif line == "}": + current_arch = None + elif line.startswith("def "): + content = "" + while not content.endswith(";") and pos < len(lines): + line = lines[pos].split(" // ")[0].strip() + content += line + pos += 1 + entries = re.findall('GCCBuiltin<"(\\w+)">', content) + if len(entries) > 0: + intrinsic = content.split(":")[0].split(" ")[1].strip() + intrinsic = intrinsic.split("_") + if len(intrinsic) < 2 or intrinsic[0] != "int": + continue + intrinsic[0] = "llvm" + intrinsic = ".".join(intrinsic) + if current_arch not in intrinsics: + intrinsics[current_arch] = [] + for entry in entries: + intrinsics[current_arch].append('"{}" => "{}",'.format(intrinsic, entry)) + continue + pos += 1 + continue + print("Done!") + + +def update_intrinsics(): + files = [] + intrinsics_path = os.path.join(LLVM_PATH, "llvm/include/llvm/IR") + for (dirpath, dirnames, filenames) in walk(intrinsics_path): + files.extend([os.path.join(intrinsics_path, f) for f in filenames if f.endswith(".td")]) + + intrinsics = {} + for file in files: + extract_instrinsics(intrinsics, file) + + archs = [arch for arch in intrinsics] + archs.sort() + output_file = os.path.join( + os.path.dirname(os.path.abspath(__file__)), + "../src/intrinsic/archs.rs", + ) + print("Updating content of `{}`...".format(output_file)) + with open(output_file, "w", encoding="utf8") as out: + out.write("// File generated by `rustc_codegen_gcc/tools/generate_intrinsics.py`\n") + out.write("// DO NOT EDIT IT!\n") + out.write("match name {\n") + for arch in archs: + if len(intrinsics[arch]) == 0: + continue + intrinsics[arch].sort() + out.write(' // {}\n'.format(arch)) + out.write('\n'.join([' {}'.format(x) for x in intrinsics[arch]])) + out.write('\n') + out.write(' _ => unimplemented!("***** unsupported LLVM intrinsic {}", name),\n') + out.write("}\n") + print("Done!") + + +def main(): + # First, we clone the LLVM repository if it's not already here. + clone_llvm_repository() + update_intrinsics() + + +if __name__ == "__main__": + sys.exit(main()) From ed0ba311c5da68edfd132c2e4f40d25f0ec24768 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Tue, 3 May 2022 18:59:13 +0200 Subject: [PATCH 075/356] Update intrinsics --- src/intrinsic/archs.rs | 3161 ++++++++++++++-------------------- tools/generate_intrinsics.py | 40 +- 2 files changed, 1335 insertions(+), 1866 deletions(-) diff --git a/src/intrinsic/archs.rs b/src/intrinsic/archs.rs index ef8a54f3530b..026ed7c6c7ca 100644 --- a/src/intrinsic/archs.rs +++ b/src/intrinsic/archs.rs @@ -1,917 +1,234 @@ +// File generated by `rustc_codegen_gcc/tools/generate_intrinsics.py` +// DO NOT EDIT IT! match name { - // AMDGPU - "llvm.AMDGPU.div.fixup.f32" => "__builtin_amdgpu_div_fixup", - "llvm.AMDGPU.div.fixup.f64" => "__builtin_amdgpu_div_fixup", - "llvm.AMDGPU.div.fixup.v2f64" => "__builtin_amdgpu_div_fixup", - "llvm.AMDGPU.div.fixup.v4f32" => "__builtin_amdgpu_div_fixup", - "llvm.AMDGPU.div.fmas.f32" => "__builtin_amdgpu_div_fmas", - "llvm.AMDGPU.div.fmas.f64" => "__builtin_amdgpu_div_fmas", - "llvm.AMDGPU.div.fmas.v2f64" => "__builtin_amdgpu_div_fmas", - "llvm.AMDGPU.div.fmas.v4f32" => "__builtin_amdgpu_div_fmas", - "llvm.AMDGPU.ldexp.f32" => "__builtin_amdgpu_ldexp", - "llvm.AMDGPU.ldexp.f64" => "__builtin_amdgpu_ldexp", - "llvm.AMDGPU.ldexp.v2f64" => "__builtin_amdgpu_ldexp", - "llvm.AMDGPU.ldexp.v4f32" => "__builtin_amdgpu_ldexp", - "llvm.AMDGPU.rcp.f32" => "__builtin_amdgpu_rcp", - "llvm.AMDGPU.rcp.f64" => "__builtin_amdgpu_rcp", - "llvm.AMDGPU.rcp.v2f64" => "__builtin_amdgpu_rcp", - "llvm.AMDGPU.rcp.v4f32" => "__builtin_amdgpu_rcp", - "llvm.AMDGPU.rsq.clamped.f32" => "__builtin_amdgpu_rsq_clamped", - "llvm.AMDGPU.rsq.clamped.f64" => "__builtin_amdgpu_rsq_clamped", - "llvm.AMDGPU.rsq.clamped.v2f64" => "__builtin_amdgpu_rsq_clamped", - "llvm.AMDGPU.rsq.clamped.v4f32" => "__builtin_amdgpu_rsq_clamped", - "llvm.AMDGPU.rsq.f32" => "__builtin_amdgpu_rsq", - "llvm.AMDGPU.rsq.f64" => "__builtin_amdgpu_rsq", - "llvm.AMDGPU.rsq.v2f64" => "__builtin_amdgpu_rsq", - "llvm.AMDGPU.rsq.v4f32" => "__builtin_amdgpu_rsq", - "llvm.AMDGPU.trig.preop.f32" => "__builtin_amdgpu_trig_preop", - "llvm.AMDGPU.trig.preop.f64" => "__builtin_amdgpu_trig_preop", - "llvm.AMDGPU.trig.preop.v2f64" => "__builtin_amdgpu_trig_preop", - "llvm.AMDGPU.trig.preop.v4f32" => "__builtin_amdgpu_trig_preop", // aarch64 "llvm.aarch64.dmb" => "__builtin_arm_dmb", "llvm.aarch64.dsb" => "__builtin_arm_dsb", "llvm.aarch64.isb" => "__builtin_arm_isb", + "llvm.aarch64.sve.aesd" => "__builtin_sve_svaesd_u8", + "llvm.aarch64.sve.aese" => "__builtin_sve_svaese_u8", + "llvm.aarch64.sve.aesimc" => "__builtin_sve_svaesimc_u8", + "llvm.aarch64.sve.aesmc" => "__builtin_sve_svaesmc_u8", + "llvm.aarch64.sve.rax1" => "__builtin_sve_svrax1_u64", + "llvm.aarch64.sve.rdffr" => "__builtin_sve_svrdffr", + "llvm.aarch64.sve.rdffr.z" => "__builtin_sve_svrdffr_z", + "llvm.aarch64.sve.setffr" => "__builtin_sve_svsetffr", + "llvm.aarch64.sve.sm4e" => "__builtin_sve_svsm4e_u32", + "llvm.aarch64.sve.sm4ekey" => "__builtin_sve_svsm4ekey_u32", + "llvm.aarch64.sve.wrffr" => "__builtin_sve_svwrffr", + "llvm.aarch64.tcancel" => "__builtin_arm_tcancel", + "llvm.aarch64.tcommit" => "__builtin_arm_tcommit", + "llvm.aarch64.tstart" => "__builtin_arm_tstart", + "llvm.aarch64.ttest" => "__builtin_arm_ttest", + // amdgcn + "llvm.amdgcn.alignbyte" => "__builtin_amdgcn_alignbyte", + "llvm.amdgcn.buffer.wbinvl1" => "__builtin_amdgcn_buffer_wbinvl1", + "llvm.amdgcn.buffer.wbinvl1.sc" => "__builtin_amdgcn_buffer_wbinvl1_sc", + "llvm.amdgcn.buffer.wbinvl1.vol" => "__builtin_amdgcn_buffer_wbinvl1_vol", + "llvm.amdgcn.cubeid" => "__builtin_amdgcn_cubeid", + "llvm.amdgcn.cubema" => "__builtin_amdgcn_cubema", + "llvm.amdgcn.cubesc" => "__builtin_amdgcn_cubesc", + "llvm.amdgcn.cubetc" => "__builtin_amdgcn_cubetc", + "llvm.amdgcn.cvt.pk.i16" => "__builtin_amdgcn_cvt_pk_i16", + "llvm.amdgcn.cvt.pk.u16" => "__builtin_amdgcn_cvt_pk_u16", + "llvm.amdgcn.cvt.pk.u8.f32" => "__builtin_amdgcn_cvt_pk_u8_f32", + "llvm.amdgcn.cvt.pknorm.i16" => "__builtin_amdgcn_cvt_pknorm_i16", + "llvm.amdgcn.cvt.pknorm.u16" => "__builtin_amdgcn_cvt_pknorm_u16", + "llvm.amdgcn.cvt.pkrtz" => "__builtin_amdgcn_cvt_pkrtz", + "llvm.amdgcn.dispatch.id" => "__builtin_amdgcn_dispatch_id", + "llvm.amdgcn.ds.bpermute" => "__builtin_amdgcn_ds_bpermute", + "llvm.amdgcn.ds.fadd.v2bf16" => "__builtin_amdgcn_ds_atomic_fadd_v2bf16", + "llvm.amdgcn.ds.gws.barrier" => "__builtin_amdgcn_ds_gws_barrier", + "llvm.amdgcn.ds.gws.init" => "__builtin_amdgcn_ds_gws_init", + "llvm.amdgcn.ds.gws.sema.br" => "__builtin_amdgcn_ds_gws_sema_br", + "llvm.amdgcn.ds.gws.sema.p" => "__builtin_amdgcn_ds_gws_sema_p", + "llvm.amdgcn.ds.gws.sema.release.all" => "__builtin_amdgcn_ds_gws_sema_release_all", + "llvm.amdgcn.ds.gws.sema.v" => "__builtin_amdgcn_ds_gws_sema_v", + "llvm.amdgcn.ds.permute" => "__builtin_amdgcn_ds_permute", + "llvm.amdgcn.ds.swizzle" => "__builtin_amdgcn_ds_swizzle", + "llvm.amdgcn.endpgm" => "__builtin_amdgcn_endpgm", + "llvm.amdgcn.fdot2" => "__builtin_amdgcn_fdot2", + "llvm.amdgcn.fmed3" => "__builtin_amdgcn_fmed3", + "llvm.amdgcn.fmul.legacy" => "__builtin_amdgcn_fmul_legacy", + "llvm.amdgcn.groupstaticsize" => "__builtin_amdgcn_groupstaticsize", + "llvm.amdgcn.implicit.buffer.ptr" => "__builtin_amdgcn_implicit_buffer_ptr", + "llvm.amdgcn.implicitarg.ptr" => "__builtin_amdgcn_implicitarg_ptr", + "llvm.amdgcn.interp.mov" => "__builtin_amdgcn_interp_mov", + "llvm.amdgcn.interp.p1" => "__builtin_amdgcn_interp_p1", + "llvm.amdgcn.interp.p1.f16" => "__builtin_amdgcn_interp_p1_f16", + "llvm.amdgcn.interp.p2" => "__builtin_amdgcn_interp_p2", + "llvm.amdgcn.interp.p2.f16" => "__builtin_amdgcn_interp_p2_f16", + "llvm.amdgcn.is.private" => "__builtin_amdgcn_is_private", + "llvm.amdgcn.is.shared" => "__builtin_amdgcn_is_shared", + "llvm.amdgcn.kernarg.segment.ptr" => "__builtin_amdgcn_kernarg_segment_ptr", + "llvm.amdgcn.lerp" => "__builtin_amdgcn_lerp", + "llvm.amdgcn.mbcnt.hi" => "__builtin_amdgcn_mbcnt_hi", + "llvm.amdgcn.mbcnt.lo" => "__builtin_amdgcn_mbcnt_lo", + "llvm.amdgcn.mqsad.pk.u16.u8" => "__builtin_amdgcn_mqsad_pk_u16_u8", + "llvm.amdgcn.mqsad.u32.u8" => "__builtin_amdgcn_mqsad_u32_u8", + "llvm.amdgcn.msad.u8" => "__builtin_amdgcn_msad_u8", + "llvm.amdgcn.perm" => "__builtin_amdgcn_perm", + "llvm.amdgcn.permlane16" => "__builtin_amdgcn_permlane16", + "llvm.amdgcn.permlanex16" => "__builtin_amdgcn_permlanex16", + "llvm.amdgcn.qsad.pk.u16.u8" => "__builtin_amdgcn_qsad_pk_u16_u8", + "llvm.amdgcn.queue.ptr" => "__builtin_amdgcn_queue_ptr", + "llvm.amdgcn.rcp.legacy" => "__builtin_amdgcn_rcp_legacy", + "llvm.amdgcn.readfirstlane" => "__builtin_amdgcn_readfirstlane", + "llvm.amdgcn.readlane" => "__builtin_amdgcn_readlane", + "llvm.amdgcn.rsq.legacy" => "__builtin_amdgcn_rsq_legacy", + "llvm.amdgcn.s.barrier" => "__builtin_amdgcn_s_barrier", + "llvm.amdgcn.s.dcache.inv" => "__builtin_amdgcn_s_dcache_inv", + "llvm.amdgcn.s.dcache.inv.vol" => "__builtin_amdgcn_s_dcache_inv_vol", + "llvm.amdgcn.s.dcache.wb" => "__builtin_amdgcn_s_dcache_wb", + "llvm.amdgcn.s.dcache.wb.vol" => "__builtin_amdgcn_s_dcache_wb_vol", + "llvm.amdgcn.s.get.waveid.in.workgroup" => "__builtin_amdgcn_s_get_waveid_in_workgroup", + "llvm.amdgcn.s.getpc" => "__builtin_amdgcn_s_getpc", + "llvm.amdgcn.s.getreg" => "__builtin_amdgcn_s_getreg", + "llvm.amdgcn.s.memrealtime" => "__builtin_amdgcn_s_memrealtime", + "llvm.amdgcn.s.memtime" => "__builtin_amdgcn_s_memtime", + "llvm.amdgcn.s.sendmsg" => "__builtin_amdgcn_s_sendmsg", + "llvm.amdgcn.s.sendmsghalt" => "__builtin_amdgcn_s_sendmsghalt", + "llvm.amdgcn.s.setprio" => "__builtin_amdgcn_s_setprio", + "llvm.amdgcn.s.setreg" => "__builtin_amdgcn_s_setreg", + "llvm.amdgcn.s.sleep" => "__builtin_amdgcn_s_decperflevel", + "llvm.amdgcn.s.sleep" => "__builtin_amdgcn_s_incperflevel", + "llvm.amdgcn.s.sleep" => "__builtin_amdgcn_s_sleep", + "llvm.amdgcn.s.waitcnt" => "__builtin_amdgcn_s_waitcnt", + "llvm.amdgcn.sad.hi.u8" => "__builtin_amdgcn_sad_hi_u8", + "llvm.amdgcn.sad.u16" => "__builtin_amdgcn_sad_u16", + "llvm.amdgcn.sad.u8" => "__builtin_amdgcn_sad_u8", + "llvm.amdgcn.sdot2" => "__builtin_amdgcn_sdot2", + "llvm.amdgcn.sdot4" => "__builtin_amdgcn_sdot4", + "llvm.amdgcn.sdot8" => "__builtin_amdgcn_sdot8", + "llvm.amdgcn.udot2" => "__builtin_amdgcn_udot2", + "llvm.amdgcn.udot4" => "__builtin_amdgcn_udot4", + "llvm.amdgcn.udot8" => "__builtin_amdgcn_udot8", + "llvm.amdgcn.wave.barrier" => "__builtin_amdgcn_wave_barrier", + "llvm.amdgcn.wavefrontsize" => "__builtin_amdgcn_wavefrontsize", + "llvm.amdgcn.writelane" => "__builtin_amdgcn_writelane", // arm "llvm.arm.cdp" => "__builtin_arm_cdp", "llvm.arm.cdp2" => "__builtin_arm_cdp2", + "llvm.arm.cmse.tt" => "__builtin_arm_cmse_TT", + "llvm.arm.cmse.tta" => "__builtin_arm_cmse_TTA", + "llvm.arm.cmse.ttat" => "__builtin_arm_cmse_TTAT", + "llvm.arm.cmse.ttt" => "__builtin_arm_cmse_TTT", "llvm.arm.dmb" => "__builtin_arm_dmb", "llvm.arm.dsb" => "__builtin_arm_dsb", "llvm.arm.get.fpscr" => "__builtin_arm_get_fpscr", "llvm.arm.isb" => "__builtin_arm_isb", + "llvm.arm.ldc" => "__builtin_arm_ldc", + "llvm.arm.ldc2" => "__builtin_arm_ldc2", + "llvm.arm.ldc2l" => "__builtin_arm_ldc2l", + "llvm.arm.ldcl" => "__builtin_arm_ldcl", "llvm.arm.mcr" => "__builtin_arm_mcr", "llvm.arm.mcr2" => "__builtin_arm_mcr2", - "llvm.arm.mcrr" => "__builtin_arm_mcrr", - "llvm.arm.mcrr2" => "__builtin_arm_mcrr2", "llvm.arm.mrc" => "__builtin_arm_mrc", "llvm.arm.mrc2" => "__builtin_arm_mrc2", "llvm.arm.qadd" => "__builtin_arm_qadd", + "llvm.arm.qadd16" => "__builtin_arm_qadd16", + "llvm.arm.qadd8" => "__builtin_arm_qadd8", + "llvm.arm.qasx" => "__builtin_arm_qasx", + "llvm.arm.qsax" => "__builtin_arm_qsax", "llvm.arm.qsub" => "__builtin_arm_qsub", + "llvm.arm.qsub16" => "__builtin_arm_qsub16", + "llvm.arm.qsub8" => "__builtin_arm_qsub8", + "llvm.arm.sadd16" => "__builtin_arm_sadd16", + "llvm.arm.sadd8" => "__builtin_arm_sadd8", + "llvm.arm.sasx" => "__builtin_arm_sasx", + "llvm.arm.sel" => "__builtin_arm_sel", "llvm.arm.set.fpscr" => "__builtin_arm_set_fpscr", + "llvm.arm.shadd16" => "__builtin_arm_shadd16", + "llvm.arm.shadd8" => "__builtin_arm_shadd8", + "llvm.arm.shasx" => "__builtin_arm_shasx", + "llvm.arm.shsax" => "__builtin_arm_shsax", + "llvm.arm.shsub16" => "__builtin_arm_shsub16", + "llvm.arm.shsub8" => "__builtin_arm_shsub8", + "llvm.arm.smlabb" => "__builtin_arm_smlabb", + "llvm.arm.smlabt" => "__builtin_arm_smlabt", + "llvm.arm.smlad" => "__builtin_arm_smlad", + "llvm.arm.smladx" => "__builtin_arm_smladx", + "llvm.arm.smlald" => "__builtin_arm_smlald", + "llvm.arm.smlaldx" => "__builtin_arm_smlaldx", + "llvm.arm.smlatb" => "__builtin_arm_smlatb", + "llvm.arm.smlatt" => "__builtin_arm_smlatt", + "llvm.arm.smlawb" => "__builtin_arm_smlawb", + "llvm.arm.smlawt" => "__builtin_arm_smlawt", + "llvm.arm.smlsd" => "__builtin_arm_smlsd", + "llvm.arm.smlsdx" => "__builtin_arm_smlsdx", + "llvm.arm.smlsld" => "__builtin_arm_smlsld", + "llvm.arm.smlsldx" => "__builtin_arm_smlsldx", + "llvm.arm.smuad" => "__builtin_arm_smuad", + "llvm.arm.smuadx" => "__builtin_arm_smuadx", + "llvm.arm.smulbb" => "__builtin_arm_smulbb", + "llvm.arm.smulbt" => "__builtin_arm_smulbt", + "llvm.arm.smultb" => "__builtin_arm_smultb", + "llvm.arm.smultt" => "__builtin_arm_smultt", + "llvm.arm.smulwb" => "__builtin_arm_smulwb", + "llvm.arm.smulwt" => "__builtin_arm_smulwt", + "llvm.arm.smusd" => "__builtin_arm_smusd", + "llvm.arm.smusdx" => "__builtin_arm_smusdx", "llvm.arm.ssat" => "__builtin_arm_ssat", - "llvm.arm.thread.pointer" => "__builtin_thread_pointer", + "llvm.arm.ssat16" => "__builtin_arm_ssat16", + "llvm.arm.ssax" => "__builtin_arm_ssax", + "llvm.arm.ssub16" => "__builtin_arm_ssub16", + "llvm.arm.ssub8" => "__builtin_arm_ssub8", + "llvm.arm.stc" => "__builtin_arm_stc", + "llvm.arm.stc2" => "__builtin_arm_stc2", + "llvm.arm.stc2l" => "__builtin_arm_stc2l", + "llvm.arm.stcl" => "__builtin_arm_stcl", + "llvm.arm.sxtab16" => "__builtin_arm_sxtab16", + "llvm.arm.sxtb16" => "__builtin_arm_sxtb16", + "llvm.arm.uadd16" => "__builtin_arm_uadd16", + "llvm.arm.uadd8" => "__builtin_arm_uadd8", + "llvm.arm.uasx" => "__builtin_arm_uasx", + "llvm.arm.uhadd16" => "__builtin_arm_uhadd16", + "llvm.arm.uhadd8" => "__builtin_arm_uhadd8", + "llvm.arm.uhasx" => "__builtin_arm_uhasx", + "llvm.arm.uhsax" => "__builtin_arm_uhsax", + "llvm.arm.uhsub16" => "__builtin_arm_uhsub16", + "llvm.arm.uhsub8" => "__builtin_arm_uhsub8", + "llvm.arm.uqadd16" => "__builtin_arm_uqadd16", + "llvm.arm.uqadd8" => "__builtin_arm_uqadd8", + "llvm.arm.uqasx" => "__builtin_arm_uqasx", + "llvm.arm.uqsax" => "__builtin_arm_uqsax", + "llvm.arm.uqsub16" => "__builtin_arm_uqsub16", + "llvm.arm.uqsub8" => "__builtin_arm_uqsub8", + "llvm.arm.usad8" => "__builtin_arm_usad8", + "llvm.arm.usada8" => "__builtin_arm_usada8", "llvm.arm.usat" => "__builtin_arm_usat", - // cuda - "llvm.cuda.syncthreads" => "__syncthreads", - // hexagon - "llvm.hexagon.A2.abs" => "__builtin_HEXAGON_A2_abs", - "llvm.hexagon.A2.absp" => "__builtin_HEXAGON_A2_absp", - "llvm.hexagon.A2.abssat" => "__builtin_HEXAGON_A2_abssat", - "llvm.hexagon.A2.add" => "__builtin_HEXAGON_A2_add", - "llvm.hexagon.A2.addh.h16.hh" => "__builtin_HEXAGON_A2_addh_h16_hh", - "llvm.hexagon.A2.addh.h16.hl" => "__builtin_HEXAGON_A2_addh_h16_hl", - "llvm.hexagon.A2.addh.h16.lh" => "__builtin_HEXAGON_A2_addh_h16_lh", - "llvm.hexagon.A2.addh.h16.ll" => "__builtin_HEXAGON_A2_addh_h16_ll", - "llvm.hexagon.A2.addh.h16.sat.hh" => "__builtin_HEXAGON_A2_addh_h16_sat_hh", - "llvm.hexagon.A2.addh.h16.sat.hl" => "__builtin_HEXAGON_A2_addh_h16_sat_hl", - "llvm.hexagon.A2.addh.h16.sat.lh" => "__builtin_HEXAGON_A2_addh_h16_sat_lh", - "llvm.hexagon.A2.addh.h16.sat.ll" => "__builtin_HEXAGON_A2_addh_h16_sat_ll", - "llvm.hexagon.A2.addh.l16.hl" => "__builtin_HEXAGON_A2_addh_l16_hl", - "llvm.hexagon.A2.addh.l16.ll" => "__builtin_HEXAGON_A2_addh_l16_ll", - "llvm.hexagon.A2.addh.l16.sat.hl" => "__builtin_HEXAGON_A2_addh_l16_sat_hl", - "llvm.hexagon.A2.addh.l16.sat.ll" => "__builtin_HEXAGON_A2_addh_l16_sat_ll", - "llvm.hexagon.A2.addi" => "__builtin_HEXAGON_A2_addi", - "llvm.hexagon.A2.addp" => "__builtin_HEXAGON_A2_addp", - "llvm.hexagon.A2.addpsat" => "__builtin_HEXAGON_A2_addpsat", - "llvm.hexagon.A2.addsat" => "__builtin_HEXAGON_A2_addsat", - "llvm.hexagon.A2.addsp" => "__builtin_HEXAGON_A2_addsp", - "llvm.hexagon.A2.and" => "__builtin_HEXAGON_A2_and", - "llvm.hexagon.A2.andir" => "__builtin_HEXAGON_A2_andir", - "llvm.hexagon.A2.andp" => "__builtin_HEXAGON_A2_andp", - "llvm.hexagon.A2.aslh" => "__builtin_HEXAGON_A2_aslh", - "llvm.hexagon.A2.asrh" => "__builtin_HEXAGON_A2_asrh", - "llvm.hexagon.A2.combine.hh" => "__builtin_HEXAGON_A2_combine_hh", - "llvm.hexagon.A2.combine.hl" => "__builtin_HEXAGON_A2_combine_hl", - "llvm.hexagon.A2.combine.lh" => "__builtin_HEXAGON_A2_combine_lh", - "llvm.hexagon.A2.combine.ll" => "__builtin_HEXAGON_A2_combine_ll", - "llvm.hexagon.A2.combineii" => "__builtin_HEXAGON_A2_combineii", - "llvm.hexagon.A2.combinew" => "__builtin_HEXAGON_A2_combinew", - "llvm.hexagon.A2.max" => "__builtin_HEXAGON_A2_max", - "llvm.hexagon.A2.maxp" => "__builtin_HEXAGON_A2_maxp", - "llvm.hexagon.A2.maxu" => "__builtin_HEXAGON_A2_maxu", - "llvm.hexagon.A2.maxup" => "__builtin_HEXAGON_A2_maxup", - "llvm.hexagon.A2.min" => "__builtin_HEXAGON_A2_min", - "llvm.hexagon.A2.minp" => "__builtin_HEXAGON_A2_minp", - "llvm.hexagon.A2.minu" => "__builtin_HEXAGON_A2_minu", - "llvm.hexagon.A2.minup" => "__builtin_HEXAGON_A2_minup", - "llvm.hexagon.A2.neg" => "__builtin_HEXAGON_A2_neg", - "llvm.hexagon.A2.negp" => "__builtin_HEXAGON_A2_negp", - "llvm.hexagon.A2.negsat" => "__builtin_HEXAGON_A2_negsat", - "llvm.hexagon.A2.not" => "__builtin_HEXAGON_A2_not", - "llvm.hexagon.A2.notp" => "__builtin_HEXAGON_A2_notp", - "llvm.hexagon.A2.or" => "__builtin_HEXAGON_A2_or", - "llvm.hexagon.A2.orir" => "__builtin_HEXAGON_A2_orir", - "llvm.hexagon.A2.orp" => "__builtin_HEXAGON_A2_orp", - "llvm.hexagon.A2.roundsat" => "__builtin_HEXAGON_A2_roundsat", - "llvm.hexagon.A2.sat" => "__builtin_HEXAGON_A2_sat", - "llvm.hexagon.A2.satb" => "__builtin_HEXAGON_A2_satb", - "llvm.hexagon.A2.sath" => "__builtin_HEXAGON_A2_sath", - "llvm.hexagon.A2.satub" => "__builtin_HEXAGON_A2_satub", - "llvm.hexagon.A2.satuh" => "__builtin_HEXAGON_A2_satuh", - "llvm.hexagon.A2.sub" => "__builtin_HEXAGON_A2_sub", - "llvm.hexagon.A2.subh.h16.hh" => "__builtin_HEXAGON_A2_subh_h16_hh", - "llvm.hexagon.A2.subh.h16.hl" => "__builtin_HEXAGON_A2_subh_h16_hl", - "llvm.hexagon.A2.subh.h16.lh" => "__builtin_HEXAGON_A2_subh_h16_lh", - "llvm.hexagon.A2.subh.h16.ll" => "__builtin_HEXAGON_A2_subh_h16_ll", - "llvm.hexagon.A2.subh.h16.sat.hh" => "__builtin_HEXAGON_A2_subh_h16_sat_hh", - "llvm.hexagon.A2.subh.h16.sat.hl" => "__builtin_HEXAGON_A2_subh_h16_sat_hl", - "llvm.hexagon.A2.subh.h16.sat.lh" => "__builtin_HEXAGON_A2_subh_h16_sat_lh", - "llvm.hexagon.A2.subh.h16.sat.ll" => "__builtin_HEXAGON_A2_subh_h16_sat_ll", - "llvm.hexagon.A2.subh.l16.hl" => "__builtin_HEXAGON_A2_subh_l16_hl", - "llvm.hexagon.A2.subh.l16.ll" => "__builtin_HEXAGON_A2_subh_l16_ll", - "llvm.hexagon.A2.subh.l16.sat.hl" => "__builtin_HEXAGON_A2_subh_l16_sat_hl", - "llvm.hexagon.A2.subh.l16.sat.ll" => "__builtin_HEXAGON_A2_subh_l16_sat_ll", - "llvm.hexagon.A2.subp" => "__builtin_HEXAGON_A2_subp", - "llvm.hexagon.A2.subri" => "__builtin_HEXAGON_A2_subri", - "llvm.hexagon.A2.subsat" => "__builtin_HEXAGON_A2_subsat", - "llvm.hexagon.A2.svaddh" => "__builtin_HEXAGON_A2_svaddh", - "llvm.hexagon.A2.svaddhs" => "__builtin_HEXAGON_A2_svaddhs", - "llvm.hexagon.A2.svadduhs" => "__builtin_HEXAGON_A2_svadduhs", - "llvm.hexagon.A2.svavgh" => "__builtin_HEXAGON_A2_svavgh", - "llvm.hexagon.A2.svavghs" => "__builtin_HEXAGON_A2_svavghs", - "llvm.hexagon.A2.svnavgh" => "__builtin_HEXAGON_A2_svnavgh", - "llvm.hexagon.A2.svsubh" => "__builtin_HEXAGON_A2_svsubh", - "llvm.hexagon.A2.svsubhs" => "__builtin_HEXAGON_A2_svsubhs", - "llvm.hexagon.A2.svsubuhs" => "__builtin_HEXAGON_A2_svsubuhs", - "llvm.hexagon.A2.swiz" => "__builtin_HEXAGON_A2_swiz", - "llvm.hexagon.A2.sxtb" => "__builtin_HEXAGON_A2_sxtb", - "llvm.hexagon.A2.sxth" => "__builtin_HEXAGON_A2_sxth", - "llvm.hexagon.A2.sxtw" => "__builtin_HEXAGON_A2_sxtw", - "llvm.hexagon.A2.tfr" => "__builtin_HEXAGON_A2_tfr", - "llvm.hexagon.A2.tfrih" => "__builtin_HEXAGON_A2_tfrih", - "llvm.hexagon.A2.tfril" => "__builtin_HEXAGON_A2_tfril", - "llvm.hexagon.A2.tfrp" => "__builtin_HEXAGON_A2_tfrp", - "llvm.hexagon.A2.tfrpi" => "__builtin_HEXAGON_A2_tfrpi", - "llvm.hexagon.A2.tfrsi" => "__builtin_HEXAGON_A2_tfrsi", - "llvm.hexagon.A2.vabsh" => "__builtin_HEXAGON_A2_vabsh", - "llvm.hexagon.A2.vabshsat" => "__builtin_HEXAGON_A2_vabshsat", - "llvm.hexagon.A2.vabsw" => "__builtin_HEXAGON_A2_vabsw", - "llvm.hexagon.A2.vabswsat" => "__builtin_HEXAGON_A2_vabswsat", - "llvm.hexagon.A2.vaddb.map" => "__builtin_HEXAGON_A2_vaddb_map", - "llvm.hexagon.A2.vaddh" => "__builtin_HEXAGON_A2_vaddh", - "llvm.hexagon.A2.vaddhs" => "__builtin_HEXAGON_A2_vaddhs", - "llvm.hexagon.A2.vaddub" => "__builtin_HEXAGON_A2_vaddub", - "llvm.hexagon.A2.vaddubs" => "__builtin_HEXAGON_A2_vaddubs", - "llvm.hexagon.A2.vadduhs" => "__builtin_HEXAGON_A2_vadduhs", - "llvm.hexagon.A2.vaddw" => "__builtin_HEXAGON_A2_vaddw", - "llvm.hexagon.A2.vaddws" => "__builtin_HEXAGON_A2_vaddws", - "llvm.hexagon.A2.vavgh" => "__builtin_HEXAGON_A2_vavgh", - "llvm.hexagon.A2.vavghcr" => "__builtin_HEXAGON_A2_vavghcr", - "llvm.hexagon.A2.vavghr" => "__builtin_HEXAGON_A2_vavghr", - "llvm.hexagon.A2.vavgub" => "__builtin_HEXAGON_A2_vavgub", - "llvm.hexagon.A2.vavgubr" => "__builtin_HEXAGON_A2_vavgubr", - "llvm.hexagon.A2.vavguh" => "__builtin_HEXAGON_A2_vavguh", - "llvm.hexagon.A2.vavguhr" => "__builtin_HEXAGON_A2_vavguhr", - "llvm.hexagon.A2.vavguw" => "__builtin_HEXAGON_A2_vavguw", - "llvm.hexagon.A2.vavguwr" => "__builtin_HEXAGON_A2_vavguwr", - "llvm.hexagon.A2.vavgw" => "__builtin_HEXAGON_A2_vavgw", - "llvm.hexagon.A2.vavgwcr" => "__builtin_HEXAGON_A2_vavgwcr", - "llvm.hexagon.A2.vavgwr" => "__builtin_HEXAGON_A2_vavgwr", - "llvm.hexagon.A2.vcmpbeq" => "__builtin_HEXAGON_A2_vcmpbeq", - "llvm.hexagon.A2.vcmpbgtu" => "__builtin_HEXAGON_A2_vcmpbgtu", - "llvm.hexagon.A2.vcmpheq" => "__builtin_HEXAGON_A2_vcmpheq", - "llvm.hexagon.A2.vcmphgt" => "__builtin_HEXAGON_A2_vcmphgt", - "llvm.hexagon.A2.vcmphgtu" => "__builtin_HEXAGON_A2_vcmphgtu", - "llvm.hexagon.A2.vcmpweq" => "__builtin_HEXAGON_A2_vcmpweq", - "llvm.hexagon.A2.vcmpwgt" => "__builtin_HEXAGON_A2_vcmpwgt", - "llvm.hexagon.A2.vcmpwgtu" => "__builtin_HEXAGON_A2_vcmpwgtu", - "llvm.hexagon.A2.vconj" => "__builtin_HEXAGON_A2_vconj", - "llvm.hexagon.A2.vmaxb" => "__builtin_HEXAGON_A2_vmaxb", - "llvm.hexagon.A2.vmaxh" => "__builtin_HEXAGON_A2_vmaxh", - "llvm.hexagon.A2.vmaxub" => "__builtin_HEXAGON_A2_vmaxub", - "llvm.hexagon.A2.vmaxuh" => "__builtin_HEXAGON_A2_vmaxuh", - "llvm.hexagon.A2.vmaxuw" => "__builtin_HEXAGON_A2_vmaxuw", - "llvm.hexagon.A2.vmaxw" => "__builtin_HEXAGON_A2_vmaxw", - "llvm.hexagon.A2.vminb" => "__builtin_HEXAGON_A2_vminb", - "llvm.hexagon.A2.vminh" => "__builtin_HEXAGON_A2_vminh", - "llvm.hexagon.A2.vminub" => "__builtin_HEXAGON_A2_vminub", - "llvm.hexagon.A2.vminuh" => "__builtin_HEXAGON_A2_vminuh", - "llvm.hexagon.A2.vminuw" => "__builtin_HEXAGON_A2_vminuw", - "llvm.hexagon.A2.vminw" => "__builtin_HEXAGON_A2_vminw", - "llvm.hexagon.A2.vnavgh" => "__builtin_HEXAGON_A2_vnavgh", - "llvm.hexagon.A2.vnavghcr" => "__builtin_HEXAGON_A2_vnavghcr", - "llvm.hexagon.A2.vnavghr" => "__builtin_HEXAGON_A2_vnavghr", - "llvm.hexagon.A2.vnavgw" => "__builtin_HEXAGON_A2_vnavgw", - "llvm.hexagon.A2.vnavgwcr" => "__builtin_HEXAGON_A2_vnavgwcr", - "llvm.hexagon.A2.vnavgwr" => "__builtin_HEXAGON_A2_vnavgwr", - "llvm.hexagon.A2.vraddub" => "__builtin_HEXAGON_A2_vraddub", - "llvm.hexagon.A2.vraddub.acc" => "__builtin_HEXAGON_A2_vraddub_acc", - "llvm.hexagon.A2.vrsadub" => "__builtin_HEXAGON_A2_vrsadub", - "llvm.hexagon.A2.vrsadub.acc" => "__builtin_HEXAGON_A2_vrsadub_acc", - "llvm.hexagon.A2.vsubb.map" => "__builtin_HEXAGON_A2_vsubb_map", - "llvm.hexagon.A2.vsubh" => "__builtin_HEXAGON_A2_vsubh", - "llvm.hexagon.A2.vsubhs" => "__builtin_HEXAGON_A2_vsubhs", - "llvm.hexagon.A2.vsubub" => "__builtin_HEXAGON_A2_vsubub", - "llvm.hexagon.A2.vsububs" => "__builtin_HEXAGON_A2_vsububs", - "llvm.hexagon.A2.vsubuhs" => "__builtin_HEXAGON_A2_vsubuhs", - "llvm.hexagon.A2.vsubw" => "__builtin_HEXAGON_A2_vsubw", - "llvm.hexagon.A2.vsubws" => "__builtin_HEXAGON_A2_vsubws", - "llvm.hexagon.A2.xor" => "__builtin_HEXAGON_A2_xor", - "llvm.hexagon.A2.xorp" => "__builtin_HEXAGON_A2_xorp", - "llvm.hexagon.A2.zxtb" => "__builtin_HEXAGON_A2_zxtb", - "llvm.hexagon.A2.zxth" => "__builtin_HEXAGON_A2_zxth", - "llvm.hexagon.A4.andn" => "__builtin_HEXAGON_A4_andn", - "llvm.hexagon.A4.andnp" => "__builtin_HEXAGON_A4_andnp", - "llvm.hexagon.A4.bitsplit" => "__builtin_HEXAGON_A4_bitsplit", - "llvm.hexagon.A4.bitspliti" => "__builtin_HEXAGON_A4_bitspliti", - "llvm.hexagon.A4.boundscheck" => "__builtin_HEXAGON_A4_boundscheck", - "llvm.hexagon.A4.cmpbeq" => "__builtin_HEXAGON_A4_cmpbeq", - "llvm.hexagon.A4.cmpbeqi" => "__builtin_HEXAGON_A4_cmpbeqi", - "llvm.hexagon.A4.cmpbgt" => "__builtin_HEXAGON_A4_cmpbgt", - "llvm.hexagon.A4.cmpbgti" => "__builtin_HEXAGON_A4_cmpbgti", - "llvm.hexagon.A4.cmpbgtu" => "__builtin_HEXAGON_A4_cmpbgtu", - "llvm.hexagon.A4.cmpbgtui" => "__builtin_HEXAGON_A4_cmpbgtui", - "llvm.hexagon.A4.cmpheq" => "__builtin_HEXAGON_A4_cmpheq", - "llvm.hexagon.A4.cmpheqi" => "__builtin_HEXAGON_A4_cmpheqi", - "llvm.hexagon.A4.cmphgt" => "__builtin_HEXAGON_A4_cmphgt", - "llvm.hexagon.A4.cmphgti" => "__builtin_HEXAGON_A4_cmphgti", - "llvm.hexagon.A4.cmphgtu" => "__builtin_HEXAGON_A4_cmphgtu", - "llvm.hexagon.A4.cmphgtui" => "__builtin_HEXAGON_A4_cmphgtui", - "llvm.hexagon.A4.combineir" => "__builtin_HEXAGON_A4_combineir", - "llvm.hexagon.A4.combineri" => "__builtin_HEXAGON_A4_combineri", - "llvm.hexagon.A4.cround.ri" => "__builtin_HEXAGON_A4_cround_ri", - "llvm.hexagon.A4.cround.rr" => "__builtin_HEXAGON_A4_cround_rr", - "llvm.hexagon.A4.modwrapu" => "__builtin_HEXAGON_A4_modwrapu", - "llvm.hexagon.A4.orn" => "__builtin_HEXAGON_A4_orn", - "llvm.hexagon.A4.ornp" => "__builtin_HEXAGON_A4_ornp", - "llvm.hexagon.A4.rcmpeq" => "__builtin_HEXAGON_A4_rcmpeq", - "llvm.hexagon.A4.rcmpeqi" => "__builtin_HEXAGON_A4_rcmpeqi", - "llvm.hexagon.A4.rcmpneq" => "__builtin_HEXAGON_A4_rcmpneq", - "llvm.hexagon.A4.rcmpneqi" => "__builtin_HEXAGON_A4_rcmpneqi", - "llvm.hexagon.A4.round.ri" => "__builtin_HEXAGON_A4_round_ri", - "llvm.hexagon.A4.round.ri.sat" => "__builtin_HEXAGON_A4_round_ri_sat", - "llvm.hexagon.A4.round.rr" => "__builtin_HEXAGON_A4_round_rr", - "llvm.hexagon.A4.round.rr.sat" => "__builtin_HEXAGON_A4_round_rr_sat", - "llvm.hexagon.A4.tlbmatch" => "__builtin_HEXAGON_A4_tlbmatch", - "llvm.hexagon.A4.vcmpbeq.any" => "__builtin_HEXAGON_A4_vcmpbeq_any", - "llvm.hexagon.A4.vcmpbeqi" => "__builtin_HEXAGON_A4_vcmpbeqi", - "llvm.hexagon.A4.vcmpbgt" => "__builtin_HEXAGON_A4_vcmpbgt", - "llvm.hexagon.A4.vcmpbgti" => "__builtin_HEXAGON_A4_vcmpbgti", - "llvm.hexagon.A4.vcmpbgtui" => "__builtin_HEXAGON_A4_vcmpbgtui", - "llvm.hexagon.A4.vcmpheqi" => "__builtin_HEXAGON_A4_vcmpheqi", - "llvm.hexagon.A4.vcmphgti" => "__builtin_HEXAGON_A4_vcmphgti", - "llvm.hexagon.A4.vcmphgtui" => "__builtin_HEXAGON_A4_vcmphgtui", - "llvm.hexagon.A4.vcmpweqi" => "__builtin_HEXAGON_A4_vcmpweqi", - "llvm.hexagon.A4.vcmpwgti" => "__builtin_HEXAGON_A4_vcmpwgti", - "llvm.hexagon.A4.vcmpwgtui" => "__builtin_HEXAGON_A4_vcmpwgtui", - "llvm.hexagon.A4.vrmaxh" => "__builtin_HEXAGON_A4_vrmaxh", - "llvm.hexagon.A4.vrmaxuh" => "__builtin_HEXAGON_A4_vrmaxuh", - "llvm.hexagon.A4.vrmaxuw" => "__builtin_HEXAGON_A4_vrmaxuw", - "llvm.hexagon.A4.vrmaxw" => "__builtin_HEXAGON_A4_vrmaxw", - "llvm.hexagon.A4.vrminh" => "__builtin_HEXAGON_A4_vrminh", - "llvm.hexagon.A4.vrminuh" => "__builtin_HEXAGON_A4_vrminuh", - "llvm.hexagon.A4.vrminuw" => "__builtin_HEXAGON_A4_vrminuw", - "llvm.hexagon.A4.vrminw" => "__builtin_HEXAGON_A4_vrminw", - "llvm.hexagon.A5.vaddhubs" => "__builtin_HEXAGON_A5_vaddhubs", - "llvm.hexagon.C2.all8" => "__builtin_HEXAGON_C2_all8", - "llvm.hexagon.C2.and" => "__builtin_HEXAGON_C2_and", - "llvm.hexagon.C2.andn" => "__builtin_HEXAGON_C2_andn", - "llvm.hexagon.C2.any8" => "__builtin_HEXAGON_C2_any8", - "llvm.hexagon.C2.bitsclr" => "__builtin_HEXAGON_C2_bitsclr", - "llvm.hexagon.C2.bitsclri" => "__builtin_HEXAGON_C2_bitsclri", - "llvm.hexagon.C2.bitsset" => "__builtin_HEXAGON_C2_bitsset", - "llvm.hexagon.C2.cmpeq" => "__builtin_HEXAGON_C2_cmpeq", - "llvm.hexagon.C2.cmpeqi" => "__builtin_HEXAGON_C2_cmpeqi", - "llvm.hexagon.C2.cmpeqp" => "__builtin_HEXAGON_C2_cmpeqp", - "llvm.hexagon.C2.cmpgei" => "__builtin_HEXAGON_C2_cmpgei", - "llvm.hexagon.C2.cmpgeui" => "__builtin_HEXAGON_C2_cmpgeui", - "llvm.hexagon.C2.cmpgt" => "__builtin_HEXAGON_C2_cmpgt", - "llvm.hexagon.C2.cmpgti" => "__builtin_HEXAGON_C2_cmpgti", - "llvm.hexagon.C2.cmpgtp" => "__builtin_HEXAGON_C2_cmpgtp", - "llvm.hexagon.C2.cmpgtu" => "__builtin_HEXAGON_C2_cmpgtu", - "llvm.hexagon.C2.cmpgtui" => "__builtin_HEXAGON_C2_cmpgtui", - "llvm.hexagon.C2.cmpgtup" => "__builtin_HEXAGON_C2_cmpgtup", - "llvm.hexagon.C2.cmplt" => "__builtin_HEXAGON_C2_cmplt", - "llvm.hexagon.C2.cmpltu" => "__builtin_HEXAGON_C2_cmpltu", - "llvm.hexagon.C2.mask" => "__builtin_HEXAGON_C2_mask", - "llvm.hexagon.C2.mux" => "__builtin_HEXAGON_C2_mux", - "llvm.hexagon.C2.muxii" => "__builtin_HEXAGON_C2_muxii", - "llvm.hexagon.C2.muxir" => "__builtin_HEXAGON_C2_muxir", - "llvm.hexagon.C2.muxri" => "__builtin_HEXAGON_C2_muxri", - "llvm.hexagon.C2.not" => "__builtin_HEXAGON_C2_not", - "llvm.hexagon.C2.or" => "__builtin_HEXAGON_C2_or", - "llvm.hexagon.C2.orn" => "__builtin_HEXAGON_C2_orn", - "llvm.hexagon.C2.pxfer.map" => "__builtin_HEXAGON_C2_pxfer_map", - "llvm.hexagon.C2.tfrpr" => "__builtin_HEXAGON_C2_tfrpr", - "llvm.hexagon.C2.tfrrp" => "__builtin_HEXAGON_C2_tfrrp", - "llvm.hexagon.C2.vitpack" => "__builtin_HEXAGON_C2_vitpack", - "llvm.hexagon.C2.vmux" => "__builtin_HEXAGON_C2_vmux", - "llvm.hexagon.C2.xor" => "__builtin_HEXAGON_C2_xor", - "llvm.hexagon.C4.and.and" => "__builtin_HEXAGON_C4_and_and", - "llvm.hexagon.C4.and.andn" => "__builtin_HEXAGON_C4_and_andn", - "llvm.hexagon.C4.and.or" => "__builtin_HEXAGON_C4_and_or", - "llvm.hexagon.C4.and.orn" => "__builtin_HEXAGON_C4_and_orn", - "llvm.hexagon.C4.cmplte" => "__builtin_HEXAGON_C4_cmplte", - "llvm.hexagon.C4.cmpltei" => "__builtin_HEXAGON_C4_cmpltei", - "llvm.hexagon.C4.cmplteu" => "__builtin_HEXAGON_C4_cmplteu", - "llvm.hexagon.C4.cmplteui" => "__builtin_HEXAGON_C4_cmplteui", - "llvm.hexagon.C4.cmpneq" => "__builtin_HEXAGON_C4_cmpneq", - "llvm.hexagon.C4.cmpneqi" => "__builtin_HEXAGON_C4_cmpneqi", - "llvm.hexagon.C4.fastcorner9" => "__builtin_HEXAGON_C4_fastcorner9", - "llvm.hexagon.C4.fastcorner9.not" => "__builtin_HEXAGON_C4_fastcorner9_not", - "llvm.hexagon.C4.nbitsclr" => "__builtin_HEXAGON_C4_nbitsclr", - "llvm.hexagon.C4.nbitsclri" => "__builtin_HEXAGON_C4_nbitsclri", - "llvm.hexagon.C4.nbitsset" => "__builtin_HEXAGON_C4_nbitsset", - "llvm.hexagon.C4.or.and" => "__builtin_HEXAGON_C4_or_and", - "llvm.hexagon.C4.or.andn" => "__builtin_HEXAGON_C4_or_andn", - "llvm.hexagon.C4.or.or" => "__builtin_HEXAGON_C4_or_or", - "llvm.hexagon.C4.or.orn" => "__builtin_HEXAGON_C4_or_orn", - "llvm.hexagon.F2.conv.d2df" => "__builtin_HEXAGON_F2_conv_d2df", - "llvm.hexagon.F2.conv.d2sf" => "__builtin_HEXAGON_F2_conv_d2sf", - "llvm.hexagon.F2.conv.df2d" => "__builtin_HEXAGON_F2_conv_df2d", - "llvm.hexagon.F2.conv.df2d.chop" => "__builtin_HEXAGON_F2_conv_df2d_chop", - "llvm.hexagon.F2.conv.df2sf" => "__builtin_HEXAGON_F2_conv_df2sf", - "llvm.hexagon.F2.conv.df2ud" => "__builtin_HEXAGON_F2_conv_df2ud", - "llvm.hexagon.F2.conv.df2ud.chop" => "__builtin_HEXAGON_F2_conv_df2ud_chop", - "llvm.hexagon.F2.conv.df2uw" => "__builtin_HEXAGON_F2_conv_df2uw", - "llvm.hexagon.F2.conv.df2uw.chop" => "__builtin_HEXAGON_F2_conv_df2uw_chop", - "llvm.hexagon.F2.conv.df2w" => "__builtin_HEXAGON_F2_conv_df2w", - "llvm.hexagon.F2.conv.df2w.chop" => "__builtin_HEXAGON_F2_conv_df2w_chop", - "llvm.hexagon.F2.conv.sf2d" => "__builtin_HEXAGON_F2_conv_sf2d", - "llvm.hexagon.F2.conv.sf2d.chop" => "__builtin_HEXAGON_F2_conv_sf2d_chop", - "llvm.hexagon.F2.conv.sf2df" => "__builtin_HEXAGON_F2_conv_sf2df", - "llvm.hexagon.F2.conv.sf2ud" => "__builtin_HEXAGON_F2_conv_sf2ud", - "llvm.hexagon.F2.conv.sf2ud.chop" => "__builtin_HEXAGON_F2_conv_sf2ud_chop", - "llvm.hexagon.F2.conv.sf2uw" => "__builtin_HEXAGON_F2_conv_sf2uw", - "llvm.hexagon.F2.conv.sf2uw.chop" => "__builtin_HEXAGON_F2_conv_sf2uw_chop", - "llvm.hexagon.F2.conv.sf2w" => "__builtin_HEXAGON_F2_conv_sf2w", - "llvm.hexagon.F2.conv.sf2w.chop" => "__builtin_HEXAGON_F2_conv_sf2w_chop", - "llvm.hexagon.F2.conv.ud2df" => "__builtin_HEXAGON_F2_conv_ud2df", - "llvm.hexagon.F2.conv.ud2sf" => "__builtin_HEXAGON_F2_conv_ud2sf", - "llvm.hexagon.F2.conv.uw2df" => "__builtin_HEXAGON_F2_conv_uw2df", - "llvm.hexagon.F2.conv.uw2sf" => "__builtin_HEXAGON_F2_conv_uw2sf", - "llvm.hexagon.F2.conv.w2df" => "__builtin_HEXAGON_F2_conv_w2df", - "llvm.hexagon.F2.conv.w2sf" => "__builtin_HEXAGON_F2_conv_w2sf", - "llvm.hexagon.F2.dfadd" => "__builtin_HEXAGON_F2_dfadd", - "llvm.hexagon.F2.dfclass" => "__builtin_HEXAGON_F2_dfclass", - "llvm.hexagon.F2.dfcmpeq" => "__builtin_HEXAGON_F2_dfcmpeq", - "llvm.hexagon.F2.dfcmpge" => "__builtin_HEXAGON_F2_dfcmpge", - "llvm.hexagon.F2.dfcmpgt" => "__builtin_HEXAGON_F2_dfcmpgt", - "llvm.hexagon.F2.dfcmpuo" => "__builtin_HEXAGON_F2_dfcmpuo", - "llvm.hexagon.F2.dffixupd" => "__builtin_HEXAGON_F2_dffixupd", - "llvm.hexagon.F2.dffixupn" => "__builtin_HEXAGON_F2_dffixupn", - "llvm.hexagon.F2.dffixupr" => "__builtin_HEXAGON_F2_dffixupr", - "llvm.hexagon.F2.dffma" => "__builtin_HEXAGON_F2_dffma", - "llvm.hexagon.F2.dffma.lib" => "__builtin_HEXAGON_F2_dffma_lib", - "llvm.hexagon.F2.dffma.sc" => "__builtin_HEXAGON_F2_dffma_sc", - "llvm.hexagon.F2.dffms" => "__builtin_HEXAGON_F2_dffms", - "llvm.hexagon.F2.dffms.lib" => "__builtin_HEXAGON_F2_dffms_lib", - "llvm.hexagon.F2.dfimm.n" => "__builtin_HEXAGON_F2_dfimm_n", - "llvm.hexagon.F2.dfimm.p" => "__builtin_HEXAGON_F2_dfimm_p", - "llvm.hexagon.F2.dfmax" => "__builtin_HEXAGON_F2_dfmax", - "llvm.hexagon.F2.dfmin" => "__builtin_HEXAGON_F2_dfmin", - "llvm.hexagon.F2.dfmpy" => "__builtin_HEXAGON_F2_dfmpy", - "llvm.hexagon.F2.dfsub" => "__builtin_HEXAGON_F2_dfsub", - "llvm.hexagon.F2.sfadd" => "__builtin_HEXAGON_F2_sfadd", - "llvm.hexagon.F2.sfclass" => "__builtin_HEXAGON_F2_sfclass", - "llvm.hexagon.F2.sfcmpeq" => "__builtin_HEXAGON_F2_sfcmpeq", - "llvm.hexagon.F2.sfcmpge" => "__builtin_HEXAGON_F2_sfcmpge", - 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"__builtin_HEXAGON_M2_mpyud_nac_lh_s1", - "llvm.hexagon.M2.mpyud.nac.ll.s0" => "__builtin_HEXAGON_M2_mpyud_nac_ll_s0", - "llvm.hexagon.M2.mpyud.nac.ll.s1" => "__builtin_HEXAGON_M2_mpyud_nac_ll_s1", - "llvm.hexagon.M2.mpyui" => "__builtin_HEXAGON_M2_mpyui", - "llvm.hexagon.M2.nacci" => "__builtin_HEXAGON_M2_nacci", - "llvm.hexagon.M2.naccii" => "__builtin_HEXAGON_M2_naccii", - "llvm.hexagon.M2.subacc" => "__builtin_HEXAGON_M2_subacc", - "llvm.hexagon.M2.vabsdiffh" => "__builtin_HEXAGON_M2_vabsdiffh", - "llvm.hexagon.M2.vabsdiffw" => "__builtin_HEXAGON_M2_vabsdiffw", - "llvm.hexagon.M2.vcmac.s0.sat.i" => "__builtin_HEXAGON_M2_vcmac_s0_sat_i", - "llvm.hexagon.M2.vcmac.s0.sat.r" => "__builtin_HEXAGON_M2_vcmac_s0_sat_r", - "llvm.hexagon.M2.vcmpy.s0.sat.i" => "__builtin_HEXAGON_M2_vcmpy_s0_sat_i", - "llvm.hexagon.M2.vcmpy.s0.sat.r" => "__builtin_HEXAGON_M2_vcmpy_s0_sat_r", - "llvm.hexagon.M2.vcmpy.s1.sat.i" => "__builtin_HEXAGON_M2_vcmpy_s1_sat_i", - "llvm.hexagon.M2.vcmpy.s1.sat.r" => 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"llvm.hexagon.M4.cmpyi.whc" => "__builtin_HEXAGON_M4_cmpyi_whc", - "llvm.hexagon.M4.cmpyr.wh" => "__builtin_HEXAGON_M4_cmpyr_wh", - "llvm.hexagon.M4.cmpyr.whc" => "__builtin_HEXAGON_M4_cmpyr_whc", - "llvm.hexagon.M4.mac.up.s1.sat" => "__builtin_HEXAGON_M4_mac_up_s1_sat", - "llvm.hexagon.M4.mpyri.addi" => "__builtin_HEXAGON_M4_mpyri_addi", - "llvm.hexagon.M4.mpyri.addr" => "__builtin_HEXAGON_M4_mpyri_addr", - "llvm.hexagon.M4.mpyri.addr.u2" => "__builtin_HEXAGON_M4_mpyri_addr_u2", - "llvm.hexagon.M4.mpyrr.addi" => "__builtin_HEXAGON_M4_mpyrr_addi", - "llvm.hexagon.M4.mpyrr.addr" => "__builtin_HEXAGON_M4_mpyrr_addr", - "llvm.hexagon.M4.nac.up.s1.sat" => "__builtin_HEXAGON_M4_nac_up_s1_sat", - "llvm.hexagon.M4.or.and" => "__builtin_HEXAGON_M4_or_and", - "llvm.hexagon.M4.or.andn" => "__builtin_HEXAGON_M4_or_andn", - "llvm.hexagon.M4.or.or" => "__builtin_HEXAGON_M4_or_or", - "llvm.hexagon.M4.or.xor" => "__builtin_HEXAGON_M4_or_xor", - "llvm.hexagon.M4.pmpyw" => "__builtin_HEXAGON_M4_pmpyw", - "llvm.hexagon.M4.pmpyw.acc" => "__builtin_HEXAGON_M4_pmpyw_acc", - "llvm.hexagon.M4.vpmpyh" => "__builtin_HEXAGON_M4_vpmpyh", - "llvm.hexagon.M4.vpmpyh.acc" => "__builtin_HEXAGON_M4_vpmpyh_acc", - "llvm.hexagon.M4.vrmpyeh.acc.s0" => "__builtin_HEXAGON_M4_vrmpyeh_acc_s0", - "llvm.hexagon.M4.vrmpyeh.acc.s1" => "__builtin_HEXAGON_M4_vrmpyeh_acc_s1", - "llvm.hexagon.M4.vrmpyeh.s0" => "__builtin_HEXAGON_M4_vrmpyeh_s0", - "llvm.hexagon.M4.vrmpyeh.s1" => "__builtin_HEXAGON_M4_vrmpyeh_s1", - "llvm.hexagon.M4.vrmpyoh.acc.s0" => "__builtin_HEXAGON_M4_vrmpyoh_acc_s0", - "llvm.hexagon.M4.vrmpyoh.acc.s1" => "__builtin_HEXAGON_M4_vrmpyoh_acc_s1", - "llvm.hexagon.M4.vrmpyoh.s0" => "__builtin_HEXAGON_M4_vrmpyoh_s0", - "llvm.hexagon.M4.vrmpyoh.s1" => "__builtin_HEXAGON_M4_vrmpyoh_s1", - "llvm.hexagon.M4.xor.and" => "__builtin_HEXAGON_M4_xor_and", - "llvm.hexagon.M4.xor.andn" => "__builtin_HEXAGON_M4_xor_andn", - "llvm.hexagon.M4.xor.or" => "__builtin_HEXAGON_M4_xor_or", - "llvm.hexagon.M4.xor.xacc" => "__builtin_HEXAGON_M4_xor_xacc", - "llvm.hexagon.M5.vdmacbsu" => "__builtin_HEXAGON_M5_vdmacbsu", - "llvm.hexagon.M5.vdmpybsu" => "__builtin_HEXAGON_M5_vdmpybsu", - "llvm.hexagon.M5.vmacbsu" => "__builtin_HEXAGON_M5_vmacbsu", - "llvm.hexagon.M5.vmacbuu" => "__builtin_HEXAGON_M5_vmacbuu", - "llvm.hexagon.M5.vmpybsu" => "__builtin_HEXAGON_M5_vmpybsu", - "llvm.hexagon.M5.vmpybuu" => "__builtin_HEXAGON_M5_vmpybuu", - "llvm.hexagon.M5.vrmacbsu" => "__builtin_HEXAGON_M5_vrmacbsu", - "llvm.hexagon.M5.vrmacbuu" => "__builtin_HEXAGON_M5_vrmacbuu", - "llvm.hexagon.M5.vrmpybsu" => "__builtin_HEXAGON_M5_vrmpybsu", - "llvm.hexagon.M5.vrmpybuu" => "__builtin_HEXAGON_M5_vrmpybuu", - "llvm.hexagon.S2.addasl.rrri" => "__builtin_HEXAGON_S2_addasl_rrri", - "llvm.hexagon.S2.asl.i.p" => "__builtin_HEXAGON_S2_asl_i_p", - "llvm.hexagon.S2.asl.i.p.acc" => "__builtin_HEXAGON_S2_asl_i_p_acc", - "llvm.hexagon.S2.asl.i.p.and" => "__builtin_HEXAGON_S2_asl_i_p_and", - "llvm.hexagon.S2.asl.i.p.nac" => "__builtin_HEXAGON_S2_asl_i_p_nac", - "llvm.hexagon.S2.asl.i.p.or" => "__builtin_HEXAGON_S2_asl_i_p_or", - "llvm.hexagon.S2.asl.i.p.xacc" => "__builtin_HEXAGON_S2_asl_i_p_xacc", - "llvm.hexagon.S2.asl.i.r" => "__builtin_HEXAGON_S2_asl_i_r", - "llvm.hexagon.S2.asl.i.r.acc" => "__builtin_HEXAGON_S2_asl_i_r_acc", - "llvm.hexagon.S2.asl.i.r.and" => "__builtin_HEXAGON_S2_asl_i_r_and", - "llvm.hexagon.S2.asl.i.r.nac" => "__builtin_HEXAGON_S2_asl_i_r_nac", - "llvm.hexagon.S2.asl.i.r.or" => "__builtin_HEXAGON_S2_asl_i_r_or", - "llvm.hexagon.S2.asl.i.r.sat" => "__builtin_HEXAGON_S2_asl_i_r_sat", - "llvm.hexagon.S2.asl.i.r.xacc" => "__builtin_HEXAGON_S2_asl_i_r_xacc", - "llvm.hexagon.S2.asl.i.vh" => "__builtin_HEXAGON_S2_asl_i_vh", - "llvm.hexagon.S2.asl.i.vw" => "__builtin_HEXAGON_S2_asl_i_vw", - "llvm.hexagon.S2.asl.r.p" => "__builtin_HEXAGON_S2_asl_r_p", - "llvm.hexagon.S2.asl.r.p.acc" => "__builtin_HEXAGON_S2_asl_r_p_acc", - "llvm.hexagon.S2.asl.r.p.and" => "__builtin_HEXAGON_S2_asl_r_p_and", - "llvm.hexagon.S2.asl.r.p.nac" => "__builtin_HEXAGON_S2_asl_r_p_nac", - "llvm.hexagon.S2.asl.r.p.or" => "__builtin_HEXAGON_S2_asl_r_p_or", - "llvm.hexagon.S2.asl.r.p.xor" => "__builtin_HEXAGON_S2_asl_r_p_xor", - "llvm.hexagon.S2.asl.r.r" => "__builtin_HEXAGON_S2_asl_r_r", - "llvm.hexagon.S2.asl.r.r.acc" => "__builtin_HEXAGON_S2_asl_r_r_acc", - "llvm.hexagon.S2.asl.r.r.and" => "__builtin_HEXAGON_S2_asl_r_r_and", - "llvm.hexagon.S2.asl.r.r.nac" => "__builtin_HEXAGON_S2_asl_r_r_nac", - "llvm.hexagon.S2.asl.r.r.or" => "__builtin_HEXAGON_S2_asl_r_r_or", - "llvm.hexagon.S2.asl.r.r.sat" => "__builtin_HEXAGON_S2_asl_r_r_sat", - "llvm.hexagon.S2.asl.r.vh" => "__builtin_HEXAGON_S2_asl_r_vh", - "llvm.hexagon.S2.asl.r.vw" => "__builtin_HEXAGON_S2_asl_r_vw", - "llvm.hexagon.S2.asr.i.p" => "__builtin_HEXAGON_S2_asr_i_p", - "llvm.hexagon.S2.asr.i.p.acc" => "__builtin_HEXAGON_S2_asr_i_p_acc", - "llvm.hexagon.S2.asr.i.p.and" => "__builtin_HEXAGON_S2_asr_i_p_and", - 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=> "__builtin_HEXAGON_S2_deinterleave", - "llvm.hexagon.S2.extractu" => "__builtin_HEXAGON_S2_extractu", - "llvm.hexagon.S2.extractu.rp" => "__builtin_HEXAGON_S2_extractu_rp", - "llvm.hexagon.S2.extractup" => "__builtin_HEXAGON_S2_extractup", - "llvm.hexagon.S2.extractup.rp" => "__builtin_HEXAGON_S2_extractup_rp", - "llvm.hexagon.S2.insert" => "__builtin_HEXAGON_S2_insert", - "llvm.hexagon.S2.insert.rp" => "__builtin_HEXAGON_S2_insert_rp", - "llvm.hexagon.S2.insertp" => "__builtin_HEXAGON_S2_insertp", - "llvm.hexagon.S2.insertp.rp" => "__builtin_HEXAGON_S2_insertp_rp", - "llvm.hexagon.S2.interleave" => "__builtin_HEXAGON_S2_interleave", - "llvm.hexagon.S2.lfsp" => "__builtin_HEXAGON_S2_lfsp", - "llvm.hexagon.S2.lsl.r.p" => "__builtin_HEXAGON_S2_lsl_r_p", - "llvm.hexagon.S2.lsl.r.p.acc" => "__builtin_HEXAGON_S2_lsl_r_p_acc", - "llvm.hexagon.S2.lsl.r.p.and" => "__builtin_HEXAGON_S2_lsl_r_p_and", - "llvm.hexagon.S2.lsl.r.p.nac" => "__builtin_HEXAGON_S2_lsl_r_p_nac", - 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- "llvm.hexagon.S2.lsr.r.r" => "__builtin_HEXAGON_S2_lsr_r_r", - "llvm.hexagon.S2.lsr.r.r.acc" => "__builtin_HEXAGON_S2_lsr_r_r_acc", - "llvm.hexagon.S2.lsr.r.r.and" => "__builtin_HEXAGON_S2_lsr_r_r_and", - "llvm.hexagon.S2.lsr.r.r.nac" => "__builtin_HEXAGON_S2_lsr_r_r_nac", - "llvm.hexagon.S2.lsr.r.r.or" => "__builtin_HEXAGON_S2_lsr_r_r_or", - "llvm.hexagon.S2.lsr.r.vh" => "__builtin_HEXAGON_S2_lsr_r_vh", - "llvm.hexagon.S2.lsr.r.vw" => "__builtin_HEXAGON_S2_lsr_r_vw", - "llvm.hexagon.S2.packhl" => "__builtin_HEXAGON_S2_packhl", - "llvm.hexagon.S2.parityp" => "__builtin_HEXAGON_S2_parityp", - "llvm.hexagon.S2.setbit.i" => "__builtin_HEXAGON_S2_setbit_i", - "llvm.hexagon.S2.setbit.r" => "__builtin_HEXAGON_S2_setbit_r", - "llvm.hexagon.S2.shuffeb" => "__builtin_HEXAGON_S2_shuffeb", - "llvm.hexagon.S2.shuffeh" => "__builtin_HEXAGON_S2_shuffeh", - "llvm.hexagon.S2.shuffob" => "__builtin_HEXAGON_S2_shuffob", - "llvm.hexagon.S2.shuffoh" => "__builtin_HEXAGON_S2_shuffoh", - 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"__builtin_HEXAGON_S2_vcrotate", - "llvm.hexagon.S2.vrcnegh" => "__builtin_HEXAGON_S2_vrcnegh", - "llvm.hexagon.S2.vrndpackwh" => "__builtin_HEXAGON_S2_vrndpackwh", - "llvm.hexagon.S2.vrndpackwhs" => "__builtin_HEXAGON_S2_vrndpackwhs", - "llvm.hexagon.S2.vsathb" => "__builtin_HEXAGON_S2_vsathb", - "llvm.hexagon.S2.vsathb.nopack" => "__builtin_HEXAGON_S2_vsathb_nopack", - "llvm.hexagon.S2.vsathub" => "__builtin_HEXAGON_S2_vsathub", - "llvm.hexagon.S2.vsathub.nopack" => "__builtin_HEXAGON_S2_vsathub_nopack", - "llvm.hexagon.S2.vsatwh" => "__builtin_HEXAGON_S2_vsatwh", - "llvm.hexagon.S2.vsatwh.nopack" => "__builtin_HEXAGON_S2_vsatwh_nopack", - "llvm.hexagon.S2.vsatwuh" => "__builtin_HEXAGON_S2_vsatwuh", - "llvm.hexagon.S2.vsatwuh.nopack" => "__builtin_HEXAGON_S2_vsatwuh_nopack", - "llvm.hexagon.S2.vsplatrb" => "__builtin_HEXAGON_S2_vsplatrb", - "llvm.hexagon.S2.vsplatrh" => "__builtin_HEXAGON_S2_vsplatrh", - "llvm.hexagon.S2.vspliceib" => "__builtin_HEXAGON_S2_vspliceib", - "llvm.hexagon.S2.vsplicerb" => "__builtin_HEXAGON_S2_vsplicerb", - "llvm.hexagon.S2.vsxtbh" => "__builtin_HEXAGON_S2_vsxtbh", - "llvm.hexagon.S2.vsxthw" => "__builtin_HEXAGON_S2_vsxthw", - "llvm.hexagon.S2.vtrunehb" => "__builtin_HEXAGON_S2_vtrunehb", - "llvm.hexagon.S2.vtrunewh" => "__builtin_HEXAGON_S2_vtrunewh", - "llvm.hexagon.S2.vtrunohb" => "__builtin_HEXAGON_S2_vtrunohb", - "llvm.hexagon.S2.vtrunowh" => "__builtin_HEXAGON_S2_vtrunowh", - "llvm.hexagon.S2.vzxtbh" => "__builtin_HEXAGON_S2_vzxtbh", - "llvm.hexagon.S2.vzxthw" => "__builtin_HEXAGON_S2_vzxthw", - "llvm.hexagon.S4.addaddi" => "__builtin_HEXAGON_S4_addaddi", - "llvm.hexagon.S4.addi.asl.ri" => "__builtin_HEXAGON_S4_addi_asl_ri", - "llvm.hexagon.S4.addi.lsr.ri" => "__builtin_HEXAGON_S4_addi_lsr_ri", - "llvm.hexagon.S4.andi.asl.ri" => "__builtin_HEXAGON_S4_andi_asl_ri", - "llvm.hexagon.S4.andi.lsr.ri" => "__builtin_HEXAGON_S4_andi_lsr_ri", - "llvm.hexagon.S4.clbaddi" => "__builtin_HEXAGON_S4_clbaddi", - "llvm.hexagon.S4.clbpaddi" => "__builtin_HEXAGON_S4_clbpaddi", - "llvm.hexagon.S4.clbpnorm" => "__builtin_HEXAGON_S4_clbpnorm", - "llvm.hexagon.S4.extract" => "__builtin_HEXAGON_S4_extract", - "llvm.hexagon.S4.extract.rp" => "__builtin_HEXAGON_S4_extract_rp", - "llvm.hexagon.S4.extractp" => "__builtin_HEXAGON_S4_extractp", - "llvm.hexagon.S4.extractp.rp" => "__builtin_HEXAGON_S4_extractp_rp", - "llvm.hexagon.S4.lsli" => "__builtin_HEXAGON_S4_lsli", - "llvm.hexagon.S4.ntstbit.i" => "__builtin_HEXAGON_S4_ntstbit_i", - "llvm.hexagon.S4.ntstbit.r" => "__builtin_HEXAGON_S4_ntstbit_r", - "llvm.hexagon.S4.or.andi" => "__builtin_HEXAGON_S4_or_andi", - "llvm.hexagon.S4.or.andix" => "__builtin_HEXAGON_S4_or_andix", - "llvm.hexagon.S4.or.ori" => "__builtin_HEXAGON_S4_or_ori", - "llvm.hexagon.S4.ori.asl.ri" => "__builtin_HEXAGON_S4_ori_asl_ri", - "llvm.hexagon.S4.ori.lsr.ri" => "__builtin_HEXAGON_S4_ori_lsr_ri", - "llvm.hexagon.S4.parity" => "__builtin_HEXAGON_S4_parity", - "llvm.hexagon.S4.subaddi" => "__builtin_HEXAGON_S4_subaddi", - "llvm.hexagon.S4.subi.asl.ri" => "__builtin_HEXAGON_S4_subi_asl_ri", - "llvm.hexagon.S4.subi.lsr.ri" => "__builtin_HEXAGON_S4_subi_lsr_ri", - "llvm.hexagon.S4.vrcrotate" => "__builtin_HEXAGON_S4_vrcrotate", - "llvm.hexagon.S4.vrcrotate.acc" => "__builtin_HEXAGON_S4_vrcrotate_acc", - "llvm.hexagon.S4.vxaddsubh" => "__builtin_HEXAGON_S4_vxaddsubh", - "llvm.hexagon.S4.vxaddsubhr" => "__builtin_HEXAGON_S4_vxaddsubhr", - "llvm.hexagon.S4.vxaddsubw" => "__builtin_HEXAGON_S4_vxaddsubw", - "llvm.hexagon.S4.vxsubaddh" => "__builtin_HEXAGON_S4_vxsubaddh", - "llvm.hexagon.S4.vxsubaddhr" => "__builtin_HEXAGON_S4_vxsubaddhr", - "llvm.hexagon.S4.vxsubaddw" => "__builtin_HEXAGON_S4_vxsubaddw", - "llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax" => "__builtin_HEXAGON_S5_asrhub_rnd_sat_goodsyntax", - "llvm.hexagon.S5.asrhub.sat" => "__builtin_HEXAGON_S5_asrhub_sat", - "llvm.hexagon.S5.popcountp" => "__builtin_HEXAGON_S5_popcountp", - "llvm.hexagon.S5.vasrhrnd.goodsyntax" => "__builtin_HEXAGON_S5_vasrhrnd_goodsyntax", - "llvm.hexagon.SI.to.SXTHI.asrh" => "__builtin_SI_to_SXTHI_asrh", - "llvm.hexagon.circ.ldd" => "__builtin_circ_ldd", + "llvm.arm.usat16" => "__builtin_arm_usat16", + "llvm.arm.usax" => "__builtin_arm_usax", + "llvm.arm.usub16" => "__builtin_arm_usub16", + "llvm.arm.usub8" => "__builtin_arm_usub8", + "llvm.arm.uxtab16" => "__builtin_arm_uxtab16", + "llvm.arm.uxtb16" => "__builtin_arm_uxtb16", + // bpf + "llvm.bpf.btf.type.id" => "__builtin_bpf_btf_type_id", + "llvm.bpf.compare" => "__builtin_bpf_compare", + "llvm.bpf.load.byte" => "__builtin_bpf_load_byte", + "llvm.bpf.load.half" => "__builtin_bpf_load_half", + "llvm.bpf.load.word" => "__builtin_bpf_load_word", + "llvm.bpf.passthrough" => "__builtin_bpf_passthrough", + "llvm.bpf.preserve.enum.value" => "__builtin_bpf_preserve_enum_value", + "llvm.bpf.preserve.field.info" => "__builtin_bpf_preserve_field_info", + "llvm.bpf.preserve.type.info" => "__builtin_bpf_preserve_type_info", + "llvm.bpf.pseudo" => "__builtin_bpf_pseudo", // mips + "llvm.mips.absq.s.ph" => "__builtin_mips_absq_s_ph", + "llvm.mips.absq.s.qb" => "__builtin_mips_absq_s_qb", + "llvm.mips.absq.s.w" => "__builtin_mips_absq_s_w", "llvm.mips.add.a.b" => "__builtin_msa_add_a_b", "llvm.mips.add.a.d" => "__builtin_msa_add_a_d", "llvm.mips.add.a.h" => "__builtin_msa_add_a_h", "llvm.mips.add.a.w" => "__builtin_msa_add_a_w", + "llvm.mips.addq.ph" => "__builtin_mips_addq_ph", + "llvm.mips.addq.s.ph" => "__builtin_mips_addq_s_ph", + "llvm.mips.addq.s.w" => "__builtin_mips_addq_s_w", + "llvm.mips.addqh.ph" => "__builtin_mips_addqh_ph", + "llvm.mips.addqh.r.ph" => "__builtin_mips_addqh_r_ph", + "llvm.mips.addqh.r.w" => "__builtin_mips_addqh_r_w", + "llvm.mips.addqh.w" => "__builtin_mips_addqh_w", "llvm.mips.adds.a.b" => "__builtin_msa_adds_a_b", "llvm.mips.adds.a.d" => "__builtin_msa_adds_a_d", "llvm.mips.adds.a.h" => "__builtin_msa_adds_a_h", @@ -1067,6 +384,9 @@ match name { "llvm.mips.clti.u.d" => "__builtin_msa_clti_u_d", "llvm.mips.clti.u.h" => "__builtin_msa_clti_u_h", "llvm.mips.clti.u.w" => "__builtin_msa_clti_u_w", + "llvm.mips.cmp.eq.ph" => "__builtin_mips_cmp_eq_ph", + "llvm.mips.cmp.le.ph" => "__builtin_mips_cmp_le_ph", + "llvm.mips.cmp.lt.ph" => "__builtin_mips_cmp_lt_ph", "llvm.mips.cmpgdu.eq.qb" => "__builtin_mips_cmpgdu_eq_qb", "llvm.mips.cmpgdu.le.qb" => "__builtin_mips_cmpgdu_le_qb", "llvm.mips.cmpgdu.lt.qb" => "__builtin_mips_cmpgdu_lt_qb", @@ -1107,10 +427,18 @@ match name { "llvm.mips.dpadd.u.d" => "__builtin_msa_dpadd_u_d", "llvm.mips.dpadd.u.h" => "__builtin_msa_dpadd_u_h", "llvm.mips.dpadd.u.w" => "__builtin_msa_dpadd_u_w", + "llvm.mips.dpaq.s.w.ph" => "__builtin_mips_dpaq_s_w_ph", + "llvm.mips.dpaq.sa.l.w" => "__builtin_mips_dpaq_sa_l_w", + "llvm.mips.dpaqx.s.w.ph" => "__builtin_mips_dpaqx_s_w_ph", + "llvm.mips.dpaqx.sa.w.ph" => "__builtin_mips_dpaqx_sa_w_ph", "llvm.mips.dpau.h.qbl" => "__builtin_mips_dpau_h_qbl", "llvm.mips.dpau.h.qbr" => "__builtin_mips_dpau_h_qbr", "llvm.mips.dpax.w.ph" => "__builtin_mips_dpax_w_ph", "llvm.mips.dps.w.ph" => "__builtin_mips_dps_w_ph", + "llvm.mips.dpsq.s.w.ph" => "__builtin_mips_dpsq_s_w_ph", + "llvm.mips.dpsq.sa.l.w" => "__builtin_mips_dpsq_sa_l_w", + "llvm.mips.dpsqx.s.w.ph" => "__builtin_mips_dpsqx_s_w_ph", + "llvm.mips.dpsqx.sa.w.ph" => "__builtin_mips_dpsqx_sa_w_ph", "llvm.mips.dpsu.h.qbl" => "__builtin_mips_dpsu_h_qbl", "llvm.mips.dpsu.h.qbr" => "__builtin_mips_dpsu_h_qbr", "llvm.mips.dpsub.s.d" => "__builtin_msa_dpsub_s_d", @@ -1154,11 +482,14 @@ match name { "llvm.mips.fcune.w" => "__builtin_msa_fcune_w", "llvm.mips.fdiv.d" => "__builtin_msa_fdiv_d", "llvm.mips.fdiv.w" => "__builtin_msa_fdiv_w", + "llvm.mips.fexdo.h" => "__builtin_msa_fexdo_h", "llvm.mips.fexdo.w" => "__builtin_msa_fexdo_w", "llvm.mips.fexp2.d" => "__builtin_msa_fexp2_d", "llvm.mips.fexp2.w" => "__builtin_msa_fexp2_w", "llvm.mips.fexupl.d" => "__builtin_msa_fexupl_d", + "llvm.mips.fexupl.w" => "__builtin_msa_fexupl_w", "llvm.mips.fexupr.d" => "__builtin_msa_fexupr_d", + "llvm.mips.fexupr.w" => "__builtin_msa_fexupr_w", "llvm.mips.ffint.s.d" => "__builtin_msa_ffint_s_d", "llvm.mips.ffint.s.w" => "__builtin_msa_ffint_s_w", "llvm.mips.ffint.u.d" => "__builtin_msa_ffint_u_d", @@ -1275,6 +606,8 @@ match name { "llvm.mips.ldi.d" => "__builtin_msa_ldi_d", "llvm.mips.ldi.h" => "__builtin_msa_ldi_h", "llvm.mips.ldi.w" => "__builtin_msa_ldi_w", + "llvm.mips.ldr.d" => "__builtin_msa_ldr_d", + "llvm.mips.ldr.w" => "__builtin_msa_ldr_w", "llvm.mips.lhx" => "__builtin_mips_lhx", "llvm.mips.lsa" => "__builtin_mips_lsa", "llvm.mips.lwx" => "__builtin_mips_lwx", @@ -1288,6 +621,10 @@ match name { "llvm.mips.maddv.d" => "__builtin_msa_maddv_d", "llvm.mips.maddv.h" => "__builtin_msa_maddv_h", "llvm.mips.maddv.w" => "__builtin_msa_maddv_w", + "llvm.mips.maq.s.w.phl" => "__builtin_mips_maq_s_w_phl", + "llvm.mips.maq.s.w.phr" => "__builtin_mips_maq_s_w_phr", + "llvm.mips.maq.sa.w.phl" => "__builtin_mips_maq_sa_w_phl", + "llvm.mips.maq.sa.w.phr" => "__builtin_mips_maq_sa_w_phr", "llvm.mips.max.a.b" => "__builtin_msa_max_a_b", "llvm.mips.max.a.d" => "__builtin_msa_max_a_d", "llvm.mips.max.a.h" => "__builtin_msa_max_a_h", @@ -1353,9 +690,18 @@ match name { "llvm.mips.mul.q.h" => "__builtin_msa_mul_q_h", "llvm.mips.mul.q.w" => "__builtin_msa_mul_q_w", "llvm.mips.mul.s.ph" => "__builtin_mips_mul_s_ph", + "llvm.mips.muleq.s.w.phl" => "__builtin_mips_muleq_s_w_phl", + "llvm.mips.muleq.s.w.phr" => "__builtin_mips_muleq_s_w_phr", + "llvm.mips.muleu.s.ph.qbl" => "__builtin_mips_muleu_s_ph_qbl", + "llvm.mips.muleu.s.ph.qbr" => "__builtin_mips_muleu_s_ph_qbr", + "llvm.mips.mulq.rs.ph" => "__builtin_mips_mulq_rs_ph", + "llvm.mips.mulq.rs.w" => "__builtin_mips_mulq_rs_w", + "llvm.mips.mulq.s.ph" => "__builtin_mips_mulq_s_ph", + "llvm.mips.mulq.s.w" => "__builtin_mips_mulq_s_w", "llvm.mips.mulr.q.h" => "__builtin_msa_mulr_q_h", "llvm.mips.mulr.q.w" => "__builtin_msa_mulr_q_w", "llvm.mips.mulsa.w.ph" => "__builtin_mips_mulsa_w_ph", + "llvm.mips.mulsaq.s.w.ph" => "__builtin_mips_mulsaq_s_w_ph", "llvm.mips.mult" => "__builtin_mips_mult", "llvm.mips.multu" => "__builtin_mips_multu", "llvm.mips.mulv.b" => "__builtin_msa_mulv_b", @@ -1374,6 +720,7 @@ match name { "llvm.mips.nori.b" => "__builtin_msa_nori_b", "llvm.mips.or.v" => "__builtin_msa_or_v", "llvm.mips.ori.b" => "__builtin_msa_ori_b", + "llvm.mips.packrl.ph" => "__builtin_mips_packrl_ph", "llvm.mips.pckev.b" => "__builtin_msa_pckev_b", "llvm.mips.pckev.d" => "__builtin_msa_pckev_d", "llvm.mips.pckev.h" => "__builtin_msa_pckev_h", @@ -1386,13 +733,29 @@ match name { "llvm.mips.pcnt.d" => "__builtin_msa_pcnt_d", "llvm.mips.pcnt.h" => "__builtin_msa_pcnt_h", "llvm.mips.pcnt.w" => "__builtin_msa_pcnt_w", + "llvm.mips.pick.ph" => "__builtin_mips_pick_ph", "llvm.mips.pick.qb" => "__builtin_mips_pick_qb", + "llvm.mips.preceq.w.phl" => "__builtin_mips_preceq_w_phl", + "llvm.mips.preceq.w.phr" => "__builtin_mips_preceq_w_phr", + "llvm.mips.precequ.ph.qbl" => "__builtin_mips_precequ_ph_qbl", + "llvm.mips.precequ.ph.qbla" => "__builtin_mips_precequ_ph_qbla", + "llvm.mips.precequ.ph.qbr" => "__builtin_mips_precequ_ph_qbr", + "llvm.mips.precequ.ph.qbra" => "__builtin_mips_precequ_ph_qbra", + "llvm.mips.preceu.ph.qbl" => "__builtin_mips_preceu_ph_qbl", + "llvm.mips.preceu.ph.qbla" => "__builtin_mips_preceu_ph_qbla", + "llvm.mips.preceu.ph.qbr" => "__builtin_mips_preceu_ph_qbr", + "llvm.mips.preceu.ph.qbra" => "__builtin_mips_preceu_ph_qbra", "llvm.mips.precr.qb.ph" => "__builtin_mips_precr_qb_ph", "llvm.mips.precr.sra.ph.w" => "__builtin_mips_precr_sra_ph_w", "llvm.mips.precr.sra.r.ph.w" => "__builtin_mips_precr_sra_r_ph_w", + "llvm.mips.precrq.ph.w" => "__builtin_mips_precrq_ph_w", + "llvm.mips.precrq.qb.ph" => "__builtin_mips_precrq_qb_ph", + "llvm.mips.precrq.rs.ph.w" => "__builtin_mips_precrq_rs_ph_w", + "llvm.mips.precrqu.s.qb.ph" => "__builtin_mips_precrqu_s_qb_ph", "llvm.mips.prepend" => "__builtin_mips_prepend", "llvm.mips.raddu.w.qb" => "__builtin_mips_raddu_w_qb", "llvm.mips.rddsp" => "__builtin_mips_rddsp", + "llvm.mips.repl.ph" => "__builtin_mips_repl_ph", "llvm.mips.repl.qb" => "__builtin_mips_repl_qb", "llvm.mips.sat.s.b" => "__builtin_msa_sat_s_b", "llvm.mips.sat.s.d" => "__builtin_msa_sat_s_d", @@ -1406,9 +769,15 @@ match name { "llvm.mips.shf.h" => "__builtin_msa_shf_h", "llvm.mips.shf.w" => "__builtin_msa_shf_w", "llvm.mips.shilo" => "__builtin_mips_shilo", + "llvm.mips.shll.ph" => "__builtin_mips_shll_ph", "llvm.mips.shll.qb" => "__builtin_mips_shll_qb", + "llvm.mips.shll.s.ph" => "__builtin_mips_shll_s_ph", + "llvm.mips.shll.s.w" => "__builtin_mips_shll_s_w", + "llvm.mips.shra.ph" => "__builtin_mips_shra_ph", "llvm.mips.shra.qb" => "__builtin_mips_shra_qb", + "llvm.mips.shra.r.ph" => "__builtin_mips_shra_r_ph", "llvm.mips.shra.r.qb" => "__builtin_mips_shra_r_qb", + "llvm.mips.shra.r.w" => "__builtin_mips_shra_r_w", "llvm.mips.shrl.ph" => "__builtin_mips_shrl_ph", "llvm.mips.shrl.qb" => "__builtin_mips_shrl_qb", "llvm.mips.sld.b" => "__builtin_msa_sld_b", @@ -1471,6 +840,15 @@ match name { "llvm.mips.st.d" => "__builtin_msa_st_d", "llvm.mips.st.h" => "__builtin_msa_st_h", "llvm.mips.st.w" => "__builtin_msa_st_w", + "llvm.mips.str.d" => "__builtin_msa_str_d", + "llvm.mips.str.w" => "__builtin_msa_str_w", + "llvm.mips.subq.ph" => "__builtin_mips_subq_ph", + "llvm.mips.subq.s.ph" => "__builtin_mips_subq_s_ph", + "llvm.mips.subq.s.w" => "__builtin_mips_subq_s_w", + "llvm.mips.subqh.ph" => "__builtin_mips_subqh_ph", + "llvm.mips.subqh.r.ph" => "__builtin_mips_subqh_r_ph", + "llvm.mips.subqh.r.w" => "__builtin_mips_subqh_r_w", + "llvm.mips.subqh.w" => "__builtin_mips_subqh_w", "llvm.mips.subs.s.b" => "__builtin_msa_subs_s_b", "llvm.mips.subs.s.d" => "__builtin_msa_subs_s_d", "llvm.mips.subs.s.h" => "__builtin_msa_subs_s_h", @@ -1509,532 +887,15 @@ match name { "llvm.mips.xor.v" => "__builtin_msa_xor_v", "llvm.mips.xori.b" => "__builtin_msa_xori_b", // nvvm - "llvm.nvvm.abs.i" => "__nvvm_abs_i", - "llvm.nvvm.abs.ll" => "__nvvm_abs_ll", - "llvm.nvvm.add.rm.d" => "__nvvm_add_rm_d", - "llvm.nvvm.add.rm.f" => "__nvvm_add_rm_f", - "llvm.nvvm.add.rm.ftz.f" => "__nvvm_add_rm_ftz_f", - "llvm.nvvm.add.rn.d" => "__nvvm_add_rn_d", - "llvm.nvvm.add.rn.f" => "__nvvm_add_rn_f", - "llvm.nvvm.add.rn.ftz.f" => "__nvvm_add_rn_ftz_f", - "llvm.nvvm.add.rp.d" => "__nvvm_add_rp_d", - "llvm.nvvm.add.rp.f" => "__nvvm_add_rp_f", - "llvm.nvvm.add.rp.ftz.f" => "__nvvm_add_rp_ftz_f", - "llvm.nvvm.add.rz.d" => "__nvvm_add_rz_d", - "llvm.nvvm.add.rz.f" => "__nvvm_add_rz_f", - "llvm.nvvm.add.rz.ftz.f" => "__nvvm_add_rz_ftz_f", - "llvm.nvvm.barrier0" => "__nvvm_bar0", - "llvm.nvvm.barrier0.and" => "__nvvm_bar0_and", - "llvm.nvvm.barrier0.or" => "__nvvm_bar0_or", - "llvm.nvvm.barrier0.popc" => "__nvvm_bar0_popc", - "llvm.nvvm.bitcast.d2ll" => "__nvvm_bitcast_d2ll", - "llvm.nvvm.bitcast.f2i" => "__nvvm_bitcast_f2i", - "llvm.nvvm.bitcast.i2f" => "__nvvm_bitcast_i2f", - "llvm.nvvm.bitcast.ll2d" => "__nvvm_bitcast_ll2d", - "llvm.nvvm.brev32" => "__nvvm_brev32", - "llvm.nvvm.brev64" => "__nvvm_brev64", - "llvm.nvvm.ceil.d" => "__nvvm_ceil_d", - "llvm.nvvm.ceil.f" => "__nvvm_ceil_f", - "llvm.nvvm.ceil.ftz.f" => "__nvvm_ceil_ftz_f", - "llvm.nvvm.clz.i" => "__nvvm_clz_i", - "llvm.nvvm.clz.ll" => "__nvvm_clz_ll", - "llvm.nvvm.cos.approx.f" => "__nvvm_cos_approx_f", - "llvm.nvvm.cos.approx.ftz.f" => "__nvvm_cos_approx_ftz_f", - "llvm.nvvm.d2f.rm" => "__nvvm_d2f_rm", - "llvm.nvvm.d2f.rm.ftz" => "__nvvm_d2f_rm_ftz", - "llvm.nvvm.d2f.rn" => "__nvvm_d2f_rn", - "llvm.nvvm.d2f.rn.ftz" => "__nvvm_d2f_rn_ftz", - "llvm.nvvm.d2f.rp" => "__nvvm_d2f_rp", - "llvm.nvvm.d2f.rp.ftz" => "__nvvm_d2f_rp_ftz", - "llvm.nvvm.d2f.rz" => "__nvvm_d2f_rz", - "llvm.nvvm.d2f.rz.ftz" => "__nvvm_d2f_rz_ftz", - "llvm.nvvm.d2i.hi" => "__nvvm_d2i_hi", - "llvm.nvvm.d2i.lo" => "__nvvm_d2i_lo", - "llvm.nvvm.d2i.rm" => "__nvvm_d2i_rm", - "llvm.nvvm.d2i.rn" => "__nvvm_d2i_rn", - "llvm.nvvm.d2i.rp" => "__nvvm_d2i_rp", - "llvm.nvvm.d2i.rz" => "__nvvm_d2i_rz", - "llvm.nvvm.d2ll.rm" => "__nvvm_d2ll_rm", - "llvm.nvvm.d2ll.rn" => "__nvvm_d2ll_rn", - "llvm.nvvm.d2ll.rp" => "__nvvm_d2ll_rp", - "llvm.nvvm.d2ll.rz" => "__nvvm_d2ll_rz", - "llvm.nvvm.d2ui.rm" => "__nvvm_d2ui_rm", - "llvm.nvvm.d2ui.rn" => "__nvvm_d2ui_rn", - "llvm.nvvm.d2ui.rp" => "__nvvm_d2ui_rp", - "llvm.nvvm.d2ui.rz" => "__nvvm_d2ui_rz", - "llvm.nvvm.d2ull.rm" => "__nvvm_d2ull_rm", - "llvm.nvvm.d2ull.rn" => "__nvvm_d2ull_rn", - "llvm.nvvm.d2ull.rp" => "__nvvm_d2ull_rp", - "llvm.nvvm.d2ull.rz" => "__nvvm_d2ull_rz", - "llvm.nvvm.div.approx.f" => "__nvvm_div_approx_f", - "llvm.nvvm.div.approx.ftz.f" => "__nvvm_div_approx_ftz_f", - "llvm.nvvm.div.rm.d" => "__nvvm_div_rm_d", - "llvm.nvvm.div.rm.f" => "__nvvm_div_rm_f", - "llvm.nvvm.div.rm.ftz.f" => "__nvvm_div_rm_ftz_f", - "llvm.nvvm.div.rn.d" => "__nvvm_div_rn_d", - "llvm.nvvm.div.rn.f" => "__nvvm_div_rn_f", - "llvm.nvvm.div.rn.ftz.f" => "__nvvm_div_rn_ftz_f", - "llvm.nvvm.div.rp.d" => "__nvvm_div_rp_d", - "llvm.nvvm.div.rp.f" => "__nvvm_div_rp_f", - "llvm.nvvm.div.rp.ftz.f" => "__nvvm_div_rp_ftz_f", - "llvm.nvvm.div.rz.d" => "__nvvm_div_rz_d", - "llvm.nvvm.div.rz.f" => "__nvvm_div_rz_f", - "llvm.nvvm.div.rz.ftz.f" => "__nvvm_div_rz_ftz_f", - "llvm.nvvm.ex2.approx.d" => "__nvvm_ex2_approx_d", - "llvm.nvvm.ex2.approx.f" => "__nvvm_ex2_approx_f", - "llvm.nvvm.ex2.approx.ftz.f" => "__nvvm_ex2_approx_ftz_f", - "llvm.nvvm.f2h.rn" => "__nvvm_f2h_rn", - "llvm.nvvm.f2h.rn.ftz" => "__nvvm_f2h_rn_ftz", - "llvm.nvvm.f2i.rm" => "__nvvm_f2i_rm", - "llvm.nvvm.f2i.rm.ftz" => "__nvvm_f2i_rm_ftz", - "llvm.nvvm.f2i.rn" => "__nvvm_f2i_rn", - "llvm.nvvm.f2i.rn.ftz" => "__nvvm_f2i_rn_ftz", - "llvm.nvvm.f2i.rp" => "__nvvm_f2i_rp", - "llvm.nvvm.f2i.rp.ftz" => "__nvvm_f2i_rp_ftz", - "llvm.nvvm.f2i.rz" => "__nvvm_f2i_rz", - "llvm.nvvm.f2i.rz.ftz" => "__nvvm_f2i_rz_ftz", - "llvm.nvvm.f2ll.rm" => "__nvvm_f2ll_rm", - "llvm.nvvm.f2ll.rm.ftz" => "__nvvm_f2ll_rm_ftz", - "llvm.nvvm.f2ll.rn" => "__nvvm_f2ll_rn", - "llvm.nvvm.f2ll.rn.ftz" => "__nvvm_f2ll_rn_ftz", - "llvm.nvvm.f2ll.rp" => "__nvvm_f2ll_rp", - "llvm.nvvm.f2ll.rp.ftz" => "__nvvm_f2ll_rp_ftz", - "llvm.nvvm.f2ll.rz" => "__nvvm_f2ll_rz", - "llvm.nvvm.f2ll.rz.ftz" => "__nvvm_f2ll_rz_ftz", - "llvm.nvvm.f2ui.rm" => "__nvvm_f2ui_rm", - "llvm.nvvm.f2ui.rm.ftz" => "__nvvm_f2ui_rm_ftz", - "llvm.nvvm.f2ui.rn" => "__nvvm_f2ui_rn", - "llvm.nvvm.f2ui.rn.ftz" => "__nvvm_f2ui_rn_ftz", - "llvm.nvvm.f2ui.rp" => "__nvvm_f2ui_rp", - "llvm.nvvm.f2ui.rp.ftz" => "__nvvm_f2ui_rp_ftz", - "llvm.nvvm.f2ui.rz" => "__nvvm_f2ui_rz", - "llvm.nvvm.f2ui.rz.ftz" => "__nvvm_f2ui_rz_ftz", - "llvm.nvvm.f2ull.rm" => "__nvvm_f2ull_rm", - "llvm.nvvm.f2ull.rm.ftz" => "__nvvm_f2ull_rm_ftz", - "llvm.nvvm.f2ull.rn" => "__nvvm_f2ull_rn", - "llvm.nvvm.f2ull.rn.ftz" => "__nvvm_f2ull_rn_ftz", - "llvm.nvvm.f2ull.rp" => "__nvvm_f2ull_rp", - "llvm.nvvm.f2ull.rp.ftz" => "__nvvm_f2ull_rp_ftz", - "llvm.nvvm.f2ull.rz" => "__nvvm_f2ull_rz", - "llvm.nvvm.f2ull.rz.ftz" => "__nvvm_f2ull_rz_ftz", - "llvm.nvvm.fabs.d" => "__nvvm_fabs_d", - "llvm.nvvm.fabs.f" => "__nvvm_fabs_f", - "llvm.nvvm.fabs.ftz.f" => "__nvvm_fabs_ftz_f", - "llvm.nvvm.floor.d" => "__nvvm_floor_d", - "llvm.nvvm.floor.f" => "__nvvm_floor_f", - "llvm.nvvm.floor.ftz.f" => "__nvvm_floor_ftz_f", - "llvm.nvvm.fma.rm.d" => "__nvvm_fma_rm_d", - "llvm.nvvm.fma.rm.f" => "__nvvm_fma_rm_f", - "llvm.nvvm.fma.rm.ftz.f" => "__nvvm_fma_rm_ftz_f", - "llvm.nvvm.fma.rn.d" => "__nvvm_fma_rn_d", - "llvm.nvvm.fma.rn.f" => "__nvvm_fma_rn_f", - "llvm.nvvm.fma.rn.ftz.f" => "__nvvm_fma_rn_ftz_f", - "llvm.nvvm.fma.rp.d" => "__nvvm_fma_rp_d", - "llvm.nvvm.fma.rp.f" => "__nvvm_fma_rp_f", - "llvm.nvvm.fma.rp.ftz.f" => "__nvvm_fma_rp_ftz_f", - "llvm.nvvm.fma.rz.d" => "__nvvm_fma_rz_d", - "llvm.nvvm.fma.rz.f" => "__nvvm_fma_rz_f", - "llvm.nvvm.fma.rz.ftz.f" => "__nvvm_fma_rz_ftz_f", - "llvm.nvvm.fmax.d" => "__nvvm_fmax_d", - "llvm.nvvm.fmax.f" => "__nvvm_fmax_f", - "llvm.nvvm.fmax.ftz.f" => "__nvvm_fmax_ftz_f", - "llvm.nvvm.fmin.d" => "__nvvm_fmin_d", - "llvm.nvvm.fmin.f" => "__nvvm_fmin_f", - "llvm.nvvm.fmin.ftz.f" => "__nvvm_fmin_ftz_f", - "llvm.nvvm.h2f" => "__nvvm_h2f", - "llvm.nvvm.i2d.rm" => "__nvvm_i2d_rm", - "llvm.nvvm.i2d.rn" => "__nvvm_i2d_rn", - "llvm.nvvm.i2d.rp" => "__nvvm_i2d_rp", - "llvm.nvvm.i2d.rz" => "__nvvm_i2d_rz", - "llvm.nvvm.i2f.rm" => "__nvvm_i2f_rm", - "llvm.nvvm.i2f.rn" => "__nvvm_i2f_rn", - "llvm.nvvm.i2f.rp" => "__nvvm_i2f_rp", - "llvm.nvvm.i2f.rz" => "__nvvm_i2f_rz", - "llvm.nvvm.isspacep.const" => "__nvvm_isspacep_const", - "llvm.nvvm.isspacep.global" => "__nvvm_isspacep_global", - "llvm.nvvm.isspacep.local" => "__nvvm_isspacep_local", - "llvm.nvvm.isspacep.shared" => "__nvvm_isspacep_shared", - "llvm.nvvm.istypep.sampler" => "__nvvm_istypep_sampler", - "llvm.nvvm.istypep.surface" => "__nvvm_istypep_surface", - "llvm.nvvm.istypep.texture" => "__nvvm_istypep_texture", - "llvm.nvvm.lg2.approx.d" => "__nvvm_lg2_approx_d", - "llvm.nvvm.lg2.approx.f" => "__nvvm_lg2_approx_f", - "llvm.nvvm.lg2.approx.ftz.f" => "__nvvm_lg2_approx_ftz_f", - "llvm.nvvm.ll2d.rm" => "__nvvm_ll2d_rm", - "llvm.nvvm.ll2d.rn" => "__nvvm_ll2d_rn", - "llvm.nvvm.ll2d.rp" => "__nvvm_ll2d_rp", - "llvm.nvvm.ll2d.rz" => "__nvvm_ll2d_rz", - "llvm.nvvm.ll2f.rm" => "__nvvm_ll2f_rm", - "llvm.nvvm.ll2f.rn" => "__nvvm_ll2f_rn", - "llvm.nvvm.ll2f.rp" => "__nvvm_ll2f_rp", - "llvm.nvvm.ll2f.rz" => "__nvvm_ll2f_rz", - "llvm.nvvm.lohi.i2d" => "__nvvm_lohi_i2d", - "llvm.nvvm.max.i" => "__nvvm_max_i", - "llvm.nvvm.max.ll" => "__nvvm_max_ll", - "llvm.nvvm.max.ui" => "__nvvm_max_ui", - "llvm.nvvm.max.ull" => "__nvvm_max_ull", - "llvm.nvvm.membar.cta" => "__nvvm_membar_cta", - "llvm.nvvm.membar.gl" => "__nvvm_membar_gl", - "llvm.nvvm.membar.sys" => "__nvvm_membar_sys", - "llvm.nvvm.min.i" => "__nvvm_min_i", - "llvm.nvvm.min.ll" => "__nvvm_min_ll", - "llvm.nvvm.min.ui" => "__nvvm_min_ui", - "llvm.nvvm.min.ull" => "__nvvm_min_ull", - "llvm.nvvm.mul.rm.d" => "__nvvm_mul_rm_d", - "llvm.nvvm.mul.rm.f" => "__nvvm_mul_rm_f", - "llvm.nvvm.mul.rm.ftz.f" => "__nvvm_mul_rm_ftz_f", - "llvm.nvvm.mul.rn.d" => "__nvvm_mul_rn_d", - "llvm.nvvm.mul.rn.f" => "__nvvm_mul_rn_f", - "llvm.nvvm.mul.rn.ftz.f" => "__nvvm_mul_rn_ftz_f", - "llvm.nvvm.mul.rp.d" => "__nvvm_mul_rp_d", - "llvm.nvvm.mul.rp.f" => "__nvvm_mul_rp_f", - "llvm.nvvm.mul.rp.ftz.f" => "__nvvm_mul_rp_ftz_f", - "llvm.nvvm.mul.rz.d" => "__nvvm_mul_rz_d", - "llvm.nvvm.mul.rz.f" => "__nvvm_mul_rz_f", - "llvm.nvvm.mul.rz.ftz.f" => "__nvvm_mul_rz_ftz_f", - "llvm.nvvm.mul24.i" => "__nvvm_mul24_i", - "llvm.nvvm.mul24.ui" => "__nvvm_mul24_ui", - "llvm.nvvm.mulhi.i" => "__nvvm_mulhi_i", - "llvm.nvvm.mulhi.ll" => "__nvvm_mulhi_ll", - "llvm.nvvm.mulhi.ui" => "__nvvm_mulhi_ui", - "llvm.nvvm.mulhi.ull" => "__nvvm_mulhi_ull", - "llvm.nvvm.popc.i" => "__nvvm_popc_i", - "llvm.nvvm.popc.ll" => "__nvvm_popc_ll", "llvm.nvvm.prmt" => "__nvvm_prmt", - "llvm.nvvm.rcp.approx.ftz.d" => "__nvvm_rcp_approx_ftz_d", - "llvm.nvvm.rcp.rm.d" => "__nvvm_rcp_rm_d", - "llvm.nvvm.rcp.rm.f" => "__nvvm_rcp_rm_f", - "llvm.nvvm.rcp.rm.ftz.f" => "__nvvm_rcp_rm_ftz_f", - "llvm.nvvm.rcp.rn.d" => "__nvvm_rcp_rn_d", - "llvm.nvvm.rcp.rn.f" => "__nvvm_rcp_rn_f", - "llvm.nvvm.rcp.rn.ftz.f" => "__nvvm_rcp_rn_ftz_f", - "llvm.nvvm.rcp.rp.d" => "__nvvm_rcp_rp_d", - "llvm.nvvm.rcp.rp.f" => "__nvvm_rcp_rp_f", - "llvm.nvvm.rcp.rp.ftz.f" => "__nvvm_rcp_rp_ftz_f", - "llvm.nvvm.rcp.rz.d" => "__nvvm_rcp_rz_d", - "llvm.nvvm.rcp.rz.f" => "__nvvm_rcp_rz_f", - "llvm.nvvm.rcp.rz.ftz.f" => "__nvvm_rcp_rz_ftz_f", - "llvm.nvvm.read.ptx.sreg.ctaid.x" => "__nvvm_read_ptx_sreg_ctaid_x", - "llvm.nvvm.read.ptx.sreg.ctaid.y" => "__nvvm_read_ptx_sreg_ctaid_y", - "llvm.nvvm.read.ptx.sreg.ctaid.z" => "__nvvm_read_ptx_sreg_ctaid_z", - "llvm.nvvm.read.ptx.sreg.envreg0" => "__nvvm_read_ptx_sreg_envreg0", - "llvm.nvvm.read.ptx.sreg.envreg1" => "__nvvm_read_ptx_sreg_envreg1", - "llvm.nvvm.read.ptx.sreg.envreg10" => "__nvvm_read_ptx_sreg_envreg10", - "llvm.nvvm.read.ptx.sreg.envreg11" => "__nvvm_read_ptx_sreg_envreg11", - "llvm.nvvm.read.ptx.sreg.envreg12" => "__nvvm_read_ptx_sreg_envreg12", - "llvm.nvvm.read.ptx.sreg.envreg13" => "__nvvm_read_ptx_sreg_envreg13", - "llvm.nvvm.read.ptx.sreg.envreg14" => "__nvvm_read_ptx_sreg_envreg14", - "llvm.nvvm.read.ptx.sreg.envreg15" => "__nvvm_read_ptx_sreg_envreg15", - "llvm.nvvm.read.ptx.sreg.envreg16" => "__nvvm_read_ptx_sreg_envreg16", - "llvm.nvvm.read.ptx.sreg.envreg17" => "__nvvm_read_ptx_sreg_envreg17", - "llvm.nvvm.read.ptx.sreg.envreg18" => "__nvvm_read_ptx_sreg_envreg18", - "llvm.nvvm.read.ptx.sreg.envreg19" => "__nvvm_read_ptx_sreg_envreg19", - "llvm.nvvm.read.ptx.sreg.envreg2" => "__nvvm_read_ptx_sreg_envreg2", - "llvm.nvvm.read.ptx.sreg.envreg20" => "__nvvm_read_ptx_sreg_envreg20", - "llvm.nvvm.read.ptx.sreg.envreg21" => "__nvvm_read_ptx_sreg_envreg21", - "llvm.nvvm.read.ptx.sreg.envreg22" => "__nvvm_read_ptx_sreg_envreg22", - "llvm.nvvm.read.ptx.sreg.envreg23" => "__nvvm_read_ptx_sreg_envreg23", - "llvm.nvvm.read.ptx.sreg.envreg24" => "__nvvm_read_ptx_sreg_envreg24", - "llvm.nvvm.read.ptx.sreg.envreg25" => "__nvvm_read_ptx_sreg_envreg25", - "llvm.nvvm.read.ptx.sreg.envreg26" => "__nvvm_read_ptx_sreg_envreg26", - "llvm.nvvm.read.ptx.sreg.envreg27" => "__nvvm_read_ptx_sreg_envreg27", - "llvm.nvvm.read.ptx.sreg.envreg28" => "__nvvm_read_ptx_sreg_envreg28", - "llvm.nvvm.read.ptx.sreg.envreg29" => "__nvvm_read_ptx_sreg_envreg29", - "llvm.nvvm.read.ptx.sreg.envreg3" => "__nvvm_read_ptx_sreg_envreg3", - "llvm.nvvm.read.ptx.sreg.envreg30" => "__nvvm_read_ptx_sreg_envreg30", - "llvm.nvvm.read.ptx.sreg.envreg31" => "__nvvm_read_ptx_sreg_envreg31", - "llvm.nvvm.read.ptx.sreg.envreg4" => "__nvvm_read_ptx_sreg_envreg4", - "llvm.nvvm.read.ptx.sreg.envreg5" => "__nvvm_read_ptx_sreg_envreg5", - "llvm.nvvm.read.ptx.sreg.envreg6" => "__nvvm_read_ptx_sreg_envreg6", - "llvm.nvvm.read.ptx.sreg.envreg7" => "__nvvm_read_ptx_sreg_envreg7", - "llvm.nvvm.read.ptx.sreg.envreg8" => "__nvvm_read_ptx_sreg_envreg8", - "llvm.nvvm.read.ptx.sreg.envreg9" => "__nvvm_read_ptx_sreg_envreg9", - "llvm.nvvm.read.ptx.sreg.nctaid.x" => "__nvvm_read_ptx_sreg_nctaid_x", - "llvm.nvvm.read.ptx.sreg.nctaid.y" => "__nvvm_read_ptx_sreg_nctaid_y", - "llvm.nvvm.read.ptx.sreg.nctaid.z" => "__nvvm_read_ptx_sreg_nctaid_z", - "llvm.nvvm.read.ptx.sreg.ntid.x" => "__nvvm_read_ptx_sreg_ntid_x", - "llvm.nvvm.read.ptx.sreg.ntid.y" => "__nvvm_read_ptx_sreg_ntid_y", - "llvm.nvvm.read.ptx.sreg.ntid.z" => "__nvvm_read_ptx_sreg_ntid_z", - "llvm.nvvm.read.ptx.sreg.tid.x" => "__nvvm_read_ptx_sreg_tid_x", - "llvm.nvvm.read.ptx.sreg.tid.y" => "__nvvm_read_ptx_sreg_tid_y", - "llvm.nvvm.read.ptx.sreg.tid.z" => "__nvvm_read_ptx_sreg_tid_z", - "llvm.nvvm.read.ptx.sreg.warpsize" => "__nvvm_read_ptx_sreg_warpsize", - "llvm.nvvm.rotate.b32" => "__nvvm_rotate_b32", - "llvm.nvvm.rotate.b64" => "__nvvm_rotate_b64", - "llvm.nvvm.rotate.right.b64" => "__nvvm_rotate_right_b64", - "llvm.nvvm.round.d" => "__nvvm_round_d", - "llvm.nvvm.round.f" => "__nvvm_round_f", - "llvm.nvvm.round.ftz.f" => "__nvvm_round_ftz_f", - "llvm.nvvm.rsqrt.approx.d" => "__nvvm_rsqrt_approx_d", - "llvm.nvvm.rsqrt.approx.f" => "__nvvm_rsqrt_approx_f", - "llvm.nvvm.rsqrt.approx.ftz.f" => "__nvvm_rsqrt_approx_ftz_f", - "llvm.nvvm.sad.i" => "__nvvm_sad_i", - "llvm.nvvm.sad.ui" => "__nvvm_sad_ui", - "llvm.nvvm.saturate.d" => "__nvvm_saturate_d", - "llvm.nvvm.saturate.f" => "__nvvm_saturate_f", - "llvm.nvvm.saturate.ftz.f" => "__nvvm_saturate_ftz_f", - "llvm.nvvm.sin.approx.f" => "__nvvm_sin_approx_f", - "llvm.nvvm.sin.approx.ftz.f" => "__nvvm_sin_approx_ftz_f", - "llvm.nvvm.sqrt.approx.f" => "__nvvm_sqrt_approx_f", - "llvm.nvvm.sqrt.approx.ftz.f" => "__nvvm_sqrt_approx_ftz_f", - "llvm.nvvm.sqrt.f" => "__nvvm_sqrt_f", - "llvm.nvvm.sqrt.rm.d" => "__nvvm_sqrt_rm_d", - "llvm.nvvm.sqrt.rm.f" => "__nvvm_sqrt_rm_f", - "llvm.nvvm.sqrt.rm.ftz.f" => "__nvvm_sqrt_rm_ftz_f", - "llvm.nvvm.sqrt.rn.d" => "__nvvm_sqrt_rn_d", - "llvm.nvvm.sqrt.rn.f" => "__nvvm_sqrt_rn_f", - "llvm.nvvm.sqrt.rn.ftz.f" => "__nvvm_sqrt_rn_ftz_f", - "llvm.nvvm.sqrt.rp.d" => "__nvvm_sqrt_rp_d", - "llvm.nvvm.sqrt.rp.f" => "__nvvm_sqrt_rp_f", - "llvm.nvvm.sqrt.rp.ftz.f" => "__nvvm_sqrt_rp_ftz_f", - "llvm.nvvm.sqrt.rz.d" => "__nvvm_sqrt_rz_d", - "llvm.nvvm.sqrt.rz.f" => "__nvvm_sqrt_rz_f", - "llvm.nvvm.sqrt.rz.ftz.f" => "__nvvm_sqrt_rz_ftz_f", - "llvm.nvvm.suq.array.size" => "__nvvm_suq_array_size", - "llvm.nvvm.suq.channel.data.type" => "__nvvm_suq_channel_data_type", - "llvm.nvvm.suq.channel.order" => "__nvvm_suq_channel_order", - "llvm.nvvm.suq.depth" => "__nvvm_suq_depth", - "llvm.nvvm.suq.height" => "__nvvm_suq_height", - "llvm.nvvm.suq.width" => "__nvvm_suq_width", - "llvm.nvvm.sust.b.1d.array.i16.clamp" => "__nvvm_sust_b_1d_array_i16_clamp", - "llvm.nvvm.sust.b.1d.array.i16.trap" => "__nvvm_sust_b_1d_array_i16_trap", - "llvm.nvvm.sust.b.1d.array.i16.zero" => "__nvvm_sust_b_1d_array_i16_zero", - "llvm.nvvm.sust.b.1d.array.i32.clamp" => "__nvvm_sust_b_1d_array_i32_clamp", - "llvm.nvvm.sust.b.1d.array.i32.trap" => "__nvvm_sust_b_1d_array_i32_trap", - "llvm.nvvm.sust.b.1d.array.i32.zero" => "__nvvm_sust_b_1d_array_i32_zero", - "llvm.nvvm.sust.b.1d.array.i64.clamp" => "__nvvm_sust_b_1d_array_i64_clamp", - "llvm.nvvm.sust.b.1d.array.i64.trap" => "__nvvm_sust_b_1d_array_i64_trap", - "llvm.nvvm.sust.b.1d.array.i64.zero" => "__nvvm_sust_b_1d_array_i64_zero", - "llvm.nvvm.sust.b.1d.array.i8.clamp" => "__nvvm_sust_b_1d_array_i8_clamp", - "llvm.nvvm.sust.b.1d.array.i8.trap" => "__nvvm_sust_b_1d_array_i8_trap", - "llvm.nvvm.sust.b.1d.array.i8.zero" => "__nvvm_sust_b_1d_array_i8_zero", - "llvm.nvvm.sust.b.1d.array.v2i16.clamp" => "__nvvm_sust_b_1d_array_v2i16_clamp", - "llvm.nvvm.sust.b.1d.array.v2i16.trap" => "__nvvm_sust_b_1d_array_v2i16_trap", - "llvm.nvvm.sust.b.1d.array.v2i16.zero" => "__nvvm_sust_b_1d_array_v2i16_zero", - "llvm.nvvm.sust.b.1d.array.v2i32.clamp" => "__nvvm_sust_b_1d_array_v2i32_clamp", - "llvm.nvvm.sust.b.1d.array.v2i32.trap" => "__nvvm_sust_b_1d_array_v2i32_trap", - "llvm.nvvm.sust.b.1d.array.v2i32.zero" => "__nvvm_sust_b_1d_array_v2i32_zero", - "llvm.nvvm.sust.b.1d.array.v2i64.clamp" => "__nvvm_sust_b_1d_array_v2i64_clamp", - "llvm.nvvm.sust.b.1d.array.v2i64.trap" => "__nvvm_sust_b_1d_array_v2i64_trap", - "llvm.nvvm.sust.b.1d.array.v2i64.zero" => "__nvvm_sust_b_1d_array_v2i64_zero", - "llvm.nvvm.sust.b.1d.array.v2i8.clamp" => "__nvvm_sust_b_1d_array_v2i8_clamp", - "llvm.nvvm.sust.b.1d.array.v2i8.trap" => "__nvvm_sust_b_1d_array_v2i8_trap", - "llvm.nvvm.sust.b.1d.array.v2i8.zero" => "__nvvm_sust_b_1d_array_v2i8_zero", - "llvm.nvvm.sust.b.1d.array.v4i16.clamp" => "__nvvm_sust_b_1d_array_v4i16_clamp", - "llvm.nvvm.sust.b.1d.array.v4i16.trap" => "__nvvm_sust_b_1d_array_v4i16_trap", - "llvm.nvvm.sust.b.1d.array.v4i16.zero" => "__nvvm_sust_b_1d_array_v4i16_zero", - "llvm.nvvm.sust.b.1d.array.v4i32.clamp" => "__nvvm_sust_b_1d_array_v4i32_clamp", - "llvm.nvvm.sust.b.1d.array.v4i32.trap" => "__nvvm_sust_b_1d_array_v4i32_trap", - "llvm.nvvm.sust.b.1d.array.v4i32.zero" => "__nvvm_sust_b_1d_array_v4i32_zero", - "llvm.nvvm.sust.b.1d.array.v4i8.clamp" => "__nvvm_sust_b_1d_array_v4i8_clamp", - "llvm.nvvm.sust.b.1d.array.v4i8.trap" => "__nvvm_sust_b_1d_array_v4i8_trap", - "llvm.nvvm.sust.b.1d.array.v4i8.zero" => "__nvvm_sust_b_1d_array_v4i8_zero", - "llvm.nvvm.sust.b.1d.i16.clamp" => "__nvvm_sust_b_1d_i16_clamp", - "llvm.nvvm.sust.b.1d.i16.trap" => "__nvvm_sust_b_1d_i16_trap", - "llvm.nvvm.sust.b.1d.i16.zero" => "__nvvm_sust_b_1d_i16_zero", - "llvm.nvvm.sust.b.1d.i32.clamp" => "__nvvm_sust_b_1d_i32_clamp", - "llvm.nvvm.sust.b.1d.i32.trap" => "__nvvm_sust_b_1d_i32_trap", - "llvm.nvvm.sust.b.1d.i32.zero" => "__nvvm_sust_b_1d_i32_zero", - "llvm.nvvm.sust.b.1d.i64.clamp" => "__nvvm_sust_b_1d_i64_clamp", - "llvm.nvvm.sust.b.1d.i64.trap" => "__nvvm_sust_b_1d_i64_trap", - "llvm.nvvm.sust.b.1d.i64.zero" => "__nvvm_sust_b_1d_i64_zero", - "llvm.nvvm.sust.b.1d.i8.clamp" => "__nvvm_sust_b_1d_i8_clamp", - "llvm.nvvm.sust.b.1d.i8.trap" => "__nvvm_sust_b_1d_i8_trap", - "llvm.nvvm.sust.b.1d.i8.zero" => "__nvvm_sust_b_1d_i8_zero", - "llvm.nvvm.sust.b.1d.v2i16.clamp" => "__nvvm_sust_b_1d_v2i16_clamp", - "llvm.nvvm.sust.b.1d.v2i16.trap" => "__nvvm_sust_b_1d_v2i16_trap", - "llvm.nvvm.sust.b.1d.v2i16.zero" => "__nvvm_sust_b_1d_v2i16_zero", - "llvm.nvvm.sust.b.1d.v2i32.clamp" => "__nvvm_sust_b_1d_v2i32_clamp", - "llvm.nvvm.sust.b.1d.v2i32.trap" => "__nvvm_sust_b_1d_v2i32_trap", - "llvm.nvvm.sust.b.1d.v2i32.zero" => "__nvvm_sust_b_1d_v2i32_zero", - "llvm.nvvm.sust.b.1d.v2i64.clamp" => "__nvvm_sust_b_1d_v2i64_clamp", - "llvm.nvvm.sust.b.1d.v2i64.trap" => "__nvvm_sust_b_1d_v2i64_trap", - "llvm.nvvm.sust.b.1d.v2i64.zero" => "__nvvm_sust_b_1d_v2i64_zero", - "llvm.nvvm.sust.b.1d.v2i8.clamp" => "__nvvm_sust_b_1d_v2i8_clamp", - "llvm.nvvm.sust.b.1d.v2i8.trap" => "__nvvm_sust_b_1d_v2i8_trap", - "llvm.nvvm.sust.b.1d.v2i8.zero" => "__nvvm_sust_b_1d_v2i8_zero", - "llvm.nvvm.sust.b.1d.v4i16.clamp" => "__nvvm_sust_b_1d_v4i16_clamp", - "llvm.nvvm.sust.b.1d.v4i16.trap" => "__nvvm_sust_b_1d_v4i16_trap", - "llvm.nvvm.sust.b.1d.v4i16.zero" => "__nvvm_sust_b_1d_v4i16_zero", - "llvm.nvvm.sust.b.1d.v4i32.clamp" => "__nvvm_sust_b_1d_v4i32_clamp", - "llvm.nvvm.sust.b.1d.v4i32.trap" => "__nvvm_sust_b_1d_v4i32_trap", - "llvm.nvvm.sust.b.1d.v4i32.zero" => "__nvvm_sust_b_1d_v4i32_zero", - "llvm.nvvm.sust.b.1d.v4i8.clamp" => "__nvvm_sust_b_1d_v4i8_clamp", - "llvm.nvvm.sust.b.1d.v4i8.trap" => "__nvvm_sust_b_1d_v4i8_trap", - "llvm.nvvm.sust.b.1d.v4i8.zero" => "__nvvm_sust_b_1d_v4i8_zero", - "llvm.nvvm.sust.b.2d.array.i16.clamp" => "__nvvm_sust_b_2d_array_i16_clamp", - "llvm.nvvm.sust.b.2d.array.i16.trap" => "__nvvm_sust_b_2d_array_i16_trap", - "llvm.nvvm.sust.b.2d.array.i16.zero" => "__nvvm_sust_b_2d_array_i16_zero", - "llvm.nvvm.sust.b.2d.array.i32.clamp" => "__nvvm_sust_b_2d_array_i32_clamp", - "llvm.nvvm.sust.b.2d.array.i32.trap" => "__nvvm_sust_b_2d_array_i32_trap", - "llvm.nvvm.sust.b.2d.array.i32.zero" => "__nvvm_sust_b_2d_array_i32_zero", - "llvm.nvvm.sust.b.2d.array.i64.clamp" => "__nvvm_sust_b_2d_array_i64_clamp", - "llvm.nvvm.sust.b.2d.array.i64.trap" => "__nvvm_sust_b_2d_array_i64_trap", - "llvm.nvvm.sust.b.2d.array.i64.zero" => "__nvvm_sust_b_2d_array_i64_zero", - "llvm.nvvm.sust.b.2d.array.i8.clamp" => "__nvvm_sust_b_2d_array_i8_clamp", - "llvm.nvvm.sust.b.2d.array.i8.trap" => "__nvvm_sust_b_2d_array_i8_trap", - "llvm.nvvm.sust.b.2d.array.i8.zero" => "__nvvm_sust_b_2d_array_i8_zero", - "llvm.nvvm.sust.b.2d.array.v2i16.clamp" => "__nvvm_sust_b_2d_array_v2i16_clamp", - "llvm.nvvm.sust.b.2d.array.v2i16.trap" => "__nvvm_sust_b_2d_array_v2i16_trap", - "llvm.nvvm.sust.b.2d.array.v2i16.zero" => "__nvvm_sust_b_2d_array_v2i16_zero", - "llvm.nvvm.sust.b.2d.array.v2i32.clamp" => "__nvvm_sust_b_2d_array_v2i32_clamp", - "llvm.nvvm.sust.b.2d.array.v2i32.trap" => "__nvvm_sust_b_2d_array_v2i32_trap", - "llvm.nvvm.sust.b.2d.array.v2i32.zero" => "__nvvm_sust_b_2d_array_v2i32_zero", - "llvm.nvvm.sust.b.2d.array.v2i64.clamp" => "__nvvm_sust_b_2d_array_v2i64_clamp", - "llvm.nvvm.sust.b.2d.array.v2i64.trap" => "__nvvm_sust_b_2d_array_v2i64_trap", - "llvm.nvvm.sust.b.2d.array.v2i64.zero" => "__nvvm_sust_b_2d_array_v2i64_zero", - "llvm.nvvm.sust.b.2d.array.v2i8.clamp" => "__nvvm_sust_b_2d_array_v2i8_clamp", - "llvm.nvvm.sust.b.2d.array.v2i8.trap" => "__nvvm_sust_b_2d_array_v2i8_trap", - "llvm.nvvm.sust.b.2d.array.v2i8.zero" => "__nvvm_sust_b_2d_array_v2i8_zero", - "llvm.nvvm.sust.b.2d.array.v4i16.clamp" => "__nvvm_sust_b_2d_array_v4i16_clamp", - "llvm.nvvm.sust.b.2d.array.v4i16.trap" => "__nvvm_sust_b_2d_array_v4i16_trap", - "llvm.nvvm.sust.b.2d.array.v4i16.zero" => "__nvvm_sust_b_2d_array_v4i16_zero", - "llvm.nvvm.sust.b.2d.array.v4i32.clamp" => "__nvvm_sust_b_2d_array_v4i32_clamp", - "llvm.nvvm.sust.b.2d.array.v4i32.trap" => "__nvvm_sust_b_2d_array_v4i32_trap", - "llvm.nvvm.sust.b.2d.array.v4i32.zero" => "__nvvm_sust_b_2d_array_v4i32_zero", - "llvm.nvvm.sust.b.2d.array.v4i8.clamp" => "__nvvm_sust_b_2d_array_v4i8_clamp", - "llvm.nvvm.sust.b.2d.array.v4i8.trap" => "__nvvm_sust_b_2d_array_v4i8_trap", - "llvm.nvvm.sust.b.2d.array.v4i8.zero" => "__nvvm_sust_b_2d_array_v4i8_zero", - "llvm.nvvm.sust.b.2d.i16.clamp" => "__nvvm_sust_b_2d_i16_clamp", - "llvm.nvvm.sust.b.2d.i16.trap" => "__nvvm_sust_b_2d_i16_trap", - "llvm.nvvm.sust.b.2d.i16.zero" => "__nvvm_sust_b_2d_i16_zero", - "llvm.nvvm.sust.b.2d.i32.clamp" => "__nvvm_sust_b_2d_i32_clamp", - "llvm.nvvm.sust.b.2d.i32.trap" => "__nvvm_sust_b_2d_i32_trap", - "llvm.nvvm.sust.b.2d.i32.zero" => "__nvvm_sust_b_2d_i32_zero", - "llvm.nvvm.sust.b.2d.i64.clamp" => "__nvvm_sust_b_2d_i64_clamp", - "llvm.nvvm.sust.b.2d.i64.trap" => "__nvvm_sust_b_2d_i64_trap", - "llvm.nvvm.sust.b.2d.i64.zero" => "__nvvm_sust_b_2d_i64_zero", - "llvm.nvvm.sust.b.2d.i8.clamp" => "__nvvm_sust_b_2d_i8_clamp", - "llvm.nvvm.sust.b.2d.i8.trap" => "__nvvm_sust_b_2d_i8_trap", - "llvm.nvvm.sust.b.2d.i8.zero" => "__nvvm_sust_b_2d_i8_zero", - "llvm.nvvm.sust.b.2d.v2i16.clamp" => "__nvvm_sust_b_2d_v2i16_clamp", - "llvm.nvvm.sust.b.2d.v2i16.trap" => "__nvvm_sust_b_2d_v2i16_trap", - "llvm.nvvm.sust.b.2d.v2i16.zero" => "__nvvm_sust_b_2d_v2i16_zero", - "llvm.nvvm.sust.b.2d.v2i32.clamp" => "__nvvm_sust_b_2d_v2i32_clamp", - "llvm.nvvm.sust.b.2d.v2i32.trap" => "__nvvm_sust_b_2d_v2i32_trap", - "llvm.nvvm.sust.b.2d.v2i32.zero" => "__nvvm_sust_b_2d_v2i32_zero", - "llvm.nvvm.sust.b.2d.v2i64.clamp" => "__nvvm_sust_b_2d_v2i64_clamp", - "llvm.nvvm.sust.b.2d.v2i64.trap" => "__nvvm_sust_b_2d_v2i64_trap", - "llvm.nvvm.sust.b.2d.v2i64.zero" => "__nvvm_sust_b_2d_v2i64_zero", - "llvm.nvvm.sust.b.2d.v2i8.clamp" => "__nvvm_sust_b_2d_v2i8_clamp", - "llvm.nvvm.sust.b.2d.v2i8.trap" => "__nvvm_sust_b_2d_v2i8_trap", - "llvm.nvvm.sust.b.2d.v2i8.zero" => "__nvvm_sust_b_2d_v2i8_zero", - "llvm.nvvm.sust.b.2d.v4i16.clamp" => "__nvvm_sust_b_2d_v4i16_clamp", - "llvm.nvvm.sust.b.2d.v4i16.trap" => "__nvvm_sust_b_2d_v4i16_trap", - "llvm.nvvm.sust.b.2d.v4i16.zero" => "__nvvm_sust_b_2d_v4i16_zero", - "llvm.nvvm.sust.b.2d.v4i32.clamp" => "__nvvm_sust_b_2d_v4i32_clamp", - "llvm.nvvm.sust.b.2d.v4i32.trap" => "__nvvm_sust_b_2d_v4i32_trap", - "llvm.nvvm.sust.b.2d.v4i32.zero" => "__nvvm_sust_b_2d_v4i32_zero", - "llvm.nvvm.sust.b.2d.v4i8.clamp" => "__nvvm_sust_b_2d_v4i8_clamp", - "llvm.nvvm.sust.b.2d.v4i8.trap" => "__nvvm_sust_b_2d_v4i8_trap", - "llvm.nvvm.sust.b.2d.v4i8.zero" => "__nvvm_sust_b_2d_v4i8_zero", - "llvm.nvvm.sust.b.3d.i16.clamp" => "__nvvm_sust_b_3d_i16_clamp", - "llvm.nvvm.sust.b.3d.i16.trap" => "__nvvm_sust_b_3d_i16_trap", - "llvm.nvvm.sust.b.3d.i16.zero" => "__nvvm_sust_b_3d_i16_zero", - "llvm.nvvm.sust.b.3d.i32.clamp" => "__nvvm_sust_b_3d_i32_clamp", - "llvm.nvvm.sust.b.3d.i32.trap" => "__nvvm_sust_b_3d_i32_trap", - "llvm.nvvm.sust.b.3d.i32.zero" => "__nvvm_sust_b_3d_i32_zero", - "llvm.nvvm.sust.b.3d.i64.clamp" => "__nvvm_sust_b_3d_i64_clamp", - "llvm.nvvm.sust.b.3d.i64.trap" => "__nvvm_sust_b_3d_i64_trap", - "llvm.nvvm.sust.b.3d.i64.zero" => "__nvvm_sust_b_3d_i64_zero", - "llvm.nvvm.sust.b.3d.i8.clamp" => "__nvvm_sust_b_3d_i8_clamp", - "llvm.nvvm.sust.b.3d.i8.trap" => "__nvvm_sust_b_3d_i8_trap", - "llvm.nvvm.sust.b.3d.i8.zero" => "__nvvm_sust_b_3d_i8_zero", - "llvm.nvvm.sust.b.3d.v2i16.clamp" => "__nvvm_sust_b_3d_v2i16_clamp", - "llvm.nvvm.sust.b.3d.v2i16.trap" => "__nvvm_sust_b_3d_v2i16_trap", - "llvm.nvvm.sust.b.3d.v2i16.zero" => "__nvvm_sust_b_3d_v2i16_zero", - "llvm.nvvm.sust.b.3d.v2i32.clamp" => "__nvvm_sust_b_3d_v2i32_clamp", - "llvm.nvvm.sust.b.3d.v2i32.trap" => "__nvvm_sust_b_3d_v2i32_trap", - "llvm.nvvm.sust.b.3d.v2i32.zero" => "__nvvm_sust_b_3d_v2i32_zero", - "llvm.nvvm.sust.b.3d.v2i64.clamp" => "__nvvm_sust_b_3d_v2i64_clamp", - "llvm.nvvm.sust.b.3d.v2i64.trap" => "__nvvm_sust_b_3d_v2i64_trap", - "llvm.nvvm.sust.b.3d.v2i64.zero" => "__nvvm_sust_b_3d_v2i64_zero", - "llvm.nvvm.sust.b.3d.v2i8.clamp" => "__nvvm_sust_b_3d_v2i8_clamp", - "llvm.nvvm.sust.b.3d.v2i8.trap" => "__nvvm_sust_b_3d_v2i8_trap", - "llvm.nvvm.sust.b.3d.v2i8.zero" => "__nvvm_sust_b_3d_v2i8_zero", - "llvm.nvvm.sust.b.3d.v4i16.clamp" => "__nvvm_sust_b_3d_v4i16_clamp", - "llvm.nvvm.sust.b.3d.v4i16.trap" => "__nvvm_sust_b_3d_v4i16_trap", - "llvm.nvvm.sust.b.3d.v4i16.zero" => "__nvvm_sust_b_3d_v4i16_zero", - "llvm.nvvm.sust.b.3d.v4i32.clamp" => "__nvvm_sust_b_3d_v4i32_clamp", - "llvm.nvvm.sust.b.3d.v4i32.trap" => "__nvvm_sust_b_3d_v4i32_trap", - "llvm.nvvm.sust.b.3d.v4i32.zero" => "__nvvm_sust_b_3d_v4i32_zero", - "llvm.nvvm.sust.b.3d.v4i8.clamp" => "__nvvm_sust_b_3d_v4i8_clamp", - "llvm.nvvm.sust.b.3d.v4i8.trap" => "__nvvm_sust_b_3d_v4i8_trap", - "llvm.nvvm.sust.b.3d.v4i8.zero" => "__nvvm_sust_b_3d_v4i8_zero", - "llvm.nvvm.sust.p.1d.array.i16.trap" => "__nvvm_sust_p_1d_array_i16_trap", - "llvm.nvvm.sust.p.1d.array.i32.trap" => "__nvvm_sust_p_1d_array_i32_trap", - "llvm.nvvm.sust.p.1d.array.i8.trap" => "__nvvm_sust_p_1d_array_i8_trap", - "llvm.nvvm.sust.p.1d.array.v2i16.trap" => "__nvvm_sust_p_1d_array_v2i16_trap", - "llvm.nvvm.sust.p.1d.array.v2i32.trap" => "__nvvm_sust_p_1d_array_v2i32_trap", - "llvm.nvvm.sust.p.1d.array.v2i8.trap" => "__nvvm_sust_p_1d_array_v2i8_trap", - "llvm.nvvm.sust.p.1d.array.v4i16.trap" => "__nvvm_sust_p_1d_array_v4i16_trap", - "llvm.nvvm.sust.p.1d.array.v4i32.trap" => "__nvvm_sust_p_1d_array_v4i32_trap", - "llvm.nvvm.sust.p.1d.array.v4i8.trap" => "__nvvm_sust_p_1d_array_v4i8_trap", - "llvm.nvvm.sust.p.1d.i16.trap" => "__nvvm_sust_p_1d_i16_trap", - "llvm.nvvm.sust.p.1d.i32.trap" => "__nvvm_sust_p_1d_i32_trap", - "llvm.nvvm.sust.p.1d.i8.trap" => "__nvvm_sust_p_1d_i8_trap", - "llvm.nvvm.sust.p.1d.v2i16.trap" => "__nvvm_sust_p_1d_v2i16_trap", - "llvm.nvvm.sust.p.1d.v2i32.trap" => "__nvvm_sust_p_1d_v2i32_trap", - "llvm.nvvm.sust.p.1d.v2i8.trap" => "__nvvm_sust_p_1d_v2i8_trap", - "llvm.nvvm.sust.p.1d.v4i16.trap" => "__nvvm_sust_p_1d_v4i16_trap", - "llvm.nvvm.sust.p.1d.v4i32.trap" => "__nvvm_sust_p_1d_v4i32_trap", - "llvm.nvvm.sust.p.1d.v4i8.trap" => "__nvvm_sust_p_1d_v4i8_trap", - "llvm.nvvm.sust.p.2d.array.i16.trap" => "__nvvm_sust_p_2d_array_i16_trap", - "llvm.nvvm.sust.p.2d.array.i32.trap" => "__nvvm_sust_p_2d_array_i32_trap", - "llvm.nvvm.sust.p.2d.array.i8.trap" => "__nvvm_sust_p_2d_array_i8_trap", - "llvm.nvvm.sust.p.2d.array.v2i16.trap" => "__nvvm_sust_p_2d_array_v2i16_trap", - "llvm.nvvm.sust.p.2d.array.v2i32.trap" => "__nvvm_sust_p_2d_array_v2i32_trap", - "llvm.nvvm.sust.p.2d.array.v2i8.trap" => "__nvvm_sust_p_2d_array_v2i8_trap", - "llvm.nvvm.sust.p.2d.array.v4i16.trap" => "__nvvm_sust_p_2d_array_v4i16_trap", - "llvm.nvvm.sust.p.2d.array.v4i32.trap" => "__nvvm_sust_p_2d_array_v4i32_trap", - "llvm.nvvm.sust.p.2d.array.v4i8.trap" => "__nvvm_sust_p_2d_array_v4i8_trap", - "llvm.nvvm.sust.p.2d.i16.trap" => "__nvvm_sust_p_2d_i16_trap", - "llvm.nvvm.sust.p.2d.i32.trap" => "__nvvm_sust_p_2d_i32_trap", - "llvm.nvvm.sust.p.2d.i8.trap" => "__nvvm_sust_p_2d_i8_trap", - "llvm.nvvm.sust.p.2d.v2i16.trap" => "__nvvm_sust_p_2d_v2i16_trap", - "llvm.nvvm.sust.p.2d.v2i32.trap" => "__nvvm_sust_p_2d_v2i32_trap", - "llvm.nvvm.sust.p.2d.v2i8.trap" => "__nvvm_sust_p_2d_v2i8_trap", - "llvm.nvvm.sust.p.2d.v4i16.trap" => "__nvvm_sust_p_2d_v4i16_trap", - "llvm.nvvm.sust.p.2d.v4i32.trap" => "__nvvm_sust_p_2d_v4i32_trap", - "llvm.nvvm.sust.p.2d.v4i8.trap" => "__nvvm_sust_p_2d_v4i8_trap", - "llvm.nvvm.sust.p.3d.i16.trap" => "__nvvm_sust_p_3d_i16_trap", - "llvm.nvvm.sust.p.3d.i32.trap" => "__nvvm_sust_p_3d_i32_trap", - "llvm.nvvm.sust.p.3d.i8.trap" => "__nvvm_sust_p_3d_i8_trap", - "llvm.nvvm.sust.p.3d.v2i16.trap" => "__nvvm_sust_p_3d_v2i16_trap", - "llvm.nvvm.sust.p.3d.v2i32.trap" => "__nvvm_sust_p_3d_v2i32_trap", - "llvm.nvvm.sust.p.3d.v2i8.trap" => "__nvvm_sust_p_3d_v2i8_trap", - "llvm.nvvm.sust.p.3d.v4i16.trap" => "__nvvm_sust_p_3d_v4i16_trap", - "llvm.nvvm.sust.p.3d.v4i32.trap" => "__nvvm_sust_p_3d_v4i32_trap", - "llvm.nvvm.sust.p.3d.v4i8.trap" => "__nvvm_sust_p_3d_v4i8_trap", - "llvm.nvvm.swap.lo.hi.b64" => "__nvvm_swap_lo_hi_b64", - "llvm.nvvm.trunc.d" => "__nvvm_trunc_d", - "llvm.nvvm.trunc.f" => "__nvvm_trunc_f", - "llvm.nvvm.trunc.ftz.f" => "__nvvm_trunc_ftz_f", - "llvm.nvvm.txq.array.size" => "__nvvm_txq_array_size", - "llvm.nvvm.txq.channel.data.type" => "__nvvm_txq_channel_data_type", - "llvm.nvvm.txq.channel.order" => "__nvvm_txq_channel_order", - "llvm.nvvm.txq.depth" => "__nvvm_txq_depth", - "llvm.nvvm.txq.height" => "__nvvm_txq_height", - "llvm.nvvm.txq.num.mipmap.levels" => "__nvvm_txq_num_mipmap_levels", - "llvm.nvvm.txq.num.samples" => "__nvvm_txq_num_samples", - "llvm.nvvm.txq.width" => "__nvvm_txq_width", - "llvm.nvvm.ui2d.rm" => "__nvvm_ui2d_rm", - "llvm.nvvm.ui2d.rn" => "__nvvm_ui2d_rn", - "llvm.nvvm.ui2d.rp" => "__nvvm_ui2d_rp", - "llvm.nvvm.ui2d.rz" => "__nvvm_ui2d_rz", - "llvm.nvvm.ui2f.rm" => "__nvvm_ui2f_rm", - "llvm.nvvm.ui2f.rn" => "__nvvm_ui2f_rn", - "llvm.nvvm.ui2f.rp" => "__nvvm_ui2f_rp", - "llvm.nvvm.ui2f.rz" => "__nvvm_ui2f_rz", - "llvm.nvvm.ull2d.rm" => "__nvvm_ull2d_rm", - "llvm.nvvm.ull2d.rn" => "__nvvm_ull2d_rn", - "llvm.nvvm.ull2d.rp" => "__nvvm_ull2d_rp", - "llvm.nvvm.ull2d.rz" => "__nvvm_ull2d_rz", - "llvm.nvvm.ull2f.rm" => "__nvvm_ull2f_rm", - "llvm.nvvm.ull2f.rn" => "__nvvm_ull2f_rn", - "llvm.nvvm.ull2f.rp" => "__nvvm_ull2f_rp", - "llvm.nvvm.ull2f.rz" => "__nvvm_ull2f_rz", // ppc + "llvm.ppc.addex" => "__builtin_ppc_addex", + "llvm.ppc.addf128.round.to.odd" => "__builtin_addf128_round_to_odd", + "llvm.ppc.altivec.crypto.vpermxor" => "__builtin_altivec_crypto_vpermxor", + "llvm.ppc.altivec.crypto.vpermxor.be" => "__builtin_altivec_crypto_vpermxor_be", + "llvm.ppc.altivec.crypto.vsbox" => "__builtin_altivec_crypto_vsbox", + "llvm.ppc.altivec.crypto.vshasigmad" => "__builtin_altivec_crypto_vshasigmad", + "llvm.ppc.altivec.crypto.vshasigmaw" => "__builtin_altivec_crypto_vshasigmaw", "llvm.ppc.altivec.dss" => "__builtin_altivec_dss", "llvm.ppc.altivec.dssall" => "__builtin_altivec_dssall", "llvm.ppc.altivec.dst" => "__builtin_altivec_dst", @@ -2043,29 +904,34 @@ match name { "llvm.ppc.altivec.dstt" => "__builtin_altivec_dstt", "llvm.ppc.altivec.mfvscr" => "__builtin_altivec_mfvscr", "llvm.ppc.altivec.mtvscr" => "__builtin_altivec_mtvscr", - "llvm.ppc.altivec.vaddcuw" => "__builtin_altivec_vaddcuw", - "llvm.ppc.altivec.vaddsbs" => "__builtin_altivec_vaddsbs", - "llvm.ppc.altivec.vaddshs" => "__builtin_altivec_vaddshs", - "llvm.ppc.altivec.vaddsws" => "__builtin_altivec_vaddsws", - "llvm.ppc.altivec.vaddubs" => "__builtin_altivec_vaddubs", - "llvm.ppc.altivec.vadduhs" => "__builtin_altivec_vadduhs", - "llvm.ppc.altivec.vadduws" => "__builtin_altivec_vadduws", - "llvm.ppc.altivec.vavgsb" => "__builtin_altivec_vavgsb", - "llvm.ppc.altivec.vavgsh" => "__builtin_altivec_vavgsh", - "llvm.ppc.altivec.vavgsw" => "__builtin_altivec_vavgsw", - "llvm.ppc.altivec.vavgub" => "__builtin_altivec_vavgub", - "llvm.ppc.altivec.vavguh" => "__builtin_altivec_vavguh", - "llvm.ppc.altivec.vavguw" => "__builtin_altivec_vavguw", + "llvm.ppc.altivec.mtvsrbm" => "__builtin_altivec_mtvsrbm", + "llvm.ppc.altivec.mtvsrdm" => "__builtin_altivec_mtvsrdm", + "llvm.ppc.altivec.mtvsrhm" => "__builtin_altivec_mtvsrhm", + "llvm.ppc.altivec.mtvsrqm" => "__builtin_altivec_mtvsrqm", + "llvm.ppc.altivec.mtvsrwm" => "__builtin_altivec_mtvsrwm", + "llvm.ppc.altivec.vaddecuq" => "__builtin_altivec_vaddecuq", + "llvm.ppc.altivec.vaddeuqm" => "__builtin_altivec_vaddeuqm", + "llvm.ppc.altivec.vbpermd" => "__builtin_altivec_vbpermd", + "llvm.ppc.altivec.vbpermq" => "__builtin_altivec_vbpermq", "llvm.ppc.altivec.vcfsx" => "__builtin_altivec_vcfsx", + "llvm.ppc.altivec.vcfuged" => "__builtin_altivec_vcfuged", "llvm.ppc.altivec.vcfux" => "__builtin_altivec_vcfux", + "llvm.ppc.altivec.vclrlb" => "__builtin_altivec_vclrlb", + "llvm.ppc.altivec.vclrrb" => "__builtin_altivec_vclrrb", + "llvm.ppc.altivec.vclzdm" => "__builtin_altivec_vclzdm", + "llvm.ppc.altivec.vclzlsbb" => "__builtin_altivec_vclzlsbb", "llvm.ppc.altivec.vcmpbfp" => "__builtin_altivec_vcmpbfp", "llvm.ppc.altivec.vcmpbfp.p" => "__builtin_altivec_vcmpbfp_p", "llvm.ppc.altivec.vcmpeqfp" => "__builtin_altivec_vcmpeqfp", "llvm.ppc.altivec.vcmpeqfp.p" => "__builtin_altivec_vcmpeqfp_p", "llvm.ppc.altivec.vcmpequb" => "__builtin_altivec_vcmpequb", "llvm.ppc.altivec.vcmpequb.p" => "__builtin_altivec_vcmpequb_p", + "llvm.ppc.altivec.vcmpequd" => "__builtin_altivec_vcmpequd", + "llvm.ppc.altivec.vcmpequd.p" => "__builtin_altivec_vcmpequd_p", "llvm.ppc.altivec.vcmpequh" => "__builtin_altivec_vcmpequh", "llvm.ppc.altivec.vcmpequh.p" => "__builtin_altivec_vcmpequh_p", + "llvm.ppc.altivec.vcmpequq" => "__builtin_altivec_vcmpequq", + "llvm.ppc.altivec.vcmpequq.p" => "__builtin_altivec_vcmpequq_p", "llvm.ppc.altivec.vcmpequw" => "__builtin_altivec_vcmpequw", "llvm.ppc.altivec.vcmpequw.p" => "__builtin_altivec_vcmpequw_p", "llvm.ppc.altivec.vcmpgefp" => "__builtin_altivec_vcmpgefp", @@ -2074,91 +940,142 @@ match name { "llvm.ppc.altivec.vcmpgtfp.p" => "__builtin_altivec_vcmpgtfp_p", "llvm.ppc.altivec.vcmpgtsb" => "__builtin_altivec_vcmpgtsb", "llvm.ppc.altivec.vcmpgtsb.p" => "__builtin_altivec_vcmpgtsb_p", + "llvm.ppc.altivec.vcmpgtsd" => "__builtin_altivec_vcmpgtsd", + "llvm.ppc.altivec.vcmpgtsd.p" => "__builtin_altivec_vcmpgtsd_p", "llvm.ppc.altivec.vcmpgtsh" => "__builtin_altivec_vcmpgtsh", "llvm.ppc.altivec.vcmpgtsh.p" => "__builtin_altivec_vcmpgtsh_p", + "llvm.ppc.altivec.vcmpgtsq" => "__builtin_altivec_vcmpgtsq", + "llvm.ppc.altivec.vcmpgtsq.p" => "__builtin_altivec_vcmpgtsq_p", "llvm.ppc.altivec.vcmpgtsw" => "__builtin_altivec_vcmpgtsw", "llvm.ppc.altivec.vcmpgtsw.p" => "__builtin_altivec_vcmpgtsw_p", "llvm.ppc.altivec.vcmpgtub" => "__builtin_altivec_vcmpgtub", "llvm.ppc.altivec.vcmpgtub.p" => "__builtin_altivec_vcmpgtub_p", + "llvm.ppc.altivec.vcmpgtud" => "__builtin_altivec_vcmpgtud", + "llvm.ppc.altivec.vcmpgtud.p" => "__builtin_altivec_vcmpgtud_p", "llvm.ppc.altivec.vcmpgtuh" => "__builtin_altivec_vcmpgtuh", "llvm.ppc.altivec.vcmpgtuh.p" => "__builtin_altivec_vcmpgtuh_p", + "llvm.ppc.altivec.vcmpgtuq" => "__builtin_altivec_vcmpgtuq", + "llvm.ppc.altivec.vcmpgtuq.p" => "__builtin_altivec_vcmpgtuq_p", "llvm.ppc.altivec.vcmpgtuw" => "__builtin_altivec_vcmpgtuw", "llvm.ppc.altivec.vcmpgtuw.p" => "__builtin_altivec_vcmpgtuw_p", + "llvm.ppc.altivec.vcmpneb" => "__builtin_altivec_vcmpneb", + "llvm.ppc.altivec.vcmpneb.p" => "__builtin_altivec_vcmpneb_p", + "llvm.ppc.altivec.vcmpneh" => "__builtin_altivec_vcmpneh", + "llvm.ppc.altivec.vcmpneh.p" => "__builtin_altivec_vcmpneh_p", + "llvm.ppc.altivec.vcmpnew" => "__builtin_altivec_vcmpnew", + "llvm.ppc.altivec.vcmpnew.p" => "__builtin_altivec_vcmpnew_p", + "llvm.ppc.altivec.vcmpnezb" => "__builtin_altivec_vcmpnezb", + "llvm.ppc.altivec.vcmpnezb.p" => "__builtin_altivec_vcmpnezb_p", + "llvm.ppc.altivec.vcmpnezh" => "__builtin_altivec_vcmpnezh", + "llvm.ppc.altivec.vcmpnezh.p" => "__builtin_altivec_vcmpnezh_p", + "llvm.ppc.altivec.vcmpnezw" => "__builtin_altivec_vcmpnezw", + "llvm.ppc.altivec.vcmpnezw.p" => "__builtin_altivec_vcmpnezw_p", + "llvm.ppc.altivec.vcntmbb" => "__builtin_altivec_vcntmbb", + "llvm.ppc.altivec.vcntmbd" => "__builtin_altivec_vcntmbd", + "llvm.ppc.altivec.vcntmbh" => "__builtin_altivec_vcntmbh", + "llvm.ppc.altivec.vcntmbw" => "__builtin_altivec_vcntmbw", "llvm.ppc.altivec.vctsxs" => "__builtin_altivec_vctsxs", "llvm.ppc.altivec.vctuxs" => "__builtin_altivec_vctuxs", - "llvm.ppc.altivec.vexptefp" => "__builtin_altivec_vexptefp", - "llvm.ppc.altivec.vlogefp" => "__builtin_altivec_vlogefp", + "llvm.ppc.altivec.vctzdm" => "__builtin_altivec_vctzdm", + "llvm.ppc.altivec.vctzlsbb" => "__builtin_altivec_vctzlsbb", + "llvm.ppc.altivec.vexpandbm" => "__builtin_altivec_vexpandbm", + "llvm.ppc.altivec.vexpanddm" => "__builtin_altivec_vexpanddm", + "llvm.ppc.altivec.vexpandhm" => "__builtin_altivec_vexpandhm", + "llvm.ppc.altivec.vexpandqm" => "__builtin_altivec_vexpandqm", + "llvm.ppc.altivec.vexpandwm" => "__builtin_altivec_vexpandwm", + "llvm.ppc.altivec.vextddvlx" => "__builtin_altivec_vextddvlx", + "llvm.ppc.altivec.vextddvrx" => "__builtin_altivec_vextddvrx", + "llvm.ppc.altivec.vextdubvlx" => "__builtin_altivec_vextdubvlx", + "llvm.ppc.altivec.vextdubvrx" => "__builtin_altivec_vextdubvrx", + "llvm.ppc.altivec.vextduhvlx" => "__builtin_altivec_vextduhvlx", + "llvm.ppc.altivec.vextduhvrx" => "__builtin_altivec_vextduhvrx", + "llvm.ppc.altivec.vextduwvlx" => "__builtin_altivec_vextduwvlx", + "llvm.ppc.altivec.vextduwvrx" => "__builtin_altivec_vextduwvrx", + "llvm.ppc.altivec.vextractbm" => "__builtin_altivec_vextractbm", + "llvm.ppc.altivec.vextractdm" => "__builtin_altivec_vextractdm", + "llvm.ppc.altivec.vextracthm" => "__builtin_altivec_vextracthm", + "llvm.ppc.altivec.vextractqm" => "__builtin_altivec_vextractqm", + "llvm.ppc.altivec.vextractwm" => "__builtin_altivec_vextractwm", + "llvm.ppc.altivec.vextsb2d" => "__builtin_altivec_vextsb2d", + "llvm.ppc.altivec.vextsb2w" => "__builtin_altivec_vextsb2w", + "llvm.ppc.altivec.vextsd2q" => "__builtin_altivec_vextsd2q", + "llvm.ppc.altivec.vextsh2d" => "__builtin_altivec_vextsh2d", + "llvm.ppc.altivec.vextsh2w" => "__builtin_altivec_vextsh2w", + "llvm.ppc.altivec.vextsw2d" => "__builtin_altivec_vextsw2d", + "llvm.ppc.altivec.vgbbd" => "__builtin_altivec_vgbbd", + "llvm.ppc.altivec.vgnb" => "__builtin_altivec_vgnb", + "llvm.ppc.altivec.vinsblx" => "__builtin_altivec_vinsblx", + "llvm.ppc.altivec.vinsbrx" => "__builtin_altivec_vinsbrx", + "llvm.ppc.altivec.vinsbvlx" => "__builtin_altivec_vinsbvlx", + "llvm.ppc.altivec.vinsbvrx" => "__builtin_altivec_vinsbvrx", + "llvm.ppc.altivec.vinsdlx" => "__builtin_altivec_vinsdlx", + "llvm.ppc.altivec.vinsdrx" => "__builtin_altivec_vinsdrx", + "llvm.ppc.altivec.vinshlx" => "__builtin_altivec_vinshlx", + "llvm.ppc.altivec.vinshrx" => "__builtin_altivec_vinshrx", + "llvm.ppc.altivec.vinshvlx" => "__builtin_altivec_vinshvlx", + "llvm.ppc.altivec.vinshvrx" => "__builtin_altivec_vinshvrx", + "llvm.ppc.altivec.vinswlx" => "__builtin_altivec_vinswlx", + "llvm.ppc.altivec.vinswrx" => "__builtin_altivec_vinswrx", + "llvm.ppc.altivec.vinswvlx" => "__builtin_altivec_vinswvlx", + "llvm.ppc.altivec.vinswvrx" => "__builtin_altivec_vinswvrx", "llvm.ppc.altivec.vmaddfp" => "__builtin_altivec_vmaddfp", - "llvm.ppc.altivec.vmaxfp" => "__builtin_altivec_vmaxfp", - "llvm.ppc.altivec.vmaxsb" => "__builtin_altivec_vmaxsb", - "llvm.ppc.altivec.vmaxsh" => "__builtin_altivec_vmaxsh", - "llvm.ppc.altivec.vmaxsw" => "__builtin_altivec_vmaxsw", - "llvm.ppc.altivec.vmaxub" => "__builtin_altivec_vmaxub", - "llvm.ppc.altivec.vmaxuh" => "__builtin_altivec_vmaxuh", - "llvm.ppc.altivec.vmaxuw" => "__builtin_altivec_vmaxuw", "llvm.ppc.altivec.vmhaddshs" => "__builtin_altivec_vmhaddshs", "llvm.ppc.altivec.vmhraddshs" => "__builtin_altivec_vmhraddshs", - "llvm.ppc.altivec.vminfp" => "__builtin_altivec_vminfp", - "llvm.ppc.altivec.vminsb" => "__builtin_altivec_vminsb", - "llvm.ppc.altivec.vminsh" => "__builtin_altivec_vminsh", - "llvm.ppc.altivec.vminsw" => "__builtin_altivec_vminsw", - "llvm.ppc.altivec.vminub" => "__builtin_altivec_vminub", - "llvm.ppc.altivec.vminuh" => "__builtin_altivec_vminuh", - "llvm.ppc.altivec.vminuw" => "__builtin_altivec_vminuw", "llvm.ppc.altivec.vmladduhm" => "__builtin_altivec_vmladduhm", + "llvm.ppc.altivec.vmsumcud" => "__builtin_altivec_vmsumcud", "llvm.ppc.altivec.vmsummbm" => "__builtin_altivec_vmsummbm", "llvm.ppc.altivec.vmsumshm" => "__builtin_altivec_vmsumshm", "llvm.ppc.altivec.vmsumshs" => "__builtin_altivec_vmsumshs", "llvm.ppc.altivec.vmsumubm" => "__builtin_altivec_vmsumubm", + "llvm.ppc.altivec.vmsumudm" => "__builtin_altivec_vmsumudm", "llvm.ppc.altivec.vmsumuhm" => "__builtin_altivec_vmsumuhm", "llvm.ppc.altivec.vmsumuhs" => "__builtin_altivec_vmsumuhs", "llvm.ppc.altivec.vmulesb" => "__builtin_altivec_vmulesb", "llvm.ppc.altivec.vmulesh" => "__builtin_altivec_vmulesh", + "llvm.ppc.altivec.vmulesw" => "__builtin_altivec_vmulesw", "llvm.ppc.altivec.vmuleub" => "__builtin_altivec_vmuleub", "llvm.ppc.altivec.vmuleuh" => "__builtin_altivec_vmuleuh", + "llvm.ppc.altivec.vmuleuw" => "__builtin_altivec_vmuleuw", "llvm.ppc.altivec.vmulosb" => "__builtin_altivec_vmulosb", "llvm.ppc.altivec.vmulosh" => "__builtin_altivec_vmulosh", + "llvm.ppc.altivec.vmulosw" => "__builtin_altivec_vmulosw", "llvm.ppc.altivec.vmuloub" => "__builtin_altivec_vmuloub", "llvm.ppc.altivec.vmulouh" => "__builtin_altivec_vmulouh", + "llvm.ppc.altivec.vmulouw" => "__builtin_altivec_vmulouw", "llvm.ppc.altivec.vnmsubfp" => "__builtin_altivec_vnmsubfp", + "llvm.ppc.altivec.vpdepd" => "__builtin_altivec_vpdepd", "llvm.ppc.altivec.vperm" => "__builtin_altivec_vperm_4si", + "llvm.ppc.altivec.vpextd" => "__builtin_altivec_vpextd", "llvm.ppc.altivec.vpkpx" => "__builtin_altivec_vpkpx", + "llvm.ppc.altivec.vpksdss" => "__builtin_altivec_vpksdss", + "llvm.ppc.altivec.vpksdus" => "__builtin_altivec_vpksdus", "llvm.ppc.altivec.vpkshss" => "__builtin_altivec_vpkshss", "llvm.ppc.altivec.vpkshus" => "__builtin_altivec_vpkshus", "llvm.ppc.altivec.vpkswss" => "__builtin_altivec_vpkswss", "llvm.ppc.altivec.vpkswus" => "__builtin_altivec_vpkswus", + "llvm.ppc.altivec.vpkudus" => "__builtin_altivec_vpkudus", "llvm.ppc.altivec.vpkuhus" => "__builtin_altivec_vpkuhus", "llvm.ppc.altivec.vpkuwus" => "__builtin_altivec_vpkuwus", - "llvm.ppc.altivec.vrefp" => "__builtin_altivec_vrefp", + "llvm.ppc.altivec.vprtybd" => "__builtin_altivec_vprtybd", + "llvm.ppc.altivec.vprtybq" => "__builtin_altivec_vprtybq", + "llvm.ppc.altivec.vprtybw" => "__builtin_altivec_vprtybw", "llvm.ppc.altivec.vrfim" => "__builtin_altivec_vrfim", "llvm.ppc.altivec.vrfin" => "__builtin_altivec_vrfin", "llvm.ppc.altivec.vrfip" => "__builtin_altivec_vrfip", "llvm.ppc.altivec.vrfiz" => "__builtin_altivec_vrfiz", - "llvm.ppc.altivec.vrlb" => "__builtin_altivec_vrlb", - "llvm.ppc.altivec.vrlh" => "__builtin_altivec_vrlh", - "llvm.ppc.altivec.vrlw" => "__builtin_altivec_vrlw", - "llvm.ppc.altivec.vrsqrtefp" => "__builtin_altivec_vrsqrtefp", "llvm.ppc.altivec.vsel" => "__builtin_altivec_vsel_4si", - "llvm.ppc.altivec.vsl" => "__builtin_altivec_vsl", - "llvm.ppc.altivec.vslb" => "__builtin_altivec_vslb", - "llvm.ppc.altivec.vslh" => "__builtin_altivec_vslh", - "llvm.ppc.altivec.vslo" => "__builtin_altivec_vslo", - "llvm.ppc.altivec.vslw" => "__builtin_altivec_vslw", - "llvm.ppc.altivec.vsr" => "__builtin_altivec_vsr", - "llvm.ppc.altivec.vsrab" => "__builtin_altivec_vsrab", - "llvm.ppc.altivec.vsrah" => "__builtin_altivec_vsrah", - "llvm.ppc.altivec.vsraw" => "__builtin_altivec_vsraw", - "llvm.ppc.altivec.vsrb" => "__builtin_altivec_vsrb", - "llvm.ppc.altivec.vsrh" => "__builtin_altivec_vsrh", - "llvm.ppc.altivec.vsro" => "__builtin_altivec_vsro", - "llvm.ppc.altivec.vsrw" => "__builtin_altivec_vsrw", - "llvm.ppc.altivec.vsubcuw" => "__builtin_altivec_vsubcuw", - "llvm.ppc.altivec.vsubsbs" => "__builtin_altivec_vsubsbs", - "llvm.ppc.altivec.vsubshs" => "__builtin_altivec_vsubshs", - "llvm.ppc.altivec.vsubsws" => "__builtin_altivec_vsubsws", - "llvm.ppc.altivec.vsububs" => "__builtin_altivec_vsububs", - "llvm.ppc.altivec.vsubuhs" => "__builtin_altivec_vsubuhs", - "llvm.ppc.altivec.vsubuws" => "__builtin_altivec_vsubuws", + "llvm.ppc.altivec.vsldbi" => "__builtin_altivec_vsldbi", + "llvm.ppc.altivec.vsrdbi" => "__builtin_altivec_vsrdbi", + "llvm.ppc.altivec.vstribl" => "__builtin_altivec_vstribl", + "llvm.ppc.altivec.vstribl.p" => "__builtin_altivec_vstribl_p", + "llvm.ppc.altivec.vstribr" => "__builtin_altivec_vstribr", + "llvm.ppc.altivec.vstribr.p" => "__builtin_altivec_vstribr_p", + "llvm.ppc.altivec.vstrihl" => "__builtin_altivec_vstrihl", + "llvm.ppc.altivec.vstrihl.p" => "__builtin_altivec_vstrihl_p", + "llvm.ppc.altivec.vstrihr" => "__builtin_altivec_vstrihr", + "llvm.ppc.altivec.vstrihr.p" => "__builtin_altivec_vstrihr_p", + "llvm.ppc.altivec.vsubecuq" => "__builtin_altivec_vsubecuq", + "llvm.ppc.altivec.vsubeuqm" => "__builtin_altivec_vsubeuqm", "llvm.ppc.altivec.vsum2sws" => "__builtin_altivec_vsum2sws", "llvm.ppc.altivec.vsum4sbs" => "__builtin_altivec_vsum4sbs", "llvm.ppc.altivec.vsum4shs" => "__builtin_altivec_vsum4shs", @@ -2167,53 +1084,221 @@ match name { "llvm.ppc.altivec.vupkhpx" => "__builtin_altivec_vupkhpx", "llvm.ppc.altivec.vupkhsb" => "__builtin_altivec_vupkhsb", "llvm.ppc.altivec.vupkhsh" => "__builtin_altivec_vupkhsh", + "llvm.ppc.altivec.vupkhsw" => "__builtin_altivec_vupkhsw", "llvm.ppc.altivec.vupklpx" => "__builtin_altivec_vupklpx", "llvm.ppc.altivec.vupklsb" => "__builtin_altivec_vupklsb", "llvm.ppc.altivec.vupklsh" => "__builtin_altivec_vupklsh", - // ptx - "llvm.ptx.bar.sync" => "__builtin_ptx_bar_sync", - "llvm.ptx.read.clock" => "__builtin_ptx_read_clock", - "llvm.ptx.read.clock64" => "__builtin_ptx_read_clock64", - "llvm.ptx.read.gridid" => "__builtin_ptx_read_gridid", - "llvm.ptx.read.laneid" => "__builtin_ptx_read_laneid", - "llvm.ptx.read.lanemask.eq" => "__builtin_ptx_read_lanemask_eq", - "llvm.ptx.read.lanemask.ge" => "__builtin_ptx_read_lanemask_ge", - "llvm.ptx.read.lanemask.gt" => "__builtin_ptx_read_lanemask_gt", - "llvm.ptx.read.lanemask.le" => "__builtin_ptx_read_lanemask_le", - "llvm.ptx.read.lanemask.lt" => "__builtin_ptx_read_lanemask_lt", - "llvm.ptx.read.nsmid" => "__builtin_ptx_read_nsmid", - "llvm.ptx.read.nwarpid" => "__builtin_ptx_read_nwarpid", - "llvm.ptx.read.pm0" => "__builtin_ptx_read_pm0", - "llvm.ptx.read.pm1" => "__builtin_ptx_read_pm1", - "llvm.ptx.read.pm2" => "__builtin_ptx_read_pm2", - "llvm.ptx.read.pm3" => "__builtin_ptx_read_pm3", - "llvm.ptx.read.smid" => "__builtin_ptx_read_smid", - "llvm.ptx.read.warpid" => "__builtin_ptx_read_warpid", + "llvm.ppc.altivec.vupklsw" => "__builtin_altivec_vupklsw", + "llvm.ppc.bcdadd" => "__builtin_ppc_bcdadd", + "llvm.ppc.bcdadd.p" => "__builtin_ppc_bcdadd_p", + "llvm.ppc.bcdsub" => "__builtin_ppc_bcdsub", + "llvm.ppc.bcdsub.p" => "__builtin_ppc_bcdsub_p", + "llvm.ppc.bpermd" => "__builtin_bpermd", + "llvm.ppc.cfuged" => "__builtin_cfuged", + "llvm.ppc.cmpeqb" => "__builtin_ppc_cmpeqb", + "llvm.ppc.cmprb" => "__builtin_ppc_cmprb", + "llvm.ppc.cntlzdm" => "__builtin_cntlzdm", + "llvm.ppc.cnttzdm" => "__builtin_cnttzdm", + "llvm.ppc.compare.exp.eq" => "__builtin_ppc_compare_exp_eq", + "llvm.ppc.compare.exp.gt" => "__builtin_ppc_compare_exp_gt", + "llvm.ppc.compare.exp.lt" => "__builtin_ppc_compare_exp_lt", + "llvm.ppc.compare.exp.uo" => "__builtin_ppc_compare_exp_uo", + "llvm.ppc.darn" => "__builtin_darn", + "llvm.ppc.darn32" => "__builtin_darn_32", + "llvm.ppc.darnraw" => "__builtin_darn_raw", + "llvm.ppc.dcbf" => "__builtin_dcbf", + "llvm.ppc.dcbfl" => "__builtin_ppc_dcbfl", + "llvm.ppc.dcbflp" => "__builtin_ppc_dcbflp", + "llvm.ppc.dcbst" => "__builtin_ppc_dcbst", + "llvm.ppc.dcbt" => "__builtin_ppc_dcbt", + "llvm.ppc.dcbtst" => "__builtin_ppc_dcbtst", + "llvm.ppc.dcbtstt" => "__builtin_ppc_dcbtstt", + "llvm.ppc.dcbtt" => "__builtin_ppc_dcbtt", + "llvm.ppc.dcbz" => "__builtin_ppc_dcbz", + "llvm.ppc.divde" => "__builtin_divde", + "llvm.ppc.divdeu" => "__builtin_divdeu", + "llvm.ppc.divf128.round.to.odd" => "__builtin_divf128_round_to_odd", + "llvm.ppc.divwe" => "__builtin_divwe", + "llvm.ppc.divweu" => "__builtin_divweu", + "llvm.ppc.eieio" => "__builtin_ppc_eieio", + "llvm.ppc.extract.exp" => "__builtin_ppc_extract_exp", + "llvm.ppc.extract.sig" => "__builtin_ppc_extract_sig", + "llvm.ppc.fcfid" => "__builtin_ppc_fcfid", + "llvm.ppc.fcfud" => "__builtin_ppc_fcfud", + "llvm.ppc.fctid" => "__builtin_ppc_fctid", + "llvm.ppc.fctidz" => "__builtin_ppc_fctidz", + "llvm.ppc.fctiw" => "__builtin_ppc_fctiw", + "llvm.ppc.fctiwz" => "__builtin_ppc_fctiwz", + "llvm.ppc.fctudz" => "__builtin_ppc_fctudz", + "llvm.ppc.fctuwz" => "__builtin_ppc_fctuwz", + "llvm.ppc.fmaf128.round.to.odd" => "__builtin_fmaf128_round_to_odd", + "llvm.ppc.fmsub" => "__builtin_ppc_fmsub", + "llvm.ppc.fmsubs" => "__builtin_ppc_fmsubs", + "llvm.ppc.fnmadd" => "__builtin_ppc_fnmadd", + "llvm.ppc.fnmadds" => "__builtin_ppc_fnmadds", + "llvm.ppc.fre" => "__builtin_ppc_fre", + "llvm.ppc.fres" => "__builtin_ppc_fres", + "llvm.ppc.frsqrte" => "__builtin_ppc_frsqrte", + "llvm.ppc.frsqrtes" => "__builtin_ppc_frsqrtes", + "llvm.ppc.fsel" => "__builtin_ppc_fsel", + "llvm.ppc.fsels" => "__builtin_ppc_fsels", + "llvm.ppc.get.texasr" => "__builtin_get_texasr", + "llvm.ppc.get.texasru" => "__builtin_get_texasru", + "llvm.ppc.get.tfhar" => "__builtin_get_tfhar", + "llvm.ppc.get.tfiar" => "__builtin_get_tfiar", + "llvm.ppc.icbt" => "__builtin_ppc_icbt", + "llvm.ppc.insert.exp" => "__builtin_ppc_insert_exp", + "llvm.ppc.iospace.eieio" => "__builtin_ppc_iospace_eieio", + "llvm.ppc.iospace.lwsync" => "__builtin_ppc_iospace_lwsync", + "llvm.ppc.iospace.sync" => "__builtin_ppc_iospace_sync", + "llvm.ppc.isync" => "__builtin_ppc_isync", + "llvm.ppc.load4r" => "__builtin_ppc_load4r", + "llvm.ppc.load8r" => "__builtin_ppc_load8r", + "llvm.ppc.lwsync" => "__builtin_ppc_lwsync", + "llvm.ppc.maddhd" => "__builtin_ppc_maddhd", + "llvm.ppc.maddhdu" => "__builtin_ppc_maddhdu", + "llvm.ppc.maddld" => "__builtin_ppc_maddld", + "llvm.ppc.mfmsr" => "__builtin_ppc_mfmsr", + "llvm.ppc.mftbu" => "__builtin_ppc_mftbu", + "llvm.ppc.mtfsb0" => "__builtin_ppc_mtfsb0", + "llvm.ppc.mtfsb1" => "__builtin_ppc_mtfsb1", + "llvm.ppc.mtfsfi" => "__builtin_ppc_mtfsfi", + "llvm.ppc.mtmsr" => "__builtin_ppc_mtmsr", + "llvm.ppc.mulf128.round.to.odd" => "__builtin_mulf128_round_to_odd", + "llvm.ppc.mulhd" => "__builtin_ppc_mulhd", + "llvm.ppc.mulhdu" => "__builtin_ppc_mulhdu", + "llvm.ppc.mulhw" => "__builtin_ppc_mulhw", + "llvm.ppc.mulhwu" => "__builtin_ppc_mulhwu", + "llvm.ppc.pack.longdouble" => "__builtin_pack_longdouble", + "llvm.ppc.pdepd" => "__builtin_pdepd", + "llvm.ppc.pextd" => "__builtin_pextd", + "llvm.ppc.readflm" => "__builtin_readflm", + "llvm.ppc.scalar.extract.expq" => "__builtin_vsx_scalar_extract_expq", + "llvm.ppc.scalar.insert.exp.qp" => "__builtin_vsx_scalar_insert_exp_qp", + "llvm.ppc.set.texasr" => "__builtin_set_texasr", + "llvm.ppc.set.texasru" => "__builtin_set_texasru", + "llvm.ppc.set.tfhar" => "__builtin_set_tfhar", + "llvm.ppc.set.tfiar" => "__builtin_set_tfiar", + "llvm.ppc.setb" => "__builtin_ppc_setb", + "llvm.ppc.setflm" => "__builtin_setflm", + "llvm.ppc.setrnd" => "__builtin_setrnd", + "llvm.ppc.sqrtf128.round.to.odd" => "__builtin_sqrtf128_round_to_odd", + "llvm.ppc.stbcx" => "__builtin_ppc_stbcx", + "llvm.ppc.stdcx" => "__builtin_ppc_stdcx", + "llvm.ppc.stfiw" => "__builtin_ppc_stfiw", + "llvm.ppc.store2r" => "__builtin_ppc_store2r", + "llvm.ppc.store4r" => "__builtin_ppc_store4r", + "llvm.ppc.store8r" => "__builtin_ppc_store8r", + "llvm.ppc.stwcx" => "__builtin_ppc_stwcx", + "llvm.ppc.subf128.round.to.odd" => "__builtin_subf128_round_to_odd", + "llvm.ppc.sync" => "__builtin_ppc_sync", + "llvm.ppc.tabort" => "__builtin_tabort", + "llvm.ppc.tabortdc" => "__builtin_tabortdc", + "llvm.ppc.tabortdci" => "__builtin_tabortdci", + "llvm.ppc.tabortwc" => "__builtin_tabortwc", + "llvm.ppc.tabortwci" => "__builtin_tabortwci", + "llvm.ppc.tbegin" => "__builtin_tbegin", + "llvm.ppc.tcheck" => "__builtin_tcheck", + "llvm.ppc.tdw" => "__builtin_ppc_tdw", + "llvm.ppc.tend" => "__builtin_tend", + "llvm.ppc.tendall" => "__builtin_tendall", + "llvm.ppc.trap" => "__builtin_ppc_trap", + "llvm.ppc.trapd" => "__builtin_ppc_trapd", + "llvm.ppc.trechkpt" => "__builtin_trechkpt", + "llvm.ppc.treclaim" => "__builtin_treclaim", + "llvm.ppc.tresume" => "__builtin_tresume", + "llvm.ppc.truncf128.round.to.odd" => "__builtin_truncf128_round_to_odd", + "llvm.ppc.tsr" => "__builtin_tsr", + "llvm.ppc.tsuspend" => "__builtin_tsuspend", + "llvm.ppc.ttest" => "__builtin_ttest", + "llvm.ppc.tw" => "__builtin_ppc_tw", + "llvm.ppc.unpack.longdouble" => "__builtin_unpack_longdouble", + "llvm.ppc.vsx.xvcmpeqdp.p" => "__builtin_vsx_xvcmpeqdp_p", + "llvm.ppc.vsx.xvcmpeqsp.p" => "__builtin_vsx_xvcmpeqsp_p", + "llvm.ppc.vsx.xvcmpgedp.p" => "__builtin_vsx_xvcmpgedp_p", + "llvm.ppc.vsx.xvcmpgesp.p" => "__builtin_vsx_xvcmpgesp_p", + "llvm.ppc.vsx.xvcmpgtdp.p" => "__builtin_vsx_xvcmpgtdp_p", + "llvm.ppc.vsx.xvcmpgtsp.p" => "__builtin_vsx_xvcmpgtsp_p", + "llvm.ppc.vsx.xvredp" => "__builtin_vsx_xvredp", + "llvm.ppc.vsx.xvresp" => "__builtin_vsx_xvresp", + "llvm.ppc.vsx.xvrsqrtedp" => "__builtin_vsx_xvrsqrtedp", + "llvm.ppc.vsx.xvrsqrtesp" => "__builtin_vsx_xvrsqrtesp", + "llvm.ppc.vsx.xxpermx" => "__builtin_vsx_xxpermx", + // s390 + "llvm.s390.efpc" => "__builtin_s390_efpc", + "llvm.s390.etnd" => "__builtin_tx_nesting_depth", + "llvm.s390.lcbb" => "__builtin_s390_lcbb", + "llvm.s390.ppa.txassist" => "__builtin_tx_assist", + "llvm.s390.sfpc" => "__builtin_s390_sfpc", + "llvm.s390.tend" => "__builtin_tend", + "llvm.s390.vcfn" => "__builtin_s390_vcfn", + "llvm.s390.vclfnhs" => "__builtin_s390_vclfnhs", + "llvm.s390.vclfnls" => "__builtin_s390_vclfnls", + "llvm.s390.vcnf" => "__builtin_s390_vcnf", + "llvm.s390.vcrnfs" => "__builtin_s390_vcrnfs", + "llvm.s390.vlbb" => "__builtin_s390_vlbb", + "llvm.s390.vll" => "__builtin_s390_vll", + "llvm.s390.vlrl" => "__builtin_s390_vlrl", + "llvm.s390.vmslg" => "__builtin_s390_vmslg", + "llvm.s390.vpdi" => "__builtin_s390_vpdi", + "llvm.s390.vperm" => "__builtin_s390_vperm", + "llvm.s390.vsld" => "__builtin_s390_vsld", + "llvm.s390.vsldb" => "__builtin_s390_vsldb", + "llvm.s390.vsrd" => "__builtin_s390_vsrd", + "llvm.s390.vstl" => "__builtin_s390_vstl", + "llvm.s390.vstrl" => "__builtin_s390_vstrl", + // ve + "llvm.ve.vl.extract.vm512l" => "__builtin_ve_vl_extract_vm512l", + "llvm.ve.vl.extract.vm512u" => "__builtin_ve_vl_extract_vm512u", + "llvm.ve.vl.insert.vm512l" => "__builtin_ve_vl_insert_vm512l", + "llvm.ve.vl.insert.vm512u" => "__builtin_ve_vl_insert_vm512u", + "llvm.ve.vl.pack.f32a" => "__builtin_ve_vl_pack_f32a", + "llvm.ve.vl.pack.f32p" => "__builtin_ve_vl_pack_f32p", // x86 - "llvm.x86.addcarry.u32" => "__builtin_ia32_addcarry_u32", - "llvm.x86.addcarry.u64" => "__builtin_ia32_addcarry_u64", - "llvm.x86.addcarryx.u32" => "__builtin_ia32_addcarryx_u32", - "llvm.x86.addcarryx.u64" => "__builtin_ia32_addcarryx_u64", + "llvm.x86.3dnow.pavgusb" => "__builtin_ia32_pavgusb", + "llvm.x86.3dnow.pf2id" => "__builtin_ia32_pf2id", + "llvm.x86.3dnow.pfacc" => "__builtin_ia32_pfacc", + "llvm.x86.3dnow.pfadd" => "__builtin_ia32_pfadd", + "llvm.x86.3dnow.pfcmpeq" => "__builtin_ia32_pfcmpeq", + "llvm.x86.3dnow.pfcmpge" => "__builtin_ia32_pfcmpge", + "llvm.x86.3dnow.pfcmpgt" => "__builtin_ia32_pfcmpgt", + "llvm.x86.3dnow.pfmax" => "__builtin_ia32_pfmax", + "llvm.x86.3dnow.pfmin" => "__builtin_ia32_pfmin", + "llvm.x86.3dnow.pfmul" => "__builtin_ia32_pfmul", + "llvm.x86.3dnow.pfrcp" => "__builtin_ia32_pfrcp", + "llvm.x86.3dnow.pfrcpit1" => "__builtin_ia32_pfrcpit1", + "llvm.x86.3dnow.pfrcpit2" => "__builtin_ia32_pfrcpit2", + "llvm.x86.3dnow.pfrsqit1" => "__builtin_ia32_pfrsqit1", + "llvm.x86.3dnow.pfrsqrt" => "__builtin_ia32_pfrsqrt", + "llvm.x86.3dnow.pfsub" => "__builtin_ia32_pfsub", + "llvm.x86.3dnow.pfsubr" => "__builtin_ia32_pfsubr", + "llvm.x86.3dnow.pi2fd" => "__builtin_ia32_pi2fd", + "llvm.x86.3dnow.pmulhrw" => "__builtin_ia32_pmulhrw", + "llvm.x86.3dnowa.pf2iw" => "__builtin_ia32_pf2iw", + "llvm.x86.3dnowa.pfnacc" => "__builtin_ia32_pfnacc", + "llvm.x86.3dnowa.pfpnacc" => "__builtin_ia32_pfpnacc", + "llvm.x86.3dnowa.pi2fw" => "__builtin_ia32_pi2fw", "llvm.x86.aesni.aesdec" => "__builtin_ia32_aesdec128", + "llvm.x86.aesni.aesdec.256" => "__builtin_ia32_aesdec256", + "llvm.x86.aesni.aesdec.512" => "__builtin_ia32_aesdec512", "llvm.x86.aesni.aesdeclast" => "__builtin_ia32_aesdeclast128", + "llvm.x86.aesni.aesdeclast.256" => "__builtin_ia32_aesdeclast256", + "llvm.x86.aesni.aesdeclast.512" => "__builtin_ia32_aesdeclast512", "llvm.x86.aesni.aesenc" => "__builtin_ia32_aesenc128", + "llvm.x86.aesni.aesenc.256" => "__builtin_ia32_aesenc256", + "llvm.x86.aesni.aesenc.512" => "__builtin_ia32_aesenc512", "llvm.x86.aesni.aesenclast" => "__builtin_ia32_aesenclast128", + "llvm.x86.aesni.aesenclast.256" => "__builtin_ia32_aesenclast256", + "llvm.x86.aesni.aesenclast.512" => "__builtin_ia32_aesenclast512", "llvm.x86.aesni.aesimc" => "__builtin_ia32_aesimc128", "llvm.x86.aesni.aeskeygenassist" => "__builtin_ia32_aeskeygenassist128", "llvm.x86.avx.addsub.pd.256" => "__builtin_ia32_addsubpd256", "llvm.x86.avx.addsub.ps.256" => "__builtin_ia32_addsubps256", - "llvm.x86.avx.blend.pd.256" => "__builtin_ia32_blendpd256", - "llvm.x86.avx.blend.ps.256" => "__builtin_ia32_blendps256", "llvm.x86.avx.blendv.pd.256" => "__builtin_ia32_blendvpd256", "llvm.x86.avx.blendv.ps.256" => "__builtin_ia32_blendvps256", - "llvm.x86.avx.cmp.pd.256" => "__builtin_ia32_cmppd256", - "llvm.x86.avx.cmp.ps.256" => "__builtin_ia32_cmpps256", "llvm.x86.avx.cvt.pd2.ps.256" => "__builtin_ia32_cvtpd2ps256", "llvm.x86.avx.cvt.pd2dq.256" => "__builtin_ia32_cvtpd2dq256", - "llvm.x86.avx.cvt.ps2.pd.256" => "__builtin_ia32_cvtps2pd256", "llvm.x86.avx.cvt.ps2dq.256" => "__builtin_ia32_cvtps2dq256", - "llvm.x86.avx.cvtdq2.pd.256" => "__builtin_ia32_cvtdq2pd256", - "llvm.x86.avx.cvtdq2.ps.256" => "__builtin_ia32_cvtdq2ps256", "llvm.x86.avx.cvtt.pd2dq.256" => "__builtin_ia32_cvttpd2dq256", "llvm.x86.avx.cvtt.ps2dq.256" => "__builtin_ia32_cvttps2dq256", "llvm.x86.avx.dp.ps.256" => "__builtin_ia32_dpps256", @@ -2243,22 +1328,6 @@ match name { "llvm.x86.avx.round.pd.256" => "__builtin_ia32_roundpd256", "llvm.x86.avx.round.ps.256" => "__builtin_ia32_roundps256", "llvm.x86.avx.rsqrt.ps.256" => "__builtin_ia32_rsqrtps256", - "llvm.x86.avx.sqrt.pd.256" => "__builtin_ia32_sqrtpd256", - "llvm.x86.avx.sqrt.ps.256" => "__builtin_ia32_sqrtps256", - "llvm.x86.avx.storeu.dq.256" => "__builtin_ia32_storedqu256", - "llvm.x86.avx.storeu.pd.256" => "__builtin_ia32_storeupd256", - "llvm.x86.avx.storeu.ps.256" => "__builtin_ia32_storeups256", - "llvm.x86.avx.vbroadcastf128.pd.256" => "__builtin_ia32_vbroadcastf128_pd256", - "llvm.x86.avx.vbroadcastf128.ps.256" => "__builtin_ia32_vbroadcastf128_ps256", - "llvm.x86.avx.vextractf128.pd.256" => "__builtin_ia32_vextractf128_pd256", - "llvm.x86.avx.vextractf128.ps.256" => "__builtin_ia32_vextractf128_ps256", - "llvm.x86.avx.vextractf128.si.256" => "__builtin_ia32_vextractf128_si256", - "llvm.x86.avx.vinsertf128.pd.256" => "__builtin_ia32_vinsertf128_pd256", - "llvm.x86.avx.vinsertf128.ps.256" => "__builtin_ia32_vinsertf128_ps256", - "llvm.x86.avx.vinsertf128.si.256" => "__builtin_ia32_vinsertf128_si256", - "llvm.x86.avx.vperm2f128.pd.256" => "__builtin_ia32_vperm2f128_pd256", - "llvm.x86.avx.vperm2f128.ps.256" => "__builtin_ia32_vperm2f128_ps256", - "llvm.x86.avx.vperm2f128.si.256" => "__builtin_ia32_vperm2f128_si256", "llvm.x86.avx.vpermilvar.pd" => "__builtin_ia32_vpermilvarpd", "llvm.x86.avx.vpermilvar.pd.256" => "__builtin_ia32_vpermilvarpd256", "llvm.x86.avx.vpermilvar.ps" => "__builtin_ia32_vpermilvarps", @@ -2301,33 +1370,14 @@ match name { "llvm.x86.avx2.maskstore.d.256" => "__builtin_ia32_maskstored256", "llvm.x86.avx2.maskstore.q" => "__builtin_ia32_maskstoreq", "llvm.x86.avx2.maskstore.q.256" => "__builtin_ia32_maskstoreq256", - "llvm.x86.avx2.movntdqa" => "__builtin_ia32_movntdqa256", "llvm.x86.avx2.mpsadbw" => "__builtin_ia32_mpsadbw256", - "llvm.x86.avx2.pabs.b" => "__builtin_ia32_pabsb256", - "llvm.x86.avx2.pabs.d" => "__builtin_ia32_pabsd256", - "llvm.x86.avx2.pabs.w" => "__builtin_ia32_pabsw256", "llvm.x86.avx2.packssdw" => "__builtin_ia32_packssdw256", "llvm.x86.avx2.packsswb" => "__builtin_ia32_packsswb256", "llvm.x86.avx2.packusdw" => "__builtin_ia32_packusdw256", "llvm.x86.avx2.packuswb" => "__builtin_ia32_packuswb256", - "llvm.x86.avx2.padds.b" => "__builtin_ia32_paddsb256", - "llvm.x86.avx2.padds.w" => "__builtin_ia32_paddsw256", - "llvm.x86.avx2.paddus.b" => "__builtin_ia32_paddusb256", - "llvm.x86.avx2.paddus.w" => "__builtin_ia32_paddusw256", "llvm.x86.avx2.pavg.b" => "__builtin_ia32_pavgb256", "llvm.x86.avx2.pavg.w" => "__builtin_ia32_pavgw256", - "llvm.x86.avx2.pblendd.128" => "__builtin_ia32_pblendd128", - "llvm.x86.avx2.pblendd.256" => "__builtin_ia32_pblendd256", "llvm.x86.avx2.pblendvb" => "__builtin_ia32_pblendvb256", - "llvm.x86.avx2.pblendw" => "__builtin_ia32_pblendw256", - "llvm.x86.avx2.pbroadcastb.128" => "__builtin_ia32_pbroadcastb128", - "llvm.x86.avx2.pbroadcastb.256" => "__builtin_ia32_pbroadcastb256", - "llvm.x86.avx2.pbroadcastd.128" => "__builtin_ia32_pbroadcastd128", - "llvm.x86.avx2.pbroadcastd.256" => "__builtin_ia32_pbroadcastd256", - "llvm.x86.avx2.pbroadcastq.128" => "__builtin_ia32_pbroadcastq128", - "llvm.x86.avx2.pbroadcastq.256" => "__builtin_ia32_pbroadcastq256", - "llvm.x86.avx2.pbroadcastw.128" => "__builtin_ia32_pbroadcastw128", - "llvm.x86.avx2.pbroadcastw.256" => "__builtin_ia32_pbroadcastw256", "llvm.x86.avx2.permd" => "__builtin_ia32_permvarsi256", "llvm.x86.avx2.permps" => "__builtin_ia32_permvarsf256", "llvm.x86.avx2.phadd.d" => "__builtin_ia32_phaddd256", @@ -2338,44 +1388,16 @@ match name { "llvm.x86.avx2.phsub.w" => "__builtin_ia32_phsubw256", "llvm.x86.avx2.pmadd.ub.sw" => "__builtin_ia32_pmaddubsw256", "llvm.x86.avx2.pmadd.wd" => "__builtin_ia32_pmaddwd256", - "llvm.x86.avx2.pmaxs.b" => "__builtin_ia32_pmaxsb256", - "llvm.x86.avx2.pmaxs.d" => "__builtin_ia32_pmaxsd256", - "llvm.x86.avx2.pmaxs.w" => "__builtin_ia32_pmaxsw256", - "llvm.x86.avx2.pmaxu.b" => "__builtin_ia32_pmaxub256", - "llvm.x86.avx2.pmaxu.d" => "__builtin_ia32_pmaxud256", - "llvm.x86.avx2.pmaxu.w" => "__builtin_ia32_pmaxuw256", - "llvm.x86.avx2.pmins.b" => "__builtin_ia32_pminsb256", - "llvm.x86.avx2.pmins.d" => "__builtin_ia32_pminsd256", - "llvm.x86.avx2.pmins.w" => "__builtin_ia32_pminsw256", - "llvm.x86.avx2.pminu.b" => "__builtin_ia32_pminub256", - "llvm.x86.avx2.pminu.d" => "__builtin_ia32_pminud256", - "llvm.x86.avx2.pminu.w" => "__builtin_ia32_pminuw256", "llvm.x86.avx2.pmovmskb" => "__builtin_ia32_pmovmskb256", - "llvm.x86.avx2.pmovsxbd" => "__builtin_ia32_pmovsxbd256", - "llvm.x86.avx2.pmovsxbq" => "__builtin_ia32_pmovsxbq256", - "llvm.x86.avx2.pmovsxbw" => "__builtin_ia32_pmovsxbw256", - "llvm.x86.avx2.pmovsxdq" => "__builtin_ia32_pmovsxdq256", - "llvm.x86.avx2.pmovsxwd" => "__builtin_ia32_pmovsxwd256", - "llvm.x86.avx2.pmovsxwq" => "__builtin_ia32_pmovsxwq256", - "llvm.x86.avx2.pmovzxbd" => "__builtin_ia32_pmovzxbd256", - "llvm.x86.avx2.pmovzxbq" => "__builtin_ia32_pmovzxbq256", - "llvm.x86.avx2.pmovzxbw" => "__builtin_ia32_pmovzxbw256", - "llvm.x86.avx2.pmovzxdq" => "__builtin_ia32_pmovzxdq256", - "llvm.x86.avx2.pmovzxwd" => "__builtin_ia32_pmovzxwd256", - "llvm.x86.avx2.pmovzxwq" => "__builtin_ia32_pmovzxwq256", - "llvm.x86.avx2.pmul.dq" => "__builtin_ia32_pmuldq256", "llvm.x86.avx2.pmul.hr.sw" => "__builtin_ia32_pmulhrsw256", "llvm.x86.avx2.pmulh.w" => "__builtin_ia32_pmulhw256", "llvm.x86.avx2.pmulhu.w" => "__builtin_ia32_pmulhuw256", - "llvm.x86.avx2.pmulu.dq" => "__builtin_ia32_pmuludq256", "llvm.x86.avx2.psad.bw" => "__builtin_ia32_psadbw256", "llvm.x86.avx2.pshuf.b" => "__builtin_ia32_pshufb256", "llvm.x86.avx2.psign.b" => "__builtin_ia32_psignb256", "llvm.x86.avx2.psign.d" => "__builtin_ia32_psignd256", "llvm.x86.avx2.psign.w" => "__builtin_ia32_psignw256", "llvm.x86.avx2.psll.d" => "__builtin_ia32_pslld256", - "llvm.x86.avx2.psll.dq" => "__builtin_ia32_pslldqi256", - "llvm.x86.avx2.psll.dq.bs" => "__builtin_ia32_pslldqi256_byteshift", "llvm.x86.avx2.psll.q" => "__builtin_ia32_psllq256", "llvm.x86.avx2.psll.w" => "__builtin_ia32_psllw256", "llvm.x86.avx2.pslli.d" => "__builtin_ia32_pslldi256", @@ -2392,8 +1414,6 @@ match name { "llvm.x86.avx2.psrav.d" => "__builtin_ia32_psrav4si", "llvm.x86.avx2.psrav.d.256" => "__builtin_ia32_psrav8si", "llvm.x86.avx2.psrl.d" => "__builtin_ia32_psrld256", - "llvm.x86.avx2.psrl.dq" => "__builtin_ia32_psrldqi256", - "llvm.x86.avx2.psrl.dq.bs" => "__builtin_ia32_psrldqi256_byteshift", "llvm.x86.avx2.psrl.q" => "__builtin_ia32_psrlq256", "llvm.x86.avx2.psrl.w" => "__builtin_ia32_psrlw256", "llvm.x86.avx2.psrli.d" => "__builtin_ia32_psrldi256", @@ -2403,188 +1423,588 @@ match name { "llvm.x86.avx2.psrlv.d.256" => "__builtin_ia32_psrlv8si", "llvm.x86.avx2.psrlv.q" => "__builtin_ia32_psrlv2di", "llvm.x86.avx2.psrlv.q.256" => "__builtin_ia32_psrlv4di", - "llvm.x86.avx2.psubs.b" => "__builtin_ia32_psubsb256", - "llvm.x86.avx2.psubs.w" => "__builtin_ia32_psubsw256", - "llvm.x86.avx2.psubus.b" => "__builtin_ia32_psubusb256", - "llvm.x86.avx2.psubus.w" => "__builtin_ia32_psubusw256", - "llvm.x86.avx2.vbroadcast.sd.pd.256" => "__builtin_ia32_vbroadcastsd_pd256", - "llvm.x86.avx2.vbroadcast.ss.ps" => "__builtin_ia32_vbroadcastss_ps", - "llvm.x86.avx2.vbroadcast.ss.ps.256" => "__builtin_ia32_vbroadcastss_ps256", - "llvm.x86.avx2.vextracti128" => "__builtin_ia32_extract128i256", - "llvm.x86.avx2.vinserti128" => "__builtin_ia32_insert128i256", - "llvm.x86.avx2.vperm2i128" => "__builtin_ia32_permti256", - "llvm.x86.avx512.cvtsd2usi" => "__builtin_ia32_cvtsd2usi", - "llvm.x86.avx512.cvtsd2usi64" => "__builtin_ia32_cvtsd2usi64", - "llvm.x86.avx512.cvtss2usi" => "__builtin_ia32_cvtss2usi", - "llvm.x86.avx512.cvtss2usi64" => "__builtin_ia32_cvtss2usi64", - "llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_cvttsd2usi", - "llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_cvttsd2usi64", - "llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_cvttss2usi", - "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_cvttss2usi64", - "llvm.x86.avx512.cvtusi2sd" => "__builtin_ia32_cvtusi2sd", - "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss", - "llvm.x86.avx512.cvtusi642sd" => "__builtin_ia32_cvtusi642sd", - "llvm.x86.avx512.cvtusi642ss" => "__builtin_ia32_cvtusi642ss", - "llvm.x86.avx512.gather.dpd.512" => "__builtin_ia32_gathersiv8df", - "llvm.x86.avx512.gather.dpi.512" => "__builtin_ia32_gathersiv16si", - "llvm.x86.avx512.gather.dpq.512" => "__builtin_ia32_gathersiv8di", - "llvm.x86.avx512.gather.dps.512" => "__builtin_ia32_gathersiv16sf", - "llvm.x86.avx512.gather.qpd.512" => "__builtin_ia32_gatherdiv8df", - "llvm.x86.avx512.gather.qpi.512" => "__builtin_ia32_gatherdiv16si", - "llvm.x86.avx512.gather.qpq.512" => "__builtin_ia32_gatherdiv8di", - "llvm.x86.avx512.gather.qps.512" => "__builtin_ia32_gatherdiv16sf", + "llvm.x86.avx512.add.pd.512" => "__builtin_ia32_addpd512", + "llvm.x86.avx512.add.ps.512" => "__builtin_ia32_addps512", + "llvm.x86.avx512.broadcastmb.128" => "__builtin_ia32_broadcastmb128", + "llvm.x86.avx512.broadcastmb.256" => "__builtin_ia32_broadcastmb256", + "llvm.x86.avx512.broadcastmb.512" => "__builtin_ia32_broadcastmb512", + "llvm.x86.avx512.broadcastmw.128" => "__builtin_ia32_broadcastmw128", + "llvm.x86.avx512.broadcastmw.256" => "__builtin_ia32_broadcastmw256", + "llvm.x86.avx512.broadcastmw.512" => "__builtin_ia32_broadcastmw512", + "llvm.x86.avx512.conflict.d.128" => "__builtin_ia32_vpconflictsi_128", + "llvm.x86.avx512.conflict.d.256" => "__builtin_ia32_vpconflictsi_256", + "llvm.x86.avx512.conflict.d.512" => "__builtin_ia32_vpconflictsi_512", + "llvm.x86.avx512.conflict.q.128" => "__builtin_ia32_vpconflictdi_128", + "llvm.x86.avx512.conflict.q.256" => "__builtin_ia32_vpconflictdi_256", + "llvm.x86.avx512.conflict.q.512" => "__builtin_ia32_vpconflictdi_512", + "llvm.x86.avx512.cvtsi2sd64" => "__builtin_ia32_cvtsi2sd64", + "llvm.x86.avx512.cvtsi2ss32" => "__builtin_ia32_cvtsi2ss32", + "llvm.x86.avx512.cvtsi2ss64" => "__builtin_ia32_cvtsi2ss64", + "llvm.x86.avx512.cvttsd2si" => "__builtin_ia32_vcvttsd2si32", + "llvm.x86.avx512.cvttsd2si64" => "__builtin_ia32_vcvttsd2si64", + "llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_vcvttsd2usi32", + "llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_vcvttsd2usi64", + "llvm.x86.avx512.cvttss2si" => "__builtin_ia32_vcvttss2si32", + "llvm.x86.avx512.cvttss2si64" => "__builtin_ia32_vcvttss2si64", + "llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_vcvttss2usi32", + "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_vcvttss2usi64", + "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss32", + "llvm.x86.avx512.cvtusi642sd" => "__builtin_ia32_cvtusi2sd64", + "llvm.x86.avx512.cvtusi642ss" => "__builtin_ia32_cvtusi2ss64", + "llvm.x86.avx512.dbpsadbw.128" => "__builtin_ia32_dbpsadbw128", + "llvm.x86.avx512.dbpsadbw.256" => "__builtin_ia32_dbpsadbw256", + "llvm.x86.avx512.dbpsadbw.512" => "__builtin_ia32_dbpsadbw512", + "llvm.x86.avx512.div.pd.512" => "__builtin_ia32_divpd512", + "llvm.x86.avx512.div.ps.512" => "__builtin_ia32_divps512", + "llvm.x86.avx512.exp2.pd" => "__builtin_ia32_exp2pd_mask", + "llvm.x86.avx512.exp2.ps" => "__builtin_ia32_exp2ps_mask", "llvm.x86.avx512.gatherpf.dpd.512" => "__builtin_ia32_gatherpfdpd", "llvm.x86.avx512.gatherpf.dps.512" => "__builtin_ia32_gatherpfdps", "llvm.x86.avx512.gatherpf.qpd.512" => "__builtin_ia32_gatherpfqpd", "llvm.x86.avx512.gatherpf.qps.512" => "__builtin_ia32_gatherpfqps", - "llvm.x86.avx512.kand.w" => "__builtin_ia32_kandhi", - "llvm.x86.avx512.kandn.w" => "__builtin_ia32_kandnhi", - "llvm.x86.avx512.knot.w" => "__builtin_ia32_knothi", - "llvm.x86.avx512.kor.w" => "__builtin_ia32_korhi", - "llvm.x86.avx512.kortestc.w" => "__builtin_ia32_kortestchi", - "llvm.x86.avx512.kortestz.w" => "__builtin_ia32_kortestzhi", - "llvm.x86.avx512.kunpck.bw" => "__builtin_ia32_kunpckhi", - "llvm.x86.avx512.kxnor.w" => "__builtin_ia32_kxnorhi", - "llvm.x86.avx512.kxor.w" => "__builtin_ia32_kxorhi", - "llvm.x86.avx512.mask.blend.d.512" => "__builtin_ia32_blendmd_512_mask", - "llvm.x86.avx512.mask.blend.pd.512" => "__builtin_ia32_blendmpd_512_mask", - "llvm.x86.avx512.mask.blend.ps.512" => "__builtin_ia32_blendmps_512_mask", - "llvm.x86.avx512.mask.blend.q.512" => "__builtin_ia32_blendmq_512_mask", - "llvm.x86.avx512.mask.cmp.pd.512" => "__builtin_ia32_cmppd512_mask", - "llvm.x86.avx512.mask.cmp.ps.512" => "__builtin_ia32_cmpps512_mask", - "llvm.x86.avx512.mask.conflict.d.512" => "__builtin_ia32_vpconflictsi_512_mask", - "llvm.x86.avx512.mask.conflict.q.512" => "__builtin_ia32_vpconflictdi_512_mask", - "llvm.x86.avx512.mask.cvtdq2pd.512" => "__builtin_ia32_cvtdq2pd512_mask", - "llvm.x86.avx512.mask.cvtdq2ps.512" => "__builtin_ia32_cvtdq2ps512_mask", + "llvm.x86.avx512.mask.add.sd.round" => "__builtin_ia32_addsd_round_mask", + "llvm.x86.avx512.mask.add.ss.round" => "__builtin_ia32_addss_round_mask", + "llvm.x86.avx512.mask.cmp.sd" => "__builtin_ia32_cmpsd_mask", + "llvm.x86.avx512.mask.cmp.ss" => "__builtin_ia32_cmpss_mask", + "llvm.x86.avx512.mask.cvtpd2dq.128" => "__builtin_ia32_cvtpd2dq128_mask", "llvm.x86.avx512.mask.cvtpd2dq.512" => "__builtin_ia32_cvtpd2dq512_mask", + "llvm.x86.avx512.mask.cvtpd2ps" => "__builtin_ia32_cvtpd2ps_mask", "llvm.x86.avx512.mask.cvtpd2ps.512" => "__builtin_ia32_cvtpd2ps512_mask", + "llvm.x86.avx512.mask.cvtpd2qq.128" => "__builtin_ia32_cvtpd2qq128_mask", + "llvm.x86.avx512.mask.cvtpd2qq.256" => "__builtin_ia32_cvtpd2qq256_mask", + "llvm.x86.avx512.mask.cvtpd2qq.512" => "__builtin_ia32_cvtpd2qq512_mask", + "llvm.x86.avx512.mask.cvtpd2udq.128" => "__builtin_ia32_cvtpd2udq128_mask", + "llvm.x86.avx512.mask.cvtpd2udq.256" => "__builtin_ia32_cvtpd2udq256_mask", "llvm.x86.avx512.mask.cvtpd2udq.512" => "__builtin_ia32_cvtpd2udq512_mask", + "llvm.x86.avx512.mask.cvtpd2uqq.128" => "__builtin_ia32_cvtpd2uqq128_mask", + "llvm.x86.avx512.mask.cvtpd2uqq.256" => "__builtin_ia32_cvtpd2uqq256_mask", + "llvm.x86.avx512.mask.cvtpd2uqq.512" => "__builtin_ia32_cvtpd2uqq512_mask", + "llvm.x86.avx512.mask.cvtps2dq.128" => "__builtin_ia32_cvtps2dq128_mask", + "llvm.x86.avx512.mask.cvtps2dq.256" => "__builtin_ia32_cvtps2dq256_mask", "llvm.x86.avx512.mask.cvtps2dq.512" => "__builtin_ia32_cvtps2dq512_mask", + "llvm.x86.avx512.mask.cvtps2pd.512" => "__builtin_ia32_cvtps2pd512_mask", + "llvm.x86.avx512.mask.cvtps2qq.128" => "__builtin_ia32_cvtps2qq128_mask", + "llvm.x86.avx512.mask.cvtps2qq.256" => "__builtin_ia32_cvtps2qq256_mask", + "llvm.x86.avx512.mask.cvtps2qq.512" => "__builtin_ia32_cvtps2qq512_mask", + "llvm.x86.avx512.mask.cvtps2udq.128" => "__builtin_ia32_cvtps2udq128_mask", + "llvm.x86.avx512.mask.cvtps2udq.256" => "__builtin_ia32_cvtps2udq256_mask", "llvm.x86.avx512.mask.cvtps2udq.512" => "__builtin_ia32_cvtps2udq512_mask", + "llvm.x86.avx512.mask.cvtps2uqq.128" => "__builtin_ia32_cvtps2uqq128_mask", + "llvm.x86.avx512.mask.cvtps2uqq.256" => "__builtin_ia32_cvtps2uqq256_mask", + "llvm.x86.avx512.mask.cvtps2uqq.512" => "__builtin_ia32_cvtps2uqq512_mask", + "llvm.x86.avx512.mask.cvtqq2ps.128" => "__builtin_ia32_cvtqq2ps128_mask", + "llvm.x86.avx512.mask.cvtsd2ss.round" => "__builtin_ia32_cvtsd2ss_round_mask", + "llvm.x86.avx512.mask.cvtss2sd.round" => "__builtin_ia32_cvtss2sd_round_mask", + "llvm.x86.avx512.mask.cvttpd2dq.128" => "__builtin_ia32_cvttpd2dq128_mask", "llvm.x86.avx512.mask.cvttpd2dq.512" => "__builtin_ia32_cvttpd2dq512_mask", + "llvm.x86.avx512.mask.cvttpd2qq.128" => "__builtin_ia32_cvttpd2qq128_mask", + "llvm.x86.avx512.mask.cvttpd2qq.256" => "__builtin_ia32_cvttpd2qq256_mask", + "llvm.x86.avx512.mask.cvttpd2qq.512" => "__builtin_ia32_cvttpd2qq512_mask", + "llvm.x86.avx512.mask.cvttpd2udq.128" => "__builtin_ia32_cvttpd2udq128_mask", + "llvm.x86.avx512.mask.cvttpd2udq.256" => "__builtin_ia32_cvttpd2udq256_mask", "llvm.x86.avx512.mask.cvttpd2udq.512" => "__builtin_ia32_cvttpd2udq512_mask", + "llvm.x86.avx512.mask.cvttpd2uqq.128" => "__builtin_ia32_cvttpd2uqq128_mask", + "llvm.x86.avx512.mask.cvttpd2uqq.256" => "__builtin_ia32_cvttpd2uqq256_mask", + "llvm.x86.avx512.mask.cvttpd2uqq.512" => "__builtin_ia32_cvttpd2uqq512_mask", "llvm.x86.avx512.mask.cvttps2dq.512" => "__builtin_ia32_cvttps2dq512_mask", + "llvm.x86.avx512.mask.cvttps2qq.128" => "__builtin_ia32_cvttps2qq128_mask", + "llvm.x86.avx512.mask.cvttps2qq.256" => "__builtin_ia32_cvttps2qq256_mask", + "llvm.x86.avx512.mask.cvttps2qq.512" => "__builtin_ia32_cvttps2qq512_mask", + "llvm.x86.avx512.mask.cvttps2udq.128" => "__builtin_ia32_cvttps2udq128_mask", + "llvm.x86.avx512.mask.cvttps2udq.256" => "__builtin_ia32_cvttps2udq256_mask", "llvm.x86.avx512.mask.cvttps2udq.512" => "__builtin_ia32_cvttps2udq512_mask", - "llvm.x86.avx512.mask.cvtudq2pd.512" => "__builtin_ia32_cvtudq2pd512_mask", - "llvm.x86.avx512.mask.cvtudq2ps.512" => "__builtin_ia32_cvtudq2ps512_mask", - "llvm.x86.avx512.mask.loadu.d.512" => "__builtin_ia32_loaddqusi512_mask", - "llvm.x86.avx512.mask.loadu.pd.512" => "__builtin_ia32_loadupd512_mask", - "llvm.x86.avx512.mask.loadu.ps.512" => "__builtin_ia32_loadups512_mask", - "llvm.x86.avx512.mask.loadu.q.512" => "__builtin_ia32_loaddqudi512_mask", - "llvm.x86.avx512.mask.lzcnt.d.512" => "__builtin_ia32_vplzcntd_512_mask", - "llvm.x86.avx512.mask.lzcnt.q.512" => "__builtin_ia32_vplzcntq_512_mask", - "llvm.x86.avx512.mask.max.pd.512" => "__builtin_ia32_maxpd512_mask", - "llvm.x86.avx512.mask.max.ps.512" => "__builtin_ia32_maxps512_mask", - "llvm.x86.avx512.mask.min.pd.512" => "__builtin_ia32_minpd512_mask", - "llvm.x86.avx512.mask.min.ps.512" => "__builtin_ia32_minps512_mask", - "llvm.x86.avx512.mask.pabs.d.512" => "__builtin_ia32_pabsd512_mask", - "llvm.x86.avx512.mask.pabs.q.512" => "__builtin_ia32_pabsq512_mask", - "llvm.x86.avx512.mask.pand.d.512" => "__builtin_ia32_pandd512_mask", - "llvm.x86.avx512.mask.pand.q.512" => "__builtin_ia32_pandq512_mask", - "llvm.x86.avx512.mask.pbroadcast.d.gpr.512" => "__builtin_ia32_pbroadcastd512_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.q.gpr.512" => "__builtin_ia32_pbroadcastq512_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.q.mem.512" => "__builtin_ia32_pbroadcastq512_mem_mask", - "llvm.x86.avx512.mask.pcmpeq.b.128" => "__builtin_ia32_pcmpeqb128_mask", - "llvm.x86.avx512.mask.pcmpeq.b.256" => "__builtin_ia32_pcmpeqb256_mask", - "llvm.x86.avx512.mask.pcmpeq.b.512" => "__builtin_ia32_pcmpeqb512_mask", - "llvm.x86.avx512.mask.pcmpeq.d.128" => "__builtin_ia32_pcmpeqd128_mask", - "llvm.x86.avx512.mask.pcmpeq.d.256" => "__builtin_ia32_pcmpeqd256_mask", - "llvm.x86.avx512.mask.pcmpeq.d.512" => "__builtin_ia32_pcmpeqd512_mask", - "llvm.x86.avx512.mask.pcmpeq.q.128" => "__builtin_ia32_pcmpeqq128_mask", - "llvm.x86.avx512.mask.pcmpeq.q.256" => "__builtin_ia32_pcmpeqq256_mask", - "llvm.x86.avx512.mask.pcmpeq.q.512" => "__builtin_ia32_pcmpeqq512_mask", - "llvm.x86.avx512.mask.pcmpeq.w.128" => "__builtin_ia32_pcmpeqw128_mask", - "llvm.x86.avx512.mask.pcmpeq.w.256" => "__builtin_ia32_pcmpeqw256_mask", - "llvm.x86.avx512.mask.pcmpeq.w.512" => "__builtin_ia32_pcmpeqw512_mask", - "llvm.x86.avx512.mask.pcmpgt.b.128" => "__builtin_ia32_pcmpgtb128_mask", - "llvm.x86.avx512.mask.pcmpgt.b.256" => "__builtin_ia32_pcmpgtb256_mask", - "llvm.x86.avx512.mask.pcmpgt.b.512" => "__builtin_ia32_pcmpgtb512_mask", - "llvm.x86.avx512.mask.pcmpgt.d.128" => "__builtin_ia32_pcmpgtd128_mask", - "llvm.x86.avx512.mask.pcmpgt.d.256" => "__builtin_ia32_pcmpgtd256_mask", - "llvm.x86.avx512.mask.pcmpgt.d.512" => "__builtin_ia32_pcmpgtd512_mask", - "llvm.x86.avx512.mask.pcmpgt.q.128" => "__builtin_ia32_pcmpgtq128_mask", - "llvm.x86.avx512.mask.pcmpgt.q.256" => "__builtin_ia32_pcmpgtq256_mask", - "llvm.x86.avx512.mask.pcmpgt.q.512" => "__builtin_ia32_pcmpgtq512_mask", - "llvm.x86.avx512.mask.pcmpgt.w.128" => "__builtin_ia32_pcmpgtw128_mask", - "llvm.x86.avx512.mask.pcmpgt.w.256" => "__builtin_ia32_pcmpgtw256_mask", - "llvm.x86.avx512.mask.pcmpgt.w.512" => "__builtin_ia32_pcmpgtw512_mask", - "llvm.x86.avx512.mask.pmaxs.d.512" => "__builtin_ia32_pmaxsd512_mask", - "llvm.x86.avx512.mask.pmaxs.q.512" => "__builtin_ia32_pmaxsq512_mask", - "llvm.x86.avx512.mask.pmaxu.d.512" => "__builtin_ia32_pmaxud512_mask", - "llvm.x86.avx512.mask.pmaxu.q.512" => "__builtin_ia32_pmaxuq512_mask", - "llvm.x86.avx512.mask.pmins.d.512" => "__builtin_ia32_pminsd512_mask", - "llvm.x86.avx512.mask.pmins.q.512" => "__builtin_ia32_pminsq512_mask", - "llvm.x86.avx512.mask.pminu.d.512" => "__builtin_ia32_pminud512_mask", - "llvm.x86.avx512.mask.pminu.q.512" => "__builtin_ia32_pminuq512_mask", - "llvm.x86.avx512.mask.pmul.dq.512" => "__builtin_ia32_pmuldq512_mask", - "llvm.x86.avx512.mask.pmulu.dq.512" => "__builtin_ia32_pmuludq512_mask", - "llvm.x86.avx512.mask.ptestm.d.512" => "__builtin_ia32_ptestmd512", - "llvm.x86.avx512.mask.ptestm.q.512" => "__builtin_ia32_ptestmq512", + "llvm.x86.avx512.mask.cvttps2uqq.128" => "__builtin_ia32_cvttps2uqq128_mask", + "llvm.x86.avx512.mask.cvttps2uqq.256" => "__builtin_ia32_cvttps2uqq256_mask", + "llvm.x86.avx512.mask.cvttps2uqq.512" => "__builtin_ia32_cvttps2uqq512_mask", + "llvm.x86.avx512.mask.cvtuqq2ps.128" => "__builtin_ia32_cvtuqq2ps128_mask", + "llvm.x86.avx512.mask.div.sd.round" => "__builtin_ia32_divsd_round_mask", + "llvm.x86.avx512.mask.div.ss.round" => "__builtin_ia32_divss_round_mask", + "llvm.x86.avx512.mask.fixupimm.pd.128" => "__builtin_ia32_fixupimmpd128_mask", + "llvm.x86.avx512.mask.fixupimm.pd.256" => "__builtin_ia32_fixupimmpd256_mask", + "llvm.x86.avx512.mask.fixupimm.pd.512" => "__builtin_ia32_fixupimmpd512_mask", + "llvm.x86.avx512.mask.fixupimm.ps.128" => "__builtin_ia32_fixupimmps128_mask", + "llvm.x86.avx512.mask.fixupimm.ps.256" => "__builtin_ia32_fixupimmps256_mask", + "llvm.x86.avx512.mask.fixupimm.ps.512" => "__builtin_ia32_fixupimmps512_mask", + "llvm.x86.avx512.mask.fixupimm.sd" => "__builtin_ia32_fixupimmsd_mask", + "llvm.x86.avx512.mask.fixupimm.ss" => "__builtin_ia32_fixupimmss_mask", + "llvm.x86.avx512.mask.fpclass.sd" => "__builtin_ia32_fpclasssd_mask", + "llvm.x86.avx512.mask.fpclass.ss" => "__builtin_ia32_fpclassss_mask", + "llvm.x86.avx512.mask.getexp.pd.128" => "__builtin_ia32_getexppd128_mask", + "llvm.x86.avx512.mask.getexp.pd.256" => "__builtin_ia32_getexppd256_mask", + "llvm.x86.avx512.mask.getexp.pd.512" => "__builtin_ia32_getexppd512_mask", + "llvm.x86.avx512.mask.getexp.ps.128" => "__builtin_ia32_getexpps128_mask", + "llvm.x86.avx512.mask.getexp.ps.256" => "__builtin_ia32_getexpps256_mask", + "llvm.x86.avx512.mask.getexp.ps.512" => "__builtin_ia32_getexpps512_mask", + "llvm.x86.avx512.mask.getexp.sd" => "__builtin_ia32_getexpsd128_round_mask", + "llvm.x86.avx512.mask.getexp.ss" => "__builtin_ia32_getexpss128_round_mask", + "llvm.x86.avx512.mask.getmant.pd.128" => "__builtin_ia32_getmantpd128_mask", + "llvm.x86.avx512.mask.getmant.pd.256" => "__builtin_ia32_getmantpd256_mask", + "llvm.x86.avx512.mask.getmant.pd.512" => "__builtin_ia32_getmantpd512_mask", + "llvm.x86.avx512.mask.getmant.ps.128" => "__builtin_ia32_getmantps128_mask", + "llvm.x86.avx512.mask.getmant.ps.256" => "__builtin_ia32_getmantps256_mask", + "llvm.x86.avx512.mask.getmant.ps.512" => "__builtin_ia32_getmantps512_mask", + "llvm.x86.avx512.mask.getmant.sd" => "__builtin_ia32_getmantsd_round_mask", + "llvm.x86.avx512.mask.getmant.ss" => "__builtin_ia32_getmantss_round_mask", + "llvm.x86.avx512.mask.max.sd.round" => "__builtin_ia32_maxsd_round_mask", + "llvm.x86.avx512.mask.max.ss.round" => "__builtin_ia32_maxss_round_mask", + "llvm.x86.avx512.mask.min.sd.round" => "__builtin_ia32_minsd_round_mask", + "llvm.x86.avx512.mask.min.ss.round" => "__builtin_ia32_minss_round_mask", + "llvm.x86.avx512.mask.mul.sd.round" => "__builtin_ia32_mulsd_round_mask", + "llvm.x86.avx512.mask.mul.ss.round" => "__builtin_ia32_mulss_round_mask", + "llvm.x86.avx512.mask.pmov.db.128" => "__builtin_ia32_pmovdb128_mask", + "llvm.x86.avx512.mask.pmov.db.256" => "__builtin_ia32_pmovdb256_mask", + "llvm.x86.avx512.mask.pmov.db.mem.128" => "__builtin_ia32_pmovdb128mem_mask", + "llvm.x86.avx512.mask.pmov.db.mem.256" => "__builtin_ia32_pmovdb256mem_mask", + "llvm.x86.avx512.mask.pmov.db.mem.512" => "__builtin_ia32_pmovdb512mem_mask", + "llvm.x86.avx512.mask.pmov.dw.128" => "__builtin_ia32_pmovdw128_mask", + "llvm.x86.avx512.mask.pmov.dw.256" => "__builtin_ia32_pmovdw256_mask", + "llvm.x86.avx512.mask.pmov.dw.mem.128" => "__builtin_ia32_pmovdw128mem_mask", + "llvm.x86.avx512.mask.pmov.dw.mem.256" => "__builtin_ia32_pmovdw256mem_mask", + "llvm.x86.avx512.mask.pmov.dw.mem.512" => "__builtin_ia32_pmovdw512mem_mask", + "llvm.x86.avx512.mask.pmov.qb.128" => "__builtin_ia32_pmovqb128_mask", + "llvm.x86.avx512.mask.pmov.qb.256" => "__builtin_ia32_pmovqb256_mask", + "llvm.x86.avx512.mask.pmov.qb.512" => "__builtin_ia32_pmovqb512_mask", + "llvm.x86.avx512.mask.pmov.qb.mem.128" => "__builtin_ia32_pmovqb128mem_mask", + "llvm.x86.avx512.mask.pmov.qb.mem.256" => "__builtin_ia32_pmovqb256mem_mask", + "llvm.x86.avx512.mask.pmov.qb.mem.512" => "__builtin_ia32_pmovqb512mem_mask", + "llvm.x86.avx512.mask.pmov.qd.128" => "__builtin_ia32_pmovqd128_mask", + "llvm.x86.avx512.mask.pmov.qd.mem.128" => "__builtin_ia32_pmovqd128mem_mask", + "llvm.x86.avx512.mask.pmov.qd.mem.256" => "__builtin_ia32_pmovqd256mem_mask", + "llvm.x86.avx512.mask.pmov.qd.mem.512" => "__builtin_ia32_pmovqd512mem_mask", + "llvm.x86.avx512.mask.pmov.qw.128" => "__builtin_ia32_pmovqw128_mask", + "llvm.x86.avx512.mask.pmov.qw.256" => "__builtin_ia32_pmovqw256_mask", + "llvm.x86.avx512.mask.pmov.qw.mem.128" => "__builtin_ia32_pmovqw128mem_mask", + "llvm.x86.avx512.mask.pmov.qw.mem.256" => "__builtin_ia32_pmovqw256mem_mask", + "llvm.x86.avx512.mask.pmov.qw.mem.512" => "__builtin_ia32_pmovqw512mem_mask", + "llvm.x86.avx512.mask.pmov.wb.128" => "__builtin_ia32_pmovwb128_mask", + "llvm.x86.avx512.mask.pmov.wb.mem.128" => "__builtin_ia32_pmovwb128mem_mask", + "llvm.x86.avx512.mask.pmov.wb.mem.256" => "__builtin_ia32_pmovwb256mem_mask", + "llvm.x86.avx512.mask.pmov.wb.mem.512" => "__builtin_ia32_pmovwb512mem_mask", + "llvm.x86.avx512.mask.pmovs.db.128" => "__builtin_ia32_pmovsdb128_mask", + "llvm.x86.avx512.mask.pmovs.db.256" => "__builtin_ia32_pmovsdb256_mask", + "llvm.x86.avx512.mask.pmovs.db.512" => "__builtin_ia32_pmovsdb512_mask", + "llvm.x86.avx512.mask.pmovs.db.mem.128" => "__builtin_ia32_pmovsdb128mem_mask", + "llvm.x86.avx512.mask.pmovs.db.mem.256" => "__builtin_ia32_pmovsdb256mem_mask", + "llvm.x86.avx512.mask.pmovs.db.mem.512" => "__builtin_ia32_pmovsdb512mem_mask", + "llvm.x86.avx512.mask.pmovs.dw.128" => "__builtin_ia32_pmovsdw128_mask", + "llvm.x86.avx512.mask.pmovs.dw.256" => "__builtin_ia32_pmovsdw256_mask", + "llvm.x86.avx512.mask.pmovs.dw.512" => "__builtin_ia32_pmovsdw512_mask", + "llvm.x86.avx512.mask.pmovs.dw.mem.128" => "__builtin_ia32_pmovsdw128mem_mask", + "llvm.x86.avx512.mask.pmovs.dw.mem.256" => "__builtin_ia32_pmovsdw256mem_mask", + "llvm.x86.avx512.mask.pmovs.dw.mem.512" => "__builtin_ia32_pmovsdw512mem_mask", + "llvm.x86.avx512.mask.pmovs.qb.128" => "__builtin_ia32_pmovsqb128_mask", + "llvm.x86.avx512.mask.pmovs.qb.256" => "__builtin_ia32_pmovsqb256_mask", + "llvm.x86.avx512.mask.pmovs.qb.512" => "__builtin_ia32_pmovsqb512_mask", + "llvm.x86.avx512.mask.pmovs.qb.mem.128" => "__builtin_ia32_pmovsqb128mem_mask", + "llvm.x86.avx512.mask.pmovs.qb.mem.256" => "__builtin_ia32_pmovsqb256mem_mask", + "llvm.x86.avx512.mask.pmovs.qb.mem.512" => "__builtin_ia32_pmovsqb512mem_mask", + "llvm.x86.avx512.mask.pmovs.qd.128" => "__builtin_ia32_pmovsqd128_mask", + "llvm.x86.avx512.mask.pmovs.qd.256" => "__builtin_ia32_pmovsqd256_mask", + "llvm.x86.avx512.mask.pmovs.qd.512" => "__builtin_ia32_pmovsqd512_mask", + "llvm.x86.avx512.mask.pmovs.qd.mem.128" => "__builtin_ia32_pmovsqd128mem_mask", + "llvm.x86.avx512.mask.pmovs.qd.mem.256" => "__builtin_ia32_pmovsqd256mem_mask", + "llvm.x86.avx512.mask.pmovs.qd.mem.512" => "__builtin_ia32_pmovsqd512mem_mask", + "llvm.x86.avx512.mask.pmovs.qw.128" => "__builtin_ia32_pmovsqw128_mask", + "llvm.x86.avx512.mask.pmovs.qw.256" => "__builtin_ia32_pmovsqw256_mask", + "llvm.x86.avx512.mask.pmovs.qw.512" => "__builtin_ia32_pmovsqw512_mask", + "llvm.x86.avx512.mask.pmovs.qw.mem.128" => "__builtin_ia32_pmovsqw128mem_mask", + "llvm.x86.avx512.mask.pmovs.qw.mem.256" => "__builtin_ia32_pmovsqw256mem_mask", + "llvm.x86.avx512.mask.pmovs.qw.mem.512" => "__builtin_ia32_pmovsqw512mem_mask", + "llvm.x86.avx512.mask.pmovs.wb.128" => "__builtin_ia32_pmovswb128_mask", + "llvm.x86.avx512.mask.pmovs.wb.256" => "__builtin_ia32_pmovswb256_mask", + "llvm.x86.avx512.mask.pmovs.wb.512" => "__builtin_ia32_pmovswb512_mask", + "llvm.x86.avx512.mask.pmovs.wb.mem.128" => "__builtin_ia32_pmovswb128mem_mask", + "llvm.x86.avx512.mask.pmovs.wb.mem.256" => "__builtin_ia32_pmovswb256mem_mask", + "llvm.x86.avx512.mask.pmovs.wb.mem.512" => "__builtin_ia32_pmovswb512mem_mask", + "llvm.x86.avx512.mask.pmovus.db.128" => "__builtin_ia32_pmovusdb128_mask", + "llvm.x86.avx512.mask.pmovus.db.256" => "__builtin_ia32_pmovusdb256_mask", + "llvm.x86.avx512.mask.pmovus.db.512" => "__builtin_ia32_pmovusdb512_mask", + "llvm.x86.avx512.mask.pmovus.db.mem.128" => "__builtin_ia32_pmovusdb128mem_mask", + "llvm.x86.avx512.mask.pmovus.db.mem.256" => "__builtin_ia32_pmovusdb256mem_mask", + "llvm.x86.avx512.mask.pmovus.db.mem.512" => "__builtin_ia32_pmovusdb512mem_mask", + "llvm.x86.avx512.mask.pmovus.dw.128" => "__builtin_ia32_pmovusdw128_mask", + "llvm.x86.avx512.mask.pmovus.dw.256" => "__builtin_ia32_pmovusdw256_mask", + "llvm.x86.avx512.mask.pmovus.dw.512" => "__builtin_ia32_pmovusdw512_mask", + "llvm.x86.avx512.mask.pmovus.dw.mem.128" => "__builtin_ia32_pmovusdw128mem_mask", + "llvm.x86.avx512.mask.pmovus.dw.mem.256" => "__builtin_ia32_pmovusdw256mem_mask", + "llvm.x86.avx512.mask.pmovus.dw.mem.512" => "__builtin_ia32_pmovusdw512mem_mask", + "llvm.x86.avx512.mask.pmovus.qb.128" => "__builtin_ia32_pmovusqb128_mask", + "llvm.x86.avx512.mask.pmovus.qb.256" => "__builtin_ia32_pmovusqb256_mask", + "llvm.x86.avx512.mask.pmovus.qb.512" => "__builtin_ia32_pmovusqb512_mask", + "llvm.x86.avx512.mask.pmovus.qb.mem.128" => "__builtin_ia32_pmovusqb128mem_mask", + "llvm.x86.avx512.mask.pmovus.qb.mem.256" => "__builtin_ia32_pmovusqb256mem_mask", + "llvm.x86.avx512.mask.pmovus.qb.mem.512" => "__builtin_ia32_pmovusqb512mem_mask", + "llvm.x86.avx512.mask.pmovus.qd.128" => "__builtin_ia32_pmovusqd128_mask", + "llvm.x86.avx512.mask.pmovus.qd.256" => "__builtin_ia32_pmovusqd256_mask", + "llvm.x86.avx512.mask.pmovus.qd.512" => "__builtin_ia32_pmovusqd512_mask", + "llvm.x86.avx512.mask.pmovus.qd.mem.128" => "__builtin_ia32_pmovusqd128mem_mask", + "llvm.x86.avx512.mask.pmovus.qd.mem.256" => "__builtin_ia32_pmovusqd256mem_mask", + "llvm.x86.avx512.mask.pmovus.qd.mem.512" => "__builtin_ia32_pmovusqd512mem_mask", + "llvm.x86.avx512.mask.pmovus.qw.128" => "__builtin_ia32_pmovusqw128_mask", + "llvm.x86.avx512.mask.pmovus.qw.256" => "__builtin_ia32_pmovusqw256_mask", + "llvm.x86.avx512.mask.pmovus.qw.512" => "__builtin_ia32_pmovusqw512_mask", + "llvm.x86.avx512.mask.pmovus.qw.mem.128" => "__builtin_ia32_pmovusqw128mem_mask", + "llvm.x86.avx512.mask.pmovus.qw.mem.256" => "__builtin_ia32_pmovusqw256mem_mask", + "llvm.x86.avx512.mask.pmovus.qw.mem.512" => "__builtin_ia32_pmovusqw512mem_mask", + "llvm.x86.avx512.mask.pmovus.wb.128" => "__builtin_ia32_pmovuswb128_mask", + "llvm.x86.avx512.mask.pmovus.wb.256" => "__builtin_ia32_pmovuswb256_mask", + "llvm.x86.avx512.mask.pmovus.wb.512" => "__builtin_ia32_pmovuswb512_mask", + "llvm.x86.avx512.mask.pmovus.wb.mem.128" => "__builtin_ia32_pmovuswb128mem_mask", + "llvm.x86.avx512.mask.pmovus.wb.mem.256" => "__builtin_ia32_pmovuswb256mem_mask", + "llvm.x86.avx512.mask.pmovus.wb.mem.512" => "__builtin_ia32_pmovuswb512mem_mask", + "llvm.x86.avx512.mask.range.pd.128" => "__builtin_ia32_rangepd128_mask", + "llvm.x86.avx512.mask.range.pd.256" => "__builtin_ia32_rangepd256_mask", + "llvm.x86.avx512.mask.range.pd.512" => "__builtin_ia32_rangepd512_mask", + "llvm.x86.avx512.mask.range.ps.128" => "__builtin_ia32_rangeps128_mask", + "llvm.x86.avx512.mask.range.ps.256" => "__builtin_ia32_rangeps256_mask", + "llvm.x86.avx512.mask.range.ps.512" => "__builtin_ia32_rangeps512_mask", + "llvm.x86.avx512.mask.range.sd" => "__builtin_ia32_rangesd128_round_mask", + "llvm.x86.avx512.mask.range.ss" => "__builtin_ia32_rangess128_round_mask", + "llvm.x86.avx512.mask.reduce.pd.128" => "__builtin_ia32_reducepd128_mask", + "llvm.x86.avx512.mask.reduce.pd.256" => "__builtin_ia32_reducepd256_mask", + "llvm.x86.avx512.mask.reduce.pd.512" => "__builtin_ia32_reducepd512_mask", + "llvm.x86.avx512.mask.reduce.ps.128" => "__builtin_ia32_reduceps128_mask", + "llvm.x86.avx512.mask.reduce.ps.256" => "__builtin_ia32_reduceps256_mask", + "llvm.x86.avx512.mask.reduce.ps.512" => "__builtin_ia32_reduceps512_mask", + "llvm.x86.avx512.mask.reduce.sd" => "__builtin_ia32_reducesd_mask", + "llvm.x86.avx512.mask.reduce.ss" => "__builtin_ia32_reducess_mask", + "llvm.x86.avx512.mask.rndscale.pd.128" => "__builtin_ia32_rndscalepd_128_mask", + "llvm.x86.avx512.mask.rndscale.pd.256" => "__builtin_ia32_rndscalepd_256_mask", "llvm.x86.avx512.mask.rndscale.pd.512" => "__builtin_ia32_rndscalepd_mask", + "llvm.x86.avx512.mask.rndscale.ps.128" => "__builtin_ia32_rndscaleps_128_mask", + "llvm.x86.avx512.mask.rndscale.ps.256" => "__builtin_ia32_rndscaleps_256_mask", "llvm.x86.avx512.mask.rndscale.ps.512" => "__builtin_ia32_rndscaleps_mask", - "llvm.x86.avx512.mask.store.ss" => "__builtin_ia32_storess_mask", - "llvm.x86.avx512.mask.storeu.d.512" => "__builtin_ia32_storedqusi512_mask", - "llvm.x86.avx512.mask.storeu.pd.512" => "__builtin_ia32_storeupd512_mask", - "llvm.x86.avx512.mask.storeu.ps.512" => "__builtin_ia32_storeups512_mask", - "llvm.x86.avx512.mask.storeu.q.512" => "__builtin_ia32_storedqudi512_mask", - "llvm.x86.avx512.mask.valign.d.512" => "__builtin_ia32_alignd512_mask", - "llvm.x86.avx512.mask.valign.q.512" => "__builtin_ia32_alignq512_mask", - "llvm.x86.avx512.mask.vcvtph2ps.512" => "__builtin_ia32_vcvtph2ps512_mask", + "llvm.x86.avx512.mask.rndscale.sd" => "__builtin_ia32_rndscalesd_round_mask", + "llvm.x86.avx512.mask.rndscale.ss" => "__builtin_ia32_rndscaless_round_mask", + "llvm.x86.avx512.mask.scalef.pd.128" => "__builtin_ia32_scalefpd128_mask", + "llvm.x86.avx512.mask.scalef.pd.256" => "__builtin_ia32_scalefpd256_mask", + "llvm.x86.avx512.mask.scalef.pd.512" => "__builtin_ia32_scalefpd512_mask", + "llvm.x86.avx512.mask.scalef.ps.128" => "__builtin_ia32_scalefps128_mask", + "llvm.x86.avx512.mask.scalef.ps.256" => "__builtin_ia32_scalefps256_mask", + "llvm.x86.avx512.mask.scalef.ps.512" => "__builtin_ia32_scalefps512_mask", + "llvm.x86.avx512.mask.scalef.sd" => "__builtin_ia32_scalefsd_round_mask", + "llvm.x86.avx512.mask.scalef.ss" => "__builtin_ia32_scalefss_round_mask", + "llvm.x86.avx512.mask.sub.sd.round" => "__builtin_ia32_subsd_round_mask", + "llvm.x86.avx512.mask.sub.ss.round" => "__builtin_ia32_subss_round_mask", + "llvm.x86.avx512.mask.vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph_mask", + "llvm.x86.avx512.mask.vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256_mask", "llvm.x86.avx512.mask.vcvtps2ph.512" => "__builtin_ia32_vcvtps2ph512_mask", - "llvm.x86.avx512.mask.vpermt.d.512" => "__builtin_ia32_vpermt2vard512_mask", - "llvm.x86.avx512.mask.vpermt.pd.512" => "__builtin_ia32_vpermt2varpd512_mask", - "llvm.x86.avx512.mask.vpermt.ps.512" => "__builtin_ia32_vpermt2varps512_mask", - "llvm.x86.avx512.mask.vpermt.q.512" => "__builtin_ia32_vpermt2varq512_mask", - "llvm.x86.avx512.movntdqa" => "__builtin_ia32_movntdqa512", - "llvm.x86.avx512.pbroadcastd.512" => "__builtin_ia32_pbroadcastd512", - "llvm.x86.avx512.pbroadcastq.512" => "__builtin_ia32_pbroadcastq512", - "llvm.x86.avx512.pmovzxbd" => "__builtin_ia32_pmovzxbd512", - "llvm.x86.avx512.pmovzxbq" => "__builtin_ia32_pmovzxbq512", - "llvm.x86.avx512.pmovzxdq" => "__builtin_ia32_pmovzxdq512", - "llvm.x86.avx512.pmovzxwd" => "__builtin_ia32_pmovzxwd512", - "llvm.x86.avx512.pmovzxwq" => "__builtin_ia32_pmovzxwq512", - "llvm.x86.avx512.psll.dq" => "__builtin_ia32_pslldqi512", - "llvm.x86.avx512.psll.dq.bs" => "__builtin_ia32_pslldqi512_byteshift", - "llvm.x86.avx512.psrl.dq" => "__builtin_ia32_psrldqi512", - "llvm.x86.avx512.psrl.dq.bs" => "__builtin_ia32_psrldqi512_byteshift", + "llvm.x86.avx512.maskz.fixupimm.pd.128" => "__builtin_ia32_fixupimmpd128_maskz", + "llvm.x86.avx512.maskz.fixupimm.pd.256" => "__builtin_ia32_fixupimmpd256_maskz", + "llvm.x86.avx512.maskz.fixupimm.pd.512" => "__builtin_ia32_fixupimmpd512_maskz", + "llvm.x86.avx512.maskz.fixupimm.ps.128" => "__builtin_ia32_fixupimmps128_maskz", + "llvm.x86.avx512.maskz.fixupimm.ps.256" => "__builtin_ia32_fixupimmps256_maskz", + "llvm.x86.avx512.maskz.fixupimm.ps.512" => "__builtin_ia32_fixupimmps512_maskz", + "llvm.x86.avx512.maskz.fixupimm.sd" => "__builtin_ia32_fixupimmsd_maskz", + "llvm.x86.avx512.maskz.fixupimm.ss" => "__builtin_ia32_fixupimmss_maskz", + "llvm.x86.avx512.max.pd.512" => "__builtin_ia32_maxpd512", + "llvm.x86.avx512.max.ps.512" => "__builtin_ia32_maxps512", + "llvm.x86.avx512.min.pd.512" => "__builtin_ia32_minpd512", + "llvm.x86.avx512.min.ps.512" => "__builtin_ia32_minps512", + "llvm.x86.avx512.mul.pd.512" => "__builtin_ia32_mulpd512", + "llvm.x86.avx512.mul.ps.512" => "__builtin_ia32_mulps512", + "llvm.x86.avx512.packssdw.512" => "__builtin_ia32_packssdw512", + "llvm.x86.avx512.packsswb.512" => "__builtin_ia32_packsswb512", + "llvm.x86.avx512.packusdw.512" => "__builtin_ia32_packusdw512", + "llvm.x86.avx512.packuswb.512" => "__builtin_ia32_packuswb512", + "llvm.x86.avx512.pavg.b.512" => "__builtin_ia32_pavgb512", + "llvm.x86.avx512.pavg.w.512" => "__builtin_ia32_pavgw512", + "llvm.x86.avx512.permvar.df.256" => "__builtin_ia32_permvardf256", + "llvm.x86.avx512.permvar.df.512" => "__builtin_ia32_permvardf512", + "llvm.x86.avx512.permvar.di.256" => "__builtin_ia32_permvardi256", + "llvm.x86.avx512.permvar.di.512" => "__builtin_ia32_permvardi512", + "llvm.x86.avx512.permvar.hi.128" => "__builtin_ia32_permvarhi128", + "llvm.x86.avx512.permvar.hi.256" => "__builtin_ia32_permvarhi256", + "llvm.x86.avx512.permvar.hi.512" => "__builtin_ia32_permvarhi512", + "llvm.x86.avx512.permvar.qi.128" => "__builtin_ia32_permvarqi128", + "llvm.x86.avx512.permvar.qi.256" => "__builtin_ia32_permvarqi256", + "llvm.x86.avx512.permvar.qi.512" => "__builtin_ia32_permvarqi512", + "llvm.x86.avx512.permvar.sf.512" => "__builtin_ia32_permvarsf512", + "llvm.x86.avx512.permvar.si.512" => "__builtin_ia32_permvarsi512", + "llvm.x86.avx512.pmaddubs.w.512" => "__builtin_ia32_pmaddubsw512", + "llvm.x86.avx512.pmaddw.d.512" => "__builtin_ia32_pmaddwd512", + "llvm.x86.avx512.pmul.hr.sw.512" => "__builtin_ia32_pmulhrsw512", + "llvm.x86.avx512.pmulh.w.512" => "__builtin_ia32_pmulhw512", + "llvm.x86.avx512.pmulhu.w.512" => "__builtin_ia32_pmulhuw512", + "llvm.x86.avx512.pmultishift.qb.128" => "__builtin_ia32_vpmultishiftqb128", + "llvm.x86.avx512.pmultishift.qb.256" => "__builtin_ia32_vpmultishiftqb256", + "llvm.x86.avx512.pmultishift.qb.512" => "__builtin_ia32_vpmultishiftqb512", + "llvm.x86.avx512.psad.bw.512" => "__builtin_ia32_psadbw512", + "llvm.x86.avx512.pshuf.b.512" => "__builtin_ia32_pshufb512", + "llvm.x86.avx512.psll.d.512" => "__builtin_ia32_pslld512", + "llvm.x86.avx512.psll.q.512" => "__builtin_ia32_psllq512", + "llvm.x86.avx512.psll.w.512" => "__builtin_ia32_psllw512", + "llvm.x86.avx512.pslli.d.512" => "__builtin_ia32_pslldi512", + "llvm.x86.avx512.pslli.q.512" => "__builtin_ia32_psllqi512", + "llvm.x86.avx512.pslli.w.512" => "__builtin_ia32_psllwi512", + "llvm.x86.avx512.psllv.d.512" => "__builtin_ia32_psllv16si", + "llvm.x86.avx512.psllv.q.512" => "__builtin_ia32_psllv8di", + "llvm.x86.avx512.psllv.w.128" => "__builtin_ia32_psllv8hi", + "llvm.x86.avx512.psllv.w.256" => "__builtin_ia32_psllv16hi", + "llvm.x86.avx512.psllv.w.512" => "__builtin_ia32_psllv32hi", + "llvm.x86.avx512.psra.d.512" => "__builtin_ia32_psrad512", + "llvm.x86.avx512.psra.q.128" => "__builtin_ia32_psraq128", + "llvm.x86.avx512.psra.q.256" => "__builtin_ia32_psraq256", + "llvm.x86.avx512.psra.q.512" => "__builtin_ia32_psraq512", + "llvm.x86.avx512.psra.w.512" => "__builtin_ia32_psraw512", + "llvm.x86.avx512.psrai.d.512" => "__builtin_ia32_psradi512", + "llvm.x86.avx512.psrai.q.128" => "__builtin_ia32_psraqi128", + "llvm.x86.avx512.psrai.q.256" => "__builtin_ia32_psraqi256", + "llvm.x86.avx512.psrai.q.512" => "__builtin_ia32_psraqi512", + "llvm.x86.avx512.psrai.w.512" => "__builtin_ia32_psrawi512", + "llvm.x86.avx512.psrav.d.512" => "__builtin_ia32_psrav16si", + "llvm.x86.avx512.psrav.q.128" => "__builtin_ia32_psravq128", + "llvm.x86.avx512.psrav.q.256" => "__builtin_ia32_psravq256", + "llvm.x86.avx512.psrav.q.512" => "__builtin_ia32_psrav8di", + "llvm.x86.avx512.psrav.w.128" => "__builtin_ia32_psrav8hi", + "llvm.x86.avx512.psrav.w.256" => "__builtin_ia32_psrav16hi", + "llvm.x86.avx512.psrav.w.512" => "__builtin_ia32_psrav32hi", + "llvm.x86.avx512.psrl.d.512" => "__builtin_ia32_psrld512", + "llvm.x86.avx512.psrl.q.512" => "__builtin_ia32_psrlq512", + "llvm.x86.avx512.psrl.w.512" => "__builtin_ia32_psrlw512", + "llvm.x86.avx512.psrli.d.512" => "__builtin_ia32_psrldi512", + "llvm.x86.avx512.psrli.q.512" => "__builtin_ia32_psrlqi512", + "llvm.x86.avx512.psrli.w.512" => "__builtin_ia32_psrlwi512", + "llvm.x86.avx512.psrlv.d.512" => "__builtin_ia32_psrlv16si", + "llvm.x86.avx512.psrlv.q.512" => "__builtin_ia32_psrlv8di", + "llvm.x86.avx512.psrlv.w.128" => "__builtin_ia32_psrlv8hi", + "llvm.x86.avx512.psrlv.w.256" => "__builtin_ia32_psrlv16hi", + "llvm.x86.avx512.psrlv.w.512" => "__builtin_ia32_psrlv32hi", + "llvm.x86.avx512.pternlog.d.128" => "__builtin_ia32_pternlogd128", + "llvm.x86.avx512.pternlog.d.256" => "__builtin_ia32_pternlogd256", + "llvm.x86.avx512.pternlog.d.512" => "__builtin_ia32_pternlogd512", + "llvm.x86.avx512.pternlog.q.128" => "__builtin_ia32_pternlogq128", + "llvm.x86.avx512.pternlog.q.256" => "__builtin_ia32_pternlogq256", + "llvm.x86.avx512.pternlog.q.512" => "__builtin_ia32_pternlogq512", + "llvm.x86.avx512.rcp14.pd.128" => "__builtin_ia32_rcp14pd128_mask", + "llvm.x86.avx512.rcp14.pd.256" => "__builtin_ia32_rcp14pd256_mask", "llvm.x86.avx512.rcp14.pd.512" => "__builtin_ia32_rcp14pd512_mask", + "llvm.x86.avx512.rcp14.ps.128" => "__builtin_ia32_rcp14ps128_mask", + "llvm.x86.avx512.rcp14.ps.256" => "__builtin_ia32_rcp14ps256_mask", "llvm.x86.avx512.rcp14.ps.512" => "__builtin_ia32_rcp14ps512_mask", "llvm.x86.avx512.rcp14.sd" => "__builtin_ia32_rcp14sd_mask", "llvm.x86.avx512.rcp14.ss" => "__builtin_ia32_rcp14ss_mask", "llvm.x86.avx512.rcp28.pd" => "__builtin_ia32_rcp28pd_mask", "llvm.x86.avx512.rcp28.ps" => "__builtin_ia32_rcp28ps_mask", - "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_mask", - "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_mask", - "llvm.x86.avx512.rndscale.sd" => "__builtin_ia32_rndscalesd", - "llvm.x86.avx512.rndscale.ss" => "__builtin_ia32_rndscaless", + "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_round_mask", + "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_round_mask", + "llvm.x86.avx512.rsqrt14.pd.128" => "__builtin_ia32_rsqrt14pd128_mask", + "llvm.x86.avx512.rsqrt14.pd.256" => "__builtin_ia32_rsqrt14pd256_mask", "llvm.x86.avx512.rsqrt14.pd.512" => "__builtin_ia32_rsqrt14pd512_mask", + "llvm.x86.avx512.rsqrt14.ps.128" => "__builtin_ia32_rsqrt14ps128_mask", + "llvm.x86.avx512.rsqrt14.ps.256" => "__builtin_ia32_rsqrt14ps256_mask", "llvm.x86.avx512.rsqrt14.ps.512" => "__builtin_ia32_rsqrt14ps512_mask", "llvm.x86.avx512.rsqrt14.sd" => "__builtin_ia32_rsqrt14sd_mask", "llvm.x86.avx512.rsqrt14.ss" => "__builtin_ia32_rsqrt14ss_mask", "llvm.x86.avx512.rsqrt28.pd" => "__builtin_ia32_rsqrt28pd_mask", "llvm.x86.avx512.rsqrt28.ps" => "__builtin_ia32_rsqrt28ps_mask", - "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_mask", - "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_mask", - "llvm.x86.avx512.scatter.dpd.512" => "__builtin_ia32_scattersiv8df", - "llvm.x86.avx512.scatter.dpi.512" => "__builtin_ia32_scattersiv16si", - "llvm.x86.avx512.scatter.dpq.512" => "__builtin_ia32_scattersiv8di", - "llvm.x86.avx512.scatter.dps.512" => "__builtin_ia32_scattersiv16sf", - "llvm.x86.avx512.scatter.qpd.512" => "__builtin_ia32_scatterdiv8df", - "llvm.x86.avx512.scatter.qpi.512" => "__builtin_ia32_scatterdiv16si", - "llvm.x86.avx512.scatter.qpq.512" => "__builtin_ia32_scatterdiv8di", - "llvm.x86.avx512.scatter.qps.512" => "__builtin_ia32_scatterdiv16sf", + "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_round_mask", + "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_round_mask", "llvm.x86.avx512.scatterpf.dpd.512" => "__builtin_ia32_scatterpfdpd", "llvm.x86.avx512.scatterpf.dps.512" => "__builtin_ia32_scatterpfdps", "llvm.x86.avx512.scatterpf.qpd.512" => "__builtin_ia32_scatterpfqpd", "llvm.x86.avx512.scatterpf.qps.512" => "__builtin_ia32_scatterpfqps", - "llvm.x86.avx512.sqrt.pd.512" => "__builtin_ia32_sqrtpd512_mask", - "llvm.x86.avx512.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask", - "llvm.x86.avx512.sqrt.sd" => "__builtin_ia32_sqrtrndsd", - "llvm.x86.avx512.sqrt.ss" => "__builtin_ia32_sqrtrndss", - "llvm.x86.avx512.vbroadcast.sd.512" => "__builtin_ia32_vbroadcastsd512", - "llvm.x86.avx512.vbroadcast.sd.pd.512" => "__builtin_ia32_vbroadcastsd_pd512", - "llvm.x86.avx512.vbroadcast.ss.512" => "__builtin_ia32_vbroadcastss512", - "llvm.x86.avx512.vbroadcast.ss.ps.512" => "__builtin_ia32_vbroadcastss_ps512", + "llvm.x86.avx512.sub.pd.512" => "__builtin_ia32_subpd512", + "llvm.x86.avx512.sub.ps.512" => "__builtin_ia32_subps512", + "llvm.x86.avx512.vcomi.sd" => "__builtin_ia32_vcomisd", + "llvm.x86.avx512.vcomi.ss" => "__builtin_ia32_vcomiss", + "llvm.x86.avx512.vcvtsd2si32" => "__builtin_ia32_vcvtsd2si32", + "llvm.x86.avx512.vcvtsd2si64" => "__builtin_ia32_vcvtsd2si64", + "llvm.x86.avx512.vcvtsd2usi32" => "__builtin_ia32_vcvtsd2usi32", + "llvm.x86.avx512.vcvtsd2usi64" => "__builtin_ia32_vcvtsd2usi64", + "llvm.x86.avx512.vcvtss2si32" => "__builtin_ia32_vcvtss2si32", + "llvm.x86.avx512.vcvtss2si64" => "__builtin_ia32_vcvtss2si64", + "llvm.x86.avx512.vcvtss2usi32" => "__builtin_ia32_vcvtss2usi32", + "llvm.x86.avx512.vcvtss2usi64" => "__builtin_ia32_vcvtss2usi64", + "llvm.x86.avx512.vpdpbusd.128" => "__builtin_ia32_vpdpbusd128", + "llvm.x86.avx512.vpdpbusd.256" => "__builtin_ia32_vpdpbusd256", + "llvm.x86.avx512.vpdpbusd.512" => "__builtin_ia32_vpdpbusd512", + "llvm.x86.avx512.vpdpbusds.128" => "__builtin_ia32_vpdpbusds128", + "llvm.x86.avx512.vpdpbusds.256" => "__builtin_ia32_vpdpbusds256", + "llvm.x86.avx512.vpdpbusds.512" => "__builtin_ia32_vpdpbusds512", + "llvm.x86.avx512.vpdpwssd.128" => "__builtin_ia32_vpdpwssd128", + "llvm.x86.avx512.vpdpwssd.256" => "__builtin_ia32_vpdpwssd256", + "llvm.x86.avx512.vpdpwssd.512" => "__builtin_ia32_vpdpwssd512", + "llvm.x86.avx512.vpdpwssds.128" => "__builtin_ia32_vpdpwssds128", + "llvm.x86.avx512.vpdpwssds.256" => "__builtin_ia32_vpdpwssds256", + "llvm.x86.avx512.vpdpwssds.512" => "__builtin_ia32_vpdpwssds512", + "llvm.x86.avx512.vpermi2var.d.128" => "__builtin_ia32_vpermi2vard128", + "llvm.x86.avx512.vpermi2var.d.256" => "__builtin_ia32_vpermi2vard256", + "llvm.x86.avx512.vpermi2var.d.512" => "__builtin_ia32_vpermi2vard512", + "llvm.x86.avx512.vpermi2var.hi.128" => "__builtin_ia32_vpermi2varhi128", + "llvm.x86.avx512.vpermi2var.hi.256" => "__builtin_ia32_vpermi2varhi256", + "llvm.x86.avx512.vpermi2var.hi.512" => "__builtin_ia32_vpermi2varhi512", + "llvm.x86.avx512.vpermi2var.pd.128" => "__builtin_ia32_vpermi2varpd128", + "llvm.x86.avx512.vpermi2var.pd.256" => "__builtin_ia32_vpermi2varpd256", + "llvm.x86.avx512.vpermi2var.pd.512" => "__builtin_ia32_vpermi2varpd512", + "llvm.x86.avx512.vpermi2var.ps.128" => "__builtin_ia32_vpermi2varps128", + "llvm.x86.avx512.vpermi2var.ps.256" => "__builtin_ia32_vpermi2varps256", + "llvm.x86.avx512.vpermi2var.ps.512" => "__builtin_ia32_vpermi2varps512", + "llvm.x86.avx512.vpermi2var.q.128" => "__builtin_ia32_vpermi2varq128", + "llvm.x86.avx512.vpermi2var.q.256" => "__builtin_ia32_vpermi2varq256", + "llvm.x86.avx512.vpermi2var.q.512" => "__builtin_ia32_vpermi2varq512", + "llvm.x86.avx512.vpermi2var.qi.128" => "__builtin_ia32_vpermi2varqi128", + "llvm.x86.avx512.vpermi2var.qi.256" => "__builtin_ia32_vpermi2varqi256", + "llvm.x86.avx512.vpermi2var.qi.512" => "__builtin_ia32_vpermi2varqi512", + "llvm.x86.avx512.vpermilvar.pd.512" => "__builtin_ia32_vpermilvarpd512", + "llvm.x86.avx512.vpermilvar.ps.512" => "__builtin_ia32_vpermilvarps512", + "llvm.x86.avx512.vpmadd52h.uq.128" => "__builtin_ia32_vpmadd52huq128", + "llvm.x86.avx512.vpmadd52h.uq.256" => "__builtin_ia32_vpmadd52huq256", + "llvm.x86.avx512.vpmadd52h.uq.512" => "__builtin_ia32_vpmadd52huq512", + "llvm.x86.avx512.vpmadd52l.uq.128" => "__builtin_ia32_vpmadd52luq128", + "llvm.x86.avx512.vpmadd52l.uq.256" => "__builtin_ia32_vpmadd52luq256", + "llvm.x86.avx512.vpmadd52l.uq.512" => "__builtin_ia32_vpmadd52luq512", + "llvm.x86.avx512bf16.cvtne2ps2bf16.128" => "__builtin_ia32_cvtne2ps2bf16_128", + "llvm.x86.avx512bf16.cvtne2ps2bf16.256" => "__builtin_ia32_cvtne2ps2bf16_256", + "llvm.x86.avx512bf16.cvtne2ps2bf16.512" => "__builtin_ia32_cvtne2ps2bf16_512", + "llvm.x86.avx512bf16.cvtneps2bf16.256" => "__builtin_ia32_cvtneps2bf16_256", + "llvm.x86.avx512bf16.cvtneps2bf16.512" => "__builtin_ia32_cvtneps2bf16_512", + "llvm.x86.avx512bf16.dpbf16ps.128" => "__builtin_ia32_dpbf16ps_128", + "llvm.x86.avx512bf16.dpbf16ps.256" => "__builtin_ia32_dpbf16ps_256", + "llvm.x86.avx512bf16.dpbf16ps.512" => "__builtin_ia32_dpbf16ps_512", + "llvm.x86.avx512fp16.add.ph.512" => "__builtin_ia32_addph512", + "llvm.x86.avx512fp16.div.ph.512" => "__builtin_ia32_divph512", + "llvm.x86.avx512fp16.mask.add.sh.round" => "__builtin_ia32_addsh_round_mask", + "llvm.x86.avx512fp16.mask.cmp.sh" => "__builtin_ia32_cmpsh_mask", + "llvm.x86.avx512fp16.mask.div.sh.round" => "__builtin_ia32_divsh_round_mask", + "llvm.x86.avx512fp16.mask.fpclass.sh" => "__builtin_ia32_fpclasssh_mask", + "llvm.x86.avx512fp16.mask.getexp.ph.128" => "__builtin_ia32_getexpph128_mask", + "llvm.x86.avx512fp16.mask.getexp.ph.256" => "__builtin_ia32_getexpph256_mask", + "llvm.x86.avx512fp16.mask.getexp.ph.512" => "__builtin_ia32_getexpph512_mask", + "llvm.x86.avx512fp16.mask.getexp.sh" => "__builtin_ia32_getexpsh128_round_mask", + "llvm.x86.avx512fp16.mask.getmant.ph.128" => "__builtin_ia32_getmantph128_mask", + "llvm.x86.avx512fp16.mask.getmant.ph.256" => "__builtin_ia32_getmantph256_mask", + "llvm.x86.avx512fp16.mask.getmant.ph.512" => "__builtin_ia32_getmantph512_mask", + "llvm.x86.avx512fp16.mask.getmant.sh" => "__builtin_ia32_getmantsh_round_mask", + "llvm.x86.avx512fp16.mask.max.sh.round" => "__builtin_ia32_maxsh_round_mask", + "llvm.x86.avx512fp16.mask.min.sh.round" => "__builtin_ia32_minsh_round_mask", + "llvm.x86.avx512fp16.mask.mul.sh.round" => "__builtin_ia32_mulsh_round_mask", + "llvm.x86.avx512fp16.mask.rcp.ph.128" => "__builtin_ia32_rcpph128_mask", + "llvm.x86.avx512fp16.mask.rcp.ph.256" => "__builtin_ia32_rcpph256_mask", + "llvm.x86.avx512fp16.mask.rcp.ph.512" => "__builtin_ia32_rcpph512_mask", + "llvm.x86.avx512fp16.mask.rcp.sh" => "__builtin_ia32_rcpsh_mask", + "llvm.x86.avx512fp16.mask.reduce.ph.128" => "__builtin_ia32_reduceph128_mask", + "llvm.x86.avx512fp16.mask.reduce.ph.256" => "__builtin_ia32_reduceph256_mask", + "llvm.x86.avx512fp16.mask.reduce.ph.512" => "__builtin_ia32_reduceph512_mask", + "llvm.x86.avx512fp16.mask.reduce.sh" => "__builtin_ia32_reducesh_mask", + "llvm.x86.avx512fp16.mask.rndscale.ph.128" => "__builtin_ia32_rndscaleph_128_mask", + "llvm.x86.avx512fp16.mask.rndscale.ph.256" => "__builtin_ia32_rndscaleph_256_mask", + "llvm.x86.avx512fp16.mask.rndscale.ph.512" => "__builtin_ia32_rndscaleph_mask", + "llvm.x86.avx512fp16.mask.rndscale.sh" => "__builtin_ia32_rndscalesh_round_mask", + "llvm.x86.avx512fp16.mask.rsqrt.ph.128" => "__builtin_ia32_rsqrtph128_mask", + "llvm.x86.avx512fp16.mask.rsqrt.ph.256" => "__builtin_ia32_rsqrtph256_mask", + "llvm.x86.avx512fp16.mask.rsqrt.ph.512" => "__builtin_ia32_rsqrtph512_mask", + "llvm.x86.avx512fp16.mask.rsqrt.sh" => "__builtin_ia32_rsqrtsh_mask", + "llvm.x86.avx512fp16.mask.scalef.ph.128" => "__builtin_ia32_scalefph128_mask", + "llvm.x86.avx512fp16.mask.scalef.ph.256" => "__builtin_ia32_scalefph256_mask", + "llvm.x86.avx512fp16.mask.scalef.ph.512" => "__builtin_ia32_scalefph512_mask", + "llvm.x86.avx512fp16.mask.scalef.sh" => "__builtin_ia32_scalefsh_round_mask", + "llvm.x86.avx512fp16.mask.sub.sh.round" => "__builtin_ia32_subsh_round_mask", + "llvm.x86.avx512fp16.mask.vcvtdq2ph.128" => "__builtin_ia32_vcvtdq2ph128_mask", + "llvm.x86.avx512fp16.mask.vcvtpd2ph.128" => "__builtin_ia32_vcvtpd2ph128_mask", + "llvm.x86.avx512fp16.mask.vcvtpd2ph.256" => "__builtin_ia32_vcvtpd2ph256_mask", + "llvm.x86.avx512fp16.mask.vcvtpd2ph.512" => "__builtin_ia32_vcvtpd2ph512_mask", + "llvm.x86.avx512fp16.mask.vcvtph2dq.128" => "__builtin_ia32_vcvtph2dq128_mask", + "llvm.x86.avx512fp16.mask.vcvtph2dq.256" => "__builtin_ia32_vcvtph2dq256_mask", + "llvm.x86.avx512fp16.mask.vcvtph2dq.512" => "__builtin_ia32_vcvtph2dq512_mask", + "llvm.x86.avx512fp16.mask.vcvtph2pd.128" => "__builtin_ia32_vcvtph2pd128_mask", + "llvm.x86.avx512fp16.mask.vcvtph2pd.256" => "__builtin_ia32_vcvtph2pd256_mask", + "llvm.x86.avx512fp16.mask.vcvtph2pd.512" => "__builtin_ia32_vcvtph2pd512_mask", + "llvm.x86.avx512fp16.mask.vcvtph2psx.128" => "__builtin_ia32_vcvtph2psx128_mask", + "llvm.x86.avx512fp16.mask.vcvtph2psx.256" => "__builtin_ia32_vcvtph2psx256_mask", + "llvm.x86.avx512fp16.mask.vcvtph2psx.512" => "__builtin_ia32_vcvtph2psx512_mask", + "llvm.x86.avx512fp16.mask.vcvtph2qq.128" => "__builtin_ia32_vcvtph2qq128_mask", + "llvm.x86.avx512fp16.mask.vcvtph2qq.256" => "__builtin_ia32_vcvtph2qq256_mask", + "llvm.x86.avx512fp16.mask.vcvtph2qq.512" => "__builtin_ia32_vcvtph2qq512_mask", + "llvm.x86.avx512fp16.mask.vcvtph2udq.128" => "__builtin_ia32_vcvtph2udq128_mask", + "llvm.x86.avx512fp16.mask.vcvtph2udq.256" => "__builtin_ia32_vcvtph2udq256_mask", + "llvm.x86.avx512fp16.mask.vcvtph2udq.512" => "__builtin_ia32_vcvtph2udq512_mask", + "llvm.x86.avx512fp16.mask.vcvtph2uqq.128" => "__builtin_ia32_vcvtph2uqq128_mask", + "llvm.x86.avx512fp16.mask.vcvtph2uqq.256" => "__builtin_ia32_vcvtph2uqq256_mask", + "llvm.x86.avx512fp16.mask.vcvtph2uqq.512" => "__builtin_ia32_vcvtph2uqq512_mask", + "llvm.x86.avx512fp16.mask.vcvtph2uw.128" => "__builtin_ia32_vcvtph2uw128_mask", + "llvm.x86.avx512fp16.mask.vcvtph2uw.256" => "__builtin_ia32_vcvtph2uw256_mask", + "llvm.x86.avx512fp16.mask.vcvtph2uw.512" => "__builtin_ia32_vcvtph2uw512_mask", + "llvm.x86.avx512fp16.mask.vcvtph2w.128" => "__builtin_ia32_vcvtph2w128_mask", + "llvm.x86.avx512fp16.mask.vcvtph2w.256" => "__builtin_ia32_vcvtph2w256_mask", + "llvm.x86.avx512fp16.mask.vcvtph2w.512" => "__builtin_ia32_vcvtph2w512_mask", + "llvm.x86.avx512fp16.mask.vcvtps2phx.128" => "__builtin_ia32_vcvtps2phx128_mask", + "llvm.x86.avx512fp16.mask.vcvtps2phx.256" => "__builtin_ia32_vcvtps2phx256_mask", + "llvm.x86.avx512fp16.mask.vcvtps2phx.512" => "__builtin_ia32_vcvtps2phx512_mask", + "llvm.x86.avx512fp16.mask.vcvtqq2ph.128" => "__builtin_ia32_vcvtqq2ph128_mask", + "llvm.x86.avx512fp16.mask.vcvtqq2ph.256" => "__builtin_ia32_vcvtqq2ph256_mask", + "llvm.x86.avx512fp16.mask.vcvtsd2sh.round" => "__builtin_ia32_vcvtsd2sh_round_mask", + "llvm.x86.avx512fp16.mask.vcvtsh2sd.round" => "__builtin_ia32_vcvtsh2sd_round_mask", + "llvm.x86.avx512fp16.mask.vcvtsh2ss.round" => "__builtin_ia32_vcvtsh2ss_round_mask", + "llvm.x86.avx512fp16.mask.vcvtss2sh.round" => "__builtin_ia32_vcvtss2sh_round_mask", + "llvm.x86.avx512fp16.mask.vcvttph2dq.128" => "__builtin_ia32_vcvttph2dq128_mask", + "llvm.x86.avx512fp16.mask.vcvttph2dq.256" => "__builtin_ia32_vcvttph2dq256_mask", + "llvm.x86.avx512fp16.mask.vcvttph2dq.512" => "__builtin_ia32_vcvttph2dq512_mask", + "llvm.x86.avx512fp16.mask.vcvttph2qq.128" => "__builtin_ia32_vcvttph2qq128_mask", + "llvm.x86.avx512fp16.mask.vcvttph2qq.256" => "__builtin_ia32_vcvttph2qq256_mask", + "llvm.x86.avx512fp16.mask.vcvttph2qq.512" => "__builtin_ia32_vcvttph2qq512_mask", + "llvm.x86.avx512fp16.mask.vcvttph2udq.128" => "__builtin_ia32_vcvttph2udq128_mask", + "llvm.x86.avx512fp16.mask.vcvttph2udq.256" => "__builtin_ia32_vcvttph2udq256_mask", + "llvm.x86.avx512fp16.mask.vcvttph2udq.512" => "__builtin_ia32_vcvttph2udq512_mask", + "llvm.x86.avx512fp16.mask.vcvttph2uqq.128" => "__builtin_ia32_vcvttph2uqq128_mask", + "llvm.x86.avx512fp16.mask.vcvttph2uqq.256" => "__builtin_ia32_vcvttph2uqq256_mask", + "llvm.x86.avx512fp16.mask.vcvttph2uqq.512" => "__builtin_ia32_vcvttph2uqq512_mask", + "llvm.x86.avx512fp16.mask.vcvttph2uw.128" => "__builtin_ia32_vcvttph2uw128_mask", + "llvm.x86.avx512fp16.mask.vcvttph2uw.256" => "__builtin_ia32_vcvttph2uw256_mask", + "llvm.x86.avx512fp16.mask.vcvttph2uw.512" => "__builtin_ia32_vcvttph2uw512_mask", + "llvm.x86.avx512fp16.mask.vcvttph2w.128" => "__builtin_ia32_vcvttph2w128_mask", + "llvm.x86.avx512fp16.mask.vcvttph2w.256" => "__builtin_ia32_vcvttph2w256_mask", + "llvm.x86.avx512fp16.mask.vcvttph2w.512" => "__builtin_ia32_vcvttph2w512_mask", + "llvm.x86.avx512fp16.mask.vcvtudq2ph.128" => "__builtin_ia32_vcvtudq2ph128_mask", + "llvm.x86.avx512fp16.mask.vcvtuqq2ph.128" => "__builtin_ia32_vcvtuqq2ph128_mask", + "llvm.x86.avx512fp16.mask.vcvtuqq2ph.256" => "__builtin_ia32_vcvtuqq2ph256_mask", + "llvm.x86.avx512fp16.mask.vfcmadd.cph.128" => "__builtin_ia32_vfcmaddcph128_mask", + "llvm.x86.avx512fp16.mask.vfcmadd.cph.256" => "__builtin_ia32_vfcmaddcph256_mask", + "llvm.x86.avx512fp16.mask.vfcmadd.cph.512" => "__builtin_ia32_vfcmaddcph512_mask3", + "llvm.x86.avx512fp16.mask.vfcmadd.csh" => "__builtin_ia32_vfcmaddcsh_mask", + "llvm.x86.avx512fp16.mask.vfcmul.cph.128" => "__builtin_ia32_vfcmulcph128_mask", + "llvm.x86.avx512fp16.mask.vfcmul.cph.256" => "__builtin_ia32_vfcmulcph256_mask", + "llvm.x86.avx512fp16.mask.vfcmul.cph.512" => "__builtin_ia32_vfcmulcph512_mask", + "llvm.x86.avx512fp16.mask.vfcmul.csh" => "__builtin_ia32_vfcmulcsh_mask", + "llvm.x86.avx512fp16.mask.vfmadd.cph.128" => "__builtin_ia32_vfmaddcph128_mask", + "llvm.x86.avx512fp16.mask.vfmadd.cph.256" => "__builtin_ia32_vfmaddcph256_mask", + "llvm.x86.avx512fp16.mask.vfmadd.cph.512" => "__builtin_ia32_vfmaddcph512_mask3", + "llvm.x86.avx512fp16.mask.vfmadd.csh" => "__builtin_ia32_vfmaddcsh_mask", + "llvm.x86.avx512fp16.mask.vfmul.cph.128" => "__builtin_ia32_vfmulcph128_mask", + "llvm.x86.avx512fp16.mask.vfmul.cph.256" => "__builtin_ia32_vfmulcph256_mask", + "llvm.x86.avx512fp16.mask.vfmul.cph.512" => "__builtin_ia32_vfmulcph512_mask", + "llvm.x86.avx512fp16.mask.vfmul.csh" => "__builtin_ia32_vfmulcsh_mask", + "llvm.x86.avx512fp16.maskz.vfcmadd.cph.128" => "__builtin_ia32_vfcmaddcph128_maskz", + "llvm.x86.avx512fp16.maskz.vfcmadd.cph.256" => "__builtin_ia32_vfcmaddcph256_maskz", + "llvm.x86.avx512fp16.maskz.vfcmadd.cph.512" => "__builtin_ia32_vfcmaddcph512_maskz", + "llvm.x86.avx512fp16.maskz.vfcmadd.csh" => "__builtin_ia32_vfcmaddcsh_maskz", + "llvm.x86.avx512fp16.maskz.vfmadd.cph.128" => "__builtin_ia32_vfmaddcph128_maskz", + "llvm.x86.avx512fp16.maskz.vfmadd.cph.256" => "__builtin_ia32_vfmaddcph256_maskz", + "llvm.x86.avx512fp16.maskz.vfmadd.cph.512" => "__builtin_ia32_vfmaddcph512_maskz", + "llvm.x86.avx512fp16.maskz.vfmadd.csh" => "__builtin_ia32_vfmaddcsh_maskz", + "llvm.x86.avx512fp16.max.ph.128" => "__builtin_ia32_maxph128", + "llvm.x86.avx512fp16.max.ph.256" => "__builtin_ia32_maxph256", + "llvm.x86.avx512fp16.max.ph.512" => "__builtin_ia32_maxph512", + "llvm.x86.avx512fp16.min.ph.128" => "__builtin_ia32_minph128", + "llvm.x86.avx512fp16.min.ph.256" => "__builtin_ia32_minph256", + "llvm.x86.avx512fp16.min.ph.512" => "__builtin_ia32_minph512", + "llvm.x86.avx512fp16.mul.ph.512" => "__builtin_ia32_mulph512", + "llvm.x86.avx512fp16.sub.ph.512" => "__builtin_ia32_subph512", + "llvm.x86.avx512fp16.vcomi.sh" => "__builtin_ia32_vcomish", + "llvm.x86.avx512fp16.vcvtsh2si32" => "__builtin_ia32_vcvtsh2si32", + "llvm.x86.avx512fp16.vcvtsh2si64" => "__builtin_ia32_vcvtsh2si64", + "llvm.x86.avx512fp16.vcvtsh2usi32" => "__builtin_ia32_vcvtsh2usi32", + "llvm.x86.avx512fp16.vcvtsh2usi64" => "__builtin_ia32_vcvtsh2usi64", + "llvm.x86.avx512fp16.vcvtsi2sh" => "__builtin_ia32_vcvtsi2sh", + "llvm.x86.avx512fp16.vcvtsi642sh" => "__builtin_ia32_vcvtsi642sh", + "llvm.x86.avx512fp16.vcvttsh2si32" => "__builtin_ia32_vcvttsh2si32", + "llvm.x86.avx512fp16.vcvttsh2si64" => "__builtin_ia32_vcvttsh2si64", + "llvm.x86.avx512fp16.vcvttsh2usi32" => "__builtin_ia32_vcvttsh2usi32", + "llvm.x86.avx512fp16.vcvttsh2usi64" => "__builtin_ia32_vcvttsh2usi64", + "llvm.x86.avx512fp16.vcvtusi2sh" => "__builtin_ia32_vcvtusi2sh", + "llvm.x86.avx512fp16.vcvtusi642sh" => "__builtin_ia32_vcvtusi642sh", + "llvm.x86.avx512fp16.vfmaddsub.ph.128" => "__builtin_ia32_vfmaddsubph", + "llvm.x86.avx512fp16.vfmaddsub.ph.256" => "__builtin_ia32_vfmaddsubph256", "llvm.x86.bmi.bextr.32" => "__builtin_ia32_bextr_u32", "llvm.x86.bmi.bextr.64" => "__builtin_ia32_bextr_u64", "llvm.x86.bmi.bzhi.32" => "__builtin_ia32_bzhi_si", @@ -2593,60 +2013,132 @@ match name { "llvm.x86.bmi.pdep.64" => "__builtin_ia32_pdep_di", "llvm.x86.bmi.pext.32" => "__builtin_ia32_pext_si", "llvm.x86.bmi.pext.64" => "__builtin_ia32_pext_di", - "llvm.x86.fma.mask.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask", - "llvm.x86.fma.mask.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask", - "llvm.x86.fma.mask.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask", - "llvm.x86.fma.mask.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask", - "llvm.x86.fma.mask.vfmsub.pd.512" => "__builtin_ia32_vfmsubpd512_mask", - "llvm.x86.fma.mask.vfmsub.ps.512" => "__builtin_ia32_vfmsubps512_mask", - "llvm.x86.fma.mask.vfmsubadd.pd.512" => "__builtin_ia32_vfmsubaddpd512_mask", - "llvm.x86.fma.mask.vfmsubadd.ps.512" => "__builtin_ia32_vfmsubaddps512_mask", - "llvm.x86.fma.mask.vfnmadd.pd.512" => "__builtin_ia32_vfnmaddpd512_mask", - "llvm.x86.fma.mask.vfnmadd.ps.512" => "__builtin_ia32_vfnmaddps512_mask", - "llvm.x86.fma.mask.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask", - "llvm.x86.fma.mask.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask", - "llvm.x86.fma.vfmadd.pd" => "__builtin_ia32_vfmaddpd", - "llvm.x86.fma.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256", - "llvm.x86.fma.vfmadd.ps" => "__builtin_ia32_vfmaddps", - "llvm.x86.fma.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256", - "llvm.x86.fma.vfmadd.sd" => "__builtin_ia32_vfmaddsd", - "llvm.x86.fma.vfmadd.ss" => "__builtin_ia32_vfmaddss", + "llvm.x86.cldemote" => "__builtin_ia32_cldemote", + "llvm.x86.clflushopt" => "__builtin_ia32_clflushopt", + "llvm.x86.clrssbsy" => "__builtin_ia32_clrssbsy", + "llvm.x86.clui" => "__builtin_ia32_clui", + "llvm.x86.clwb" => "__builtin_ia32_clwb", + "llvm.x86.clzero" => "__builtin_ia32_clzero", + "llvm.x86.directstore32" => "__builtin_ia32_directstore_u32", + "llvm.x86.directstore64" => "__builtin_ia32_directstore_u64", + "llvm.x86.enqcmd" => "__builtin_ia32_enqcmd", + "llvm.x86.enqcmds" => "__builtin_ia32_enqcmds", + "llvm.x86.flags.read.u32" => "__builtin_ia32_readeflags_u32", + "llvm.x86.flags.read.u64" => "__builtin_ia32_readeflags_u64", + "llvm.x86.flags.write.u32" => "__builtin_ia32_writeeflags_u32", + "llvm.x86.flags.write.u64" => "__builtin_ia32_writeeflags_u64", "llvm.x86.fma.vfmaddsub.pd" => "__builtin_ia32_vfmaddsubpd", "llvm.x86.fma.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256", "llvm.x86.fma.vfmaddsub.ps" => "__builtin_ia32_vfmaddsubps", "llvm.x86.fma.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256", - "llvm.x86.fma.vfmsub.pd" => "__builtin_ia32_vfmsubpd", - "llvm.x86.fma.vfmsub.pd.256" => "__builtin_ia32_vfmsubpd256", - "llvm.x86.fma.vfmsub.ps" => "__builtin_ia32_vfmsubps", - "llvm.x86.fma.vfmsub.ps.256" => "__builtin_ia32_vfmsubps256", - "llvm.x86.fma.vfmsub.sd" => "__builtin_ia32_vfmsubsd", - "llvm.x86.fma.vfmsub.ss" => "__builtin_ia32_vfmsubss", - "llvm.x86.fma.vfmsubadd.pd" => "__builtin_ia32_vfmsubaddpd", - "llvm.x86.fma.vfmsubadd.pd.256" => "__builtin_ia32_vfmsubaddpd256", - "llvm.x86.fma.vfmsubadd.ps" => "__builtin_ia32_vfmsubaddps", - "llvm.x86.fma.vfmsubadd.ps.256" => "__builtin_ia32_vfmsubaddps256", - "llvm.x86.fma.vfnmadd.pd" => "__builtin_ia32_vfnmaddpd", - "llvm.x86.fma.vfnmadd.pd.256" => "__builtin_ia32_vfnmaddpd256", - "llvm.x86.fma.vfnmadd.ps" => "__builtin_ia32_vfnmaddps", - "llvm.x86.fma.vfnmadd.ps.256" => "__builtin_ia32_vfnmaddps256", - "llvm.x86.fma.vfnmadd.sd" => "__builtin_ia32_vfnmaddsd", - "llvm.x86.fma.vfnmadd.ss" => "__builtin_ia32_vfnmaddss", - "llvm.x86.fma.vfnmsub.pd" => "__builtin_ia32_vfnmsubpd", - "llvm.x86.fma.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256", - "llvm.x86.fma.vfnmsub.ps" => "__builtin_ia32_vfnmsubps", - "llvm.x86.fma.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256", - "llvm.x86.fma.vfnmsub.sd" => "__builtin_ia32_vfnmsubsd", - "llvm.x86.fma.vfnmsub.ss" => "__builtin_ia32_vfnmsubss", + "llvm.x86.fxrstor" => "__builtin_ia32_fxrstor", + "llvm.x86.fxrstor64" => "__builtin_ia32_fxrstor64", + "llvm.x86.fxsave" => "__builtin_ia32_fxsave", + "llvm.x86.fxsave64" => "__builtin_ia32_fxsave64", + "llvm.x86.incsspd" => "__builtin_ia32_incsspd", + "llvm.x86.incsspq" => "__builtin_ia32_incsspq", + "llvm.x86.invpcid" => "__builtin_ia32_invpcid", + "llvm.x86.ldtilecfg" => "__builtin_ia32_tile_loadconfig", + "llvm.x86.ldtilecfg.internal" => "__builtin_ia32_tile_loadconfig_internal", + "llvm.x86.llwpcb" => "__builtin_ia32_llwpcb", + "llvm.x86.loadiwkey" => "__builtin_ia32_loadiwkey", + "llvm.x86.lwpins32" => "__builtin_ia32_lwpins32", + "llvm.x86.lwpins64" => "__builtin_ia32_lwpins64", + "llvm.x86.lwpval32" => "__builtin_ia32_lwpval32", + "llvm.x86.lwpval64" => "__builtin_ia32_lwpval64", "llvm.x86.mmx.emms" => "__builtin_ia32_emms", "llvm.x86.mmx.femms" => "__builtin_ia32_femms", + "llvm.x86.mmx.maskmovq" => "__builtin_ia32_maskmovq", + "llvm.x86.mmx.movnt.dq" => "__builtin_ia32_movntq", + "llvm.x86.mmx.packssdw" => "__builtin_ia32_packssdw", + "llvm.x86.mmx.packsswb" => "__builtin_ia32_packsswb", + "llvm.x86.mmx.packuswb" => "__builtin_ia32_packuswb", + "llvm.x86.mmx.padd.b" => "__builtin_ia32_paddb", + "llvm.x86.mmx.padd.d" => "__builtin_ia32_paddd", + "llvm.x86.mmx.padd.q" => "__builtin_ia32_paddq", + "llvm.x86.mmx.padd.w" => "__builtin_ia32_paddw", + "llvm.x86.mmx.padds.b" => "__builtin_ia32_paddsb", + "llvm.x86.mmx.padds.w" => "__builtin_ia32_paddsw", + "llvm.x86.mmx.paddus.b" => "__builtin_ia32_paddusb", + "llvm.x86.mmx.paddus.w" => "__builtin_ia32_paddusw", + "llvm.x86.mmx.palignr.b" => "__builtin_ia32_palignr", + "llvm.x86.mmx.pand" => "__builtin_ia32_pand", + "llvm.x86.mmx.pandn" => "__builtin_ia32_pandn", + "llvm.x86.mmx.pavg.b" => "__builtin_ia32_pavgb", + "llvm.x86.mmx.pavg.w" => "__builtin_ia32_pavgw", + "llvm.x86.mmx.pcmpeq.b" => "__builtin_ia32_pcmpeqb", + "llvm.x86.mmx.pcmpeq.d" => "__builtin_ia32_pcmpeqd", + "llvm.x86.mmx.pcmpeq.w" => "__builtin_ia32_pcmpeqw", + "llvm.x86.mmx.pcmpgt.b" => "__builtin_ia32_pcmpgtb", + "llvm.x86.mmx.pcmpgt.d" => "__builtin_ia32_pcmpgtd", + "llvm.x86.mmx.pcmpgt.w" => "__builtin_ia32_pcmpgtw", + "llvm.x86.mmx.pextr.w" => "__builtin_ia32_vec_ext_v4hi", + "llvm.x86.mmx.pinsr.w" => "__builtin_ia32_vec_set_v4hi", + "llvm.x86.mmx.pmadd.wd" => "__builtin_ia32_pmaddwd", + "llvm.x86.mmx.pmaxs.w" => "__builtin_ia32_pmaxsw", + "llvm.x86.mmx.pmaxu.b" => "__builtin_ia32_pmaxub", + "llvm.x86.mmx.pmins.w" => "__builtin_ia32_pminsw", + "llvm.x86.mmx.pminu.b" => "__builtin_ia32_pminub", + "llvm.x86.mmx.pmovmskb" => "__builtin_ia32_pmovmskb", + "llvm.x86.mmx.pmulh.w" => "__builtin_ia32_pmulhw", + "llvm.x86.mmx.pmulhu.w" => "__builtin_ia32_pmulhuw", + "llvm.x86.mmx.pmull.w" => "__builtin_ia32_pmullw", + "llvm.x86.mmx.pmulu.dq" => "__builtin_ia32_pmuludq", + "llvm.x86.mmx.por" => "__builtin_ia32_por", + "llvm.x86.mmx.psad.bw" => "__builtin_ia32_psadbw", + "llvm.x86.mmx.psll.d" => "__builtin_ia32_pslld", + "llvm.x86.mmx.psll.q" => "__builtin_ia32_psllq", + "llvm.x86.mmx.psll.w" => "__builtin_ia32_psllw", + "llvm.x86.mmx.pslli.d" => "__builtin_ia32_pslldi", + "llvm.x86.mmx.pslli.q" => "__builtin_ia32_psllqi", + "llvm.x86.mmx.pslli.w" => "__builtin_ia32_psllwi", + "llvm.x86.mmx.psra.d" => "__builtin_ia32_psrad", + "llvm.x86.mmx.psra.w" => "__builtin_ia32_psraw", + "llvm.x86.mmx.psrai.d" => "__builtin_ia32_psradi", + "llvm.x86.mmx.psrai.w" => "__builtin_ia32_psrawi", + "llvm.x86.mmx.psrl.d" => "__builtin_ia32_psrld", + "llvm.x86.mmx.psrl.q" => "__builtin_ia32_psrlq", + "llvm.x86.mmx.psrl.w" => "__builtin_ia32_psrlw", + "llvm.x86.mmx.psrli.d" => "__builtin_ia32_psrldi", + "llvm.x86.mmx.psrli.q" => "__builtin_ia32_psrlqi", + "llvm.x86.mmx.psrli.w" => "__builtin_ia32_psrlwi", + "llvm.x86.mmx.psub.b" => "__builtin_ia32_psubb", + "llvm.x86.mmx.psub.d" => "__builtin_ia32_psubd", + "llvm.x86.mmx.psub.q" => "__builtin_ia32_psubq", + "llvm.x86.mmx.psub.w" => "__builtin_ia32_psubw", + "llvm.x86.mmx.psubs.b" => "__builtin_ia32_psubsb", + "llvm.x86.mmx.psubs.w" => "__builtin_ia32_psubsw", + "llvm.x86.mmx.psubus.b" => "__builtin_ia32_psubusb", + "llvm.x86.mmx.psubus.w" => "__builtin_ia32_psubusw", + "llvm.x86.mmx.punpckhbw" => "__builtin_ia32_punpckhbw", + "llvm.x86.mmx.punpckhdq" => "__builtin_ia32_punpckhdq", + "llvm.x86.mmx.punpckhwd" => "__builtin_ia32_punpckhwd", + "llvm.x86.mmx.punpcklbw" => "__builtin_ia32_punpcklbw", + "llvm.x86.mmx.punpckldq" => "__builtin_ia32_punpckldq", + "llvm.x86.mmx.punpcklwd" => "__builtin_ia32_punpcklwd", + "llvm.x86.mmx.pxor" => "__builtin_ia32_pxor", + "llvm.x86.monitorx" => "__builtin_ia32_monitorx", + "llvm.x86.movdir64b" => "__builtin_ia32_movdir64b", + "llvm.x86.mwaitx" => "__builtin_ia32_mwaitx", "llvm.x86.pclmulqdq" => "__builtin_ia32_pclmulqdq128", + "llvm.x86.pclmulqdq.256" => "__builtin_ia32_pclmulqdq256", + "llvm.x86.pclmulqdq.512" => "__builtin_ia32_pclmulqdq512", + "llvm.x86.ptwrite32" => "__builtin_ia32_ptwrite32", + "llvm.x86.ptwrite64" => "__builtin_ia32_ptwrite64", "llvm.x86.rdfsbase.32" => "__builtin_ia32_rdfsbase32", "llvm.x86.rdfsbase.64" => "__builtin_ia32_rdfsbase64", "llvm.x86.rdgsbase.32" => "__builtin_ia32_rdgsbase32", "llvm.x86.rdgsbase.64" => "__builtin_ia32_rdgsbase64", + "llvm.x86.rdpid" => "__builtin_ia32_rdpid", "llvm.x86.rdpmc" => "__builtin_ia32_rdpmc", + "llvm.x86.rdsspd" => "__builtin_ia32_rdsspd", + "llvm.x86.rdsspq" => "__builtin_ia32_rdsspq", "llvm.x86.rdtsc" => "__builtin_ia32_rdtsc", - "llvm.x86.rdtscp" => "__builtin_ia32_rdtscp", + "llvm.x86.rstorssp" => "__builtin_ia32_rstorssp", + "llvm.x86.saveprevssp" => "__builtin_ia32_saveprevssp", + "llvm.x86.senduipi" => "__builtin_ia32_senduipi", + "llvm.x86.serialize" => "__builtin_ia32_serialize", + "llvm.x86.setssbsy" => "__builtin_ia32_setssbsy", "llvm.x86.sha1msg1" => "__builtin_ia32_sha1msg1", "llvm.x86.sha1msg2" => "__builtin_ia32_sha1msg2", "llvm.x86.sha1nexte" => "__builtin_ia32_sha1nexte", @@ -2654,8 +2146,7 @@ match name { "llvm.x86.sha256msg1" => "__builtin_ia32_sha256msg1", "llvm.x86.sha256msg2" => "__builtin_ia32_sha256msg2", "llvm.x86.sha256rnds2" => "__builtin_ia32_sha256rnds2", - "llvm.x86.sse.add.ss" => "__builtin_ia32_addss", - "llvm.x86.sse.cmp.ps" => "__builtin_ia32_cmpps", + "llvm.x86.slwpcb" => "__builtin_ia32_slwpcb", "llvm.x86.sse.cmp.ss" => "__builtin_ia32_cmpss", "llvm.x86.sse.comieq.ss" => "__builtin_ia32_comieq", "llvm.x86.sse.comige.ss" => "__builtin_ia32_comige", @@ -2663,37 +2154,34 @@ match name { "llvm.x86.sse.comile.ss" => "__builtin_ia32_comile", "llvm.x86.sse.comilt.ss" => "__builtin_ia32_comilt", "llvm.x86.sse.comineq.ss" => "__builtin_ia32_comineq", - "llvm.x86.sse.cvtsi2ss" => "__builtin_ia32_cvtsi2ss", - "llvm.x86.sse.cvtsi642ss" => "__builtin_ia32_cvtsi642ss", + "llvm.x86.sse.cvtpd2pi" => "__builtin_ia32_cvtpd2pi", + "llvm.x86.sse.cvtpi2pd" => "__builtin_ia32_cvtpi2pd", + "llvm.x86.sse.cvtpi2ps" => "__builtin_ia32_cvtpi2ps", + "llvm.x86.sse.cvtps2pi" => "__builtin_ia32_cvtps2pi", "llvm.x86.sse.cvtss2si" => "__builtin_ia32_cvtss2si", "llvm.x86.sse.cvtss2si64" => "__builtin_ia32_cvtss2si64", + "llvm.x86.sse.cvttpd2pi" => "__builtin_ia32_cvttpd2pi", + "llvm.x86.sse.cvttps2pi" => "__builtin_ia32_cvttps2pi", "llvm.x86.sse.cvttss2si" => "__builtin_ia32_cvttss2si", "llvm.x86.sse.cvttss2si64" => "__builtin_ia32_cvttss2si64", - "llvm.x86.sse.div.ss" => "__builtin_ia32_divss", "llvm.x86.sse.max.ps" => "__builtin_ia32_maxps", "llvm.x86.sse.max.ss" => "__builtin_ia32_maxss", "llvm.x86.sse.min.ps" => "__builtin_ia32_minps", "llvm.x86.sse.min.ss" => "__builtin_ia32_minss", "llvm.x86.sse.movmsk.ps" => "__builtin_ia32_movmskps", - "llvm.x86.sse.mul.ss" => "__builtin_ia32_mulss", + "llvm.x86.sse.pshuf.w" => "__builtin_ia32_pshufw", "llvm.x86.sse.rcp.ps" => "__builtin_ia32_rcpps", "llvm.x86.sse.rcp.ss" => "__builtin_ia32_rcpss", "llvm.x86.sse.rsqrt.ps" => "__builtin_ia32_rsqrtps", "llvm.x86.sse.rsqrt.ss" => "__builtin_ia32_rsqrtss", "llvm.x86.sse.sfence" => "__builtin_ia32_sfence", - "llvm.x86.sse.sqrt.ps" => "__builtin_ia32_sqrtps", - "llvm.x86.sse.sqrt.ss" => "__builtin_ia32_sqrtss", - "llvm.x86.sse.storeu.ps" => "__builtin_ia32_storeups", - "llvm.x86.sse.sub.ss" => "__builtin_ia32_subss", "llvm.x86.sse.ucomieq.ss" => "__builtin_ia32_ucomieq", "llvm.x86.sse.ucomige.ss" => "__builtin_ia32_ucomige", "llvm.x86.sse.ucomigt.ss" => "__builtin_ia32_ucomigt", "llvm.x86.sse.ucomile.ss" => "__builtin_ia32_ucomile", "llvm.x86.sse.ucomilt.ss" => "__builtin_ia32_ucomilt", "llvm.x86.sse.ucomineq.ss" => "__builtin_ia32_ucomineq", - "llvm.x86.sse2.add.sd" => "__builtin_ia32_addsd", "llvm.x86.sse2.clflush" => "__builtin_ia32_clflush", - "llvm.x86.sse2.cmp.pd" => "__builtin_ia32_cmppd", "llvm.x86.sse2.cmp.sd" => "__builtin_ia32_cmpsd", "llvm.x86.sse2.comieq.sd" => "__builtin_ia32_comisdeq", "llvm.x86.sse2.comige.sd" => "__builtin_ia32_comisdge", @@ -2701,23 +2189,16 @@ match name { "llvm.x86.sse2.comile.sd" => "__builtin_ia32_comisdle", "llvm.x86.sse2.comilt.sd" => "__builtin_ia32_comisdlt", "llvm.x86.sse2.comineq.sd" => "__builtin_ia32_comisdneq", - "llvm.x86.sse2.cvtdq2pd" => "__builtin_ia32_cvtdq2pd", - "llvm.x86.sse2.cvtdq2ps" => "__builtin_ia32_cvtdq2ps", "llvm.x86.sse2.cvtpd2dq" => "__builtin_ia32_cvtpd2dq", "llvm.x86.sse2.cvtpd2ps" => "__builtin_ia32_cvtpd2ps", "llvm.x86.sse2.cvtps2dq" => "__builtin_ia32_cvtps2dq", - "llvm.x86.sse2.cvtps2pd" => "__builtin_ia32_cvtps2pd", "llvm.x86.sse2.cvtsd2si" => "__builtin_ia32_cvtsd2si", "llvm.x86.sse2.cvtsd2si64" => "__builtin_ia32_cvtsd2si64", "llvm.x86.sse2.cvtsd2ss" => "__builtin_ia32_cvtsd2ss", - "llvm.x86.sse2.cvtsi2sd" => "__builtin_ia32_cvtsi2sd", - "llvm.x86.sse2.cvtsi642sd" => "__builtin_ia32_cvtsi642sd", - "llvm.x86.sse2.cvtss2sd" => "__builtin_ia32_cvtss2sd", "llvm.x86.sse2.cvttpd2dq" => "__builtin_ia32_cvttpd2dq", "llvm.x86.sse2.cvttps2dq" => "__builtin_ia32_cvttps2dq", "llvm.x86.sse2.cvttsd2si" => "__builtin_ia32_cvttsd2si", "llvm.x86.sse2.cvttsd2si64" => "__builtin_ia32_cvttsd2si64", - "llvm.x86.sse2.div.sd" => "__builtin_ia32_divsd", "llvm.x86.sse2.lfence" => "__builtin_ia32_lfence", "llvm.x86.sse2.maskmov.dqu" => "__builtin_ia32_maskmovdqu", "llvm.x86.sse2.max.pd" => "__builtin_ia32_maxpd", @@ -2726,33 +2207,18 @@ match name { "llvm.x86.sse2.min.pd" => "__builtin_ia32_minpd", "llvm.x86.sse2.min.sd" => "__builtin_ia32_minsd", "llvm.x86.sse2.movmsk.pd" => "__builtin_ia32_movmskpd", - "llvm.x86.sse2.mul.sd" => "__builtin_ia32_mulsd", "llvm.x86.sse2.packssdw.128" => "__builtin_ia32_packssdw128", "llvm.x86.sse2.packsswb.128" => "__builtin_ia32_packsswb128", "llvm.x86.sse2.packuswb.128" => "__builtin_ia32_packuswb128", - "llvm.x86.sse2.padds.b" => "__builtin_ia32_paddsb128", - "llvm.x86.sse2.padds.w" => "__builtin_ia32_paddsw128", - "llvm.x86.sse2.paddus.b" => "__builtin_ia32_paddusb128", - "llvm.x86.sse2.paddus.w" => "__builtin_ia32_paddusw128", "llvm.x86.sse2.pause" => "__builtin_ia32_pause", "llvm.x86.sse2.pavg.b" => "__builtin_ia32_pavgb128", "llvm.x86.sse2.pavg.w" => "__builtin_ia32_pavgw128", "llvm.x86.sse2.pmadd.wd" => "__builtin_ia32_pmaddwd128", - "llvm.x86.sse2.pmaxs.w" => "__builtin_ia32_pmaxsw128", - "llvm.x86.sse2.pmaxu.b" => "__builtin_ia32_pmaxub128", - "llvm.x86.sse2.pmins.w" => "__builtin_ia32_pminsw128", - "llvm.x86.sse2.pminu.b" => "__builtin_ia32_pminub128", "llvm.x86.sse2.pmovmskb.128" => "__builtin_ia32_pmovmskb128", "llvm.x86.sse2.pmulh.w" => "__builtin_ia32_pmulhw128", "llvm.x86.sse2.pmulhu.w" => "__builtin_ia32_pmulhuw128", - "llvm.x86.sse2.pmulu.dq" => "__builtin_ia32_pmuludq128", "llvm.x86.sse2.psad.bw" => "__builtin_ia32_psadbw128", - "llvm.x86.sse2.pshuf.d" => "__builtin_ia32_pshufd", - "llvm.x86.sse2.pshufh.w" => "__builtin_ia32_pshufhw", - "llvm.x86.sse2.pshufl.w" => "__builtin_ia32_pshuflw", "llvm.x86.sse2.psll.d" => "__builtin_ia32_pslld128", - "llvm.x86.sse2.psll.dq" => "__builtin_ia32_pslldqi128", - "llvm.x86.sse2.psll.dq.bs" => "__builtin_ia32_pslldqi128_byteshift", "llvm.x86.sse2.psll.q" => "__builtin_ia32_psllq128", "llvm.x86.sse2.psll.w" => "__builtin_ia32_psllw128", "llvm.x86.sse2.pslli.d" => "__builtin_ia32_pslldi128", @@ -2763,23 +2229,11 @@ match name { "llvm.x86.sse2.psrai.d" => "__builtin_ia32_psradi128", "llvm.x86.sse2.psrai.w" => "__builtin_ia32_psrawi128", "llvm.x86.sse2.psrl.d" => "__builtin_ia32_psrld128", - "llvm.x86.sse2.psrl.dq" => "__builtin_ia32_psrldqi128", - "llvm.x86.sse2.psrl.dq.bs" => "__builtin_ia32_psrldqi128_byteshift", "llvm.x86.sse2.psrl.q" => "__builtin_ia32_psrlq128", "llvm.x86.sse2.psrl.w" => "__builtin_ia32_psrlw128", "llvm.x86.sse2.psrli.d" => "__builtin_ia32_psrldi128", "llvm.x86.sse2.psrli.q" => "__builtin_ia32_psrlqi128", "llvm.x86.sse2.psrli.w" => "__builtin_ia32_psrlwi128", - "llvm.x86.sse2.psubs.b" => "__builtin_ia32_psubsb128", - "llvm.x86.sse2.psubs.w" => "__builtin_ia32_psubsw128", - "llvm.x86.sse2.psubus.b" => "__builtin_ia32_psubusb128", - "llvm.x86.sse2.psubus.w" => "__builtin_ia32_psubusw128", - "llvm.x86.sse2.sqrt.pd" => "__builtin_ia32_sqrtpd", - "llvm.x86.sse2.sqrt.sd" => "__builtin_ia32_sqrtsd", - "llvm.x86.sse2.storel.dq" => "__builtin_ia32_storelv4si", - "llvm.x86.sse2.storeu.dq" => "__builtin_ia32_storedqu", - "llvm.x86.sse2.storeu.pd" => "__builtin_ia32_storeupd", - "llvm.x86.sse2.sub.sd" => "__builtin_ia32_subsd", "llvm.x86.sse2.ucomieq.sd" => "__builtin_ia32_ucomisdeq", "llvm.x86.sse2.ucomige.sd" => "__builtin_ia32_ucomisdge", "llvm.x86.sse2.ucomigt.sd" => "__builtin_ia32_ucomisdgt", @@ -2795,41 +2249,15 @@ match name { "llvm.x86.sse3.ldu.dq" => "__builtin_ia32_lddqu", "llvm.x86.sse3.monitor" => "__builtin_ia32_monitor", "llvm.x86.sse3.mwait" => "__builtin_ia32_mwait", - "llvm.x86.sse41.blendpd" => "__builtin_ia32_blendpd", - "llvm.x86.sse41.blendps" => "__builtin_ia32_blendps", "llvm.x86.sse41.blendvpd" => "__builtin_ia32_blendvpd", "llvm.x86.sse41.blendvps" => "__builtin_ia32_blendvps", "llvm.x86.sse41.dppd" => "__builtin_ia32_dppd", "llvm.x86.sse41.dpps" => "__builtin_ia32_dpps", - "llvm.x86.sse41.extractps" => "__builtin_ia32_extractps128", "llvm.x86.sse41.insertps" => "__builtin_ia32_insertps128", - "llvm.x86.sse41.movntdqa" => "__builtin_ia32_movntdqa", "llvm.x86.sse41.mpsadbw" => "__builtin_ia32_mpsadbw128", "llvm.x86.sse41.packusdw" => "__builtin_ia32_packusdw128", "llvm.x86.sse41.pblendvb" => "__builtin_ia32_pblendvb128", - "llvm.x86.sse41.pblendw" => "__builtin_ia32_pblendw128", "llvm.x86.sse41.phminposuw" => "__builtin_ia32_phminposuw128", - "llvm.x86.sse41.pmaxsb" => "__builtin_ia32_pmaxsb128", - "llvm.x86.sse41.pmaxsd" => "__builtin_ia32_pmaxsd128", - "llvm.x86.sse41.pmaxud" => "__builtin_ia32_pmaxud128", - "llvm.x86.sse41.pmaxuw" => "__builtin_ia32_pmaxuw128", - "llvm.x86.sse41.pminsb" => "__builtin_ia32_pminsb128", - "llvm.x86.sse41.pminsd" => "__builtin_ia32_pminsd128", - "llvm.x86.sse41.pminud" => "__builtin_ia32_pminud128", - "llvm.x86.sse41.pminuw" => "__builtin_ia32_pminuw128", - "llvm.x86.sse41.pmovsxbd" => "__builtin_ia32_pmovsxbd128", - "llvm.x86.sse41.pmovsxbq" => "__builtin_ia32_pmovsxbq128", - "llvm.x86.sse41.pmovsxbw" => "__builtin_ia32_pmovsxbw128", - "llvm.x86.sse41.pmovsxdq" => "__builtin_ia32_pmovsxdq128", - "llvm.x86.sse41.pmovsxwd" => "__builtin_ia32_pmovsxwd128", - "llvm.x86.sse41.pmovsxwq" => "__builtin_ia32_pmovsxwq128", - "llvm.x86.sse41.pmovzxbd" => "__builtin_ia32_pmovzxbd128", - "llvm.x86.sse41.pmovzxbq" => "__builtin_ia32_pmovzxbq128", - "llvm.x86.sse41.pmovzxbw" => "__builtin_ia32_pmovzxbw128", - "llvm.x86.sse41.pmovzxdq" => "__builtin_ia32_pmovzxdq128", - "llvm.x86.sse41.pmovzxwd" => "__builtin_ia32_pmovzxwd128", - "llvm.x86.sse41.pmovzxwq" => "__builtin_ia32_pmovzxwq128", - "llvm.x86.sse41.pmuldq" => "__builtin_ia32_pmuldq128", "llvm.x86.sse41.ptestc" => "__builtin_ia32_ptestc128", "llvm.x86.sse41.ptestnzc" => "__builtin_ia32_ptestnzc128", "llvm.x86.sse41.ptestz" => "__builtin_ia32_ptestz128", @@ -2859,35 +2287,82 @@ match name { "llvm.x86.sse4a.extrqi" => "__builtin_ia32_extrqi", "llvm.x86.sse4a.insertq" => "__builtin_ia32_insertq", "llvm.x86.sse4a.insertqi" => "__builtin_ia32_insertqi", - "llvm.x86.sse4a.movnt.sd" => "__builtin_ia32_movntsd", - "llvm.x86.sse4a.movnt.ss" => "__builtin_ia32_movntss", - "llvm.x86.ssse3.pabs.b.128" => "__builtin_ia32_pabsb128", - "llvm.x86.ssse3.pabs.d.128" => "__builtin_ia32_pabsd128", - "llvm.x86.ssse3.pabs.w.128" => "__builtin_ia32_pabsw128", + "llvm.x86.ssse3.pabs.b" => "__builtin_ia32_pabsb", + "llvm.x86.ssse3.pabs.d" => "__builtin_ia32_pabsd", + "llvm.x86.ssse3.pabs.w" => "__builtin_ia32_pabsw", + "llvm.x86.ssse3.phadd.d" => "__builtin_ia32_phaddd", "llvm.x86.ssse3.phadd.d.128" => "__builtin_ia32_phaddd128", + "llvm.x86.ssse3.phadd.sw" => "__builtin_ia32_phaddsw", "llvm.x86.ssse3.phadd.sw.128" => "__builtin_ia32_phaddsw128", + "llvm.x86.ssse3.phadd.w" => "__builtin_ia32_phaddw", "llvm.x86.ssse3.phadd.w.128" => "__builtin_ia32_phaddw128", + "llvm.x86.ssse3.phsub.d" => "__builtin_ia32_phsubd", "llvm.x86.ssse3.phsub.d.128" => "__builtin_ia32_phsubd128", + "llvm.x86.ssse3.phsub.sw" => "__builtin_ia32_phsubsw", "llvm.x86.ssse3.phsub.sw.128" => "__builtin_ia32_phsubsw128", + "llvm.x86.ssse3.phsub.w" => "__builtin_ia32_phsubw", "llvm.x86.ssse3.phsub.w.128" => "__builtin_ia32_phsubw128", + "llvm.x86.ssse3.pmadd.ub.sw" => "__builtin_ia32_pmaddubsw", "llvm.x86.ssse3.pmadd.ub.sw.128" => "__builtin_ia32_pmaddubsw128", + "llvm.x86.ssse3.pmul.hr.sw" => "__builtin_ia32_pmulhrsw", "llvm.x86.ssse3.pmul.hr.sw.128" => "__builtin_ia32_pmulhrsw128", + "llvm.x86.ssse3.pshuf.b" => "__builtin_ia32_pshufb", "llvm.x86.ssse3.pshuf.b.128" => "__builtin_ia32_pshufb128", + "llvm.x86.ssse3.psign.b" => "__builtin_ia32_psignb", "llvm.x86.ssse3.psign.b.128" => "__builtin_ia32_psignb128", + "llvm.x86.ssse3.psign.d" => "__builtin_ia32_psignd", "llvm.x86.ssse3.psign.d.128" => "__builtin_ia32_psignd128", + "llvm.x86.ssse3.psign.w" => "__builtin_ia32_psignw", "llvm.x86.ssse3.psign.w.128" => "__builtin_ia32_psignw128", - "llvm.x86.subborrow.u32" => "__builtin_ia32_subborrow_u32", - "llvm.x86.subborrow.u64" => "__builtin_ia32_subborrow_u64", + "llvm.x86.sttilecfg" => "__builtin_ia32_tile_storeconfig", + "llvm.x86.stui" => "__builtin_ia32_stui", "llvm.x86.tbm.bextri.u32" => "__builtin_ia32_bextri_u32", "llvm.x86.tbm.bextri.u64" => "__builtin_ia32_bextri_u64", - "llvm.x86.vcvtph2ps.128" => "__builtin_ia32_vcvtph2ps", - "llvm.x86.vcvtph2ps.256" => "__builtin_ia32_vcvtph2ps256", + "llvm.x86.tdpbf16ps" => "__builtin_ia32_tdpbf16ps", + "llvm.x86.tdpbf16ps.internal" => "__builtin_ia32_tdpbf16ps_internal", + "llvm.x86.tdpbssd" => "__builtin_ia32_tdpbssd", + "llvm.x86.tdpbssd.internal" => "__builtin_ia32_tdpbssd_internal", + "llvm.x86.tdpbsud" => "__builtin_ia32_tdpbsud", + "llvm.x86.tdpbsud.internal" => "__builtin_ia32_tdpbsud_internal", + "llvm.x86.tdpbusd" => "__builtin_ia32_tdpbusd", + "llvm.x86.tdpbusd.internal" => "__builtin_ia32_tdpbusd_internal", + "llvm.x86.tdpbuud" => "__builtin_ia32_tdpbuud", + "llvm.x86.tdpbuud.internal" => "__builtin_ia32_tdpbuud_internal", + "llvm.x86.testui" => "__builtin_ia32_testui", + "llvm.x86.tileloadd64" => "__builtin_ia32_tileloadd64", + "llvm.x86.tileloadd64.internal" => "__builtin_ia32_tileloadd64_internal", + "llvm.x86.tileloaddt164" => "__builtin_ia32_tileloaddt164", + "llvm.x86.tileloaddt164.internal" => "__builtin_ia32_tileloaddt164_internal", + "llvm.x86.tilerelease" => "__builtin_ia32_tilerelease", + "llvm.x86.tilestored64" => "__builtin_ia32_tilestored64", + "llvm.x86.tilestored64.internal" => "__builtin_ia32_tilestored64_internal", + "llvm.x86.tilezero" => "__builtin_ia32_tilezero", + "llvm.x86.tilezero.internal" => "__builtin_ia32_tilezero_internal", + "llvm.x86.tpause" => "__builtin_ia32_tpause", + "llvm.x86.umonitor" => "__builtin_ia32_umonitor", + "llvm.x86.umwait" => "__builtin_ia32_umwait", "llvm.x86.vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph", "llvm.x86.vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256", + "llvm.x86.vgf2p8affineinvqb.128" => "__builtin_ia32_vgf2p8affineinvqb_v16qi", + "llvm.x86.vgf2p8affineinvqb.256" => "__builtin_ia32_vgf2p8affineinvqb_v32qi", + "llvm.x86.vgf2p8affineinvqb.512" => "__builtin_ia32_vgf2p8affineinvqb_v64qi", + "llvm.x86.vgf2p8affineqb.128" => "__builtin_ia32_vgf2p8affineqb_v16qi", + "llvm.x86.vgf2p8affineqb.256" => "__builtin_ia32_vgf2p8affineqb_v32qi", + "llvm.x86.vgf2p8affineqb.512" => "__builtin_ia32_vgf2p8affineqb_v64qi", + "llvm.x86.vgf2p8mulb.128" => "__builtin_ia32_vgf2p8mulb_v16qi", + "llvm.x86.vgf2p8mulb.256" => "__builtin_ia32_vgf2p8mulb_v32qi", + "llvm.x86.vgf2p8mulb.512" => "__builtin_ia32_vgf2p8mulb_v64qi", + "llvm.x86.wbinvd" => "__builtin_ia32_wbinvd", + "llvm.x86.wbnoinvd" => "__builtin_ia32_wbnoinvd", "llvm.x86.wrfsbase.32" => "__builtin_ia32_wrfsbase32", "llvm.x86.wrfsbase.64" => "__builtin_ia32_wrfsbase64", "llvm.x86.wrgsbase.32" => "__builtin_ia32_wrgsbase32", "llvm.x86.wrgsbase.64" => "__builtin_ia32_wrgsbase64", + "llvm.x86.wrpkru" => "__builtin_ia32_wrpkru", + "llvm.x86.wrssd" => "__builtin_ia32_wrssd", + "llvm.x86.wrssq" => "__builtin_ia32_wrssq", + "llvm.x86.wrussd" => "__builtin_ia32_wrussd", + "llvm.x86.wrussq" => "__builtin_ia32_wrussq", "llvm.x86.xabort" => "__builtin_ia32_xabort", "llvm.x86.xbegin" => "__builtin_ia32_xbegin", "llvm.x86.xend" => "__builtin_ia32_xend", @@ -2897,16 +2372,6 @@ match name { "llvm.x86.xop.vfrcz.ps.256" => "__builtin_ia32_vfrczps256", "llvm.x86.xop.vfrcz.sd" => "__builtin_ia32_vfrczsd", "llvm.x86.xop.vfrcz.ss" => "__builtin_ia32_vfrczss", - "llvm.x86.xop.vpcmov" => "__builtin_ia32_vpcmov", - "llvm.x86.xop.vpcmov.256" => "__builtin_ia32_vpcmov_256", - "llvm.x86.xop.vpcomb" => "__builtin_ia32_vpcomb", - "llvm.x86.xop.vpcomd" => "__builtin_ia32_vpcomd", - "llvm.x86.xop.vpcomq" => "__builtin_ia32_vpcomq", - "llvm.x86.xop.vpcomub" => "__builtin_ia32_vpcomub", - "llvm.x86.xop.vpcomud" => "__builtin_ia32_vpcomud", - "llvm.x86.xop.vpcomuq" => "__builtin_ia32_vpcomuq", - "llvm.x86.xop.vpcomuw" => "__builtin_ia32_vpcomuw", - "llvm.x86.xop.vpcomw" => "__builtin_ia32_vpcomw", "llvm.x86.xop.vpermil2pd" => "__builtin_ia32_vpermil2pd", "llvm.x86.xop.vpermil2pd.256" => "__builtin_ia32_vpermil2pd256", "llvm.x86.xop.vpermil2ps" => "__builtin_ia32_vpermil2ps", @@ -2939,14 +2404,6 @@ match name { "llvm.x86.xop.vpmadcsswd" => "__builtin_ia32_vpmadcsswd", "llvm.x86.xop.vpmadcswd" => "__builtin_ia32_vpmadcswd", "llvm.x86.xop.vpperm" => "__builtin_ia32_vpperm", - "llvm.x86.xop.vprotb" => "__builtin_ia32_vprotb", - "llvm.x86.xop.vprotbi" => "__builtin_ia32_vprotbi", - "llvm.x86.xop.vprotd" => "__builtin_ia32_vprotd", - "llvm.x86.xop.vprotdi" => "__builtin_ia32_vprotdi", - "llvm.x86.xop.vprotq" => "__builtin_ia32_vprotq", - "llvm.x86.xop.vprotqi" => "__builtin_ia32_vprotqi", - "llvm.x86.xop.vprotw" => "__builtin_ia32_vprotw", - "llvm.x86.xop.vprotwi" => "__builtin_ia32_vprotwi", "llvm.x86.xop.vpshab" => "__builtin_ia32_vpshab", "llvm.x86.xop.vpshad" => "__builtin_ia32_vpshad", "llvm.x86.xop.vpshaq" => "__builtin_ia32_vpshaq", @@ -2955,6 +2412,8 @@ match name { "llvm.x86.xop.vpshld" => "__builtin_ia32_vpshld", "llvm.x86.xop.vpshlq" => "__builtin_ia32_vpshlq", "llvm.x86.xop.vpshlw" => "__builtin_ia32_vpshlw", + "llvm.x86.xresldtrk" => "__builtin_ia32_xresldtrk", + "llvm.x86.xsusldtrk" => "__builtin_ia32_xsusldtrk", "llvm.x86.xtest" => "__builtin_ia32_xtest", // xcore "llvm.xcore.bitrev" => "__builtin_bitrev", diff --git a/tools/generate_intrinsics.py b/tools/generate_intrinsics.py index 587db3679ef4..069611e60eb0 100644 --- a/tools/generate_intrinsics.py +++ b/tools/generate_intrinsics.py @@ -5,11 +5,6 @@ import subprocess from os import walk -LLVM_PATH = llvm_path = os.path.join( - os.path.dirname(os.path.abspath(__file__)), - "llvm-project", -) - def run_command(command, cwd=None): p = subprocess.Popen(command, cwd=cwd) if p.wait() != 0: @@ -17,21 +12,27 @@ def run_command(command, cwd=None): sys.exit(1) -def clone_llvm_repository(): - if os.path.exists(LLVM_PATH): +def clone_repository(repo_name, path, repo_url, sub_path=None): + if os.path.exists(path): while True: - choice = input("There is already a llvm-project folder, do you want to update it? [y/N]") + choice = input("There is already a `{}` folder, do you want to update it? [y/N]".format(repo_name)) if choice == "" or choice.lower() == "n": print("Skipping repository update.") return elif choice.lower() == "y": print("Updating repository...") - run_command(["git", "pull", "origin"], cwd="llvm-project") + run_command(["git", "pull", "origin"], cwd=path) return else: print("Didn't understand answer...") - print("Cloning LLVM repository...") - run_command(["git", "clone", "https://github.com/llvm/llvm-project", "--depth", "1", LLVM_PATH]) + print("Cloning {} repository...".format(repo_name)) + if sub_path is None: + run_command(["git", "clone", repo_url, "--depth", "1", path]) + else: + run_command(["git", "clone", repo_url, "--filter=tree:0", "--no-checkout", path]) + run_command(["git", "sparse-checkout", "init"], cwd=path) + run_command(["git", "sparse-checkout", "set", "add", sub_path], cwd=path) + run_command(["git", "checkout"], cwd=path) def extract_instrinsics(intrinsics, file): @@ -76,9 +77,9 @@ def extract_instrinsics(intrinsics, file): print("Done!") -def update_intrinsics(): +def update_intrinsics(llvm_path): files = [] - intrinsics_path = os.path.join(LLVM_PATH, "llvm/include/llvm/IR") + intrinsics_path = os.path.join(llvm_path, "llvm/include/llvm/IR") for (dirpath, dirnames, filenames) in walk(intrinsics_path): files.extend([os.path.join(intrinsics_path, f) for f in filenames if f.endswith(".td")]) @@ -110,9 +111,18 @@ def update_intrinsics(): def main(): + llvm_path = os.path.join( + os.path.dirname(os.path.abspath(__file__)), + "llvm-project", + ) + # First, we clone the LLVM repository if it's not already here. - clone_llvm_repository() - update_intrinsics() + clone_repository( + "llvm-project", + llvm_path, + "https://github.com/llvm/llvm-project", + sub_path="llvm/include/llvm/IR") + update_intrinsics(llvm_path) if __name__ == "__main__": From 19d8617330a481dc2a0cea149f5d75c7ed3d3203 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Tue, 3 May 2022 21:24:14 +0200 Subject: [PATCH 076/356] Generate intrinsics translations from llvmint as well --- .gitignore | 1 + tools/generate_intrinsics.py | 97 +++++++++++++++++++++++++++++++++--- 2 files changed, 91 insertions(+), 7 deletions(-) diff --git a/.gitignore b/.gitignore index ba11981a5e3c..ffd36ddb7db0 100644 --- a/.gitignore +++ b/.gitignore @@ -21,3 +21,4 @@ test-backend gcc_path benchmarks tools/llvm-project +tools/llvmint diff --git a/tools/generate_intrinsics.py b/tools/generate_intrinsics.py index 069611e60eb0..88b8b54b6baa 100644 --- a/tools/generate_intrinsics.py +++ b/tools/generate_intrinsics.py @@ -1,3 +1,4 @@ +import json import os import re import sys @@ -35,6 +36,10 @@ def clone_repository(repo_name, path, repo_url, sub_path=None): run_command(["git", "checkout"], cwd=path) +def append_intrinsic(array, intrinsic_name, translation): + array.append((intrinsic_name, translation)) + + def extract_instrinsics(intrinsics, file): print("Extracting intrinsics from `{}`...".format(file)) with open(file, "r", encoding="utf8") as f: @@ -70,25 +75,85 @@ def extract_instrinsics(intrinsics, file): if current_arch not in intrinsics: intrinsics[current_arch] = [] for entry in entries: - intrinsics[current_arch].append('"{}" => "{}",'.format(intrinsic, entry)) + append_intrinsic(intrinsics[current_arch], intrinsic, entry) continue pos += 1 continue print("Done!") -def update_intrinsics(llvm_path): +def extract_instrinsics_from_llvm(llvm_path, intrinsics): files = [] intrinsics_path = os.path.join(llvm_path, "llvm/include/llvm/IR") for (dirpath, dirnames, filenames) in walk(intrinsics_path): files.extend([os.path.join(intrinsics_path, f) for f in filenames if f.endswith(".td")]) - intrinsics = {} for file in files: extract_instrinsics(intrinsics, file) + +def append_translation(json_data, p, array): + it = json_data["index"][p] + content = it["docs"].split('`') + if len(content) != 5: + return + append_intrinsic(array, content[1], content[3]) + + +def extract_instrinsics_from_llvmint(llvmint, intrinsics): + archs = [ + "AMDGPU", + "aarch64", + "arm", + "cuda", + "hexagon", + "mips", + "nvvm", + "ppc", + "ptx", + "x86", + "xcore", + ] + + json_file = os.path.join(llvmint, "target/doc/llvmint.json") + if not os.path.exists(json_file): + # We need to regenerate the documentation! + run_command( + ["cargo", "rustdoc", "--", "-Zunstable-options", "--output-format", "json"], + cwd=llvmint, + ) + with open(json_file, "r", encoding="utf8") as f: + json_data = json.loads(f.read()) + for p in json_data["paths"]: + it = json_data["paths"][p] + if it["crate_id"] != 0: + # This is from an external crate. + continue + if it["kind"] != "function": + # We're only looking for functions. + continue + # if len(it["path"]) == 2: + # # This is a "general" intrinsic, not bound to a specific arch. + # append_translation(json_data, p, general) + # continue + if len(it["path"]) != 3 or it["path"][1] not in archs: + continue + arch = it["path"][1] + if arch not in intrinsics: + intrinsics[arch] = [] + append_translation(json_data, p, intrinsics[arch]) + + +def update_intrinsics(llvm_path, llvmint): + intrinsics = {} + all_intrinsics = {} + + extract_instrinsics_from_llvm(llvm_path, intrinsics) + extract_instrinsics_from_llvmint(llvmint, intrinsics) + archs = [arch for arch in intrinsics] archs.sort() + output_file = os.path.join( os.path.dirname(os.path.abspath(__file__)), "../src/intrinsic/archs.rs", @@ -103,8 +168,16 @@ def update_intrinsics(llvm_path): continue intrinsics[arch].sort() out.write(' // {}\n'.format(arch)) - out.write('\n'.join([' {}'.format(x) for x in intrinsics[arch]])) - out.write('\n') + for entry in intrinsics[arch]: + if entry[0] in all_intrinsics: + if all_intrinsics[entry[0]] == entry[1]: + # This is a "full" duplicate, both the LLVM instruction and the GCC + # translation are the same. + continue + out.write(' // [DUPLICATE]: "{}" => "{}",\n'.format(entry[0], entry[1])) + else: + out.write(' "{}" => "{}",\n'.format(entry[0], entry[1])) + all_intrinsics[entry[0]] = entry[1] out.write(' _ => unimplemented!("***** unsupported LLVM intrinsic {}", name),\n') out.write("}\n") print("Done!") @@ -115,14 +188,24 @@ def main(): os.path.dirname(os.path.abspath(__file__)), "llvm-project", ) + llvmint_path = os.path.join( + os.path.dirname(os.path.abspath(__file__)), + "llvmint", + ) # First, we clone the LLVM repository if it's not already here. clone_repository( "llvm-project", llvm_path, "https://github.com/llvm/llvm-project", - sub_path="llvm/include/llvm/IR") - update_intrinsics(llvm_path) + sub_path="llvm/include/llvm/IR", + ) + clone_repository( + "llvmint", + llvmint_path, + "https://github.com/GuillaumeGomez/llvmint", + ) + update_intrinsics(llvm_path, llvmint_path) if __name__ == "__main__": From f402cfe561fa371483360c1559c9507667470304 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Tue, 3 May 2022 21:24:22 +0200 Subject: [PATCH 077/356] Update intrinsics --- src/intrinsic/archs.rs | 1873 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 1862 insertions(+), 11 deletions(-) diff --git a/src/intrinsic/archs.rs b/src/intrinsic/archs.rs index 026ed7c6c7ca..427ca77e9d0b 100644 --- a/src/intrinsic/archs.rs +++ b/src/intrinsic/archs.rs @@ -1,6 +1,35 @@ // File generated by `rustc_codegen_gcc/tools/generate_intrinsics.py` // DO NOT EDIT IT! match name { + // AMDGPU + "llvm.AMDGPU.div.fixup.f32" => "__builtin_amdgpu_div_fixup", + "llvm.AMDGPU.div.fixup.f64" => "__builtin_amdgpu_div_fixup", + "llvm.AMDGPU.div.fixup.v2f64" => "__builtin_amdgpu_div_fixup", + "llvm.AMDGPU.div.fixup.v4f32" => "__builtin_amdgpu_div_fixup", + "llvm.AMDGPU.div.fmas.f32" => "__builtin_amdgpu_div_fmas", + "llvm.AMDGPU.div.fmas.f64" => "__builtin_amdgpu_div_fmas", + "llvm.AMDGPU.div.fmas.v2f64" => "__builtin_amdgpu_div_fmas", + "llvm.AMDGPU.div.fmas.v4f32" => "__builtin_amdgpu_div_fmas", + "llvm.AMDGPU.ldexp.f32" => "__builtin_amdgpu_ldexp", + "llvm.AMDGPU.ldexp.f64" => "__builtin_amdgpu_ldexp", + "llvm.AMDGPU.ldexp.v2f64" => "__builtin_amdgpu_ldexp", + "llvm.AMDGPU.ldexp.v4f32" => "__builtin_amdgpu_ldexp", + "llvm.AMDGPU.rcp.f32" => "__builtin_amdgpu_rcp", + "llvm.AMDGPU.rcp.f64" => "__builtin_amdgpu_rcp", + "llvm.AMDGPU.rcp.v2f64" => "__builtin_amdgpu_rcp", + "llvm.AMDGPU.rcp.v4f32" => "__builtin_amdgpu_rcp", + "llvm.AMDGPU.rsq.clamped.f32" => "__builtin_amdgpu_rsq_clamped", + "llvm.AMDGPU.rsq.clamped.f64" => "__builtin_amdgpu_rsq_clamped", + "llvm.AMDGPU.rsq.clamped.v2f64" => "__builtin_amdgpu_rsq_clamped", + "llvm.AMDGPU.rsq.clamped.v4f32" => "__builtin_amdgpu_rsq_clamped", + "llvm.AMDGPU.rsq.f32" => "__builtin_amdgpu_rsq", + "llvm.AMDGPU.rsq.f64" => "__builtin_amdgpu_rsq", + "llvm.AMDGPU.rsq.v2f64" => "__builtin_amdgpu_rsq", + "llvm.AMDGPU.rsq.v4f32" => "__builtin_amdgpu_rsq", + "llvm.AMDGPU.trig.preop.f32" => "__builtin_amdgpu_trig_preop", + "llvm.AMDGPU.trig.preop.f64" => "__builtin_amdgpu_trig_preop", + "llvm.AMDGPU.trig.preop.v2f64" => "__builtin_amdgpu_trig_preop", + "llvm.AMDGPU.trig.preop.v4f32" => "__builtin_amdgpu_trig_preop", // aarch64 "llvm.aarch64.dmb" => "__builtin_arm_dmb", "llvm.aarch64.dsb" => "__builtin_arm_dsb", @@ -91,8 +120,8 @@ match name { "llvm.amdgcn.s.setprio" => "__builtin_amdgcn_s_setprio", "llvm.amdgcn.s.setreg" => "__builtin_amdgcn_s_setreg", "llvm.amdgcn.s.sleep" => "__builtin_amdgcn_s_decperflevel", - "llvm.amdgcn.s.sleep" => "__builtin_amdgcn_s_incperflevel", - "llvm.amdgcn.s.sleep" => "__builtin_amdgcn_s_sleep", + // [DUPLICATE]: "llvm.amdgcn.s.sleep" => "__builtin_amdgcn_s_incperflevel", + // [DUPLICATE]: "llvm.amdgcn.s.sleep" => "__builtin_amdgcn_s_sleep", "llvm.amdgcn.s.waitcnt" => "__builtin_amdgcn_s_waitcnt", "llvm.amdgcn.sad.hi.u8" => "__builtin_amdgcn_sad_hi_u8", "llvm.amdgcn.sad.u16" => "__builtin_amdgcn_sad_u16", @@ -123,6 +152,8 @@ match name { "llvm.arm.ldcl" => "__builtin_arm_ldcl", "llvm.arm.mcr" => "__builtin_arm_mcr", "llvm.arm.mcr2" => "__builtin_arm_mcr2", + "llvm.arm.mcrr" => "__builtin_arm_mcrr", + "llvm.arm.mcrr2" => "__builtin_arm_mcrr2", "llvm.arm.mrc" => "__builtin_arm_mrc", "llvm.arm.mrc2" => "__builtin_arm_mrc2", "llvm.arm.qadd" => "__builtin_arm_qadd", @@ -179,6 +210,7 @@ match name { "llvm.arm.stcl" => "__builtin_arm_stcl", "llvm.arm.sxtab16" => "__builtin_arm_sxtab16", "llvm.arm.sxtb16" => "__builtin_arm_sxtb16", + "llvm.arm.thread.pointer" => "__builtin_thread_pointer", "llvm.arm.uadd16" => "__builtin_arm_uadd16", "llvm.arm.uadd8" => "__builtin_arm_uadd8", "llvm.arm.uasx" => "__builtin_arm_uasx", @@ -214,6 +246,862 @@ match name { "llvm.bpf.preserve.field.info" => "__builtin_bpf_preserve_field_info", "llvm.bpf.preserve.type.info" => "__builtin_bpf_preserve_type_info", "llvm.bpf.pseudo" => "__builtin_bpf_pseudo", + // cuda + "llvm.cuda.syncthreads" => "__syncthreads", + // hexagon + "llvm.hexagon.A2.abs" => "__builtin_HEXAGON_A2_abs", + "llvm.hexagon.A2.absp" => "__builtin_HEXAGON_A2_absp", + "llvm.hexagon.A2.abssat" => "__builtin_HEXAGON_A2_abssat", + "llvm.hexagon.A2.add" => "__builtin_HEXAGON_A2_add", + "llvm.hexagon.A2.addh.h16.hh" => "__builtin_HEXAGON_A2_addh_h16_hh", + "llvm.hexagon.A2.addh.h16.hl" => "__builtin_HEXAGON_A2_addh_h16_hl", + "llvm.hexagon.A2.addh.h16.lh" => "__builtin_HEXAGON_A2_addh_h16_lh", + "llvm.hexagon.A2.addh.h16.ll" => "__builtin_HEXAGON_A2_addh_h16_ll", + "llvm.hexagon.A2.addh.h16.sat.hh" => "__builtin_HEXAGON_A2_addh_h16_sat_hh", + "llvm.hexagon.A2.addh.h16.sat.hl" => "__builtin_HEXAGON_A2_addh_h16_sat_hl", + "llvm.hexagon.A2.addh.h16.sat.lh" => "__builtin_HEXAGON_A2_addh_h16_sat_lh", + "llvm.hexagon.A2.addh.h16.sat.ll" => "__builtin_HEXAGON_A2_addh_h16_sat_ll", + "llvm.hexagon.A2.addh.l16.hl" => "__builtin_HEXAGON_A2_addh_l16_hl", + "llvm.hexagon.A2.addh.l16.ll" => "__builtin_HEXAGON_A2_addh_l16_ll", + "llvm.hexagon.A2.addh.l16.sat.hl" => "__builtin_HEXAGON_A2_addh_l16_sat_hl", + "llvm.hexagon.A2.addh.l16.sat.ll" => "__builtin_HEXAGON_A2_addh_l16_sat_ll", + "llvm.hexagon.A2.addi" => "__builtin_HEXAGON_A2_addi", + "llvm.hexagon.A2.addp" => "__builtin_HEXAGON_A2_addp", + "llvm.hexagon.A2.addpsat" => "__builtin_HEXAGON_A2_addpsat", + "llvm.hexagon.A2.addsat" => "__builtin_HEXAGON_A2_addsat", + "llvm.hexagon.A2.addsp" => "__builtin_HEXAGON_A2_addsp", + "llvm.hexagon.A2.and" => "__builtin_HEXAGON_A2_and", + "llvm.hexagon.A2.andir" => "__builtin_HEXAGON_A2_andir", + "llvm.hexagon.A2.andp" => "__builtin_HEXAGON_A2_andp", + "llvm.hexagon.A2.aslh" => "__builtin_HEXAGON_A2_aslh", + "llvm.hexagon.A2.asrh" => "__builtin_HEXAGON_A2_asrh", + "llvm.hexagon.A2.combine.hh" => "__builtin_HEXAGON_A2_combine_hh", + "llvm.hexagon.A2.combine.hl" => "__builtin_HEXAGON_A2_combine_hl", + "llvm.hexagon.A2.combine.lh" => "__builtin_HEXAGON_A2_combine_lh", + "llvm.hexagon.A2.combine.ll" => "__builtin_HEXAGON_A2_combine_ll", + "llvm.hexagon.A2.combineii" => "__builtin_HEXAGON_A2_combineii", + "llvm.hexagon.A2.combinew" => "__builtin_HEXAGON_A2_combinew", + "llvm.hexagon.A2.max" => "__builtin_HEXAGON_A2_max", + "llvm.hexagon.A2.maxp" => "__builtin_HEXAGON_A2_maxp", + "llvm.hexagon.A2.maxu" => "__builtin_HEXAGON_A2_maxu", + "llvm.hexagon.A2.maxup" => "__builtin_HEXAGON_A2_maxup", + "llvm.hexagon.A2.min" => "__builtin_HEXAGON_A2_min", + "llvm.hexagon.A2.minp" => "__builtin_HEXAGON_A2_minp", + "llvm.hexagon.A2.minu" => "__builtin_HEXAGON_A2_minu", + "llvm.hexagon.A2.minup" => "__builtin_HEXAGON_A2_minup", + "llvm.hexagon.A2.neg" => "__builtin_HEXAGON_A2_neg", + "llvm.hexagon.A2.negp" => "__builtin_HEXAGON_A2_negp", + "llvm.hexagon.A2.negsat" => "__builtin_HEXAGON_A2_negsat", + "llvm.hexagon.A2.not" => "__builtin_HEXAGON_A2_not", + "llvm.hexagon.A2.notp" => "__builtin_HEXAGON_A2_notp", + "llvm.hexagon.A2.or" => "__builtin_HEXAGON_A2_or", + "llvm.hexagon.A2.orir" => "__builtin_HEXAGON_A2_orir", + "llvm.hexagon.A2.orp" => "__builtin_HEXAGON_A2_orp", + "llvm.hexagon.A2.roundsat" => "__builtin_HEXAGON_A2_roundsat", + "llvm.hexagon.A2.sat" => "__builtin_HEXAGON_A2_sat", + "llvm.hexagon.A2.satb" => "__builtin_HEXAGON_A2_satb", + "llvm.hexagon.A2.sath" => "__builtin_HEXAGON_A2_sath", + "llvm.hexagon.A2.satub" => "__builtin_HEXAGON_A2_satub", + "llvm.hexagon.A2.satuh" => "__builtin_HEXAGON_A2_satuh", + "llvm.hexagon.A2.sub" => "__builtin_HEXAGON_A2_sub", + "llvm.hexagon.A2.subh.h16.hh" => "__builtin_HEXAGON_A2_subh_h16_hh", + "llvm.hexagon.A2.subh.h16.hl" => "__builtin_HEXAGON_A2_subh_h16_hl", + "llvm.hexagon.A2.subh.h16.lh" => "__builtin_HEXAGON_A2_subh_h16_lh", + "llvm.hexagon.A2.subh.h16.ll" => "__builtin_HEXAGON_A2_subh_h16_ll", + "llvm.hexagon.A2.subh.h16.sat.hh" => "__builtin_HEXAGON_A2_subh_h16_sat_hh", + "llvm.hexagon.A2.subh.h16.sat.hl" => "__builtin_HEXAGON_A2_subh_h16_sat_hl", + "llvm.hexagon.A2.subh.h16.sat.lh" => "__builtin_HEXAGON_A2_subh_h16_sat_lh", + "llvm.hexagon.A2.subh.h16.sat.ll" => "__builtin_HEXAGON_A2_subh_h16_sat_ll", + "llvm.hexagon.A2.subh.l16.hl" => "__builtin_HEXAGON_A2_subh_l16_hl", + "llvm.hexagon.A2.subh.l16.ll" => "__builtin_HEXAGON_A2_subh_l16_ll", + "llvm.hexagon.A2.subh.l16.sat.hl" => "__builtin_HEXAGON_A2_subh_l16_sat_hl", + "llvm.hexagon.A2.subh.l16.sat.ll" => "__builtin_HEXAGON_A2_subh_l16_sat_ll", + "llvm.hexagon.A2.subp" => "__builtin_HEXAGON_A2_subp", + "llvm.hexagon.A2.subri" => "__builtin_HEXAGON_A2_subri", + "llvm.hexagon.A2.subsat" => "__builtin_HEXAGON_A2_subsat", + "llvm.hexagon.A2.svaddh" => "__builtin_HEXAGON_A2_svaddh", + "llvm.hexagon.A2.svaddhs" => "__builtin_HEXAGON_A2_svaddhs", + "llvm.hexagon.A2.svadduhs" => "__builtin_HEXAGON_A2_svadduhs", + "llvm.hexagon.A2.svavgh" => "__builtin_HEXAGON_A2_svavgh", + "llvm.hexagon.A2.svavghs" => "__builtin_HEXAGON_A2_svavghs", + "llvm.hexagon.A2.svnavgh" => "__builtin_HEXAGON_A2_svnavgh", + "llvm.hexagon.A2.svsubh" => "__builtin_HEXAGON_A2_svsubh", + "llvm.hexagon.A2.svsubhs" => "__builtin_HEXAGON_A2_svsubhs", + "llvm.hexagon.A2.svsubuhs" => "__builtin_HEXAGON_A2_svsubuhs", + "llvm.hexagon.A2.swiz" => "__builtin_HEXAGON_A2_swiz", + "llvm.hexagon.A2.sxtb" => "__builtin_HEXAGON_A2_sxtb", + "llvm.hexagon.A2.sxth" => "__builtin_HEXAGON_A2_sxth", + "llvm.hexagon.A2.sxtw" => "__builtin_HEXAGON_A2_sxtw", + "llvm.hexagon.A2.tfr" => "__builtin_HEXAGON_A2_tfr", + "llvm.hexagon.A2.tfrih" => "__builtin_HEXAGON_A2_tfrih", + "llvm.hexagon.A2.tfril" => "__builtin_HEXAGON_A2_tfril", + "llvm.hexagon.A2.tfrp" => "__builtin_HEXAGON_A2_tfrp", + "llvm.hexagon.A2.tfrpi" => "__builtin_HEXAGON_A2_tfrpi", + "llvm.hexagon.A2.tfrsi" => "__builtin_HEXAGON_A2_tfrsi", + "llvm.hexagon.A2.vabsh" => "__builtin_HEXAGON_A2_vabsh", + "llvm.hexagon.A2.vabshsat" => "__builtin_HEXAGON_A2_vabshsat", + "llvm.hexagon.A2.vabsw" => "__builtin_HEXAGON_A2_vabsw", + "llvm.hexagon.A2.vabswsat" => "__builtin_HEXAGON_A2_vabswsat", + "llvm.hexagon.A2.vaddb.map" => "__builtin_HEXAGON_A2_vaddb_map", + "llvm.hexagon.A2.vaddh" => "__builtin_HEXAGON_A2_vaddh", + "llvm.hexagon.A2.vaddhs" => "__builtin_HEXAGON_A2_vaddhs", + "llvm.hexagon.A2.vaddub" => "__builtin_HEXAGON_A2_vaddub", + "llvm.hexagon.A2.vaddubs" => "__builtin_HEXAGON_A2_vaddubs", + "llvm.hexagon.A2.vadduhs" => "__builtin_HEXAGON_A2_vadduhs", + "llvm.hexagon.A2.vaddw" => "__builtin_HEXAGON_A2_vaddw", + "llvm.hexagon.A2.vaddws" => "__builtin_HEXAGON_A2_vaddws", + "llvm.hexagon.A2.vavgh" => "__builtin_HEXAGON_A2_vavgh", + "llvm.hexagon.A2.vavghcr" => "__builtin_HEXAGON_A2_vavghcr", + "llvm.hexagon.A2.vavghr" => "__builtin_HEXAGON_A2_vavghr", + "llvm.hexagon.A2.vavgub" => "__builtin_HEXAGON_A2_vavgub", + "llvm.hexagon.A2.vavgubr" => "__builtin_HEXAGON_A2_vavgubr", + "llvm.hexagon.A2.vavguh" => "__builtin_HEXAGON_A2_vavguh", + "llvm.hexagon.A2.vavguhr" => "__builtin_HEXAGON_A2_vavguhr", + "llvm.hexagon.A2.vavguw" => "__builtin_HEXAGON_A2_vavguw", + "llvm.hexagon.A2.vavguwr" => "__builtin_HEXAGON_A2_vavguwr", + "llvm.hexagon.A2.vavgw" => "__builtin_HEXAGON_A2_vavgw", + "llvm.hexagon.A2.vavgwcr" => "__builtin_HEXAGON_A2_vavgwcr", + "llvm.hexagon.A2.vavgwr" => "__builtin_HEXAGON_A2_vavgwr", + "llvm.hexagon.A2.vcmpbeq" => "__builtin_HEXAGON_A2_vcmpbeq", + "llvm.hexagon.A2.vcmpbgtu" => "__builtin_HEXAGON_A2_vcmpbgtu", + "llvm.hexagon.A2.vcmpheq" => "__builtin_HEXAGON_A2_vcmpheq", + "llvm.hexagon.A2.vcmphgt" => "__builtin_HEXAGON_A2_vcmphgt", + "llvm.hexagon.A2.vcmphgtu" => "__builtin_HEXAGON_A2_vcmphgtu", + "llvm.hexagon.A2.vcmpweq" => "__builtin_HEXAGON_A2_vcmpweq", + "llvm.hexagon.A2.vcmpwgt" => "__builtin_HEXAGON_A2_vcmpwgt", + "llvm.hexagon.A2.vcmpwgtu" => "__builtin_HEXAGON_A2_vcmpwgtu", + "llvm.hexagon.A2.vconj" => "__builtin_HEXAGON_A2_vconj", + "llvm.hexagon.A2.vmaxb" => "__builtin_HEXAGON_A2_vmaxb", + "llvm.hexagon.A2.vmaxh" => "__builtin_HEXAGON_A2_vmaxh", + "llvm.hexagon.A2.vmaxub" => "__builtin_HEXAGON_A2_vmaxub", + "llvm.hexagon.A2.vmaxuh" => "__builtin_HEXAGON_A2_vmaxuh", + "llvm.hexagon.A2.vmaxuw" => "__builtin_HEXAGON_A2_vmaxuw", + "llvm.hexagon.A2.vmaxw" => "__builtin_HEXAGON_A2_vmaxw", + "llvm.hexagon.A2.vminb" => "__builtin_HEXAGON_A2_vminb", + "llvm.hexagon.A2.vminh" => "__builtin_HEXAGON_A2_vminh", + "llvm.hexagon.A2.vminub" => "__builtin_HEXAGON_A2_vminub", + "llvm.hexagon.A2.vminuh" => "__builtin_HEXAGON_A2_vminuh", + "llvm.hexagon.A2.vminuw" => "__builtin_HEXAGON_A2_vminuw", + "llvm.hexagon.A2.vminw" => "__builtin_HEXAGON_A2_vminw", + "llvm.hexagon.A2.vnavgh" => "__builtin_HEXAGON_A2_vnavgh", + "llvm.hexagon.A2.vnavghcr" => "__builtin_HEXAGON_A2_vnavghcr", + "llvm.hexagon.A2.vnavghr" => "__builtin_HEXAGON_A2_vnavghr", + "llvm.hexagon.A2.vnavgw" => "__builtin_HEXAGON_A2_vnavgw", + "llvm.hexagon.A2.vnavgwcr" => "__builtin_HEXAGON_A2_vnavgwcr", + "llvm.hexagon.A2.vnavgwr" => "__builtin_HEXAGON_A2_vnavgwr", + "llvm.hexagon.A2.vraddub" => "__builtin_HEXAGON_A2_vraddub", + "llvm.hexagon.A2.vraddub.acc" => "__builtin_HEXAGON_A2_vraddub_acc", + "llvm.hexagon.A2.vrsadub" => "__builtin_HEXAGON_A2_vrsadub", + "llvm.hexagon.A2.vrsadub.acc" => "__builtin_HEXAGON_A2_vrsadub_acc", + "llvm.hexagon.A2.vsubb.map" => "__builtin_HEXAGON_A2_vsubb_map", + "llvm.hexagon.A2.vsubh" => "__builtin_HEXAGON_A2_vsubh", + "llvm.hexagon.A2.vsubhs" => "__builtin_HEXAGON_A2_vsubhs", + "llvm.hexagon.A2.vsubub" => "__builtin_HEXAGON_A2_vsubub", + "llvm.hexagon.A2.vsububs" => "__builtin_HEXAGON_A2_vsububs", + "llvm.hexagon.A2.vsubuhs" => "__builtin_HEXAGON_A2_vsubuhs", + "llvm.hexagon.A2.vsubw" => "__builtin_HEXAGON_A2_vsubw", + "llvm.hexagon.A2.vsubws" => "__builtin_HEXAGON_A2_vsubws", + "llvm.hexagon.A2.xor" => "__builtin_HEXAGON_A2_xor", + "llvm.hexagon.A2.xorp" => "__builtin_HEXAGON_A2_xorp", + "llvm.hexagon.A2.zxtb" => "__builtin_HEXAGON_A2_zxtb", + "llvm.hexagon.A2.zxth" => "__builtin_HEXAGON_A2_zxth", + "llvm.hexagon.A4.andn" => "__builtin_HEXAGON_A4_andn", + "llvm.hexagon.A4.andnp" => "__builtin_HEXAGON_A4_andnp", + "llvm.hexagon.A4.bitsplit" => "__builtin_HEXAGON_A4_bitsplit", + "llvm.hexagon.A4.bitspliti" => "__builtin_HEXAGON_A4_bitspliti", + "llvm.hexagon.A4.boundscheck" => "__builtin_HEXAGON_A4_boundscheck", + "llvm.hexagon.A4.cmpbeq" => "__builtin_HEXAGON_A4_cmpbeq", + "llvm.hexagon.A4.cmpbeqi" => "__builtin_HEXAGON_A4_cmpbeqi", + "llvm.hexagon.A4.cmpbgt" => "__builtin_HEXAGON_A4_cmpbgt", + "llvm.hexagon.A4.cmpbgti" => "__builtin_HEXAGON_A4_cmpbgti", + "llvm.hexagon.A4.cmpbgtu" => "__builtin_HEXAGON_A4_cmpbgtu", + "llvm.hexagon.A4.cmpbgtui" => "__builtin_HEXAGON_A4_cmpbgtui", + "llvm.hexagon.A4.cmpheq" => "__builtin_HEXAGON_A4_cmpheq", + "llvm.hexagon.A4.cmpheqi" => "__builtin_HEXAGON_A4_cmpheqi", + "llvm.hexagon.A4.cmphgt" => "__builtin_HEXAGON_A4_cmphgt", + "llvm.hexagon.A4.cmphgti" => "__builtin_HEXAGON_A4_cmphgti", + "llvm.hexagon.A4.cmphgtu" => "__builtin_HEXAGON_A4_cmphgtu", + "llvm.hexagon.A4.cmphgtui" => "__builtin_HEXAGON_A4_cmphgtui", + "llvm.hexagon.A4.combineir" => "__builtin_HEXAGON_A4_combineir", + "llvm.hexagon.A4.combineri" => "__builtin_HEXAGON_A4_combineri", + "llvm.hexagon.A4.cround.ri" => "__builtin_HEXAGON_A4_cround_ri", + "llvm.hexagon.A4.cround.rr" => "__builtin_HEXAGON_A4_cround_rr", + "llvm.hexagon.A4.modwrapu" => "__builtin_HEXAGON_A4_modwrapu", + "llvm.hexagon.A4.orn" => "__builtin_HEXAGON_A4_orn", + "llvm.hexagon.A4.ornp" => "__builtin_HEXAGON_A4_ornp", + "llvm.hexagon.A4.rcmpeq" => "__builtin_HEXAGON_A4_rcmpeq", + "llvm.hexagon.A4.rcmpeqi" => "__builtin_HEXAGON_A4_rcmpeqi", + "llvm.hexagon.A4.rcmpneq" => "__builtin_HEXAGON_A4_rcmpneq", + "llvm.hexagon.A4.rcmpneqi" => "__builtin_HEXAGON_A4_rcmpneqi", + "llvm.hexagon.A4.round.ri" => "__builtin_HEXAGON_A4_round_ri", + "llvm.hexagon.A4.round.ri.sat" => "__builtin_HEXAGON_A4_round_ri_sat", + "llvm.hexagon.A4.round.rr" => "__builtin_HEXAGON_A4_round_rr", + "llvm.hexagon.A4.round.rr.sat" => "__builtin_HEXAGON_A4_round_rr_sat", + "llvm.hexagon.A4.tlbmatch" => "__builtin_HEXAGON_A4_tlbmatch", + "llvm.hexagon.A4.vcmpbeq.any" => "__builtin_HEXAGON_A4_vcmpbeq_any", + "llvm.hexagon.A4.vcmpbeqi" => "__builtin_HEXAGON_A4_vcmpbeqi", + "llvm.hexagon.A4.vcmpbgt" => "__builtin_HEXAGON_A4_vcmpbgt", + "llvm.hexagon.A4.vcmpbgti" => "__builtin_HEXAGON_A4_vcmpbgti", + "llvm.hexagon.A4.vcmpbgtui" => "__builtin_HEXAGON_A4_vcmpbgtui", + "llvm.hexagon.A4.vcmpheqi" => "__builtin_HEXAGON_A4_vcmpheqi", + "llvm.hexagon.A4.vcmphgti" => "__builtin_HEXAGON_A4_vcmphgti", + "llvm.hexagon.A4.vcmphgtui" => "__builtin_HEXAGON_A4_vcmphgtui", + "llvm.hexagon.A4.vcmpweqi" => "__builtin_HEXAGON_A4_vcmpweqi", + "llvm.hexagon.A4.vcmpwgti" => "__builtin_HEXAGON_A4_vcmpwgti", + "llvm.hexagon.A4.vcmpwgtui" => "__builtin_HEXAGON_A4_vcmpwgtui", + "llvm.hexagon.A4.vrmaxh" => "__builtin_HEXAGON_A4_vrmaxh", + "llvm.hexagon.A4.vrmaxuh" => "__builtin_HEXAGON_A4_vrmaxuh", + "llvm.hexagon.A4.vrmaxuw" => "__builtin_HEXAGON_A4_vrmaxuw", + "llvm.hexagon.A4.vrmaxw" => "__builtin_HEXAGON_A4_vrmaxw", + "llvm.hexagon.A4.vrminh" => "__builtin_HEXAGON_A4_vrminh", + "llvm.hexagon.A4.vrminuh" => "__builtin_HEXAGON_A4_vrminuh", + "llvm.hexagon.A4.vrminuw" => "__builtin_HEXAGON_A4_vrminuw", + "llvm.hexagon.A4.vrminw" => "__builtin_HEXAGON_A4_vrminw", + "llvm.hexagon.A5.vaddhubs" => "__builtin_HEXAGON_A5_vaddhubs", + "llvm.hexagon.C2.all8" => "__builtin_HEXAGON_C2_all8", + "llvm.hexagon.C2.and" => "__builtin_HEXAGON_C2_and", + "llvm.hexagon.C2.andn" => "__builtin_HEXAGON_C2_andn", + "llvm.hexagon.C2.any8" => "__builtin_HEXAGON_C2_any8", + "llvm.hexagon.C2.bitsclr" => "__builtin_HEXAGON_C2_bitsclr", + "llvm.hexagon.C2.bitsclri" => "__builtin_HEXAGON_C2_bitsclri", + "llvm.hexagon.C2.bitsset" => "__builtin_HEXAGON_C2_bitsset", + "llvm.hexagon.C2.cmpeq" => "__builtin_HEXAGON_C2_cmpeq", + "llvm.hexagon.C2.cmpeqi" => "__builtin_HEXAGON_C2_cmpeqi", + "llvm.hexagon.C2.cmpeqp" => "__builtin_HEXAGON_C2_cmpeqp", + "llvm.hexagon.C2.cmpgei" => "__builtin_HEXAGON_C2_cmpgei", + "llvm.hexagon.C2.cmpgeui" => "__builtin_HEXAGON_C2_cmpgeui", + "llvm.hexagon.C2.cmpgt" => "__builtin_HEXAGON_C2_cmpgt", + "llvm.hexagon.C2.cmpgti" => "__builtin_HEXAGON_C2_cmpgti", + "llvm.hexagon.C2.cmpgtp" => "__builtin_HEXAGON_C2_cmpgtp", + "llvm.hexagon.C2.cmpgtu" => "__builtin_HEXAGON_C2_cmpgtu", + "llvm.hexagon.C2.cmpgtui" => "__builtin_HEXAGON_C2_cmpgtui", + "llvm.hexagon.C2.cmpgtup" => "__builtin_HEXAGON_C2_cmpgtup", + "llvm.hexagon.C2.cmplt" => "__builtin_HEXAGON_C2_cmplt", + "llvm.hexagon.C2.cmpltu" => "__builtin_HEXAGON_C2_cmpltu", + "llvm.hexagon.C2.mask" => "__builtin_HEXAGON_C2_mask", + "llvm.hexagon.C2.mux" => "__builtin_HEXAGON_C2_mux", + "llvm.hexagon.C2.muxii" => "__builtin_HEXAGON_C2_muxii", + "llvm.hexagon.C2.muxir" => "__builtin_HEXAGON_C2_muxir", + "llvm.hexagon.C2.muxri" => "__builtin_HEXAGON_C2_muxri", + "llvm.hexagon.C2.not" => "__builtin_HEXAGON_C2_not", + "llvm.hexagon.C2.or" => "__builtin_HEXAGON_C2_or", + "llvm.hexagon.C2.orn" => "__builtin_HEXAGON_C2_orn", + "llvm.hexagon.C2.pxfer.map" => "__builtin_HEXAGON_C2_pxfer_map", + "llvm.hexagon.C2.tfrpr" => "__builtin_HEXAGON_C2_tfrpr", + "llvm.hexagon.C2.tfrrp" => "__builtin_HEXAGON_C2_tfrrp", + "llvm.hexagon.C2.vitpack" => "__builtin_HEXAGON_C2_vitpack", + "llvm.hexagon.C2.vmux" => "__builtin_HEXAGON_C2_vmux", + "llvm.hexagon.C2.xor" => "__builtin_HEXAGON_C2_xor", + "llvm.hexagon.C4.and.and" => "__builtin_HEXAGON_C4_and_and", + "llvm.hexagon.C4.and.andn" => "__builtin_HEXAGON_C4_and_andn", + "llvm.hexagon.C4.and.or" => "__builtin_HEXAGON_C4_and_or", + "llvm.hexagon.C4.and.orn" => "__builtin_HEXAGON_C4_and_orn", + "llvm.hexagon.C4.cmplte" => "__builtin_HEXAGON_C4_cmplte", + "llvm.hexagon.C4.cmpltei" => "__builtin_HEXAGON_C4_cmpltei", + "llvm.hexagon.C4.cmplteu" => "__builtin_HEXAGON_C4_cmplteu", + "llvm.hexagon.C4.cmplteui" => "__builtin_HEXAGON_C4_cmplteui", + "llvm.hexagon.C4.cmpneq" => "__builtin_HEXAGON_C4_cmpneq", + "llvm.hexagon.C4.cmpneqi" => "__builtin_HEXAGON_C4_cmpneqi", + "llvm.hexagon.C4.fastcorner9" => "__builtin_HEXAGON_C4_fastcorner9", + "llvm.hexagon.C4.fastcorner9.not" => "__builtin_HEXAGON_C4_fastcorner9_not", + "llvm.hexagon.C4.nbitsclr" => "__builtin_HEXAGON_C4_nbitsclr", + "llvm.hexagon.C4.nbitsclri" => "__builtin_HEXAGON_C4_nbitsclri", + "llvm.hexagon.C4.nbitsset" => "__builtin_HEXAGON_C4_nbitsset", + "llvm.hexagon.C4.or.and" => "__builtin_HEXAGON_C4_or_and", + "llvm.hexagon.C4.or.andn" => "__builtin_HEXAGON_C4_or_andn", + "llvm.hexagon.C4.or.or" => "__builtin_HEXAGON_C4_or_or", + "llvm.hexagon.C4.or.orn" => "__builtin_HEXAGON_C4_or_orn", + "llvm.hexagon.F2.conv.d2df" => "__builtin_HEXAGON_F2_conv_d2df", + "llvm.hexagon.F2.conv.d2sf" => "__builtin_HEXAGON_F2_conv_d2sf", + "llvm.hexagon.F2.conv.df2d" => "__builtin_HEXAGON_F2_conv_df2d", + "llvm.hexagon.F2.conv.df2d.chop" => "__builtin_HEXAGON_F2_conv_df2d_chop", + "llvm.hexagon.F2.conv.df2sf" => "__builtin_HEXAGON_F2_conv_df2sf", + "llvm.hexagon.F2.conv.df2ud" => "__builtin_HEXAGON_F2_conv_df2ud", + "llvm.hexagon.F2.conv.df2ud.chop" => "__builtin_HEXAGON_F2_conv_df2ud_chop", + "llvm.hexagon.F2.conv.df2uw" => "__builtin_HEXAGON_F2_conv_df2uw", + "llvm.hexagon.F2.conv.df2uw.chop" => "__builtin_HEXAGON_F2_conv_df2uw_chop", + "llvm.hexagon.F2.conv.df2w" => "__builtin_HEXAGON_F2_conv_df2w", + "llvm.hexagon.F2.conv.df2w.chop" => "__builtin_HEXAGON_F2_conv_df2w_chop", + "llvm.hexagon.F2.conv.sf2d" => "__builtin_HEXAGON_F2_conv_sf2d", + "llvm.hexagon.F2.conv.sf2d.chop" => "__builtin_HEXAGON_F2_conv_sf2d_chop", + "llvm.hexagon.F2.conv.sf2df" => "__builtin_HEXAGON_F2_conv_sf2df", + "llvm.hexagon.F2.conv.sf2ud" => "__builtin_HEXAGON_F2_conv_sf2ud", + "llvm.hexagon.F2.conv.sf2ud.chop" => "__builtin_HEXAGON_F2_conv_sf2ud_chop", + "llvm.hexagon.F2.conv.sf2uw" => "__builtin_HEXAGON_F2_conv_sf2uw", + "llvm.hexagon.F2.conv.sf2uw.chop" => "__builtin_HEXAGON_F2_conv_sf2uw_chop", + "llvm.hexagon.F2.conv.sf2w" => "__builtin_HEXAGON_F2_conv_sf2w", + "llvm.hexagon.F2.conv.sf2w.chop" => "__builtin_HEXAGON_F2_conv_sf2w_chop", + "llvm.hexagon.F2.conv.ud2df" => "__builtin_HEXAGON_F2_conv_ud2df", + "llvm.hexagon.F2.conv.ud2sf" => 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"llvm.hexagon.M2.mpy.nac.sat.hh.s1" => "__builtin_HEXAGON_M2_mpy_nac_sat_hh_s1", + "llvm.hexagon.M2.mpy.nac.sat.hl.s0" => "__builtin_HEXAGON_M2_mpy_nac_sat_hl_s0", + "llvm.hexagon.M2.mpy.nac.sat.hl.s1" => "__builtin_HEXAGON_M2_mpy_nac_sat_hl_s1", + "llvm.hexagon.M2.mpy.nac.sat.lh.s0" => "__builtin_HEXAGON_M2_mpy_nac_sat_lh_s0", + "llvm.hexagon.M2.mpy.nac.sat.lh.s1" => "__builtin_HEXAGON_M2_mpy_nac_sat_lh_s1", + "llvm.hexagon.M2.mpy.nac.sat.ll.s0" => "__builtin_HEXAGON_M2_mpy_nac_sat_ll_s0", + "llvm.hexagon.M2.mpy.nac.sat.ll.s1" => "__builtin_HEXAGON_M2_mpy_nac_sat_ll_s1", + "llvm.hexagon.M2.mpy.rnd.hh.s0" => "__builtin_HEXAGON_M2_mpy_rnd_hh_s0", + "llvm.hexagon.M2.mpy.rnd.hh.s1" => "__builtin_HEXAGON_M2_mpy_rnd_hh_s1", + "llvm.hexagon.M2.mpy.rnd.hl.s0" => "__builtin_HEXAGON_M2_mpy_rnd_hl_s0", + "llvm.hexagon.M2.mpy.rnd.hl.s1" => "__builtin_HEXAGON_M2_mpy_rnd_hl_s1", + "llvm.hexagon.M2.mpy.rnd.lh.s0" => "__builtin_HEXAGON_M2_mpy_rnd_lh_s0", + "llvm.hexagon.M2.mpy.rnd.lh.s1" => "__builtin_HEXAGON_M2_mpy_rnd_lh_s1", + "llvm.hexagon.M2.mpy.rnd.ll.s0" => "__builtin_HEXAGON_M2_mpy_rnd_ll_s0", + "llvm.hexagon.M2.mpy.rnd.ll.s1" => "__builtin_HEXAGON_M2_mpy_rnd_ll_s1", + "llvm.hexagon.M2.mpy.sat.hh.s0" => "__builtin_HEXAGON_M2_mpy_sat_hh_s0", + "llvm.hexagon.M2.mpy.sat.hh.s1" => "__builtin_HEXAGON_M2_mpy_sat_hh_s1", + "llvm.hexagon.M2.mpy.sat.hl.s0" => "__builtin_HEXAGON_M2_mpy_sat_hl_s0", + "llvm.hexagon.M2.mpy.sat.hl.s1" => "__builtin_HEXAGON_M2_mpy_sat_hl_s1", + "llvm.hexagon.M2.mpy.sat.lh.s0" => "__builtin_HEXAGON_M2_mpy_sat_lh_s0", + "llvm.hexagon.M2.mpy.sat.lh.s1" => "__builtin_HEXAGON_M2_mpy_sat_lh_s1", + "llvm.hexagon.M2.mpy.sat.ll.s0" => "__builtin_HEXAGON_M2_mpy_sat_ll_s0", + "llvm.hexagon.M2.mpy.sat.ll.s1" => "__builtin_HEXAGON_M2_mpy_sat_ll_s1", + "llvm.hexagon.M2.mpy.sat.rnd.hh.s0" => "__builtin_HEXAGON_M2_mpy_sat_rnd_hh_s0", + "llvm.hexagon.M2.mpy.sat.rnd.hh.s1" => "__builtin_HEXAGON_M2_mpy_sat_rnd_hh_s1", + "llvm.hexagon.M2.mpy.sat.rnd.hl.s0" => "__builtin_HEXAGON_M2_mpy_sat_rnd_hl_s0", + "llvm.hexagon.M2.mpy.sat.rnd.hl.s1" => "__builtin_HEXAGON_M2_mpy_sat_rnd_hl_s1", + "llvm.hexagon.M2.mpy.sat.rnd.lh.s0" => "__builtin_HEXAGON_M2_mpy_sat_rnd_lh_s0", + "llvm.hexagon.M2.mpy.sat.rnd.lh.s1" => "__builtin_HEXAGON_M2_mpy_sat_rnd_lh_s1", + "llvm.hexagon.M2.mpy.sat.rnd.ll.s0" => "__builtin_HEXAGON_M2_mpy_sat_rnd_ll_s0", + "llvm.hexagon.M2.mpy.sat.rnd.ll.s1" => "__builtin_HEXAGON_M2_mpy_sat_rnd_ll_s1", + "llvm.hexagon.M2.mpy.up" => "__builtin_HEXAGON_M2_mpy_up", + "llvm.hexagon.M2.mpy.up.s1" => "__builtin_HEXAGON_M2_mpy_up_s1", + "llvm.hexagon.M2.mpy.up.s1.sat" => "__builtin_HEXAGON_M2_mpy_up_s1_sat", + "llvm.hexagon.M2.mpyd.acc.hh.s0" => "__builtin_HEXAGON_M2_mpyd_acc_hh_s0", + "llvm.hexagon.M2.mpyd.acc.hh.s1" => "__builtin_HEXAGON_M2_mpyd_acc_hh_s1", + "llvm.hexagon.M2.mpyd.acc.hl.s0" => "__builtin_HEXAGON_M2_mpyd_acc_hl_s0", + "llvm.hexagon.M2.mpyd.acc.hl.s1" => "__builtin_HEXAGON_M2_mpyd_acc_hl_s1", + "llvm.hexagon.M2.mpyd.acc.lh.s0" => "__builtin_HEXAGON_M2_mpyd_acc_lh_s0", + "llvm.hexagon.M2.mpyd.acc.lh.s1" => "__builtin_HEXAGON_M2_mpyd_acc_lh_s1", + "llvm.hexagon.M2.mpyd.acc.ll.s0" => "__builtin_HEXAGON_M2_mpyd_acc_ll_s0", + "llvm.hexagon.M2.mpyd.acc.ll.s1" => "__builtin_HEXAGON_M2_mpyd_acc_ll_s1", + "llvm.hexagon.M2.mpyd.hh.s0" => "__builtin_HEXAGON_M2_mpyd_hh_s0", + "llvm.hexagon.M2.mpyd.hh.s1" => "__builtin_HEXAGON_M2_mpyd_hh_s1", + "llvm.hexagon.M2.mpyd.hl.s0" => "__builtin_HEXAGON_M2_mpyd_hl_s0", + "llvm.hexagon.M2.mpyd.hl.s1" => "__builtin_HEXAGON_M2_mpyd_hl_s1", + "llvm.hexagon.M2.mpyd.lh.s0" => "__builtin_HEXAGON_M2_mpyd_lh_s0", + "llvm.hexagon.M2.mpyd.lh.s1" => "__builtin_HEXAGON_M2_mpyd_lh_s1", + "llvm.hexagon.M2.mpyd.ll.s0" => "__builtin_HEXAGON_M2_mpyd_ll_s0", + "llvm.hexagon.M2.mpyd.ll.s1" => "__builtin_HEXAGON_M2_mpyd_ll_s1", + "llvm.hexagon.M2.mpyd.nac.hh.s0" => "__builtin_HEXAGON_M2_mpyd_nac_hh_s0", + "llvm.hexagon.M2.mpyd.nac.hh.s1" => "__builtin_HEXAGON_M2_mpyd_nac_hh_s1", + "llvm.hexagon.M2.mpyd.nac.hl.s0" => "__builtin_HEXAGON_M2_mpyd_nac_hl_s0", + "llvm.hexagon.M2.mpyd.nac.hl.s1" => "__builtin_HEXAGON_M2_mpyd_nac_hl_s1", + "llvm.hexagon.M2.mpyd.nac.lh.s0" => "__builtin_HEXAGON_M2_mpyd_nac_lh_s0", + "llvm.hexagon.M2.mpyd.nac.lh.s1" => "__builtin_HEXAGON_M2_mpyd_nac_lh_s1", + "llvm.hexagon.M2.mpyd.nac.ll.s0" => "__builtin_HEXAGON_M2_mpyd_nac_ll_s0", + "llvm.hexagon.M2.mpyd.nac.ll.s1" => "__builtin_HEXAGON_M2_mpyd_nac_ll_s1", + "llvm.hexagon.M2.mpyd.rnd.hh.s0" => "__builtin_HEXAGON_M2_mpyd_rnd_hh_s0", + "llvm.hexagon.M2.mpyd.rnd.hh.s1" => "__builtin_HEXAGON_M2_mpyd_rnd_hh_s1", + "llvm.hexagon.M2.mpyd.rnd.hl.s0" => "__builtin_HEXAGON_M2_mpyd_rnd_hl_s0", + "llvm.hexagon.M2.mpyd.rnd.hl.s1" => "__builtin_HEXAGON_M2_mpyd_rnd_hl_s1", + "llvm.hexagon.M2.mpyd.rnd.lh.s0" => "__builtin_HEXAGON_M2_mpyd_rnd_lh_s0", + "llvm.hexagon.M2.mpyd.rnd.lh.s1" => "__builtin_HEXAGON_M2_mpyd_rnd_lh_s1", + "llvm.hexagon.M2.mpyd.rnd.ll.s0" => "__builtin_HEXAGON_M2_mpyd_rnd_ll_s0", + "llvm.hexagon.M2.mpyd.rnd.ll.s1" => "__builtin_HEXAGON_M2_mpyd_rnd_ll_s1", + "llvm.hexagon.M2.mpyi" => "__builtin_HEXAGON_M2_mpyi", + "llvm.hexagon.M2.mpysmi" => "__builtin_HEXAGON_M2_mpysmi", + "llvm.hexagon.M2.mpysu.up" => "__builtin_HEXAGON_M2_mpysu_up", + "llvm.hexagon.M2.mpyu.acc.hh.s0" => "__builtin_HEXAGON_M2_mpyu_acc_hh_s0", + "llvm.hexagon.M2.mpyu.acc.hh.s1" => "__builtin_HEXAGON_M2_mpyu_acc_hh_s1", + "llvm.hexagon.M2.mpyu.acc.hl.s0" => "__builtin_HEXAGON_M2_mpyu_acc_hl_s0", + "llvm.hexagon.M2.mpyu.acc.hl.s1" => "__builtin_HEXAGON_M2_mpyu_acc_hl_s1", + "llvm.hexagon.M2.mpyu.acc.lh.s0" => "__builtin_HEXAGON_M2_mpyu_acc_lh_s0", + "llvm.hexagon.M2.mpyu.acc.lh.s1" => "__builtin_HEXAGON_M2_mpyu_acc_lh_s1", + "llvm.hexagon.M2.mpyu.acc.ll.s0" => "__builtin_HEXAGON_M2_mpyu_acc_ll_s0", + "llvm.hexagon.M2.mpyu.acc.ll.s1" => "__builtin_HEXAGON_M2_mpyu_acc_ll_s1", + "llvm.hexagon.M2.mpyu.hh.s0" => "__builtin_HEXAGON_M2_mpyu_hh_s0", + "llvm.hexagon.M2.mpyu.hh.s1" => "__builtin_HEXAGON_M2_mpyu_hh_s1", + "llvm.hexagon.M2.mpyu.hl.s0" => "__builtin_HEXAGON_M2_mpyu_hl_s0", + "llvm.hexagon.M2.mpyu.hl.s1" => "__builtin_HEXAGON_M2_mpyu_hl_s1", + "llvm.hexagon.M2.mpyu.lh.s0" => "__builtin_HEXAGON_M2_mpyu_lh_s0", + "llvm.hexagon.M2.mpyu.lh.s1" => "__builtin_HEXAGON_M2_mpyu_lh_s1", + "llvm.hexagon.M2.mpyu.ll.s0" => "__builtin_HEXAGON_M2_mpyu_ll_s0", + "llvm.hexagon.M2.mpyu.ll.s1" => "__builtin_HEXAGON_M2_mpyu_ll_s1", + "llvm.hexagon.M2.mpyu.nac.hh.s0" => "__builtin_HEXAGON_M2_mpyu_nac_hh_s0", + "llvm.hexagon.M2.mpyu.nac.hh.s1" => "__builtin_HEXAGON_M2_mpyu_nac_hh_s1", + "llvm.hexagon.M2.mpyu.nac.hl.s0" => "__builtin_HEXAGON_M2_mpyu_nac_hl_s0", + "llvm.hexagon.M2.mpyu.nac.hl.s1" => "__builtin_HEXAGON_M2_mpyu_nac_hl_s1", + "llvm.hexagon.M2.mpyu.nac.lh.s0" => "__builtin_HEXAGON_M2_mpyu_nac_lh_s0", + "llvm.hexagon.M2.mpyu.nac.lh.s1" => "__builtin_HEXAGON_M2_mpyu_nac_lh_s1", + "llvm.hexagon.M2.mpyu.nac.ll.s0" => "__builtin_HEXAGON_M2_mpyu_nac_ll_s0", + "llvm.hexagon.M2.mpyu.nac.ll.s1" => "__builtin_HEXAGON_M2_mpyu_nac_ll_s1", + "llvm.hexagon.M2.mpyu.up" => "__builtin_HEXAGON_M2_mpyu_up", + "llvm.hexagon.M2.mpyud.acc.hh.s0" => "__builtin_HEXAGON_M2_mpyud_acc_hh_s0", + "llvm.hexagon.M2.mpyud.acc.hh.s1" => "__builtin_HEXAGON_M2_mpyud_acc_hh_s1", + "llvm.hexagon.M2.mpyud.acc.hl.s0" => "__builtin_HEXAGON_M2_mpyud_acc_hl_s0", + "llvm.hexagon.M2.mpyud.acc.hl.s1" => "__builtin_HEXAGON_M2_mpyud_acc_hl_s1", + "llvm.hexagon.M2.mpyud.acc.lh.s0" => "__builtin_HEXAGON_M2_mpyud_acc_lh_s0", + "llvm.hexagon.M2.mpyud.acc.lh.s1" => "__builtin_HEXAGON_M2_mpyud_acc_lh_s1", + "llvm.hexagon.M2.mpyud.acc.ll.s0" => "__builtin_HEXAGON_M2_mpyud_acc_ll_s0", + "llvm.hexagon.M2.mpyud.acc.ll.s1" => "__builtin_HEXAGON_M2_mpyud_acc_ll_s1", + "llvm.hexagon.M2.mpyud.hh.s0" => "__builtin_HEXAGON_M2_mpyud_hh_s0", + "llvm.hexagon.M2.mpyud.hh.s1" => "__builtin_HEXAGON_M2_mpyud_hh_s1", + "llvm.hexagon.M2.mpyud.hl.s0" => "__builtin_HEXAGON_M2_mpyud_hl_s0", + "llvm.hexagon.M2.mpyud.hl.s1" => "__builtin_HEXAGON_M2_mpyud_hl_s1", + "llvm.hexagon.M2.mpyud.lh.s0" => "__builtin_HEXAGON_M2_mpyud_lh_s0", + "llvm.hexagon.M2.mpyud.lh.s1" => "__builtin_HEXAGON_M2_mpyud_lh_s1", + "llvm.hexagon.M2.mpyud.ll.s0" => "__builtin_HEXAGON_M2_mpyud_ll_s0", + "llvm.hexagon.M2.mpyud.ll.s1" => "__builtin_HEXAGON_M2_mpyud_ll_s1", + "llvm.hexagon.M2.mpyud.nac.hh.s0" => "__builtin_HEXAGON_M2_mpyud_nac_hh_s0", + "llvm.hexagon.M2.mpyud.nac.hh.s1" => "__builtin_HEXAGON_M2_mpyud_nac_hh_s1", + "llvm.hexagon.M2.mpyud.nac.hl.s0" => "__builtin_HEXAGON_M2_mpyud_nac_hl_s0", + "llvm.hexagon.M2.mpyud.nac.hl.s1" => "__builtin_HEXAGON_M2_mpyud_nac_hl_s1", + "llvm.hexagon.M2.mpyud.nac.lh.s0" => "__builtin_HEXAGON_M2_mpyud_nac_lh_s0", + "llvm.hexagon.M2.mpyud.nac.lh.s1" => "__builtin_HEXAGON_M2_mpyud_nac_lh_s1", + "llvm.hexagon.M2.mpyud.nac.ll.s0" => "__builtin_HEXAGON_M2_mpyud_nac_ll_s0", + "llvm.hexagon.M2.mpyud.nac.ll.s1" => "__builtin_HEXAGON_M2_mpyud_nac_ll_s1", + "llvm.hexagon.M2.mpyui" => "__builtin_HEXAGON_M2_mpyui", + "llvm.hexagon.M2.nacci" => "__builtin_HEXAGON_M2_nacci", + "llvm.hexagon.M2.naccii" => "__builtin_HEXAGON_M2_naccii", + "llvm.hexagon.M2.subacc" => "__builtin_HEXAGON_M2_subacc", + "llvm.hexagon.M2.vabsdiffh" => "__builtin_HEXAGON_M2_vabsdiffh", + "llvm.hexagon.M2.vabsdiffw" => "__builtin_HEXAGON_M2_vabsdiffw", + "llvm.hexagon.M2.vcmac.s0.sat.i" => "__builtin_HEXAGON_M2_vcmac_s0_sat_i", + "llvm.hexagon.M2.vcmac.s0.sat.r" => "__builtin_HEXAGON_M2_vcmac_s0_sat_r", + "llvm.hexagon.M2.vcmpy.s0.sat.i" => "__builtin_HEXAGON_M2_vcmpy_s0_sat_i", + "llvm.hexagon.M2.vcmpy.s0.sat.r" => "__builtin_HEXAGON_M2_vcmpy_s0_sat_r", + "llvm.hexagon.M2.vcmpy.s1.sat.i" => "__builtin_HEXAGON_M2_vcmpy_s1_sat_i", + "llvm.hexagon.M2.vcmpy.s1.sat.r" => "__builtin_HEXAGON_M2_vcmpy_s1_sat_r", + "llvm.hexagon.M2.vdmacs.s0" => "__builtin_HEXAGON_M2_vdmacs_s0", + "llvm.hexagon.M2.vdmacs.s1" => "__builtin_HEXAGON_M2_vdmacs_s1", + "llvm.hexagon.M2.vdmpyrs.s0" => "__builtin_HEXAGON_M2_vdmpyrs_s0", + "llvm.hexagon.M2.vdmpyrs.s1" => "__builtin_HEXAGON_M2_vdmpyrs_s1", + "llvm.hexagon.M2.vdmpys.s0" => "__builtin_HEXAGON_M2_vdmpys_s0", + "llvm.hexagon.M2.vdmpys.s1" => "__builtin_HEXAGON_M2_vdmpys_s1", + "llvm.hexagon.M2.vmac2" => "__builtin_HEXAGON_M2_vmac2", + "llvm.hexagon.M2.vmac2es" => "__builtin_HEXAGON_M2_vmac2es", + "llvm.hexagon.M2.vmac2es.s0" => "__builtin_HEXAGON_M2_vmac2es_s0", + "llvm.hexagon.M2.vmac2es.s1" => "__builtin_HEXAGON_M2_vmac2es_s1", + "llvm.hexagon.M2.vmac2s.s0" => "__builtin_HEXAGON_M2_vmac2s_s0", + "llvm.hexagon.M2.vmac2s.s1" => "__builtin_HEXAGON_M2_vmac2s_s1", + "llvm.hexagon.M2.vmac2su.s0" => "__builtin_HEXAGON_M2_vmac2su_s0", + "llvm.hexagon.M2.vmac2su.s1" => "__builtin_HEXAGON_M2_vmac2su_s1", + "llvm.hexagon.M2.vmpy2es.s0" => "__builtin_HEXAGON_M2_vmpy2es_s0", + "llvm.hexagon.M2.vmpy2es.s1" => "__builtin_HEXAGON_M2_vmpy2es_s1", + "llvm.hexagon.M2.vmpy2s.s0" => "__builtin_HEXAGON_M2_vmpy2s_s0", + "llvm.hexagon.M2.vmpy2s.s0pack" => "__builtin_HEXAGON_M2_vmpy2s_s0pack", + "llvm.hexagon.M2.vmpy2s.s1" => "__builtin_HEXAGON_M2_vmpy2s_s1", + "llvm.hexagon.M2.vmpy2s.s1pack" => "__builtin_HEXAGON_M2_vmpy2s_s1pack", + "llvm.hexagon.M2.vmpy2su.s0" => "__builtin_HEXAGON_M2_vmpy2su_s0", + "llvm.hexagon.M2.vmpy2su.s1" => "__builtin_HEXAGON_M2_vmpy2su_s1", + "llvm.hexagon.M2.vraddh" => "__builtin_HEXAGON_M2_vraddh", + "llvm.hexagon.M2.vradduh" => "__builtin_HEXAGON_M2_vradduh", + "llvm.hexagon.M2.vrcmaci.s0" => "__builtin_HEXAGON_M2_vrcmaci_s0", + "llvm.hexagon.M2.vrcmaci.s0c" => "__builtin_HEXAGON_M2_vrcmaci_s0c", + "llvm.hexagon.M2.vrcmacr.s0" => "__builtin_HEXAGON_M2_vrcmacr_s0", + "llvm.hexagon.M2.vrcmacr.s0c" => "__builtin_HEXAGON_M2_vrcmacr_s0c", + "llvm.hexagon.M2.vrcmpyi.s0" => "__builtin_HEXAGON_M2_vrcmpyi_s0", + "llvm.hexagon.M2.vrcmpyi.s0c" => "__builtin_HEXAGON_M2_vrcmpyi_s0c", + "llvm.hexagon.M2.vrcmpyr.s0" => "__builtin_HEXAGON_M2_vrcmpyr_s0", + "llvm.hexagon.M2.vrcmpyr.s0c" => "__builtin_HEXAGON_M2_vrcmpyr_s0c", + "llvm.hexagon.M2.vrcmpys.acc.s1" => "__builtin_HEXAGON_M2_vrcmpys_acc_s1", + "llvm.hexagon.M2.vrcmpys.s1" => "__builtin_HEXAGON_M2_vrcmpys_s1", + "llvm.hexagon.M2.vrcmpys.s1rp" => "__builtin_HEXAGON_M2_vrcmpys_s1rp", + "llvm.hexagon.M2.vrmac.s0" => "__builtin_HEXAGON_M2_vrmac_s0", + "llvm.hexagon.M2.vrmpy.s0" => "__builtin_HEXAGON_M2_vrmpy_s0", + "llvm.hexagon.M2.xor.xacc" => "__builtin_HEXAGON_M2_xor_xacc", + "llvm.hexagon.M4.and.and" => "__builtin_HEXAGON_M4_and_and", + "llvm.hexagon.M4.and.andn" => "__builtin_HEXAGON_M4_and_andn", + "llvm.hexagon.M4.and.or" => "__builtin_HEXAGON_M4_and_or", + "llvm.hexagon.M4.and.xor" => "__builtin_HEXAGON_M4_and_xor", + "llvm.hexagon.M4.cmpyi.wh" => "__builtin_HEXAGON_M4_cmpyi_wh", + "llvm.hexagon.M4.cmpyi.whc" => "__builtin_HEXAGON_M4_cmpyi_whc", + "llvm.hexagon.M4.cmpyr.wh" => "__builtin_HEXAGON_M4_cmpyr_wh", + "llvm.hexagon.M4.cmpyr.whc" => "__builtin_HEXAGON_M4_cmpyr_whc", + "llvm.hexagon.M4.mac.up.s1.sat" => "__builtin_HEXAGON_M4_mac_up_s1_sat", + "llvm.hexagon.M4.mpyri.addi" => "__builtin_HEXAGON_M4_mpyri_addi", + "llvm.hexagon.M4.mpyri.addr" => "__builtin_HEXAGON_M4_mpyri_addr", + "llvm.hexagon.M4.mpyri.addr.u2" => "__builtin_HEXAGON_M4_mpyri_addr_u2", + "llvm.hexagon.M4.mpyrr.addi" => "__builtin_HEXAGON_M4_mpyrr_addi", + "llvm.hexagon.M4.mpyrr.addr" => "__builtin_HEXAGON_M4_mpyrr_addr", + "llvm.hexagon.M4.nac.up.s1.sat" => "__builtin_HEXAGON_M4_nac_up_s1_sat", + "llvm.hexagon.M4.or.and" => "__builtin_HEXAGON_M4_or_and", + "llvm.hexagon.M4.or.andn" => "__builtin_HEXAGON_M4_or_andn", + "llvm.hexagon.M4.or.or" => "__builtin_HEXAGON_M4_or_or", + "llvm.hexagon.M4.or.xor" => "__builtin_HEXAGON_M4_or_xor", + "llvm.hexagon.M4.pmpyw" => "__builtin_HEXAGON_M4_pmpyw", + "llvm.hexagon.M4.pmpyw.acc" => "__builtin_HEXAGON_M4_pmpyw_acc", + "llvm.hexagon.M4.vpmpyh" => "__builtin_HEXAGON_M4_vpmpyh", + "llvm.hexagon.M4.vpmpyh.acc" => "__builtin_HEXAGON_M4_vpmpyh_acc", + "llvm.hexagon.M4.vrmpyeh.acc.s0" => "__builtin_HEXAGON_M4_vrmpyeh_acc_s0", + "llvm.hexagon.M4.vrmpyeh.acc.s1" => "__builtin_HEXAGON_M4_vrmpyeh_acc_s1", + "llvm.hexagon.M4.vrmpyeh.s0" => "__builtin_HEXAGON_M4_vrmpyeh_s0", + "llvm.hexagon.M4.vrmpyeh.s1" => "__builtin_HEXAGON_M4_vrmpyeh_s1", + "llvm.hexagon.M4.vrmpyoh.acc.s0" => "__builtin_HEXAGON_M4_vrmpyoh_acc_s0", + "llvm.hexagon.M4.vrmpyoh.acc.s1" => "__builtin_HEXAGON_M4_vrmpyoh_acc_s1", + "llvm.hexagon.M4.vrmpyoh.s0" => "__builtin_HEXAGON_M4_vrmpyoh_s0", + "llvm.hexagon.M4.vrmpyoh.s1" => "__builtin_HEXAGON_M4_vrmpyoh_s1", + "llvm.hexagon.M4.xor.and" => "__builtin_HEXAGON_M4_xor_and", + "llvm.hexagon.M4.xor.andn" => "__builtin_HEXAGON_M4_xor_andn", + "llvm.hexagon.M4.xor.or" => "__builtin_HEXAGON_M4_xor_or", + "llvm.hexagon.M4.xor.xacc" => "__builtin_HEXAGON_M4_xor_xacc", + "llvm.hexagon.M5.vdmacbsu" => "__builtin_HEXAGON_M5_vdmacbsu", + "llvm.hexagon.M5.vdmpybsu" => "__builtin_HEXAGON_M5_vdmpybsu", + "llvm.hexagon.M5.vmacbsu" => "__builtin_HEXAGON_M5_vmacbsu", + "llvm.hexagon.M5.vmacbuu" => "__builtin_HEXAGON_M5_vmacbuu", + "llvm.hexagon.M5.vmpybsu" => "__builtin_HEXAGON_M5_vmpybsu", + "llvm.hexagon.M5.vmpybuu" => "__builtin_HEXAGON_M5_vmpybuu", + "llvm.hexagon.M5.vrmacbsu" => "__builtin_HEXAGON_M5_vrmacbsu", + "llvm.hexagon.M5.vrmacbuu" => "__builtin_HEXAGON_M5_vrmacbuu", + "llvm.hexagon.M5.vrmpybsu" => "__builtin_HEXAGON_M5_vrmpybsu", + "llvm.hexagon.M5.vrmpybuu" => "__builtin_HEXAGON_M5_vrmpybuu", + "llvm.hexagon.S2.addasl.rrri" => "__builtin_HEXAGON_S2_addasl_rrri", + "llvm.hexagon.S2.asl.i.p" => "__builtin_HEXAGON_S2_asl_i_p", + "llvm.hexagon.S2.asl.i.p.acc" => "__builtin_HEXAGON_S2_asl_i_p_acc", + "llvm.hexagon.S2.asl.i.p.and" => "__builtin_HEXAGON_S2_asl_i_p_and", + "llvm.hexagon.S2.asl.i.p.nac" => "__builtin_HEXAGON_S2_asl_i_p_nac", + "llvm.hexagon.S2.asl.i.p.or" => "__builtin_HEXAGON_S2_asl_i_p_or", + "llvm.hexagon.S2.asl.i.p.xacc" => "__builtin_HEXAGON_S2_asl_i_p_xacc", + "llvm.hexagon.S2.asl.i.r" => "__builtin_HEXAGON_S2_asl_i_r", + "llvm.hexagon.S2.asl.i.r.acc" => "__builtin_HEXAGON_S2_asl_i_r_acc", + "llvm.hexagon.S2.asl.i.r.and" => "__builtin_HEXAGON_S2_asl_i_r_and", + "llvm.hexagon.S2.asl.i.r.nac" => "__builtin_HEXAGON_S2_asl_i_r_nac", + "llvm.hexagon.S2.asl.i.r.or" => "__builtin_HEXAGON_S2_asl_i_r_or", + "llvm.hexagon.S2.asl.i.r.sat" => "__builtin_HEXAGON_S2_asl_i_r_sat", + "llvm.hexagon.S2.asl.i.r.xacc" => "__builtin_HEXAGON_S2_asl_i_r_xacc", + "llvm.hexagon.S2.asl.i.vh" => "__builtin_HEXAGON_S2_asl_i_vh", + "llvm.hexagon.S2.asl.i.vw" => "__builtin_HEXAGON_S2_asl_i_vw", + "llvm.hexagon.S2.asl.r.p" => "__builtin_HEXAGON_S2_asl_r_p", + "llvm.hexagon.S2.asl.r.p.acc" => "__builtin_HEXAGON_S2_asl_r_p_acc", + "llvm.hexagon.S2.asl.r.p.and" => "__builtin_HEXAGON_S2_asl_r_p_and", + "llvm.hexagon.S2.asl.r.p.nac" => "__builtin_HEXAGON_S2_asl_r_p_nac", + "llvm.hexagon.S2.asl.r.p.or" => "__builtin_HEXAGON_S2_asl_r_p_or", + "llvm.hexagon.S2.asl.r.p.xor" => "__builtin_HEXAGON_S2_asl_r_p_xor", + "llvm.hexagon.S2.asl.r.r" => "__builtin_HEXAGON_S2_asl_r_r", + "llvm.hexagon.S2.asl.r.r.acc" => "__builtin_HEXAGON_S2_asl_r_r_acc", + "llvm.hexagon.S2.asl.r.r.and" => "__builtin_HEXAGON_S2_asl_r_r_and", + "llvm.hexagon.S2.asl.r.r.nac" => "__builtin_HEXAGON_S2_asl_r_r_nac", + "llvm.hexagon.S2.asl.r.r.or" => "__builtin_HEXAGON_S2_asl_r_r_or", + "llvm.hexagon.S2.asl.r.r.sat" => "__builtin_HEXAGON_S2_asl_r_r_sat", + "llvm.hexagon.S2.asl.r.vh" => "__builtin_HEXAGON_S2_asl_r_vh", + "llvm.hexagon.S2.asl.r.vw" => "__builtin_HEXAGON_S2_asl_r_vw", + "llvm.hexagon.S2.asr.i.p" => "__builtin_HEXAGON_S2_asr_i_p", + "llvm.hexagon.S2.asr.i.p.acc" => "__builtin_HEXAGON_S2_asr_i_p_acc", + "llvm.hexagon.S2.asr.i.p.and" => "__builtin_HEXAGON_S2_asr_i_p_and", + "llvm.hexagon.S2.asr.i.p.nac" => "__builtin_HEXAGON_S2_asr_i_p_nac", + "llvm.hexagon.S2.asr.i.p.or" => "__builtin_HEXAGON_S2_asr_i_p_or", + "llvm.hexagon.S2.asr.i.p.rnd" => "__builtin_HEXAGON_S2_asr_i_p_rnd", + "llvm.hexagon.S2.asr.i.p.rnd.goodsyntax" => "__builtin_HEXAGON_S2_asr_i_p_rnd_goodsyntax", + "llvm.hexagon.S2.asr.i.r" => "__builtin_HEXAGON_S2_asr_i_r", + "llvm.hexagon.S2.asr.i.r.acc" => "__builtin_HEXAGON_S2_asr_i_r_acc", + "llvm.hexagon.S2.asr.i.r.and" => "__builtin_HEXAGON_S2_asr_i_r_and", + "llvm.hexagon.S2.asr.i.r.nac" => "__builtin_HEXAGON_S2_asr_i_r_nac", + "llvm.hexagon.S2.asr.i.r.or" => "__builtin_HEXAGON_S2_asr_i_r_or", + "llvm.hexagon.S2.asr.i.r.rnd" => "__builtin_HEXAGON_S2_asr_i_r_rnd", + "llvm.hexagon.S2.asr.i.r.rnd.goodsyntax" => "__builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax", + "llvm.hexagon.S2.asr.i.svw.trun" => "__builtin_HEXAGON_S2_asr_i_svw_trun", + "llvm.hexagon.S2.asr.i.vh" => "__builtin_HEXAGON_S2_asr_i_vh", + "llvm.hexagon.S2.asr.i.vw" => "__builtin_HEXAGON_S2_asr_i_vw", + "llvm.hexagon.S2.asr.r.p" => "__builtin_HEXAGON_S2_asr_r_p", + "llvm.hexagon.S2.asr.r.p.acc" => "__builtin_HEXAGON_S2_asr_r_p_acc", + "llvm.hexagon.S2.asr.r.p.and" => "__builtin_HEXAGON_S2_asr_r_p_and", + "llvm.hexagon.S2.asr.r.p.nac" => "__builtin_HEXAGON_S2_asr_r_p_nac", + "llvm.hexagon.S2.asr.r.p.or" => "__builtin_HEXAGON_S2_asr_r_p_or", + "llvm.hexagon.S2.asr.r.p.xor" => "__builtin_HEXAGON_S2_asr_r_p_xor", + "llvm.hexagon.S2.asr.r.r" => "__builtin_HEXAGON_S2_asr_r_r", + "llvm.hexagon.S2.asr.r.r.acc" => "__builtin_HEXAGON_S2_asr_r_r_acc", + "llvm.hexagon.S2.asr.r.r.and" => "__builtin_HEXAGON_S2_asr_r_r_and", + "llvm.hexagon.S2.asr.r.r.nac" => "__builtin_HEXAGON_S2_asr_r_r_nac", + "llvm.hexagon.S2.asr.r.r.or" => "__builtin_HEXAGON_S2_asr_r_r_or", + "llvm.hexagon.S2.asr.r.r.sat" => "__builtin_HEXAGON_S2_asr_r_r_sat", + "llvm.hexagon.S2.asr.r.svw.trun" => "__builtin_HEXAGON_S2_asr_r_svw_trun", + "llvm.hexagon.S2.asr.r.vh" => "__builtin_HEXAGON_S2_asr_r_vh", + "llvm.hexagon.S2.asr.r.vw" => "__builtin_HEXAGON_S2_asr_r_vw", + "llvm.hexagon.S2.brev" => "__builtin_HEXAGON_S2_brev", + "llvm.hexagon.S2.brevp" => "__builtin_HEXAGON_S2_brevp", + "llvm.hexagon.S2.cl0" => "__builtin_HEXAGON_S2_cl0", + "llvm.hexagon.S2.cl0p" => "__builtin_HEXAGON_S2_cl0p", + "llvm.hexagon.S2.cl1" => "__builtin_HEXAGON_S2_cl1", + "llvm.hexagon.S2.cl1p" => "__builtin_HEXAGON_S2_cl1p", + "llvm.hexagon.S2.clb" => "__builtin_HEXAGON_S2_clb", + "llvm.hexagon.S2.clbnorm" => "__builtin_HEXAGON_S2_clbnorm", + "llvm.hexagon.S2.clbp" => "__builtin_HEXAGON_S2_clbp", + "llvm.hexagon.S2.clrbit.i" => "__builtin_HEXAGON_S2_clrbit_i", + "llvm.hexagon.S2.clrbit.r" => "__builtin_HEXAGON_S2_clrbit_r", + "llvm.hexagon.S2.ct0" => "__builtin_HEXAGON_S2_ct0", + "llvm.hexagon.S2.ct0p" => "__builtin_HEXAGON_S2_ct0p", + "llvm.hexagon.S2.ct1" => "__builtin_HEXAGON_S2_ct1", + "llvm.hexagon.S2.ct1p" => "__builtin_HEXAGON_S2_ct1p", + "llvm.hexagon.S2.deinterleave" => "__builtin_HEXAGON_S2_deinterleave", + "llvm.hexagon.S2.extractu" => "__builtin_HEXAGON_S2_extractu", + "llvm.hexagon.S2.extractu.rp" => "__builtin_HEXAGON_S2_extractu_rp", + "llvm.hexagon.S2.extractup" => "__builtin_HEXAGON_S2_extractup", + "llvm.hexagon.S2.extractup.rp" => "__builtin_HEXAGON_S2_extractup_rp", + "llvm.hexagon.S2.insert" => "__builtin_HEXAGON_S2_insert", + "llvm.hexagon.S2.insert.rp" => "__builtin_HEXAGON_S2_insert_rp", + "llvm.hexagon.S2.insertp" => "__builtin_HEXAGON_S2_insertp", + "llvm.hexagon.S2.insertp.rp" => "__builtin_HEXAGON_S2_insertp_rp", + "llvm.hexagon.S2.interleave" => "__builtin_HEXAGON_S2_interleave", + "llvm.hexagon.S2.lfsp" => "__builtin_HEXAGON_S2_lfsp", + "llvm.hexagon.S2.lsl.r.p" => "__builtin_HEXAGON_S2_lsl_r_p", + "llvm.hexagon.S2.lsl.r.p.acc" => "__builtin_HEXAGON_S2_lsl_r_p_acc", + "llvm.hexagon.S2.lsl.r.p.and" => "__builtin_HEXAGON_S2_lsl_r_p_and", + "llvm.hexagon.S2.lsl.r.p.nac" => "__builtin_HEXAGON_S2_lsl_r_p_nac", + "llvm.hexagon.S2.lsl.r.p.or" => "__builtin_HEXAGON_S2_lsl_r_p_or", + "llvm.hexagon.S2.lsl.r.p.xor" => "__builtin_HEXAGON_S2_lsl_r_p_xor", + "llvm.hexagon.S2.lsl.r.r" => "__builtin_HEXAGON_S2_lsl_r_r", + "llvm.hexagon.S2.lsl.r.r.acc" => "__builtin_HEXAGON_S2_lsl_r_r_acc", + "llvm.hexagon.S2.lsl.r.r.and" => "__builtin_HEXAGON_S2_lsl_r_r_and", + "llvm.hexagon.S2.lsl.r.r.nac" => "__builtin_HEXAGON_S2_lsl_r_r_nac", + "llvm.hexagon.S2.lsl.r.r.or" => "__builtin_HEXAGON_S2_lsl_r_r_or", + "llvm.hexagon.S2.lsl.r.vh" => "__builtin_HEXAGON_S2_lsl_r_vh", + "llvm.hexagon.S2.lsl.r.vw" => "__builtin_HEXAGON_S2_lsl_r_vw", + "llvm.hexagon.S2.lsr.i.p" => "__builtin_HEXAGON_S2_lsr_i_p", + "llvm.hexagon.S2.lsr.i.p.acc" => "__builtin_HEXAGON_S2_lsr_i_p_acc", + "llvm.hexagon.S2.lsr.i.p.and" => "__builtin_HEXAGON_S2_lsr_i_p_and", + "llvm.hexagon.S2.lsr.i.p.nac" => "__builtin_HEXAGON_S2_lsr_i_p_nac", + "llvm.hexagon.S2.lsr.i.p.or" => "__builtin_HEXAGON_S2_lsr_i_p_or", + "llvm.hexagon.S2.lsr.i.p.xacc" => "__builtin_HEXAGON_S2_lsr_i_p_xacc", + "llvm.hexagon.S2.lsr.i.r" => "__builtin_HEXAGON_S2_lsr_i_r", + "llvm.hexagon.S2.lsr.i.r.acc" => "__builtin_HEXAGON_S2_lsr_i_r_acc", + "llvm.hexagon.S2.lsr.i.r.and" => "__builtin_HEXAGON_S2_lsr_i_r_and", + "llvm.hexagon.S2.lsr.i.r.nac" => "__builtin_HEXAGON_S2_lsr_i_r_nac", + "llvm.hexagon.S2.lsr.i.r.or" => "__builtin_HEXAGON_S2_lsr_i_r_or", + "llvm.hexagon.S2.lsr.i.r.xacc" => "__builtin_HEXAGON_S2_lsr_i_r_xacc", + "llvm.hexagon.S2.lsr.i.vh" => "__builtin_HEXAGON_S2_lsr_i_vh", + "llvm.hexagon.S2.lsr.i.vw" => "__builtin_HEXAGON_S2_lsr_i_vw", + "llvm.hexagon.S2.lsr.r.p" => "__builtin_HEXAGON_S2_lsr_r_p", + "llvm.hexagon.S2.lsr.r.p.acc" => "__builtin_HEXAGON_S2_lsr_r_p_acc", + "llvm.hexagon.S2.lsr.r.p.and" => "__builtin_HEXAGON_S2_lsr_r_p_and", + "llvm.hexagon.S2.lsr.r.p.nac" => "__builtin_HEXAGON_S2_lsr_r_p_nac", + "llvm.hexagon.S2.lsr.r.p.or" => "__builtin_HEXAGON_S2_lsr_r_p_or", + "llvm.hexagon.S2.lsr.r.p.xor" => "__builtin_HEXAGON_S2_lsr_r_p_xor", + "llvm.hexagon.S2.lsr.r.r" => "__builtin_HEXAGON_S2_lsr_r_r", + "llvm.hexagon.S2.lsr.r.r.acc" => "__builtin_HEXAGON_S2_lsr_r_r_acc", + "llvm.hexagon.S2.lsr.r.r.and" => "__builtin_HEXAGON_S2_lsr_r_r_and", + "llvm.hexagon.S2.lsr.r.r.nac" => "__builtin_HEXAGON_S2_lsr_r_r_nac", + "llvm.hexagon.S2.lsr.r.r.or" => "__builtin_HEXAGON_S2_lsr_r_r_or", + "llvm.hexagon.S2.lsr.r.vh" => "__builtin_HEXAGON_S2_lsr_r_vh", + "llvm.hexagon.S2.lsr.r.vw" => "__builtin_HEXAGON_S2_lsr_r_vw", + "llvm.hexagon.S2.packhl" => "__builtin_HEXAGON_S2_packhl", + "llvm.hexagon.S2.parityp" => "__builtin_HEXAGON_S2_parityp", + "llvm.hexagon.S2.setbit.i" => "__builtin_HEXAGON_S2_setbit_i", + "llvm.hexagon.S2.setbit.r" => "__builtin_HEXAGON_S2_setbit_r", + "llvm.hexagon.S2.shuffeb" => "__builtin_HEXAGON_S2_shuffeb", + "llvm.hexagon.S2.shuffeh" => "__builtin_HEXAGON_S2_shuffeh", + "llvm.hexagon.S2.shuffob" => "__builtin_HEXAGON_S2_shuffob", + "llvm.hexagon.S2.shuffoh" => "__builtin_HEXAGON_S2_shuffoh", + "llvm.hexagon.S2.svsathb" => "__builtin_HEXAGON_S2_svsathb", + "llvm.hexagon.S2.svsathub" => "__builtin_HEXAGON_S2_svsathub", + "llvm.hexagon.S2.tableidxb.goodsyntax" => "__builtin_HEXAGON_S2_tableidxb_goodsyntax", + "llvm.hexagon.S2.tableidxd.goodsyntax" => "__builtin_HEXAGON_S2_tableidxd_goodsyntax", + "llvm.hexagon.S2.tableidxh.goodsyntax" => "__builtin_HEXAGON_S2_tableidxh_goodsyntax", + "llvm.hexagon.S2.tableidxw.goodsyntax" => "__builtin_HEXAGON_S2_tableidxw_goodsyntax", + "llvm.hexagon.S2.togglebit.i" => "__builtin_HEXAGON_S2_togglebit_i", + "llvm.hexagon.S2.togglebit.r" => "__builtin_HEXAGON_S2_togglebit_r", + "llvm.hexagon.S2.tstbit.i" => "__builtin_HEXAGON_S2_tstbit_i", + "llvm.hexagon.S2.tstbit.r" => "__builtin_HEXAGON_S2_tstbit_r", + "llvm.hexagon.S2.valignib" => "__builtin_HEXAGON_S2_valignib", + "llvm.hexagon.S2.valignrb" => "__builtin_HEXAGON_S2_valignrb", + "llvm.hexagon.S2.vcnegh" => "__builtin_HEXAGON_S2_vcnegh", + "llvm.hexagon.S2.vcrotate" => "__builtin_HEXAGON_S2_vcrotate", + "llvm.hexagon.S2.vrcnegh" => "__builtin_HEXAGON_S2_vrcnegh", + "llvm.hexagon.S2.vrndpackwh" => "__builtin_HEXAGON_S2_vrndpackwh", + "llvm.hexagon.S2.vrndpackwhs" => "__builtin_HEXAGON_S2_vrndpackwhs", + "llvm.hexagon.S2.vsathb" => "__builtin_HEXAGON_S2_vsathb", + "llvm.hexagon.S2.vsathb.nopack" => "__builtin_HEXAGON_S2_vsathb_nopack", + "llvm.hexagon.S2.vsathub" => "__builtin_HEXAGON_S2_vsathub", + "llvm.hexagon.S2.vsathub.nopack" => "__builtin_HEXAGON_S2_vsathub_nopack", + "llvm.hexagon.S2.vsatwh" => "__builtin_HEXAGON_S2_vsatwh", + "llvm.hexagon.S2.vsatwh.nopack" => "__builtin_HEXAGON_S2_vsatwh_nopack", + "llvm.hexagon.S2.vsatwuh" => "__builtin_HEXAGON_S2_vsatwuh", + "llvm.hexagon.S2.vsatwuh.nopack" => "__builtin_HEXAGON_S2_vsatwuh_nopack", + "llvm.hexagon.S2.vsplatrb" => "__builtin_HEXAGON_S2_vsplatrb", + "llvm.hexagon.S2.vsplatrh" => "__builtin_HEXAGON_S2_vsplatrh", + "llvm.hexagon.S2.vspliceib" => "__builtin_HEXAGON_S2_vspliceib", + "llvm.hexagon.S2.vsplicerb" => "__builtin_HEXAGON_S2_vsplicerb", + "llvm.hexagon.S2.vsxtbh" => "__builtin_HEXAGON_S2_vsxtbh", + "llvm.hexagon.S2.vsxthw" => "__builtin_HEXAGON_S2_vsxthw", + "llvm.hexagon.S2.vtrunehb" => "__builtin_HEXAGON_S2_vtrunehb", + "llvm.hexagon.S2.vtrunewh" => "__builtin_HEXAGON_S2_vtrunewh", + "llvm.hexagon.S2.vtrunohb" => "__builtin_HEXAGON_S2_vtrunohb", + "llvm.hexagon.S2.vtrunowh" => "__builtin_HEXAGON_S2_vtrunowh", + "llvm.hexagon.S2.vzxtbh" => "__builtin_HEXAGON_S2_vzxtbh", + "llvm.hexagon.S2.vzxthw" => "__builtin_HEXAGON_S2_vzxthw", + "llvm.hexagon.S4.addaddi" => "__builtin_HEXAGON_S4_addaddi", + "llvm.hexagon.S4.addi.asl.ri" => "__builtin_HEXAGON_S4_addi_asl_ri", + "llvm.hexagon.S4.addi.lsr.ri" => "__builtin_HEXAGON_S4_addi_lsr_ri", + "llvm.hexagon.S4.andi.asl.ri" => "__builtin_HEXAGON_S4_andi_asl_ri", + "llvm.hexagon.S4.andi.lsr.ri" => "__builtin_HEXAGON_S4_andi_lsr_ri", + "llvm.hexagon.S4.clbaddi" => "__builtin_HEXAGON_S4_clbaddi", + "llvm.hexagon.S4.clbpaddi" => "__builtin_HEXAGON_S4_clbpaddi", + "llvm.hexagon.S4.clbpnorm" => "__builtin_HEXAGON_S4_clbpnorm", + "llvm.hexagon.S4.extract" => "__builtin_HEXAGON_S4_extract", + "llvm.hexagon.S4.extract.rp" => "__builtin_HEXAGON_S4_extract_rp", + "llvm.hexagon.S4.extractp" => "__builtin_HEXAGON_S4_extractp", + "llvm.hexagon.S4.extractp.rp" => "__builtin_HEXAGON_S4_extractp_rp", + "llvm.hexagon.S4.lsli" => "__builtin_HEXAGON_S4_lsli", + "llvm.hexagon.S4.ntstbit.i" => "__builtin_HEXAGON_S4_ntstbit_i", + "llvm.hexagon.S4.ntstbit.r" => "__builtin_HEXAGON_S4_ntstbit_r", + "llvm.hexagon.S4.or.andi" => "__builtin_HEXAGON_S4_or_andi", + "llvm.hexagon.S4.or.andix" => "__builtin_HEXAGON_S4_or_andix", + "llvm.hexagon.S4.or.ori" => "__builtin_HEXAGON_S4_or_ori", + "llvm.hexagon.S4.ori.asl.ri" => "__builtin_HEXAGON_S4_ori_asl_ri", + "llvm.hexagon.S4.ori.lsr.ri" => "__builtin_HEXAGON_S4_ori_lsr_ri", + "llvm.hexagon.S4.parity" => "__builtin_HEXAGON_S4_parity", + "llvm.hexagon.S4.subaddi" => "__builtin_HEXAGON_S4_subaddi", + "llvm.hexagon.S4.subi.asl.ri" => "__builtin_HEXAGON_S4_subi_asl_ri", + "llvm.hexagon.S4.subi.lsr.ri" => "__builtin_HEXAGON_S4_subi_lsr_ri", + "llvm.hexagon.S4.vrcrotate" => "__builtin_HEXAGON_S4_vrcrotate", + "llvm.hexagon.S4.vrcrotate.acc" => "__builtin_HEXAGON_S4_vrcrotate_acc", + "llvm.hexagon.S4.vxaddsubh" => "__builtin_HEXAGON_S4_vxaddsubh", + "llvm.hexagon.S4.vxaddsubhr" => "__builtin_HEXAGON_S4_vxaddsubhr", + "llvm.hexagon.S4.vxaddsubw" => "__builtin_HEXAGON_S4_vxaddsubw", + "llvm.hexagon.S4.vxsubaddh" => "__builtin_HEXAGON_S4_vxsubaddh", + "llvm.hexagon.S4.vxsubaddhr" => "__builtin_HEXAGON_S4_vxsubaddhr", + "llvm.hexagon.S4.vxsubaddw" => "__builtin_HEXAGON_S4_vxsubaddw", + "llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax" => "__builtin_HEXAGON_S5_asrhub_rnd_sat_goodsyntax", + "llvm.hexagon.S5.asrhub.sat" => "__builtin_HEXAGON_S5_asrhub_sat", + "llvm.hexagon.S5.popcountp" => "__builtin_HEXAGON_S5_popcountp", + "llvm.hexagon.S5.vasrhrnd.goodsyntax" => "__builtin_HEXAGON_S5_vasrhrnd_goodsyntax", + "llvm.hexagon.SI.to.SXTHI.asrh" => "__builtin_SI_to_SXTHI_asrh", + "llvm.hexagon.circ.ldd" => "__builtin_circ_ldd", // mips "llvm.mips.absq.s.ph" => "__builtin_mips_absq_s_ph", "llvm.mips.absq.s.qb" => "__builtin_mips_absq_s_qb", @@ -887,7 +1775,531 @@ match name { "llvm.mips.xor.v" => "__builtin_msa_xor_v", "llvm.mips.xori.b" => "__builtin_msa_xori_b", // nvvm + "llvm.nvvm.abs.i" => "__nvvm_abs_i", + "llvm.nvvm.abs.ll" => "__nvvm_abs_ll", + "llvm.nvvm.add.rm.d" => "__nvvm_add_rm_d", + "llvm.nvvm.add.rm.f" => "__nvvm_add_rm_f", + "llvm.nvvm.add.rm.ftz.f" => "__nvvm_add_rm_ftz_f", + "llvm.nvvm.add.rn.d" => "__nvvm_add_rn_d", + "llvm.nvvm.add.rn.f" => "__nvvm_add_rn_f", + "llvm.nvvm.add.rn.ftz.f" => "__nvvm_add_rn_ftz_f", + "llvm.nvvm.add.rp.d" => "__nvvm_add_rp_d", + "llvm.nvvm.add.rp.f" => "__nvvm_add_rp_f", + "llvm.nvvm.add.rp.ftz.f" => "__nvvm_add_rp_ftz_f", + "llvm.nvvm.add.rz.d" => "__nvvm_add_rz_d", + "llvm.nvvm.add.rz.f" => "__nvvm_add_rz_f", + "llvm.nvvm.add.rz.ftz.f" => "__nvvm_add_rz_ftz_f", + "llvm.nvvm.barrier0" => "__nvvm_bar0", + "llvm.nvvm.barrier0.and" => "__nvvm_bar0_and", + "llvm.nvvm.barrier0.or" => "__nvvm_bar0_or", + "llvm.nvvm.barrier0.popc" => "__nvvm_bar0_popc", + "llvm.nvvm.bitcast.d2ll" => "__nvvm_bitcast_d2ll", + "llvm.nvvm.bitcast.f2i" => "__nvvm_bitcast_f2i", + "llvm.nvvm.bitcast.i2f" => "__nvvm_bitcast_i2f", + "llvm.nvvm.bitcast.ll2d" => "__nvvm_bitcast_ll2d", + "llvm.nvvm.brev32" => "__nvvm_brev32", + "llvm.nvvm.brev64" => "__nvvm_brev64", + "llvm.nvvm.ceil.d" => "__nvvm_ceil_d", + "llvm.nvvm.ceil.f" => "__nvvm_ceil_f", + "llvm.nvvm.ceil.ftz.f" => "__nvvm_ceil_ftz_f", + "llvm.nvvm.clz.i" => "__nvvm_clz_i", + "llvm.nvvm.clz.ll" => "__nvvm_clz_ll", + "llvm.nvvm.cos.approx.f" => "__nvvm_cos_approx_f", + "llvm.nvvm.cos.approx.ftz.f" => "__nvvm_cos_approx_ftz_f", + "llvm.nvvm.d2f.rm" => "__nvvm_d2f_rm", + "llvm.nvvm.d2f.rm.ftz" => "__nvvm_d2f_rm_ftz", + "llvm.nvvm.d2f.rn" => "__nvvm_d2f_rn", + "llvm.nvvm.d2f.rn.ftz" => "__nvvm_d2f_rn_ftz", + "llvm.nvvm.d2f.rp" => "__nvvm_d2f_rp", + "llvm.nvvm.d2f.rp.ftz" => "__nvvm_d2f_rp_ftz", + "llvm.nvvm.d2f.rz" => "__nvvm_d2f_rz", + "llvm.nvvm.d2f.rz.ftz" => "__nvvm_d2f_rz_ftz", + "llvm.nvvm.d2i.hi" => "__nvvm_d2i_hi", + "llvm.nvvm.d2i.lo" => "__nvvm_d2i_lo", + "llvm.nvvm.d2i.rm" => "__nvvm_d2i_rm", + "llvm.nvvm.d2i.rn" => "__nvvm_d2i_rn", + "llvm.nvvm.d2i.rp" => "__nvvm_d2i_rp", + "llvm.nvvm.d2i.rz" => "__nvvm_d2i_rz", + "llvm.nvvm.d2ll.rm" => "__nvvm_d2ll_rm", + "llvm.nvvm.d2ll.rn" => "__nvvm_d2ll_rn", + "llvm.nvvm.d2ll.rp" => "__nvvm_d2ll_rp", + "llvm.nvvm.d2ll.rz" => "__nvvm_d2ll_rz", + "llvm.nvvm.d2ui.rm" => "__nvvm_d2ui_rm", + "llvm.nvvm.d2ui.rn" => "__nvvm_d2ui_rn", + "llvm.nvvm.d2ui.rp" => "__nvvm_d2ui_rp", + "llvm.nvvm.d2ui.rz" => "__nvvm_d2ui_rz", + "llvm.nvvm.d2ull.rm" => "__nvvm_d2ull_rm", + "llvm.nvvm.d2ull.rn" => "__nvvm_d2ull_rn", + "llvm.nvvm.d2ull.rp" => "__nvvm_d2ull_rp", + "llvm.nvvm.d2ull.rz" => "__nvvm_d2ull_rz", + "llvm.nvvm.div.approx.f" => "__nvvm_div_approx_f", + "llvm.nvvm.div.approx.ftz.f" => "__nvvm_div_approx_ftz_f", + "llvm.nvvm.div.rm.d" => "__nvvm_div_rm_d", + "llvm.nvvm.div.rm.f" => "__nvvm_div_rm_f", + "llvm.nvvm.div.rm.ftz.f" => "__nvvm_div_rm_ftz_f", + "llvm.nvvm.div.rn.d" => "__nvvm_div_rn_d", + "llvm.nvvm.div.rn.f" => "__nvvm_div_rn_f", + "llvm.nvvm.div.rn.ftz.f" => "__nvvm_div_rn_ftz_f", + "llvm.nvvm.div.rp.d" => "__nvvm_div_rp_d", + "llvm.nvvm.div.rp.f" => "__nvvm_div_rp_f", + "llvm.nvvm.div.rp.ftz.f" => "__nvvm_div_rp_ftz_f", + "llvm.nvvm.div.rz.d" => "__nvvm_div_rz_d", + "llvm.nvvm.div.rz.f" => "__nvvm_div_rz_f", + "llvm.nvvm.div.rz.ftz.f" => "__nvvm_div_rz_ftz_f", + "llvm.nvvm.ex2.approx.d" => "__nvvm_ex2_approx_d", + "llvm.nvvm.ex2.approx.f" => "__nvvm_ex2_approx_f", + "llvm.nvvm.ex2.approx.ftz.f" => "__nvvm_ex2_approx_ftz_f", + "llvm.nvvm.f2h.rn" => "__nvvm_f2h_rn", + "llvm.nvvm.f2h.rn.ftz" => "__nvvm_f2h_rn_ftz", + "llvm.nvvm.f2i.rm" => "__nvvm_f2i_rm", + "llvm.nvvm.f2i.rm.ftz" => "__nvvm_f2i_rm_ftz", + "llvm.nvvm.f2i.rn" => "__nvvm_f2i_rn", + "llvm.nvvm.f2i.rn.ftz" => "__nvvm_f2i_rn_ftz", + "llvm.nvvm.f2i.rp" => "__nvvm_f2i_rp", + "llvm.nvvm.f2i.rp.ftz" => "__nvvm_f2i_rp_ftz", + "llvm.nvvm.f2i.rz" => "__nvvm_f2i_rz", + "llvm.nvvm.f2i.rz.ftz" => "__nvvm_f2i_rz_ftz", + "llvm.nvvm.f2ll.rm" => "__nvvm_f2ll_rm", + "llvm.nvvm.f2ll.rm.ftz" => "__nvvm_f2ll_rm_ftz", + "llvm.nvvm.f2ll.rn" => "__nvvm_f2ll_rn", + "llvm.nvvm.f2ll.rn.ftz" => "__nvvm_f2ll_rn_ftz", + "llvm.nvvm.f2ll.rp" => "__nvvm_f2ll_rp", + "llvm.nvvm.f2ll.rp.ftz" => "__nvvm_f2ll_rp_ftz", + "llvm.nvvm.f2ll.rz" => "__nvvm_f2ll_rz", + "llvm.nvvm.f2ll.rz.ftz" => "__nvvm_f2ll_rz_ftz", + "llvm.nvvm.f2ui.rm" => "__nvvm_f2ui_rm", + "llvm.nvvm.f2ui.rm.ftz" => "__nvvm_f2ui_rm_ftz", + "llvm.nvvm.f2ui.rn" => "__nvvm_f2ui_rn", + "llvm.nvvm.f2ui.rn.ftz" => "__nvvm_f2ui_rn_ftz", + "llvm.nvvm.f2ui.rp" => "__nvvm_f2ui_rp", + "llvm.nvvm.f2ui.rp.ftz" => "__nvvm_f2ui_rp_ftz", + "llvm.nvvm.f2ui.rz" => "__nvvm_f2ui_rz", + "llvm.nvvm.f2ui.rz.ftz" => "__nvvm_f2ui_rz_ftz", + "llvm.nvvm.f2ull.rm" => "__nvvm_f2ull_rm", + "llvm.nvvm.f2ull.rm.ftz" => "__nvvm_f2ull_rm_ftz", + "llvm.nvvm.f2ull.rn" => "__nvvm_f2ull_rn", + "llvm.nvvm.f2ull.rn.ftz" => "__nvvm_f2ull_rn_ftz", + "llvm.nvvm.f2ull.rp" => "__nvvm_f2ull_rp", + "llvm.nvvm.f2ull.rp.ftz" => "__nvvm_f2ull_rp_ftz", + "llvm.nvvm.f2ull.rz" => "__nvvm_f2ull_rz", + "llvm.nvvm.f2ull.rz.ftz" => "__nvvm_f2ull_rz_ftz", + "llvm.nvvm.fabs.d" => "__nvvm_fabs_d", + "llvm.nvvm.fabs.f" => "__nvvm_fabs_f", + "llvm.nvvm.fabs.ftz.f" => "__nvvm_fabs_ftz_f", + "llvm.nvvm.floor.d" => "__nvvm_floor_d", + "llvm.nvvm.floor.f" => "__nvvm_floor_f", + "llvm.nvvm.floor.ftz.f" => "__nvvm_floor_ftz_f", + "llvm.nvvm.fma.rm.d" => "__nvvm_fma_rm_d", + "llvm.nvvm.fma.rm.f" => "__nvvm_fma_rm_f", + "llvm.nvvm.fma.rm.ftz.f" => "__nvvm_fma_rm_ftz_f", + "llvm.nvvm.fma.rn.d" => "__nvvm_fma_rn_d", + "llvm.nvvm.fma.rn.f" => "__nvvm_fma_rn_f", + "llvm.nvvm.fma.rn.ftz.f" => "__nvvm_fma_rn_ftz_f", + "llvm.nvvm.fma.rp.d" => "__nvvm_fma_rp_d", + "llvm.nvvm.fma.rp.f" => "__nvvm_fma_rp_f", + "llvm.nvvm.fma.rp.ftz.f" => "__nvvm_fma_rp_ftz_f", + "llvm.nvvm.fma.rz.d" => "__nvvm_fma_rz_d", + "llvm.nvvm.fma.rz.f" => "__nvvm_fma_rz_f", + "llvm.nvvm.fma.rz.ftz.f" => "__nvvm_fma_rz_ftz_f", + "llvm.nvvm.fmax.d" => "__nvvm_fmax_d", + "llvm.nvvm.fmax.f" => "__nvvm_fmax_f", + "llvm.nvvm.fmax.ftz.f" => "__nvvm_fmax_ftz_f", + "llvm.nvvm.fmin.d" => "__nvvm_fmin_d", + "llvm.nvvm.fmin.f" => "__nvvm_fmin_f", + "llvm.nvvm.fmin.ftz.f" => "__nvvm_fmin_ftz_f", + "llvm.nvvm.h2f" => "__nvvm_h2f", + "llvm.nvvm.i2d.rm" => "__nvvm_i2d_rm", + "llvm.nvvm.i2d.rn" => "__nvvm_i2d_rn", + "llvm.nvvm.i2d.rp" => "__nvvm_i2d_rp", + "llvm.nvvm.i2d.rz" => "__nvvm_i2d_rz", + "llvm.nvvm.i2f.rm" => "__nvvm_i2f_rm", + "llvm.nvvm.i2f.rn" => "__nvvm_i2f_rn", + "llvm.nvvm.i2f.rp" => "__nvvm_i2f_rp", + "llvm.nvvm.i2f.rz" => "__nvvm_i2f_rz", + "llvm.nvvm.isspacep.const" => "__nvvm_isspacep_const", + "llvm.nvvm.isspacep.global" => "__nvvm_isspacep_global", + "llvm.nvvm.isspacep.local" => "__nvvm_isspacep_local", + "llvm.nvvm.isspacep.shared" => "__nvvm_isspacep_shared", + "llvm.nvvm.istypep.sampler" => "__nvvm_istypep_sampler", + "llvm.nvvm.istypep.surface" => "__nvvm_istypep_surface", + "llvm.nvvm.istypep.texture" => "__nvvm_istypep_texture", + "llvm.nvvm.lg2.approx.d" => "__nvvm_lg2_approx_d", + "llvm.nvvm.lg2.approx.f" => "__nvvm_lg2_approx_f", + "llvm.nvvm.lg2.approx.ftz.f" => "__nvvm_lg2_approx_ftz_f", + "llvm.nvvm.ll2d.rm" => "__nvvm_ll2d_rm", + "llvm.nvvm.ll2d.rn" => "__nvvm_ll2d_rn", + "llvm.nvvm.ll2d.rp" => "__nvvm_ll2d_rp", + "llvm.nvvm.ll2d.rz" => "__nvvm_ll2d_rz", + "llvm.nvvm.ll2f.rm" => "__nvvm_ll2f_rm", + "llvm.nvvm.ll2f.rn" => "__nvvm_ll2f_rn", + "llvm.nvvm.ll2f.rp" => "__nvvm_ll2f_rp", + "llvm.nvvm.ll2f.rz" => "__nvvm_ll2f_rz", + "llvm.nvvm.lohi.i2d" => "__nvvm_lohi_i2d", + "llvm.nvvm.max.i" => "__nvvm_max_i", + "llvm.nvvm.max.ll" => "__nvvm_max_ll", + "llvm.nvvm.max.ui" => "__nvvm_max_ui", + "llvm.nvvm.max.ull" => "__nvvm_max_ull", + "llvm.nvvm.membar.cta" => "__nvvm_membar_cta", + "llvm.nvvm.membar.gl" => "__nvvm_membar_gl", + "llvm.nvvm.membar.sys" => "__nvvm_membar_sys", + "llvm.nvvm.min.i" => "__nvvm_min_i", + "llvm.nvvm.min.ll" => "__nvvm_min_ll", + "llvm.nvvm.min.ui" => "__nvvm_min_ui", + "llvm.nvvm.min.ull" => "__nvvm_min_ull", + "llvm.nvvm.mul.rm.d" => "__nvvm_mul_rm_d", + "llvm.nvvm.mul.rm.f" => "__nvvm_mul_rm_f", + "llvm.nvvm.mul.rm.ftz.f" => "__nvvm_mul_rm_ftz_f", + "llvm.nvvm.mul.rn.d" => "__nvvm_mul_rn_d", + "llvm.nvvm.mul.rn.f" => "__nvvm_mul_rn_f", + "llvm.nvvm.mul.rn.ftz.f" => "__nvvm_mul_rn_ftz_f", + "llvm.nvvm.mul.rp.d" => "__nvvm_mul_rp_d", + "llvm.nvvm.mul.rp.f" => "__nvvm_mul_rp_f", + "llvm.nvvm.mul.rp.ftz.f" => "__nvvm_mul_rp_ftz_f", + "llvm.nvvm.mul.rz.d" => "__nvvm_mul_rz_d", + "llvm.nvvm.mul.rz.f" => "__nvvm_mul_rz_f", + "llvm.nvvm.mul.rz.ftz.f" => "__nvvm_mul_rz_ftz_f", + "llvm.nvvm.mul24.i" => "__nvvm_mul24_i", + "llvm.nvvm.mul24.ui" => "__nvvm_mul24_ui", + "llvm.nvvm.mulhi.i" => "__nvvm_mulhi_i", + "llvm.nvvm.mulhi.ll" => "__nvvm_mulhi_ll", + "llvm.nvvm.mulhi.ui" => "__nvvm_mulhi_ui", + "llvm.nvvm.mulhi.ull" => "__nvvm_mulhi_ull", + "llvm.nvvm.popc.i" => "__nvvm_popc_i", + "llvm.nvvm.popc.ll" => "__nvvm_popc_ll", "llvm.nvvm.prmt" => "__nvvm_prmt", + "llvm.nvvm.rcp.approx.ftz.d" => "__nvvm_rcp_approx_ftz_d", + "llvm.nvvm.rcp.rm.d" => "__nvvm_rcp_rm_d", + "llvm.nvvm.rcp.rm.f" => "__nvvm_rcp_rm_f", + "llvm.nvvm.rcp.rm.ftz.f" => "__nvvm_rcp_rm_ftz_f", + "llvm.nvvm.rcp.rn.d" => "__nvvm_rcp_rn_d", + "llvm.nvvm.rcp.rn.f" => "__nvvm_rcp_rn_f", + "llvm.nvvm.rcp.rn.ftz.f" => "__nvvm_rcp_rn_ftz_f", + "llvm.nvvm.rcp.rp.d" => "__nvvm_rcp_rp_d", + "llvm.nvvm.rcp.rp.f" => "__nvvm_rcp_rp_f", + "llvm.nvvm.rcp.rp.ftz.f" => "__nvvm_rcp_rp_ftz_f", + "llvm.nvvm.rcp.rz.d" => "__nvvm_rcp_rz_d", + "llvm.nvvm.rcp.rz.f" => "__nvvm_rcp_rz_f", + "llvm.nvvm.rcp.rz.ftz.f" => "__nvvm_rcp_rz_ftz_f", + "llvm.nvvm.read.ptx.sreg.ctaid.x" => "__nvvm_read_ptx_sreg_ctaid_x", + "llvm.nvvm.read.ptx.sreg.ctaid.y" => "__nvvm_read_ptx_sreg_ctaid_y", + "llvm.nvvm.read.ptx.sreg.ctaid.z" => "__nvvm_read_ptx_sreg_ctaid_z", + "llvm.nvvm.read.ptx.sreg.envreg0" => "__nvvm_read_ptx_sreg_envreg0", + "llvm.nvvm.read.ptx.sreg.envreg1" => "__nvvm_read_ptx_sreg_envreg1", + "llvm.nvvm.read.ptx.sreg.envreg10" => "__nvvm_read_ptx_sreg_envreg10", + "llvm.nvvm.read.ptx.sreg.envreg11" => "__nvvm_read_ptx_sreg_envreg11", + "llvm.nvvm.read.ptx.sreg.envreg12" => "__nvvm_read_ptx_sreg_envreg12", + "llvm.nvvm.read.ptx.sreg.envreg13" => "__nvvm_read_ptx_sreg_envreg13", + "llvm.nvvm.read.ptx.sreg.envreg14" => "__nvvm_read_ptx_sreg_envreg14", + "llvm.nvvm.read.ptx.sreg.envreg15" => "__nvvm_read_ptx_sreg_envreg15", + "llvm.nvvm.read.ptx.sreg.envreg16" => "__nvvm_read_ptx_sreg_envreg16", + "llvm.nvvm.read.ptx.sreg.envreg17" => "__nvvm_read_ptx_sreg_envreg17", + "llvm.nvvm.read.ptx.sreg.envreg18" => "__nvvm_read_ptx_sreg_envreg18", + "llvm.nvvm.read.ptx.sreg.envreg19" => "__nvvm_read_ptx_sreg_envreg19", + "llvm.nvvm.read.ptx.sreg.envreg2" => "__nvvm_read_ptx_sreg_envreg2", + "llvm.nvvm.read.ptx.sreg.envreg20" => "__nvvm_read_ptx_sreg_envreg20", + "llvm.nvvm.read.ptx.sreg.envreg21" => "__nvvm_read_ptx_sreg_envreg21", + "llvm.nvvm.read.ptx.sreg.envreg22" => "__nvvm_read_ptx_sreg_envreg22", + "llvm.nvvm.read.ptx.sreg.envreg23" => "__nvvm_read_ptx_sreg_envreg23", + "llvm.nvvm.read.ptx.sreg.envreg24" => "__nvvm_read_ptx_sreg_envreg24", + "llvm.nvvm.read.ptx.sreg.envreg25" => "__nvvm_read_ptx_sreg_envreg25", + "llvm.nvvm.read.ptx.sreg.envreg26" => "__nvvm_read_ptx_sreg_envreg26", + "llvm.nvvm.read.ptx.sreg.envreg27" => "__nvvm_read_ptx_sreg_envreg27", + "llvm.nvvm.read.ptx.sreg.envreg28" => "__nvvm_read_ptx_sreg_envreg28", + "llvm.nvvm.read.ptx.sreg.envreg29" => "__nvvm_read_ptx_sreg_envreg29", + "llvm.nvvm.read.ptx.sreg.envreg3" => "__nvvm_read_ptx_sreg_envreg3", + "llvm.nvvm.read.ptx.sreg.envreg30" => "__nvvm_read_ptx_sreg_envreg30", + "llvm.nvvm.read.ptx.sreg.envreg31" => "__nvvm_read_ptx_sreg_envreg31", + "llvm.nvvm.read.ptx.sreg.envreg4" => "__nvvm_read_ptx_sreg_envreg4", + "llvm.nvvm.read.ptx.sreg.envreg5" => "__nvvm_read_ptx_sreg_envreg5", + "llvm.nvvm.read.ptx.sreg.envreg6" => "__nvvm_read_ptx_sreg_envreg6", + "llvm.nvvm.read.ptx.sreg.envreg7" => "__nvvm_read_ptx_sreg_envreg7", + "llvm.nvvm.read.ptx.sreg.envreg8" => "__nvvm_read_ptx_sreg_envreg8", + "llvm.nvvm.read.ptx.sreg.envreg9" => "__nvvm_read_ptx_sreg_envreg9", + "llvm.nvvm.read.ptx.sreg.nctaid.x" => "__nvvm_read_ptx_sreg_nctaid_x", + "llvm.nvvm.read.ptx.sreg.nctaid.y" => "__nvvm_read_ptx_sreg_nctaid_y", + "llvm.nvvm.read.ptx.sreg.nctaid.z" => "__nvvm_read_ptx_sreg_nctaid_z", + "llvm.nvvm.read.ptx.sreg.ntid.x" => "__nvvm_read_ptx_sreg_ntid_x", + "llvm.nvvm.read.ptx.sreg.ntid.y" => "__nvvm_read_ptx_sreg_ntid_y", + "llvm.nvvm.read.ptx.sreg.ntid.z" => "__nvvm_read_ptx_sreg_ntid_z", + "llvm.nvvm.read.ptx.sreg.tid.x" => "__nvvm_read_ptx_sreg_tid_x", + "llvm.nvvm.read.ptx.sreg.tid.y" => "__nvvm_read_ptx_sreg_tid_y", + "llvm.nvvm.read.ptx.sreg.tid.z" => "__nvvm_read_ptx_sreg_tid_z", + "llvm.nvvm.read.ptx.sreg.warpsize" => "__nvvm_read_ptx_sreg_warpsize", + "llvm.nvvm.rotate.b32" => "__nvvm_rotate_b32", + "llvm.nvvm.rotate.b64" => "__nvvm_rotate_b64", + "llvm.nvvm.rotate.right.b64" => "__nvvm_rotate_right_b64", + "llvm.nvvm.round.d" => "__nvvm_round_d", + "llvm.nvvm.round.f" => "__nvvm_round_f", + "llvm.nvvm.round.ftz.f" => "__nvvm_round_ftz_f", + "llvm.nvvm.rsqrt.approx.d" => "__nvvm_rsqrt_approx_d", + "llvm.nvvm.rsqrt.approx.f" => "__nvvm_rsqrt_approx_f", + "llvm.nvvm.rsqrt.approx.ftz.f" => "__nvvm_rsqrt_approx_ftz_f", + "llvm.nvvm.sad.i" => "__nvvm_sad_i", + "llvm.nvvm.sad.ui" => "__nvvm_sad_ui", + "llvm.nvvm.saturate.d" => "__nvvm_saturate_d", + "llvm.nvvm.saturate.f" => "__nvvm_saturate_f", + "llvm.nvvm.saturate.ftz.f" => "__nvvm_saturate_ftz_f", + "llvm.nvvm.sin.approx.f" => "__nvvm_sin_approx_f", + "llvm.nvvm.sin.approx.ftz.f" => "__nvvm_sin_approx_ftz_f", + "llvm.nvvm.sqrt.approx.f" => "__nvvm_sqrt_approx_f", + "llvm.nvvm.sqrt.approx.ftz.f" => "__nvvm_sqrt_approx_ftz_f", + "llvm.nvvm.sqrt.f" => "__nvvm_sqrt_f", + "llvm.nvvm.sqrt.rm.d" => "__nvvm_sqrt_rm_d", + "llvm.nvvm.sqrt.rm.f" => "__nvvm_sqrt_rm_f", + "llvm.nvvm.sqrt.rm.ftz.f" => "__nvvm_sqrt_rm_ftz_f", + "llvm.nvvm.sqrt.rn.d" => "__nvvm_sqrt_rn_d", + "llvm.nvvm.sqrt.rn.f" => "__nvvm_sqrt_rn_f", + "llvm.nvvm.sqrt.rn.ftz.f" => "__nvvm_sqrt_rn_ftz_f", + "llvm.nvvm.sqrt.rp.d" => "__nvvm_sqrt_rp_d", + "llvm.nvvm.sqrt.rp.f" => "__nvvm_sqrt_rp_f", + "llvm.nvvm.sqrt.rp.ftz.f" => "__nvvm_sqrt_rp_ftz_f", + "llvm.nvvm.sqrt.rz.d" => "__nvvm_sqrt_rz_d", + "llvm.nvvm.sqrt.rz.f" => "__nvvm_sqrt_rz_f", + "llvm.nvvm.sqrt.rz.ftz.f" => "__nvvm_sqrt_rz_ftz_f", + "llvm.nvvm.suq.array.size" => "__nvvm_suq_array_size", + "llvm.nvvm.suq.channel.data.type" => "__nvvm_suq_channel_data_type", + "llvm.nvvm.suq.channel.order" => "__nvvm_suq_channel_order", + "llvm.nvvm.suq.depth" => "__nvvm_suq_depth", + "llvm.nvvm.suq.height" => "__nvvm_suq_height", + "llvm.nvvm.suq.width" => "__nvvm_suq_width", + "llvm.nvvm.sust.b.1d.array.i16.clamp" => "__nvvm_sust_b_1d_array_i16_clamp", + "llvm.nvvm.sust.b.1d.array.i16.trap" => "__nvvm_sust_b_1d_array_i16_trap", + "llvm.nvvm.sust.b.1d.array.i16.zero" => "__nvvm_sust_b_1d_array_i16_zero", + "llvm.nvvm.sust.b.1d.array.i32.clamp" => "__nvvm_sust_b_1d_array_i32_clamp", + "llvm.nvvm.sust.b.1d.array.i32.trap" => "__nvvm_sust_b_1d_array_i32_trap", + "llvm.nvvm.sust.b.1d.array.i32.zero" => "__nvvm_sust_b_1d_array_i32_zero", + "llvm.nvvm.sust.b.1d.array.i64.clamp" => "__nvvm_sust_b_1d_array_i64_clamp", + "llvm.nvvm.sust.b.1d.array.i64.trap" => "__nvvm_sust_b_1d_array_i64_trap", + "llvm.nvvm.sust.b.1d.array.i64.zero" => "__nvvm_sust_b_1d_array_i64_zero", + "llvm.nvvm.sust.b.1d.array.i8.clamp" => "__nvvm_sust_b_1d_array_i8_clamp", + "llvm.nvvm.sust.b.1d.array.i8.trap" => "__nvvm_sust_b_1d_array_i8_trap", + "llvm.nvvm.sust.b.1d.array.i8.zero" => "__nvvm_sust_b_1d_array_i8_zero", + "llvm.nvvm.sust.b.1d.array.v2i16.clamp" => "__nvvm_sust_b_1d_array_v2i16_clamp", + "llvm.nvvm.sust.b.1d.array.v2i16.trap" => "__nvvm_sust_b_1d_array_v2i16_trap", + "llvm.nvvm.sust.b.1d.array.v2i16.zero" => "__nvvm_sust_b_1d_array_v2i16_zero", + "llvm.nvvm.sust.b.1d.array.v2i32.clamp" => "__nvvm_sust_b_1d_array_v2i32_clamp", + "llvm.nvvm.sust.b.1d.array.v2i32.trap" => "__nvvm_sust_b_1d_array_v2i32_trap", + "llvm.nvvm.sust.b.1d.array.v2i32.zero" => "__nvvm_sust_b_1d_array_v2i32_zero", + "llvm.nvvm.sust.b.1d.array.v2i64.clamp" => "__nvvm_sust_b_1d_array_v2i64_clamp", + "llvm.nvvm.sust.b.1d.array.v2i64.trap" => "__nvvm_sust_b_1d_array_v2i64_trap", + "llvm.nvvm.sust.b.1d.array.v2i64.zero" => "__nvvm_sust_b_1d_array_v2i64_zero", + "llvm.nvvm.sust.b.1d.array.v2i8.clamp" => "__nvvm_sust_b_1d_array_v2i8_clamp", + "llvm.nvvm.sust.b.1d.array.v2i8.trap" => "__nvvm_sust_b_1d_array_v2i8_trap", + "llvm.nvvm.sust.b.1d.array.v2i8.zero" => "__nvvm_sust_b_1d_array_v2i8_zero", + "llvm.nvvm.sust.b.1d.array.v4i16.clamp" => "__nvvm_sust_b_1d_array_v4i16_clamp", + "llvm.nvvm.sust.b.1d.array.v4i16.trap" => "__nvvm_sust_b_1d_array_v4i16_trap", + "llvm.nvvm.sust.b.1d.array.v4i16.zero" => "__nvvm_sust_b_1d_array_v4i16_zero", + "llvm.nvvm.sust.b.1d.array.v4i32.clamp" => "__nvvm_sust_b_1d_array_v4i32_clamp", + "llvm.nvvm.sust.b.1d.array.v4i32.trap" => "__nvvm_sust_b_1d_array_v4i32_trap", + "llvm.nvvm.sust.b.1d.array.v4i32.zero" => "__nvvm_sust_b_1d_array_v4i32_zero", + "llvm.nvvm.sust.b.1d.array.v4i8.clamp" => "__nvvm_sust_b_1d_array_v4i8_clamp", + "llvm.nvvm.sust.b.1d.array.v4i8.trap" => "__nvvm_sust_b_1d_array_v4i8_trap", + "llvm.nvvm.sust.b.1d.array.v4i8.zero" => "__nvvm_sust_b_1d_array_v4i8_zero", + "llvm.nvvm.sust.b.1d.i16.clamp" => "__nvvm_sust_b_1d_i16_clamp", + "llvm.nvvm.sust.b.1d.i16.trap" => "__nvvm_sust_b_1d_i16_trap", + "llvm.nvvm.sust.b.1d.i16.zero" => "__nvvm_sust_b_1d_i16_zero", + "llvm.nvvm.sust.b.1d.i32.clamp" => "__nvvm_sust_b_1d_i32_clamp", + "llvm.nvvm.sust.b.1d.i32.trap" => "__nvvm_sust_b_1d_i32_trap", + "llvm.nvvm.sust.b.1d.i32.zero" => "__nvvm_sust_b_1d_i32_zero", + "llvm.nvvm.sust.b.1d.i64.clamp" => "__nvvm_sust_b_1d_i64_clamp", + "llvm.nvvm.sust.b.1d.i64.trap" => "__nvvm_sust_b_1d_i64_trap", + "llvm.nvvm.sust.b.1d.i64.zero" => "__nvvm_sust_b_1d_i64_zero", + "llvm.nvvm.sust.b.1d.i8.clamp" => "__nvvm_sust_b_1d_i8_clamp", + "llvm.nvvm.sust.b.1d.i8.trap" => "__nvvm_sust_b_1d_i8_trap", + "llvm.nvvm.sust.b.1d.i8.zero" => "__nvvm_sust_b_1d_i8_zero", + "llvm.nvvm.sust.b.1d.v2i16.clamp" => "__nvvm_sust_b_1d_v2i16_clamp", + "llvm.nvvm.sust.b.1d.v2i16.trap" => "__nvvm_sust_b_1d_v2i16_trap", + "llvm.nvvm.sust.b.1d.v2i16.zero" => "__nvvm_sust_b_1d_v2i16_zero", + "llvm.nvvm.sust.b.1d.v2i32.clamp" => "__nvvm_sust_b_1d_v2i32_clamp", + "llvm.nvvm.sust.b.1d.v2i32.trap" => "__nvvm_sust_b_1d_v2i32_trap", + "llvm.nvvm.sust.b.1d.v2i32.zero" => "__nvvm_sust_b_1d_v2i32_zero", + "llvm.nvvm.sust.b.1d.v2i64.clamp" => "__nvvm_sust_b_1d_v2i64_clamp", + "llvm.nvvm.sust.b.1d.v2i64.trap" => "__nvvm_sust_b_1d_v2i64_trap", + "llvm.nvvm.sust.b.1d.v2i64.zero" => "__nvvm_sust_b_1d_v2i64_zero", + "llvm.nvvm.sust.b.1d.v2i8.clamp" => "__nvvm_sust_b_1d_v2i8_clamp", + "llvm.nvvm.sust.b.1d.v2i8.trap" => "__nvvm_sust_b_1d_v2i8_trap", + "llvm.nvvm.sust.b.1d.v2i8.zero" => "__nvvm_sust_b_1d_v2i8_zero", + "llvm.nvvm.sust.b.1d.v4i16.clamp" => "__nvvm_sust_b_1d_v4i16_clamp", + "llvm.nvvm.sust.b.1d.v4i16.trap" => "__nvvm_sust_b_1d_v4i16_trap", + "llvm.nvvm.sust.b.1d.v4i16.zero" => "__nvvm_sust_b_1d_v4i16_zero", + "llvm.nvvm.sust.b.1d.v4i32.clamp" => "__nvvm_sust_b_1d_v4i32_clamp", + "llvm.nvvm.sust.b.1d.v4i32.trap" => "__nvvm_sust_b_1d_v4i32_trap", + "llvm.nvvm.sust.b.1d.v4i32.zero" => "__nvvm_sust_b_1d_v4i32_zero", + "llvm.nvvm.sust.b.1d.v4i8.clamp" => "__nvvm_sust_b_1d_v4i8_clamp", + "llvm.nvvm.sust.b.1d.v4i8.trap" => "__nvvm_sust_b_1d_v4i8_trap", + "llvm.nvvm.sust.b.1d.v4i8.zero" => "__nvvm_sust_b_1d_v4i8_zero", + "llvm.nvvm.sust.b.2d.array.i16.clamp" => "__nvvm_sust_b_2d_array_i16_clamp", + "llvm.nvvm.sust.b.2d.array.i16.trap" => "__nvvm_sust_b_2d_array_i16_trap", + "llvm.nvvm.sust.b.2d.array.i16.zero" => "__nvvm_sust_b_2d_array_i16_zero", + "llvm.nvvm.sust.b.2d.array.i32.clamp" => "__nvvm_sust_b_2d_array_i32_clamp", + "llvm.nvvm.sust.b.2d.array.i32.trap" => "__nvvm_sust_b_2d_array_i32_trap", + "llvm.nvvm.sust.b.2d.array.i32.zero" => "__nvvm_sust_b_2d_array_i32_zero", + "llvm.nvvm.sust.b.2d.array.i64.clamp" => "__nvvm_sust_b_2d_array_i64_clamp", + "llvm.nvvm.sust.b.2d.array.i64.trap" => "__nvvm_sust_b_2d_array_i64_trap", + "llvm.nvvm.sust.b.2d.array.i64.zero" => "__nvvm_sust_b_2d_array_i64_zero", + "llvm.nvvm.sust.b.2d.array.i8.clamp" => "__nvvm_sust_b_2d_array_i8_clamp", + "llvm.nvvm.sust.b.2d.array.i8.trap" => "__nvvm_sust_b_2d_array_i8_trap", + "llvm.nvvm.sust.b.2d.array.i8.zero" => "__nvvm_sust_b_2d_array_i8_zero", + "llvm.nvvm.sust.b.2d.array.v2i16.clamp" => "__nvvm_sust_b_2d_array_v2i16_clamp", + "llvm.nvvm.sust.b.2d.array.v2i16.trap" => "__nvvm_sust_b_2d_array_v2i16_trap", + "llvm.nvvm.sust.b.2d.array.v2i16.zero" => "__nvvm_sust_b_2d_array_v2i16_zero", + "llvm.nvvm.sust.b.2d.array.v2i32.clamp" => "__nvvm_sust_b_2d_array_v2i32_clamp", + "llvm.nvvm.sust.b.2d.array.v2i32.trap" => "__nvvm_sust_b_2d_array_v2i32_trap", + "llvm.nvvm.sust.b.2d.array.v2i32.zero" => "__nvvm_sust_b_2d_array_v2i32_zero", + "llvm.nvvm.sust.b.2d.array.v2i64.clamp" => "__nvvm_sust_b_2d_array_v2i64_clamp", + "llvm.nvvm.sust.b.2d.array.v2i64.trap" => "__nvvm_sust_b_2d_array_v2i64_trap", + "llvm.nvvm.sust.b.2d.array.v2i64.zero" => "__nvvm_sust_b_2d_array_v2i64_zero", + "llvm.nvvm.sust.b.2d.array.v2i8.clamp" => "__nvvm_sust_b_2d_array_v2i8_clamp", + "llvm.nvvm.sust.b.2d.array.v2i8.trap" => "__nvvm_sust_b_2d_array_v2i8_trap", + "llvm.nvvm.sust.b.2d.array.v2i8.zero" => "__nvvm_sust_b_2d_array_v2i8_zero", + "llvm.nvvm.sust.b.2d.array.v4i16.clamp" => "__nvvm_sust_b_2d_array_v4i16_clamp", + "llvm.nvvm.sust.b.2d.array.v4i16.trap" => "__nvvm_sust_b_2d_array_v4i16_trap", + "llvm.nvvm.sust.b.2d.array.v4i16.zero" => "__nvvm_sust_b_2d_array_v4i16_zero", + "llvm.nvvm.sust.b.2d.array.v4i32.clamp" => "__nvvm_sust_b_2d_array_v4i32_clamp", + "llvm.nvvm.sust.b.2d.array.v4i32.trap" => "__nvvm_sust_b_2d_array_v4i32_trap", + "llvm.nvvm.sust.b.2d.array.v4i32.zero" => "__nvvm_sust_b_2d_array_v4i32_zero", + "llvm.nvvm.sust.b.2d.array.v4i8.clamp" => "__nvvm_sust_b_2d_array_v4i8_clamp", + "llvm.nvvm.sust.b.2d.array.v4i8.trap" => "__nvvm_sust_b_2d_array_v4i8_trap", + "llvm.nvvm.sust.b.2d.array.v4i8.zero" => "__nvvm_sust_b_2d_array_v4i8_zero", + "llvm.nvvm.sust.b.2d.i16.clamp" => "__nvvm_sust_b_2d_i16_clamp", + "llvm.nvvm.sust.b.2d.i16.trap" => "__nvvm_sust_b_2d_i16_trap", + "llvm.nvvm.sust.b.2d.i16.zero" => "__nvvm_sust_b_2d_i16_zero", + "llvm.nvvm.sust.b.2d.i32.clamp" => "__nvvm_sust_b_2d_i32_clamp", + "llvm.nvvm.sust.b.2d.i32.trap" => "__nvvm_sust_b_2d_i32_trap", + "llvm.nvvm.sust.b.2d.i32.zero" => "__nvvm_sust_b_2d_i32_zero", + "llvm.nvvm.sust.b.2d.i64.clamp" => "__nvvm_sust_b_2d_i64_clamp", + "llvm.nvvm.sust.b.2d.i64.trap" => "__nvvm_sust_b_2d_i64_trap", + "llvm.nvvm.sust.b.2d.i64.zero" => "__nvvm_sust_b_2d_i64_zero", + "llvm.nvvm.sust.b.2d.i8.clamp" => "__nvvm_sust_b_2d_i8_clamp", + "llvm.nvvm.sust.b.2d.i8.trap" => "__nvvm_sust_b_2d_i8_trap", + "llvm.nvvm.sust.b.2d.i8.zero" => "__nvvm_sust_b_2d_i8_zero", + "llvm.nvvm.sust.b.2d.v2i16.clamp" => "__nvvm_sust_b_2d_v2i16_clamp", + "llvm.nvvm.sust.b.2d.v2i16.trap" => "__nvvm_sust_b_2d_v2i16_trap", + "llvm.nvvm.sust.b.2d.v2i16.zero" => "__nvvm_sust_b_2d_v2i16_zero", + "llvm.nvvm.sust.b.2d.v2i32.clamp" => "__nvvm_sust_b_2d_v2i32_clamp", + "llvm.nvvm.sust.b.2d.v2i32.trap" => "__nvvm_sust_b_2d_v2i32_trap", + "llvm.nvvm.sust.b.2d.v2i32.zero" => "__nvvm_sust_b_2d_v2i32_zero", + "llvm.nvvm.sust.b.2d.v2i64.clamp" => "__nvvm_sust_b_2d_v2i64_clamp", + "llvm.nvvm.sust.b.2d.v2i64.trap" => "__nvvm_sust_b_2d_v2i64_trap", + "llvm.nvvm.sust.b.2d.v2i64.zero" => "__nvvm_sust_b_2d_v2i64_zero", + "llvm.nvvm.sust.b.2d.v2i8.clamp" => "__nvvm_sust_b_2d_v2i8_clamp", + "llvm.nvvm.sust.b.2d.v2i8.trap" => "__nvvm_sust_b_2d_v2i8_trap", + "llvm.nvvm.sust.b.2d.v2i8.zero" => "__nvvm_sust_b_2d_v2i8_zero", + "llvm.nvvm.sust.b.2d.v4i16.clamp" => "__nvvm_sust_b_2d_v4i16_clamp", + "llvm.nvvm.sust.b.2d.v4i16.trap" => "__nvvm_sust_b_2d_v4i16_trap", + "llvm.nvvm.sust.b.2d.v4i16.zero" => "__nvvm_sust_b_2d_v4i16_zero", + "llvm.nvvm.sust.b.2d.v4i32.clamp" => "__nvvm_sust_b_2d_v4i32_clamp", + "llvm.nvvm.sust.b.2d.v4i32.trap" => "__nvvm_sust_b_2d_v4i32_trap", + "llvm.nvvm.sust.b.2d.v4i32.zero" => "__nvvm_sust_b_2d_v4i32_zero", + "llvm.nvvm.sust.b.2d.v4i8.clamp" => "__nvvm_sust_b_2d_v4i8_clamp", + "llvm.nvvm.sust.b.2d.v4i8.trap" => "__nvvm_sust_b_2d_v4i8_trap", + "llvm.nvvm.sust.b.2d.v4i8.zero" => "__nvvm_sust_b_2d_v4i8_zero", + "llvm.nvvm.sust.b.3d.i16.clamp" => "__nvvm_sust_b_3d_i16_clamp", + "llvm.nvvm.sust.b.3d.i16.trap" => "__nvvm_sust_b_3d_i16_trap", + "llvm.nvvm.sust.b.3d.i16.zero" => "__nvvm_sust_b_3d_i16_zero", + "llvm.nvvm.sust.b.3d.i32.clamp" => "__nvvm_sust_b_3d_i32_clamp", + "llvm.nvvm.sust.b.3d.i32.trap" => "__nvvm_sust_b_3d_i32_trap", + "llvm.nvvm.sust.b.3d.i32.zero" => "__nvvm_sust_b_3d_i32_zero", + "llvm.nvvm.sust.b.3d.i64.clamp" => "__nvvm_sust_b_3d_i64_clamp", + "llvm.nvvm.sust.b.3d.i64.trap" => "__nvvm_sust_b_3d_i64_trap", + "llvm.nvvm.sust.b.3d.i64.zero" => "__nvvm_sust_b_3d_i64_zero", + "llvm.nvvm.sust.b.3d.i8.clamp" => "__nvvm_sust_b_3d_i8_clamp", + "llvm.nvvm.sust.b.3d.i8.trap" => "__nvvm_sust_b_3d_i8_trap", + "llvm.nvvm.sust.b.3d.i8.zero" => "__nvvm_sust_b_3d_i8_zero", + "llvm.nvvm.sust.b.3d.v2i16.clamp" => "__nvvm_sust_b_3d_v2i16_clamp", + "llvm.nvvm.sust.b.3d.v2i16.trap" => "__nvvm_sust_b_3d_v2i16_trap", + "llvm.nvvm.sust.b.3d.v2i16.zero" => "__nvvm_sust_b_3d_v2i16_zero", + "llvm.nvvm.sust.b.3d.v2i32.clamp" => "__nvvm_sust_b_3d_v2i32_clamp", + "llvm.nvvm.sust.b.3d.v2i32.trap" => "__nvvm_sust_b_3d_v2i32_trap", + "llvm.nvvm.sust.b.3d.v2i32.zero" => "__nvvm_sust_b_3d_v2i32_zero", + "llvm.nvvm.sust.b.3d.v2i64.clamp" => "__nvvm_sust_b_3d_v2i64_clamp", + "llvm.nvvm.sust.b.3d.v2i64.trap" => "__nvvm_sust_b_3d_v2i64_trap", + "llvm.nvvm.sust.b.3d.v2i64.zero" => "__nvvm_sust_b_3d_v2i64_zero", + "llvm.nvvm.sust.b.3d.v2i8.clamp" => "__nvvm_sust_b_3d_v2i8_clamp", + "llvm.nvvm.sust.b.3d.v2i8.trap" => "__nvvm_sust_b_3d_v2i8_trap", + "llvm.nvvm.sust.b.3d.v2i8.zero" => "__nvvm_sust_b_3d_v2i8_zero", + "llvm.nvvm.sust.b.3d.v4i16.clamp" => "__nvvm_sust_b_3d_v4i16_clamp", + "llvm.nvvm.sust.b.3d.v4i16.trap" => "__nvvm_sust_b_3d_v4i16_trap", + "llvm.nvvm.sust.b.3d.v4i16.zero" => "__nvvm_sust_b_3d_v4i16_zero", + "llvm.nvvm.sust.b.3d.v4i32.clamp" => "__nvvm_sust_b_3d_v4i32_clamp", + "llvm.nvvm.sust.b.3d.v4i32.trap" => "__nvvm_sust_b_3d_v4i32_trap", + "llvm.nvvm.sust.b.3d.v4i32.zero" => "__nvvm_sust_b_3d_v4i32_zero", + "llvm.nvvm.sust.b.3d.v4i8.clamp" => "__nvvm_sust_b_3d_v4i8_clamp", + "llvm.nvvm.sust.b.3d.v4i8.trap" => "__nvvm_sust_b_3d_v4i8_trap", + "llvm.nvvm.sust.b.3d.v4i8.zero" => "__nvvm_sust_b_3d_v4i8_zero", + "llvm.nvvm.sust.p.1d.array.i16.trap" => "__nvvm_sust_p_1d_array_i16_trap", + "llvm.nvvm.sust.p.1d.array.i32.trap" => "__nvvm_sust_p_1d_array_i32_trap", + "llvm.nvvm.sust.p.1d.array.i8.trap" => "__nvvm_sust_p_1d_array_i8_trap", + "llvm.nvvm.sust.p.1d.array.v2i16.trap" => "__nvvm_sust_p_1d_array_v2i16_trap", + "llvm.nvvm.sust.p.1d.array.v2i32.trap" => "__nvvm_sust_p_1d_array_v2i32_trap", + "llvm.nvvm.sust.p.1d.array.v2i8.trap" => "__nvvm_sust_p_1d_array_v2i8_trap", + "llvm.nvvm.sust.p.1d.array.v4i16.trap" => "__nvvm_sust_p_1d_array_v4i16_trap", + "llvm.nvvm.sust.p.1d.array.v4i32.trap" => "__nvvm_sust_p_1d_array_v4i32_trap", + "llvm.nvvm.sust.p.1d.array.v4i8.trap" => "__nvvm_sust_p_1d_array_v4i8_trap", + "llvm.nvvm.sust.p.1d.i16.trap" => "__nvvm_sust_p_1d_i16_trap", + "llvm.nvvm.sust.p.1d.i32.trap" => "__nvvm_sust_p_1d_i32_trap", + "llvm.nvvm.sust.p.1d.i8.trap" => "__nvvm_sust_p_1d_i8_trap", + "llvm.nvvm.sust.p.1d.v2i16.trap" => "__nvvm_sust_p_1d_v2i16_trap", + "llvm.nvvm.sust.p.1d.v2i32.trap" => "__nvvm_sust_p_1d_v2i32_trap", + "llvm.nvvm.sust.p.1d.v2i8.trap" => "__nvvm_sust_p_1d_v2i8_trap", + "llvm.nvvm.sust.p.1d.v4i16.trap" => "__nvvm_sust_p_1d_v4i16_trap", + "llvm.nvvm.sust.p.1d.v4i32.trap" => "__nvvm_sust_p_1d_v4i32_trap", + "llvm.nvvm.sust.p.1d.v4i8.trap" => "__nvvm_sust_p_1d_v4i8_trap", + "llvm.nvvm.sust.p.2d.array.i16.trap" => "__nvvm_sust_p_2d_array_i16_trap", + "llvm.nvvm.sust.p.2d.array.i32.trap" => "__nvvm_sust_p_2d_array_i32_trap", + "llvm.nvvm.sust.p.2d.array.i8.trap" => "__nvvm_sust_p_2d_array_i8_trap", + "llvm.nvvm.sust.p.2d.array.v2i16.trap" => "__nvvm_sust_p_2d_array_v2i16_trap", + "llvm.nvvm.sust.p.2d.array.v2i32.trap" => "__nvvm_sust_p_2d_array_v2i32_trap", + "llvm.nvvm.sust.p.2d.array.v2i8.trap" => "__nvvm_sust_p_2d_array_v2i8_trap", + "llvm.nvvm.sust.p.2d.array.v4i16.trap" => "__nvvm_sust_p_2d_array_v4i16_trap", + "llvm.nvvm.sust.p.2d.array.v4i32.trap" => "__nvvm_sust_p_2d_array_v4i32_trap", + "llvm.nvvm.sust.p.2d.array.v4i8.trap" => "__nvvm_sust_p_2d_array_v4i8_trap", + "llvm.nvvm.sust.p.2d.i16.trap" => "__nvvm_sust_p_2d_i16_trap", + "llvm.nvvm.sust.p.2d.i32.trap" => "__nvvm_sust_p_2d_i32_trap", + "llvm.nvvm.sust.p.2d.i8.trap" => "__nvvm_sust_p_2d_i8_trap", + "llvm.nvvm.sust.p.2d.v2i16.trap" => "__nvvm_sust_p_2d_v2i16_trap", + "llvm.nvvm.sust.p.2d.v2i32.trap" => "__nvvm_sust_p_2d_v2i32_trap", + "llvm.nvvm.sust.p.2d.v2i8.trap" => "__nvvm_sust_p_2d_v2i8_trap", + "llvm.nvvm.sust.p.2d.v4i16.trap" => "__nvvm_sust_p_2d_v4i16_trap", + "llvm.nvvm.sust.p.2d.v4i32.trap" => "__nvvm_sust_p_2d_v4i32_trap", + "llvm.nvvm.sust.p.2d.v4i8.trap" => "__nvvm_sust_p_2d_v4i8_trap", + "llvm.nvvm.sust.p.3d.i16.trap" => "__nvvm_sust_p_3d_i16_trap", + "llvm.nvvm.sust.p.3d.i32.trap" => "__nvvm_sust_p_3d_i32_trap", + "llvm.nvvm.sust.p.3d.i8.trap" => "__nvvm_sust_p_3d_i8_trap", + "llvm.nvvm.sust.p.3d.v2i16.trap" => "__nvvm_sust_p_3d_v2i16_trap", + "llvm.nvvm.sust.p.3d.v2i32.trap" => "__nvvm_sust_p_3d_v2i32_trap", + "llvm.nvvm.sust.p.3d.v2i8.trap" => "__nvvm_sust_p_3d_v2i8_trap", + "llvm.nvvm.sust.p.3d.v4i16.trap" => "__nvvm_sust_p_3d_v4i16_trap", + "llvm.nvvm.sust.p.3d.v4i32.trap" => "__nvvm_sust_p_3d_v4i32_trap", + "llvm.nvvm.sust.p.3d.v4i8.trap" => "__nvvm_sust_p_3d_v4i8_trap", + "llvm.nvvm.swap.lo.hi.b64" => "__nvvm_swap_lo_hi_b64", + "llvm.nvvm.trunc.d" => "__nvvm_trunc_d", + "llvm.nvvm.trunc.f" => "__nvvm_trunc_f", + "llvm.nvvm.trunc.ftz.f" => "__nvvm_trunc_ftz_f", + "llvm.nvvm.txq.array.size" => "__nvvm_txq_array_size", + "llvm.nvvm.txq.channel.data.type" => "__nvvm_txq_channel_data_type", + "llvm.nvvm.txq.channel.order" => "__nvvm_txq_channel_order", + "llvm.nvvm.txq.depth" => "__nvvm_txq_depth", + "llvm.nvvm.txq.height" => "__nvvm_txq_height", + "llvm.nvvm.txq.num.mipmap.levels" => "__nvvm_txq_num_mipmap_levels", + "llvm.nvvm.txq.num.samples" => "__nvvm_txq_num_samples", + "llvm.nvvm.txq.width" => "__nvvm_txq_width", + "llvm.nvvm.ui2d.rm" => "__nvvm_ui2d_rm", + "llvm.nvvm.ui2d.rn" => "__nvvm_ui2d_rn", + "llvm.nvvm.ui2d.rp" => "__nvvm_ui2d_rp", + "llvm.nvvm.ui2d.rz" => "__nvvm_ui2d_rz", + "llvm.nvvm.ui2f.rm" => "__nvvm_ui2f_rm", + "llvm.nvvm.ui2f.rn" => "__nvvm_ui2f_rn", + "llvm.nvvm.ui2f.rp" => "__nvvm_ui2f_rp", + "llvm.nvvm.ui2f.rz" => "__nvvm_ui2f_rz", + "llvm.nvvm.ull2d.rm" => "__nvvm_ull2d_rm", + "llvm.nvvm.ull2d.rn" => "__nvvm_ull2d_rn", + "llvm.nvvm.ull2d.rp" => "__nvvm_ull2d_rp", + "llvm.nvvm.ull2d.rz" => "__nvvm_ull2d_rz", + "llvm.nvvm.ull2f.rm" => "__nvvm_ull2f_rm", + "llvm.nvvm.ull2f.rn" => "__nvvm_ull2f_rn", + "llvm.nvvm.ull2f.rp" => "__nvvm_ull2f_rp", + "llvm.nvvm.ull2f.rz" => "__nvvm_ull2f_rz", // ppc "llvm.ppc.addex" => "__builtin_ppc_addex", "llvm.ppc.addf128.round.to.odd" => "__builtin_addf128_round_to_odd", @@ -909,8 +2321,21 @@ match name { "llvm.ppc.altivec.mtvsrhm" => "__builtin_altivec_mtvsrhm", "llvm.ppc.altivec.mtvsrqm" => "__builtin_altivec_mtvsrqm", "llvm.ppc.altivec.mtvsrwm" => "__builtin_altivec_mtvsrwm", + "llvm.ppc.altivec.vaddcuw" => "__builtin_altivec_vaddcuw", "llvm.ppc.altivec.vaddecuq" => "__builtin_altivec_vaddecuq", "llvm.ppc.altivec.vaddeuqm" => "__builtin_altivec_vaddeuqm", + "llvm.ppc.altivec.vaddsbs" => "__builtin_altivec_vaddsbs", + "llvm.ppc.altivec.vaddshs" => "__builtin_altivec_vaddshs", + "llvm.ppc.altivec.vaddsws" => "__builtin_altivec_vaddsws", + "llvm.ppc.altivec.vaddubs" => "__builtin_altivec_vaddubs", + "llvm.ppc.altivec.vadduhs" => "__builtin_altivec_vadduhs", + "llvm.ppc.altivec.vadduws" => "__builtin_altivec_vadduws", + "llvm.ppc.altivec.vavgsb" => "__builtin_altivec_vavgsb", + "llvm.ppc.altivec.vavgsh" => "__builtin_altivec_vavgsh", + "llvm.ppc.altivec.vavgsw" => "__builtin_altivec_vavgsw", + "llvm.ppc.altivec.vavgub" => "__builtin_altivec_vavgub", + "llvm.ppc.altivec.vavguh" => "__builtin_altivec_vavguh", + "llvm.ppc.altivec.vavguw" => "__builtin_altivec_vavguw", "llvm.ppc.altivec.vbpermd" => "__builtin_altivec_vbpermd", "llvm.ppc.altivec.vbpermq" => "__builtin_altivec_vbpermq", "llvm.ppc.altivec.vcfsx" => "__builtin_altivec_vcfsx", @@ -983,6 +2408,7 @@ match name { "llvm.ppc.altivec.vexpandhm" => "__builtin_altivec_vexpandhm", "llvm.ppc.altivec.vexpandqm" => "__builtin_altivec_vexpandqm", "llvm.ppc.altivec.vexpandwm" => "__builtin_altivec_vexpandwm", + "llvm.ppc.altivec.vexptefp" => "__builtin_altivec_vexptefp", "llvm.ppc.altivec.vextddvlx" => "__builtin_altivec_vextddvlx", "llvm.ppc.altivec.vextddvrx" => "__builtin_altivec_vextddvrx", "llvm.ppc.altivec.vextdubvlx" => "__builtin_altivec_vextdubvlx", @@ -1018,9 +2444,24 @@ match name { "llvm.ppc.altivec.vinswrx" => "__builtin_altivec_vinswrx", "llvm.ppc.altivec.vinswvlx" => "__builtin_altivec_vinswvlx", "llvm.ppc.altivec.vinswvrx" => "__builtin_altivec_vinswvrx", + "llvm.ppc.altivec.vlogefp" => "__builtin_altivec_vlogefp", "llvm.ppc.altivec.vmaddfp" => "__builtin_altivec_vmaddfp", + "llvm.ppc.altivec.vmaxfp" => "__builtin_altivec_vmaxfp", + "llvm.ppc.altivec.vmaxsb" => "__builtin_altivec_vmaxsb", + "llvm.ppc.altivec.vmaxsh" => "__builtin_altivec_vmaxsh", + "llvm.ppc.altivec.vmaxsw" => "__builtin_altivec_vmaxsw", + "llvm.ppc.altivec.vmaxub" => "__builtin_altivec_vmaxub", + "llvm.ppc.altivec.vmaxuh" => "__builtin_altivec_vmaxuh", + "llvm.ppc.altivec.vmaxuw" => "__builtin_altivec_vmaxuw", "llvm.ppc.altivec.vmhaddshs" => "__builtin_altivec_vmhaddshs", "llvm.ppc.altivec.vmhraddshs" => "__builtin_altivec_vmhraddshs", + "llvm.ppc.altivec.vminfp" => "__builtin_altivec_vminfp", + "llvm.ppc.altivec.vminsb" => "__builtin_altivec_vminsb", + "llvm.ppc.altivec.vminsh" => "__builtin_altivec_vminsh", + "llvm.ppc.altivec.vminsw" => "__builtin_altivec_vminsw", + "llvm.ppc.altivec.vminub" => "__builtin_altivec_vminub", + "llvm.ppc.altivec.vminuh" => "__builtin_altivec_vminuh", + "llvm.ppc.altivec.vminuw" => "__builtin_altivec_vminuw", "llvm.ppc.altivec.vmladduhm" => "__builtin_altivec_vmladduhm", "llvm.ppc.altivec.vmsumcud" => "__builtin_altivec_vmsumcud", "llvm.ppc.altivec.vmsummbm" => "__builtin_altivec_vmsummbm", @@ -1059,13 +2500,31 @@ match name { "llvm.ppc.altivec.vprtybd" => "__builtin_altivec_vprtybd", "llvm.ppc.altivec.vprtybq" => "__builtin_altivec_vprtybq", "llvm.ppc.altivec.vprtybw" => "__builtin_altivec_vprtybw", + "llvm.ppc.altivec.vrefp" => "__builtin_altivec_vrefp", "llvm.ppc.altivec.vrfim" => "__builtin_altivec_vrfim", "llvm.ppc.altivec.vrfin" => "__builtin_altivec_vrfin", "llvm.ppc.altivec.vrfip" => "__builtin_altivec_vrfip", "llvm.ppc.altivec.vrfiz" => "__builtin_altivec_vrfiz", + "llvm.ppc.altivec.vrlb" => "__builtin_altivec_vrlb", + "llvm.ppc.altivec.vrlh" => "__builtin_altivec_vrlh", + "llvm.ppc.altivec.vrlw" => "__builtin_altivec_vrlw", + "llvm.ppc.altivec.vrsqrtefp" => "__builtin_altivec_vrsqrtefp", "llvm.ppc.altivec.vsel" => "__builtin_altivec_vsel_4si", + "llvm.ppc.altivec.vsl" => "__builtin_altivec_vsl", + "llvm.ppc.altivec.vslb" => "__builtin_altivec_vslb", "llvm.ppc.altivec.vsldbi" => "__builtin_altivec_vsldbi", + "llvm.ppc.altivec.vslh" => "__builtin_altivec_vslh", + "llvm.ppc.altivec.vslo" => "__builtin_altivec_vslo", + "llvm.ppc.altivec.vslw" => "__builtin_altivec_vslw", + "llvm.ppc.altivec.vsr" => "__builtin_altivec_vsr", + "llvm.ppc.altivec.vsrab" => "__builtin_altivec_vsrab", + "llvm.ppc.altivec.vsrah" => "__builtin_altivec_vsrah", + "llvm.ppc.altivec.vsraw" => "__builtin_altivec_vsraw", + "llvm.ppc.altivec.vsrb" => "__builtin_altivec_vsrb", "llvm.ppc.altivec.vsrdbi" => "__builtin_altivec_vsrdbi", + "llvm.ppc.altivec.vsrh" => "__builtin_altivec_vsrh", + "llvm.ppc.altivec.vsro" => "__builtin_altivec_vsro", + "llvm.ppc.altivec.vsrw" => "__builtin_altivec_vsrw", "llvm.ppc.altivec.vstribl" => "__builtin_altivec_vstribl", "llvm.ppc.altivec.vstribl.p" => "__builtin_altivec_vstribl_p", "llvm.ppc.altivec.vstribr" => "__builtin_altivec_vstribr", @@ -1074,8 +2533,15 @@ match name { "llvm.ppc.altivec.vstrihl.p" => "__builtin_altivec_vstrihl_p", "llvm.ppc.altivec.vstrihr" => "__builtin_altivec_vstrihr", "llvm.ppc.altivec.vstrihr.p" => "__builtin_altivec_vstrihr_p", + "llvm.ppc.altivec.vsubcuw" => "__builtin_altivec_vsubcuw", "llvm.ppc.altivec.vsubecuq" => "__builtin_altivec_vsubecuq", "llvm.ppc.altivec.vsubeuqm" => "__builtin_altivec_vsubeuqm", + "llvm.ppc.altivec.vsubsbs" => "__builtin_altivec_vsubsbs", + "llvm.ppc.altivec.vsubshs" => "__builtin_altivec_vsubshs", + "llvm.ppc.altivec.vsubsws" => "__builtin_altivec_vsubsws", + "llvm.ppc.altivec.vsububs" => "__builtin_altivec_vsububs", + "llvm.ppc.altivec.vsubuhs" => "__builtin_altivec_vsubuhs", + "llvm.ppc.altivec.vsubuws" => "__builtin_altivec_vsubuws", "llvm.ppc.altivec.vsum2sws" => "__builtin_altivec_vsum2sws", "llvm.ppc.altivec.vsum4sbs" => "__builtin_altivec_vsum4sbs", "llvm.ppc.altivec.vsum4shs" => "__builtin_altivec_vsum4shs", @@ -1224,6 +2690,25 @@ match name { "llvm.ppc.vsx.xvrsqrtedp" => "__builtin_vsx_xvrsqrtedp", "llvm.ppc.vsx.xvrsqrtesp" => "__builtin_vsx_xvrsqrtesp", "llvm.ppc.vsx.xxpermx" => "__builtin_vsx_xxpermx", + // ptx + "llvm.ptx.bar.sync" => "__builtin_ptx_bar_sync", + "llvm.ptx.read.clock" => "__builtin_ptx_read_clock", + "llvm.ptx.read.clock64" => "__builtin_ptx_read_clock64", + "llvm.ptx.read.gridid" => "__builtin_ptx_read_gridid", + "llvm.ptx.read.laneid" => "__builtin_ptx_read_laneid", + "llvm.ptx.read.lanemask.eq" => "__builtin_ptx_read_lanemask_eq", + "llvm.ptx.read.lanemask.ge" => "__builtin_ptx_read_lanemask_ge", + "llvm.ptx.read.lanemask.gt" => "__builtin_ptx_read_lanemask_gt", + "llvm.ptx.read.lanemask.le" => "__builtin_ptx_read_lanemask_le", + "llvm.ptx.read.lanemask.lt" => "__builtin_ptx_read_lanemask_lt", + "llvm.ptx.read.nsmid" => "__builtin_ptx_read_nsmid", + "llvm.ptx.read.nwarpid" => "__builtin_ptx_read_nwarpid", + "llvm.ptx.read.pm0" => "__builtin_ptx_read_pm0", + "llvm.ptx.read.pm1" => "__builtin_ptx_read_pm1", + "llvm.ptx.read.pm2" => "__builtin_ptx_read_pm2", + "llvm.ptx.read.pm3" => "__builtin_ptx_read_pm3", + "llvm.ptx.read.smid" => "__builtin_ptx_read_smid", + "llvm.ptx.read.warpid" => "__builtin_ptx_read_warpid", // s390 "llvm.s390.efpc" => "__builtin_s390_efpc", "llvm.s390.etnd" => "__builtin_tx_nesting_depth", @@ -1278,6 +2763,10 @@ match name { "llvm.x86.3dnowa.pfnacc" => "__builtin_ia32_pfnacc", "llvm.x86.3dnowa.pfpnacc" => "__builtin_ia32_pfpnacc", "llvm.x86.3dnowa.pi2fw" => "__builtin_ia32_pi2fw", + "llvm.x86.addcarry.u32" => "__builtin_ia32_addcarry_u32", + "llvm.x86.addcarry.u64" => "__builtin_ia32_addcarry_u64", + "llvm.x86.addcarryx.u32" => "__builtin_ia32_addcarryx_u32", + "llvm.x86.addcarryx.u64" => "__builtin_ia32_addcarryx_u64", "llvm.x86.aesni.aesdec" => "__builtin_ia32_aesdec128", "llvm.x86.aesni.aesdec.256" => "__builtin_ia32_aesdec256", "llvm.x86.aesni.aesdec.512" => "__builtin_ia32_aesdec512", @@ -1294,11 +2783,18 @@ match name { "llvm.x86.aesni.aeskeygenassist" => "__builtin_ia32_aeskeygenassist128", "llvm.x86.avx.addsub.pd.256" => "__builtin_ia32_addsubpd256", "llvm.x86.avx.addsub.ps.256" => "__builtin_ia32_addsubps256", + "llvm.x86.avx.blend.pd.256" => "__builtin_ia32_blendpd256", + "llvm.x86.avx.blend.ps.256" => "__builtin_ia32_blendps256", "llvm.x86.avx.blendv.pd.256" => "__builtin_ia32_blendvpd256", "llvm.x86.avx.blendv.ps.256" => "__builtin_ia32_blendvps256", + "llvm.x86.avx.cmp.pd.256" => "__builtin_ia32_cmppd256", + "llvm.x86.avx.cmp.ps.256" => "__builtin_ia32_cmpps256", "llvm.x86.avx.cvt.pd2.ps.256" => "__builtin_ia32_cvtpd2ps256", "llvm.x86.avx.cvt.pd2dq.256" => "__builtin_ia32_cvtpd2dq256", + "llvm.x86.avx.cvt.ps2.pd.256" => "__builtin_ia32_cvtps2pd256", "llvm.x86.avx.cvt.ps2dq.256" => "__builtin_ia32_cvtps2dq256", + "llvm.x86.avx.cvtdq2.pd.256" => "__builtin_ia32_cvtdq2pd256", + "llvm.x86.avx.cvtdq2.ps.256" => "__builtin_ia32_cvtdq2ps256", "llvm.x86.avx.cvtt.pd2dq.256" => "__builtin_ia32_cvttpd2dq256", "llvm.x86.avx.cvtt.ps2dq.256" => "__builtin_ia32_cvttps2dq256", "llvm.x86.avx.dp.ps.256" => "__builtin_ia32_dpps256", @@ -1328,6 +2824,22 @@ match name { "llvm.x86.avx.round.pd.256" => "__builtin_ia32_roundpd256", "llvm.x86.avx.round.ps.256" => "__builtin_ia32_roundps256", "llvm.x86.avx.rsqrt.ps.256" => "__builtin_ia32_rsqrtps256", + "llvm.x86.avx.sqrt.pd.256" => "__builtin_ia32_sqrtpd256", + "llvm.x86.avx.sqrt.ps.256" => "__builtin_ia32_sqrtps256", + "llvm.x86.avx.storeu.dq.256" => "__builtin_ia32_storedqu256", + "llvm.x86.avx.storeu.pd.256" => "__builtin_ia32_storeupd256", + "llvm.x86.avx.storeu.ps.256" => "__builtin_ia32_storeups256", + "llvm.x86.avx.vbroadcastf128.pd.256" => "__builtin_ia32_vbroadcastf128_pd256", + "llvm.x86.avx.vbroadcastf128.ps.256" => "__builtin_ia32_vbroadcastf128_ps256", + "llvm.x86.avx.vextractf128.pd.256" => "__builtin_ia32_vextractf128_pd256", + "llvm.x86.avx.vextractf128.ps.256" => "__builtin_ia32_vextractf128_ps256", + "llvm.x86.avx.vextractf128.si.256" => "__builtin_ia32_vextractf128_si256", + "llvm.x86.avx.vinsertf128.pd.256" => "__builtin_ia32_vinsertf128_pd256", + "llvm.x86.avx.vinsertf128.ps.256" => "__builtin_ia32_vinsertf128_ps256", + "llvm.x86.avx.vinsertf128.si.256" => "__builtin_ia32_vinsertf128_si256", + "llvm.x86.avx.vperm2f128.pd.256" => "__builtin_ia32_vperm2f128_pd256", + "llvm.x86.avx.vperm2f128.ps.256" => "__builtin_ia32_vperm2f128_ps256", + "llvm.x86.avx.vperm2f128.si.256" => "__builtin_ia32_vperm2f128_si256", "llvm.x86.avx.vpermilvar.pd" => "__builtin_ia32_vpermilvarpd", "llvm.x86.avx.vpermilvar.pd.256" => "__builtin_ia32_vpermilvarpd256", "llvm.x86.avx.vpermilvar.ps" => "__builtin_ia32_vpermilvarps", @@ -1370,14 +2882,33 @@ match name { "llvm.x86.avx2.maskstore.d.256" => "__builtin_ia32_maskstored256", "llvm.x86.avx2.maskstore.q" => "__builtin_ia32_maskstoreq", "llvm.x86.avx2.maskstore.q.256" => "__builtin_ia32_maskstoreq256", + "llvm.x86.avx2.movntdqa" => "__builtin_ia32_movntdqa256", "llvm.x86.avx2.mpsadbw" => "__builtin_ia32_mpsadbw256", + "llvm.x86.avx2.pabs.b" => "__builtin_ia32_pabsb256", + "llvm.x86.avx2.pabs.d" => "__builtin_ia32_pabsd256", + "llvm.x86.avx2.pabs.w" => "__builtin_ia32_pabsw256", "llvm.x86.avx2.packssdw" => "__builtin_ia32_packssdw256", "llvm.x86.avx2.packsswb" => "__builtin_ia32_packsswb256", "llvm.x86.avx2.packusdw" => "__builtin_ia32_packusdw256", "llvm.x86.avx2.packuswb" => "__builtin_ia32_packuswb256", + "llvm.x86.avx2.padds.b" => "__builtin_ia32_paddsb256", + "llvm.x86.avx2.padds.w" => "__builtin_ia32_paddsw256", + "llvm.x86.avx2.paddus.b" => "__builtin_ia32_paddusb256", + "llvm.x86.avx2.paddus.w" => "__builtin_ia32_paddusw256", "llvm.x86.avx2.pavg.b" => "__builtin_ia32_pavgb256", "llvm.x86.avx2.pavg.w" => "__builtin_ia32_pavgw256", + "llvm.x86.avx2.pblendd.128" => "__builtin_ia32_pblendd128", + "llvm.x86.avx2.pblendd.256" => "__builtin_ia32_pblendd256", "llvm.x86.avx2.pblendvb" => "__builtin_ia32_pblendvb256", + "llvm.x86.avx2.pblendw" => "__builtin_ia32_pblendw256", + "llvm.x86.avx2.pbroadcastb.128" => "__builtin_ia32_pbroadcastb128", + "llvm.x86.avx2.pbroadcastb.256" => "__builtin_ia32_pbroadcastb256", + "llvm.x86.avx2.pbroadcastd.128" => "__builtin_ia32_pbroadcastd128", + "llvm.x86.avx2.pbroadcastd.256" => "__builtin_ia32_pbroadcastd256", + "llvm.x86.avx2.pbroadcastq.128" => "__builtin_ia32_pbroadcastq128", + "llvm.x86.avx2.pbroadcastq.256" => "__builtin_ia32_pbroadcastq256", + "llvm.x86.avx2.pbroadcastw.128" => "__builtin_ia32_pbroadcastw128", + "llvm.x86.avx2.pbroadcastw.256" => "__builtin_ia32_pbroadcastw256", "llvm.x86.avx2.permd" => "__builtin_ia32_permvarsi256", "llvm.x86.avx2.permps" => "__builtin_ia32_permvarsf256", "llvm.x86.avx2.phadd.d" => "__builtin_ia32_phaddd256", @@ -1388,16 +2919,44 @@ match name { "llvm.x86.avx2.phsub.w" => "__builtin_ia32_phsubw256", "llvm.x86.avx2.pmadd.ub.sw" => "__builtin_ia32_pmaddubsw256", "llvm.x86.avx2.pmadd.wd" => "__builtin_ia32_pmaddwd256", + "llvm.x86.avx2.pmaxs.b" => "__builtin_ia32_pmaxsb256", + "llvm.x86.avx2.pmaxs.d" => "__builtin_ia32_pmaxsd256", + "llvm.x86.avx2.pmaxs.w" => "__builtin_ia32_pmaxsw256", + "llvm.x86.avx2.pmaxu.b" => "__builtin_ia32_pmaxub256", + "llvm.x86.avx2.pmaxu.d" => "__builtin_ia32_pmaxud256", + "llvm.x86.avx2.pmaxu.w" => "__builtin_ia32_pmaxuw256", + "llvm.x86.avx2.pmins.b" => "__builtin_ia32_pminsb256", + "llvm.x86.avx2.pmins.d" => "__builtin_ia32_pminsd256", + "llvm.x86.avx2.pmins.w" => "__builtin_ia32_pminsw256", + "llvm.x86.avx2.pminu.b" => "__builtin_ia32_pminub256", + "llvm.x86.avx2.pminu.d" => "__builtin_ia32_pminud256", + "llvm.x86.avx2.pminu.w" => "__builtin_ia32_pminuw256", "llvm.x86.avx2.pmovmskb" => "__builtin_ia32_pmovmskb256", + "llvm.x86.avx2.pmovsxbd" => "__builtin_ia32_pmovsxbd256", + "llvm.x86.avx2.pmovsxbq" => "__builtin_ia32_pmovsxbq256", + "llvm.x86.avx2.pmovsxbw" => "__builtin_ia32_pmovsxbw256", + "llvm.x86.avx2.pmovsxdq" => "__builtin_ia32_pmovsxdq256", + "llvm.x86.avx2.pmovsxwd" => "__builtin_ia32_pmovsxwd256", + "llvm.x86.avx2.pmovsxwq" => "__builtin_ia32_pmovsxwq256", + "llvm.x86.avx2.pmovzxbd" => "__builtin_ia32_pmovzxbd256", + "llvm.x86.avx2.pmovzxbq" => "__builtin_ia32_pmovzxbq256", + "llvm.x86.avx2.pmovzxbw" => "__builtin_ia32_pmovzxbw256", + "llvm.x86.avx2.pmovzxdq" => "__builtin_ia32_pmovzxdq256", + "llvm.x86.avx2.pmovzxwd" => "__builtin_ia32_pmovzxwd256", + "llvm.x86.avx2.pmovzxwq" => "__builtin_ia32_pmovzxwq256", + "llvm.x86.avx2.pmul.dq" => "__builtin_ia32_pmuldq256", "llvm.x86.avx2.pmul.hr.sw" => "__builtin_ia32_pmulhrsw256", "llvm.x86.avx2.pmulh.w" => "__builtin_ia32_pmulhw256", "llvm.x86.avx2.pmulhu.w" => "__builtin_ia32_pmulhuw256", + "llvm.x86.avx2.pmulu.dq" => "__builtin_ia32_pmuludq256", "llvm.x86.avx2.psad.bw" => "__builtin_ia32_psadbw256", "llvm.x86.avx2.pshuf.b" => "__builtin_ia32_pshufb256", "llvm.x86.avx2.psign.b" => "__builtin_ia32_psignb256", "llvm.x86.avx2.psign.d" => "__builtin_ia32_psignd256", "llvm.x86.avx2.psign.w" => "__builtin_ia32_psignw256", "llvm.x86.avx2.psll.d" => "__builtin_ia32_pslld256", + "llvm.x86.avx2.psll.dq" => "__builtin_ia32_pslldqi256", + "llvm.x86.avx2.psll.dq.bs" => "__builtin_ia32_pslldqi256_byteshift", "llvm.x86.avx2.psll.q" => "__builtin_ia32_psllq256", "llvm.x86.avx2.psll.w" => "__builtin_ia32_psllw256", "llvm.x86.avx2.pslli.d" => "__builtin_ia32_pslldi256", @@ -1414,6 +2973,8 @@ match name { "llvm.x86.avx2.psrav.d" => "__builtin_ia32_psrav4si", "llvm.x86.avx2.psrav.d.256" => "__builtin_ia32_psrav8si", "llvm.x86.avx2.psrl.d" => "__builtin_ia32_psrld256", + "llvm.x86.avx2.psrl.dq" => "__builtin_ia32_psrldqi256", + "llvm.x86.avx2.psrl.dq.bs" => "__builtin_ia32_psrldqi256_byteshift", "llvm.x86.avx2.psrl.q" => "__builtin_ia32_psrlq256", "llvm.x86.avx2.psrl.w" => "__builtin_ia32_psrlw256", "llvm.x86.avx2.psrli.d" => "__builtin_ia32_psrldi256", @@ -1423,6 +2984,16 @@ match name { "llvm.x86.avx2.psrlv.d.256" => "__builtin_ia32_psrlv8si", "llvm.x86.avx2.psrlv.q" => "__builtin_ia32_psrlv2di", "llvm.x86.avx2.psrlv.q.256" => "__builtin_ia32_psrlv4di", + "llvm.x86.avx2.psubs.b" => "__builtin_ia32_psubsb256", + "llvm.x86.avx2.psubs.w" => "__builtin_ia32_psubsw256", + "llvm.x86.avx2.psubus.b" => "__builtin_ia32_psubusb256", + "llvm.x86.avx2.psubus.w" => "__builtin_ia32_psubusw256", + "llvm.x86.avx2.vbroadcast.sd.pd.256" => "__builtin_ia32_vbroadcastsd_pd256", + "llvm.x86.avx2.vbroadcast.ss.ps" => "__builtin_ia32_vbroadcastss_ps", + "llvm.x86.avx2.vbroadcast.ss.ps.256" => "__builtin_ia32_vbroadcastss_ps256", + "llvm.x86.avx2.vextracti128" => "__builtin_ia32_extract128i256", + "llvm.x86.avx2.vinserti128" => "__builtin_ia32_insert128i256", + "llvm.x86.avx2.vperm2i128" => "__builtin_ia32_permti256", "llvm.x86.avx512.add.pd.512" => "__builtin_ia32_addpd512", "llvm.x86.avx512.add.ps.512" => "__builtin_ia32_addps512", "llvm.x86.avx512.broadcastmb.128" => "__builtin_ia32_broadcastmb128", @@ -1437,20 +3008,32 @@ match name { "llvm.x86.avx512.conflict.q.128" => "__builtin_ia32_vpconflictdi_128", "llvm.x86.avx512.conflict.q.256" => "__builtin_ia32_vpconflictdi_256", "llvm.x86.avx512.conflict.q.512" => "__builtin_ia32_vpconflictdi_512", + "llvm.x86.avx512.cvtsd2usi" => "__builtin_ia32_cvtsd2usi", + "llvm.x86.avx512.cvtsd2usi64" => "__builtin_ia32_cvtsd2usi64", "llvm.x86.avx512.cvtsi2sd64" => "__builtin_ia32_cvtsi2sd64", "llvm.x86.avx512.cvtsi2ss32" => "__builtin_ia32_cvtsi2ss32", "llvm.x86.avx512.cvtsi2ss64" => "__builtin_ia32_cvtsi2ss64", + "llvm.x86.avx512.cvtss2usi" => "__builtin_ia32_cvtss2usi", + "llvm.x86.avx512.cvtss2usi64" => "__builtin_ia32_cvtss2usi64", "llvm.x86.avx512.cvttsd2si" => "__builtin_ia32_vcvttsd2si32", "llvm.x86.avx512.cvttsd2si64" => "__builtin_ia32_vcvttsd2si64", - "llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_vcvttsd2usi32", - "llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_vcvttsd2usi64", + "llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_cvttsd2usi", + // [DUPLICATE]: "llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_vcvttsd2usi32", + "llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_cvttsd2usi64", + // [DUPLICATE]: "llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_vcvttsd2usi64", "llvm.x86.avx512.cvttss2si" => "__builtin_ia32_vcvttss2si32", "llvm.x86.avx512.cvttss2si64" => "__builtin_ia32_vcvttss2si64", - "llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_vcvttss2usi32", - "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_vcvttss2usi64", - "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss32", + "llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_cvttss2usi", + // [DUPLICATE]: "llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_vcvttss2usi32", + "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_cvttss2usi64", + // [DUPLICATE]: "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_vcvttss2usi64", + "llvm.x86.avx512.cvtusi2sd" => "__builtin_ia32_cvtusi2sd", + "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss", + // [DUPLICATE]: "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss32", "llvm.x86.avx512.cvtusi642sd" => "__builtin_ia32_cvtusi2sd64", + // [DUPLICATE]: "llvm.x86.avx512.cvtusi642sd" => "__builtin_ia32_cvtusi642sd", "llvm.x86.avx512.cvtusi642ss" => "__builtin_ia32_cvtusi2ss64", + // [DUPLICATE]: "llvm.x86.avx512.cvtusi642ss" => "__builtin_ia32_cvtusi642ss", "llvm.x86.avx512.dbpsadbw.128" => "__builtin_ia32_dbpsadbw128", "llvm.x86.avx512.dbpsadbw.256" => "__builtin_ia32_dbpsadbw256", "llvm.x86.avx512.dbpsadbw.512" => "__builtin_ia32_dbpsadbw512", @@ -1458,14 +3041,41 @@ match name { "llvm.x86.avx512.div.ps.512" => "__builtin_ia32_divps512", "llvm.x86.avx512.exp2.pd" => "__builtin_ia32_exp2pd_mask", "llvm.x86.avx512.exp2.ps" => "__builtin_ia32_exp2ps_mask", + "llvm.x86.avx512.gather.dpd.512" => "__builtin_ia32_gathersiv8df", + "llvm.x86.avx512.gather.dpi.512" => "__builtin_ia32_gathersiv16si", + "llvm.x86.avx512.gather.dpq.512" => "__builtin_ia32_gathersiv8di", + "llvm.x86.avx512.gather.dps.512" => "__builtin_ia32_gathersiv16sf", + "llvm.x86.avx512.gather.qpd.512" => "__builtin_ia32_gatherdiv8df", + "llvm.x86.avx512.gather.qpi.512" => "__builtin_ia32_gatherdiv16si", + "llvm.x86.avx512.gather.qpq.512" => "__builtin_ia32_gatherdiv8di", + "llvm.x86.avx512.gather.qps.512" => "__builtin_ia32_gatherdiv16sf", "llvm.x86.avx512.gatherpf.dpd.512" => "__builtin_ia32_gatherpfdpd", "llvm.x86.avx512.gatherpf.dps.512" => "__builtin_ia32_gatherpfdps", "llvm.x86.avx512.gatherpf.qpd.512" => "__builtin_ia32_gatherpfqpd", "llvm.x86.avx512.gatherpf.qps.512" => "__builtin_ia32_gatherpfqps", + "llvm.x86.avx512.kand.w" => "__builtin_ia32_kandhi", + "llvm.x86.avx512.kandn.w" => "__builtin_ia32_kandnhi", + "llvm.x86.avx512.knot.w" => "__builtin_ia32_knothi", + "llvm.x86.avx512.kor.w" => "__builtin_ia32_korhi", + "llvm.x86.avx512.kortestc.w" => "__builtin_ia32_kortestchi", + "llvm.x86.avx512.kortestz.w" => "__builtin_ia32_kortestzhi", + "llvm.x86.avx512.kunpck.bw" => "__builtin_ia32_kunpckhi", + "llvm.x86.avx512.kxnor.w" => "__builtin_ia32_kxnorhi", + "llvm.x86.avx512.kxor.w" => "__builtin_ia32_kxorhi", "llvm.x86.avx512.mask.add.sd.round" => "__builtin_ia32_addsd_round_mask", "llvm.x86.avx512.mask.add.ss.round" => "__builtin_ia32_addss_round_mask", + "llvm.x86.avx512.mask.blend.d.512" => "__builtin_ia32_blendmd_512_mask", + "llvm.x86.avx512.mask.blend.pd.512" => "__builtin_ia32_blendmpd_512_mask", + "llvm.x86.avx512.mask.blend.ps.512" => "__builtin_ia32_blendmps_512_mask", + "llvm.x86.avx512.mask.blend.q.512" => "__builtin_ia32_blendmq_512_mask", + "llvm.x86.avx512.mask.cmp.pd.512" => "__builtin_ia32_cmppd512_mask", + "llvm.x86.avx512.mask.cmp.ps.512" => "__builtin_ia32_cmpps512_mask", "llvm.x86.avx512.mask.cmp.sd" => "__builtin_ia32_cmpsd_mask", "llvm.x86.avx512.mask.cmp.ss" => "__builtin_ia32_cmpss_mask", + "llvm.x86.avx512.mask.conflict.d.512" => "__builtin_ia32_vpconflictsi_512_mask", + "llvm.x86.avx512.mask.conflict.q.512" => "__builtin_ia32_vpconflictdi_512_mask", + "llvm.x86.avx512.mask.cvtdq2pd.512" => "__builtin_ia32_cvtdq2pd512_mask", + "llvm.x86.avx512.mask.cvtdq2ps.512" => "__builtin_ia32_cvtdq2ps512_mask", "llvm.x86.avx512.mask.cvtpd2dq.128" => "__builtin_ia32_cvtpd2dq128_mask", "llvm.x86.avx512.mask.cvtpd2dq.512" => "__builtin_ia32_cvtpd2dq512_mask", "llvm.x86.avx512.mask.cvtpd2ps" => "__builtin_ia32_cvtpd2ps_mask", @@ -1516,6 +3126,8 @@ match name { "llvm.x86.avx512.mask.cvttps2uqq.128" => "__builtin_ia32_cvttps2uqq128_mask", "llvm.x86.avx512.mask.cvttps2uqq.256" => "__builtin_ia32_cvttps2uqq256_mask", "llvm.x86.avx512.mask.cvttps2uqq.512" => "__builtin_ia32_cvttps2uqq512_mask", + "llvm.x86.avx512.mask.cvtudq2pd.512" => "__builtin_ia32_cvtudq2pd512_mask", + "llvm.x86.avx512.mask.cvtudq2ps.512" => "__builtin_ia32_cvtudq2ps512_mask", "llvm.x86.avx512.mask.cvtuqq2ps.128" => "__builtin_ia32_cvtuqq2ps128_mask", "llvm.x86.avx512.mask.div.sd.round" => "__builtin_ia32_divsd_round_mask", "llvm.x86.avx512.mask.div.ss.round" => "__builtin_ia32_divss_round_mask", @@ -1545,12 +3157,61 @@ match name { "llvm.x86.avx512.mask.getmant.ps.512" => "__builtin_ia32_getmantps512_mask", "llvm.x86.avx512.mask.getmant.sd" => "__builtin_ia32_getmantsd_round_mask", "llvm.x86.avx512.mask.getmant.ss" => "__builtin_ia32_getmantss_round_mask", + "llvm.x86.avx512.mask.loadu.d.512" => "__builtin_ia32_loaddqusi512_mask", + "llvm.x86.avx512.mask.loadu.pd.512" => "__builtin_ia32_loadupd512_mask", + "llvm.x86.avx512.mask.loadu.ps.512" => "__builtin_ia32_loadups512_mask", + "llvm.x86.avx512.mask.loadu.q.512" => "__builtin_ia32_loaddqudi512_mask", + "llvm.x86.avx512.mask.lzcnt.d.512" => "__builtin_ia32_vplzcntd_512_mask", + "llvm.x86.avx512.mask.lzcnt.q.512" => "__builtin_ia32_vplzcntq_512_mask", + "llvm.x86.avx512.mask.max.pd.512" => "__builtin_ia32_maxpd512_mask", + "llvm.x86.avx512.mask.max.ps.512" => "__builtin_ia32_maxps512_mask", "llvm.x86.avx512.mask.max.sd.round" => "__builtin_ia32_maxsd_round_mask", "llvm.x86.avx512.mask.max.ss.round" => "__builtin_ia32_maxss_round_mask", + "llvm.x86.avx512.mask.min.pd.512" => "__builtin_ia32_minpd512_mask", + "llvm.x86.avx512.mask.min.ps.512" => "__builtin_ia32_minps512_mask", "llvm.x86.avx512.mask.min.sd.round" => "__builtin_ia32_minsd_round_mask", "llvm.x86.avx512.mask.min.ss.round" => "__builtin_ia32_minss_round_mask", "llvm.x86.avx512.mask.mul.sd.round" => "__builtin_ia32_mulsd_round_mask", "llvm.x86.avx512.mask.mul.ss.round" => "__builtin_ia32_mulss_round_mask", + "llvm.x86.avx512.mask.pabs.d.512" => "__builtin_ia32_pabsd512_mask", + "llvm.x86.avx512.mask.pabs.q.512" => "__builtin_ia32_pabsq512_mask", + "llvm.x86.avx512.mask.pand.d.512" => "__builtin_ia32_pandd512_mask", + "llvm.x86.avx512.mask.pand.q.512" => "__builtin_ia32_pandq512_mask", + "llvm.x86.avx512.mask.pbroadcast.d.gpr.512" => "__builtin_ia32_pbroadcastd512_gpr_mask", + "llvm.x86.avx512.mask.pbroadcast.q.gpr.512" => "__builtin_ia32_pbroadcastq512_gpr_mask", + "llvm.x86.avx512.mask.pbroadcast.q.mem.512" => "__builtin_ia32_pbroadcastq512_mem_mask", + "llvm.x86.avx512.mask.pcmpeq.b.128" => "__builtin_ia32_pcmpeqb128_mask", + "llvm.x86.avx512.mask.pcmpeq.b.256" => "__builtin_ia32_pcmpeqb256_mask", + "llvm.x86.avx512.mask.pcmpeq.b.512" => "__builtin_ia32_pcmpeqb512_mask", + "llvm.x86.avx512.mask.pcmpeq.d.128" => "__builtin_ia32_pcmpeqd128_mask", + "llvm.x86.avx512.mask.pcmpeq.d.256" => "__builtin_ia32_pcmpeqd256_mask", + "llvm.x86.avx512.mask.pcmpeq.d.512" => "__builtin_ia32_pcmpeqd512_mask", + "llvm.x86.avx512.mask.pcmpeq.q.128" => "__builtin_ia32_pcmpeqq128_mask", + "llvm.x86.avx512.mask.pcmpeq.q.256" => "__builtin_ia32_pcmpeqq256_mask", + "llvm.x86.avx512.mask.pcmpeq.q.512" => "__builtin_ia32_pcmpeqq512_mask", + "llvm.x86.avx512.mask.pcmpeq.w.128" => "__builtin_ia32_pcmpeqw128_mask", + "llvm.x86.avx512.mask.pcmpeq.w.256" => "__builtin_ia32_pcmpeqw256_mask", + "llvm.x86.avx512.mask.pcmpeq.w.512" => "__builtin_ia32_pcmpeqw512_mask", + "llvm.x86.avx512.mask.pcmpgt.b.128" => "__builtin_ia32_pcmpgtb128_mask", + "llvm.x86.avx512.mask.pcmpgt.b.256" => "__builtin_ia32_pcmpgtb256_mask", + "llvm.x86.avx512.mask.pcmpgt.b.512" => "__builtin_ia32_pcmpgtb512_mask", + "llvm.x86.avx512.mask.pcmpgt.d.128" => "__builtin_ia32_pcmpgtd128_mask", + "llvm.x86.avx512.mask.pcmpgt.d.256" => "__builtin_ia32_pcmpgtd256_mask", + "llvm.x86.avx512.mask.pcmpgt.d.512" => "__builtin_ia32_pcmpgtd512_mask", + "llvm.x86.avx512.mask.pcmpgt.q.128" => "__builtin_ia32_pcmpgtq128_mask", + "llvm.x86.avx512.mask.pcmpgt.q.256" => "__builtin_ia32_pcmpgtq256_mask", + "llvm.x86.avx512.mask.pcmpgt.q.512" => "__builtin_ia32_pcmpgtq512_mask", + "llvm.x86.avx512.mask.pcmpgt.w.128" => "__builtin_ia32_pcmpgtw128_mask", + "llvm.x86.avx512.mask.pcmpgt.w.256" => "__builtin_ia32_pcmpgtw256_mask", + "llvm.x86.avx512.mask.pcmpgt.w.512" => "__builtin_ia32_pcmpgtw512_mask", + "llvm.x86.avx512.mask.pmaxs.d.512" => "__builtin_ia32_pmaxsd512_mask", + "llvm.x86.avx512.mask.pmaxs.q.512" => "__builtin_ia32_pmaxsq512_mask", + "llvm.x86.avx512.mask.pmaxu.d.512" => "__builtin_ia32_pmaxud512_mask", + "llvm.x86.avx512.mask.pmaxu.q.512" => "__builtin_ia32_pmaxuq512_mask", + "llvm.x86.avx512.mask.pmins.d.512" => "__builtin_ia32_pminsd512_mask", + "llvm.x86.avx512.mask.pmins.q.512" => "__builtin_ia32_pminsq512_mask", + "llvm.x86.avx512.mask.pminu.d.512" => "__builtin_ia32_pminud512_mask", + "llvm.x86.avx512.mask.pminu.q.512" => "__builtin_ia32_pminuq512_mask", "llvm.x86.avx512.mask.pmov.db.128" => "__builtin_ia32_pmovdb128_mask", "llvm.x86.avx512.mask.pmov.db.256" => "__builtin_ia32_pmovdb256_mask", "llvm.x86.avx512.mask.pmov.db.mem.128" => "__builtin_ia32_pmovdb128mem_mask", @@ -1652,6 +3313,10 @@ match name { "llvm.x86.avx512.mask.pmovus.wb.mem.128" => "__builtin_ia32_pmovuswb128mem_mask", "llvm.x86.avx512.mask.pmovus.wb.mem.256" => "__builtin_ia32_pmovuswb256mem_mask", "llvm.x86.avx512.mask.pmovus.wb.mem.512" => "__builtin_ia32_pmovuswb512mem_mask", + "llvm.x86.avx512.mask.pmul.dq.512" => "__builtin_ia32_pmuldq512_mask", + "llvm.x86.avx512.mask.pmulu.dq.512" => "__builtin_ia32_pmuludq512_mask", + "llvm.x86.avx512.mask.ptestm.d.512" => "__builtin_ia32_ptestmd512", + "llvm.x86.avx512.mask.ptestm.q.512" => "__builtin_ia32_ptestmq512", "llvm.x86.avx512.mask.range.pd.128" => "__builtin_ia32_rangepd128_mask", "llvm.x86.avx512.mask.range.pd.256" => "__builtin_ia32_rangepd256_mask", "llvm.x86.avx512.mask.range.pd.512" => "__builtin_ia32_rangepd512_mask", @@ -1684,11 +3349,23 @@ match name { "llvm.x86.avx512.mask.scalef.ps.512" => "__builtin_ia32_scalefps512_mask", "llvm.x86.avx512.mask.scalef.sd" => "__builtin_ia32_scalefsd_round_mask", "llvm.x86.avx512.mask.scalef.ss" => "__builtin_ia32_scalefss_round_mask", + "llvm.x86.avx512.mask.store.ss" => "__builtin_ia32_storess_mask", + "llvm.x86.avx512.mask.storeu.d.512" => "__builtin_ia32_storedqusi512_mask", + "llvm.x86.avx512.mask.storeu.pd.512" => "__builtin_ia32_storeupd512_mask", + "llvm.x86.avx512.mask.storeu.ps.512" => "__builtin_ia32_storeups512_mask", + "llvm.x86.avx512.mask.storeu.q.512" => "__builtin_ia32_storedqudi512_mask", "llvm.x86.avx512.mask.sub.sd.round" => "__builtin_ia32_subsd_round_mask", "llvm.x86.avx512.mask.sub.ss.round" => "__builtin_ia32_subss_round_mask", + "llvm.x86.avx512.mask.valign.d.512" => "__builtin_ia32_alignd512_mask", + "llvm.x86.avx512.mask.valign.q.512" => "__builtin_ia32_alignq512_mask", + "llvm.x86.avx512.mask.vcvtph2ps.512" => "__builtin_ia32_vcvtph2ps512_mask", "llvm.x86.avx512.mask.vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph_mask", "llvm.x86.avx512.mask.vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256_mask", "llvm.x86.avx512.mask.vcvtps2ph.512" => "__builtin_ia32_vcvtps2ph512_mask", + "llvm.x86.avx512.mask.vpermt.d.512" => "__builtin_ia32_vpermt2vard512_mask", + "llvm.x86.avx512.mask.vpermt.pd.512" => "__builtin_ia32_vpermt2varpd512_mask", + "llvm.x86.avx512.mask.vpermt.ps.512" => "__builtin_ia32_vpermt2varps512_mask", + "llvm.x86.avx512.mask.vpermt.q.512" => "__builtin_ia32_vpermt2varq512_mask", "llvm.x86.avx512.maskz.fixupimm.pd.128" => "__builtin_ia32_fixupimmpd128_maskz", "llvm.x86.avx512.maskz.fixupimm.pd.256" => "__builtin_ia32_fixupimmpd256_maskz", "llvm.x86.avx512.maskz.fixupimm.pd.512" => "__builtin_ia32_fixupimmpd512_maskz", @@ -1701,6 +3378,7 @@ match name { "llvm.x86.avx512.max.ps.512" => "__builtin_ia32_maxps512", "llvm.x86.avx512.min.pd.512" => "__builtin_ia32_minpd512", "llvm.x86.avx512.min.ps.512" => "__builtin_ia32_minps512", + "llvm.x86.avx512.movntdqa" => "__builtin_ia32_movntdqa512", "llvm.x86.avx512.mul.pd.512" => "__builtin_ia32_mulpd512", "llvm.x86.avx512.mul.ps.512" => "__builtin_ia32_mulps512", "llvm.x86.avx512.packssdw.512" => "__builtin_ia32_packssdw512", @@ -1709,6 +3387,8 @@ match name { "llvm.x86.avx512.packuswb.512" => "__builtin_ia32_packuswb512", "llvm.x86.avx512.pavg.b.512" => "__builtin_ia32_pavgb512", "llvm.x86.avx512.pavg.w.512" => "__builtin_ia32_pavgw512", + "llvm.x86.avx512.pbroadcastd.512" => "__builtin_ia32_pbroadcastd512", + "llvm.x86.avx512.pbroadcastq.512" => "__builtin_ia32_pbroadcastq512", "llvm.x86.avx512.permvar.df.256" => "__builtin_ia32_permvardf256", "llvm.x86.avx512.permvar.df.512" => "__builtin_ia32_permvardf512", "llvm.x86.avx512.permvar.di.256" => "__builtin_ia32_permvardi256", @@ -1723,6 +3403,11 @@ match name { "llvm.x86.avx512.permvar.si.512" => "__builtin_ia32_permvarsi512", "llvm.x86.avx512.pmaddubs.w.512" => "__builtin_ia32_pmaddubsw512", "llvm.x86.avx512.pmaddw.d.512" => "__builtin_ia32_pmaddwd512", + "llvm.x86.avx512.pmovzxbd" => "__builtin_ia32_pmovzxbd512", + "llvm.x86.avx512.pmovzxbq" => "__builtin_ia32_pmovzxbq512", + "llvm.x86.avx512.pmovzxdq" => "__builtin_ia32_pmovzxdq512", + "llvm.x86.avx512.pmovzxwd" => "__builtin_ia32_pmovzxwd512", + "llvm.x86.avx512.pmovzxwq" => "__builtin_ia32_pmovzxwq512", "llvm.x86.avx512.pmul.hr.sw.512" => "__builtin_ia32_pmulhrsw512", "llvm.x86.avx512.pmulh.w.512" => "__builtin_ia32_pmulhw512", "llvm.x86.avx512.pmulhu.w.512" => "__builtin_ia32_pmulhuw512", @@ -1732,6 +3417,8 @@ match name { "llvm.x86.avx512.psad.bw.512" => "__builtin_ia32_psadbw512", "llvm.x86.avx512.pshuf.b.512" => "__builtin_ia32_pshufb512", "llvm.x86.avx512.psll.d.512" => "__builtin_ia32_pslld512", + "llvm.x86.avx512.psll.dq" => "__builtin_ia32_pslldqi512", + "llvm.x86.avx512.psll.dq.bs" => "__builtin_ia32_pslldqi512_byteshift", "llvm.x86.avx512.psll.q.512" => "__builtin_ia32_psllq512", "llvm.x86.avx512.psll.w.512" => "__builtin_ia32_psllw512", "llvm.x86.avx512.pslli.d.512" => "__builtin_ia32_pslldi512", @@ -1760,6 +3447,8 @@ match name { "llvm.x86.avx512.psrav.w.256" => "__builtin_ia32_psrav16hi", "llvm.x86.avx512.psrav.w.512" => "__builtin_ia32_psrav32hi", "llvm.x86.avx512.psrl.d.512" => "__builtin_ia32_psrld512", + "llvm.x86.avx512.psrl.dq" => "__builtin_ia32_psrldqi512", + "llvm.x86.avx512.psrl.dq.bs" => "__builtin_ia32_psrldqi512_byteshift", "llvm.x86.avx512.psrl.q.512" => "__builtin_ia32_psrlq512", "llvm.x86.avx512.psrl.w.512" => "__builtin_ia32_psrlw512", "llvm.x86.avx512.psrli.d.512" => "__builtin_ia32_psrldi512", @@ -1786,8 +3475,12 @@ match name { "llvm.x86.avx512.rcp14.ss" => "__builtin_ia32_rcp14ss_mask", "llvm.x86.avx512.rcp28.pd" => "__builtin_ia32_rcp28pd_mask", "llvm.x86.avx512.rcp28.ps" => "__builtin_ia32_rcp28ps_mask", - "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_round_mask", - "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_round_mask", + "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_mask", + // [DUPLICATE]: "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_round_mask", + "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_mask", + // [DUPLICATE]: "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_round_mask", + "llvm.x86.avx512.rndscale.sd" => "__builtin_ia32_rndscalesd", + "llvm.x86.avx512.rndscale.ss" => "__builtin_ia32_rndscaless", "llvm.x86.avx512.rsqrt14.pd.128" => "__builtin_ia32_rsqrt14pd128_mask", "llvm.x86.avx512.rsqrt14.pd.256" => "__builtin_ia32_rsqrt14pd256_mask", "llvm.x86.avx512.rsqrt14.pd.512" => "__builtin_ia32_rsqrt14pd512_mask", @@ -1798,14 +3491,32 @@ match name { "llvm.x86.avx512.rsqrt14.ss" => "__builtin_ia32_rsqrt14ss_mask", "llvm.x86.avx512.rsqrt28.pd" => "__builtin_ia32_rsqrt28pd_mask", "llvm.x86.avx512.rsqrt28.ps" => "__builtin_ia32_rsqrt28ps_mask", - "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_round_mask", - "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_round_mask", + "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_mask", + // [DUPLICATE]: "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_round_mask", + "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_mask", + // [DUPLICATE]: "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_round_mask", + "llvm.x86.avx512.scatter.dpd.512" => "__builtin_ia32_scattersiv8df", + "llvm.x86.avx512.scatter.dpi.512" => "__builtin_ia32_scattersiv16si", + "llvm.x86.avx512.scatter.dpq.512" => "__builtin_ia32_scattersiv8di", + "llvm.x86.avx512.scatter.dps.512" => "__builtin_ia32_scattersiv16sf", + "llvm.x86.avx512.scatter.qpd.512" => "__builtin_ia32_scatterdiv8df", + "llvm.x86.avx512.scatter.qpi.512" => "__builtin_ia32_scatterdiv16si", + "llvm.x86.avx512.scatter.qpq.512" => "__builtin_ia32_scatterdiv8di", + "llvm.x86.avx512.scatter.qps.512" => "__builtin_ia32_scatterdiv16sf", "llvm.x86.avx512.scatterpf.dpd.512" => "__builtin_ia32_scatterpfdpd", "llvm.x86.avx512.scatterpf.dps.512" => "__builtin_ia32_scatterpfdps", "llvm.x86.avx512.scatterpf.qpd.512" => "__builtin_ia32_scatterpfqpd", "llvm.x86.avx512.scatterpf.qps.512" => "__builtin_ia32_scatterpfqps", + "llvm.x86.avx512.sqrt.pd.512" => "__builtin_ia32_sqrtpd512_mask", + "llvm.x86.avx512.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask", + "llvm.x86.avx512.sqrt.sd" => "__builtin_ia32_sqrtrndsd", + "llvm.x86.avx512.sqrt.ss" => "__builtin_ia32_sqrtrndss", "llvm.x86.avx512.sub.pd.512" => "__builtin_ia32_subpd512", "llvm.x86.avx512.sub.ps.512" => "__builtin_ia32_subps512", + "llvm.x86.avx512.vbroadcast.sd.512" => "__builtin_ia32_vbroadcastsd512", + "llvm.x86.avx512.vbroadcast.sd.pd.512" => "__builtin_ia32_vbroadcastsd_pd512", + "llvm.x86.avx512.vbroadcast.ss.512" => "__builtin_ia32_vbroadcastss512", + "llvm.x86.avx512.vbroadcast.ss.ps.512" => "__builtin_ia32_vbroadcastss_ps512", "llvm.x86.avx512.vcomi.sd" => "__builtin_ia32_vcomisd", "llvm.x86.avx512.vcomi.ss" => "__builtin_ia32_vcomiss", "llvm.x86.avx512.vcvtsd2si32" => "__builtin_ia32_vcvtsd2si32", @@ -2027,10 +3738,50 @@ match name { "llvm.x86.flags.read.u64" => "__builtin_ia32_readeflags_u64", "llvm.x86.flags.write.u32" => "__builtin_ia32_writeeflags_u32", "llvm.x86.flags.write.u64" => "__builtin_ia32_writeeflags_u64", + "llvm.x86.fma.mask.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask", + "llvm.x86.fma.mask.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask", + "llvm.x86.fma.mask.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask", + "llvm.x86.fma.mask.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask", + "llvm.x86.fma.mask.vfmsub.pd.512" => "__builtin_ia32_vfmsubpd512_mask", + "llvm.x86.fma.mask.vfmsub.ps.512" => "__builtin_ia32_vfmsubps512_mask", + "llvm.x86.fma.mask.vfmsubadd.pd.512" => "__builtin_ia32_vfmsubaddpd512_mask", + "llvm.x86.fma.mask.vfmsubadd.ps.512" => "__builtin_ia32_vfmsubaddps512_mask", + "llvm.x86.fma.mask.vfnmadd.pd.512" => "__builtin_ia32_vfnmaddpd512_mask", + "llvm.x86.fma.mask.vfnmadd.ps.512" => "__builtin_ia32_vfnmaddps512_mask", + "llvm.x86.fma.mask.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask", + "llvm.x86.fma.mask.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask", + "llvm.x86.fma.vfmadd.pd" => "__builtin_ia32_vfmaddpd", + "llvm.x86.fma.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256", + "llvm.x86.fma.vfmadd.ps" => "__builtin_ia32_vfmaddps", + "llvm.x86.fma.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256", + "llvm.x86.fma.vfmadd.sd" => "__builtin_ia32_vfmaddsd", + "llvm.x86.fma.vfmadd.ss" => "__builtin_ia32_vfmaddss", "llvm.x86.fma.vfmaddsub.pd" => "__builtin_ia32_vfmaddsubpd", "llvm.x86.fma.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256", "llvm.x86.fma.vfmaddsub.ps" => "__builtin_ia32_vfmaddsubps", "llvm.x86.fma.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256", + "llvm.x86.fma.vfmsub.pd" => "__builtin_ia32_vfmsubpd", + "llvm.x86.fma.vfmsub.pd.256" => "__builtin_ia32_vfmsubpd256", + "llvm.x86.fma.vfmsub.ps" => "__builtin_ia32_vfmsubps", + "llvm.x86.fma.vfmsub.ps.256" => "__builtin_ia32_vfmsubps256", + "llvm.x86.fma.vfmsub.sd" => "__builtin_ia32_vfmsubsd", + "llvm.x86.fma.vfmsub.ss" => "__builtin_ia32_vfmsubss", + "llvm.x86.fma.vfmsubadd.pd" => "__builtin_ia32_vfmsubaddpd", + "llvm.x86.fma.vfmsubadd.pd.256" => "__builtin_ia32_vfmsubaddpd256", + "llvm.x86.fma.vfmsubadd.ps" => "__builtin_ia32_vfmsubaddps", + "llvm.x86.fma.vfmsubadd.ps.256" => "__builtin_ia32_vfmsubaddps256", + "llvm.x86.fma.vfnmadd.pd" => "__builtin_ia32_vfnmaddpd", + "llvm.x86.fma.vfnmadd.pd.256" => "__builtin_ia32_vfnmaddpd256", + "llvm.x86.fma.vfnmadd.ps" => "__builtin_ia32_vfnmaddps", + "llvm.x86.fma.vfnmadd.ps.256" => "__builtin_ia32_vfnmaddps256", + "llvm.x86.fma.vfnmadd.sd" => "__builtin_ia32_vfnmaddsd", + "llvm.x86.fma.vfnmadd.ss" => "__builtin_ia32_vfnmaddss", + "llvm.x86.fma.vfnmsub.pd" => "__builtin_ia32_vfnmsubpd", + "llvm.x86.fma.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256", + "llvm.x86.fma.vfnmsub.ps" => "__builtin_ia32_vfnmsubps", + "llvm.x86.fma.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256", + "llvm.x86.fma.vfnmsub.sd" => "__builtin_ia32_vfnmsubsd", + "llvm.x86.fma.vfnmsub.ss" => "__builtin_ia32_vfnmsubss", "llvm.x86.fxrstor" => "__builtin_ia32_fxrstor", "llvm.x86.fxrstor64" => "__builtin_ia32_fxrstor64", "llvm.x86.fxsave" => "__builtin_ia32_fxsave", @@ -2134,6 +3885,7 @@ match name { "llvm.x86.rdsspd" => "__builtin_ia32_rdsspd", "llvm.x86.rdsspq" => "__builtin_ia32_rdsspq", "llvm.x86.rdtsc" => "__builtin_ia32_rdtsc", + "llvm.x86.rdtscp" => "__builtin_ia32_rdtscp", "llvm.x86.rstorssp" => "__builtin_ia32_rstorssp", "llvm.x86.saveprevssp" => "__builtin_ia32_saveprevssp", "llvm.x86.senduipi" => "__builtin_ia32_senduipi", @@ -2147,6 +3899,8 @@ match name { "llvm.x86.sha256msg2" => "__builtin_ia32_sha256msg2", "llvm.x86.sha256rnds2" => "__builtin_ia32_sha256rnds2", "llvm.x86.slwpcb" => "__builtin_ia32_slwpcb", + "llvm.x86.sse.add.ss" => "__builtin_ia32_addss", + "llvm.x86.sse.cmp.ps" => "__builtin_ia32_cmpps", "llvm.x86.sse.cmp.ss" => "__builtin_ia32_cmpss", "llvm.x86.sse.comieq.ss" => "__builtin_ia32_comieq", "llvm.x86.sse.comige.ss" => "__builtin_ia32_comige", @@ -2158,30 +3912,40 @@ match name { "llvm.x86.sse.cvtpi2pd" => "__builtin_ia32_cvtpi2pd", "llvm.x86.sse.cvtpi2ps" => "__builtin_ia32_cvtpi2ps", "llvm.x86.sse.cvtps2pi" => "__builtin_ia32_cvtps2pi", + "llvm.x86.sse.cvtsi2ss" => "__builtin_ia32_cvtsi2ss", + "llvm.x86.sse.cvtsi642ss" => "__builtin_ia32_cvtsi642ss", "llvm.x86.sse.cvtss2si" => "__builtin_ia32_cvtss2si", "llvm.x86.sse.cvtss2si64" => "__builtin_ia32_cvtss2si64", "llvm.x86.sse.cvttpd2pi" => "__builtin_ia32_cvttpd2pi", "llvm.x86.sse.cvttps2pi" => "__builtin_ia32_cvttps2pi", "llvm.x86.sse.cvttss2si" => "__builtin_ia32_cvttss2si", "llvm.x86.sse.cvttss2si64" => "__builtin_ia32_cvttss2si64", + "llvm.x86.sse.div.ss" => "__builtin_ia32_divss", "llvm.x86.sse.max.ps" => "__builtin_ia32_maxps", "llvm.x86.sse.max.ss" => "__builtin_ia32_maxss", "llvm.x86.sse.min.ps" => "__builtin_ia32_minps", "llvm.x86.sse.min.ss" => "__builtin_ia32_minss", "llvm.x86.sse.movmsk.ps" => "__builtin_ia32_movmskps", + "llvm.x86.sse.mul.ss" => "__builtin_ia32_mulss", "llvm.x86.sse.pshuf.w" => "__builtin_ia32_pshufw", "llvm.x86.sse.rcp.ps" => "__builtin_ia32_rcpps", "llvm.x86.sse.rcp.ss" => "__builtin_ia32_rcpss", "llvm.x86.sse.rsqrt.ps" => "__builtin_ia32_rsqrtps", "llvm.x86.sse.rsqrt.ss" => "__builtin_ia32_rsqrtss", "llvm.x86.sse.sfence" => "__builtin_ia32_sfence", + "llvm.x86.sse.sqrt.ps" => "__builtin_ia32_sqrtps", + "llvm.x86.sse.sqrt.ss" => "__builtin_ia32_sqrtss", + "llvm.x86.sse.storeu.ps" => "__builtin_ia32_storeups", + "llvm.x86.sse.sub.ss" => "__builtin_ia32_subss", "llvm.x86.sse.ucomieq.ss" => "__builtin_ia32_ucomieq", "llvm.x86.sse.ucomige.ss" => "__builtin_ia32_ucomige", "llvm.x86.sse.ucomigt.ss" => "__builtin_ia32_ucomigt", "llvm.x86.sse.ucomile.ss" => "__builtin_ia32_ucomile", "llvm.x86.sse.ucomilt.ss" => "__builtin_ia32_ucomilt", "llvm.x86.sse.ucomineq.ss" => "__builtin_ia32_ucomineq", + "llvm.x86.sse2.add.sd" => "__builtin_ia32_addsd", "llvm.x86.sse2.clflush" => "__builtin_ia32_clflush", + "llvm.x86.sse2.cmp.pd" => "__builtin_ia32_cmppd", "llvm.x86.sse2.cmp.sd" => "__builtin_ia32_cmpsd", "llvm.x86.sse2.comieq.sd" => "__builtin_ia32_comisdeq", "llvm.x86.sse2.comige.sd" => "__builtin_ia32_comisdge", @@ -2189,16 +3953,23 @@ match name { "llvm.x86.sse2.comile.sd" => "__builtin_ia32_comisdle", "llvm.x86.sse2.comilt.sd" => "__builtin_ia32_comisdlt", "llvm.x86.sse2.comineq.sd" => "__builtin_ia32_comisdneq", + "llvm.x86.sse2.cvtdq2pd" => "__builtin_ia32_cvtdq2pd", + "llvm.x86.sse2.cvtdq2ps" => "__builtin_ia32_cvtdq2ps", "llvm.x86.sse2.cvtpd2dq" => "__builtin_ia32_cvtpd2dq", "llvm.x86.sse2.cvtpd2ps" => "__builtin_ia32_cvtpd2ps", "llvm.x86.sse2.cvtps2dq" => "__builtin_ia32_cvtps2dq", + "llvm.x86.sse2.cvtps2pd" => "__builtin_ia32_cvtps2pd", "llvm.x86.sse2.cvtsd2si" => "__builtin_ia32_cvtsd2si", "llvm.x86.sse2.cvtsd2si64" => "__builtin_ia32_cvtsd2si64", "llvm.x86.sse2.cvtsd2ss" => "__builtin_ia32_cvtsd2ss", + "llvm.x86.sse2.cvtsi2sd" => "__builtin_ia32_cvtsi2sd", + "llvm.x86.sse2.cvtsi642sd" => "__builtin_ia32_cvtsi642sd", + "llvm.x86.sse2.cvtss2sd" => "__builtin_ia32_cvtss2sd", "llvm.x86.sse2.cvttpd2dq" => "__builtin_ia32_cvttpd2dq", "llvm.x86.sse2.cvttps2dq" => "__builtin_ia32_cvttps2dq", "llvm.x86.sse2.cvttsd2si" => "__builtin_ia32_cvttsd2si", "llvm.x86.sse2.cvttsd2si64" => "__builtin_ia32_cvttsd2si64", + "llvm.x86.sse2.div.sd" => "__builtin_ia32_divsd", "llvm.x86.sse2.lfence" => "__builtin_ia32_lfence", "llvm.x86.sse2.maskmov.dqu" => "__builtin_ia32_maskmovdqu", "llvm.x86.sse2.max.pd" => "__builtin_ia32_maxpd", @@ -2207,18 +3978,33 @@ match name { "llvm.x86.sse2.min.pd" => "__builtin_ia32_minpd", "llvm.x86.sse2.min.sd" => "__builtin_ia32_minsd", "llvm.x86.sse2.movmsk.pd" => "__builtin_ia32_movmskpd", + "llvm.x86.sse2.mul.sd" => "__builtin_ia32_mulsd", "llvm.x86.sse2.packssdw.128" => "__builtin_ia32_packssdw128", "llvm.x86.sse2.packsswb.128" => "__builtin_ia32_packsswb128", "llvm.x86.sse2.packuswb.128" => "__builtin_ia32_packuswb128", + "llvm.x86.sse2.padds.b" => "__builtin_ia32_paddsb128", + "llvm.x86.sse2.padds.w" => "__builtin_ia32_paddsw128", + "llvm.x86.sse2.paddus.b" => "__builtin_ia32_paddusb128", + "llvm.x86.sse2.paddus.w" => "__builtin_ia32_paddusw128", "llvm.x86.sse2.pause" => "__builtin_ia32_pause", "llvm.x86.sse2.pavg.b" => "__builtin_ia32_pavgb128", "llvm.x86.sse2.pavg.w" => "__builtin_ia32_pavgw128", "llvm.x86.sse2.pmadd.wd" => "__builtin_ia32_pmaddwd128", + "llvm.x86.sse2.pmaxs.w" => "__builtin_ia32_pmaxsw128", + "llvm.x86.sse2.pmaxu.b" => "__builtin_ia32_pmaxub128", + "llvm.x86.sse2.pmins.w" => "__builtin_ia32_pminsw128", + "llvm.x86.sse2.pminu.b" => "__builtin_ia32_pminub128", "llvm.x86.sse2.pmovmskb.128" => "__builtin_ia32_pmovmskb128", "llvm.x86.sse2.pmulh.w" => "__builtin_ia32_pmulhw128", "llvm.x86.sse2.pmulhu.w" => "__builtin_ia32_pmulhuw128", + "llvm.x86.sse2.pmulu.dq" => "__builtin_ia32_pmuludq128", "llvm.x86.sse2.psad.bw" => "__builtin_ia32_psadbw128", + "llvm.x86.sse2.pshuf.d" => "__builtin_ia32_pshufd", + "llvm.x86.sse2.pshufh.w" => "__builtin_ia32_pshufhw", + "llvm.x86.sse2.pshufl.w" => "__builtin_ia32_pshuflw", "llvm.x86.sse2.psll.d" => "__builtin_ia32_pslld128", + "llvm.x86.sse2.psll.dq" => "__builtin_ia32_pslldqi128", + "llvm.x86.sse2.psll.dq.bs" => "__builtin_ia32_pslldqi128_byteshift", "llvm.x86.sse2.psll.q" => "__builtin_ia32_psllq128", "llvm.x86.sse2.psll.w" => "__builtin_ia32_psllw128", "llvm.x86.sse2.pslli.d" => "__builtin_ia32_pslldi128", @@ -2229,11 +4015,23 @@ match name { "llvm.x86.sse2.psrai.d" => "__builtin_ia32_psradi128", "llvm.x86.sse2.psrai.w" => "__builtin_ia32_psrawi128", "llvm.x86.sse2.psrl.d" => "__builtin_ia32_psrld128", + "llvm.x86.sse2.psrl.dq" => "__builtin_ia32_psrldqi128", + "llvm.x86.sse2.psrl.dq.bs" => "__builtin_ia32_psrldqi128_byteshift", "llvm.x86.sse2.psrl.q" => "__builtin_ia32_psrlq128", "llvm.x86.sse2.psrl.w" => "__builtin_ia32_psrlw128", "llvm.x86.sse2.psrli.d" => "__builtin_ia32_psrldi128", "llvm.x86.sse2.psrli.q" => "__builtin_ia32_psrlqi128", "llvm.x86.sse2.psrli.w" => "__builtin_ia32_psrlwi128", + "llvm.x86.sse2.psubs.b" => "__builtin_ia32_psubsb128", + "llvm.x86.sse2.psubs.w" => "__builtin_ia32_psubsw128", + "llvm.x86.sse2.psubus.b" => "__builtin_ia32_psubusb128", + "llvm.x86.sse2.psubus.w" => "__builtin_ia32_psubusw128", + "llvm.x86.sse2.sqrt.pd" => "__builtin_ia32_sqrtpd", + "llvm.x86.sse2.sqrt.sd" => "__builtin_ia32_sqrtsd", + "llvm.x86.sse2.storel.dq" => "__builtin_ia32_storelv4si", + "llvm.x86.sse2.storeu.dq" => "__builtin_ia32_storedqu", + "llvm.x86.sse2.storeu.pd" => "__builtin_ia32_storeupd", + "llvm.x86.sse2.sub.sd" => "__builtin_ia32_subsd", "llvm.x86.sse2.ucomieq.sd" => "__builtin_ia32_ucomisdeq", "llvm.x86.sse2.ucomige.sd" => "__builtin_ia32_ucomisdge", "llvm.x86.sse2.ucomigt.sd" => "__builtin_ia32_ucomisdgt", @@ -2249,15 +4047,41 @@ match name { "llvm.x86.sse3.ldu.dq" => "__builtin_ia32_lddqu", "llvm.x86.sse3.monitor" => "__builtin_ia32_monitor", "llvm.x86.sse3.mwait" => "__builtin_ia32_mwait", + "llvm.x86.sse41.blendpd" => "__builtin_ia32_blendpd", + "llvm.x86.sse41.blendps" => "__builtin_ia32_blendps", "llvm.x86.sse41.blendvpd" => "__builtin_ia32_blendvpd", "llvm.x86.sse41.blendvps" => "__builtin_ia32_blendvps", "llvm.x86.sse41.dppd" => "__builtin_ia32_dppd", "llvm.x86.sse41.dpps" => "__builtin_ia32_dpps", + "llvm.x86.sse41.extractps" => "__builtin_ia32_extractps128", "llvm.x86.sse41.insertps" => "__builtin_ia32_insertps128", + "llvm.x86.sse41.movntdqa" => "__builtin_ia32_movntdqa", "llvm.x86.sse41.mpsadbw" => "__builtin_ia32_mpsadbw128", "llvm.x86.sse41.packusdw" => "__builtin_ia32_packusdw128", "llvm.x86.sse41.pblendvb" => "__builtin_ia32_pblendvb128", + "llvm.x86.sse41.pblendw" => "__builtin_ia32_pblendw128", "llvm.x86.sse41.phminposuw" => "__builtin_ia32_phminposuw128", + "llvm.x86.sse41.pmaxsb" => "__builtin_ia32_pmaxsb128", + "llvm.x86.sse41.pmaxsd" => "__builtin_ia32_pmaxsd128", + "llvm.x86.sse41.pmaxud" => "__builtin_ia32_pmaxud128", + "llvm.x86.sse41.pmaxuw" => "__builtin_ia32_pmaxuw128", + "llvm.x86.sse41.pminsb" => "__builtin_ia32_pminsb128", + "llvm.x86.sse41.pminsd" => "__builtin_ia32_pminsd128", + "llvm.x86.sse41.pminud" => "__builtin_ia32_pminud128", + "llvm.x86.sse41.pminuw" => "__builtin_ia32_pminuw128", + "llvm.x86.sse41.pmovsxbd" => "__builtin_ia32_pmovsxbd128", + "llvm.x86.sse41.pmovsxbq" => "__builtin_ia32_pmovsxbq128", + "llvm.x86.sse41.pmovsxbw" => "__builtin_ia32_pmovsxbw128", + "llvm.x86.sse41.pmovsxdq" => "__builtin_ia32_pmovsxdq128", + "llvm.x86.sse41.pmovsxwd" => "__builtin_ia32_pmovsxwd128", + "llvm.x86.sse41.pmovsxwq" => "__builtin_ia32_pmovsxwq128", + "llvm.x86.sse41.pmovzxbd" => "__builtin_ia32_pmovzxbd128", + "llvm.x86.sse41.pmovzxbq" => "__builtin_ia32_pmovzxbq128", + "llvm.x86.sse41.pmovzxbw" => "__builtin_ia32_pmovzxbw128", + "llvm.x86.sse41.pmovzxdq" => "__builtin_ia32_pmovzxdq128", + "llvm.x86.sse41.pmovzxwd" => "__builtin_ia32_pmovzxwd128", + "llvm.x86.sse41.pmovzxwq" => "__builtin_ia32_pmovzxwq128", + "llvm.x86.sse41.pmuldq" => "__builtin_ia32_pmuldq128", "llvm.x86.sse41.ptestc" => "__builtin_ia32_ptestc128", "llvm.x86.sse41.ptestnzc" => "__builtin_ia32_ptestnzc128", "llvm.x86.sse41.ptestz" => "__builtin_ia32_ptestz128", @@ -2287,9 +4111,14 @@ match name { "llvm.x86.sse4a.extrqi" => "__builtin_ia32_extrqi", "llvm.x86.sse4a.insertq" => "__builtin_ia32_insertq", "llvm.x86.sse4a.insertqi" => "__builtin_ia32_insertqi", + "llvm.x86.sse4a.movnt.sd" => "__builtin_ia32_movntsd", + "llvm.x86.sse4a.movnt.ss" => "__builtin_ia32_movntss", "llvm.x86.ssse3.pabs.b" => "__builtin_ia32_pabsb", + "llvm.x86.ssse3.pabs.b.128" => "__builtin_ia32_pabsb128", "llvm.x86.ssse3.pabs.d" => "__builtin_ia32_pabsd", + "llvm.x86.ssse3.pabs.d.128" => "__builtin_ia32_pabsd128", "llvm.x86.ssse3.pabs.w" => "__builtin_ia32_pabsw", + "llvm.x86.ssse3.pabs.w.128" => "__builtin_ia32_pabsw128", "llvm.x86.ssse3.phadd.d" => "__builtin_ia32_phaddd", "llvm.x86.ssse3.phadd.d.128" => "__builtin_ia32_phaddd128", "llvm.x86.ssse3.phadd.sw" => "__builtin_ia32_phaddsw", @@ -2316,6 +4145,8 @@ match name { "llvm.x86.ssse3.psign.w.128" => "__builtin_ia32_psignw128", "llvm.x86.sttilecfg" => "__builtin_ia32_tile_storeconfig", "llvm.x86.stui" => "__builtin_ia32_stui", + "llvm.x86.subborrow.u32" => "__builtin_ia32_subborrow_u32", + "llvm.x86.subborrow.u64" => "__builtin_ia32_subborrow_u64", "llvm.x86.tbm.bextri.u32" => "__builtin_ia32_bextri_u32", "llvm.x86.tbm.bextri.u64" => "__builtin_ia32_bextri_u64", "llvm.x86.tdpbf16ps" => "__builtin_ia32_tdpbf16ps", @@ -2341,6 +4172,8 @@ match name { "llvm.x86.tpause" => "__builtin_ia32_tpause", "llvm.x86.umonitor" => "__builtin_ia32_umonitor", "llvm.x86.umwait" => "__builtin_ia32_umwait", + "llvm.x86.vcvtph2ps.128" => "__builtin_ia32_vcvtph2ps", + "llvm.x86.vcvtph2ps.256" => "__builtin_ia32_vcvtph2ps256", "llvm.x86.vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph", "llvm.x86.vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256", "llvm.x86.vgf2p8affineinvqb.128" => "__builtin_ia32_vgf2p8affineinvqb_v16qi", @@ -2372,6 +4205,16 @@ match name { "llvm.x86.xop.vfrcz.ps.256" => "__builtin_ia32_vfrczps256", "llvm.x86.xop.vfrcz.sd" => "__builtin_ia32_vfrczsd", "llvm.x86.xop.vfrcz.ss" => "__builtin_ia32_vfrczss", + "llvm.x86.xop.vpcmov" => "__builtin_ia32_vpcmov", + "llvm.x86.xop.vpcmov.256" => "__builtin_ia32_vpcmov_256", + "llvm.x86.xop.vpcomb" => "__builtin_ia32_vpcomb", + "llvm.x86.xop.vpcomd" => "__builtin_ia32_vpcomd", + "llvm.x86.xop.vpcomq" => "__builtin_ia32_vpcomq", + "llvm.x86.xop.vpcomub" => "__builtin_ia32_vpcomub", + "llvm.x86.xop.vpcomud" => "__builtin_ia32_vpcomud", + "llvm.x86.xop.vpcomuq" => "__builtin_ia32_vpcomuq", + "llvm.x86.xop.vpcomuw" => "__builtin_ia32_vpcomuw", + "llvm.x86.xop.vpcomw" => "__builtin_ia32_vpcomw", "llvm.x86.xop.vpermil2pd" => "__builtin_ia32_vpermil2pd", "llvm.x86.xop.vpermil2pd.256" => "__builtin_ia32_vpermil2pd256", "llvm.x86.xop.vpermil2ps" => "__builtin_ia32_vpermil2ps", @@ -2404,6 +4247,14 @@ match name { "llvm.x86.xop.vpmadcsswd" => "__builtin_ia32_vpmadcsswd", "llvm.x86.xop.vpmadcswd" => "__builtin_ia32_vpmadcswd", "llvm.x86.xop.vpperm" => "__builtin_ia32_vpperm", + "llvm.x86.xop.vprotb" => "__builtin_ia32_vprotb", + "llvm.x86.xop.vprotbi" => "__builtin_ia32_vprotbi", + "llvm.x86.xop.vprotd" => "__builtin_ia32_vprotd", + "llvm.x86.xop.vprotdi" => "__builtin_ia32_vprotdi", + "llvm.x86.xop.vprotq" => "__builtin_ia32_vprotq", + "llvm.x86.xop.vprotqi" => "__builtin_ia32_vprotqi", + "llvm.x86.xop.vprotw" => "__builtin_ia32_vprotw", + "llvm.x86.xop.vprotwi" => "__builtin_ia32_vprotwi", "llvm.x86.xop.vpshab" => "__builtin_ia32_vpshab", "llvm.x86.xop.vpshad" => "__builtin_ia32_vpshad", "llvm.x86.xop.vpshaq" => "__builtin_ia32_vpshaq", From 618ba484e9e66dece784753947e2ddec202d282a Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Tue, 3 May 2022 22:38:53 +0200 Subject: [PATCH 078/356] Handle a syntax corner case where a def does not end with a `;` --- src/intrinsic/archs.rs | 10 +++++++--- tools/generate_intrinsics.py | 4 ++-- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/intrinsic/archs.rs b/src/intrinsic/archs.rs index 427ca77e9d0b..2782332cc57d 100644 --- a/src/intrinsic/archs.rs +++ b/src/intrinsic/archs.rs @@ -110,18 +110,18 @@ match name { "llvm.amdgcn.s.dcache.inv.vol" => "__builtin_amdgcn_s_dcache_inv_vol", "llvm.amdgcn.s.dcache.wb" => "__builtin_amdgcn_s_dcache_wb", "llvm.amdgcn.s.dcache.wb.vol" => "__builtin_amdgcn_s_dcache_wb_vol", + "llvm.amdgcn.s.decperflevel" => "__builtin_amdgcn_s_decperflevel", "llvm.amdgcn.s.get.waveid.in.workgroup" => "__builtin_amdgcn_s_get_waveid_in_workgroup", "llvm.amdgcn.s.getpc" => "__builtin_amdgcn_s_getpc", "llvm.amdgcn.s.getreg" => "__builtin_amdgcn_s_getreg", + "llvm.amdgcn.s.incperflevel" => "__builtin_amdgcn_s_incperflevel", "llvm.amdgcn.s.memrealtime" => "__builtin_amdgcn_s_memrealtime", "llvm.amdgcn.s.memtime" => "__builtin_amdgcn_s_memtime", "llvm.amdgcn.s.sendmsg" => "__builtin_amdgcn_s_sendmsg", "llvm.amdgcn.s.sendmsghalt" => "__builtin_amdgcn_s_sendmsghalt", "llvm.amdgcn.s.setprio" => "__builtin_amdgcn_s_setprio", "llvm.amdgcn.s.setreg" => "__builtin_amdgcn_s_setreg", - "llvm.amdgcn.s.sleep" => "__builtin_amdgcn_s_decperflevel", - // [DUPLICATE]: "llvm.amdgcn.s.sleep" => "__builtin_amdgcn_s_incperflevel", - // [DUPLICATE]: "llvm.amdgcn.s.sleep" => "__builtin_amdgcn_s_sleep", + "llvm.amdgcn.s.sleep" => "__builtin_amdgcn_s_sleep", "llvm.amdgcn.s.waitcnt" => "__builtin_amdgcn_s_waitcnt", "llvm.amdgcn.sad.hi.u8" => "__builtin_amdgcn_sad_hi_u8", "llvm.amdgcn.sad.u16" => "__builtin_amdgcn_sad_u16", @@ -2689,6 +2689,10 @@ match name { "llvm.ppc.vsx.xvresp" => "__builtin_vsx_xvresp", "llvm.ppc.vsx.xvrsqrtedp" => "__builtin_vsx_xvrsqrtedp", "llvm.ppc.vsx.xvrsqrtesp" => "__builtin_vsx_xvrsqrtesp", + "llvm.ppc.vsx.xxblendvb" => "__builtin_vsx_xxblendvb", + "llvm.ppc.vsx.xxblendvd" => "__builtin_vsx_xxblendvd", + "llvm.ppc.vsx.xxblendvh" => "__builtin_vsx_xxblendvh", + "llvm.ppc.vsx.xxblendvw" => "__builtin_vsx_xxblendvw", "llvm.ppc.vsx.xxpermx" => "__builtin_vsx_xxpermx", // ptx "llvm.ptx.bar.sync" => "__builtin_ptx_bar_sync", diff --git a/tools/generate_intrinsics.py b/tools/generate_intrinsics.py index 88b8b54b6baa..64f14143381c 100644 --- a/tools/generate_intrinsics.py +++ b/tools/generate_intrinsics.py @@ -60,13 +60,13 @@ def extract_instrinsics(intrinsics, file): current_arch = None elif line.startswith("def "): content = "" - while not content.endswith(";") and pos < len(lines): + while not content.endswith(";") and not content.endswith("}") and pos < len(lines): line = lines[pos].split(" // ")[0].strip() content += line pos += 1 entries = re.findall('GCCBuiltin<"(\\w+)">', content) if len(entries) > 0: - intrinsic = content.split(":")[0].split(" ")[1].strip() + intrinsic = content.split("def ")[1].strip().split(":")[0].strip() intrinsic = intrinsic.split("_") if len(intrinsic) < 2 or intrinsic[0] != "int": continue From 6e1bf49273a2011aa3fb26e641e410ca42d924af Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Tue, 3 May 2022 23:00:09 +0200 Subject: [PATCH 079/356] Give priority to intrinsics translations from llvm --- src/intrinsic/archs.rs | 36 +++++++++++++++++------------------ tools/generate_intrinsics.py | 37 ++++++++++++++++++++++++++---------- 2 files changed, 45 insertions(+), 28 deletions(-) diff --git a/src/intrinsic/archs.rs b/src/intrinsic/archs.rs index 2782332cc57d..bfeb30f2913d 100644 --- a/src/intrinsic/archs.rs +++ b/src/intrinsic/archs.rs @@ -3021,19 +3021,19 @@ match name { "llvm.x86.avx512.cvtss2usi64" => "__builtin_ia32_cvtss2usi64", "llvm.x86.avx512.cvttsd2si" => "__builtin_ia32_vcvttsd2si32", "llvm.x86.avx512.cvttsd2si64" => "__builtin_ia32_vcvttsd2si64", - "llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_cvttsd2usi", - // [DUPLICATE]: "llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_vcvttsd2usi32", - "llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_cvttsd2usi64", - // [DUPLICATE]: "llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_vcvttsd2usi64", + "llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_vcvttsd2usi32", + // [DUPLICATE]: "llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_cvttsd2usi", + "llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_vcvttsd2usi64", + // [DUPLICATE]: "llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_cvttsd2usi64", "llvm.x86.avx512.cvttss2si" => "__builtin_ia32_vcvttss2si32", "llvm.x86.avx512.cvttss2si64" => "__builtin_ia32_vcvttss2si64", - "llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_cvttss2usi", - // [DUPLICATE]: "llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_vcvttss2usi32", - "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_cvttss2usi64", - // [DUPLICATE]: "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_vcvttss2usi64", + "llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_vcvttss2usi32", + // [DUPLICATE]: "llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_cvttss2usi", + "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_vcvttss2usi64", + // [DUPLICATE]: "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_cvttss2usi64", "llvm.x86.avx512.cvtusi2sd" => "__builtin_ia32_cvtusi2sd", - "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss", - // [DUPLICATE]: "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss32", + "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss32", + // [DUPLICATE]: "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss", "llvm.x86.avx512.cvtusi642sd" => "__builtin_ia32_cvtusi2sd64", // [DUPLICATE]: "llvm.x86.avx512.cvtusi642sd" => "__builtin_ia32_cvtusi642sd", "llvm.x86.avx512.cvtusi642ss" => "__builtin_ia32_cvtusi2ss64", @@ -3479,10 +3479,10 @@ match name { "llvm.x86.avx512.rcp14.ss" => "__builtin_ia32_rcp14ss_mask", "llvm.x86.avx512.rcp28.pd" => "__builtin_ia32_rcp28pd_mask", "llvm.x86.avx512.rcp28.ps" => "__builtin_ia32_rcp28ps_mask", - "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_mask", - // [DUPLICATE]: "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_round_mask", - "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_mask", - // [DUPLICATE]: "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_round_mask", + "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_round_mask", + // [DUPLICATE]: "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_mask", + "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_round_mask", + // [DUPLICATE]: "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_mask", "llvm.x86.avx512.rndscale.sd" => "__builtin_ia32_rndscalesd", "llvm.x86.avx512.rndscale.ss" => "__builtin_ia32_rndscaless", "llvm.x86.avx512.rsqrt14.pd.128" => "__builtin_ia32_rsqrt14pd128_mask", @@ -3495,10 +3495,10 @@ match name { "llvm.x86.avx512.rsqrt14.ss" => "__builtin_ia32_rsqrt14ss_mask", "llvm.x86.avx512.rsqrt28.pd" => "__builtin_ia32_rsqrt28pd_mask", "llvm.x86.avx512.rsqrt28.ps" => "__builtin_ia32_rsqrt28ps_mask", - "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_mask", - // [DUPLICATE]: "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_round_mask", - "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_mask", - // [DUPLICATE]: "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_round_mask", + "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_round_mask", + // [DUPLICATE]: "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_mask", + "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_round_mask", + // [DUPLICATE]: "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_mask", "llvm.x86.avx512.scatter.dpd.512" => "__builtin_ia32_scattersiv8df", "llvm.x86.avx512.scatter.dpi.512" => "__builtin_ia32_scattersiv16si", "llvm.x86.avx512.scatter.dpq.512" => "__builtin_ia32_scattersiv8di", diff --git a/tools/generate_intrinsics.py b/tools/generate_intrinsics.py index 64f14143381c..a1e28c3181c9 100644 --- a/tools/generate_intrinsics.py +++ b/tools/generate_intrinsics.py @@ -144,12 +144,34 @@ def extract_instrinsics_from_llvmint(llvmint, intrinsics): append_translation(json_data, p, intrinsics[arch]) +def fill_intrinsics(intrinsics, from_intrinsics, all_intrinsics): + for arch in from_intrinsics: + if arch not in intrinsics: + intrinsics[arch] = [] + for entry in from_intrinsics[arch]: + if entry[0] in all_intrinsics: + if all_intrinsics[entry[0]] == entry[1]: + # This is a "full" duplicate, both the LLVM instruction and the GCC + # translation are the same. + continue + intrinsics[arch].append((entry[0], entry[1], True)) + else: + intrinsics[arch].append((entry[0], entry[1], False)) + all_intrinsics[entry[0]] = entry[1] + + def update_intrinsics(llvm_path, llvmint): - intrinsics = {} + intrinsics_llvm = {} + intrinsics_llvmint = {} all_intrinsics = {} - extract_instrinsics_from_llvm(llvm_path, intrinsics) - extract_instrinsics_from_llvmint(llvmint, intrinsics) + extract_instrinsics_from_llvm(llvm_path, intrinsics_llvm) + extract_instrinsics_from_llvmint(llvmint, intrinsics_llvmint) + + intrinsics = {} + # We give priority to translations from LLVM over the ones from llvmint. + fill_intrinsics(intrinsics, intrinsics_llvm, all_intrinsics) + fill_intrinsics(intrinsics, intrinsics_llvmint, all_intrinsics) archs = [arch for arch in intrinsics] archs.sort() @@ -166,18 +188,13 @@ def update_intrinsics(llvm_path, llvmint): for arch in archs: if len(intrinsics[arch]) == 0: continue - intrinsics[arch].sort() + intrinsics[arch].sort(key=lambda x: (x[0], x[2])) out.write(' // {}\n'.format(arch)) for entry in intrinsics[arch]: - if entry[0] in all_intrinsics: - if all_intrinsics[entry[0]] == entry[1]: - # This is a "full" duplicate, both the LLVM instruction and the GCC - # translation are the same. - continue + if entry[2] == True: # if it is a duplicate out.write(' // [DUPLICATE]: "{}" => "{}",\n'.format(entry[0], entry[1])) else: out.write(' "{}" => "{}",\n'.format(entry[0], entry[1])) - all_intrinsics[entry[0]] = entry[1] out.write(' _ => unimplemented!("***** unsupported LLVM intrinsic {}", name),\n') out.write("}\n") print("Done!") From 5088fb3d3b20fa20a72425e1d214343c9ed7251a Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 24 Apr 2022 12:02:16 -0400 Subject: [PATCH 080/356] Cast arguments in SIMD function --- src/intrinsic/simd.rs | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index f1167bc3a3b6..e5753e318c7f 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -539,6 +539,14 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let vec_ty = bx.cx.type_vector(elem_ty, in_len as u64); let func = bx.context.get_target_builtin_function(builtin_name); + let param1_type = func.get_parameter(0).get_type(); + let lhs = + if lhs.get_type() != param1_type { + bx.context.new_bitcast(None, lhs, param1_type) + } + else { + lhs + }; let result = bx.context.new_call(None, func, &[lhs, rhs]); // TODO(antoyo): perhaps use __builtin_convertvector for vector casting. return Ok(bx.context.new_bitcast(None, result, vec_ty)); From 4636c59df5a7be4e47758588ad188bcb1f666f7c Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Fri, 29 Apr 2022 23:14:26 -0400 Subject: [PATCH 081/356] Add more SIMD --- src/builder.rs | 2 +- src/consts.rs | 15 +------- src/context.rs | 9 +++++ src/intrinsic/llvm.rs | 19 ++++++++++ src/intrinsic/simd.rs | 87 +++++++++++++++++++++++++++++++++++-------- 5 files changed, 102 insertions(+), 30 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index 9a5cf785a1f5..f0b93c3d5170 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1343,7 +1343,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { } // TODO(antoyo): switch to using new_vector_access. let array = self.context.new_bitcast(None, v2, array_type); - for i in 0..vec_num_units { + for i in 0..(mask_num_units - vec_num_units) { elements.push(self.context.new_array_access(None, array, self.context.new_rvalue_from_int(self.int_type, i as i32)).to_rvalue()); } let v1 = self.context.new_rvalue_from_vector(None, result_type, &elements); diff --git a/src/consts.rs b/src/consts.rs index 4350c00e94a7..4b517fd85f05 100644 --- a/src/consts.rs +++ b/src/consts.rs @@ -27,12 +27,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { } // NOTE: since bitcast makes a value non-constant, don't bitcast if not necessary as some // SIMD builtins require a constant value. - if value.get_type() != typ { - self.context.new_bitcast(None, value, typ) - } - else { - value - } + self.bitcast_if_needed(value, typ) } } @@ -86,13 +81,7 @@ impl<'gcc, 'tcx> StaticMethods for CodegenCx<'gcc, 'tcx> { // TODO(antoyo): set alignment. - let value = - if value.get_type() != gcc_type { - self.context.new_bitcast(None, value, gcc_type) - } - else { - value - }; + let value = self.bitcast_if_needed(value, gcc_type); global.global_set_initializer_rvalue(value); // As an optimization, all shared statics which do not have interior diff --git a/src/context.rs b/src/context.rs index 83c4683a6683..92b30ef9b4d8 100644 --- a/src/context.rs +++ b/src/context.rs @@ -279,6 +279,15 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { pub fn sess(&self) -> &Session { &self.tcx.sess } + + pub fn bitcast_if_needed(&self, value: RValue<'gcc>, expected_type: Type<'gcc>) -> RValue<'gcc> { + if value.get_type() != expected_type { + self.context.new_bitcast(None, value, expected_type) + } + else { + value + } + } } impl<'gcc, 'tcx> BackendTypes for CodegenCx<'gcc, 'tcx> { diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 4b41b0ba6e78..aab93b927558 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -21,6 +21,25 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.xgetbv" => "__builtin_ia32_xgetbv", // NOTE: this doc specifies the equivalent GCC builtins: http://huonw.github.io/llvmint/llvmint/x86/index.html "llvm.sqrt.v2f64" => "__builtin_ia32_sqrtpd", + + // The above doc points to unknown builtins for the following, so override them: + "llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gathersiv4si", + "llvm.x86.avx2.gather.d.d.256" => "__builtin_ia32_gathersiv8si", + "llvm.x86.avx2.gather.d.ps" => "__builtin_ia32_gathersiv4sf", + "llvm.x86.avx2.gather.d.ps.256" => "__builtin_ia32_gathersiv8sf", + "llvm.x86.avx2.gather.d.q" => "__builtin_ia32_gathersiv2di", + "llvm.x86.avx2.gather.d.q.256" => "__builtin_ia32_gathersiv4di", + "llvm.x86.avx2.gather.d.pd" => "__builtin_ia32_gathersiv2df", + "llvm.x86.avx2.gather.d.pd.256" => "__builtin_ia32_gathersiv4df", + "llvm.x86.avx2.gather.q.d" => "__builtin_ia32_gatherdiv4si", + "llvm.x86.avx2.gather.q.d.256" => "__builtin_ia32_gatherdiv4si256", + "llvm.x86.avx2.gather.q.ps" => "__builtin_ia32_gatherdiv4sf", + "llvm.x86.avx2.gather.q.ps.256" => "__builtin_ia32_gatherdiv4sf256", + "llvm.x86.avx2.gather.q.q" => "__builtin_ia32_gatherdiv2di", + "llvm.x86.avx2.gather.q.q.256" => "__builtin_ia32_gatherdiv4di", + "llvm.x86.avx2.gather.q.pd" => "__builtin_ia32_gatherdiv2df", + "llvm.x86.avx2.gather.q.pd.256" => "__builtin_ia32_gatherdiv4df", + "" => "", // NOTE: this file is generated by https://github.com/GuillaumeGomez/llvmint/blob/master/generate_list.py _ => include!("archs.rs"), }; diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index e5753e318c7f..9204fbdfaba7 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -202,14 +202,8 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, }; let builtin = bx.context.get_target_builtin_function(func_name); let param1_type = builtin.get_param(0).to_rvalue().get_type(); - let vector = - if vector.get_type() != param1_type { - // TODO(antoyo): perhaps use __builtin_convertvector for vector casting. - bx.context.new_bitcast(None, vector, param1_type) - } - else { - vector - }; + // TODO(antoyo): perhaps use __builtin_convertvector for vector casting. + let vector = bx.cx.bitcast_if_needed(vector, param1_type); let result = bx.context.new_call(None, builtin, &[vector, value, bx.context.new_cast(None, index, bx.int_type)]); // TODO(antoyo): perhaps use __builtin_convertvector for vector casting. return Ok(bx.context.new_bitcast(None, result, vector.get_type())); @@ -539,18 +533,79 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let vec_ty = bx.cx.type_vector(elem_ty, in_len as u64); let func = bx.context.get_target_builtin_function(builtin_name); - let param1_type = func.get_parameter(0).get_type(); - let lhs = - if lhs.get_type() != param1_type { - bx.context.new_bitcast(None, lhs, param1_type) - } - else { - lhs - }; + let param1_type = func.get_param(0).to_rvalue().get_type(); + let param2_type = func.get_param(1).to_rvalue().get_type(); + let lhs = bx.cx.bitcast_if_needed(lhs, param1_type); + let rhs = bx.cx.bitcast_if_needed(rhs, param2_type); let result = bx.context.new_call(None, func, &[lhs, rhs]); // TODO(antoyo): perhaps use __builtin_convertvector for vector casting. return Ok(bx.context.new_bitcast(None, result, vec_ty)); } + macro_rules! arith_red { + ($name:ident : $integer_reduce:ident, $float_reduce:ident, $ordered:expr, $op:ident, + $identity:expr) => { + if name == sym::$name { + require!( + ret_ty == in_elem, + "expected return type `{}` (element of input `{}`), found `{}`", + in_elem, + in_ty, + ret_ty + ); + return match in_elem.kind() { + ty::Int(_) | ty::Uint(_) => { + let r = bx.$integer_reduce(args[0].immediate()); + if $ordered { + // if overflow occurs, the result is the + // mathematical result modulo 2^n: + Ok(bx.$op(args[1].immediate(), r)) + } else { + Ok(bx.$integer_reduce(args[0].immediate())) + } + } + ty::Float(f) => { + let acc = if $ordered { + // ordered arithmetic reductions take an accumulator + args[1].immediate() + } else { + // unordered arithmetic reductions use the identity accumulator + match f.bit_width() { + 32 => bx.const_real(bx.type_f32(), $identity), + 64 => bx.const_real(bx.type_f64(), $identity), + v => return_error!( + r#" +unsupported {} from `{}` with element `{}` of size `{}` to `{}`"#, + sym::$name, + in_ty, + in_elem, + v, + ret_ty + ), + } + }; + Ok(bx.$float_reduce(acc, args[0].immediate())) + } + _ => return_error!( + "unsupported {} from `{}` with element `{}` to `{}`", + sym::$name, + in_ty, + in_elem, + ret_ty + ), + }; + } + }; + } + + // TODO: use a recursive algorithm a-la Hacker's Delight. + arith_red!( + simd_reduce_add_unordered: vector_reduce_add, + vector_reduce_fadd_fast, + false, + add, + 0.0 + ); + unimplemented!("simd {}", name); } From ddc152b04d202123270d7cbfb3f821a392297685 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 30 Apr 2022 20:52:00 -0400 Subject: [PATCH 082/356] Add more SIMD --- src/asm.rs | 2 +- src/builder.rs | 80 +++++++++++++++++++++++ src/common.rs | 4 +- src/intrinsic/simd.rs | 145 ++++++++++++++++++++++++++++++++++-------- src/type_.rs | 4 ++ 5 files changed, 204 insertions(+), 31 deletions(-) diff --git a/src/asm.rs b/src/asm.rs index 1cae78114c9d..738c990fa827 100644 --- a/src/asm.rs +++ b/src/asm.rs @@ -595,7 +595,7 @@ fn reg_to_gcc(reg: InlineAsmRegOrRegClass) -> ConstraintOrRegister { InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg) | InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg) => "x", InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => "v", - InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => unimplemented!(), + InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => "Yk", InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => unimplemented!(), InlineAsmRegClass::X86( X86InlineAsmRegClass::x87_reg | X86InlineAsmRegClass::mmx_reg, diff --git a/src/builder.rs b/src/builder.rs index f0b93c3d5170..160a7df03158 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -7,6 +7,7 @@ use gccjit::{ BinaryOp, Block, ComparisonOp, + Context, Function, LValue, RValue, @@ -1380,6 +1381,85 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { pub fn shuffle_vector(&mut self, _v1: RValue<'gcc>, _v2: RValue<'gcc>, _mask: RValue<'gcc>) -> RValue<'gcc> { unimplemented!(); } + + pub fn vector_reduce(&mut self, src: RValue<'gcc>, op: F) -> RValue<'gcc> + where F: Fn(RValue<'gcc>, RValue<'gcc>, &'gcc Context<'gcc>) -> RValue<'gcc> + { + let vector_type = src.get_type().unqualified().dyncast_vector().expect("vector type"); + let element_count = vector_type.get_num_units(); + let mut vector_elements = vec![]; + for i in 0..element_count { + vector_elements.push(i); + } + let mask_type = self.context.new_vector_type(self.int_type, element_count as u64); + let mut shift = 1; + let mut res = src; + while shift < element_count { + let vector_elements: Vec<_> = + vector_elements.iter() + .map(|i| self.context.new_rvalue_from_int(self.int_type, ((i + shift) % element_count) as i32)) + .collect(); + let mask = self.context.new_rvalue_from_vector(None, mask_type, &vector_elements); + let shifted = self.context.new_rvalue_vector_perm(None, res, res, mask); + shift *= 2; + res = op(res, shifted, &self.context); + } + self.context.new_vector_access(None, res, self.context.new_rvalue_zero(self.int_type)) + .to_rvalue() + } + + pub fn vector_reduce_op(&mut self, src: RValue<'gcc>, op: BinaryOp) -> RValue<'gcc> { + self.vector_reduce(src, |a, b, context| context.new_binary_op(None, op, a.get_type(), a, b)) + } + + pub fn vector_reduce_fadd_fast(&mut self, acc: RValue<'gcc>, src: RValue<'gcc>) -> RValue<'gcc> { + unimplemented!(); + } + + pub fn vector_reduce_fmul_fast(&mut self, acc: RValue<'gcc>, src: RValue<'gcc>) -> RValue<'gcc> { + unimplemented!(); + } + + // Inspired by Hacker's Delight min implementation. + pub fn vector_reduce_min(&mut self, src: RValue<'gcc>) -> RValue<'gcc> { + self.vector_reduce(src, |a, b, context| { + let differences_or_zeros = difference_or_zero(a, b, context); + context.new_binary_op(None, BinaryOp::Minus, a.get_type(), a, differences_or_zeros) + }) + } + + // Inspired by Hacker's Delight max implementation. + pub fn vector_reduce_max(&mut self, src: RValue<'gcc>) -> RValue<'gcc> { + self.vector_reduce(src, |a, b, context| { + let differences_or_zeros = difference_or_zero(a, b, context); + context.new_binary_op(None, BinaryOp::Plus, b.get_type(), b, differences_or_zeros) + }) + } + + pub fn vector_select(&mut self, cond: RValue<'gcc>, then_val: RValue<'gcc>, else_val: RValue<'gcc>) -> RValue<'gcc> { + // cond is a vector of integers, not of bools. + let vector_type = cond.get_type().dyncast_vector().expect("vector type"); + let num_units = vector_type.get_num_units(); + let vector_type = self.context.new_vector_type(self.int_type, num_units as u64); + let zeros = vec![self.context.new_rvalue_zero(self.int_type); num_units]; + let zeros = self.context.new_rvalue_from_vector(None, vector_type, &zeros); + + let masks = self.context.new_comparison(None, ComparisonOp::NotEquals, cond, zeros); + let then_vals = masks & then_val; + + let ones = vec![self.context.new_rvalue_one(self.int_type); num_units]; + let ones = self.context.new_rvalue_from_vector(None, vector_type, &ones); + let inverted_masks = masks + ones; + let else_vals = inverted_masks & else_val; + + then_vals | else_vals + } +} + +fn difference_or_zero<'gcc>(a: RValue<'gcc>, b: RValue<'gcc>, context: &'gcc Context<'gcc>) -> RValue<'gcc> { + let difference = a - b; + let masks = context.new_comparison(None, ComparisonOp::GreaterThanEquals, b, a); + difference & masks } impl<'a, 'gcc, 'tcx> StaticBuilderMethods for Builder<'a, 'gcc, 'tcx> { diff --git a/src/common.rs b/src/common.rs index 703e20947fe8..e4a08da446bb 100644 --- a/src/common.rs +++ b/src/common.rs @@ -117,8 +117,8 @@ impl<'gcc, 'tcx> ConstMethods<'tcx> for CodegenCx<'gcc, 'tcx> { unimplemented!(); } - fn const_real(&self, _t: Type<'gcc>, _val: f64) -> RValue<'gcc> { - unimplemented!(); + fn const_real(&self, typ: Type<'gcc>, val: f64) -> RValue<'gcc> { + self.context.new_rvalue_from_double(typ, val) } fn const_str(&self, s: Symbol) -> (RValue<'gcc>, RValue<'gcc>) { diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index 9204fbdfaba7..dccfb89409de 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -1,6 +1,6 @@ use std::cmp::Ordering; -use gccjit::{RValue, Type, ToRValue}; +use gccjit::{BinaryOp, RValue, Type, ToRValue}; use rustc_codegen_ssa::base::compare_simd_types; use rustc_codegen_ssa::common::{TypeKind, span_invalid_monomorphization_error}; use rustc_codegen_ssa::mir::operand::OperandRef; @@ -222,6 +222,24 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, return Ok(bx.context.new_vector_access(None, vector, args[1].immediate()).to_rvalue()); } + if name == sym::simd_select { + let m_elem_ty = in_elem; + let m_len = in_len; + require_simd!(arg_tys[1], "argument"); + let (v_len, _) = arg_tys[1].simd_size_and_type(bx.tcx()); + require!( + m_len == v_len, + "mismatched lengths: mask length `{}` != other vector length `{}`", + m_len, + v_len + ); + match m_elem_ty.kind() { + ty::Int(_) => {} + _ => return_error!("mask element type is `{}`, expected `i_`", m_elem_ty), + } + return Ok(bx.vector_select(args[0].immediate(), args[1].immediate(), args[2].immediate())); + } + if name == sym::simd_cast { require_simd!(ret_ty, "return"); let (out_len, out_elem) = ret_ty.simd_size_and_type(bx.tcx()); @@ -543,7 +561,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, } macro_rules! arith_red { - ($name:ident : $integer_reduce:ident, $float_reduce:ident, $ordered:expr, $op:ident, + ($name:ident : $vec_op:expr, $float_reduce:ident, $ordered:expr, $op:ident, $identity:expr) => { if name == sym::$name { require!( @@ -555,36 +573,25 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, ); return match in_elem.kind() { ty::Int(_) | ty::Uint(_) => { - let r = bx.$integer_reduce(args[0].immediate()); + let r = bx.vector_reduce_op(args[0].immediate(), $vec_op); if $ordered { // if overflow occurs, the result is the // mathematical result modulo 2^n: Ok(bx.$op(args[1].immediate(), r)) - } else { - Ok(bx.$integer_reduce(args[0].immediate())) + } + else { + Ok(bx.vector_reduce_op(args[0].immediate(), $vec_op)) } } - ty::Float(f) => { - let acc = if $ordered { + ty::Float(_) => { + if $ordered { // ordered arithmetic reductions take an accumulator - args[1].immediate() - } else { - // unordered arithmetic reductions use the identity accumulator - match f.bit_width() { - 32 => bx.const_real(bx.type_f32(), $identity), - 64 => bx.const_real(bx.type_f64(), $identity), - v => return_error!( - r#" -unsupported {} from `{}` with element `{}` of size `{}` to `{}`"#, - sym::$name, - in_ty, - in_elem, - v, - ret_ty - ), - } - }; - Ok(bx.$float_reduce(acc, args[0].immediate())) + let acc = args[1].immediate(); + Ok(bx.$float_reduce(acc, args[0].immediate())) + } + else { + Ok(bx.vector_reduce_op(args[0].immediate(), $vec_op)) + } } _ => return_error!( "unsupported {} from `{}` with element `{}` to `{}`", @@ -598,14 +605,96 @@ unsupported {} from `{}` with element `{}` of size `{}` to `{}`"#, }; } - // TODO: use a recursive algorithm a-la Hacker's Delight. arith_red!( - simd_reduce_add_unordered: vector_reduce_add, + simd_reduce_add_unordered: BinaryOp::Plus, vector_reduce_fadd_fast, false, add, - 0.0 + 0.0 // TODO: Use this argument. ); + arith_red!( + simd_reduce_mul_unordered: BinaryOp::Mult, + vector_reduce_fmul_fast, + false, + mul, + 1.0 + ); + + macro_rules! minmax_red { + ($name:ident: $reduction:ident) => { + if name == sym::$name { + require!( + ret_ty == in_elem, + "expected return type `{}` (element of input `{}`), found `{}`", + in_elem, + in_ty, + ret_ty + ); + return match in_elem.kind() { + ty::Int(_) | ty::Uint(_) | ty::Float(_) => Ok(bx.$reduction(args[0].immediate())), + _ => return_error!( + "unsupported {} from `{}` with element `{}` to `{}`", + sym::$name, + in_ty, + in_elem, + ret_ty + ), + }; + } + }; + } + + minmax_red!(simd_reduce_min: vector_reduce_min); + minmax_red!(simd_reduce_max: vector_reduce_max); + + macro_rules! bitwise_red { + ($name:ident : $op:expr, $boolean:expr) => { + if name == sym::$name { + let input = if !$boolean { + require!( + ret_ty == in_elem, + "expected return type `{}` (element of input `{}`), found `{}`", + in_elem, + in_ty, + ret_ty + ); + args[0].immediate() + } else { + match in_elem.kind() { + ty::Int(_) | ty::Uint(_) => {} + _ => return_error!( + "unsupported {} from `{}` with element `{}` to `{}`", + sym::$name, + in_ty, + in_elem, + ret_ty + ), + } + + // boolean reductions operate on vectors of i1s: + let i1 = bx.type_i1(); + let i1xn = bx.type_vector(i1, in_len as u64); + bx.trunc(args[0].immediate(), i1xn) + }; + return match in_elem.kind() { + ty::Int(_) | ty::Uint(_) => { + let r = bx.vector_reduce_op(input, $op); + Ok(if !$boolean { r } else { bx.zext(r, bx.type_bool()) }) + } + _ => return_error!( + "unsupported {} from `{}` with element `{}` to `{}`", + sym::$name, + in_ty, + in_elem, + ret_ty + ), + }; + } + }; + } + + bitwise_red!(simd_reduce_and: BinaryOp::BitwiseAnd, false); + bitwise_red!(simd_reduce_or: BinaryOp::BitwiseOr, false); unimplemented!("simd {}", name); } diff --git a/src/type_.rs b/src/type_.rs index db2b5ea8ab20..002b95db36de 100644 --- a/src/type_.rs +++ b/src/type_.rs @@ -247,6 +247,10 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { self.context.new_array_type(None, ty, len) } + + pub fn type_bool(&self) -> Type<'gcc> { + self.context.new_type::() + } } pub fn struct_fields<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, layout: TyAndLayout<'tcx>) -> (Vec>, bool) { From a65418666f89629f1ec9acdf1e29b29e35344574 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 1 May 2022 12:39:47 -0400 Subject: [PATCH 083/356] Implement simd_select_bitmask --- src/builder.rs | 13 ++++++----- src/intrinsic/simd.rs | 52 +++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 57 insertions(+), 8 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index 160a7df03158..71738b52eff4 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1438,17 +1438,18 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { pub fn vector_select(&mut self, cond: RValue<'gcc>, then_val: RValue<'gcc>, else_val: RValue<'gcc>) -> RValue<'gcc> { // cond is a vector of integers, not of bools. - let vector_type = cond.get_type().dyncast_vector().expect("vector type"); + let cond_type = cond.get_type(); + let vector_type = cond_type.unqualified().dyncast_vector().expect("vector type"); let num_units = vector_type.get_num_units(); - let vector_type = self.context.new_vector_type(self.int_type, num_units as u64); - let zeros = vec![self.context.new_rvalue_zero(self.int_type); num_units]; - let zeros = self.context.new_rvalue_from_vector(None, vector_type, &zeros); + let element_type = vector_type.get_element_type(); + let zeros = vec![self.context.new_rvalue_zero(element_type); num_units]; + let zeros = self.context.new_rvalue_from_vector(None, cond_type, &zeros); let masks = self.context.new_comparison(None, ComparisonOp::NotEquals, cond, zeros); let then_vals = masks & then_val; - let ones = vec![self.context.new_rvalue_one(self.int_type); num_units]; - let ones = self.context.new_rvalue_from_vector(None, vector_type, &ones); + let ones = vec![self.context.new_rvalue_one(element_type); num_units]; + let ones = self.context.new_rvalue_from_vector(None, cond_type, &ones); let inverted_masks = masks + ones; let else_vals = inverted_masks & else_val; diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index dccfb89409de..6e14f6d021e1 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -4,12 +4,14 @@ use gccjit::{BinaryOp, RValue, Type, ToRValue}; use rustc_codegen_ssa::base::compare_simd_types; use rustc_codegen_ssa::common::{TypeKind, span_invalid_monomorphization_error}; use rustc_codegen_ssa::mir::operand::OperandRef; +use rustc_codegen_ssa::mir::place::PlaceRef; use rustc_codegen_ssa::traits::{BaseTypeMethods, BuilderMethods}; use rustc_hir as hir; use rustc_middle::span_bug; use rustc_middle::ty::layout::HasTyCtxt; use rustc_middle::ty::{self, Ty}; use rustc_span::{Span, Symbol, sym}; +use rustc_target::abi::Align; use crate::builder::Builder; use crate::intrinsic; @@ -55,7 +57,53 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let sig = tcx.normalize_erasing_late_bound_regions(ty::ParamEnv::reveal_all(), callee_ty.fn_sig(tcx)); let arg_tys = sig.inputs(); - let name_str = name.as_str(); + + if name == sym::simd_select_bitmask { + require_simd!(arg_tys[1], "argument"); + let (len, _) = arg_tys[1].simd_size_and_type(bx.tcx()); + + let expected_int_bits = (len.max(8) - 1).next_power_of_two(); + let expected_bytes = len / 8 + ((len % 8 > 0) as u64); + + let mask_ty = arg_tys[0]; + let mut mask = match mask_ty.kind() { + ty::Int(i) if i.bit_width() == Some(expected_int_bits) => args[0].immediate(), + ty::Uint(i) if i.bit_width() == Some(expected_int_bits) => args[0].immediate(), + ty::Array(elem, len) + if matches!(elem.kind(), ty::Uint(ty::UintTy::U8)) + && len.try_eval_usize(bx.tcx, ty::ParamEnv::reveal_all()) + == Some(expected_bytes) => + { + let place = PlaceRef::alloca(bx, args[0].layout); + args[0].val.store(bx, place); + let int_ty = bx.type_ix(expected_bytes * 8); + let ptr = bx.pointercast(place.llval, bx.cx.type_ptr_to(int_ty)); + bx.load(int_ty, ptr, Align::ONE) + } + _ => return_error!( + "invalid bitmask `{}`, expected `u{}` or `[u8; {}]`", + mask_ty, + expected_int_bits, + expected_bytes + ), + }; + + let arg1 = args[1].immediate(); + let arg1_type = arg1.get_type(); + let arg1_vector_type = arg1_type.unqualified().dyncast_vector().expect("vector type"); + let arg1_element_type = arg1_vector_type.get_element_type(); + + let mut elements = vec![]; + let one = bx.context.new_rvalue_one(mask.get_type()); + for _ in 0..len { + let element = bx.context.new_cast(None, mask & one, arg1_element_type); + elements.push(element); + mask = mask >> one; + } + let vector_mask = bx.context.new_rvalue_from_vector(None, arg1_type, &elements); + + return Ok(bx.vector_select(vector_mask, arg1, args[2].immediate())); + } // every intrinsic below takes a SIMD vector as its first argument require_simd!(arg_tys[0], "input"); @@ -102,7 +150,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, )); } - if let Some(stripped) = name_str.strip_prefix("simd_shuffle") { + if let Some(stripped) = name.as_str().strip_prefix("simd_shuffle") { let n: u64 = if stripped.is_empty() { // Make sure this is actually an array, since typeck only checks the length-suffixed From ace3250da87542526952ce3177f6950410133d1e Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 1 May 2022 12:52:59 -0400 Subject: [PATCH 084/356] Fix shuffle_vector --- src/builder.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/builder.rs b/src/builder.rs index 71738b52eff4..a53115c578b2 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1317,7 +1317,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { element_type } else { - self.int_type + self.cx.type_ix(element_type.get_size() as u64 * 8) }; for i in 0..mask_num_units { let field = struct_type.get_field(i as i32); From 6bfe2b0b05837ae671d9206b81539f998965b017 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Mon, 2 May 2022 21:50:22 -0400 Subject: [PATCH 085/356] Support more SIMD intrinsics --- src/builder.rs | 104 ++++++++++++++++++++++++++++++++++++++++- src/context.rs | 14 +++++- src/declare.rs | 5 +- src/intrinsic/archs.rs | 5 +- src/intrinsic/llvm.rs | 18 +++++++ 5 files changed, 141 insertions(+), 5 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index a53115c578b2..82b0e64e582a 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -217,11 +217,27 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { return Cow::Borrowed(args); } + let func_name = format!("{:?}", func_ptr); + let casted_args: Vec<_> = param_types .into_iter() .zip(args.iter()) .enumerate() .map(|(index, (expected_ty, &actual_val))| { + // NOTE: these intrinsics have missing parameters before the last one, so ignore the + // last argument type check. + // FIXME(antoyo): find a way to refactor in order to avoid this hack. + match &*func_name { + "__builtin_ia32_maxps512_mask" | "__builtin_ia32_maxpd512_mask" + | "__builtin_ia32_minps512_mask" | "__builtin_ia32_minpd512_mask" | "__builtin_ia32_sqrtps512_mask" + | "__builtin_ia32_sqrtpd512_mask" => { + if index == args.len() - 1 { + return actual_val; + } + }, + _ => (), + } + let actual_ty = actual_val.get_type(); if expected_ty != actual_ty { if !actual_ty.is_vector() && !expected_ty.is_vector() && actual_ty.is_integral() && expected_ty.is_integral() && actual_ty.get_size() != expected_ty.get_size() { @@ -286,7 +302,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { } fn function_ptr_call(&mut self, func_ptr: RValue<'gcc>, args: &[RValue<'gcc>], _funclet: Option<&Funclet>) -> RValue<'gcc> { - let args = self.check_ptr_call("call", func_ptr, args); + let mut args = self.check_ptr_call("call", func_ptr, args); // gccjit requires to use the result of functions, even when it's not used. // That's why we assign the result to a local or call add_eval(). @@ -298,6 +314,92 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { if return_type != void_type { unsafe { RETURN_VALUE_COUNT += 1 }; let result = current_func.new_local(None, return_type, &format!("ptrReturnValue{}", unsafe { RETURN_VALUE_COUNT })); + // Some LLVM intrinsics do not map 1-to-1 to GCC intrinsics, so we add the missing + // arguments here. + if gcc_func.get_param_count() != args.len() { + let func_name = format!("{:?}", func_ptr); + match &*func_name { + "__builtin_ia32_pmuldq512_mask" | "__builtin_ia32_pmuludq512_mask" + // FIXME(antoyo): the following intrinsics has 4 (or 5) arguments according to the doc, but is defined with 2 (or 3) arguments in library/stdarch/crates/core_arch/src/x86/avx512f.rs. + | "__builtin_ia32_pmaxsd512_mask" | "__builtin_ia32_pmaxsq512_mask" | "__builtin_ia32_pmaxsq256_mask" + | "__builtin_ia32_pmaxsq128_mask" | "__builtin_ia32_maxps512_mask" | "__builtin_ia32_maxpd512_mask" + | "__builtin_ia32_pmaxud512_mask" | "__builtin_ia32_pmaxuq512_mask" | "__builtin_ia32_pmaxuq256_mask" + | "__builtin_ia32_pmaxuq128_mask" + | "__builtin_ia32_pminsd512_mask" | "__builtin_ia32_pminsq512_mask" | "__builtin_ia32_pminsq256_mask" + | "__builtin_ia32_pminsq128_mask" | "__builtin_ia32_minps512_mask" | "__builtin_ia32_minpd512_mask" + | "__builtin_ia32_pminud512_mask" | "__builtin_ia32_pminuq512_mask" | "__builtin_ia32_pminuq256_mask" + | "__builtin_ia32_pminuq128_mask" | "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" + => { + // TODO: refactor by separating those intrinsics outside of this branch. + let add_before_last_arg = + match &*func_name { + "__builtin_ia32_maxps512_mask" | "__builtin_ia32_maxpd512_mask" + | "__builtin_ia32_minps512_mask" | "__builtin_ia32_minpd512_mask" + | "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => true, + _ => false, + }; + let new_first_arg_is_zero = + match &*func_name { + "__builtin_ia32_pmaxuq256_mask" | "__builtin_ia32_pmaxuq128_mask" + | "__builtin_ia32_pminuq256_mask" | "__builtin_ia32_pminuq128_mask" => true, + _ => false + }; + let arg3_index = + match &*func_name { + "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => 1, + _ => 2, + }; + let mut new_args = args.to_vec(); + let arg3_type = gcc_func.get_param_type(arg3_index); + let first_arg = + if new_first_arg_is_zero { + let vector_type = arg3_type.dyncast_vector().expect("vector type"); + let zero = self.context.new_rvalue_zero(vector_type.get_element_type()); + let num_units = vector_type.get_num_units(); + self.context.new_rvalue_from_vector(None, arg3_type, &vec![zero; num_units]) + } + else { + self.current_func().new_local(None, arg3_type, "undefined_for_intrinsic").to_rvalue() + }; + if add_before_last_arg { + new_args.insert(new_args.len() - 1, first_arg); + } + else { + new_args.push(first_arg); + } + let arg4_index = + match &*func_name { + "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => 2, + _ => 3, + }; + let arg4_type = gcc_func.get_param_type(arg4_index); + let minus_one = self.context.new_rvalue_from_int(arg4_type, -1); + if add_before_last_arg { + new_args.insert(new_args.len() - 1, minus_one); + } + else { + new_args.push(minus_one); + } + args = new_args.into(); + }, + "__builtin_ia32_vfmaddps512_mask" | "__builtin_ia32_vfmaddpd512_mask" => { + let mut new_args = args.to_vec(); + if args.len() == 3 { + // Both llvm.fma.v16f32 and llvm.x86.avx512.vfmaddsub.ps.512 maps to + // the same GCC intrinsic, but the former has 3 parameters and the + // latter has 4 so it doesn't require this additional argument. + let arg4_type = gcc_func.get_param_type(3); + let minus_one = self.context.new_rvalue_from_int(arg4_type, -1); + new_args.push(minus_one); + } + + let arg5_type = gcc_func.get_param_type(4); + new_args.push(self.context.new_rvalue_from_int(arg5_type, 4)); + args = new_args.into(); + }, + _ => (), + } + } self.block.add_assignment(None, result, self.cx.context.new_call_through_ptr(None, func_ptr, &args)); result.to_rvalue() } diff --git a/src/context.rs b/src/context.rs index 92b30ef9b4d8..4bc8c5a6760e 100644 --- a/src/context.rs +++ b/src/context.rs @@ -35,6 +35,7 @@ pub struct CodegenCx<'gcc, 'tcx> { pub normal_function_addresses: RefCell>>, pub functions: RefCell>>, + pub intrinsics: RefCell>>, pub tls_model: gccjit::TlsModel, @@ -184,6 +185,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { current_func: RefCell::new(None), normal_function_addresses: Default::default(), functions: RefCell::new(functions), + intrinsics: RefCell::new(FxHashMap::default()), tls_model, @@ -315,8 +317,16 @@ impl<'gcc, 'tcx> MiscMethods<'tcx> for CodegenCx<'gcc, 'tcx> { } fn get_fn_addr(&self, instance: Instance<'tcx>) -> RValue<'gcc> { - let func = get_fn(self, instance); - let func = self.rvalue_as_function(func); + let func_name = self.tcx.symbol_name(instance).name; + + let func = + if self.intrinsics.borrow().contains_key(func_name) { + self.intrinsics.borrow()[func_name].clone() + } + else { + let func = get_fn(self, instance); + self.rvalue_as_function(func) + }; let ptr = func.get_address(None); // TODO(antoyo): don't do this twice: i.e. in declare_fn and here. diff --git a/src/declare.rs b/src/declare.rs index 43017376916d..8b2146c5aa84 100644 --- a/src/declare.rs +++ b/src/declare.rs @@ -11,6 +11,7 @@ use crate::intrinsic::llvm; impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { pub fn get_or_insert_global(&self, name: &str, ty: Type<'gcc>, is_tls: bool, link_section: Option) -> LValue<'gcc> { if self.globals.borrow().contains_key(name) { + // TODO: use [] instead of .get().expect()? let typ = self.globals.borrow().get(name).expect("global").get_type(); let global = self.context.new_global(None, GlobalKind::Imported, typ, name); if is_tls { @@ -103,7 +104,9 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { /// update the declaration and return existing Value instead. fn declare_raw_fn<'gcc>(cx: &CodegenCx<'gcc, '_>, name: &str, _callconv: () /*llvm::CallConv*/, return_type: Type<'gcc>, param_types: &[Type<'gcc>], variadic: bool) -> Function<'gcc> { if name.starts_with("llvm.") { - return llvm::intrinsic(name, cx); + let intrinsic = llvm::intrinsic(name, cx); + cx.intrinsics.borrow_mut().insert(name.to_string(), intrinsic); + return intrinsic; } let func = if cx.functions.borrow().contains_key(name) { diff --git a/src/intrinsic/archs.rs b/src/intrinsic/archs.rs index bfeb30f2913d..fbcfc8be8591 100644 --- a/src/intrinsic/archs.rs +++ b/src/intrinsic/archs.rs @@ -4275,5 +4275,8 @@ match name { "llvm.xcore.getid" => "__builtin_getid", "llvm.xcore.getps" => "__builtin_getps", "llvm.xcore.setps" => "__builtin_setps", - _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), + _ => { + println!("***** unsupported LLVM intrinsic {}", name); + "" + }, } diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index aab93b927558..16f0df8a2075 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -21,6 +21,24 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.xgetbv" => "__builtin_ia32_xgetbv", // NOTE: this doc specifies the equivalent GCC builtins: http://huonw.github.io/llvmint/llvmint/x86/index.html "llvm.sqrt.v2f64" => "__builtin_ia32_sqrtpd", + "llvm.x86.avx512.pmul.dq.512" => "__builtin_ia32_pmuldq512_mask", + "llvm.x86.avx512.pmulu.dq.512" => "__builtin_ia32_pmuludq512_mask", + "llvm.x86.avx512.mask.pmaxs.q.256" => "__builtin_ia32_pmaxsq256_mask", + "llvm.x86.avx512.mask.pmaxs.q.128" => "__builtin_ia32_pmaxsq128_mask", + "llvm.x86.avx512.max.ps.512" => "__builtin_ia32_maxps512_mask", + "llvm.x86.avx512.max.pd.512" => "__builtin_ia32_maxpd512_mask", + "llvm.x86.avx512.mask.pmaxu.q.256" => "__builtin_ia32_pmaxuq256_mask", + "llvm.x86.avx512.mask.pmaxu.q.128" => "__builtin_ia32_pmaxuq128_mask", + "llvm.x86.avx512.mask.pmins.q.256" => "__builtin_ia32_pminsq256_mask", + "llvm.x86.avx512.mask.pmins.q.128" => "__builtin_ia32_pminsq128_mask", + "llvm.x86.avx512.min.ps.512" => "__builtin_ia32_minps512_mask", + "llvm.x86.avx512.min.pd.512" => "__builtin_ia32_minpd512_mask", + "llvm.x86.avx512.mask.pminu.q.256" => "__builtin_ia32_pminuq256_mask", + "llvm.x86.avx512.mask.pminu.q.128" => "__builtin_ia32_pminuq128_mask", + "llvm.fma.v16f32" => "__builtin_ia32_vfmaddps512_mask", + "llvm.fma.v8f64" => "__builtin_ia32_vfmaddpd512_mask", + "llvm.x86.avx512.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddps512_mask", + "llvm.x86.avx512.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddpd512_mask", // The above doc points to unknown builtins for the following, so override them: "llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gathersiv4si", From eba654c57ae2fe29ae963b128e5bf57ac2d08a6c Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Tue, 3 May 2022 17:47:38 -0400 Subject: [PATCH 086/356] Support more SIMD intrinsics --- src/intrinsic/llvm.rs | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 16f0df8a2075..5c8367360838 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -39,6 +39,27 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.fma.v8f64" => "__builtin_ia32_vfmaddpd512_mask", "llvm.x86.avx512.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddps512_mask", "llvm.x86.avx512.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddpd512_mask", + "llvm.x86.avx512.rcp14.ps.256" => "__builtin_ia32_rcp14ps256_mask", + "llvm.x86.avx512.rcp14.ps.128" => "__builtin_ia32_rcp14ps128_mask", + "llvm.x86.avx512.rcp14.pd.256" => "__builtin_ia32_rcp14pd256_mask", + "llvm.x86.avx512.rcp14.pd.128" => "__builtin_ia32_rcp14pd128_mask", + "llvm.x86.avx512.rsqrt14.ps.256" => "__builtin_ia32_rsqrt14ps256_mask", + "llvm.x86.avx512.rsqrt14.ps.128" => "__builtin_ia32_rsqrt14ps128_mask", + "llvm.x86.avx512.rsqrt14.pd.256" => "__builtin_ia32_rsqrt14pd256_mask", + "llvm.x86.avx512.rsqrt14.pd.128" => "__builtin_ia32_rsqrt14pd128_mask", + "llvm.x86.avx512.mask.getexp.ps.512" => "__builtin_ia32_getexpps512_mask", + "llvm.x86.avx512.mask.getexp.ps.256" => "__builtin_ia32_getexpps256_mask", + "llvm.x86.avx512.mask.getexp.ps.128" => "__builtin_ia32_getexpps128_mask", + "llvm.x86.avx512.mask.getexp.pd.512" => "__builtin_ia32_getexppd512_mask", + "llvm.x86.avx512.mask.getexp.pd.256" => "__builtin_ia32_getexppd256_mask", + "llvm.x86.avx512.mask.getexp.pd.128" => "__builtin_ia32_getexppd128_mask", + "llvm.x86.avx512.mask.rndscale.ps.256" => "__builtin_ia32_rndscaleps_256_mask", + "llvm.x86.avx512.mask.rndscale.ps.128" => "__builtin_ia32_rndscaleps_128_mask", + "llvm.x86.avx512.mask.rndscale.pd.256" => "__builtin_ia32_rndscalepd_256_mask", + "llvm.x86.avx512.mask.rndscale.pd.128" => "__builtin_ia32_rndscalepd_128_mask", + "llvm.x86.avx512.mask.scalef.ps.512" => "__builtin_ia32_scalefps512_mask", + "llvm.x86.avx512.mask.scalef.ps.256" => "__builtin_ia32_scalefps256_mask", + "llvm.x86.avx512.mask.scalef.ps.128" => "__builtin_ia32_scalefps128_mask", // The above doc points to unknown builtins for the following, so override them: "llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gathersiv4si", From 4b40ac790da69d99028324540fa84404096f04ab Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Tue, 3 May 2022 22:35:26 -0400 Subject: [PATCH 087/356] Support more SIMD intrinsics and refactor argument adjustment --- src/builder.rs | 113 +++-------------------- src/intrinsic/llvm.rs | 207 +++++++++++++++++++++++++++++++++++++----- 2 files changed, 194 insertions(+), 126 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index 82b0e64e582a..df5c29f625eb 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -48,6 +48,7 @@ use rustc_target::spec::{HasTargetSpec, Target}; use crate::common::{SignType, TypeReflection, type_is_pointer}; use crate::context::CodegenCx; +use crate::intrinsic::llvm; use crate::type_of::LayoutGccExt; // TODO(antoyo) @@ -224,18 +225,8 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { .zip(args.iter()) .enumerate() .map(|(index, (expected_ty, &actual_val))| { - // NOTE: these intrinsics have missing parameters before the last one, so ignore the - // last argument type check. - // FIXME(antoyo): find a way to refactor in order to avoid this hack. - match &*func_name { - "__builtin_ia32_maxps512_mask" | "__builtin_ia32_maxpd512_mask" - | "__builtin_ia32_minps512_mask" | "__builtin_ia32_minpd512_mask" | "__builtin_ia32_sqrtps512_mask" - | "__builtin_ia32_sqrtpd512_mask" => { - if index == args.len() - 1 { - return actual_val; - } - }, - _ => (), + if llvm::ignore_arg_cast(&func_name, index, args.len()) { + return actual_val; } let actual_ty = actual_val.get_type(); @@ -302,7 +293,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { } fn function_ptr_call(&mut self, func_ptr: RValue<'gcc>, args: &[RValue<'gcc>], _funclet: Option<&Funclet>) -> RValue<'gcc> { - let mut args = self.check_ptr_call("call", func_ptr, args); + let args = self.check_ptr_call("call", func_ptr, args); // gccjit requires to use the result of functions, even when it's not used. // That's why we assign the result to a local or call add_eval(). @@ -314,92 +305,8 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { if return_type != void_type { unsafe { RETURN_VALUE_COUNT += 1 }; let result = current_func.new_local(None, return_type, &format!("ptrReturnValue{}", unsafe { RETURN_VALUE_COUNT })); - // Some LLVM intrinsics do not map 1-to-1 to GCC intrinsics, so we add the missing - // arguments here. - if gcc_func.get_param_count() != args.len() { - let func_name = format!("{:?}", func_ptr); - match &*func_name { - "__builtin_ia32_pmuldq512_mask" | "__builtin_ia32_pmuludq512_mask" - // FIXME(antoyo): the following intrinsics has 4 (or 5) arguments according to the doc, but is defined with 2 (or 3) arguments in library/stdarch/crates/core_arch/src/x86/avx512f.rs. - | "__builtin_ia32_pmaxsd512_mask" | "__builtin_ia32_pmaxsq512_mask" | "__builtin_ia32_pmaxsq256_mask" - | "__builtin_ia32_pmaxsq128_mask" | "__builtin_ia32_maxps512_mask" | "__builtin_ia32_maxpd512_mask" - | "__builtin_ia32_pmaxud512_mask" | "__builtin_ia32_pmaxuq512_mask" | "__builtin_ia32_pmaxuq256_mask" - | "__builtin_ia32_pmaxuq128_mask" - | "__builtin_ia32_pminsd512_mask" | "__builtin_ia32_pminsq512_mask" | "__builtin_ia32_pminsq256_mask" - | "__builtin_ia32_pminsq128_mask" | "__builtin_ia32_minps512_mask" | "__builtin_ia32_minpd512_mask" - | "__builtin_ia32_pminud512_mask" | "__builtin_ia32_pminuq512_mask" | "__builtin_ia32_pminuq256_mask" - | "__builtin_ia32_pminuq128_mask" | "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" - => { - // TODO: refactor by separating those intrinsics outside of this branch. - let add_before_last_arg = - match &*func_name { - "__builtin_ia32_maxps512_mask" | "__builtin_ia32_maxpd512_mask" - | "__builtin_ia32_minps512_mask" | "__builtin_ia32_minpd512_mask" - | "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => true, - _ => false, - }; - let new_first_arg_is_zero = - match &*func_name { - "__builtin_ia32_pmaxuq256_mask" | "__builtin_ia32_pmaxuq128_mask" - | "__builtin_ia32_pminuq256_mask" | "__builtin_ia32_pminuq128_mask" => true, - _ => false - }; - let arg3_index = - match &*func_name { - "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => 1, - _ => 2, - }; - let mut new_args = args.to_vec(); - let arg3_type = gcc_func.get_param_type(arg3_index); - let first_arg = - if new_first_arg_is_zero { - let vector_type = arg3_type.dyncast_vector().expect("vector type"); - let zero = self.context.new_rvalue_zero(vector_type.get_element_type()); - let num_units = vector_type.get_num_units(); - self.context.new_rvalue_from_vector(None, arg3_type, &vec![zero; num_units]) - } - else { - self.current_func().new_local(None, arg3_type, "undefined_for_intrinsic").to_rvalue() - }; - if add_before_last_arg { - new_args.insert(new_args.len() - 1, first_arg); - } - else { - new_args.push(first_arg); - } - let arg4_index = - match &*func_name { - "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => 2, - _ => 3, - }; - let arg4_type = gcc_func.get_param_type(arg4_index); - let minus_one = self.context.new_rvalue_from_int(arg4_type, -1); - if add_before_last_arg { - new_args.insert(new_args.len() - 1, minus_one); - } - else { - new_args.push(minus_one); - } - args = new_args.into(); - }, - "__builtin_ia32_vfmaddps512_mask" | "__builtin_ia32_vfmaddpd512_mask" => { - let mut new_args = args.to_vec(); - if args.len() == 3 { - // Both llvm.fma.v16f32 and llvm.x86.avx512.vfmaddsub.ps.512 maps to - // the same GCC intrinsic, but the former has 3 parameters and the - // latter has 4 so it doesn't require this additional argument. - let arg4_type = gcc_func.get_param_type(3); - let minus_one = self.context.new_rvalue_from_int(arg4_type, -1); - new_args.push(minus_one); - } - - let arg5_type = gcc_func.get_param_type(4); - new_args.push(self.context.new_rvalue_from_int(arg5_type, 4)); - args = new_args.into(); - }, - _ => (), - } - } + let func_name = format!("{:?}", func_ptr); + let args = llvm::adjust_intrinsic_arguments(&self, gcc_func, args, &func_name); self.block.add_assignment(None, result, self.cx.context.new_call_through_ptr(None, func_ptr, &args)); result.to_rvalue() } @@ -1514,11 +1421,11 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { self.vector_reduce(src, |a, b, context| context.new_binary_op(None, op, a.get_type(), a, b)) } - pub fn vector_reduce_fadd_fast(&mut self, acc: RValue<'gcc>, src: RValue<'gcc>) -> RValue<'gcc> { + pub fn vector_reduce_fadd_fast(&mut self, _acc: RValue<'gcc>, _src: RValue<'gcc>) -> RValue<'gcc> { unimplemented!(); } - pub fn vector_reduce_fmul_fast(&mut self, acc: RValue<'gcc>, src: RValue<'gcc>) -> RValue<'gcc> { + pub fn vector_reduce_fmul_fast(&mut self, _acc: RValue<'gcc>, _src: RValue<'gcc>) -> RValue<'gcc> { unimplemented!(); } @@ -1553,6 +1460,10 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let ones = vec![self.context.new_rvalue_one(element_type); num_units]; let ones = self.context.new_rvalue_from_vector(None, cond_type, &ones); let inverted_masks = masks + ones; + // NOTE: sometimes, the type of else_val can be different than the type of then_val in + // libgccjit (vector of int vs vector of int32_t), but they should be the same for the AND + // operation to work. + let else_val = self.context.new_bitcast(None, else_val, then_val.get_type()); let else_vals = inverted_masks & else_val; then_vals | else_vals diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 5c8367360838..1175ea005472 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -1,6 +1,169 @@ -use gccjit::Function; +use std::borrow::Cow; -use crate::context::CodegenCx; +use gccjit::{Function, FunctionPtrType, RValue, ToRValue}; + +use crate::{context::CodegenCx, builder::Builder}; + +pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc, 'tcx>, gcc_func: FunctionPtrType<'gcc>, mut args: Cow<'b, [RValue<'gcc>]>, func_name: &str) -> Cow<'b, [RValue<'gcc>]> { + // Some LLVM intrinsics do not map 1-to-1 to GCC intrinsics, so we add the missing + // arguments here. + if gcc_func.get_param_count() != args.len() { + match &*func_name { + "__builtin_ia32_pmuldq512_mask" | "__builtin_ia32_pmuludq512_mask" + // FIXME(antoyo): the following intrinsics has 4 (or 5) arguments according to the doc, but is defined with 2 (or 3) arguments in library/stdarch/crates/core_arch/src/x86/avx512f.rs. + | "__builtin_ia32_pmaxsd512_mask" | "__builtin_ia32_pmaxsq512_mask" | "__builtin_ia32_pmaxsq256_mask" + | "__builtin_ia32_pmaxsq128_mask" | "__builtin_ia32_maxps512_mask" | "__builtin_ia32_maxpd512_mask" + | "__builtin_ia32_pmaxud512_mask" | "__builtin_ia32_pmaxuq512_mask" | "__builtin_ia32_pmaxuq256_mask" + | "__builtin_ia32_pmaxuq128_mask" + | "__builtin_ia32_pminsd512_mask" | "__builtin_ia32_pminsq512_mask" | "__builtin_ia32_pminsq256_mask" + | "__builtin_ia32_pminsq128_mask" | "__builtin_ia32_minps512_mask" | "__builtin_ia32_minpd512_mask" + | "__builtin_ia32_pminud512_mask" | "__builtin_ia32_pminuq512_mask" | "__builtin_ia32_pminuq256_mask" + | "__builtin_ia32_pminuq128_mask" | "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" + => { + // TODO: refactor by separating those intrinsics outside of this branch. + let add_before_last_arg = + match &*func_name { + "__builtin_ia32_maxps512_mask" | "__builtin_ia32_maxpd512_mask" + | "__builtin_ia32_minps512_mask" | "__builtin_ia32_minpd512_mask" + | "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => true, + _ => false, + }; + let new_first_arg_is_zero = + match &*func_name { + "__builtin_ia32_pmaxuq256_mask" | "__builtin_ia32_pmaxuq128_mask" + | "__builtin_ia32_pminuq256_mask" | "__builtin_ia32_pminuq128_mask" => true, + _ => false + }; + let arg3_index = + match &*func_name { + "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => 1, + _ => 2, + }; + let mut new_args = args.to_vec(); + let arg3_type = gcc_func.get_param_type(arg3_index); + let first_arg = + if new_first_arg_is_zero { + let vector_type = arg3_type.dyncast_vector().expect("vector type"); + let zero = builder.context.new_rvalue_zero(vector_type.get_element_type()); + let num_units = vector_type.get_num_units(); + builder.context.new_rvalue_from_vector(None, arg3_type, &vec![zero; num_units]) + } + else { + builder.current_func().new_local(None, arg3_type, "undefined_for_intrinsic").to_rvalue() + }; + if add_before_last_arg { + new_args.insert(new_args.len() - 1, first_arg); + } + else { + new_args.push(first_arg); + } + let arg4_index = + match &*func_name { + "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => 2, + _ => 3, + }; + let arg4_type = gcc_func.get_param_type(arg4_index); + let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); + if add_before_last_arg { + new_args.insert(new_args.len() - 1, minus_one); + } + else { + new_args.push(minus_one); + } + args = new_args.into(); + }, + "__builtin_ia32_pternlogd512_mask" | "__builtin_ia32_pternlogd256_mask" + | "__builtin_ia32_pternlogd128_mask" | "__builtin_ia32_pternlogq512_mask" + | "__builtin_ia32_pternlogq256_mask" | "__builtin_ia32_pternlogq128_mask" => { + let mut new_args = args.to_vec(); + let arg5_type = gcc_func.get_param_type(4); + let minus_one = builder.context.new_rvalue_from_int(arg5_type, -1); + new_args.push(minus_one); + args = new_args.into(); + }, + "__builtin_ia32_vfmaddps512_mask" | "__builtin_ia32_vfmaddpd512_mask" => { + let mut new_args = args.to_vec(); + + let mut last_arg = None; + if args.len() == 4 { + last_arg = new_args.pop(); + } + + let arg4_type = gcc_func.get_param_type(3); + let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); + new_args.push(minus_one); + + if args.len() == 3 { + // Both llvm.fma.v16f32 and llvm.x86.avx512.vfmadd.ps.512 maps to + // the same GCC intrinsic, but the former has 3 parameters and the + // latter has 4 so it doesn't require this additional argument. + let arg5_type = gcc_func.get_param_type(4); + new_args.push(builder.context.new_rvalue_from_int(arg5_type, 4)); + } + + if let Some(last_arg) = last_arg { + new_args.push(last_arg); + } + + args = new_args.into(); + }, + "__builtin_ia32_subps512_mask" | "__builtin_ia32_subpd512_mask" + | "__builtin_ia32_mulps512_mask" | "__builtin_ia32_mulpd512_mask" + | "__builtin_ia32_divps512_mask" | "__builtin_ia32_divpd512_mask" + | "__builtin_ia32_vfmaddsubps512_mask" | "__builtin_ia32_vfmaddsubpd512_mask" => { + let mut new_args = args.to_vec(); + let last_arg = new_args.pop().expect("last arg"); + let arg4_type = gcc_func.get_param_type(3); + let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); + new_args.push(minus_one); + new_args.push(last_arg); + args = new_args.into(); + }, + "__builtin_ia32_addps512_mask" | "__builtin_ia32_addpd512_mask" => { + let mut new_args = args.to_vec(); + let last_arg = new_args.pop().expect("last arg"); + let arg3_type = gcc_func.get_param_type(2); + let undefined = builder.current_func().new_local(None, arg3_type, "undefined_for_intrinsic").to_rvalue(); + new_args.push(undefined); + let arg4_type = gcc_func.get_param_type(3); + let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); + new_args.push(minus_one); + new_args.push(last_arg); + args = new_args.into(); + }, + _ => (), + } + } + + args +} + +pub fn ignore_arg_cast(func_name: &str, index: usize, args_len: usize) -> bool { + // NOTE: these intrinsics have missing parameters before the last one, so ignore the + // last argument type check. + // FIXME(antoyo): find a way to refactor in order to avoid this hack. + match func_name { + "__builtin_ia32_maxps512_mask" | "__builtin_ia32_maxpd512_mask" + | "__builtin_ia32_minps512_mask" | "__builtin_ia32_minpd512_mask" | "__builtin_ia32_sqrtps512_mask" + | "__builtin_ia32_sqrtpd512_mask" | "__builtin_ia32_addps512_mask" | "__builtin_ia32_addpd512_mask" + | "__builtin_ia32_subps512_mask" | "__builtin_ia32_subpd512_mask" + | "__builtin_ia32_mulps512_mask" | "__builtin_ia32_mulpd512_mask" + | "__builtin_ia32_divps512_mask" | "__builtin_ia32_divpd512_mask" + | "__builtin_ia32_vfmaddsubps512_mask" | "__builtin_ia32_vfmaddsubpd512_mask" => { + if index == args_len - 1 { + return true; + } + }, + "__builtin_ia32_vfmaddps512_mask" => { + if args_len == 4 && index == args_len - 1 { + return true; + } + }, + _ => (), + } + + false +} #[cfg(not(feature="master"))] pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function<'gcc> { @@ -37,29 +200,23 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.avx512.mask.pminu.q.128" => "__builtin_ia32_pminuq128_mask", "llvm.fma.v16f32" => "__builtin_ia32_vfmaddps512_mask", "llvm.fma.v8f64" => "__builtin_ia32_vfmaddpd512_mask", - "llvm.x86.avx512.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddps512_mask", - "llvm.x86.avx512.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddpd512_mask", - "llvm.x86.avx512.rcp14.ps.256" => "__builtin_ia32_rcp14ps256_mask", - "llvm.x86.avx512.rcp14.ps.128" => "__builtin_ia32_rcp14ps128_mask", - "llvm.x86.avx512.rcp14.pd.256" => "__builtin_ia32_rcp14pd256_mask", - "llvm.x86.avx512.rcp14.pd.128" => "__builtin_ia32_rcp14pd128_mask", - "llvm.x86.avx512.rsqrt14.ps.256" => "__builtin_ia32_rsqrt14ps256_mask", - "llvm.x86.avx512.rsqrt14.ps.128" => "__builtin_ia32_rsqrt14ps128_mask", - "llvm.x86.avx512.rsqrt14.pd.256" => "__builtin_ia32_rsqrt14pd256_mask", - "llvm.x86.avx512.rsqrt14.pd.128" => "__builtin_ia32_rsqrt14pd128_mask", - "llvm.x86.avx512.mask.getexp.ps.512" => "__builtin_ia32_getexpps512_mask", - "llvm.x86.avx512.mask.getexp.ps.256" => "__builtin_ia32_getexpps256_mask", - "llvm.x86.avx512.mask.getexp.ps.128" => "__builtin_ia32_getexpps128_mask", - "llvm.x86.avx512.mask.getexp.pd.512" => "__builtin_ia32_getexppd512_mask", - "llvm.x86.avx512.mask.getexp.pd.256" => "__builtin_ia32_getexppd256_mask", - "llvm.x86.avx512.mask.getexp.pd.128" => "__builtin_ia32_getexppd128_mask", - "llvm.x86.avx512.mask.rndscale.ps.256" => "__builtin_ia32_rndscaleps_256_mask", - "llvm.x86.avx512.mask.rndscale.ps.128" => "__builtin_ia32_rndscaleps_128_mask", - "llvm.x86.avx512.mask.rndscale.pd.256" => "__builtin_ia32_rndscalepd_256_mask", - "llvm.x86.avx512.mask.rndscale.pd.128" => "__builtin_ia32_rndscalepd_128_mask", - "llvm.x86.avx512.mask.scalef.ps.512" => "__builtin_ia32_scalefps512_mask", - "llvm.x86.avx512.mask.scalef.ps.256" => "__builtin_ia32_scalefps256_mask", - "llvm.x86.avx512.mask.scalef.ps.128" => "__builtin_ia32_scalefps128_mask", + "llvm.x86.avx512.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask", + "llvm.x86.avx512.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask", + "llvm.x86.avx512.pternlog.d.512" => "__builtin_ia32_pternlogd512_mask", + "llvm.x86.avx512.pternlog.d.256" => "__builtin_ia32_pternlogd256_mask", + "llvm.x86.avx512.pternlog.d.128" => "__builtin_ia32_pternlogd128_mask", + "llvm.x86.avx512.pternlog.q.512" => "__builtin_ia32_pternlogq512_mask", + "llvm.x86.avx512.pternlog.q.256" => "__builtin_ia32_pternlogq256_mask", + "llvm.x86.avx512.pternlog.q.128" => "__builtin_ia32_pternlogq128_mask", + "llvm.x86.avx512.add.ps.512" => "__builtin_ia32_addps512_mask", + "llvm.x86.avx512.add.pd.512" => "__builtin_ia32_addpd512_mask", + "llvm.x86.avx512.sub.ps.512" => "__builtin_ia32_subps512_mask", + "llvm.x86.avx512.sub.pd.512" => "__builtin_ia32_subpd512_mask", + "llvm.x86.avx512.mul.ps.512" => "__builtin_ia32_mulps512_mask", + "llvm.x86.avx512.mul.pd.512" => "__builtin_ia32_mulpd512_mask", + "llvm.x86.avx512.div.ps.512" => "__builtin_ia32_divps512_mask", + "llvm.x86.avx512.div.pd.512" => "__builtin_ia32_divpd512_mask", + "llvm.x86.avx512.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask", // The above doc points to unknown builtins for the following, so override them: "llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gathersiv4si", From 41807a30943b2459c8a8e2accfbbead8959490d4 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Tue, 3 May 2022 22:46:40 -0400 Subject: [PATCH 088/356] Support more SIMD intrinsics --- src/intrinsic/llvm.rs | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 1175ea005472..1b089f08f764 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -107,24 +107,24 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc args = new_args.into(); }, - "__builtin_ia32_subps512_mask" | "__builtin_ia32_subpd512_mask" + "__builtin_ia32_addps512_mask" | "__builtin_ia32_addpd512_mask" + | "__builtin_ia32_subps512_mask" | "__builtin_ia32_subpd512_mask" | "__builtin_ia32_mulps512_mask" | "__builtin_ia32_mulpd512_mask" - | "__builtin_ia32_divps512_mask" | "__builtin_ia32_divpd512_mask" - | "__builtin_ia32_vfmaddsubps512_mask" | "__builtin_ia32_vfmaddsubpd512_mask" => { + | "__builtin_ia32_divps512_mask" | "__builtin_ia32_divpd512_mask" => { let mut new_args = args.to_vec(); let last_arg = new_args.pop().expect("last arg"); + let arg3_type = gcc_func.get_param_type(2); + let undefined = builder.current_func().new_local(None, arg3_type, "undefined_for_intrinsic").to_rvalue(); + new_args.push(undefined); let arg4_type = gcc_func.get_param_type(3); let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); new_args.push(minus_one); new_args.push(last_arg); args = new_args.into(); }, - "__builtin_ia32_addps512_mask" | "__builtin_ia32_addpd512_mask" => { + "__builtin_ia32_vfmaddsubps512_mask" | "__builtin_ia32_vfmaddsubpd512_mask" => { let mut new_args = args.to_vec(); let last_arg = new_args.pop().expect("last arg"); - let arg3_type = gcc_func.get_param_type(2); - let undefined = builder.current_func().new_local(None, arg3_type, "undefined_for_intrinsic").to_rvalue(); - new_args.push(undefined); let arg4_type = gcc_func.get_param_type(3); let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); new_args.push(minus_one); @@ -154,7 +154,10 @@ pub fn ignore_arg_cast(func_name: &str, index: usize, args_len: usize) -> bool { return true; } }, - "__builtin_ia32_vfmaddps512_mask" => { + "__builtin_ia32_vfmaddps512_mask" | "__builtin_ia32_vfmaddpd512_mask" => { + // Since there are two LLVM intrinsics that map to each of these GCC builtins and only + // one of them has a missing parameter before the last one, we check the number of + // arguments to distinguish those cases. if args_len == 4 && index == args_len - 1 { return true; } @@ -217,6 +220,7 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.avx512.div.ps.512" => "__builtin_ia32_divps512_mask", "llvm.x86.avx512.div.pd.512" => "__builtin_ia32_divpd512_mask", "llvm.x86.avx512.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask", + "llvm.x86.avx512.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask", // The above doc points to unknown builtins for the following, so override them: "llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gathersiv4si", From d4ab681ebd3b22a071a02aad4005805dd13a41f2 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Wed, 4 May 2022 21:17:58 -0400 Subject: [PATCH 089/356] Add comments --- src/intrinsic/simd.rs | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index 6e14f6d021e1..6c2834fccf30 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -220,6 +220,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, // NOTE: we cannot cast to an array and assign to its element here because the value might // not be an l-value. So, call a builtin to set the element. // TODO(antoyo): perhaps we could create a new vector or maybe there's a GIMPLE instruction for that? + // TODO(antoyo): don't use target specific builtins here. let func_name = match in_len { 2 => { @@ -396,6 +397,10 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, }); } (Style::Int(_), Style::Float) => { + // TODO: add support for internal functions in libgccjit to get access to IFN_VEC_CONVERT which is + // doing like __builtin_convertvector? + // Or maybe provide convert_vector as an API since it might not easy to get the + // types of internal functions. unimplemented!(); } (Style::Float, Style::Int(_)) => { From 603d342e00719fdba6691d6bed65e66ae817d46e Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Wed, 4 May 2022 21:26:25 -0400 Subject: [PATCH 090/356] Feature-gate for libgccjit 12 --- src/builder.rs | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/builder.rs b/src/builder.rs index df5c29f625eb..d4fd6a6877fe 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1391,6 +1391,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { unimplemented!(); } + #[cfg(feature="master")] pub fn vector_reduce(&mut self, src: RValue<'gcc>, op: F) -> RValue<'gcc> where F: Fn(RValue<'gcc>, RValue<'gcc>, &'gcc Context<'gcc>) -> RValue<'gcc> { @@ -1417,6 +1418,13 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { .to_rvalue() } + #[cfg(not(feature="master"))] + pub fn vector_reduce(&mut self, src: RValue<'gcc>, op: F) -> RValue<'gcc> + where F: Fn(RValue<'gcc>, RValue<'gcc>, &'gcc Context<'gcc>) -> RValue<'gcc> + { + unimplemented!(); + } + pub fn vector_reduce_op(&mut self, src: RValue<'gcc>, op: BinaryOp) -> RValue<'gcc> { self.vector_reduce(src, |a, b, context| context.new_binary_op(None, op, a.get_type(), a, b)) } From e7df0a4b549e5d3b4aec0cc79c4262c5a2dfef13 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Wed, 4 May 2022 21:53:22 -0400 Subject: [PATCH 091/356] Simplify get() after contains() --- src/declare.rs | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/declare.rs b/src/declare.rs index 8b2146c5aa84..a619e2f77125 100644 --- a/src/declare.rs +++ b/src/declare.rs @@ -11,8 +11,7 @@ use crate::intrinsic::llvm; impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { pub fn get_or_insert_global(&self, name: &str, ty: Type<'gcc>, is_tls: bool, link_section: Option) -> LValue<'gcc> { if self.globals.borrow().contains_key(name) { - // TODO: use [] instead of .get().expect()? - let typ = self.globals.borrow().get(name).expect("global").get_type(); + let typ = self.globals.borrow()[name].get_type(); let global = self.context.new_global(None, GlobalKind::Imported, typ, name); if is_tls { global.set_tls_model(self.tls_model); @@ -110,7 +109,7 @@ fn declare_raw_fn<'gcc>(cx: &CodegenCx<'gcc, '_>, name: &str, _callconv: () /*ll } let func = if cx.functions.borrow().contains_key(name) { - *cx.functions.borrow().get(name).expect("function") + cx.functions.borrow()[name] } else { let params: Vec<_> = param_types.into_iter().enumerate() From 4a9744059f8617756c4ee981e033ad8b6f6e05d3 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Wed, 4 May 2022 22:20:38 -0400 Subject: [PATCH 092/356] Feature gate call to get_size() for libgccjit 12 --- src/builder.rs | 7 ++++++- src/intrinsic/archs.rs | 5 +---- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index d4fd6a6877fe..8fa78c7e189b 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1326,7 +1326,12 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { element_type } else { - self.cx.type_ix(element_type.get_size() as u64 * 8) + #[cfg(feature="master")] + { + self.cx.type_ix(element_type.get_size() as u64 * 8) + } + #[cfg(not(feature="master"))] + self.int_type }; for i in 0..mask_num_units { let field = struct_type.get_field(i as i32); diff --git a/src/intrinsic/archs.rs b/src/intrinsic/archs.rs index fbcfc8be8591..bfeb30f2913d 100644 --- a/src/intrinsic/archs.rs +++ b/src/intrinsic/archs.rs @@ -4275,8 +4275,5 @@ match name { "llvm.xcore.getid" => "__builtin_getid", "llvm.xcore.getps" => "__builtin_getps", "llvm.xcore.setps" => "__builtin_setps", - _ => { - println!("***** unsupported LLVM intrinsic {}", name); - "" - }, + _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), } From be960e1747cbebdf8272a79f2e6a7b6891acb0a6 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Sun, 15 May 2022 14:07:19 +0200 Subject: [PATCH 093/356] Update llvmint --- src/intrinsic/archs.rs | 1443 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 1443 insertions(+) diff --git a/src/intrinsic/archs.rs b/src/intrinsic/archs.rs index bfeb30f2913d..fb6c38fa0726 100644 --- a/src/intrinsic/archs.rs +++ b/src/intrinsic/archs.rs @@ -126,6 +126,7 @@ match name { "llvm.amdgcn.sad.hi.u8" => "__builtin_amdgcn_sad_hi_u8", "llvm.amdgcn.sad.u16" => "__builtin_amdgcn_sad_u16", "llvm.amdgcn.sad.u8" => "__builtin_amdgcn_sad_u8", + "llvm.amdgcn.sched.barrier" => "__builtin_amdgcn_sched_barrier", "llvm.amdgcn.sdot2" => "__builtin_amdgcn_sdot2", "llvm.amdgcn.sdot4" => "__builtin_amdgcn_sdot4", "llvm.amdgcn.sdot8" => "__builtin_amdgcn_sdot8", @@ -891,6 +892,8 @@ match name { "llvm.hexagon.M5.vrmacbuu" => "__builtin_HEXAGON_M5_vrmacbuu", "llvm.hexagon.M5.vrmpybsu" => "__builtin_HEXAGON_M5_vrmpybsu", "llvm.hexagon.M5.vrmpybuu" => "__builtin_HEXAGON_M5_vrmpybuu", + "llvm.hexagon.M6.vabsdiffb" => "__builtin_HEXAGON_M6_vabsdiffb", + "llvm.hexagon.M6.vabsdiffub" => "__builtin_HEXAGON_M6_vabsdiffub", "llvm.hexagon.S2.addasl.rrri" => "__builtin_HEXAGON_S2_addasl_rrri", "llvm.hexagon.S2.asl.i.p" => "__builtin_HEXAGON_S2_asl_i_p", "llvm.hexagon.S2.asl.i.p.acc" => "__builtin_HEXAGON_S2_asl_i_p_acc", @@ -955,6 +958,7 @@ match name { "llvm.hexagon.S2.asr.r.vw" => "__builtin_HEXAGON_S2_asr_r_vw", "llvm.hexagon.S2.brev" => "__builtin_HEXAGON_S2_brev", "llvm.hexagon.S2.brevp" => "__builtin_HEXAGON_S2_brevp", + "llvm.hexagon.S2.cabacencbin" => "__builtin_HEXAGON_S2_cabacencbin", "llvm.hexagon.S2.cl0" => "__builtin_HEXAGON_S2_cl0", "llvm.hexagon.S2.cl0p" => "__builtin_HEXAGON_S2_cl0p", "llvm.hexagon.S2.cl1" => "__builtin_HEXAGON_S2_cl1", @@ -1100,8 +1104,528 @@ match name { "llvm.hexagon.S5.asrhub.sat" => "__builtin_HEXAGON_S5_asrhub_sat", "llvm.hexagon.S5.popcountp" => "__builtin_HEXAGON_S5_popcountp", "llvm.hexagon.S5.vasrhrnd.goodsyntax" => "__builtin_HEXAGON_S5_vasrhrnd_goodsyntax", + "llvm.hexagon.S6.rol.i.p" => "__builtin_HEXAGON_S6_rol_i_p", + "llvm.hexagon.S6.rol.i.p.acc" => "__builtin_HEXAGON_S6_rol_i_p_acc", + "llvm.hexagon.S6.rol.i.p.and" => "__builtin_HEXAGON_S6_rol_i_p_and", + "llvm.hexagon.S6.rol.i.p.nac" => "__builtin_HEXAGON_S6_rol_i_p_nac", + "llvm.hexagon.S6.rol.i.p.or" => "__builtin_HEXAGON_S6_rol_i_p_or", + "llvm.hexagon.S6.rol.i.p.xacc" => "__builtin_HEXAGON_S6_rol_i_p_xacc", + "llvm.hexagon.S6.rol.i.r" => "__builtin_HEXAGON_S6_rol_i_r", + "llvm.hexagon.S6.rol.i.r.acc" => "__builtin_HEXAGON_S6_rol_i_r_acc", + "llvm.hexagon.S6.rol.i.r.and" => "__builtin_HEXAGON_S6_rol_i_r_and", + "llvm.hexagon.S6.rol.i.r.nac" => "__builtin_HEXAGON_S6_rol_i_r_nac", + "llvm.hexagon.S6.rol.i.r.or" => "__builtin_HEXAGON_S6_rol_i_r_or", + "llvm.hexagon.S6.rol.i.r.xacc" => "__builtin_HEXAGON_S6_rol_i_r_xacc", + "llvm.hexagon.S6.vsplatrbp" => "__builtin_HEXAGON_S6_vsplatrbp", + "llvm.hexagon.S6.vtrunehb.ppp" => "__builtin_HEXAGON_S6_vtrunehb_ppp", + "llvm.hexagon.S6.vtrunohb.ppp" => "__builtin_HEXAGON_S6_vtrunohb_ppp", "llvm.hexagon.SI.to.SXTHI.asrh" => "__builtin_SI_to_SXTHI_asrh", + "llvm.hexagon.V6.extractw" => "__builtin_HEXAGON_V6_extractw", + "llvm.hexagon.V6.extractw.128B" => "__builtin_HEXAGON_V6_extractw_128B", + "llvm.hexagon.V6.hi" => "__builtin_HEXAGON_V6_hi", + "llvm.hexagon.V6.hi.128B" => "__builtin_HEXAGON_V6_hi_128B", + "llvm.hexagon.V6.lo" => "__builtin_HEXAGON_V6_lo", + "llvm.hexagon.V6.lo.128B" => "__builtin_HEXAGON_V6_lo_128B", + "llvm.hexagon.V6.lvsplatw" => "__builtin_HEXAGON_V6_lvsplatw", + "llvm.hexagon.V6.lvsplatw.128B" => "__builtin_HEXAGON_V6_lvsplatw_128B", + "llvm.hexagon.V6.vabsdiffh" => "__builtin_HEXAGON_V6_vabsdiffh", + "llvm.hexagon.V6.vabsdiffh.128B" => "__builtin_HEXAGON_V6_vabsdiffh_128B", + "llvm.hexagon.V6.vabsdiffub" => "__builtin_HEXAGON_V6_vabsdiffub", + "llvm.hexagon.V6.vabsdiffub.128B" => "__builtin_HEXAGON_V6_vabsdiffub_128B", + "llvm.hexagon.V6.vabsdiffuh" => "__builtin_HEXAGON_V6_vabsdiffuh", + "llvm.hexagon.V6.vabsdiffuh.128B" => "__builtin_HEXAGON_V6_vabsdiffuh_128B", + "llvm.hexagon.V6.vabsdiffw" => "__builtin_HEXAGON_V6_vabsdiffw", + "llvm.hexagon.V6.vabsdiffw.128B" => "__builtin_HEXAGON_V6_vabsdiffw_128B", + "llvm.hexagon.V6.vabsh" => "__builtin_HEXAGON_V6_vabsh", + "llvm.hexagon.V6.vabsh.128B" => "__builtin_HEXAGON_V6_vabsh_128B", + "llvm.hexagon.V6.vabsh.sat" => "__builtin_HEXAGON_V6_vabsh_sat", + "llvm.hexagon.V6.vabsh.sat.128B" => "__builtin_HEXAGON_V6_vabsh_sat_128B", + "llvm.hexagon.V6.vabsw" => "__builtin_HEXAGON_V6_vabsw", + "llvm.hexagon.V6.vabsw.128B" => "__builtin_HEXAGON_V6_vabsw_128B", + "llvm.hexagon.V6.vabsw.sat" => "__builtin_HEXAGON_V6_vabsw_sat", + "llvm.hexagon.V6.vabsw.sat.128B" => "__builtin_HEXAGON_V6_vabsw_sat_128B", + "llvm.hexagon.V6.vaddb" => "__builtin_HEXAGON_V6_vaddb", + "llvm.hexagon.V6.vaddb.128B" => "__builtin_HEXAGON_V6_vaddb_128B", + "llvm.hexagon.V6.vaddb.dv" => "__builtin_HEXAGON_V6_vaddb_dv", + "llvm.hexagon.V6.vaddb.dv.128B" => "__builtin_HEXAGON_V6_vaddb_dv_128B", + "llvm.hexagon.V6.vaddh" => "__builtin_HEXAGON_V6_vaddh", + "llvm.hexagon.V6.vaddh.128B" => "__builtin_HEXAGON_V6_vaddh_128B", + "llvm.hexagon.V6.vaddh.dv" => "__builtin_HEXAGON_V6_vaddh_dv", + "llvm.hexagon.V6.vaddh.dv.128B" => "__builtin_HEXAGON_V6_vaddh_dv_128B", + "llvm.hexagon.V6.vaddhsat" => "__builtin_HEXAGON_V6_vaddhsat", + "llvm.hexagon.V6.vaddhsat.128B" => "__builtin_HEXAGON_V6_vaddhsat_128B", + "llvm.hexagon.V6.vaddhsat.dv" => "__builtin_HEXAGON_V6_vaddhsat_dv", + "llvm.hexagon.V6.vaddhsat.dv.128B" => "__builtin_HEXAGON_V6_vaddhsat_dv_128B", + "llvm.hexagon.V6.vaddhw" => "__builtin_HEXAGON_V6_vaddhw", + "llvm.hexagon.V6.vaddhw.128B" => "__builtin_HEXAGON_V6_vaddhw_128B", + "llvm.hexagon.V6.vaddubh" => "__builtin_HEXAGON_V6_vaddubh", + "llvm.hexagon.V6.vaddubh.128B" => "__builtin_HEXAGON_V6_vaddubh_128B", + "llvm.hexagon.V6.vaddubsat" => "__builtin_HEXAGON_V6_vaddubsat", + "llvm.hexagon.V6.vaddubsat.128B" => "__builtin_HEXAGON_V6_vaddubsat_128B", + "llvm.hexagon.V6.vaddubsat.dv" => "__builtin_HEXAGON_V6_vaddubsat_dv", + "llvm.hexagon.V6.vaddubsat.dv.128B" => "__builtin_HEXAGON_V6_vaddubsat_dv_128B", + "llvm.hexagon.V6.vadduhsat" => "__builtin_HEXAGON_V6_vadduhsat", + "llvm.hexagon.V6.vadduhsat.128B" => "__builtin_HEXAGON_V6_vadduhsat_128B", + "llvm.hexagon.V6.vadduhsat.dv" => "__builtin_HEXAGON_V6_vadduhsat_dv", + "llvm.hexagon.V6.vadduhsat.dv.128B" => "__builtin_HEXAGON_V6_vadduhsat_dv_128B", + "llvm.hexagon.V6.vadduhw" => "__builtin_HEXAGON_V6_vadduhw", + "llvm.hexagon.V6.vadduhw.128B" => "__builtin_HEXAGON_V6_vadduhw_128B", + "llvm.hexagon.V6.vaddw" => "__builtin_HEXAGON_V6_vaddw", + "llvm.hexagon.V6.vaddw.128B" => "__builtin_HEXAGON_V6_vaddw_128B", + "llvm.hexagon.V6.vaddw.dv" => "__builtin_HEXAGON_V6_vaddw_dv", + "llvm.hexagon.V6.vaddw.dv.128B" => "__builtin_HEXAGON_V6_vaddw_dv_128B", + "llvm.hexagon.V6.vaddwsat" => "__builtin_HEXAGON_V6_vaddwsat", + "llvm.hexagon.V6.vaddwsat.128B" => "__builtin_HEXAGON_V6_vaddwsat_128B", + "llvm.hexagon.V6.vaddwsat.dv" => "__builtin_HEXAGON_V6_vaddwsat_dv", + "llvm.hexagon.V6.vaddwsat.dv.128B" => "__builtin_HEXAGON_V6_vaddwsat_dv_128B", + "llvm.hexagon.V6.valignb" => "__builtin_HEXAGON_V6_valignb", + "llvm.hexagon.V6.valignb.128B" => "__builtin_HEXAGON_V6_valignb_128B", + "llvm.hexagon.V6.valignbi" => "__builtin_HEXAGON_V6_valignbi", + "llvm.hexagon.V6.valignbi.128B" => "__builtin_HEXAGON_V6_valignbi_128B", + "llvm.hexagon.V6.vand" => "__builtin_HEXAGON_V6_vand", + "llvm.hexagon.V6.vand.128B" => "__builtin_HEXAGON_V6_vand_128B", + "llvm.hexagon.V6.vaslh" => "__builtin_HEXAGON_V6_vaslh", + "llvm.hexagon.V6.vaslh.128B" => "__builtin_HEXAGON_V6_vaslh_128B", + "llvm.hexagon.V6.vaslhv" => "__builtin_HEXAGON_V6_vaslhv", + "llvm.hexagon.V6.vaslhv.128B" => "__builtin_HEXAGON_V6_vaslhv_128B", + "llvm.hexagon.V6.vaslw" => "__builtin_HEXAGON_V6_vaslw", + "llvm.hexagon.V6.vaslw.128B" => "__builtin_HEXAGON_V6_vaslw_128B", + "llvm.hexagon.V6.vaslw.acc" => "__builtin_HEXAGON_V6_vaslw_acc", + "llvm.hexagon.V6.vaslw.acc.128B" => "__builtin_HEXAGON_V6_vaslw_acc_128B", + "llvm.hexagon.V6.vaslwv" => "__builtin_HEXAGON_V6_vaslwv", + "llvm.hexagon.V6.vaslwv.128B" => "__builtin_HEXAGON_V6_vaslwv_128B", + "llvm.hexagon.V6.vasrh" => "__builtin_HEXAGON_V6_vasrh", + "llvm.hexagon.V6.vasrh.128B" => "__builtin_HEXAGON_V6_vasrh_128B", + "llvm.hexagon.V6.vasrhbrndsat" => "__builtin_HEXAGON_V6_vasrhbrndsat", + "llvm.hexagon.V6.vasrhbrndsat.128B" => "__builtin_HEXAGON_V6_vasrhbrndsat_128B", + "llvm.hexagon.V6.vasrhubrndsat" => "__builtin_HEXAGON_V6_vasrhubrndsat", + "llvm.hexagon.V6.vasrhubrndsat.128B" => "__builtin_HEXAGON_V6_vasrhubrndsat_128B", + "llvm.hexagon.V6.vasrhubsat" => "__builtin_HEXAGON_V6_vasrhubsat", + "llvm.hexagon.V6.vasrhubsat.128B" => "__builtin_HEXAGON_V6_vasrhubsat_128B", + "llvm.hexagon.V6.vasrhv" => "__builtin_HEXAGON_V6_vasrhv", + "llvm.hexagon.V6.vasrhv.128B" => "__builtin_HEXAGON_V6_vasrhv_128B", + "llvm.hexagon.V6.vasrw" => "__builtin_HEXAGON_V6_vasrw", + "llvm.hexagon.V6.vasrw.128B" => "__builtin_HEXAGON_V6_vasrw_128B", + "llvm.hexagon.V6.vasrw.acc" => "__builtin_HEXAGON_V6_vasrw_acc", + "llvm.hexagon.V6.vasrw.acc.128B" => "__builtin_HEXAGON_V6_vasrw_acc_128B", + "llvm.hexagon.V6.vasrwh" => "__builtin_HEXAGON_V6_vasrwh", + "llvm.hexagon.V6.vasrwh.128B" => "__builtin_HEXAGON_V6_vasrwh_128B", + "llvm.hexagon.V6.vasrwhrndsat" => "__builtin_HEXAGON_V6_vasrwhrndsat", + "llvm.hexagon.V6.vasrwhrndsat.128B" => "__builtin_HEXAGON_V6_vasrwhrndsat_128B", + "llvm.hexagon.V6.vasrwhsat" => "__builtin_HEXAGON_V6_vasrwhsat", + "llvm.hexagon.V6.vasrwhsat.128B" => "__builtin_HEXAGON_V6_vasrwhsat_128B", + "llvm.hexagon.V6.vasrwuhsat" => "__builtin_HEXAGON_V6_vasrwuhsat", + "llvm.hexagon.V6.vasrwuhsat.128B" => "__builtin_HEXAGON_V6_vasrwuhsat_128B", + "llvm.hexagon.V6.vasrwv" => "__builtin_HEXAGON_V6_vasrwv", + "llvm.hexagon.V6.vasrwv.128B" => "__builtin_HEXAGON_V6_vasrwv_128B", + "llvm.hexagon.V6.vassign" => "__builtin_HEXAGON_V6_vassign", + "llvm.hexagon.V6.vassign.128B" => "__builtin_HEXAGON_V6_vassign_128B", + "llvm.hexagon.V6.vassignp" => "__builtin_HEXAGON_V6_vassignp", + "llvm.hexagon.V6.vassignp.128B" => "__builtin_HEXAGON_V6_vassignp_128B", + "llvm.hexagon.V6.vavgh" => "__builtin_HEXAGON_V6_vavgh", + "llvm.hexagon.V6.vavgh.128B" => "__builtin_HEXAGON_V6_vavgh_128B", + "llvm.hexagon.V6.vavghrnd" => "__builtin_HEXAGON_V6_vavghrnd", + "llvm.hexagon.V6.vavghrnd.128B" => "__builtin_HEXAGON_V6_vavghrnd_128B", + "llvm.hexagon.V6.vavgub" => "__builtin_HEXAGON_V6_vavgub", + "llvm.hexagon.V6.vavgub.128B" => "__builtin_HEXAGON_V6_vavgub_128B", + "llvm.hexagon.V6.vavgubrnd" => "__builtin_HEXAGON_V6_vavgubrnd", + "llvm.hexagon.V6.vavgubrnd.128B" => "__builtin_HEXAGON_V6_vavgubrnd_128B", + "llvm.hexagon.V6.vavguh" => "__builtin_HEXAGON_V6_vavguh", + "llvm.hexagon.V6.vavguh.128B" => "__builtin_HEXAGON_V6_vavguh_128B", + "llvm.hexagon.V6.vavguhrnd" => "__builtin_HEXAGON_V6_vavguhrnd", + "llvm.hexagon.V6.vavguhrnd.128B" => "__builtin_HEXAGON_V6_vavguhrnd_128B", + "llvm.hexagon.V6.vavgw" => "__builtin_HEXAGON_V6_vavgw", + "llvm.hexagon.V6.vavgw.128B" => "__builtin_HEXAGON_V6_vavgw_128B", + "llvm.hexagon.V6.vavgwrnd" => "__builtin_HEXAGON_V6_vavgwrnd", + "llvm.hexagon.V6.vavgwrnd.128B" => "__builtin_HEXAGON_V6_vavgwrnd_128B", + "llvm.hexagon.V6.vcl0h" => "__builtin_HEXAGON_V6_vcl0h", + "llvm.hexagon.V6.vcl0h.128B" => "__builtin_HEXAGON_V6_vcl0h_128B", + "llvm.hexagon.V6.vcl0w" => "__builtin_HEXAGON_V6_vcl0w", + "llvm.hexagon.V6.vcl0w.128B" => "__builtin_HEXAGON_V6_vcl0w_128B", + "llvm.hexagon.V6.vcombine" => "__builtin_HEXAGON_V6_vcombine", + "llvm.hexagon.V6.vcombine.128B" => "__builtin_HEXAGON_V6_vcombine_128B", + "llvm.hexagon.V6.vd0" => "__builtin_HEXAGON_V6_vd0", + "llvm.hexagon.V6.vd0.128B" => "__builtin_HEXAGON_V6_vd0_128B", + "llvm.hexagon.V6.vdealb" => "__builtin_HEXAGON_V6_vdealb", + "llvm.hexagon.V6.vdealb.128B" => "__builtin_HEXAGON_V6_vdealb_128B", + "llvm.hexagon.V6.vdealb4w" => "__builtin_HEXAGON_V6_vdealb4w", + "llvm.hexagon.V6.vdealb4w.128B" => "__builtin_HEXAGON_V6_vdealb4w_128B", + "llvm.hexagon.V6.vdealh" => "__builtin_HEXAGON_V6_vdealh", + "llvm.hexagon.V6.vdealh.128B" => "__builtin_HEXAGON_V6_vdealh_128B", + "llvm.hexagon.V6.vdealvdd" => "__builtin_HEXAGON_V6_vdealvdd", + "llvm.hexagon.V6.vdealvdd.128B" => "__builtin_HEXAGON_V6_vdealvdd_128B", + "llvm.hexagon.V6.vdelta" => "__builtin_HEXAGON_V6_vdelta", + "llvm.hexagon.V6.vdelta.128B" => "__builtin_HEXAGON_V6_vdelta_128B", + "llvm.hexagon.V6.vdmpybus" => "__builtin_HEXAGON_V6_vdmpybus", + "llvm.hexagon.V6.vdmpybus.128B" => "__builtin_HEXAGON_V6_vdmpybus_128B", + "llvm.hexagon.V6.vdmpybus.acc" => "__builtin_HEXAGON_V6_vdmpybus_acc", + "llvm.hexagon.V6.vdmpybus.acc.128B" => "__builtin_HEXAGON_V6_vdmpybus_acc_128B", + "llvm.hexagon.V6.vdmpybus.dv" => "__builtin_HEXAGON_V6_vdmpybus_dv", + "llvm.hexagon.V6.vdmpybus.dv.128B" => "__builtin_HEXAGON_V6_vdmpybus_dv_128B", + "llvm.hexagon.V6.vdmpybus.dv.acc" => "__builtin_HEXAGON_V6_vdmpybus_dv_acc", + "llvm.hexagon.V6.vdmpybus.dv.acc.128B" => "__builtin_HEXAGON_V6_vdmpybus_dv_acc_128B", + "llvm.hexagon.V6.vdmpyhb" => "__builtin_HEXAGON_V6_vdmpyhb", + "llvm.hexagon.V6.vdmpyhb.128B" => "__builtin_HEXAGON_V6_vdmpyhb_128B", + "llvm.hexagon.V6.vdmpyhb.acc" => "__builtin_HEXAGON_V6_vdmpyhb_acc", + "llvm.hexagon.V6.vdmpyhb.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhb_acc_128B", + "llvm.hexagon.V6.vdmpyhb.dv" => "__builtin_HEXAGON_V6_vdmpyhb_dv", + "llvm.hexagon.V6.vdmpyhb.dv.128B" => "__builtin_HEXAGON_V6_vdmpyhb_dv_128B", + "llvm.hexagon.V6.vdmpyhb.dv.acc" => "__builtin_HEXAGON_V6_vdmpyhb_dv_acc", + "llvm.hexagon.V6.vdmpyhb.dv.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhb_dv_acc_128B", + "llvm.hexagon.V6.vdmpyhisat" => "__builtin_HEXAGON_V6_vdmpyhisat", + "llvm.hexagon.V6.vdmpyhisat.128B" => "__builtin_HEXAGON_V6_vdmpyhisat_128B", + "llvm.hexagon.V6.vdmpyhisat.acc" => "__builtin_HEXAGON_V6_vdmpyhisat_acc", + "llvm.hexagon.V6.vdmpyhisat.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhisat_acc_128B", + "llvm.hexagon.V6.vdmpyhsat" => "__builtin_HEXAGON_V6_vdmpyhsat", + "llvm.hexagon.V6.vdmpyhsat.128B" => "__builtin_HEXAGON_V6_vdmpyhsat_128B", + "llvm.hexagon.V6.vdmpyhsat.acc" => "__builtin_HEXAGON_V6_vdmpyhsat_acc", + "llvm.hexagon.V6.vdmpyhsat.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhsat_acc_128B", + "llvm.hexagon.V6.vdmpyhsuisat" => "__builtin_HEXAGON_V6_vdmpyhsuisat", + "llvm.hexagon.V6.vdmpyhsuisat.128B" => "__builtin_HEXAGON_V6_vdmpyhsuisat_128B", + "llvm.hexagon.V6.vdmpyhsuisat.acc" => "__builtin_HEXAGON_V6_vdmpyhsuisat_acc", + "llvm.hexagon.V6.vdmpyhsuisat.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhsuisat_acc_128B", + "llvm.hexagon.V6.vdmpyhsusat" => "__builtin_HEXAGON_V6_vdmpyhsusat", + "llvm.hexagon.V6.vdmpyhsusat.128B" => "__builtin_HEXAGON_V6_vdmpyhsusat_128B", + "llvm.hexagon.V6.vdmpyhsusat.acc" => "__builtin_HEXAGON_V6_vdmpyhsusat_acc", + "llvm.hexagon.V6.vdmpyhsusat.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhsusat_acc_128B", + "llvm.hexagon.V6.vdmpyhvsat" => "__builtin_HEXAGON_V6_vdmpyhvsat", + "llvm.hexagon.V6.vdmpyhvsat.128B" => "__builtin_HEXAGON_V6_vdmpyhvsat_128B", + "llvm.hexagon.V6.vdmpyhvsat.acc" => "__builtin_HEXAGON_V6_vdmpyhvsat_acc", + "llvm.hexagon.V6.vdmpyhvsat.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhvsat_acc_128B", + "llvm.hexagon.V6.vdsaduh" => "__builtin_HEXAGON_V6_vdsaduh", + "llvm.hexagon.V6.vdsaduh.128B" => "__builtin_HEXAGON_V6_vdsaduh_128B", + "llvm.hexagon.V6.vdsaduh.acc" => "__builtin_HEXAGON_V6_vdsaduh_acc", + "llvm.hexagon.V6.vdsaduh.acc.128B" => "__builtin_HEXAGON_V6_vdsaduh_acc_128B", + "llvm.hexagon.V6.vinsertwr" => "__builtin_HEXAGON_V6_vinsertwr", + "llvm.hexagon.V6.vinsertwr.128B" => "__builtin_HEXAGON_V6_vinsertwr_128B", + "llvm.hexagon.V6.vlalignb" => "__builtin_HEXAGON_V6_vlalignb", + "llvm.hexagon.V6.vlalignb.128B" => "__builtin_HEXAGON_V6_vlalignb_128B", + "llvm.hexagon.V6.vlalignbi" => "__builtin_HEXAGON_V6_vlalignbi", + "llvm.hexagon.V6.vlalignbi.128B" => "__builtin_HEXAGON_V6_vlalignbi_128B", + "llvm.hexagon.V6.vlsrh" => "__builtin_HEXAGON_V6_vlsrh", + "llvm.hexagon.V6.vlsrh.128B" => "__builtin_HEXAGON_V6_vlsrh_128B", + "llvm.hexagon.V6.vlsrhv" => "__builtin_HEXAGON_V6_vlsrhv", + "llvm.hexagon.V6.vlsrhv.128B" => "__builtin_HEXAGON_V6_vlsrhv_128B", + "llvm.hexagon.V6.vlsrw" => "__builtin_HEXAGON_V6_vlsrw", + "llvm.hexagon.V6.vlsrw.128B" => "__builtin_HEXAGON_V6_vlsrw_128B", + "llvm.hexagon.V6.vlsrwv" => "__builtin_HEXAGON_V6_vlsrwv", + "llvm.hexagon.V6.vlsrwv.128B" => "__builtin_HEXAGON_V6_vlsrwv_128B", + "llvm.hexagon.V6.vlutb" => "__builtin_HEXAGON_V6_vlutb", + "llvm.hexagon.V6.vlutb.128B" => "__builtin_HEXAGON_V6_vlutb_128B", + "llvm.hexagon.V6.vlutb.acc" => "__builtin_HEXAGON_V6_vlutb_acc", + "llvm.hexagon.V6.vlutb.acc.128B" => "__builtin_HEXAGON_V6_vlutb_acc_128B", + "llvm.hexagon.V6.vlutb.dv" => "__builtin_HEXAGON_V6_vlutb_dv", + "llvm.hexagon.V6.vlutb.dv.128B" => "__builtin_HEXAGON_V6_vlutb_dv_128B", + "llvm.hexagon.V6.vlutb.dv.acc" => "__builtin_HEXAGON_V6_vlutb_dv_acc", + "llvm.hexagon.V6.vlutb.dv.acc.128B" => "__builtin_HEXAGON_V6_vlutb_dv_acc_128B", + "llvm.hexagon.V6.vlutvvb" => "__builtin_HEXAGON_V6_vlutvvb", + "llvm.hexagon.V6.vlutvvb.128B" => "__builtin_HEXAGON_V6_vlutvvb_128B", + "llvm.hexagon.V6.vlutvvb.oracc" => "__builtin_HEXAGON_V6_vlutvvb_oracc", + "llvm.hexagon.V6.vlutvvb.oracc.128B" => "__builtin_HEXAGON_V6_vlutvvb_oracc_128B", + "llvm.hexagon.V6.vlutvwh" => "__builtin_HEXAGON_V6_vlutvwh", + "llvm.hexagon.V6.vlutvwh.128B" => "__builtin_HEXAGON_V6_vlutvwh_128B", + "llvm.hexagon.V6.vlutvwh.oracc" => "__builtin_HEXAGON_V6_vlutvwh_oracc", + "llvm.hexagon.V6.vlutvwh.oracc.128B" => "__builtin_HEXAGON_V6_vlutvwh_oracc_128B", + "llvm.hexagon.V6.vmaxh" => "__builtin_HEXAGON_V6_vmaxh", + "llvm.hexagon.V6.vmaxh.128B" => "__builtin_HEXAGON_V6_vmaxh_128B", + "llvm.hexagon.V6.vmaxub" => "__builtin_HEXAGON_V6_vmaxub", + "llvm.hexagon.V6.vmaxub.128B" => "__builtin_HEXAGON_V6_vmaxub_128B", + "llvm.hexagon.V6.vmaxuh" => "__builtin_HEXAGON_V6_vmaxuh", + "llvm.hexagon.V6.vmaxuh.128B" => "__builtin_HEXAGON_V6_vmaxuh_128B", + "llvm.hexagon.V6.vmaxw" => "__builtin_HEXAGON_V6_vmaxw", + "llvm.hexagon.V6.vmaxw.128B" => "__builtin_HEXAGON_V6_vmaxw_128B", + "llvm.hexagon.V6.vminh" => "__builtin_HEXAGON_V6_vminh", + "llvm.hexagon.V6.vminh.128B" => "__builtin_HEXAGON_V6_vminh_128B", + "llvm.hexagon.V6.vminub" => "__builtin_HEXAGON_V6_vminub", + "llvm.hexagon.V6.vminub.128B" => "__builtin_HEXAGON_V6_vminub_128B", + "llvm.hexagon.V6.vminuh" => "__builtin_HEXAGON_V6_vminuh", + "llvm.hexagon.V6.vminuh.128B" => "__builtin_HEXAGON_V6_vminuh_128B", + "llvm.hexagon.V6.vminw" => "__builtin_HEXAGON_V6_vminw", + "llvm.hexagon.V6.vminw.128B" => "__builtin_HEXAGON_V6_vminw_128B", + "llvm.hexagon.V6.vmpabus" => "__builtin_HEXAGON_V6_vmpabus", + "llvm.hexagon.V6.vmpabus.128B" => "__builtin_HEXAGON_V6_vmpabus_128B", + "llvm.hexagon.V6.vmpabus.acc" => "__builtin_HEXAGON_V6_vmpabus_acc", + "llvm.hexagon.V6.vmpabus.acc.128B" => "__builtin_HEXAGON_V6_vmpabus_acc_128B", + "llvm.hexagon.V6.vmpabusv" => "__builtin_HEXAGON_V6_vmpabusv", + "llvm.hexagon.V6.vmpabusv.128B" => "__builtin_HEXAGON_V6_vmpabusv_128B", + "llvm.hexagon.V6.vmpabuuv" => "__builtin_HEXAGON_V6_vmpabuuv", + "llvm.hexagon.V6.vmpabuuv.128B" => "__builtin_HEXAGON_V6_vmpabuuv_128B", + "llvm.hexagon.V6.vmpahb" => "__builtin_HEXAGON_V6_vmpahb", + "llvm.hexagon.V6.vmpahb.128B" => "__builtin_HEXAGON_V6_vmpahb_128B", + "llvm.hexagon.V6.vmpahb.acc" => "__builtin_HEXAGON_V6_vmpahb_acc", + "llvm.hexagon.V6.vmpahb.acc.128B" => "__builtin_HEXAGON_V6_vmpahb_acc_128B", + "llvm.hexagon.V6.vmpybus" => "__builtin_HEXAGON_V6_vmpybus", + "llvm.hexagon.V6.vmpybus.128B" => "__builtin_HEXAGON_V6_vmpybus_128B", + "llvm.hexagon.V6.vmpybus.acc" => "__builtin_HEXAGON_V6_vmpybus_acc", + "llvm.hexagon.V6.vmpybus.acc.128B" => "__builtin_HEXAGON_V6_vmpybus_acc_128B", + "llvm.hexagon.V6.vmpybusv" => "__builtin_HEXAGON_V6_vmpybusv", + "llvm.hexagon.V6.vmpybusv.128B" => "__builtin_HEXAGON_V6_vmpybusv_128B", + "llvm.hexagon.V6.vmpybusv.acc" => "__builtin_HEXAGON_V6_vmpybusv_acc", + "llvm.hexagon.V6.vmpybusv.acc.128B" => "__builtin_HEXAGON_V6_vmpybusv_acc_128B", + "llvm.hexagon.V6.vmpybv" => "__builtin_HEXAGON_V6_vmpybv", + "llvm.hexagon.V6.vmpybv.128B" => "__builtin_HEXAGON_V6_vmpybv_128B", + "llvm.hexagon.V6.vmpybv.acc" => "__builtin_HEXAGON_V6_vmpybv_acc", + "llvm.hexagon.V6.vmpybv.acc.128B" => "__builtin_HEXAGON_V6_vmpybv_acc_128B", + "llvm.hexagon.V6.vmpyewuh" => "__builtin_HEXAGON_V6_vmpyewuh", + "llvm.hexagon.V6.vmpyewuh.128B" => "__builtin_HEXAGON_V6_vmpyewuh_128B", + "llvm.hexagon.V6.vmpyh" => "__builtin_HEXAGON_V6_vmpyh", + "llvm.hexagon.V6.vmpyh.128B" => "__builtin_HEXAGON_V6_vmpyh_128B", + "llvm.hexagon.V6.vmpyhsat.acc" => "__builtin_HEXAGON_V6_vmpyhsat_acc", + "llvm.hexagon.V6.vmpyhsat.acc.128B" => "__builtin_HEXAGON_V6_vmpyhsat_acc_128B", + "llvm.hexagon.V6.vmpyhsrs" => "__builtin_HEXAGON_V6_vmpyhsrs", + "llvm.hexagon.V6.vmpyhsrs.128B" => "__builtin_HEXAGON_V6_vmpyhsrs_128B", + "llvm.hexagon.V6.vmpyhss" => "__builtin_HEXAGON_V6_vmpyhss", + "llvm.hexagon.V6.vmpyhss.128B" => "__builtin_HEXAGON_V6_vmpyhss_128B", + "llvm.hexagon.V6.vmpyhus" => "__builtin_HEXAGON_V6_vmpyhus", + "llvm.hexagon.V6.vmpyhus.128B" => "__builtin_HEXAGON_V6_vmpyhus_128B", + "llvm.hexagon.V6.vmpyhus.acc" => "__builtin_HEXAGON_V6_vmpyhus_acc", + "llvm.hexagon.V6.vmpyhus.acc.128B" => "__builtin_HEXAGON_V6_vmpyhus_acc_128B", + "llvm.hexagon.V6.vmpyhv" => "__builtin_HEXAGON_V6_vmpyhv", + "llvm.hexagon.V6.vmpyhv.128B" => "__builtin_HEXAGON_V6_vmpyhv_128B", + "llvm.hexagon.V6.vmpyhv.acc" => "__builtin_HEXAGON_V6_vmpyhv_acc", + "llvm.hexagon.V6.vmpyhv.acc.128B" => "__builtin_HEXAGON_V6_vmpyhv_acc_128B", + "llvm.hexagon.V6.vmpyhvsrs" => "__builtin_HEXAGON_V6_vmpyhvsrs", + "llvm.hexagon.V6.vmpyhvsrs.128B" => "__builtin_HEXAGON_V6_vmpyhvsrs_128B", + "llvm.hexagon.V6.vmpyieoh" => "__builtin_HEXAGON_V6_vmpyieoh", + "llvm.hexagon.V6.vmpyieoh.128B" => "__builtin_HEXAGON_V6_vmpyieoh_128B", + "llvm.hexagon.V6.vmpyiewh.acc" => "__builtin_HEXAGON_V6_vmpyiewh_acc", + "llvm.hexagon.V6.vmpyiewh.acc.128B" => "__builtin_HEXAGON_V6_vmpyiewh_acc_128B", + "llvm.hexagon.V6.vmpyiewuh" => "__builtin_HEXAGON_V6_vmpyiewuh", + "llvm.hexagon.V6.vmpyiewuh.128B" => "__builtin_HEXAGON_V6_vmpyiewuh_128B", + "llvm.hexagon.V6.vmpyiewuh.acc" => "__builtin_HEXAGON_V6_vmpyiewuh_acc", + "llvm.hexagon.V6.vmpyiewuh.acc.128B" => "__builtin_HEXAGON_V6_vmpyiewuh_acc_128B", + "llvm.hexagon.V6.vmpyih" => "__builtin_HEXAGON_V6_vmpyih", + "llvm.hexagon.V6.vmpyih.128B" => "__builtin_HEXAGON_V6_vmpyih_128B", + "llvm.hexagon.V6.vmpyih.acc" => "__builtin_HEXAGON_V6_vmpyih_acc", + "llvm.hexagon.V6.vmpyih.acc.128B" => "__builtin_HEXAGON_V6_vmpyih_acc_128B", + "llvm.hexagon.V6.vmpyihb" => "__builtin_HEXAGON_V6_vmpyihb", + "llvm.hexagon.V6.vmpyihb.128B" => "__builtin_HEXAGON_V6_vmpyihb_128B", + "llvm.hexagon.V6.vmpyihb.acc" => "__builtin_HEXAGON_V6_vmpyihb_acc", + "llvm.hexagon.V6.vmpyihb.acc.128B" => "__builtin_HEXAGON_V6_vmpyihb_acc_128B", + "llvm.hexagon.V6.vmpyiowh" => "__builtin_HEXAGON_V6_vmpyiowh", + "llvm.hexagon.V6.vmpyiowh.128B" => "__builtin_HEXAGON_V6_vmpyiowh_128B", + "llvm.hexagon.V6.vmpyiwb" => "__builtin_HEXAGON_V6_vmpyiwb", + "llvm.hexagon.V6.vmpyiwb.128B" => "__builtin_HEXAGON_V6_vmpyiwb_128B", + "llvm.hexagon.V6.vmpyiwb.acc" => "__builtin_HEXAGON_V6_vmpyiwb_acc", + "llvm.hexagon.V6.vmpyiwb.acc.128B" => "__builtin_HEXAGON_V6_vmpyiwb_acc_128B", + "llvm.hexagon.V6.vmpyiwh" => "__builtin_HEXAGON_V6_vmpyiwh", + "llvm.hexagon.V6.vmpyiwh.128B" => "__builtin_HEXAGON_V6_vmpyiwh_128B", + "llvm.hexagon.V6.vmpyiwh.acc" => "__builtin_HEXAGON_V6_vmpyiwh_acc", + "llvm.hexagon.V6.vmpyiwh.acc.128B" => "__builtin_HEXAGON_V6_vmpyiwh_acc_128B", + "llvm.hexagon.V6.vmpyowh" => "__builtin_HEXAGON_V6_vmpyowh", + "llvm.hexagon.V6.vmpyowh.128B" => "__builtin_HEXAGON_V6_vmpyowh_128B", + "llvm.hexagon.V6.vmpyowh.rnd" => "__builtin_HEXAGON_V6_vmpyowh_rnd", + "llvm.hexagon.V6.vmpyowh.rnd.128B" => "__builtin_HEXAGON_V6_vmpyowh_rnd_128B", + "llvm.hexagon.V6.vmpyowh.rnd.sacc" => "__builtin_HEXAGON_V6_vmpyowh_rnd_sacc", + "llvm.hexagon.V6.vmpyowh.rnd.sacc.128B" => "__builtin_HEXAGON_V6_vmpyowh_rnd_sacc_128B", + "llvm.hexagon.V6.vmpyowh.sacc" => "__builtin_HEXAGON_V6_vmpyowh_sacc", + "llvm.hexagon.V6.vmpyowh.sacc.128B" => "__builtin_HEXAGON_V6_vmpyowh_sacc_128B", + "llvm.hexagon.V6.vmpyub" => "__builtin_HEXAGON_V6_vmpyub", + "llvm.hexagon.V6.vmpyub.128B" => "__builtin_HEXAGON_V6_vmpyub_128B", + "llvm.hexagon.V6.vmpyub.acc" => "__builtin_HEXAGON_V6_vmpyub_acc", + "llvm.hexagon.V6.vmpyub.acc.128B" => "__builtin_HEXAGON_V6_vmpyub_acc_128B", + "llvm.hexagon.V6.vmpyubv" => "__builtin_HEXAGON_V6_vmpyubv", + "llvm.hexagon.V6.vmpyubv.128B" => "__builtin_HEXAGON_V6_vmpyubv_128B", + "llvm.hexagon.V6.vmpyubv.acc" => "__builtin_HEXAGON_V6_vmpyubv_acc", + "llvm.hexagon.V6.vmpyubv.acc.128B" => "__builtin_HEXAGON_V6_vmpyubv_acc_128B", + "llvm.hexagon.V6.vmpyuh" => "__builtin_HEXAGON_V6_vmpyuh", + "llvm.hexagon.V6.vmpyuh.128B" => "__builtin_HEXAGON_V6_vmpyuh_128B", + "llvm.hexagon.V6.vmpyuh.acc" => "__builtin_HEXAGON_V6_vmpyuh_acc", + "llvm.hexagon.V6.vmpyuh.acc.128B" => "__builtin_HEXAGON_V6_vmpyuh_acc_128B", + "llvm.hexagon.V6.vmpyuhv" => "__builtin_HEXAGON_V6_vmpyuhv", + "llvm.hexagon.V6.vmpyuhv.128B" => "__builtin_HEXAGON_V6_vmpyuhv_128B", + "llvm.hexagon.V6.vmpyuhv.acc" => "__builtin_HEXAGON_V6_vmpyuhv_acc", + "llvm.hexagon.V6.vmpyuhv.acc.128B" => "__builtin_HEXAGON_V6_vmpyuhv_acc_128B", + "llvm.hexagon.V6.vnavgh" => "__builtin_HEXAGON_V6_vnavgh", + "llvm.hexagon.V6.vnavgh.128B" => "__builtin_HEXAGON_V6_vnavgh_128B", + "llvm.hexagon.V6.vnavgub" => "__builtin_HEXAGON_V6_vnavgub", + "llvm.hexagon.V6.vnavgub.128B" => "__builtin_HEXAGON_V6_vnavgub_128B", + "llvm.hexagon.V6.vnavgw" => "__builtin_HEXAGON_V6_vnavgw", + "llvm.hexagon.V6.vnavgw.128B" => "__builtin_HEXAGON_V6_vnavgw_128B", + "llvm.hexagon.V6.vnormamth" => "__builtin_HEXAGON_V6_vnormamth", + "llvm.hexagon.V6.vnormamth.128B" => "__builtin_HEXAGON_V6_vnormamth_128B", + "llvm.hexagon.V6.vnormamtw" => "__builtin_HEXAGON_V6_vnormamtw", + "llvm.hexagon.V6.vnormamtw.128B" => "__builtin_HEXAGON_V6_vnormamtw_128B", + "llvm.hexagon.V6.vnot" => "__builtin_HEXAGON_V6_vnot", + "llvm.hexagon.V6.vnot.128B" => "__builtin_HEXAGON_V6_vnot_128B", + "llvm.hexagon.V6.vor" => "__builtin_HEXAGON_V6_vor", + "llvm.hexagon.V6.vor.128B" => "__builtin_HEXAGON_V6_vor_128B", + "llvm.hexagon.V6.vpackeb" => "__builtin_HEXAGON_V6_vpackeb", + "llvm.hexagon.V6.vpackeb.128B" => "__builtin_HEXAGON_V6_vpackeb_128B", + "llvm.hexagon.V6.vpackeh" => "__builtin_HEXAGON_V6_vpackeh", + "llvm.hexagon.V6.vpackeh.128B" => "__builtin_HEXAGON_V6_vpackeh_128B", + "llvm.hexagon.V6.vpackhb.sat" => "__builtin_HEXAGON_V6_vpackhb_sat", + "llvm.hexagon.V6.vpackhb.sat.128B" => "__builtin_HEXAGON_V6_vpackhb_sat_128B", + "llvm.hexagon.V6.vpackhub.sat" => "__builtin_HEXAGON_V6_vpackhub_sat", + "llvm.hexagon.V6.vpackhub.sat.128B" => "__builtin_HEXAGON_V6_vpackhub_sat_128B", + "llvm.hexagon.V6.vpackob" => "__builtin_HEXAGON_V6_vpackob", + "llvm.hexagon.V6.vpackob.128B" => "__builtin_HEXAGON_V6_vpackob_128B", + "llvm.hexagon.V6.vpackoh" => "__builtin_HEXAGON_V6_vpackoh", + "llvm.hexagon.V6.vpackoh.128B" => "__builtin_HEXAGON_V6_vpackoh_128B", + "llvm.hexagon.V6.vpackwh.sat" => "__builtin_HEXAGON_V6_vpackwh_sat", + "llvm.hexagon.V6.vpackwh.sat.128B" => "__builtin_HEXAGON_V6_vpackwh_sat_128B", + "llvm.hexagon.V6.vpackwuh.sat" => "__builtin_HEXAGON_V6_vpackwuh_sat", + "llvm.hexagon.V6.vpackwuh.sat.128B" => "__builtin_HEXAGON_V6_vpackwuh_sat_128B", + "llvm.hexagon.V6.vpopcounth" => "__builtin_HEXAGON_V6_vpopcounth", + "llvm.hexagon.V6.vpopcounth.128B" => "__builtin_HEXAGON_V6_vpopcounth_128B", + "llvm.hexagon.V6.vrdelta" => "__builtin_HEXAGON_V6_vrdelta", + "llvm.hexagon.V6.vrdelta.128B" => "__builtin_HEXAGON_V6_vrdelta_128B", + "llvm.hexagon.V6.vrmpybus" => "__builtin_HEXAGON_V6_vrmpybus", + "llvm.hexagon.V6.vrmpybus.128B" => "__builtin_HEXAGON_V6_vrmpybus_128B", + "llvm.hexagon.V6.vrmpybus.acc" => "__builtin_HEXAGON_V6_vrmpybus_acc", + "llvm.hexagon.V6.vrmpybus.acc.128B" => "__builtin_HEXAGON_V6_vrmpybus_acc_128B", + "llvm.hexagon.V6.vrmpybusi" => "__builtin_HEXAGON_V6_vrmpybusi", + "llvm.hexagon.V6.vrmpybusi.128B" => "__builtin_HEXAGON_V6_vrmpybusi_128B", + "llvm.hexagon.V6.vrmpybusi.acc" => "__builtin_HEXAGON_V6_vrmpybusi_acc", + "llvm.hexagon.V6.vrmpybusi.acc.128B" => "__builtin_HEXAGON_V6_vrmpybusi_acc_128B", + "llvm.hexagon.V6.vrmpybusv" => "__builtin_HEXAGON_V6_vrmpybusv", + "llvm.hexagon.V6.vrmpybusv.128B" => "__builtin_HEXAGON_V6_vrmpybusv_128B", + "llvm.hexagon.V6.vrmpybusv.acc" => "__builtin_HEXAGON_V6_vrmpybusv_acc", + "llvm.hexagon.V6.vrmpybusv.acc.128B" => "__builtin_HEXAGON_V6_vrmpybusv_acc_128B", + "llvm.hexagon.V6.vrmpybv" => "__builtin_HEXAGON_V6_vrmpybv", + "llvm.hexagon.V6.vrmpybv.128B" => "__builtin_HEXAGON_V6_vrmpybv_128B", + "llvm.hexagon.V6.vrmpybv.acc" => "__builtin_HEXAGON_V6_vrmpybv_acc", + "llvm.hexagon.V6.vrmpybv.acc.128B" => "__builtin_HEXAGON_V6_vrmpybv_acc_128B", + "llvm.hexagon.V6.vrmpyub" => "__builtin_HEXAGON_V6_vrmpyub", + "llvm.hexagon.V6.vrmpyub.128B" => "__builtin_HEXAGON_V6_vrmpyub_128B", + "llvm.hexagon.V6.vrmpyub.acc" => "__builtin_HEXAGON_V6_vrmpyub_acc", + "llvm.hexagon.V6.vrmpyub.acc.128B" => "__builtin_HEXAGON_V6_vrmpyub_acc_128B", + "llvm.hexagon.V6.vrmpyubi" => "__builtin_HEXAGON_V6_vrmpyubi", + "llvm.hexagon.V6.vrmpyubi.128B" => "__builtin_HEXAGON_V6_vrmpyubi_128B", + "llvm.hexagon.V6.vrmpyubi.acc" => "__builtin_HEXAGON_V6_vrmpyubi_acc", + "llvm.hexagon.V6.vrmpyubi.acc.128B" => "__builtin_HEXAGON_V6_vrmpyubi_acc_128B", + "llvm.hexagon.V6.vrmpyubv" => "__builtin_HEXAGON_V6_vrmpyubv", + "llvm.hexagon.V6.vrmpyubv.128B" => "__builtin_HEXAGON_V6_vrmpyubv_128B", + "llvm.hexagon.V6.vrmpyubv.acc" => "__builtin_HEXAGON_V6_vrmpyubv_acc", + "llvm.hexagon.V6.vrmpyubv.acc.128B" => "__builtin_HEXAGON_V6_vrmpyubv_acc_128B", + "llvm.hexagon.V6.vror" => "__builtin_HEXAGON_V6_vror", + "llvm.hexagon.V6.vror.128B" => "__builtin_HEXAGON_V6_vror_128B", + "llvm.hexagon.V6.vroundhb" => "__builtin_HEXAGON_V6_vroundhb", + "llvm.hexagon.V6.vroundhb.128B" => "__builtin_HEXAGON_V6_vroundhb_128B", + "llvm.hexagon.V6.vroundhub" => "__builtin_HEXAGON_V6_vroundhub", + "llvm.hexagon.V6.vroundhub.128B" => "__builtin_HEXAGON_V6_vroundhub_128B", + "llvm.hexagon.V6.vroundwh" => "__builtin_HEXAGON_V6_vroundwh", + "llvm.hexagon.V6.vroundwh.128B" => "__builtin_HEXAGON_V6_vroundwh_128B", + "llvm.hexagon.V6.vroundwuh" => "__builtin_HEXAGON_V6_vroundwuh", + "llvm.hexagon.V6.vroundwuh.128B" => "__builtin_HEXAGON_V6_vroundwuh_128B", + "llvm.hexagon.V6.vrsadubi" => "__builtin_HEXAGON_V6_vrsadubi", + "llvm.hexagon.V6.vrsadubi.128B" => "__builtin_HEXAGON_V6_vrsadubi_128B", + "llvm.hexagon.V6.vrsadubi.acc" => "__builtin_HEXAGON_V6_vrsadubi_acc", + "llvm.hexagon.V6.vrsadubi.acc.128B" => "__builtin_HEXAGON_V6_vrsadubi_acc_128B", + "llvm.hexagon.V6.vsathub" => "__builtin_HEXAGON_V6_vsathub", + "llvm.hexagon.V6.vsathub.128B" => "__builtin_HEXAGON_V6_vsathub_128B", + "llvm.hexagon.V6.vsatwh" => "__builtin_HEXAGON_V6_vsatwh", + "llvm.hexagon.V6.vsatwh.128B" => "__builtin_HEXAGON_V6_vsatwh_128B", + "llvm.hexagon.V6.vsb" => "__builtin_HEXAGON_V6_vsb", + "llvm.hexagon.V6.vsb.128B" => "__builtin_HEXAGON_V6_vsb_128B", + "llvm.hexagon.V6.vsh" => "__builtin_HEXAGON_V6_vsh", + "llvm.hexagon.V6.vsh.128B" => "__builtin_HEXAGON_V6_vsh_128B", + "llvm.hexagon.V6.vshufeh" => "__builtin_HEXAGON_V6_vshufeh", + "llvm.hexagon.V6.vshufeh.128B" => "__builtin_HEXAGON_V6_vshufeh_128B", + "llvm.hexagon.V6.vshuffb" => "__builtin_HEXAGON_V6_vshuffb", + "llvm.hexagon.V6.vshuffb.128B" => "__builtin_HEXAGON_V6_vshuffb_128B", + "llvm.hexagon.V6.vshuffeb" => "__builtin_HEXAGON_V6_vshuffeb", + "llvm.hexagon.V6.vshuffeb.128B" => "__builtin_HEXAGON_V6_vshuffeb_128B", + "llvm.hexagon.V6.vshuffh" => "__builtin_HEXAGON_V6_vshuffh", + "llvm.hexagon.V6.vshuffh.128B" => "__builtin_HEXAGON_V6_vshuffh_128B", + "llvm.hexagon.V6.vshuffob" => "__builtin_HEXAGON_V6_vshuffob", + "llvm.hexagon.V6.vshuffob.128B" => "__builtin_HEXAGON_V6_vshuffob_128B", + "llvm.hexagon.V6.vshuffvdd" => "__builtin_HEXAGON_V6_vshuffvdd", + "llvm.hexagon.V6.vshuffvdd.128B" => "__builtin_HEXAGON_V6_vshuffvdd_128B", + "llvm.hexagon.V6.vshufoeb" => "__builtin_HEXAGON_V6_vshufoeb", + "llvm.hexagon.V6.vshufoeb.128B" => "__builtin_HEXAGON_V6_vshufoeb_128B", + "llvm.hexagon.V6.vshufoeh" => "__builtin_HEXAGON_V6_vshufoeh", + "llvm.hexagon.V6.vshufoeh.128B" => "__builtin_HEXAGON_V6_vshufoeh_128B", + "llvm.hexagon.V6.vshufoh" => "__builtin_HEXAGON_V6_vshufoh", + "llvm.hexagon.V6.vshufoh.128B" => "__builtin_HEXAGON_V6_vshufoh_128B", + "llvm.hexagon.V6.vsubb" => "__builtin_HEXAGON_V6_vsubb", + "llvm.hexagon.V6.vsubb.128B" => "__builtin_HEXAGON_V6_vsubb_128B", + "llvm.hexagon.V6.vsubb.dv" => "__builtin_HEXAGON_V6_vsubb_dv", + "llvm.hexagon.V6.vsubb.dv.128B" => "__builtin_HEXAGON_V6_vsubb_dv_128B", + "llvm.hexagon.V6.vsubh" => "__builtin_HEXAGON_V6_vsubh", + "llvm.hexagon.V6.vsubh.128B" => "__builtin_HEXAGON_V6_vsubh_128B", + "llvm.hexagon.V6.vsubh.dv" => "__builtin_HEXAGON_V6_vsubh_dv", + "llvm.hexagon.V6.vsubh.dv.128B" => "__builtin_HEXAGON_V6_vsubh_dv_128B", + "llvm.hexagon.V6.vsubhsat" => "__builtin_HEXAGON_V6_vsubhsat", + "llvm.hexagon.V6.vsubhsat.128B" => "__builtin_HEXAGON_V6_vsubhsat_128B", + "llvm.hexagon.V6.vsubhsat.dv" => "__builtin_HEXAGON_V6_vsubhsat_dv", + "llvm.hexagon.V6.vsubhsat.dv.128B" => "__builtin_HEXAGON_V6_vsubhsat_dv_128B", + "llvm.hexagon.V6.vsubhw" => "__builtin_HEXAGON_V6_vsubhw", + "llvm.hexagon.V6.vsubhw.128B" => "__builtin_HEXAGON_V6_vsubhw_128B", + "llvm.hexagon.V6.vsububh" => "__builtin_HEXAGON_V6_vsububh", + "llvm.hexagon.V6.vsububh.128B" => "__builtin_HEXAGON_V6_vsububh_128B", + "llvm.hexagon.V6.vsububsat" => "__builtin_HEXAGON_V6_vsububsat", + "llvm.hexagon.V6.vsububsat.128B" => "__builtin_HEXAGON_V6_vsububsat_128B", + "llvm.hexagon.V6.vsububsat.dv" => "__builtin_HEXAGON_V6_vsububsat_dv", + "llvm.hexagon.V6.vsububsat.dv.128B" => "__builtin_HEXAGON_V6_vsububsat_dv_128B", + "llvm.hexagon.V6.vsubuhsat" => "__builtin_HEXAGON_V6_vsubuhsat", + "llvm.hexagon.V6.vsubuhsat.128B" => "__builtin_HEXAGON_V6_vsubuhsat_128B", + "llvm.hexagon.V6.vsubuhsat.dv" => "__builtin_HEXAGON_V6_vsubuhsat_dv", + "llvm.hexagon.V6.vsubuhsat.dv.128B" => "__builtin_HEXAGON_V6_vsubuhsat_dv_128B", + "llvm.hexagon.V6.vsubuhw" => "__builtin_HEXAGON_V6_vsubuhw", + "llvm.hexagon.V6.vsubuhw.128B" => "__builtin_HEXAGON_V6_vsubuhw_128B", + "llvm.hexagon.V6.vsubw" => "__builtin_HEXAGON_V6_vsubw", + "llvm.hexagon.V6.vsubw.128B" => "__builtin_HEXAGON_V6_vsubw_128B", + "llvm.hexagon.V6.vsubw.dv" => "__builtin_HEXAGON_V6_vsubw_dv", + "llvm.hexagon.V6.vsubw.dv.128B" => "__builtin_HEXAGON_V6_vsubw_dv_128B", + "llvm.hexagon.V6.vsubwsat" => "__builtin_HEXAGON_V6_vsubwsat", + "llvm.hexagon.V6.vsubwsat.128B" => "__builtin_HEXAGON_V6_vsubwsat_128B", + "llvm.hexagon.V6.vsubwsat.dv" => "__builtin_HEXAGON_V6_vsubwsat_dv", + "llvm.hexagon.V6.vsubwsat.dv.128B" => "__builtin_HEXAGON_V6_vsubwsat_dv_128B", + "llvm.hexagon.V6.vtmpyb" => "__builtin_HEXAGON_V6_vtmpyb", + "llvm.hexagon.V6.vtmpyb.128B" => "__builtin_HEXAGON_V6_vtmpyb_128B", + "llvm.hexagon.V6.vtmpyb.acc" => "__builtin_HEXAGON_V6_vtmpyb_acc", + "llvm.hexagon.V6.vtmpyb.acc.128B" => "__builtin_HEXAGON_V6_vtmpyb_acc_128B", + "llvm.hexagon.V6.vtmpybus" => "__builtin_HEXAGON_V6_vtmpybus", + "llvm.hexagon.V6.vtmpybus.128B" => "__builtin_HEXAGON_V6_vtmpybus_128B", + "llvm.hexagon.V6.vtmpybus.acc" => "__builtin_HEXAGON_V6_vtmpybus_acc", + "llvm.hexagon.V6.vtmpybus.acc.128B" => "__builtin_HEXAGON_V6_vtmpybus_acc_128B", + "llvm.hexagon.V6.vtmpyhb" => "__builtin_HEXAGON_V6_vtmpyhb", + "llvm.hexagon.V6.vtmpyhb.128B" => "__builtin_HEXAGON_V6_vtmpyhb_128B", + "llvm.hexagon.V6.vtmpyhb.acc" => "__builtin_HEXAGON_V6_vtmpyhb_acc", + "llvm.hexagon.V6.vtmpyhb.acc.128B" => "__builtin_HEXAGON_V6_vtmpyhb_acc_128B", + "llvm.hexagon.V6.vunpackb" => "__builtin_HEXAGON_V6_vunpackb", + "llvm.hexagon.V6.vunpackb.128B" => "__builtin_HEXAGON_V6_vunpackb_128B", + "llvm.hexagon.V6.vunpackh" => "__builtin_HEXAGON_V6_vunpackh", + "llvm.hexagon.V6.vunpackh.128B" => "__builtin_HEXAGON_V6_vunpackh_128B", + "llvm.hexagon.V6.vunpackob" => "__builtin_HEXAGON_V6_vunpackob", + "llvm.hexagon.V6.vunpackob.128B" => "__builtin_HEXAGON_V6_vunpackob_128B", + "llvm.hexagon.V6.vunpackoh" => "__builtin_HEXAGON_V6_vunpackoh", + "llvm.hexagon.V6.vunpackoh.128B" => "__builtin_HEXAGON_V6_vunpackoh_128B", + "llvm.hexagon.V6.vunpackub" => "__builtin_HEXAGON_V6_vunpackub", + "llvm.hexagon.V6.vunpackub.128B" => "__builtin_HEXAGON_V6_vunpackub_128B", + "llvm.hexagon.V6.vunpackuh" => "__builtin_HEXAGON_V6_vunpackuh", + "llvm.hexagon.V6.vunpackuh.128B" => "__builtin_HEXAGON_V6_vunpackuh_128B", + "llvm.hexagon.V6.vxor" => "__builtin_HEXAGON_V6_vxor", + "llvm.hexagon.V6.vxor.128B" => "__builtin_HEXAGON_V6_vxor_128B", + "llvm.hexagon.V6.vzb" => "__builtin_HEXAGON_V6_vzb", + "llvm.hexagon.V6.vzb.128B" => "__builtin_HEXAGON_V6_vzb_128B", + "llvm.hexagon.V6.vzh" => "__builtin_HEXAGON_V6_vzh", + "llvm.hexagon.V6.vzh.128B" => "__builtin_HEXAGON_V6_vzh_128B", + "llvm.hexagon.brev.ldb" => "__builtin_brev_ldb", + "llvm.hexagon.brev.ldd" => "__builtin_brev_ldd", + "llvm.hexagon.brev.ldh" => "__builtin_brev_ldh", + "llvm.hexagon.brev.ldub" => "__builtin_brev_ldub", + "llvm.hexagon.brev.lduh" => "__builtin_brev_lduh", + "llvm.hexagon.brev.ldw" => "__builtin_brev_ldw", + "llvm.hexagon.brev.stb" => "__builtin_brev_stb", + "llvm.hexagon.brev.std" => "__builtin_brev_std", + "llvm.hexagon.brev.sth" => "__builtin_brev_sth", + "llvm.hexagon.brev.sthhi" => "__builtin_brev_sthhi", + "llvm.hexagon.brev.stw" => "__builtin_brev_stw", + "llvm.hexagon.circ.ldb" => "__builtin_circ_ldb", "llvm.hexagon.circ.ldd" => "__builtin_circ_ldd", + "llvm.hexagon.circ.ldh" => "__builtin_circ_ldh", + "llvm.hexagon.circ.ldub" => "__builtin_circ_ldub", + "llvm.hexagon.circ.lduh" => "__builtin_circ_lduh", + "llvm.hexagon.circ.ldw" => "__builtin_circ_ldw", + "llvm.hexagon.circ.stb" => "__builtin_circ_stb", + "llvm.hexagon.circ.std" => "__builtin_circ_std", + "llvm.hexagon.circ.sth" => "__builtin_circ_sth", + "llvm.hexagon.circ.sthhi" => "__builtin_circ_sthhi", + "llvm.hexagon.circ.stw" => "__builtin_circ_stw", + "llvm.hexagon.mm256i.vaddw" => "__builtin__mm256i_vaddw", + "llvm.hexagon.prefetch" => "__builtin_HEXAGON_prefetch", // mips "llvm.mips.absq.s.ph" => "__builtin_mips_absq_s_ph", "llvm.mips.absq.s.qb" => "__builtin_mips_absq_s_qb", @@ -1789,7 +2313,9 @@ match name { "llvm.nvvm.add.rz.d" => "__nvvm_add_rz_d", "llvm.nvvm.add.rz.f" => "__nvvm_add_rz_f", "llvm.nvvm.add.rz.ftz.f" => "__nvvm_add_rz_ftz_f", + "llvm.nvvm.bar.sync" => "__nvvm_bar_sync", "llvm.nvvm.barrier0" => "__nvvm_bar0", + // [DUPLICATE]: "llvm.nvvm.barrier0" => "__syncthreads", "llvm.nvvm.barrier0.and" => "__nvvm_bar0_and", "llvm.nvvm.barrier0.or" => "__nvvm_bar0_or", "llvm.nvvm.barrier0.popc" => "__nvvm_bar0_popc", @@ -1980,6 +2506,8 @@ match name { "llvm.nvvm.rcp.rz.d" => "__nvvm_rcp_rz_d", "llvm.nvvm.rcp.rz.f" => "__nvvm_rcp_rz_f", "llvm.nvvm.rcp.rz.ftz.f" => "__nvvm_rcp_rz_ftz_f", + "llvm.nvvm.read.ptx.sreg.clock" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.clock64" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.ctaid.x" => "__nvvm_read_ptx_sreg_ctaid_x", "llvm.nvvm.read.ptx.sreg.ctaid.y" => "__nvvm_read_ptx_sreg_ctaid_y", "llvm.nvvm.read.ptx.sreg.ctaid.z" => "__nvvm_read_ptx_sreg_ctaid_z", @@ -2015,16 +2543,32 @@ match name { "llvm.nvvm.read.ptx.sreg.envreg7" => "__nvvm_read_ptx_sreg_envreg7", "llvm.nvvm.read.ptx.sreg.envreg8" => "__nvvm_read_ptx_sreg_envreg8", "llvm.nvvm.read.ptx.sreg.envreg9" => "__nvvm_read_ptx_sreg_envreg9", + "llvm.nvvm.read.ptx.sreg.gridid" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.laneid" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.lanemask.eq" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.lanemask.ge" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.lanemask.gt" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.lanemask.le" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.lanemask.lt" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.nctaid.x" => "__nvvm_read_ptx_sreg_nctaid_x", "llvm.nvvm.read.ptx.sreg.nctaid.y" => "__nvvm_read_ptx_sreg_nctaid_y", "llvm.nvvm.read.ptx.sreg.nctaid.z" => "__nvvm_read_ptx_sreg_nctaid_z", + "llvm.nvvm.read.ptx.sreg.nsmid" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.ntid.x" => "__nvvm_read_ptx_sreg_ntid_x", "llvm.nvvm.read.ptx.sreg.ntid.y" => "__nvvm_read_ptx_sreg_ntid_y", "llvm.nvvm.read.ptx.sreg.ntid.z" => "__nvvm_read_ptx_sreg_ntid_z", + "llvm.nvvm.read.ptx.sreg.nwarpid" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.pm0" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.pm1" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.pm2" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.pm3" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.smid" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.tid.x" => "__nvvm_read_ptx_sreg_tid_x", "llvm.nvvm.read.ptx.sreg.tid.y" => "__nvvm_read_ptx_sreg_tid_y", "llvm.nvvm.read.ptx.sreg.tid.z" => "__nvvm_read_ptx_sreg_tid_z", + "llvm.nvvm.read.ptx.sreg.warpid" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.warpsize" => "__nvvm_read_ptx_sreg_warpsize", + // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.warpsize" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.rotate.b32" => "__nvvm_rotate_b32", "llvm.nvvm.rotate.b64" => "__nvvm_rotate_b64", "llvm.nvvm.rotate.right.b64" => "__nvvm_rotate_right_b64", @@ -2039,6 +2583,14 @@ match name { "llvm.nvvm.saturate.d" => "__nvvm_saturate_d", "llvm.nvvm.saturate.f" => "__nvvm_saturate_f", "llvm.nvvm.saturate.ftz.f" => "__nvvm_saturate_ftz_f", + "llvm.nvvm.shfl.bfly.f32" => "__nvvm_shfl_bfly_f32", + "llvm.nvvm.shfl.bfly.i32" => "__nvvm_shfl_bfly_i32", + "llvm.nvvm.shfl.down.f32" => "__nvvm_shfl_down_f32", + "llvm.nvvm.shfl.down.i32" => "__nvvm_shfl_down_i32", + "llvm.nvvm.shfl.idx.f32" => "__nvvm_shfl_idx_f32", + "llvm.nvvm.shfl.idx.i32" => "__nvvm_shfl_idx_i32", + "llvm.nvvm.shfl.up.f32" => "__nvvm_shfl_up_f32", + "llvm.nvvm.shfl.up.i32" => "__nvvm_shfl_up_i32", "llvm.nvvm.sin.approx.f" => "__nvvm_sin_approx_f", "llvm.nvvm.sin.approx.ftz.f" => "__nvvm_sin_approx_ftz_f", "llvm.nvvm.sqrt.approx.f" => "__nvvm_sqrt_approx_f", @@ -2303,8 +2855,16 @@ match name { // ppc "llvm.ppc.addex" => "__builtin_ppc_addex", "llvm.ppc.addf128.round.to.odd" => "__builtin_addf128_round_to_odd", + "llvm.ppc.altivec.crypto.vcipher" => "__builtin_altivec_crypto_vcipher", + "llvm.ppc.altivec.crypto.vcipherlast" => "__builtin_altivec_crypto_vcipherlast", + "llvm.ppc.altivec.crypto.vncipher" => "__builtin_altivec_crypto_vncipher", + "llvm.ppc.altivec.crypto.vncipherlast" => "__builtin_altivec_crypto_vncipherlast", "llvm.ppc.altivec.crypto.vpermxor" => "__builtin_altivec_crypto_vpermxor", "llvm.ppc.altivec.crypto.vpermxor.be" => "__builtin_altivec_crypto_vpermxor_be", + "llvm.ppc.altivec.crypto.vpmsumb" => "__builtin_altivec_crypto_vpmsumb", + "llvm.ppc.altivec.crypto.vpmsumd" => "__builtin_altivec_crypto_vpmsumd", + "llvm.ppc.altivec.crypto.vpmsumh" => "__builtin_altivec_crypto_vpmsumh", + "llvm.ppc.altivec.crypto.vpmsumw" => "__builtin_altivec_crypto_vpmsumw", "llvm.ppc.altivec.crypto.vsbox" => "__builtin_altivec_crypto_vsbox", "llvm.ppc.altivec.crypto.vshasigmad" => "__builtin_altivec_crypto_vshasigmad", "llvm.ppc.altivec.crypto.vshasigmaw" => "__builtin_altivec_crypto_vshasigmaw", @@ -2448,18 +3008,22 @@ match name { "llvm.ppc.altivec.vmaddfp" => "__builtin_altivec_vmaddfp", "llvm.ppc.altivec.vmaxfp" => "__builtin_altivec_vmaxfp", "llvm.ppc.altivec.vmaxsb" => "__builtin_altivec_vmaxsb", + "llvm.ppc.altivec.vmaxsd" => "__builtin_altivec_vmaxsd", "llvm.ppc.altivec.vmaxsh" => "__builtin_altivec_vmaxsh", "llvm.ppc.altivec.vmaxsw" => "__builtin_altivec_vmaxsw", "llvm.ppc.altivec.vmaxub" => "__builtin_altivec_vmaxub", + "llvm.ppc.altivec.vmaxud" => "__builtin_altivec_vmaxud", "llvm.ppc.altivec.vmaxuh" => "__builtin_altivec_vmaxuh", "llvm.ppc.altivec.vmaxuw" => "__builtin_altivec_vmaxuw", "llvm.ppc.altivec.vmhaddshs" => "__builtin_altivec_vmhaddshs", "llvm.ppc.altivec.vmhraddshs" => "__builtin_altivec_vmhraddshs", "llvm.ppc.altivec.vminfp" => "__builtin_altivec_vminfp", "llvm.ppc.altivec.vminsb" => "__builtin_altivec_vminsb", + "llvm.ppc.altivec.vminsd" => "__builtin_altivec_vminsd", "llvm.ppc.altivec.vminsh" => "__builtin_altivec_vminsh", "llvm.ppc.altivec.vminsw" => "__builtin_altivec_vminsw", "llvm.ppc.altivec.vminub" => "__builtin_altivec_vminub", + "llvm.ppc.altivec.vminud" => "__builtin_altivec_vminud", "llvm.ppc.altivec.vminuh" => "__builtin_altivec_vminuh", "llvm.ppc.altivec.vminuw" => "__builtin_altivec_vminuw", "llvm.ppc.altivec.vmladduhm" => "__builtin_altivec_vmladduhm", @@ -2506,6 +3070,7 @@ match name { "llvm.ppc.altivec.vrfip" => "__builtin_altivec_vrfip", "llvm.ppc.altivec.vrfiz" => "__builtin_altivec_vrfiz", "llvm.ppc.altivec.vrlb" => "__builtin_altivec_vrlb", + "llvm.ppc.altivec.vrld" => "__builtin_altivec_vrld", "llvm.ppc.altivec.vrlh" => "__builtin_altivec_vrlh", "llvm.ppc.altivec.vrlw" => "__builtin_altivec_vrlw", "llvm.ppc.altivec.vrsqrtefp" => "__builtin_altivec_vrsqrtefp", @@ -2638,6 +3203,89 @@ match name { "llvm.ppc.pack.longdouble" => "__builtin_pack_longdouble", "llvm.ppc.pdepd" => "__builtin_pdepd", "llvm.ppc.pextd" => "__builtin_pextd", + "llvm.ppc.qpx.qvfabs" => "__builtin_qpx_qvfabs", + "llvm.ppc.qpx.qvfadd" => "__builtin_qpx_qvfadd", + "llvm.ppc.qpx.qvfadds" => "__builtin_qpx_qvfadds", + "llvm.ppc.qpx.qvfcfid" => "__builtin_qpx_qvfcfid", + "llvm.ppc.qpx.qvfcfids" => "__builtin_qpx_qvfcfids", + "llvm.ppc.qpx.qvfcfidu" => "__builtin_qpx_qvfcfidu", + "llvm.ppc.qpx.qvfcfidus" => "__builtin_qpx_qvfcfidus", + "llvm.ppc.qpx.qvfcmpeq" => "__builtin_qpx_qvfcmpeq", + "llvm.ppc.qpx.qvfcmpgt" => "__builtin_qpx_qvfcmpgt", + "llvm.ppc.qpx.qvfcmplt" => "__builtin_qpx_qvfcmplt", + "llvm.ppc.qpx.qvfcpsgn" => "__builtin_qpx_qvfcpsgn", + "llvm.ppc.qpx.qvfctid" => "__builtin_qpx_qvfctid", + "llvm.ppc.qpx.qvfctidu" => "__builtin_qpx_qvfctidu", + "llvm.ppc.qpx.qvfctiduz" => "__builtin_qpx_qvfctiduz", + "llvm.ppc.qpx.qvfctidz" => "__builtin_qpx_qvfctidz", + "llvm.ppc.qpx.qvfctiw" => "__builtin_qpx_qvfctiw", + "llvm.ppc.qpx.qvfctiwu" => "__builtin_qpx_qvfctiwu", + "llvm.ppc.qpx.qvfctiwuz" => "__builtin_qpx_qvfctiwuz", + "llvm.ppc.qpx.qvfctiwz" => "__builtin_qpx_qvfctiwz", + "llvm.ppc.qpx.qvflogical" => "__builtin_qpx_qvflogical", + "llvm.ppc.qpx.qvfmadd" => "__builtin_qpx_qvfmadd", + "llvm.ppc.qpx.qvfmadds" => "__builtin_qpx_qvfmadds", + "llvm.ppc.qpx.qvfmsub" => "__builtin_qpx_qvfmsub", + "llvm.ppc.qpx.qvfmsubs" => "__builtin_qpx_qvfmsubs", + "llvm.ppc.qpx.qvfmul" => "__builtin_qpx_qvfmul", + "llvm.ppc.qpx.qvfmuls" => "__builtin_qpx_qvfmuls", + "llvm.ppc.qpx.qvfnabs" => "__builtin_qpx_qvfnabs", + "llvm.ppc.qpx.qvfneg" => "__builtin_qpx_qvfneg", + "llvm.ppc.qpx.qvfnmadd" => "__builtin_qpx_qvfnmadd", + "llvm.ppc.qpx.qvfnmadds" => "__builtin_qpx_qvfnmadds", + "llvm.ppc.qpx.qvfnmsub" => "__builtin_qpx_qvfnmsub", + "llvm.ppc.qpx.qvfnmsubs" => "__builtin_qpx_qvfnmsubs", + "llvm.ppc.qpx.qvfperm" => "__builtin_qpx_qvfperm", + "llvm.ppc.qpx.qvfre" => "__builtin_qpx_qvfre", + "llvm.ppc.qpx.qvfres" => "__builtin_qpx_qvfres", + "llvm.ppc.qpx.qvfrim" => "__builtin_qpx_qvfrim", + "llvm.ppc.qpx.qvfrin" => "__builtin_qpx_qvfrin", + "llvm.ppc.qpx.qvfrip" => "__builtin_qpx_qvfrip", + "llvm.ppc.qpx.qvfriz" => "__builtin_qpx_qvfriz", + "llvm.ppc.qpx.qvfrsp" => "__builtin_qpx_qvfrsp", + "llvm.ppc.qpx.qvfrsqrte" => "__builtin_qpx_qvfrsqrte", + "llvm.ppc.qpx.qvfrsqrtes" => "__builtin_qpx_qvfrsqrtes", + "llvm.ppc.qpx.qvfsel" => "__builtin_qpx_qvfsel", + "llvm.ppc.qpx.qvfsub" => "__builtin_qpx_qvfsub", + "llvm.ppc.qpx.qvfsubs" => "__builtin_qpx_qvfsubs", + "llvm.ppc.qpx.qvftstnan" => "__builtin_qpx_qvftstnan", + "llvm.ppc.qpx.qvfxmadd" => "__builtin_qpx_qvfxmadd", + "llvm.ppc.qpx.qvfxmadds" => "__builtin_qpx_qvfxmadds", + "llvm.ppc.qpx.qvfxmul" => "__builtin_qpx_qvfxmul", + "llvm.ppc.qpx.qvfxmuls" => "__builtin_qpx_qvfxmuls", + "llvm.ppc.qpx.qvfxxcpnmadd" => "__builtin_qpx_qvfxxcpnmadd", + "llvm.ppc.qpx.qvfxxcpnmadds" => "__builtin_qpx_qvfxxcpnmadds", + "llvm.ppc.qpx.qvfxxmadd" => "__builtin_qpx_qvfxxmadd", + "llvm.ppc.qpx.qvfxxmadds" => "__builtin_qpx_qvfxxmadds", + "llvm.ppc.qpx.qvfxxnpmadd" => "__builtin_qpx_qvfxxnpmadd", + "llvm.ppc.qpx.qvfxxnpmadds" => "__builtin_qpx_qvfxxnpmadds", + "llvm.ppc.qpx.qvgpci" => "__builtin_qpx_qvgpci", + "llvm.ppc.qpx.qvlfcd" => "__builtin_qpx_qvlfcd", + "llvm.ppc.qpx.qvlfcda" => "__builtin_qpx_qvlfcda", + "llvm.ppc.qpx.qvlfcs" => "__builtin_qpx_qvlfcs", + "llvm.ppc.qpx.qvlfcsa" => "__builtin_qpx_qvlfcsa", + "llvm.ppc.qpx.qvlfd" => "__builtin_qpx_qvlfd", + "llvm.ppc.qpx.qvlfda" => "__builtin_qpx_qvlfda", + "llvm.ppc.qpx.qvlfiwa" => "__builtin_qpx_qvlfiwa", + "llvm.ppc.qpx.qvlfiwaa" => "__builtin_qpx_qvlfiwaa", + "llvm.ppc.qpx.qvlfiwz" => "__builtin_qpx_qvlfiwz", + "llvm.ppc.qpx.qvlfiwza" => "__builtin_qpx_qvlfiwza", + "llvm.ppc.qpx.qvlfs" => "__builtin_qpx_qvlfs", + "llvm.ppc.qpx.qvlfsa" => "__builtin_qpx_qvlfsa", + "llvm.ppc.qpx.qvlpcld" => "__builtin_qpx_qvlpcld", + "llvm.ppc.qpx.qvlpcls" => "__builtin_qpx_qvlpcls", + "llvm.ppc.qpx.qvlpcrd" => "__builtin_qpx_qvlpcrd", + "llvm.ppc.qpx.qvlpcrs" => "__builtin_qpx_qvlpcrs", + "llvm.ppc.qpx.qvstfcd" => "__builtin_qpx_qvstfcd", + "llvm.ppc.qpx.qvstfcda" => "__builtin_qpx_qvstfcda", + "llvm.ppc.qpx.qvstfcs" => "__builtin_qpx_qvstfcs", + "llvm.ppc.qpx.qvstfcsa" => "__builtin_qpx_qvstfcsa", + "llvm.ppc.qpx.qvstfd" => "__builtin_qpx_qvstfd", + "llvm.ppc.qpx.qvstfda" => "__builtin_qpx_qvstfda", + "llvm.ppc.qpx.qvstfiw" => "__builtin_qpx_qvstfiw", + "llvm.ppc.qpx.qvstfiwa" => "__builtin_qpx_qvstfiwa", + "llvm.ppc.qpx.qvstfs" => "__builtin_qpx_qvstfs", + "llvm.ppc.qpx.qvstfsa" => "__builtin_qpx_qvstfsa", "llvm.ppc.readflm" => "__builtin_readflm", "llvm.ppc.scalar.extract.expq" => "__builtin_vsx_scalar_extract_expq", "llvm.ppc.scalar.insert.exp.qp" => "__builtin_vsx_scalar_insert_exp_qp", @@ -2679,12 +3327,26 @@ match name { "llvm.ppc.ttest" => "__builtin_ttest", "llvm.ppc.tw" => "__builtin_ppc_tw", "llvm.ppc.unpack.longdouble" => "__builtin_unpack_longdouble", + "llvm.ppc.vsx.xsmaxdp" => "__builtin_vsx_xsmaxdp", + "llvm.ppc.vsx.xsmindp" => "__builtin_vsx_xsmindp", + "llvm.ppc.vsx.xvcmpeqdp" => "__builtin_vsx_xvcmpeqdp", "llvm.ppc.vsx.xvcmpeqdp.p" => "__builtin_vsx_xvcmpeqdp_p", + "llvm.ppc.vsx.xvcmpeqsp" => "__builtin_vsx_xvcmpeqsp", "llvm.ppc.vsx.xvcmpeqsp.p" => "__builtin_vsx_xvcmpeqsp_p", + "llvm.ppc.vsx.xvcmpgedp" => "__builtin_vsx_xvcmpgedp", "llvm.ppc.vsx.xvcmpgedp.p" => "__builtin_vsx_xvcmpgedp_p", + "llvm.ppc.vsx.xvcmpgesp" => "__builtin_vsx_xvcmpgesp", "llvm.ppc.vsx.xvcmpgesp.p" => "__builtin_vsx_xvcmpgesp_p", + "llvm.ppc.vsx.xvcmpgtdp" => "__builtin_vsx_xvcmpgtdp", "llvm.ppc.vsx.xvcmpgtdp.p" => "__builtin_vsx_xvcmpgtdp_p", + "llvm.ppc.vsx.xvcmpgtsp" => "__builtin_vsx_xvcmpgtsp", "llvm.ppc.vsx.xvcmpgtsp.p" => "__builtin_vsx_xvcmpgtsp_p", + "llvm.ppc.vsx.xvdivdp" => "__builtin_vsx_xvdivdp", + "llvm.ppc.vsx.xvdivsp" => "__builtin_vsx_xvdivsp", + "llvm.ppc.vsx.xvmaxdp" => "__builtin_vsx_xvmaxdp", + "llvm.ppc.vsx.xvmaxsp" => "__builtin_vsx_xvmaxsp", + "llvm.ppc.vsx.xvmindp" => "__builtin_vsx_xvmindp", + "llvm.ppc.vsx.xvminsp" => "__builtin_vsx_xvminsp", "llvm.ppc.vsx.xvredp" => "__builtin_vsx_xvredp", "llvm.ppc.vsx.xvresp" => "__builtin_vsx_xvresp", "llvm.ppc.vsx.xvrsqrtedp" => "__builtin_vsx_xvrsqrtedp", @@ -2693,6 +3355,7 @@ match name { "llvm.ppc.vsx.xxblendvd" => "__builtin_vsx_xxblendvd", "llvm.ppc.vsx.xxblendvh" => "__builtin_vsx_xxblendvh", "llvm.ppc.vsx.xxblendvw" => "__builtin_vsx_xxblendvw", + "llvm.ppc.vsx.xxleqv" => "__builtin_vsx_xxleqv", "llvm.ppc.vsx.xxpermx" => "__builtin_vsx_xxpermx", // ptx "llvm.ptx.bar.sync" => "__builtin_ptx_bar_sync", @@ -3012,8 +3675,30 @@ match name { "llvm.x86.avx512.conflict.q.128" => "__builtin_ia32_vpconflictdi_128", "llvm.x86.avx512.conflict.q.256" => "__builtin_ia32_vpconflictdi_256", "llvm.x86.avx512.conflict.q.512" => "__builtin_ia32_vpconflictdi_512", + "llvm.x86.avx512.cvtb2mask.128" => "__builtin_ia32_cvtb2mask128", + "llvm.x86.avx512.cvtb2mask.256" => "__builtin_ia32_cvtb2mask256", + "llvm.x86.avx512.cvtb2mask.512" => "__builtin_ia32_cvtb2mask512", + "llvm.x86.avx512.cvtd2mask.128" => "__builtin_ia32_cvtd2mask128", + "llvm.x86.avx512.cvtd2mask.256" => "__builtin_ia32_cvtd2mask256", + "llvm.x86.avx512.cvtd2mask.512" => "__builtin_ia32_cvtd2mask512", + "llvm.x86.avx512.cvtmask2b.128" => "__builtin_ia32_cvtmask2b128", + "llvm.x86.avx512.cvtmask2b.256" => "__builtin_ia32_cvtmask2b256", + "llvm.x86.avx512.cvtmask2b.512" => "__builtin_ia32_cvtmask2b512", + "llvm.x86.avx512.cvtmask2d.128" => "__builtin_ia32_cvtmask2d128", + "llvm.x86.avx512.cvtmask2d.256" => "__builtin_ia32_cvtmask2d256", + "llvm.x86.avx512.cvtmask2d.512" => "__builtin_ia32_cvtmask2d512", + "llvm.x86.avx512.cvtmask2q.128" => "__builtin_ia32_cvtmask2q128", + "llvm.x86.avx512.cvtmask2q.256" => "__builtin_ia32_cvtmask2q256", + "llvm.x86.avx512.cvtmask2q.512" => "__builtin_ia32_cvtmask2q512", + "llvm.x86.avx512.cvtmask2w.128" => "__builtin_ia32_cvtmask2w128", + "llvm.x86.avx512.cvtmask2w.256" => "__builtin_ia32_cvtmask2w256", + "llvm.x86.avx512.cvtmask2w.512" => "__builtin_ia32_cvtmask2w512", + "llvm.x86.avx512.cvtq2mask.128" => "__builtin_ia32_cvtq2mask128", + "llvm.x86.avx512.cvtq2mask.256" => "__builtin_ia32_cvtq2mask256", + "llvm.x86.avx512.cvtq2mask.512" => "__builtin_ia32_cvtq2mask512", "llvm.x86.avx512.cvtsd2usi" => "__builtin_ia32_cvtsd2usi", "llvm.x86.avx512.cvtsd2usi64" => "__builtin_ia32_cvtsd2usi64", + "llvm.x86.avx512.cvtsi2sd32" => "__builtin_ia32_cvtsi2sd32", "llvm.x86.avx512.cvtsi2sd64" => "__builtin_ia32_cvtsi2sd64", "llvm.x86.avx512.cvtsi2ss32" => "__builtin_ia32_cvtsi2ss32", "llvm.x86.avx512.cvtsi2ss64" => "__builtin_ia32_cvtsi2ss64", @@ -3032,12 +3717,16 @@ match name { "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_vcvttss2usi64", // [DUPLICATE]: "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_cvttss2usi64", "llvm.x86.avx512.cvtusi2sd" => "__builtin_ia32_cvtusi2sd", + // [DUPLICATE]: "llvm.x86.avx512.cvtusi2sd" => "__builtin_ia32_cvtusi2sd32", "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss32", // [DUPLICATE]: "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss", "llvm.x86.avx512.cvtusi642sd" => "__builtin_ia32_cvtusi2sd64", // [DUPLICATE]: "llvm.x86.avx512.cvtusi642sd" => "__builtin_ia32_cvtusi642sd", "llvm.x86.avx512.cvtusi642ss" => "__builtin_ia32_cvtusi2ss64", // [DUPLICATE]: "llvm.x86.avx512.cvtusi642ss" => "__builtin_ia32_cvtusi642ss", + "llvm.x86.avx512.cvtw2mask.128" => "__builtin_ia32_cvtw2mask128", + "llvm.x86.avx512.cvtw2mask.256" => "__builtin_ia32_cvtw2mask256", + "llvm.x86.avx512.cvtw2mask.512" => "__builtin_ia32_cvtw2mask512", "llvm.x86.avx512.dbpsadbw.128" => "__builtin_ia32_dbpsadbw128", "llvm.x86.avx512.dbpsadbw.256" => "__builtin_ia32_dbpsadbw256", "llvm.x86.avx512.dbpsadbw.512" => "__builtin_ia32_dbpsadbw512", @@ -3053,6 +3742,22 @@ match name { "llvm.x86.avx512.gather.qpi.512" => "__builtin_ia32_gatherdiv16si", "llvm.x86.avx512.gather.qpq.512" => "__builtin_ia32_gatherdiv8di", "llvm.x86.avx512.gather.qps.512" => "__builtin_ia32_gatherdiv16sf", + "llvm.x86.avx512.gather3div2.df" => "__builtin_ia32_gather3div2df", + "llvm.x86.avx512.gather3div2.di" => "__builtin_ia32_gather3div2di", + "llvm.x86.avx512.gather3div4.df" => "__builtin_ia32_gather3div4df", + "llvm.x86.avx512.gather3div4.di" => "__builtin_ia32_gather3div4di", + "llvm.x86.avx512.gather3div4.sf" => "__builtin_ia32_gather3div4sf", + "llvm.x86.avx512.gather3div4.si" => "__builtin_ia32_gather3div4si", + "llvm.x86.avx512.gather3div8.sf" => "__builtin_ia32_gather3div8sf", + "llvm.x86.avx512.gather3div8.si" => "__builtin_ia32_gather3div8si", + "llvm.x86.avx512.gather3siv2.df" => "__builtin_ia32_gather3siv2df", + "llvm.x86.avx512.gather3siv2.di" => "__builtin_ia32_gather3siv2di", + "llvm.x86.avx512.gather3siv4.df" => "__builtin_ia32_gather3siv4df", + "llvm.x86.avx512.gather3siv4.di" => "__builtin_ia32_gather3siv4di", + "llvm.x86.avx512.gather3siv4.sf" => "__builtin_ia32_gather3siv4sf", + "llvm.x86.avx512.gather3siv4.si" => "__builtin_ia32_gather3siv4si", + "llvm.x86.avx512.gather3siv8.sf" => "__builtin_ia32_gather3siv8sf", + "llvm.x86.avx512.gather3siv8.si" => "__builtin_ia32_gather3siv8si", "llvm.x86.avx512.gatherpf.dpd.512" => "__builtin_ia32_gatherpfdpd", "llvm.x86.avx512.gatherpf.dps.512" => "__builtin_ia32_gatherpfdps", "llvm.x86.avx512.gatherpf.qpd.512" => "__builtin_ia32_gatherpfqpd", @@ -3064,25 +3769,100 @@ match name { "llvm.x86.avx512.kortestc.w" => "__builtin_ia32_kortestchi", "llvm.x86.avx512.kortestz.w" => "__builtin_ia32_kortestzhi", "llvm.x86.avx512.kunpck.bw" => "__builtin_ia32_kunpckhi", + "llvm.x86.avx512.kunpck.dq" => "__builtin_ia32_kunpckdi", + "llvm.x86.avx512.kunpck.wd" => "__builtin_ia32_kunpcksi", "llvm.x86.avx512.kxnor.w" => "__builtin_ia32_kxnorhi", "llvm.x86.avx512.kxor.w" => "__builtin_ia32_kxorhi", + "llvm.x86.avx512.mask.add.pd.128" => "__builtin_ia32_addpd128_mask", + "llvm.x86.avx512.mask.add.pd.256" => "__builtin_ia32_addpd256_mask", + "llvm.x86.avx512.mask.add.pd.512" => "__builtin_ia32_addpd512_mask", + "llvm.x86.avx512.mask.add.ps.128" => "__builtin_ia32_addps128_mask", + "llvm.x86.avx512.mask.add.ps.256" => "__builtin_ia32_addps256_mask", + "llvm.x86.avx512.mask.add.ps.512" => "__builtin_ia32_addps512_mask", "llvm.x86.avx512.mask.add.sd.round" => "__builtin_ia32_addsd_round_mask", "llvm.x86.avx512.mask.add.ss.round" => "__builtin_ia32_addss_round_mask", + "llvm.x86.avx512.mask.and.pd.128" => "__builtin_ia32_andpd128_mask", + "llvm.x86.avx512.mask.and.pd.256" => "__builtin_ia32_andpd256_mask", + "llvm.x86.avx512.mask.and.pd.512" => "__builtin_ia32_andpd512_mask", + "llvm.x86.avx512.mask.and.ps.128" => "__builtin_ia32_andps128_mask", + "llvm.x86.avx512.mask.and.ps.256" => "__builtin_ia32_andps256_mask", + "llvm.x86.avx512.mask.and.ps.512" => "__builtin_ia32_andps512_mask", + "llvm.x86.avx512.mask.andn.pd.128" => "__builtin_ia32_andnpd128_mask", + "llvm.x86.avx512.mask.andn.pd.256" => "__builtin_ia32_andnpd256_mask", + "llvm.x86.avx512.mask.andn.pd.512" => "__builtin_ia32_andnpd512_mask", + "llvm.x86.avx512.mask.andn.ps.128" => "__builtin_ia32_andnps128_mask", + "llvm.x86.avx512.mask.andn.ps.256" => "__builtin_ia32_andnps256_mask", + "llvm.x86.avx512.mask.andn.ps.512" => "__builtin_ia32_andnps512_mask", "llvm.x86.avx512.mask.blend.d.512" => "__builtin_ia32_blendmd_512_mask", "llvm.x86.avx512.mask.blend.pd.512" => "__builtin_ia32_blendmpd_512_mask", "llvm.x86.avx512.mask.blend.ps.512" => "__builtin_ia32_blendmps_512_mask", "llvm.x86.avx512.mask.blend.q.512" => "__builtin_ia32_blendmq_512_mask", + "llvm.x86.avx512.mask.broadcastf32x2.256" => "__builtin_ia32_broadcastf32x2_256_mask", + "llvm.x86.avx512.mask.broadcastf32x2.512" => "__builtin_ia32_broadcastf32x2_512_mask", + "llvm.x86.avx512.mask.broadcastf32x4.256" => "__builtin_ia32_broadcastf32x4_256_mask", + "llvm.x86.avx512.mask.broadcastf32x4.512" => "__builtin_ia32_broadcastf32x4_512", + "llvm.x86.avx512.mask.broadcastf32x8.512" => "__builtin_ia32_broadcastf32x8_512_mask", + "llvm.x86.avx512.mask.broadcastf64x2.256" => "__builtin_ia32_broadcastf64x2_256_mask", + "llvm.x86.avx512.mask.broadcastf64x2.512" => "__builtin_ia32_broadcastf64x2_512_mask", + "llvm.x86.avx512.mask.broadcastf64x4.512" => "__builtin_ia32_broadcastf64x4_512", + "llvm.x86.avx512.mask.broadcasti32x2.128" => "__builtin_ia32_broadcasti32x2_128_mask", + "llvm.x86.avx512.mask.broadcasti32x2.256" => "__builtin_ia32_broadcasti32x2_256_mask", + "llvm.x86.avx512.mask.broadcasti32x2.512" => "__builtin_ia32_broadcasti32x2_512_mask", + "llvm.x86.avx512.mask.broadcasti32x4.256" => "__builtin_ia32_broadcasti32x4_256_mask", + "llvm.x86.avx512.mask.broadcasti32x4.512" => "__builtin_ia32_broadcasti32x4_512", + "llvm.x86.avx512.mask.broadcasti32x8.512" => "__builtin_ia32_broadcasti32x8_512_mask", + "llvm.x86.avx512.mask.broadcasti64x2.256" => "__builtin_ia32_broadcasti64x2_256_mask", + "llvm.x86.avx512.mask.broadcasti64x2.512" => "__builtin_ia32_broadcasti64x2_512_mask", + "llvm.x86.avx512.mask.broadcasti64x4.512" => "__builtin_ia32_broadcasti64x4_512", + "llvm.x86.avx512.mask.cmp.pd.128" => "__builtin_ia32_cmppd128_mask", + "llvm.x86.avx512.mask.cmp.pd.256" => "__builtin_ia32_cmppd256_mask", "llvm.x86.avx512.mask.cmp.pd.512" => "__builtin_ia32_cmppd512_mask", + "llvm.x86.avx512.mask.cmp.ps.128" => "__builtin_ia32_cmpps128_mask", + "llvm.x86.avx512.mask.cmp.ps.256" => "__builtin_ia32_cmpps256_mask", "llvm.x86.avx512.mask.cmp.ps.512" => "__builtin_ia32_cmpps512_mask", "llvm.x86.avx512.mask.cmp.sd" => "__builtin_ia32_cmpsd_mask", "llvm.x86.avx512.mask.cmp.ss" => "__builtin_ia32_cmpss_mask", + "llvm.x86.avx512.mask.compress.d.128" => "__builtin_ia32_compresssi128_mask", + "llvm.x86.avx512.mask.compress.d.256" => "__builtin_ia32_compresssi256_mask", + "llvm.x86.avx512.mask.compress.d.512" => "__builtin_ia32_compresssi512_mask", + "llvm.x86.avx512.mask.compress.pd.128" => "__builtin_ia32_compressdf128_mask", + "llvm.x86.avx512.mask.compress.pd.256" => "__builtin_ia32_compressdf256_mask", + "llvm.x86.avx512.mask.compress.pd.512" => "__builtin_ia32_compressdf512_mask", + "llvm.x86.avx512.mask.compress.ps.128" => "__builtin_ia32_compresssf128_mask", + "llvm.x86.avx512.mask.compress.ps.256" => "__builtin_ia32_compresssf256_mask", + "llvm.x86.avx512.mask.compress.ps.512" => "__builtin_ia32_compresssf512_mask", + "llvm.x86.avx512.mask.compress.q.128" => "__builtin_ia32_compressdi128_mask", + "llvm.x86.avx512.mask.compress.q.256" => "__builtin_ia32_compressdi256_mask", + "llvm.x86.avx512.mask.compress.q.512" => "__builtin_ia32_compressdi512_mask", + "llvm.x86.avx512.mask.compress.store.d.128" => "__builtin_ia32_compressstoresi128_mask", + "llvm.x86.avx512.mask.compress.store.d.256" => "__builtin_ia32_compressstoresi256_mask", + "llvm.x86.avx512.mask.compress.store.d.512" => "__builtin_ia32_compressstoresi512_mask", + "llvm.x86.avx512.mask.compress.store.pd.128" => "__builtin_ia32_compressstoredf128_mask", + "llvm.x86.avx512.mask.compress.store.pd.256" => "__builtin_ia32_compressstoredf256_mask", + "llvm.x86.avx512.mask.compress.store.pd.512" => "__builtin_ia32_compressstoredf512_mask", + "llvm.x86.avx512.mask.compress.store.ps.128" => "__builtin_ia32_compressstoresf128_mask", + "llvm.x86.avx512.mask.compress.store.ps.256" => "__builtin_ia32_compressstoresf256_mask", + "llvm.x86.avx512.mask.compress.store.ps.512" => "__builtin_ia32_compressstoresf512_mask", + "llvm.x86.avx512.mask.compress.store.q.128" => "__builtin_ia32_compressstoredi128_mask", + "llvm.x86.avx512.mask.compress.store.q.256" => "__builtin_ia32_compressstoredi256_mask", + "llvm.x86.avx512.mask.compress.store.q.512" => "__builtin_ia32_compressstoredi512_mask", + "llvm.x86.avx512.mask.conflict.d.128" => "__builtin_ia32_vpconflictsi_128_mask", + "llvm.x86.avx512.mask.conflict.d.256" => "__builtin_ia32_vpconflictsi_256_mask", "llvm.x86.avx512.mask.conflict.d.512" => "__builtin_ia32_vpconflictsi_512_mask", + "llvm.x86.avx512.mask.conflict.q.128" => "__builtin_ia32_vpconflictdi_128_mask", + "llvm.x86.avx512.mask.conflict.q.256" => "__builtin_ia32_vpconflictdi_256_mask", "llvm.x86.avx512.mask.conflict.q.512" => "__builtin_ia32_vpconflictdi_512_mask", + "llvm.x86.avx512.mask.cvtdq2pd.128" => "__builtin_ia32_cvtdq2pd128_mask", + "llvm.x86.avx512.mask.cvtdq2pd.256" => "__builtin_ia32_cvtdq2pd256_mask", "llvm.x86.avx512.mask.cvtdq2pd.512" => "__builtin_ia32_cvtdq2pd512_mask", + "llvm.x86.avx512.mask.cvtdq2ps.128" => "__builtin_ia32_cvtdq2ps128_mask", + "llvm.x86.avx512.mask.cvtdq2ps.256" => "__builtin_ia32_cvtdq2ps256_mask", "llvm.x86.avx512.mask.cvtdq2ps.512" => "__builtin_ia32_cvtdq2ps512_mask", "llvm.x86.avx512.mask.cvtpd2dq.128" => "__builtin_ia32_cvtpd2dq128_mask", + "llvm.x86.avx512.mask.cvtpd2dq.256" => "__builtin_ia32_cvtpd2dq256_mask", "llvm.x86.avx512.mask.cvtpd2dq.512" => "__builtin_ia32_cvtpd2dq512_mask", "llvm.x86.avx512.mask.cvtpd2ps" => "__builtin_ia32_cvtpd2ps_mask", + "llvm.x86.avx512.mask.cvtpd2ps.256" => "__builtin_ia32_cvtpd2ps256_mask", "llvm.x86.avx512.mask.cvtpd2ps.512" => "__builtin_ia32_cvtpd2ps512_mask", "llvm.x86.avx512.mask.cvtpd2qq.128" => "__builtin_ia32_cvtpd2qq128_mask", "llvm.x86.avx512.mask.cvtpd2qq.256" => "__builtin_ia32_cvtpd2qq256_mask", @@ -3096,6 +3876,8 @@ match name { "llvm.x86.avx512.mask.cvtps2dq.128" => "__builtin_ia32_cvtps2dq128_mask", "llvm.x86.avx512.mask.cvtps2dq.256" => "__builtin_ia32_cvtps2dq256_mask", "llvm.x86.avx512.mask.cvtps2dq.512" => "__builtin_ia32_cvtps2dq512_mask", + "llvm.x86.avx512.mask.cvtps2pd.128" => "__builtin_ia32_cvtps2pd128_mask", + "llvm.x86.avx512.mask.cvtps2pd.256" => "__builtin_ia32_cvtps2pd256_mask", "llvm.x86.avx512.mask.cvtps2pd.512" => "__builtin_ia32_cvtps2pd512_mask", "llvm.x86.avx512.mask.cvtps2qq.128" => "__builtin_ia32_cvtps2qq128_mask", "llvm.x86.avx512.mask.cvtps2qq.256" => "__builtin_ia32_cvtps2qq256_mask", @@ -3106,10 +3888,16 @@ match name { "llvm.x86.avx512.mask.cvtps2uqq.128" => "__builtin_ia32_cvtps2uqq128_mask", "llvm.x86.avx512.mask.cvtps2uqq.256" => "__builtin_ia32_cvtps2uqq256_mask", "llvm.x86.avx512.mask.cvtps2uqq.512" => "__builtin_ia32_cvtps2uqq512_mask", + "llvm.x86.avx512.mask.cvtqq2pd.128" => "__builtin_ia32_cvtqq2pd128_mask", + "llvm.x86.avx512.mask.cvtqq2pd.256" => "__builtin_ia32_cvtqq2pd256_mask", + "llvm.x86.avx512.mask.cvtqq2pd.512" => "__builtin_ia32_cvtqq2pd512_mask", "llvm.x86.avx512.mask.cvtqq2ps.128" => "__builtin_ia32_cvtqq2ps128_mask", + "llvm.x86.avx512.mask.cvtqq2ps.256" => "__builtin_ia32_cvtqq2ps256_mask", + "llvm.x86.avx512.mask.cvtqq2ps.512" => "__builtin_ia32_cvtqq2ps512_mask", "llvm.x86.avx512.mask.cvtsd2ss.round" => "__builtin_ia32_cvtsd2ss_round_mask", "llvm.x86.avx512.mask.cvtss2sd.round" => "__builtin_ia32_cvtss2sd_round_mask", "llvm.x86.avx512.mask.cvttpd2dq.128" => "__builtin_ia32_cvttpd2dq128_mask", + "llvm.x86.avx512.mask.cvttpd2dq.256" => "__builtin_ia32_cvttpd2dq256_mask", "llvm.x86.avx512.mask.cvttpd2dq.512" => "__builtin_ia32_cvttpd2dq512_mask", "llvm.x86.avx512.mask.cvttpd2qq.128" => "__builtin_ia32_cvttpd2qq128_mask", "llvm.x86.avx512.mask.cvttpd2qq.256" => "__builtin_ia32_cvttpd2qq256_mask", @@ -3120,6 +3908,8 @@ match name { "llvm.x86.avx512.mask.cvttpd2uqq.128" => "__builtin_ia32_cvttpd2uqq128_mask", "llvm.x86.avx512.mask.cvttpd2uqq.256" => "__builtin_ia32_cvttpd2uqq256_mask", "llvm.x86.avx512.mask.cvttpd2uqq.512" => "__builtin_ia32_cvttpd2uqq512_mask", + "llvm.x86.avx512.mask.cvttps2dq.128" => "__builtin_ia32_cvttps2dq128_mask", + "llvm.x86.avx512.mask.cvttps2dq.256" => "__builtin_ia32_cvttps2dq256_mask", "llvm.x86.avx512.mask.cvttps2dq.512" => "__builtin_ia32_cvttps2dq512_mask", "llvm.x86.avx512.mask.cvttps2qq.128" => "__builtin_ia32_cvttps2qq128_mask", "llvm.x86.avx512.mask.cvttps2qq.256" => "__builtin_ia32_cvttps2qq256_mask", @@ -3130,11 +3920,53 @@ match name { "llvm.x86.avx512.mask.cvttps2uqq.128" => "__builtin_ia32_cvttps2uqq128_mask", "llvm.x86.avx512.mask.cvttps2uqq.256" => "__builtin_ia32_cvttps2uqq256_mask", "llvm.x86.avx512.mask.cvttps2uqq.512" => "__builtin_ia32_cvttps2uqq512_mask", + "llvm.x86.avx512.mask.cvtudq2pd.128" => "__builtin_ia32_cvtudq2pd128_mask", + "llvm.x86.avx512.mask.cvtudq2pd.256" => "__builtin_ia32_cvtudq2pd256_mask", "llvm.x86.avx512.mask.cvtudq2pd.512" => "__builtin_ia32_cvtudq2pd512_mask", + "llvm.x86.avx512.mask.cvtudq2ps.128" => "__builtin_ia32_cvtudq2ps128_mask", + "llvm.x86.avx512.mask.cvtudq2ps.256" => "__builtin_ia32_cvtudq2ps256_mask", "llvm.x86.avx512.mask.cvtudq2ps.512" => "__builtin_ia32_cvtudq2ps512_mask", + "llvm.x86.avx512.mask.cvtuqq2pd.128" => "__builtin_ia32_cvtuqq2pd128_mask", + "llvm.x86.avx512.mask.cvtuqq2pd.256" => "__builtin_ia32_cvtuqq2pd256_mask", + "llvm.x86.avx512.mask.cvtuqq2pd.512" => "__builtin_ia32_cvtuqq2pd512_mask", "llvm.x86.avx512.mask.cvtuqq2ps.128" => "__builtin_ia32_cvtuqq2ps128_mask", + "llvm.x86.avx512.mask.cvtuqq2ps.256" => "__builtin_ia32_cvtuqq2ps256_mask", + "llvm.x86.avx512.mask.cvtuqq2ps.512" => "__builtin_ia32_cvtuqq2ps512_mask", + "llvm.x86.avx512.mask.dbpsadbw.128" => "__builtin_ia32_dbpsadbw128_mask", + "llvm.x86.avx512.mask.dbpsadbw.256" => "__builtin_ia32_dbpsadbw256_mask", + "llvm.x86.avx512.mask.dbpsadbw.512" => "__builtin_ia32_dbpsadbw512_mask", + "llvm.x86.avx512.mask.div.pd.128" => "__builtin_ia32_divpd_mask", + "llvm.x86.avx512.mask.div.pd.256" => "__builtin_ia32_divpd256_mask", + "llvm.x86.avx512.mask.div.pd.512" => "__builtin_ia32_divpd512_mask", + "llvm.x86.avx512.mask.div.ps.128" => "__builtin_ia32_divps_mask", + "llvm.x86.avx512.mask.div.ps.256" => "__builtin_ia32_divps256_mask", + "llvm.x86.avx512.mask.div.ps.512" => "__builtin_ia32_divps512_mask", "llvm.x86.avx512.mask.div.sd.round" => "__builtin_ia32_divsd_round_mask", "llvm.x86.avx512.mask.div.ss.round" => "__builtin_ia32_divss_round_mask", + "llvm.x86.avx512.mask.expand.d.128" => "__builtin_ia32_expandsi128_mask", + "llvm.x86.avx512.mask.expand.d.256" => "__builtin_ia32_expandsi256_mask", + "llvm.x86.avx512.mask.expand.d.512" => "__builtin_ia32_expandsi512_mask", + "llvm.x86.avx512.mask.expand.load.d.128" => "__builtin_ia32_expandloadsi128_mask", + "llvm.x86.avx512.mask.expand.load.d.256" => "__builtin_ia32_expandloadsi256_mask", + "llvm.x86.avx512.mask.expand.load.d.512" => "__builtin_ia32_expandloadsi512_mask", + "llvm.x86.avx512.mask.expand.load.pd.128" => "__builtin_ia32_expandloaddf128_mask", + "llvm.x86.avx512.mask.expand.load.pd.256" => "__builtin_ia32_expandloaddf256_mask", + "llvm.x86.avx512.mask.expand.load.pd.512" => "__builtin_ia32_expandloaddf512_mask", + "llvm.x86.avx512.mask.expand.load.ps.128" => "__builtin_ia32_expandloadsf128_mask", + "llvm.x86.avx512.mask.expand.load.ps.256" => "__builtin_ia32_expandloadsf256_mask", + "llvm.x86.avx512.mask.expand.load.ps.512" => "__builtin_ia32_expandloadsf512_mask", + "llvm.x86.avx512.mask.expand.load.q.128" => "__builtin_ia32_expandloaddi128_mask", + "llvm.x86.avx512.mask.expand.load.q.256" => "__builtin_ia32_expandloaddi256_mask", + "llvm.x86.avx512.mask.expand.load.q.512" => "__builtin_ia32_expandloaddi512_mask", + "llvm.x86.avx512.mask.expand.pd.128" => "__builtin_ia32_expanddf128_mask", + "llvm.x86.avx512.mask.expand.pd.256" => "__builtin_ia32_expanddf256_mask", + "llvm.x86.avx512.mask.expand.pd.512" => "__builtin_ia32_expanddf512_mask", + "llvm.x86.avx512.mask.expand.ps.128" => "__builtin_ia32_expandsf128_mask", + "llvm.x86.avx512.mask.expand.ps.256" => "__builtin_ia32_expandsf256_mask", + "llvm.x86.avx512.mask.expand.ps.512" => "__builtin_ia32_expandsf512_mask", + "llvm.x86.avx512.mask.expand.q.128" => "__builtin_ia32_expanddi128_mask", + "llvm.x86.avx512.mask.expand.q.256" => "__builtin_ia32_expanddi256_mask", + "llvm.x86.avx512.mask.expand.q.512" => "__builtin_ia32_expanddi512_mask", "llvm.x86.avx512.mask.fixupimm.pd.128" => "__builtin_ia32_fixupimmpd128_mask", "llvm.x86.avx512.mask.fixupimm.pd.256" => "__builtin_ia32_fixupimmpd256_mask", "llvm.x86.avx512.mask.fixupimm.pd.512" => "__builtin_ia32_fixupimmpd512_mask", @@ -3143,6 +3975,12 @@ match name { "llvm.x86.avx512.mask.fixupimm.ps.512" => "__builtin_ia32_fixupimmps512_mask", "llvm.x86.avx512.mask.fixupimm.sd" => "__builtin_ia32_fixupimmsd_mask", "llvm.x86.avx512.mask.fixupimm.ss" => "__builtin_ia32_fixupimmss_mask", + "llvm.x86.avx512.mask.fpclass.pd.128" => "__builtin_ia32_fpclasspd128_mask", + "llvm.x86.avx512.mask.fpclass.pd.256" => "__builtin_ia32_fpclasspd256_mask", + "llvm.x86.avx512.mask.fpclass.pd.512" => "__builtin_ia32_fpclasspd512_mask", + "llvm.x86.avx512.mask.fpclass.ps.128" => "__builtin_ia32_fpclassps128_mask", + "llvm.x86.avx512.mask.fpclass.ps.256" => "__builtin_ia32_fpclassps256_mask", + "llvm.x86.avx512.mask.fpclass.ps.512" => "__builtin_ia32_fpclassps512_mask", "llvm.x86.avx512.mask.fpclass.sd" => "__builtin_ia32_fpclasssd_mask", "llvm.x86.avx512.mask.fpclass.ss" => "__builtin_ia32_fpclassss_mask", "llvm.x86.avx512.mask.getexp.pd.128" => "__builtin_ia32_getexppd128_mask", @@ -3161,29 +3999,125 @@ match name { "llvm.x86.avx512.mask.getmant.ps.512" => "__builtin_ia32_getmantps512_mask", "llvm.x86.avx512.mask.getmant.sd" => "__builtin_ia32_getmantsd_round_mask", "llvm.x86.avx512.mask.getmant.ss" => "__builtin_ia32_getmantss_round_mask", + "llvm.x86.avx512.mask.insertf32x4.256" => "__builtin_ia32_insertf32x4_256_mask", + "llvm.x86.avx512.mask.insertf32x4.512" => "__builtin_ia32_insertf32x4_mask", + "llvm.x86.avx512.mask.insertf32x8.512" => "__builtin_ia32_insertf32x8_mask", + "llvm.x86.avx512.mask.insertf64x2.256" => "__builtin_ia32_insertf64x2_256_mask", + "llvm.x86.avx512.mask.insertf64x2.512" => "__builtin_ia32_insertf64x2_512_mask", + "llvm.x86.avx512.mask.insertf64x4.512" => "__builtin_ia32_insertf64x4_mask", + "llvm.x86.avx512.mask.inserti32x4.256" => "__builtin_ia32_inserti32x4_256_mask", + "llvm.x86.avx512.mask.inserti32x4.512" => "__builtin_ia32_inserti32x4_mask", + "llvm.x86.avx512.mask.inserti32x8.512" => "__builtin_ia32_inserti32x8_mask", + "llvm.x86.avx512.mask.inserti64x2.256" => "__builtin_ia32_inserti64x2_256_mask", + "llvm.x86.avx512.mask.inserti64x2.512" => "__builtin_ia32_inserti64x2_512_mask", + "llvm.x86.avx512.mask.inserti64x4.512" => "__builtin_ia32_inserti64x4_mask", "llvm.x86.avx512.mask.loadu.d.512" => "__builtin_ia32_loaddqusi512_mask", "llvm.x86.avx512.mask.loadu.pd.512" => "__builtin_ia32_loadupd512_mask", "llvm.x86.avx512.mask.loadu.ps.512" => "__builtin_ia32_loadups512_mask", "llvm.x86.avx512.mask.loadu.q.512" => "__builtin_ia32_loaddqudi512_mask", "llvm.x86.avx512.mask.lzcnt.d.512" => "__builtin_ia32_vplzcntd_512_mask", "llvm.x86.avx512.mask.lzcnt.q.512" => "__builtin_ia32_vplzcntq_512_mask", + "llvm.x86.avx512.mask.max.pd.128" => "__builtin_ia32_maxpd_mask", + "llvm.x86.avx512.mask.max.pd.256" => "__builtin_ia32_maxpd256_mask", "llvm.x86.avx512.mask.max.pd.512" => "__builtin_ia32_maxpd512_mask", + "llvm.x86.avx512.mask.max.ps.128" => "__builtin_ia32_maxps_mask", + "llvm.x86.avx512.mask.max.ps.256" => "__builtin_ia32_maxps256_mask", "llvm.x86.avx512.mask.max.ps.512" => "__builtin_ia32_maxps512_mask", "llvm.x86.avx512.mask.max.sd.round" => "__builtin_ia32_maxsd_round_mask", "llvm.x86.avx512.mask.max.ss.round" => "__builtin_ia32_maxss_round_mask", + "llvm.x86.avx512.mask.min.pd.128" => "__builtin_ia32_minpd_mask", + "llvm.x86.avx512.mask.min.pd.256" => "__builtin_ia32_minpd256_mask", "llvm.x86.avx512.mask.min.pd.512" => "__builtin_ia32_minpd512_mask", + "llvm.x86.avx512.mask.min.ps.128" => "__builtin_ia32_minps_mask", + "llvm.x86.avx512.mask.min.ps.256" => "__builtin_ia32_minps256_mask", "llvm.x86.avx512.mask.min.ps.512" => "__builtin_ia32_minps512_mask", "llvm.x86.avx512.mask.min.sd.round" => "__builtin_ia32_minsd_round_mask", "llvm.x86.avx512.mask.min.ss.round" => "__builtin_ia32_minss_round_mask", + "llvm.x86.avx512.mask.move.sd" => "__builtin_ia32_movsd_mask", + "llvm.x86.avx512.mask.move.ss" => "__builtin_ia32_movss_mask", + "llvm.x86.avx512.mask.mul.pd.128" => "__builtin_ia32_mulpd_mask", + "llvm.x86.avx512.mask.mul.pd.256" => "__builtin_ia32_mulpd256_mask", + "llvm.x86.avx512.mask.mul.pd.512" => "__builtin_ia32_mulpd512_mask", + "llvm.x86.avx512.mask.mul.ps.128" => "__builtin_ia32_mulps_mask", + "llvm.x86.avx512.mask.mul.ps.256" => "__builtin_ia32_mulps256_mask", + "llvm.x86.avx512.mask.mul.ps.512" => "__builtin_ia32_mulps512_mask", "llvm.x86.avx512.mask.mul.sd.round" => "__builtin_ia32_mulsd_round_mask", "llvm.x86.avx512.mask.mul.ss.round" => "__builtin_ia32_mulss_round_mask", + "llvm.x86.avx512.mask.or.pd.128" => "__builtin_ia32_orpd128_mask", + "llvm.x86.avx512.mask.or.pd.256" => "__builtin_ia32_orpd256_mask", + "llvm.x86.avx512.mask.or.pd.512" => "__builtin_ia32_orpd512_mask", + "llvm.x86.avx512.mask.or.ps.128" => "__builtin_ia32_orps128_mask", + "llvm.x86.avx512.mask.or.ps.256" => "__builtin_ia32_orps256_mask", + "llvm.x86.avx512.mask.or.ps.512" => "__builtin_ia32_orps512_mask", + "llvm.x86.avx512.mask.pabs.b.128" => "__builtin_ia32_pabsb128_mask", + "llvm.x86.avx512.mask.pabs.b.256" => "__builtin_ia32_pabsb256_mask", + "llvm.x86.avx512.mask.pabs.b.512" => "__builtin_ia32_pabsb512_mask", + "llvm.x86.avx512.mask.pabs.d.128" => "__builtin_ia32_pabsd128_mask", + "llvm.x86.avx512.mask.pabs.d.256" => "__builtin_ia32_pabsd256_mask", "llvm.x86.avx512.mask.pabs.d.512" => "__builtin_ia32_pabsd512_mask", + "llvm.x86.avx512.mask.pabs.q.128" => "__builtin_ia32_pabsq128_mask", + "llvm.x86.avx512.mask.pabs.q.256" => "__builtin_ia32_pabsq256_mask", "llvm.x86.avx512.mask.pabs.q.512" => "__builtin_ia32_pabsq512_mask", + "llvm.x86.avx512.mask.pabs.w.128" => "__builtin_ia32_pabsw128_mask", + "llvm.x86.avx512.mask.pabs.w.256" => "__builtin_ia32_pabsw256_mask", + "llvm.x86.avx512.mask.pabs.w.512" => "__builtin_ia32_pabsw512_mask", + "llvm.x86.avx512.mask.packssdw.128" => "__builtin_ia32_packssdw128_mask", + "llvm.x86.avx512.mask.packssdw.256" => "__builtin_ia32_packssdw256_mask", + "llvm.x86.avx512.mask.packssdw.512" => "__builtin_ia32_packssdw512_mask", + "llvm.x86.avx512.mask.packsswb.128" => "__builtin_ia32_packsswb128_mask", + "llvm.x86.avx512.mask.packsswb.256" => "__builtin_ia32_packsswb256_mask", + "llvm.x86.avx512.mask.packsswb.512" => "__builtin_ia32_packsswb512_mask", + "llvm.x86.avx512.mask.packusdw.128" => "__builtin_ia32_packusdw128_mask", + "llvm.x86.avx512.mask.packusdw.256" => "__builtin_ia32_packusdw256_mask", + "llvm.x86.avx512.mask.packusdw.512" => "__builtin_ia32_packusdw512_mask", + "llvm.x86.avx512.mask.packuswb.128" => "__builtin_ia32_packuswb128_mask", + "llvm.x86.avx512.mask.packuswb.256" => "__builtin_ia32_packuswb256_mask", + "llvm.x86.avx512.mask.packuswb.512" => "__builtin_ia32_packuswb512_mask", + "llvm.x86.avx512.mask.padd.b.128" => "__builtin_ia32_paddb128_mask", + "llvm.x86.avx512.mask.padd.b.256" => "__builtin_ia32_paddb256_mask", + "llvm.x86.avx512.mask.padd.b.512" => "__builtin_ia32_paddb512_mask", + "llvm.x86.avx512.mask.padd.d.128" => "__builtin_ia32_paddd128_mask", + "llvm.x86.avx512.mask.padd.d.256" => "__builtin_ia32_paddd256_mask", + "llvm.x86.avx512.mask.padd.d.512" => "__builtin_ia32_paddd512_mask", + "llvm.x86.avx512.mask.padd.q.128" => "__builtin_ia32_paddq128_mask", + "llvm.x86.avx512.mask.padd.q.256" => "__builtin_ia32_paddq256_mask", + "llvm.x86.avx512.mask.padd.q.512" => "__builtin_ia32_paddq512_mask", + "llvm.x86.avx512.mask.padd.w.128" => "__builtin_ia32_paddw128_mask", + "llvm.x86.avx512.mask.padd.w.256" => "__builtin_ia32_paddw256_mask", + "llvm.x86.avx512.mask.padd.w.512" => "__builtin_ia32_paddw512_mask", + "llvm.x86.avx512.mask.padds.b.128" => "__builtin_ia32_paddsb128_mask", + "llvm.x86.avx512.mask.padds.b.256" => "__builtin_ia32_paddsb256_mask", + "llvm.x86.avx512.mask.padds.b.512" => "__builtin_ia32_paddsb512_mask", + "llvm.x86.avx512.mask.padds.w.128" => "__builtin_ia32_paddsw128_mask", + "llvm.x86.avx512.mask.padds.w.256" => "__builtin_ia32_paddsw256_mask", + "llvm.x86.avx512.mask.padds.w.512" => "__builtin_ia32_paddsw512_mask", + "llvm.x86.avx512.mask.paddus.b.128" => "__builtin_ia32_paddusb128_mask", + "llvm.x86.avx512.mask.paddus.b.256" => "__builtin_ia32_paddusb256_mask", + "llvm.x86.avx512.mask.paddus.b.512" => "__builtin_ia32_paddusb512_mask", + "llvm.x86.avx512.mask.paddus.w.128" => "__builtin_ia32_paddusw128_mask", + "llvm.x86.avx512.mask.paddus.w.256" => "__builtin_ia32_paddusw256_mask", + "llvm.x86.avx512.mask.paddus.w.512" => "__builtin_ia32_paddusw512_mask", "llvm.x86.avx512.mask.pand.d.512" => "__builtin_ia32_pandd512_mask", "llvm.x86.avx512.mask.pand.q.512" => "__builtin_ia32_pandq512_mask", + "llvm.x86.avx512.mask.pavg.b.128" => "__builtin_ia32_pavgb128_mask", + "llvm.x86.avx512.mask.pavg.b.256" => "__builtin_ia32_pavgb256_mask", + "llvm.x86.avx512.mask.pavg.b.512" => "__builtin_ia32_pavgb512_mask", + "llvm.x86.avx512.mask.pavg.w.128" => "__builtin_ia32_pavgw128_mask", + "llvm.x86.avx512.mask.pavg.w.256" => "__builtin_ia32_pavgw256_mask", + "llvm.x86.avx512.mask.pavg.w.512" => "__builtin_ia32_pavgw512_mask", + "llvm.x86.avx512.mask.pbroadcast.b.gpr.128" => "__builtin_ia32_pbroadcastb128_gpr_mask", + "llvm.x86.avx512.mask.pbroadcast.b.gpr.256" => "__builtin_ia32_pbroadcastb256_gpr_mask", + "llvm.x86.avx512.mask.pbroadcast.b.gpr.512" => "__builtin_ia32_pbroadcastb512_gpr_mask", + "llvm.x86.avx512.mask.pbroadcast.d.gpr.128" => "__builtin_ia32_pbroadcastd128_gpr_mask", + "llvm.x86.avx512.mask.pbroadcast.d.gpr.256" => "__builtin_ia32_pbroadcastd256_gpr_mask", "llvm.x86.avx512.mask.pbroadcast.d.gpr.512" => "__builtin_ia32_pbroadcastd512_gpr_mask", + "llvm.x86.avx512.mask.pbroadcast.q.gpr.128" => "__builtin_ia32_pbroadcastq128_gpr_mask", + "llvm.x86.avx512.mask.pbroadcast.q.gpr.256" => "__builtin_ia32_pbroadcastq256_gpr_mask", "llvm.x86.avx512.mask.pbroadcast.q.gpr.512" => "__builtin_ia32_pbroadcastq512_gpr_mask", "llvm.x86.avx512.mask.pbroadcast.q.mem.512" => "__builtin_ia32_pbroadcastq512_mem_mask", + "llvm.x86.avx512.mask.pbroadcast.w.gpr.128" => "__builtin_ia32_pbroadcastw128_gpr_mask", + "llvm.x86.avx512.mask.pbroadcast.w.gpr.256" => "__builtin_ia32_pbroadcastw256_gpr_mask", + "llvm.x86.avx512.mask.pbroadcast.w.gpr.512" => "__builtin_ia32_pbroadcastw512_gpr_mask", "llvm.x86.avx512.mask.pcmpeq.b.128" => "__builtin_ia32_pcmpeqb128_mask", "llvm.x86.avx512.mask.pcmpeq.b.256" => "__builtin_ia32_pcmpeqb256_mask", "llvm.x86.avx512.mask.pcmpeq.b.512" => "__builtin_ia32_pcmpeqb512_mask", @@ -3208,21 +4142,83 @@ match name { "llvm.x86.avx512.mask.pcmpgt.w.128" => "__builtin_ia32_pcmpgtw128_mask", "llvm.x86.avx512.mask.pcmpgt.w.256" => "__builtin_ia32_pcmpgtw256_mask", "llvm.x86.avx512.mask.pcmpgt.w.512" => "__builtin_ia32_pcmpgtw512_mask", + "llvm.x86.avx512.mask.permvar.df.256" => "__builtin_ia32_permvardf256_mask", + "llvm.x86.avx512.mask.permvar.df.512" => "__builtin_ia32_permvardf512_mask", + "llvm.x86.avx512.mask.permvar.di.256" => "__builtin_ia32_permvardi256_mask", + "llvm.x86.avx512.mask.permvar.di.512" => "__builtin_ia32_permvardi512_mask", + "llvm.x86.avx512.mask.permvar.hi.128" => "__builtin_ia32_permvarhi128_mask", + "llvm.x86.avx512.mask.permvar.hi.256" => "__builtin_ia32_permvarhi256_mask", + "llvm.x86.avx512.mask.permvar.hi.512" => "__builtin_ia32_permvarhi512_mask", + "llvm.x86.avx512.mask.permvar.qi.128" => "__builtin_ia32_permvarqi128_mask", + "llvm.x86.avx512.mask.permvar.qi.256" => "__builtin_ia32_permvarqi256_mask", + "llvm.x86.avx512.mask.permvar.qi.512" => "__builtin_ia32_permvarqi512_mask", + "llvm.x86.avx512.mask.permvar.sf.256" => "__builtin_ia32_permvarsf256_mask", + "llvm.x86.avx512.mask.permvar.sf.512" => "__builtin_ia32_permvarsf512_mask", + "llvm.x86.avx512.mask.permvar.si.256" => "__builtin_ia32_permvarsi256_mask", + "llvm.x86.avx512.mask.permvar.si.512" => "__builtin_ia32_permvarsi512_mask", + "llvm.x86.avx512.mask.pmaddubs.w.128" => "__builtin_ia32_pmaddubsw128_mask", + "llvm.x86.avx512.mask.pmaddubs.w.256" => "__builtin_ia32_pmaddubsw256_mask", + "llvm.x86.avx512.mask.pmaddubs.w.512" => "__builtin_ia32_pmaddubsw512_mask", + "llvm.x86.avx512.mask.pmaddw.d.128" => "__builtin_ia32_pmaddwd128_mask", + "llvm.x86.avx512.mask.pmaddw.d.256" => "__builtin_ia32_pmaddwd256_mask", + "llvm.x86.avx512.mask.pmaddw.d.512" => "__builtin_ia32_pmaddwd512_mask", + "llvm.x86.avx512.mask.pmaxs.b.128" => "__builtin_ia32_pmaxsb128_mask", + "llvm.x86.avx512.mask.pmaxs.b.256" => "__builtin_ia32_pmaxsb256_mask", + "llvm.x86.avx512.mask.pmaxs.b.512" => "__builtin_ia32_pmaxsb512_mask", + "llvm.x86.avx512.mask.pmaxs.d.128" => "__builtin_ia32_pmaxsd128_mask", + "llvm.x86.avx512.mask.pmaxs.d.256" => "__builtin_ia32_pmaxsd256_mask", "llvm.x86.avx512.mask.pmaxs.d.512" => "__builtin_ia32_pmaxsd512_mask", + "llvm.x86.avx512.mask.pmaxs.q.128" => "__builtin_ia32_pmaxsq128_mask", + "llvm.x86.avx512.mask.pmaxs.q.256" => "__builtin_ia32_pmaxsq256_mask", "llvm.x86.avx512.mask.pmaxs.q.512" => "__builtin_ia32_pmaxsq512_mask", + "llvm.x86.avx512.mask.pmaxs.w.128" => "__builtin_ia32_pmaxsw128_mask", + "llvm.x86.avx512.mask.pmaxs.w.256" => "__builtin_ia32_pmaxsw256_mask", + "llvm.x86.avx512.mask.pmaxs.w.512" => "__builtin_ia32_pmaxsw512_mask", + "llvm.x86.avx512.mask.pmaxu.b.128" => "__builtin_ia32_pmaxub128_mask", + "llvm.x86.avx512.mask.pmaxu.b.256" => "__builtin_ia32_pmaxub256_mask", + "llvm.x86.avx512.mask.pmaxu.b.512" => "__builtin_ia32_pmaxub512_mask", + "llvm.x86.avx512.mask.pmaxu.d.128" => "__builtin_ia32_pmaxud128_mask", + "llvm.x86.avx512.mask.pmaxu.d.256" => "__builtin_ia32_pmaxud256_mask", "llvm.x86.avx512.mask.pmaxu.d.512" => "__builtin_ia32_pmaxud512_mask", + "llvm.x86.avx512.mask.pmaxu.q.128" => "__builtin_ia32_pmaxuq128_mask", + "llvm.x86.avx512.mask.pmaxu.q.256" => "__builtin_ia32_pmaxuq256_mask", "llvm.x86.avx512.mask.pmaxu.q.512" => "__builtin_ia32_pmaxuq512_mask", + "llvm.x86.avx512.mask.pmaxu.w.128" => "__builtin_ia32_pmaxuw128_mask", + "llvm.x86.avx512.mask.pmaxu.w.256" => "__builtin_ia32_pmaxuw256_mask", + "llvm.x86.avx512.mask.pmaxu.w.512" => "__builtin_ia32_pmaxuw512_mask", + "llvm.x86.avx512.mask.pmins.b.128" => "__builtin_ia32_pminsb128_mask", + "llvm.x86.avx512.mask.pmins.b.256" => "__builtin_ia32_pminsb256_mask", + "llvm.x86.avx512.mask.pmins.b.512" => "__builtin_ia32_pminsb512_mask", + "llvm.x86.avx512.mask.pmins.d.128" => "__builtin_ia32_pminsd128_mask", + "llvm.x86.avx512.mask.pmins.d.256" => "__builtin_ia32_pminsd256_mask", "llvm.x86.avx512.mask.pmins.d.512" => "__builtin_ia32_pminsd512_mask", + "llvm.x86.avx512.mask.pmins.q.128" => "__builtin_ia32_pminsq128_mask", + "llvm.x86.avx512.mask.pmins.q.256" => "__builtin_ia32_pminsq256_mask", "llvm.x86.avx512.mask.pmins.q.512" => "__builtin_ia32_pminsq512_mask", + "llvm.x86.avx512.mask.pmins.w.128" => "__builtin_ia32_pminsw128_mask", + "llvm.x86.avx512.mask.pmins.w.256" => "__builtin_ia32_pminsw256_mask", + "llvm.x86.avx512.mask.pmins.w.512" => "__builtin_ia32_pminsw512_mask", + "llvm.x86.avx512.mask.pminu.b.128" => "__builtin_ia32_pminub128_mask", + "llvm.x86.avx512.mask.pminu.b.256" => "__builtin_ia32_pminub256_mask", + "llvm.x86.avx512.mask.pminu.b.512" => "__builtin_ia32_pminub512_mask", + "llvm.x86.avx512.mask.pminu.d.128" => "__builtin_ia32_pminud128_mask", + "llvm.x86.avx512.mask.pminu.d.256" => "__builtin_ia32_pminud256_mask", "llvm.x86.avx512.mask.pminu.d.512" => "__builtin_ia32_pminud512_mask", + "llvm.x86.avx512.mask.pminu.q.128" => "__builtin_ia32_pminuq128_mask", + "llvm.x86.avx512.mask.pminu.q.256" => "__builtin_ia32_pminuq256_mask", "llvm.x86.avx512.mask.pminu.q.512" => "__builtin_ia32_pminuq512_mask", + "llvm.x86.avx512.mask.pminu.w.128" => "__builtin_ia32_pminuw128_mask", + "llvm.x86.avx512.mask.pminu.w.256" => "__builtin_ia32_pminuw256_mask", + "llvm.x86.avx512.mask.pminu.w.512" => "__builtin_ia32_pminuw512_mask", "llvm.x86.avx512.mask.pmov.db.128" => "__builtin_ia32_pmovdb128_mask", "llvm.x86.avx512.mask.pmov.db.256" => "__builtin_ia32_pmovdb256_mask", + "llvm.x86.avx512.mask.pmov.db.512" => "__builtin_ia32_pmovdb512_mask", "llvm.x86.avx512.mask.pmov.db.mem.128" => "__builtin_ia32_pmovdb128mem_mask", "llvm.x86.avx512.mask.pmov.db.mem.256" => "__builtin_ia32_pmovdb256mem_mask", "llvm.x86.avx512.mask.pmov.db.mem.512" => "__builtin_ia32_pmovdb512mem_mask", "llvm.x86.avx512.mask.pmov.dw.128" => "__builtin_ia32_pmovdw128_mask", "llvm.x86.avx512.mask.pmov.dw.256" => "__builtin_ia32_pmovdw256_mask", + "llvm.x86.avx512.mask.pmov.dw.512" => "__builtin_ia32_pmovdw512_mask", "llvm.x86.avx512.mask.pmov.dw.mem.128" => "__builtin_ia32_pmovdw128mem_mask", "llvm.x86.avx512.mask.pmov.dw.mem.256" => "__builtin_ia32_pmovdw256mem_mask", "llvm.x86.avx512.mask.pmov.dw.mem.512" => "__builtin_ia32_pmovdw512mem_mask", @@ -3233,15 +4229,20 @@ match name { "llvm.x86.avx512.mask.pmov.qb.mem.256" => "__builtin_ia32_pmovqb256mem_mask", "llvm.x86.avx512.mask.pmov.qb.mem.512" => "__builtin_ia32_pmovqb512mem_mask", "llvm.x86.avx512.mask.pmov.qd.128" => "__builtin_ia32_pmovqd128_mask", + "llvm.x86.avx512.mask.pmov.qd.256" => "__builtin_ia32_pmovqd256_mask", + "llvm.x86.avx512.mask.pmov.qd.512" => "__builtin_ia32_pmovqd512_mask", "llvm.x86.avx512.mask.pmov.qd.mem.128" => "__builtin_ia32_pmovqd128mem_mask", "llvm.x86.avx512.mask.pmov.qd.mem.256" => "__builtin_ia32_pmovqd256mem_mask", "llvm.x86.avx512.mask.pmov.qd.mem.512" => "__builtin_ia32_pmovqd512mem_mask", "llvm.x86.avx512.mask.pmov.qw.128" => "__builtin_ia32_pmovqw128_mask", "llvm.x86.avx512.mask.pmov.qw.256" => "__builtin_ia32_pmovqw256_mask", + "llvm.x86.avx512.mask.pmov.qw.512" => "__builtin_ia32_pmovqw512_mask", "llvm.x86.avx512.mask.pmov.qw.mem.128" => "__builtin_ia32_pmovqw128mem_mask", "llvm.x86.avx512.mask.pmov.qw.mem.256" => "__builtin_ia32_pmovqw256mem_mask", "llvm.x86.avx512.mask.pmov.qw.mem.512" => "__builtin_ia32_pmovqw512mem_mask", "llvm.x86.avx512.mask.pmov.wb.128" => "__builtin_ia32_pmovwb128_mask", + "llvm.x86.avx512.mask.pmov.wb.256" => "__builtin_ia32_pmovwb256_mask", + "llvm.x86.avx512.mask.pmov.wb.512" => "__builtin_ia32_pmovwb512_mask", "llvm.x86.avx512.mask.pmov.wb.mem.128" => "__builtin_ia32_pmovwb128mem_mask", "llvm.x86.avx512.mask.pmov.wb.mem.256" => "__builtin_ia32_pmovwb256mem_mask", "llvm.x86.avx512.mask.pmov.wb.mem.512" => "__builtin_ia32_pmovwb512mem_mask", @@ -3281,6 +4282,24 @@ match name { "llvm.x86.avx512.mask.pmovs.wb.mem.128" => "__builtin_ia32_pmovswb128mem_mask", "llvm.x86.avx512.mask.pmovs.wb.mem.256" => "__builtin_ia32_pmovswb256mem_mask", "llvm.x86.avx512.mask.pmovs.wb.mem.512" => "__builtin_ia32_pmovswb512mem_mask", + "llvm.x86.avx512.mask.pmovsxb.d.128" => "__builtin_ia32_pmovsxbd128_mask", + "llvm.x86.avx512.mask.pmovsxb.d.256" => "__builtin_ia32_pmovsxbd256_mask", + "llvm.x86.avx512.mask.pmovsxb.d.512" => "__builtin_ia32_pmovsxbd512_mask", + "llvm.x86.avx512.mask.pmovsxb.q.128" => "__builtin_ia32_pmovsxbq128_mask", + "llvm.x86.avx512.mask.pmovsxb.q.256" => "__builtin_ia32_pmovsxbq256_mask", + "llvm.x86.avx512.mask.pmovsxb.q.512" => "__builtin_ia32_pmovsxbq512_mask", + "llvm.x86.avx512.mask.pmovsxb.w.128" => "__builtin_ia32_pmovsxbw128_mask", + "llvm.x86.avx512.mask.pmovsxb.w.256" => "__builtin_ia32_pmovsxbw256_mask", + "llvm.x86.avx512.mask.pmovsxb.w.512" => "__builtin_ia32_pmovsxbw512_mask", + "llvm.x86.avx512.mask.pmovsxd.q.128" => "__builtin_ia32_pmovsxdq128_mask", + "llvm.x86.avx512.mask.pmovsxd.q.256" => "__builtin_ia32_pmovsxdq256_mask", + "llvm.x86.avx512.mask.pmovsxd.q.512" => "__builtin_ia32_pmovsxdq512_mask", + "llvm.x86.avx512.mask.pmovsxw.d.128" => "__builtin_ia32_pmovsxwd128_mask", + "llvm.x86.avx512.mask.pmovsxw.d.256" => "__builtin_ia32_pmovsxwd256_mask", + "llvm.x86.avx512.mask.pmovsxw.d.512" => "__builtin_ia32_pmovsxwd512_mask", + "llvm.x86.avx512.mask.pmovsxw.q.128" => "__builtin_ia32_pmovsxwq128_mask", + "llvm.x86.avx512.mask.pmovsxw.q.256" => "__builtin_ia32_pmovsxwq256_mask", + "llvm.x86.avx512.mask.pmovsxw.q.512" => "__builtin_ia32_pmovsxwq512_mask", "llvm.x86.avx512.mask.pmovus.db.128" => "__builtin_ia32_pmovusdb128_mask", "llvm.x86.avx512.mask.pmovus.db.256" => "__builtin_ia32_pmovusdb256_mask", "llvm.x86.avx512.mask.pmovus.db.512" => "__builtin_ia32_pmovusdb512_mask", @@ -3317,8 +4336,189 @@ match name { "llvm.x86.avx512.mask.pmovus.wb.mem.128" => "__builtin_ia32_pmovuswb128mem_mask", "llvm.x86.avx512.mask.pmovus.wb.mem.256" => "__builtin_ia32_pmovuswb256mem_mask", "llvm.x86.avx512.mask.pmovus.wb.mem.512" => "__builtin_ia32_pmovuswb512mem_mask", + "llvm.x86.avx512.mask.pmovzxb.d.128" => "__builtin_ia32_pmovzxbd128_mask", + "llvm.x86.avx512.mask.pmovzxb.d.256" => "__builtin_ia32_pmovzxbd256_mask", + "llvm.x86.avx512.mask.pmovzxb.d.512" => "__builtin_ia32_pmovzxbd512_mask", + "llvm.x86.avx512.mask.pmovzxb.q.128" => "__builtin_ia32_pmovzxbq128_mask", + "llvm.x86.avx512.mask.pmovzxb.q.256" => "__builtin_ia32_pmovzxbq256_mask", + "llvm.x86.avx512.mask.pmovzxb.q.512" => "__builtin_ia32_pmovzxbq512_mask", + "llvm.x86.avx512.mask.pmovzxb.w.128" => "__builtin_ia32_pmovzxbw128_mask", + "llvm.x86.avx512.mask.pmovzxb.w.256" => "__builtin_ia32_pmovzxbw256_mask", + "llvm.x86.avx512.mask.pmovzxb.w.512" => "__builtin_ia32_pmovzxbw512_mask", + "llvm.x86.avx512.mask.pmovzxd.q.128" => "__builtin_ia32_pmovzxdq128_mask", + "llvm.x86.avx512.mask.pmovzxd.q.256" => "__builtin_ia32_pmovzxdq256_mask", + "llvm.x86.avx512.mask.pmovzxd.q.512" => "__builtin_ia32_pmovzxdq512_mask", + "llvm.x86.avx512.mask.pmovzxw.d.128" => "__builtin_ia32_pmovzxwd128_mask", + "llvm.x86.avx512.mask.pmovzxw.d.256" => "__builtin_ia32_pmovzxwd256_mask", + "llvm.x86.avx512.mask.pmovzxw.d.512" => "__builtin_ia32_pmovzxwd512_mask", + "llvm.x86.avx512.mask.pmovzxw.q.128" => "__builtin_ia32_pmovzxwq128_mask", + "llvm.x86.avx512.mask.pmovzxw.q.256" => "__builtin_ia32_pmovzxwq256_mask", + "llvm.x86.avx512.mask.pmovzxw.q.512" => "__builtin_ia32_pmovzxwq512_mask", + "llvm.x86.avx512.mask.pmul.dq.128" => "__builtin_ia32_pmuldq128_mask", + "llvm.x86.avx512.mask.pmul.dq.256" => "__builtin_ia32_pmuldq256_mask", "llvm.x86.avx512.mask.pmul.dq.512" => "__builtin_ia32_pmuldq512_mask", + "llvm.x86.avx512.mask.pmul.hr.sw.128" => "__builtin_ia32_pmulhrsw128_mask", + "llvm.x86.avx512.mask.pmul.hr.sw.256" => "__builtin_ia32_pmulhrsw256_mask", + "llvm.x86.avx512.mask.pmul.hr.sw.512" => "__builtin_ia32_pmulhrsw512_mask", + "llvm.x86.avx512.mask.pmulh.w.128" => "__builtin_ia32_pmulhw128_mask", + "llvm.x86.avx512.mask.pmulh.w.256" => "__builtin_ia32_pmulhw256_mask", + "llvm.x86.avx512.mask.pmulh.w.512" => "__builtin_ia32_pmulhw512_mask", + "llvm.x86.avx512.mask.pmulhu.w.128" => "__builtin_ia32_pmulhuw128_mask", + "llvm.x86.avx512.mask.pmulhu.w.256" => "__builtin_ia32_pmulhuw256_mask", + "llvm.x86.avx512.mask.pmulhu.w.512" => "__builtin_ia32_pmulhuw512_mask", + "llvm.x86.avx512.mask.pmull.d.128" => "__builtin_ia32_pmulld128_mask", + "llvm.x86.avx512.mask.pmull.d.256" => "__builtin_ia32_pmulld256_mask", + "llvm.x86.avx512.mask.pmull.d.512" => "__builtin_ia32_pmulld512_mask", + "llvm.x86.avx512.mask.pmull.q.128" => "__builtin_ia32_pmullq128_mask", + "llvm.x86.avx512.mask.pmull.q.256" => "__builtin_ia32_pmullq256_mask", + "llvm.x86.avx512.mask.pmull.q.512" => "__builtin_ia32_pmullq512_mask", + "llvm.x86.avx512.mask.pmull.w.128" => "__builtin_ia32_pmullw128_mask", + "llvm.x86.avx512.mask.pmull.w.256" => "__builtin_ia32_pmullw256_mask", + "llvm.x86.avx512.mask.pmull.w.512" => "__builtin_ia32_pmullw512_mask", + "llvm.x86.avx512.mask.pmultishift.qb.128" => "__builtin_ia32_vpmultishiftqb128_mask", + "llvm.x86.avx512.mask.pmultishift.qb.256" => "__builtin_ia32_vpmultishiftqb256_mask", + "llvm.x86.avx512.mask.pmultishift.qb.512" => "__builtin_ia32_vpmultishiftqb512_mask", + "llvm.x86.avx512.mask.pmulu.dq.128" => "__builtin_ia32_pmuludq128_mask", + "llvm.x86.avx512.mask.pmulu.dq.256" => "__builtin_ia32_pmuludq256_mask", "llvm.x86.avx512.mask.pmulu.dq.512" => "__builtin_ia32_pmuludq512_mask", + "llvm.x86.avx512.mask.prol.d.128" => "__builtin_ia32_prold128_mask", + "llvm.x86.avx512.mask.prol.d.256" => "__builtin_ia32_prold256_mask", + "llvm.x86.avx512.mask.prol.d.512" => "__builtin_ia32_prold512_mask", + "llvm.x86.avx512.mask.prol.q.128" => "__builtin_ia32_prolq128_mask", + "llvm.x86.avx512.mask.prol.q.256" => "__builtin_ia32_prolq256_mask", + "llvm.x86.avx512.mask.prol.q.512" => "__builtin_ia32_prolq512_mask", + "llvm.x86.avx512.mask.prolv.d.128" => "__builtin_ia32_prolvd128_mask", + "llvm.x86.avx512.mask.prolv.d.256" => "__builtin_ia32_prolvd256_mask", + "llvm.x86.avx512.mask.prolv.d.512" => "__builtin_ia32_prolvd512_mask", + "llvm.x86.avx512.mask.prolv.q.128" => "__builtin_ia32_prolvq128_mask", + "llvm.x86.avx512.mask.prolv.q.256" => "__builtin_ia32_prolvq256_mask", + "llvm.x86.avx512.mask.prolv.q.512" => "__builtin_ia32_prolvq512_mask", + "llvm.x86.avx512.mask.pror.d.128" => "__builtin_ia32_prord128_mask", + "llvm.x86.avx512.mask.pror.d.256" => "__builtin_ia32_prord256_mask", + "llvm.x86.avx512.mask.pror.d.512" => "__builtin_ia32_prord512_mask", + "llvm.x86.avx512.mask.pror.q.128" => "__builtin_ia32_prorq128_mask", + "llvm.x86.avx512.mask.pror.q.256" => "__builtin_ia32_prorq256_mask", + "llvm.x86.avx512.mask.pror.q.512" => "__builtin_ia32_prorq512_mask", + "llvm.x86.avx512.mask.prorv.d.128" => "__builtin_ia32_prorvd128_mask", + "llvm.x86.avx512.mask.prorv.d.256" => "__builtin_ia32_prorvd256_mask", + "llvm.x86.avx512.mask.prorv.d.512" => "__builtin_ia32_prorvd512_mask", + "llvm.x86.avx512.mask.prorv.q.128" => "__builtin_ia32_prorvq128_mask", + "llvm.x86.avx512.mask.prorv.q.256" => "__builtin_ia32_prorvq256_mask", + "llvm.x86.avx512.mask.prorv.q.512" => "__builtin_ia32_prorvq512_mask", + "llvm.x86.avx512.mask.pshuf.b.128" => "__builtin_ia32_pshufb128_mask", + "llvm.x86.avx512.mask.pshuf.b.256" => "__builtin_ia32_pshufb256_mask", + "llvm.x86.avx512.mask.pshuf.b.512" => "__builtin_ia32_pshufb512_mask", + "llvm.x86.avx512.mask.psll.d" => "__builtin_ia32_pslld512_mask", + "llvm.x86.avx512.mask.psll.d.128" => "__builtin_ia32_pslld128_mask", + "llvm.x86.avx512.mask.psll.d.256" => "__builtin_ia32_pslld256_mask", + "llvm.x86.avx512.mask.psll.di.128" => "__builtin_ia32_pslldi128_mask", + "llvm.x86.avx512.mask.psll.di.256" => "__builtin_ia32_pslldi256_mask", + "llvm.x86.avx512.mask.psll.di.512" => "__builtin_ia32_pslldi512_mask", + "llvm.x86.avx512.mask.psll.q" => "__builtin_ia32_psllq512_mask", + "llvm.x86.avx512.mask.psll.q.128" => "__builtin_ia32_psllq128_mask", + "llvm.x86.avx512.mask.psll.q.256" => "__builtin_ia32_psllq256_mask", + "llvm.x86.avx512.mask.psll.qi.128" => "__builtin_ia32_psllqi128_mask", + "llvm.x86.avx512.mask.psll.qi.256" => "__builtin_ia32_psllqi256_mask", + "llvm.x86.avx512.mask.psll.qi.512" => "__builtin_ia32_psllqi512_mask", + "llvm.x86.avx512.mask.psll.w.128" => "__builtin_ia32_psllw128_mask", + "llvm.x86.avx512.mask.psll.w.256" => "__builtin_ia32_psllw256_mask", + "llvm.x86.avx512.mask.psll.w.512" => "__builtin_ia32_psllw512_mask", + "llvm.x86.avx512.mask.psll.wi.128" => "__builtin_ia32_psllwi128_mask", + "llvm.x86.avx512.mask.psll.wi.256" => "__builtin_ia32_psllwi256_mask", + "llvm.x86.avx512.mask.psll.wi.512" => "__builtin_ia32_psllwi512_mask", + "llvm.x86.avx512.mask.psllv.d" => "__builtin_ia32_psllv16si_mask", + "llvm.x86.avx512.mask.psllv.q" => "__builtin_ia32_psllv8di_mask", + "llvm.x86.avx512.mask.psllv16.hi" => "__builtin_ia32_psllv16hi_mask", + "llvm.x86.avx512.mask.psllv2.di" => "__builtin_ia32_psllv2di_mask", + "llvm.x86.avx512.mask.psllv32hi" => "__builtin_ia32_psllv32hi_mask", + "llvm.x86.avx512.mask.psllv4.di" => "__builtin_ia32_psllv4di_mask", + "llvm.x86.avx512.mask.psllv4.si" => "__builtin_ia32_psllv4si_mask", + "llvm.x86.avx512.mask.psllv8.hi" => "__builtin_ia32_psllv8hi_mask", + "llvm.x86.avx512.mask.psllv8.si" => "__builtin_ia32_psllv8si_mask", + "llvm.x86.avx512.mask.psra.d" => "__builtin_ia32_psrad512_mask", + "llvm.x86.avx512.mask.psra.d.128" => "__builtin_ia32_psrad128_mask", + "llvm.x86.avx512.mask.psra.d.256" => "__builtin_ia32_psrad256_mask", + "llvm.x86.avx512.mask.psra.di.128" => "__builtin_ia32_psradi128_mask", + "llvm.x86.avx512.mask.psra.di.256" => "__builtin_ia32_psradi256_mask", + "llvm.x86.avx512.mask.psra.di.512" => "__builtin_ia32_psradi512_mask", + "llvm.x86.avx512.mask.psra.q" => "__builtin_ia32_psraq512_mask", + "llvm.x86.avx512.mask.psra.q.128" => "__builtin_ia32_psraq128_mask", + "llvm.x86.avx512.mask.psra.q.256" => "__builtin_ia32_psraq256_mask", + "llvm.x86.avx512.mask.psra.qi.128" => "__builtin_ia32_psraqi128_mask", + "llvm.x86.avx512.mask.psra.qi.256" => "__builtin_ia32_psraqi256_mask", + "llvm.x86.avx512.mask.psra.qi.512" => "__builtin_ia32_psraqi512_mask", + "llvm.x86.avx512.mask.psra.w.128" => "__builtin_ia32_psraw128_mask", + "llvm.x86.avx512.mask.psra.w.256" => "__builtin_ia32_psraw256_mask", + "llvm.x86.avx512.mask.psra.w.512" => "__builtin_ia32_psraw512_mask", + "llvm.x86.avx512.mask.psra.wi.128" => "__builtin_ia32_psrawi128_mask", + "llvm.x86.avx512.mask.psra.wi.256" => "__builtin_ia32_psrawi256_mask", + "llvm.x86.avx512.mask.psra.wi.512" => "__builtin_ia32_psrawi512_mask", + "llvm.x86.avx512.mask.psrav.d" => "__builtin_ia32_psrav16si_mask", + "llvm.x86.avx512.mask.psrav.q" => "__builtin_ia32_psrav8di_mask", + "llvm.x86.avx512.mask.psrav.q.128" => "__builtin_ia32_psravq128_mask", + "llvm.x86.avx512.mask.psrav.q.256" => "__builtin_ia32_psravq256_mask", + "llvm.x86.avx512.mask.psrav16.hi" => "__builtin_ia32_psrav16hi_mask", + "llvm.x86.avx512.mask.psrav32.hi" => "__builtin_ia32_psrav32hi_mask", + "llvm.x86.avx512.mask.psrav4.si" => "__builtin_ia32_psrav4si_mask", + "llvm.x86.avx512.mask.psrav8.hi" => "__builtin_ia32_psrav8hi_mask", + "llvm.x86.avx512.mask.psrav8.si" => "__builtin_ia32_psrav8si_mask", + "llvm.x86.avx512.mask.psrl.d" => "__builtin_ia32_psrld512_mask", + "llvm.x86.avx512.mask.psrl.d.128" => "__builtin_ia32_psrld128_mask", + "llvm.x86.avx512.mask.psrl.d.256" => "__builtin_ia32_psrld256_mask", + "llvm.x86.avx512.mask.psrl.di.128" => "__builtin_ia32_psrldi128_mask", + "llvm.x86.avx512.mask.psrl.di.256" => "__builtin_ia32_psrldi256_mask", + "llvm.x86.avx512.mask.psrl.di.512" => "__builtin_ia32_psrldi512_mask", + "llvm.x86.avx512.mask.psrl.q" => "__builtin_ia32_psrlq512_mask", + "llvm.x86.avx512.mask.psrl.q.128" => "__builtin_ia32_psrlq128_mask", + "llvm.x86.avx512.mask.psrl.q.256" => "__builtin_ia32_psrlq256_mask", + "llvm.x86.avx512.mask.psrl.qi.128" => "__builtin_ia32_psrlqi128_mask", + "llvm.x86.avx512.mask.psrl.qi.256" => "__builtin_ia32_psrlqi256_mask", + "llvm.x86.avx512.mask.psrl.qi.512" => "__builtin_ia32_psrlqi512_mask", + "llvm.x86.avx512.mask.psrl.w.128" => "__builtin_ia32_psrlw128_mask", + "llvm.x86.avx512.mask.psrl.w.256" => "__builtin_ia32_psrlw256_mask", + "llvm.x86.avx512.mask.psrl.w.512" => "__builtin_ia32_psrlw512_mask", + "llvm.x86.avx512.mask.psrl.wi.128" => "__builtin_ia32_psrlwi128_mask", + "llvm.x86.avx512.mask.psrl.wi.256" => "__builtin_ia32_psrlwi256_mask", + "llvm.x86.avx512.mask.psrl.wi.512" => "__builtin_ia32_psrlwi512_mask", + "llvm.x86.avx512.mask.psrlv.d" => "__builtin_ia32_psrlv16si_mask", + "llvm.x86.avx512.mask.psrlv.q" => "__builtin_ia32_psrlv8di_mask", + "llvm.x86.avx512.mask.psrlv16.hi" => "__builtin_ia32_psrlv16hi_mask", + "llvm.x86.avx512.mask.psrlv2.di" => "__builtin_ia32_psrlv2di_mask", + "llvm.x86.avx512.mask.psrlv32hi" => "__builtin_ia32_psrlv32hi_mask", + "llvm.x86.avx512.mask.psrlv4.di" => "__builtin_ia32_psrlv4di_mask", + "llvm.x86.avx512.mask.psrlv4.si" => "__builtin_ia32_psrlv4si_mask", + "llvm.x86.avx512.mask.psrlv8.hi" => "__builtin_ia32_psrlv8hi_mask", + "llvm.x86.avx512.mask.psrlv8.si" => "__builtin_ia32_psrlv8si_mask", + "llvm.x86.avx512.mask.psub.b.128" => "__builtin_ia32_psubb128_mask", + "llvm.x86.avx512.mask.psub.b.256" => "__builtin_ia32_psubb256_mask", + "llvm.x86.avx512.mask.psub.b.512" => "__builtin_ia32_psubb512_mask", + "llvm.x86.avx512.mask.psub.d.128" => "__builtin_ia32_psubd128_mask", + "llvm.x86.avx512.mask.psub.d.256" => "__builtin_ia32_psubd256_mask", + "llvm.x86.avx512.mask.psub.d.512" => "__builtin_ia32_psubd512_mask", + "llvm.x86.avx512.mask.psub.q.128" => "__builtin_ia32_psubq128_mask", + "llvm.x86.avx512.mask.psub.q.256" => "__builtin_ia32_psubq256_mask", + "llvm.x86.avx512.mask.psub.q.512" => "__builtin_ia32_psubq512_mask", + "llvm.x86.avx512.mask.psub.w.128" => "__builtin_ia32_psubw128_mask", + "llvm.x86.avx512.mask.psub.w.256" => "__builtin_ia32_psubw256_mask", + "llvm.x86.avx512.mask.psub.w.512" => "__builtin_ia32_psubw512_mask", + "llvm.x86.avx512.mask.psubs.b.128" => "__builtin_ia32_psubsb128_mask", + "llvm.x86.avx512.mask.psubs.b.256" => "__builtin_ia32_psubsb256_mask", + "llvm.x86.avx512.mask.psubs.b.512" => "__builtin_ia32_psubsb512_mask", + "llvm.x86.avx512.mask.psubs.w.128" => "__builtin_ia32_psubsw128_mask", + "llvm.x86.avx512.mask.psubs.w.256" => "__builtin_ia32_psubsw256_mask", + "llvm.x86.avx512.mask.psubs.w.512" => "__builtin_ia32_psubsw512_mask", + "llvm.x86.avx512.mask.psubus.b.128" => "__builtin_ia32_psubusb128_mask", + "llvm.x86.avx512.mask.psubus.b.256" => "__builtin_ia32_psubusb256_mask", + "llvm.x86.avx512.mask.psubus.b.512" => "__builtin_ia32_psubusb512_mask", + "llvm.x86.avx512.mask.psubus.w.128" => "__builtin_ia32_psubusw128_mask", + "llvm.x86.avx512.mask.psubus.w.256" => "__builtin_ia32_psubusw256_mask", + "llvm.x86.avx512.mask.psubus.w.512" => "__builtin_ia32_psubusw512_mask", + "llvm.x86.avx512.mask.pternlog.d.128" => "__builtin_ia32_pternlogd128_mask", + "llvm.x86.avx512.mask.pternlog.d.256" => "__builtin_ia32_pternlogd256_mask", + "llvm.x86.avx512.mask.pternlog.d.512" => "__builtin_ia32_pternlogd512_mask", + "llvm.x86.avx512.mask.pternlog.q.128" => "__builtin_ia32_pternlogq128_mask", + "llvm.x86.avx512.mask.pternlog.q.256" => "__builtin_ia32_pternlogq256_mask", + "llvm.x86.avx512.mask.pternlog.q.512" => "__builtin_ia32_pternlogq512_mask", "llvm.x86.avx512.mask.ptestm.d.512" => "__builtin_ia32_ptestmd512", "llvm.x86.avx512.mask.ptestm.q.512" => "__builtin_ia32_ptestmq512", "llvm.x86.avx512.mask.range.pd.128" => "__builtin_ia32_rangepd128_mask", @@ -3353,23 +4553,181 @@ match name { "llvm.x86.avx512.mask.scalef.ps.512" => "__builtin_ia32_scalefps512_mask", "llvm.x86.avx512.mask.scalef.sd" => "__builtin_ia32_scalefsd_round_mask", "llvm.x86.avx512.mask.scalef.ss" => "__builtin_ia32_scalefss_round_mask", + "llvm.x86.avx512.mask.shuf.f32x4" => "__builtin_ia32_shuf_f32x4_mask", + "llvm.x86.avx512.mask.shuf.f32x4.256" => "__builtin_ia32_shuf_f32x4_256_mask", + "llvm.x86.avx512.mask.shuf.f64x2" => "__builtin_ia32_shuf_f64x2_mask", + "llvm.x86.avx512.mask.shuf.f64x2.256" => "__builtin_ia32_shuf_f64x2_256_mask", + "llvm.x86.avx512.mask.shuf.i32x4" => "__builtin_ia32_shuf_i32x4_mask", + "llvm.x86.avx512.mask.shuf.i32x4.256" => "__builtin_ia32_shuf_i32x4_256_mask", + "llvm.x86.avx512.mask.shuf.i64x2" => "__builtin_ia32_shuf_i64x2_mask", + "llvm.x86.avx512.mask.shuf.i64x2.256" => "__builtin_ia32_shuf_i64x2_256_mask", + "llvm.x86.avx512.mask.shuf.pd.128" => "__builtin_ia32_shufpd128_mask", + "llvm.x86.avx512.mask.shuf.pd.256" => "__builtin_ia32_shufpd256_mask", + "llvm.x86.avx512.mask.shuf.pd.512" => "__builtin_ia32_shufpd512_mask", + "llvm.x86.avx512.mask.shuf.ps.128" => "__builtin_ia32_shufps128_mask", + "llvm.x86.avx512.mask.shuf.ps.256" => "__builtin_ia32_shufps256_mask", + "llvm.x86.avx512.mask.shuf.ps.512" => "__builtin_ia32_shufps512_mask", + "llvm.x86.avx512.mask.sqrt.pd.128" => "__builtin_ia32_sqrtpd128_mask", + "llvm.x86.avx512.mask.sqrt.pd.256" => "__builtin_ia32_sqrtpd256_mask", + "llvm.x86.avx512.mask.sqrt.pd.512" => "__builtin_ia32_sqrtpd512_mask", + "llvm.x86.avx512.mask.sqrt.ps.128" => "__builtin_ia32_sqrtps128_mask", + "llvm.x86.avx512.mask.sqrt.ps.256" => "__builtin_ia32_sqrtps256_mask", + "llvm.x86.avx512.mask.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask", + "llvm.x86.avx512.mask.sqrt.sd" => "__builtin_ia32_sqrtsd_round_mask", + "llvm.x86.avx512.mask.sqrt.ss" => "__builtin_ia32_sqrtss_round_mask", "llvm.x86.avx512.mask.store.ss" => "__builtin_ia32_storess_mask", "llvm.x86.avx512.mask.storeu.d.512" => "__builtin_ia32_storedqusi512_mask", "llvm.x86.avx512.mask.storeu.pd.512" => "__builtin_ia32_storeupd512_mask", "llvm.x86.avx512.mask.storeu.ps.512" => "__builtin_ia32_storeups512_mask", "llvm.x86.avx512.mask.storeu.q.512" => "__builtin_ia32_storedqudi512_mask", + "llvm.x86.avx512.mask.sub.pd.128" => "__builtin_ia32_subpd128_mask", + "llvm.x86.avx512.mask.sub.pd.256" => "__builtin_ia32_subpd256_mask", + "llvm.x86.avx512.mask.sub.pd.512" => "__builtin_ia32_subpd512_mask", + "llvm.x86.avx512.mask.sub.ps.128" => "__builtin_ia32_subps128_mask", + "llvm.x86.avx512.mask.sub.ps.256" => "__builtin_ia32_subps256_mask", + "llvm.x86.avx512.mask.sub.ps.512" => "__builtin_ia32_subps512_mask", "llvm.x86.avx512.mask.sub.sd.round" => "__builtin_ia32_subsd_round_mask", "llvm.x86.avx512.mask.sub.ss.round" => "__builtin_ia32_subss_round_mask", + "llvm.x86.avx512.mask.valign.d.128" => "__builtin_ia32_alignd128_mask", + "llvm.x86.avx512.mask.valign.d.256" => "__builtin_ia32_alignd256_mask", "llvm.x86.avx512.mask.valign.d.512" => "__builtin_ia32_alignd512_mask", + "llvm.x86.avx512.mask.valign.q.128" => "__builtin_ia32_alignq128_mask", + "llvm.x86.avx512.mask.valign.q.256" => "__builtin_ia32_alignq256_mask", "llvm.x86.avx512.mask.valign.q.512" => "__builtin_ia32_alignq512_mask", + "llvm.x86.avx512.mask.vcvtph2ps.128" => "__builtin_ia32_vcvtph2ps_mask", + "llvm.x86.avx512.mask.vcvtph2ps.256" => "__builtin_ia32_vcvtph2ps256_mask", "llvm.x86.avx512.mask.vcvtph2ps.512" => "__builtin_ia32_vcvtph2ps512_mask", "llvm.x86.avx512.mask.vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph_mask", "llvm.x86.avx512.mask.vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256_mask", "llvm.x86.avx512.mask.vcvtps2ph.512" => "__builtin_ia32_vcvtps2ph512_mask", + "llvm.x86.avx512.mask.vextractf32x4.256" => "__builtin_ia32_extractf32x4_256_mask", + "llvm.x86.avx512.mask.vextractf32x4.512" => "__builtin_ia32_extractf32x4_mask", + "llvm.x86.avx512.mask.vextractf32x8.512" => "__builtin_ia32_extractf32x8_mask", + "llvm.x86.avx512.mask.vextractf64x2.256" => "__builtin_ia32_extractf64x2_256_mask", + "llvm.x86.avx512.mask.vextractf64x2.512" => "__builtin_ia32_extractf64x2_512_mask", + "llvm.x86.avx512.mask.vextractf64x4.512" => "__builtin_ia32_extractf64x4_mask", + "llvm.x86.avx512.mask.vextracti32x4.256" => "__builtin_ia32_extracti32x4_256_mask", + "llvm.x86.avx512.mask.vextracti32x4.512" => "__builtin_ia32_extracti32x4_mask", + "llvm.x86.avx512.mask.vextracti32x8.512" => "__builtin_ia32_extracti32x8_mask", + "llvm.x86.avx512.mask.vextracti64x2.256" => "__builtin_ia32_extracti64x2_256_mask", + "llvm.x86.avx512.mask.vextracti64x2.512" => "__builtin_ia32_extracti64x2_512_mask", + "llvm.x86.avx512.mask.vextracti64x4.512" => "__builtin_ia32_extracti64x4_mask", + "llvm.x86.avx512.mask.vfmadd.pd.128" => "__builtin_ia32_vfmaddpd128_mask", + "llvm.x86.avx512.mask.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256_mask", + "llvm.x86.avx512.mask.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask", + "llvm.x86.avx512.mask.vfmadd.ps.128" => "__builtin_ia32_vfmaddps128_mask", + "llvm.x86.avx512.mask.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256_mask", + "llvm.x86.avx512.mask.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask", + "llvm.x86.avx512.mask.vfmadd.sd" => "__builtin_ia32_vfmaddsd3_mask", + "llvm.x86.avx512.mask.vfmadd.ss" => "__builtin_ia32_vfmaddss3_mask", + "llvm.x86.avx512.mask.vfmaddsub.pd.128" => "__builtin_ia32_vfmaddsubpd128_mask", + "llvm.x86.avx512.mask.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256_mask", + "llvm.x86.avx512.mask.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask", + "llvm.x86.avx512.mask.vfmaddsub.ps.128" => "__builtin_ia32_vfmaddsubps128_mask", + "llvm.x86.avx512.mask.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256_mask", + "llvm.x86.avx512.mask.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask", + "llvm.x86.avx512.mask.vfnmadd.pd.128" => "__builtin_ia32_vfnmaddpd128_mask", + "llvm.x86.avx512.mask.vfnmadd.pd.256" => "__builtin_ia32_vfnmaddpd256_mask", + "llvm.x86.avx512.mask.vfnmadd.pd.512" => "__builtin_ia32_vfnmaddpd512_mask", + "llvm.x86.avx512.mask.vfnmadd.ps.128" => "__builtin_ia32_vfnmaddps128_mask", + "llvm.x86.avx512.mask.vfnmadd.ps.256" => "__builtin_ia32_vfnmaddps256_mask", + "llvm.x86.avx512.mask.vfnmadd.ps.512" => "__builtin_ia32_vfnmaddps512_mask", + "llvm.x86.avx512.mask.vfnmsub.pd.128" => "__builtin_ia32_vfnmsubpd128_mask", + "llvm.x86.avx512.mask.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256_mask", + "llvm.x86.avx512.mask.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask", + "llvm.x86.avx512.mask.vfnmsub.ps.128" => "__builtin_ia32_vfnmsubps128_mask", + "llvm.x86.avx512.mask.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256_mask", + "llvm.x86.avx512.mask.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask", + "llvm.x86.avx512.mask.vpermi2var.d.128" => "__builtin_ia32_vpermi2vard128_mask", + "llvm.x86.avx512.mask.vpermi2var.d.256" => "__builtin_ia32_vpermi2vard256_mask", + "llvm.x86.avx512.mask.vpermi2var.d.512" => "__builtin_ia32_vpermi2vard512_mask", + "llvm.x86.avx512.mask.vpermi2var.hi.128" => "__builtin_ia32_vpermi2varhi128_mask", + "llvm.x86.avx512.mask.vpermi2var.hi.256" => "__builtin_ia32_vpermi2varhi256_mask", + "llvm.x86.avx512.mask.vpermi2var.hi.512" => "__builtin_ia32_vpermi2varhi512_mask", + "llvm.x86.avx512.mask.vpermi2var.pd.128" => "__builtin_ia32_vpermi2varpd128_mask", + "llvm.x86.avx512.mask.vpermi2var.pd.256" => "__builtin_ia32_vpermi2varpd256_mask", + "llvm.x86.avx512.mask.vpermi2var.pd.512" => "__builtin_ia32_vpermi2varpd512_mask", + "llvm.x86.avx512.mask.vpermi2var.ps.128" => "__builtin_ia32_vpermi2varps128_mask", + "llvm.x86.avx512.mask.vpermi2var.ps.256" => "__builtin_ia32_vpermi2varps256_mask", + "llvm.x86.avx512.mask.vpermi2var.ps.512" => "__builtin_ia32_vpermi2varps512_mask", + "llvm.x86.avx512.mask.vpermi2var.q.128" => "__builtin_ia32_vpermi2varq128_mask", + "llvm.x86.avx512.mask.vpermi2var.q.256" => "__builtin_ia32_vpermi2varq256_mask", + "llvm.x86.avx512.mask.vpermi2var.q.512" => "__builtin_ia32_vpermi2varq512_mask", + "llvm.x86.avx512.mask.vpermi2var.qi.128" => "__builtin_ia32_vpermi2varqi128_mask", + "llvm.x86.avx512.mask.vpermi2var.qi.256" => "__builtin_ia32_vpermi2varqi256_mask", + "llvm.x86.avx512.mask.vpermi2var.qi.512" => "__builtin_ia32_vpermi2varqi512_mask", + "llvm.x86.avx512.mask.vpermilvar.pd.128" => "__builtin_ia32_vpermilvarpd_mask", + "llvm.x86.avx512.mask.vpermilvar.pd.256" => "__builtin_ia32_vpermilvarpd256_mask", + "llvm.x86.avx512.mask.vpermilvar.pd.512" => "__builtin_ia32_vpermilvarpd512_mask", + "llvm.x86.avx512.mask.vpermilvar.ps.128" => "__builtin_ia32_vpermilvarps_mask", + "llvm.x86.avx512.mask.vpermilvar.ps.256" => "__builtin_ia32_vpermilvarps256_mask", + "llvm.x86.avx512.mask.vpermilvar.ps.512" => "__builtin_ia32_vpermilvarps512_mask", "llvm.x86.avx512.mask.vpermt.d.512" => "__builtin_ia32_vpermt2vard512_mask", "llvm.x86.avx512.mask.vpermt.pd.512" => "__builtin_ia32_vpermt2varpd512_mask", "llvm.x86.avx512.mask.vpermt.ps.512" => "__builtin_ia32_vpermt2varps512_mask", "llvm.x86.avx512.mask.vpermt.q.512" => "__builtin_ia32_vpermt2varq512_mask", + "llvm.x86.avx512.mask.vpermt2var.d.128" => "__builtin_ia32_vpermt2vard128_mask", + "llvm.x86.avx512.mask.vpermt2var.d.256" => "__builtin_ia32_vpermt2vard256_mask", + "llvm.x86.avx512.mask.vpermt2var.d.512" => "__builtin_ia32_vpermt2vard512_mask", + "llvm.x86.avx512.mask.vpermt2var.hi.128" => "__builtin_ia32_vpermt2varhi128_mask", + "llvm.x86.avx512.mask.vpermt2var.hi.256" => "__builtin_ia32_vpermt2varhi256_mask", + "llvm.x86.avx512.mask.vpermt2var.hi.512" => "__builtin_ia32_vpermt2varhi512_mask", + "llvm.x86.avx512.mask.vpermt2var.pd.128" => "__builtin_ia32_vpermt2varpd128_mask", + "llvm.x86.avx512.mask.vpermt2var.pd.256" => "__builtin_ia32_vpermt2varpd256_mask", + "llvm.x86.avx512.mask.vpermt2var.pd.512" => "__builtin_ia32_vpermt2varpd512_mask", + "llvm.x86.avx512.mask.vpermt2var.ps.128" => "__builtin_ia32_vpermt2varps128_mask", + "llvm.x86.avx512.mask.vpermt2var.ps.256" => "__builtin_ia32_vpermt2varps256_mask", + "llvm.x86.avx512.mask.vpermt2var.ps.512" => "__builtin_ia32_vpermt2varps512_mask", + "llvm.x86.avx512.mask.vpermt2var.q.128" => "__builtin_ia32_vpermt2varq128_mask", + "llvm.x86.avx512.mask.vpermt2var.q.256" => "__builtin_ia32_vpermt2varq256_mask", + "llvm.x86.avx512.mask.vpermt2var.q.512" => "__builtin_ia32_vpermt2varq512_mask", + "llvm.x86.avx512.mask.vpermt2var.qi.128" => "__builtin_ia32_vpermt2varqi128_mask", + "llvm.x86.avx512.mask.vpermt2var.qi.256" => "__builtin_ia32_vpermt2varqi256_mask", + "llvm.x86.avx512.mask.vpermt2var.qi.512" => "__builtin_ia32_vpermt2varqi512_mask", + "llvm.x86.avx512.mask.vpmadd52h.uq.128" => "__builtin_ia32_vpmadd52huq128_mask", + "llvm.x86.avx512.mask.vpmadd52h.uq.256" => "__builtin_ia32_vpmadd52huq256_mask", + "llvm.x86.avx512.mask.vpmadd52h.uq.512" => "__builtin_ia32_vpmadd52huq512_mask", + "llvm.x86.avx512.mask.vpmadd52l.uq.128" => "__builtin_ia32_vpmadd52luq128_mask", + "llvm.x86.avx512.mask.vpmadd52l.uq.256" => "__builtin_ia32_vpmadd52luq256_mask", + "llvm.x86.avx512.mask.vpmadd52l.uq.512" => "__builtin_ia32_vpmadd52luq512_mask", + "llvm.x86.avx512.mask.xor.pd.128" => "__builtin_ia32_xorpd128_mask", + "llvm.x86.avx512.mask.xor.pd.256" => "__builtin_ia32_xorpd256_mask", + "llvm.x86.avx512.mask.xor.pd.512" => "__builtin_ia32_xorpd512_mask", + "llvm.x86.avx512.mask.xor.ps.128" => "__builtin_ia32_xorps128_mask", + "llvm.x86.avx512.mask.xor.ps.256" => "__builtin_ia32_xorps256_mask", + "llvm.x86.avx512.mask.xor.ps.512" => "__builtin_ia32_xorps512_mask", + "llvm.x86.avx512.mask3.vfmadd.pd.128" => "__builtin_ia32_vfmaddpd128_mask3", + "llvm.x86.avx512.mask3.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256_mask3", + "llvm.x86.avx512.mask3.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask3", + "llvm.x86.avx512.mask3.vfmadd.ps.128" => "__builtin_ia32_vfmaddps128_mask3", + "llvm.x86.avx512.mask3.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256_mask3", + "llvm.x86.avx512.mask3.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask3", + "llvm.x86.avx512.mask3.vfmadd.sd" => "__builtin_ia32_vfmaddsd3_mask3", + "llvm.x86.avx512.mask3.vfmadd.ss" => "__builtin_ia32_vfmaddss3_mask3", + "llvm.x86.avx512.mask3.vfmaddsub.pd.128" => "__builtin_ia32_vfmaddsubpd128_mask3", + "llvm.x86.avx512.mask3.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256_mask3", + "llvm.x86.avx512.mask3.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask3", + "llvm.x86.avx512.mask3.vfmaddsub.ps.128" => "__builtin_ia32_vfmaddsubps128_mask3", + "llvm.x86.avx512.mask3.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256_mask3", + "llvm.x86.avx512.mask3.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask3", + "llvm.x86.avx512.mask3.vfmsub.pd.128" => "__builtin_ia32_vfmsubpd128_mask3", + "llvm.x86.avx512.mask3.vfmsub.pd.256" => "__builtin_ia32_vfmsubpd256_mask3", + "llvm.x86.avx512.mask3.vfmsub.pd.512" => "__builtin_ia32_vfmsubpd512_mask3", + "llvm.x86.avx512.mask3.vfmsub.ps.128" => "__builtin_ia32_vfmsubps128_mask3", + "llvm.x86.avx512.mask3.vfmsub.ps.256" => "__builtin_ia32_vfmsubps256_mask3", + "llvm.x86.avx512.mask3.vfmsub.ps.512" => "__builtin_ia32_vfmsubps512_mask3", + "llvm.x86.avx512.mask3.vfmsubadd.pd.128" => "__builtin_ia32_vfmsubaddpd128_mask3", + "llvm.x86.avx512.mask3.vfmsubadd.pd.256" => "__builtin_ia32_vfmsubaddpd256_mask3", + "llvm.x86.avx512.mask3.vfmsubadd.pd.512" => "__builtin_ia32_vfmsubaddpd512_mask3", + "llvm.x86.avx512.mask3.vfmsubadd.ps.128" => "__builtin_ia32_vfmsubaddps128_mask3", + "llvm.x86.avx512.mask3.vfmsubadd.ps.256" => "__builtin_ia32_vfmsubaddps256_mask3", + "llvm.x86.avx512.mask3.vfmsubadd.ps.512" => "__builtin_ia32_vfmsubaddps512_mask3", + "llvm.x86.avx512.mask3.vfnmsub.pd.128" => "__builtin_ia32_vfnmsubpd128_mask3", + "llvm.x86.avx512.mask3.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256_mask3", + "llvm.x86.avx512.mask3.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask3", + "llvm.x86.avx512.mask3.vfnmsub.ps.128" => "__builtin_ia32_vfnmsubps128_mask3", + "llvm.x86.avx512.mask3.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256_mask3", + "llvm.x86.avx512.mask3.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask3", "llvm.x86.avx512.maskz.fixupimm.pd.128" => "__builtin_ia32_fixupimmpd128_maskz", "llvm.x86.avx512.maskz.fixupimm.pd.256" => "__builtin_ia32_fixupimmpd256_maskz", "llvm.x86.avx512.maskz.fixupimm.pd.512" => "__builtin_ia32_fixupimmpd512_maskz", @@ -3378,6 +4736,50 @@ match name { "llvm.x86.avx512.maskz.fixupimm.ps.512" => "__builtin_ia32_fixupimmps512_maskz", "llvm.x86.avx512.maskz.fixupimm.sd" => "__builtin_ia32_fixupimmsd_maskz", "llvm.x86.avx512.maskz.fixupimm.ss" => "__builtin_ia32_fixupimmss_maskz", + "llvm.x86.avx512.maskz.pternlog.d.128" => "__builtin_ia32_pternlogd128_maskz", + "llvm.x86.avx512.maskz.pternlog.d.256" => "__builtin_ia32_pternlogd256_maskz", + "llvm.x86.avx512.maskz.pternlog.d.512" => "__builtin_ia32_pternlogd512_maskz", + "llvm.x86.avx512.maskz.pternlog.q.128" => "__builtin_ia32_pternlogq128_maskz", + "llvm.x86.avx512.maskz.pternlog.q.256" => "__builtin_ia32_pternlogq256_maskz", + "llvm.x86.avx512.maskz.pternlog.q.512" => "__builtin_ia32_pternlogq512_maskz", + "llvm.x86.avx512.maskz.vfmadd.pd.128" => "__builtin_ia32_vfmaddpd128_maskz", + "llvm.x86.avx512.maskz.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256_maskz", + "llvm.x86.avx512.maskz.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_maskz", + "llvm.x86.avx512.maskz.vfmadd.ps.128" => "__builtin_ia32_vfmaddps128_maskz", + "llvm.x86.avx512.maskz.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256_maskz", + "llvm.x86.avx512.maskz.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_maskz", + "llvm.x86.avx512.maskz.vfmadd.sd" => "__builtin_ia32_vfmaddsd3_maskz", + "llvm.x86.avx512.maskz.vfmadd.ss" => "__builtin_ia32_vfmaddss3_maskz", + "llvm.x86.avx512.maskz.vfmaddsub.pd.128" => "__builtin_ia32_vfmaddsubpd128_maskz", + "llvm.x86.avx512.maskz.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256_maskz", + "llvm.x86.avx512.maskz.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_maskz", + "llvm.x86.avx512.maskz.vfmaddsub.ps.128" => "__builtin_ia32_vfmaddsubps128_maskz", + "llvm.x86.avx512.maskz.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256_maskz", + "llvm.x86.avx512.maskz.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_maskz", + "llvm.x86.avx512.maskz.vpermt2var.d.128" => "__builtin_ia32_vpermt2vard128_maskz", + "llvm.x86.avx512.maskz.vpermt2var.d.256" => "__builtin_ia32_vpermt2vard256_maskz", + "llvm.x86.avx512.maskz.vpermt2var.d.512" => "__builtin_ia32_vpermt2vard512_maskz", + "llvm.x86.avx512.maskz.vpermt2var.hi.128" => "__builtin_ia32_vpermt2varhi128_maskz", + "llvm.x86.avx512.maskz.vpermt2var.hi.256" => "__builtin_ia32_vpermt2varhi256_maskz", + "llvm.x86.avx512.maskz.vpermt2var.hi.512" => "__builtin_ia32_vpermt2varhi512_maskz", + "llvm.x86.avx512.maskz.vpermt2var.pd.128" => "__builtin_ia32_vpermt2varpd128_maskz", + "llvm.x86.avx512.maskz.vpermt2var.pd.256" => "__builtin_ia32_vpermt2varpd256_maskz", + "llvm.x86.avx512.maskz.vpermt2var.pd.512" => "__builtin_ia32_vpermt2varpd512_maskz", + "llvm.x86.avx512.maskz.vpermt2var.ps.128" => "__builtin_ia32_vpermt2varps128_maskz", + "llvm.x86.avx512.maskz.vpermt2var.ps.256" => "__builtin_ia32_vpermt2varps256_maskz", + "llvm.x86.avx512.maskz.vpermt2var.ps.512" => "__builtin_ia32_vpermt2varps512_maskz", + "llvm.x86.avx512.maskz.vpermt2var.q.128" => "__builtin_ia32_vpermt2varq128_maskz", + "llvm.x86.avx512.maskz.vpermt2var.q.256" => "__builtin_ia32_vpermt2varq256_maskz", + "llvm.x86.avx512.maskz.vpermt2var.q.512" => "__builtin_ia32_vpermt2varq512_maskz", + "llvm.x86.avx512.maskz.vpermt2var.qi.128" => "__builtin_ia32_vpermt2varqi128_maskz", + "llvm.x86.avx512.maskz.vpermt2var.qi.256" => "__builtin_ia32_vpermt2varqi256_maskz", + "llvm.x86.avx512.maskz.vpermt2var.qi.512" => "__builtin_ia32_vpermt2varqi512_maskz", + "llvm.x86.avx512.maskz.vpmadd52h.uq.128" => "__builtin_ia32_vpmadd52huq128_maskz", + "llvm.x86.avx512.maskz.vpmadd52h.uq.256" => "__builtin_ia32_vpmadd52huq256_maskz", + "llvm.x86.avx512.maskz.vpmadd52h.uq.512" => "__builtin_ia32_vpmadd52huq512_maskz", + "llvm.x86.avx512.maskz.vpmadd52l.uq.128" => "__builtin_ia32_vpmadd52luq128_maskz", + "llvm.x86.avx512.maskz.vpmadd52l.uq.256" => "__builtin_ia32_vpmadd52luq256_maskz", + "llvm.x86.avx512.maskz.vpmadd52l.uq.512" => "__builtin_ia32_vpmadd52luq512_maskz", "llvm.x86.avx512.max.pd.512" => "__builtin_ia32_maxpd512", "llvm.x86.avx512.max.ps.512" => "__builtin_ia32_maxps512", "llvm.x86.avx512.min.pd.512" => "__builtin_ia32_minpd512", @@ -3469,6 +4871,30 @@ match name { "llvm.x86.avx512.pternlog.q.128" => "__builtin_ia32_pternlogq128", "llvm.x86.avx512.pternlog.q.256" => "__builtin_ia32_pternlogq256", "llvm.x86.avx512.pternlog.q.512" => "__builtin_ia32_pternlogq512", + "llvm.x86.avx512.ptestm.b.128" => "__builtin_ia32_ptestmb128", + "llvm.x86.avx512.ptestm.b.256" => "__builtin_ia32_ptestmb256", + "llvm.x86.avx512.ptestm.b.512" => "__builtin_ia32_ptestmb512", + "llvm.x86.avx512.ptestm.d.128" => "__builtin_ia32_ptestmd128", + "llvm.x86.avx512.ptestm.d.256" => "__builtin_ia32_ptestmd256", + "llvm.x86.avx512.ptestm.d.512" => "__builtin_ia32_ptestmd512", + "llvm.x86.avx512.ptestm.q.128" => "__builtin_ia32_ptestmq128", + "llvm.x86.avx512.ptestm.q.256" => "__builtin_ia32_ptestmq256", + "llvm.x86.avx512.ptestm.q.512" => "__builtin_ia32_ptestmq512", + "llvm.x86.avx512.ptestm.w.128" => "__builtin_ia32_ptestmw128", + "llvm.x86.avx512.ptestm.w.256" => "__builtin_ia32_ptestmw256", + "llvm.x86.avx512.ptestm.w.512" => "__builtin_ia32_ptestmw512", + "llvm.x86.avx512.ptestnm.b.128" => "__builtin_ia32_ptestnmb128", + "llvm.x86.avx512.ptestnm.b.256" => "__builtin_ia32_ptestnmb256", + "llvm.x86.avx512.ptestnm.b.512" => "__builtin_ia32_ptestnmb512", + "llvm.x86.avx512.ptestnm.d.128" => "__builtin_ia32_ptestnmd128", + "llvm.x86.avx512.ptestnm.d.256" => "__builtin_ia32_ptestnmd256", + "llvm.x86.avx512.ptestnm.d.512" => "__builtin_ia32_ptestnmd512", + "llvm.x86.avx512.ptestnm.q.128" => "__builtin_ia32_ptestnmq128", + "llvm.x86.avx512.ptestnm.q.256" => "__builtin_ia32_ptestnmq256", + "llvm.x86.avx512.ptestnm.q.512" => "__builtin_ia32_ptestnmq512", + "llvm.x86.avx512.ptestnm.w.128" => "__builtin_ia32_ptestnmw128", + "llvm.x86.avx512.ptestnm.w.256" => "__builtin_ia32_ptestnmw256", + "llvm.x86.avx512.ptestnm.w.512" => "__builtin_ia32_ptestnmw512", "llvm.x86.avx512.rcp14.pd.128" => "__builtin_ia32_rcp14pd128_mask", "llvm.x86.avx512.rcp14.pd.256" => "__builtin_ia32_rcp14pd256_mask", "llvm.x86.avx512.rcp14.pd.512" => "__builtin_ia32_rcp14pd512_mask", @@ -3507,10 +4933,26 @@ match name { "llvm.x86.avx512.scatter.qpi.512" => "__builtin_ia32_scatterdiv16si", "llvm.x86.avx512.scatter.qpq.512" => "__builtin_ia32_scatterdiv8di", "llvm.x86.avx512.scatter.qps.512" => "__builtin_ia32_scatterdiv16sf", + "llvm.x86.avx512.scatterdiv2.df" => "__builtin_ia32_scatterdiv2df", + "llvm.x86.avx512.scatterdiv2.di" => "__builtin_ia32_scatterdiv2di", + "llvm.x86.avx512.scatterdiv4.df" => "__builtin_ia32_scatterdiv4df", + "llvm.x86.avx512.scatterdiv4.di" => "__builtin_ia32_scatterdiv4di", + "llvm.x86.avx512.scatterdiv4.sf" => "__builtin_ia32_scatterdiv4sf", + "llvm.x86.avx512.scatterdiv4.si" => "__builtin_ia32_scatterdiv4si", + "llvm.x86.avx512.scatterdiv8.sf" => "__builtin_ia32_scatterdiv8sf", + "llvm.x86.avx512.scatterdiv8.si" => "__builtin_ia32_scatterdiv8si", "llvm.x86.avx512.scatterpf.dpd.512" => "__builtin_ia32_scatterpfdpd", "llvm.x86.avx512.scatterpf.dps.512" => "__builtin_ia32_scatterpfdps", "llvm.x86.avx512.scatterpf.qpd.512" => "__builtin_ia32_scatterpfqpd", "llvm.x86.avx512.scatterpf.qps.512" => "__builtin_ia32_scatterpfqps", + "llvm.x86.avx512.scattersiv2.df" => "__builtin_ia32_scattersiv2df", + "llvm.x86.avx512.scattersiv2.di" => "__builtin_ia32_scattersiv2di", + "llvm.x86.avx512.scattersiv4.df" => "__builtin_ia32_scattersiv4df", + "llvm.x86.avx512.scattersiv4.di" => "__builtin_ia32_scattersiv4di", + "llvm.x86.avx512.scattersiv4.sf" => "__builtin_ia32_scattersiv4sf", + "llvm.x86.avx512.scattersiv4.si" => "__builtin_ia32_scattersiv4si", + "llvm.x86.avx512.scattersiv8.sf" => "__builtin_ia32_scattersiv8sf", + "llvm.x86.avx512.scattersiv8.si" => "__builtin_ia32_scattersiv8si", "llvm.x86.avx512.sqrt.pd.512" => "__builtin_ia32_sqrtpd512_mask", "llvm.x86.avx512.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask", "llvm.x86.avx512.sqrt.sd" => "__builtin_ia32_sqrtrndsd", @@ -3885,6 +5327,7 @@ match name { "llvm.x86.rdgsbase.32" => "__builtin_ia32_rdgsbase32", "llvm.x86.rdgsbase.64" => "__builtin_ia32_rdgsbase64", "llvm.x86.rdpid" => "__builtin_ia32_rdpid", + "llvm.x86.rdpkru" => "__builtin_ia32_rdpkru", "llvm.x86.rdpmc" => "__builtin_ia32_rdpmc", "llvm.x86.rdsspd" => "__builtin_ia32_rdsspd", "llvm.x86.rdsspq" => "__builtin_ia32_rdsspq", From e25e2c3b94e1f89fb1d38f77a8a58da5e8a2d581 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Sun, 15 May 2022 14:48:52 +0200 Subject: [PATCH 094/356] Regenerate JSON file for llvmint every time --- tools/generate_intrinsics.py | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/tools/generate_intrinsics.py b/tools/generate_intrinsics.py index a1e28c3181c9..4129c8cb4475 100644 --- a/tools/generate_intrinsics.py +++ b/tools/generate_intrinsics.py @@ -116,12 +116,11 @@ def extract_instrinsics_from_llvmint(llvmint, intrinsics): ] json_file = os.path.join(llvmint, "target/doc/llvmint.json") - if not os.path.exists(json_file): - # We need to regenerate the documentation! - run_command( - ["cargo", "rustdoc", "--", "-Zunstable-options", "--output-format", "json"], - cwd=llvmint, - ) + # We need to regenerate the documentation! + run_command( + ["cargo", "rustdoc", "--", "-Zunstable-options", "--output-format", "json"], + cwd=llvmint, + ) with open(json_file, "r", encoding="utf8") as f: json_data = json.loads(f.read()) for p in json_data["paths"]: From bac878c9a334e60291f8c77cd02f24e35ac7b637 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Sun, 15 May 2022 15:13:48 +0200 Subject: [PATCH 095/356] Add instrinsics from aweinstock314's llvmint as well --- tools/generate_intrinsics.py | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/tools/generate_intrinsics.py b/tools/generate_intrinsics.py index 4129c8cb4475..849c6e9c9816 100644 --- a/tools/generate_intrinsics.py +++ b/tools/generate_intrinsics.py @@ -16,7 +16,7 @@ def run_command(command, cwd=None): def clone_repository(repo_name, path, repo_url, sub_path=None): if os.path.exists(path): while True: - choice = input("There is already a `{}` folder, do you want to update it? [y/N]".format(repo_name)) + choice = input("There is already a `{}` folder, do you want to update it? [y/N]".format(path)) if choice == "" or choice.lower() == "n": print("Skipping repository update.") return @@ -159,13 +159,14 @@ def fill_intrinsics(intrinsics, from_intrinsics, all_intrinsics): all_intrinsics[entry[0]] = entry[1] -def update_intrinsics(llvm_path, llvmint): +def update_intrinsics(llvm_path, llvmint, llvmint2): intrinsics_llvm = {} intrinsics_llvmint = {} all_intrinsics = {} extract_instrinsics_from_llvm(llvm_path, intrinsics_llvm) extract_instrinsics_from_llvmint(llvmint, intrinsics_llvmint) + extract_instrinsics_from_llvmint(llvmint2, intrinsics_llvmint) intrinsics = {} # We give priority to translations from LLVM over the ones from llvmint. @@ -208,6 +209,10 @@ def main(): os.path.dirname(os.path.abspath(__file__)), "llvmint", ) + llvmint2_path = os.path.join( + os.path.dirname(os.path.abspath(__file__)), + "llvmint-2", + ) # First, we clone the LLVM repository if it's not already here. clone_repository( @@ -221,7 +226,12 @@ def main(): llvmint_path, "https://github.com/GuillaumeGomez/llvmint", ) - update_intrinsics(llvm_path, llvmint_path) + clone_repository( + "llvmint2", + llvmint2_path, + "https://github.com/antoyo/llvmint", + ) + update_intrinsics(llvm_path, llvmint_path, llvmint2_path) if __name__ == "__main__": From cede91971a023e8f18ad2f69a21f15a7e0ee67e9 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Sun, 15 May 2022 15:31:25 +0200 Subject: [PATCH 096/356] Add tools/llvmint-2 to ignored entries --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index ffd36ddb7db0..12ed56675639 100644 --- a/.gitignore +++ b/.gitignore @@ -22,3 +22,4 @@ gcc_path benchmarks tools/llvm-project tools/llvmint +tools/llvmint-2 From f26eb5a7a2b484ec7331722bd13dd283c7990212 Mon Sep 17 00:00:00 2001 From: yvt Date: Wed, 25 May 2022 23:09:18 +0900 Subject: [PATCH 097/356] Update `gccjit` --- Cargo.lock | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index c5315e2392ef..6df2102470fe 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -41,7 +41,7 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" -source = "git+https://github.com/antoyo/gccjit.rs#6c2af0cf733a26740f01a7c679afc20431165a54" +source = "git+https://github.com/antoyo/gccjit.rs#bdb86fb5092895ff5589726b33250010c64d93f6" dependencies = [ "gccjit_sys", ] @@ -49,7 +49,7 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" -source = "git+https://github.com/antoyo/gccjit.rs#6c2af0cf733a26740f01a7c679afc20431165a54" +source = "git+https://github.com/antoyo/gccjit.rs#bdb86fb5092895ff5589726b33250010c64d93f6" dependencies = [ "libc 0.1.12", ] From 10a9c0e57f888b56fd396b913e0b0eeca1eb0d0c Mon Sep 17 00:00:00 2001 From: yvt Date: Thu, 26 May 2022 00:08:50 +0900 Subject: [PATCH 098/356] Mark immutable globals as read-only with `LValue::global_set_readonly` --- src/consts.rs | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/consts.rs b/src/consts.rs index 4b517fd85f05..9517cf8494b0 100644 --- a/src/consts.rs +++ b/src/consts.rs @@ -47,7 +47,10 @@ impl<'gcc, 'tcx> StaticMethods for CodegenCx<'gcc, 'tcx> { } } let global_value = self.static_addr_of_mut(cv, align, kind); - // TODO(antoyo): set global constant. + #[cfg(feature = "master")] + self.global_lvalues.borrow().get(&global_value) + .expect("`static_addr_of_mut` did not add the global to `self.global_lvalues`") + .global_set_readonly(); self.const_globals.borrow_mut().insert(cv, global_value); global_value } @@ -88,7 +91,8 @@ impl<'gcc, 'tcx> StaticMethods for CodegenCx<'gcc, 'tcx> { // mutability are placed into read-only memory. if !is_mutable { if self.type_is_freeze(ty) { - // TODO(antoyo): set global constant. + #[cfg(feature = "master")] + global.global_set_readonly(); } } From 8697dec5327c7bf103dd15756ad54a54f38a4f66 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Mon, 6 Jun 2022 20:57:49 -0400 Subject: [PATCH 099/356] Update toolchain --- rust-toolchain | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rust-toolchain b/rust-toolchain index db14ea2bebca..b20aeb979ad7 100644 --- a/rust-toolchain +++ b/rust-toolchain @@ -1,3 +1,3 @@ [toolchain] -channel = "nightly-2022-03-26" +channel = "nightly-2022-06-06" components = ["rust-src", "rustc-dev", "llvm-tools-preview"] From fb69f73d67337e740fad0cfd5a9221f7757ff5f2 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Mon, 6 Jun 2022 21:17:14 -0400 Subject: [PATCH 100/356] Fix exactudiv --- src/builder.rs | 5 ++++- src/common.rs | 59 ++++++++++++++++++++++++++++++++++++++++++++++++-- src/context.rs | 15 +++++++++++++ 3 files changed, 76 insertions(+), 3 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index 726ecd626a07..fa490fe3f222 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -492,8 +492,11 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn exactudiv(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { - // TODO(antoyo): convert the arguments to unsigned? // TODO(antoyo): poison if not exact. + let a_type = a.get_type().to_unsigned(self); + let a = self.gcc_int_cast(a, a_type); + let b_type = b.get_type().to_unsigned(self); + let b = self.gcc_int_cast(b, b_type); a / b } diff --git a/src/common.rs b/src/common.rs index 478c6a611690..ce341406eaf4 100644 --- a/src/common.rs +++ b/src/common.rs @@ -279,6 +279,21 @@ impl<'gcc, 'tcx> SignType<'gcc, 'tcx> for Type<'gcc> { else if self.is_u128(cx) { cx.i128_type } + else if self.is_uchar(cx) { + cx.char_type + } + else if self.is_ushort(cx) { + cx.short_type + } + else if self.is_uint(cx) { + cx.int_type + } + else if self.is_ulong(cx) { + cx.long_type + } + else if self.is_ulonglong(cx) { + cx.longlong_type + } else { self.clone() } @@ -300,6 +315,21 @@ impl<'gcc, 'tcx> SignType<'gcc, 'tcx> for Type<'gcc> { else if self.is_i128(cx) { cx.u128_type } + else if self.is_char(cx) { + cx.uchar_type + } + else if self.is_short(cx) { + cx.ushort_type + } + else if self.is_int(cx) { + cx.uint_type + } + else if self.is_long(cx) { + cx.ulong_type + } + else if self.is_longlong(cx) { + cx.ulonglong_type + } else { self.clone() } @@ -312,6 +342,11 @@ pub trait TypeReflection<'gcc, 'tcx> { fn is_uint(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool; fn is_ulong(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool; fn is_ulonglong(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool; + fn is_char(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool; + fn is_short(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool; + fn is_int(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool; + fn is_long(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool; + fn is_longlong(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool; fn is_i8(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool; fn is_u8(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool; @@ -332,11 +367,11 @@ pub trait TypeReflection<'gcc, 'tcx> { impl<'gcc, 'tcx> TypeReflection<'gcc, 'tcx> for Type<'gcc> { fn is_uchar(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool { - self.unqualified() == cx.u8_type + self.unqualified() == cx.uchar_type } fn is_ushort(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool { - self.unqualified() == cx.u16_type + self.unqualified() == cx.ushort_type } fn is_uint(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool { @@ -351,6 +386,26 @@ impl<'gcc, 'tcx> TypeReflection<'gcc, 'tcx> for Type<'gcc> { self.unqualified() == cx.ulonglong_type } + fn is_char(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool { + self.unqualified() == cx.char_type + } + + fn is_short(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool { + self.unqualified() == cx.short_type + } + + fn is_int(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool { + self.unqualified() == cx.int_type + } + + fn is_long(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool { + self.unqualified() == cx.long_type + } + + fn is_longlong(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool { + self.unqualified() == cx.longlong_type + } + fn is_i8(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool { self.unqualified() == cx.i8_type } diff --git a/src/context.rs b/src/context.rs index 76c1c1c4c357..44f36cfa4cad 100644 --- a/src/context.rs +++ b/src/context.rs @@ -54,10 +54,15 @@ pub struct CodegenCx<'gcc, 'tcx> { pub u128_type: Type<'gcc>, pub usize_type: Type<'gcc>, + pub char_type: Type<'gcc>, + pub uchar_type: Type<'gcc>, + pub short_type: Type<'gcc>, + pub ushort_type: Type<'gcc>, pub int_type: Type<'gcc>, pub uint_type: Type<'gcc>, pub long_type: Type<'gcc>, pub ulong_type: Type<'gcc>, + pub longlong_type: Type<'gcc>, pub ulonglong_type: Type<'gcc>, pub sizet_type: Type<'gcc>, @@ -146,10 +151,15 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { let float_type = context.new_type::(); let double_type = context.new_type::(); + let char_type = context.new_c_type(CType::Char); + let uchar_type = context.new_c_type(CType::UChar); + let short_type = context.new_c_type(CType::Short); + let ushort_type = context.new_c_type(CType::UShort); let int_type = context.new_c_type(CType::Int); let uint_type = context.new_c_type(CType::UInt); let long_type = context.new_c_type(CType::Long); let ulong_type = context.new_c_type(CType::ULong); + let longlong_type = context.new_c_type(CType::LongLong); let ulonglong_type = context.new_c_type(CType::ULongLong); let sizet_type = context.new_c_type(CType::SizeT); @@ -202,10 +212,15 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { u32_type, u64_type, u128_type, + char_type, + uchar_type, + short_type, + ushort_type, int_type, uint_type, long_type, ulong_type, + longlong_type, ulonglong_type, sizet_type, From 3b3594044327ea6a426e0b95dd3ffee725089430 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 14 May 2022 17:36:37 -0400 Subject: [PATCH 101/356] Implement more SIMD --- Cargo.toml | 4 +- src/builder.rs | 2 +- src/intrinsic/llvm.rs | 115 +++++++++++++++++++++++++++---------- src/intrinsic/simd.rs | 130 ++++++++---------------------------------- 4 files changed, 113 insertions(+), 138 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index 211d19a8dc89..0e41bec8b762 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -22,10 +22,10 @@ default = ["master"] master = ["gccjit/master"] [dependencies] -gccjit = { git = "https://github.com/antoyo/gccjit.rs" } +#gccjit = { git = "https://github.com/antoyo/gccjit.rs" } # Local copy. -#gccjit = { path = "../gccjit.rs" } +gccjit = { path = "../gccjit.rs" } target-lexicon = "0.10.0" diff --git a/src/builder.rs b/src/builder.rs index fa490fe3f222..e7adf29fed8e 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1409,7 +1409,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { } #[cfg(not(feature="master"))] - pub fn vector_reduce(&mut self, src: RValue<'gcc>, op: F) -> RValue<'gcc> + pub fn vector_reduce(&mut self, _src: RValue<'gcc>, _op: F) -> RValue<'gcc> where F: Fn(RValue<'gcc>, RValue<'gcc>, &'gcc Context<'gcc>) -> RValue<'gcc> { unimplemented!(); diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 1b089f08f764..6b78157410b0 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -75,38 +75,38 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc "__builtin_ia32_pternlogd512_mask" | "__builtin_ia32_pternlogd256_mask" | "__builtin_ia32_pternlogd128_mask" | "__builtin_ia32_pternlogq512_mask" | "__builtin_ia32_pternlogq256_mask" | "__builtin_ia32_pternlogq128_mask" => { - let mut new_args = args.to_vec(); + let mut new_args = args.to_vec(); + let arg5_type = gcc_func.get_param_type(4); + let minus_one = builder.context.new_rvalue_from_int(arg5_type, -1); + new_args.push(minus_one); + args = new_args.into(); + }, + "__builtin_ia32_vfmaddps512_mask" | "__builtin_ia32_vfmaddpd512_mask" => { + let mut new_args = args.to_vec(); + + let mut last_arg = None; + if args.len() == 4 { + last_arg = new_args.pop(); + } + + let arg4_type = gcc_func.get_param_type(3); + let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); + new_args.push(minus_one); + + if args.len() == 3 { + // Both llvm.fma.v16f32 and llvm.x86.avx512.vfmadd.ps.512 maps to + // the same GCC intrinsic, but the former has 3 parameters and the + // latter has 4 so it doesn't require this additional argument. let arg5_type = gcc_func.get_param_type(4); - let minus_one = builder.context.new_rvalue_from_int(arg5_type, -1); - new_args.push(minus_one); - args = new_args.into(); - }, - "__builtin_ia32_vfmaddps512_mask" | "__builtin_ia32_vfmaddpd512_mask" => { - let mut new_args = args.to_vec(); + new_args.push(builder.context.new_rvalue_from_int(arg5_type, 4)); + } - let mut last_arg = None; - if args.len() == 4 { - last_arg = new_args.pop(); - } + if let Some(last_arg) = last_arg { + new_args.push(last_arg); + } - let arg4_type = gcc_func.get_param_type(3); - let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); - new_args.push(minus_one); - - if args.len() == 3 { - // Both llvm.fma.v16f32 and llvm.x86.avx512.vfmadd.ps.512 maps to - // the same GCC intrinsic, but the former has 3 parameters and the - // latter has 4 so it doesn't require this additional argument. - let arg5_type = gcc_func.get_param_type(4); - new_args.push(builder.context.new_rvalue_from_int(arg5_type, 4)); - } - - if let Some(last_arg) = last_arg { - new_args.push(last_arg); - } - - args = new_args.into(); - }, + args = new_args.into(); + }, "__builtin_ia32_addps512_mask" | "__builtin_ia32_addpd512_mask" | "__builtin_ia32_subps512_mask" | "__builtin_ia32_subpd512_mask" | "__builtin_ia32_mulps512_mask" | "__builtin_ia32_mulpd512_mask" @@ -131,6 +131,18 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc new_args.push(last_arg); args = new_args.into(); }, + "__builtin_ia32_cvtdq2ps512_mask" | "__builtin_ia32_cvtudq2ps512_mask" => { + let mut new_args = args.to_vec(); + let last_arg = new_args.pop().expect("last arg"); + let arg2_type = gcc_func.get_param_type(1); + let undefined = builder.current_func().new_local(None, arg2_type, "undefined_for_intrinsic").to_rvalue(); + new_args.push(undefined); + let arg3_type = gcc_func.get_param_type(2); + let minus_one = builder.context.new_rvalue_from_int(arg3_type, -1); + new_args.push(minus_one); + new_args.push(last_arg); + args = new_args.into(); + }, _ => (), } } @@ -149,7 +161,8 @@ pub fn ignore_arg_cast(func_name: &str, index: usize, args_len: usize) -> bool { | "__builtin_ia32_subps512_mask" | "__builtin_ia32_subpd512_mask" | "__builtin_ia32_mulps512_mask" | "__builtin_ia32_mulpd512_mask" | "__builtin_ia32_divps512_mask" | "__builtin_ia32_divpd512_mask" - | "__builtin_ia32_vfmaddsubps512_mask" | "__builtin_ia32_vfmaddsubpd512_mask" => { + | "__builtin_ia32_vfmaddsubps512_mask" | "__builtin_ia32_vfmaddsubpd512_mask" + | "__builtin_ia32_cvtdq2ps512_mask" | "__builtin_ia32_cvtudq2ps512_mask" => { if index == args_len - 1 { return true; } @@ -221,6 +234,48 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.avx512.div.pd.512" => "__builtin_ia32_divpd512_mask", "llvm.x86.avx512.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask", "llvm.x86.avx512.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask", + "llvm.x86.avx512.sitofp.round.v16f32.v16i32" => "__builtin_ia32_cvtdq2ps512_mask", + "llvm.x86.avx512.uitofp.round.v16f32.v16i32" => "__builtin_ia32_cvtudq2ps512_mask", + "llvm.x86.avx512.mask.cvttps2dq.256" => "__builtin_ia32_cvttps2dq256_mask", + "llvm.x86.avx512.mask.cvttps2dq.128" => "__builtin_ia32_cvttps2dq128_mask", + "llvm.x86.avx512.mask.cvttpd2dq.256" => "__builtin_ia32_cvttpd2dq256_mask", + "llvm.x86.avx512.mask.compress.d.512" => "__builtin_ia32_compresssi512_mask", + "llvm.x86.avx512.mask.compress.d.256" => "__builtin_ia32_compresssi256_mask", + "llvm.x86.avx512.mask.compress.d.128" => "__builtin_ia32_compresssi128_mask", + "llvm.x86.avx512.mask.compress.q.512" => "__builtin_ia32_compressdi512_mask", + "llvm.x86.avx512.mask.compress.q.256" => "__builtin_ia32_compressdi256_mask", + "llvm.x86.avx512.mask.compress.q.128" => "__builtin_ia32_compressdi128_mask", + "llvm.x86.avx512.mask.compress.ps.512" => "__builtin_ia32_compresssf512_mask", + "llvm.x86.avx512.mask.compress.ps.256" => "__builtin_ia32_compresssf256_mask", + "llvm.x86.avx512.mask.compress.ps.128" => "__builtin_ia32_compresssf128_mask", + "llvm.x86.avx512.mask.compress.pd.512" => "__builtin_ia32_compressdf512_mask", + "llvm.x86.avx512.mask.compress.pd.256" => "__builtin_ia32_compressdf256_mask", + "llvm.x86.avx512.mask.compress.pd.128" => "__builtin_ia32_compressdf128_mask", + "llvm.x86.avx512.mask.compress.store.d.512" => "", + "llvm.x86.avx512.mask.compress.store.d.256" => "", + "llvm.x86.avx512.mask.compress.store.d.128" => "", + "llvm.x86.avx512.mask.compress.store.q.512" => "", + "llvm.x86.avx512.mask.compress.store.q.256" => "", + "llvm.x86.avx512.mask.compress.store.q.128" => "", + "llvm.x86.avx512.mask.compress.store.ps.512" => "", + "llvm.x86.avx512.mask.compress.store.ps.256" => "", + "llvm.x86.avx512.mask.compress.store.ps.128" => "", + "llvm.x86.avx512.mask.compress.store.pd.512" => "", + "llvm.x86.avx512.mask.compress.store.pd.256" => "", + "llvm.x86.avx512.mask.compress.store.pd.128" => "", + "llvm.x86.avx512.mask.expand.d.512" => "", + "llvm.x86.avx512.mask.expand.d.256" => "", + "llvm.x86.avx512.mask.expand.d.128" => "", + "llvm.x86.avx512.mask.expand.q.512" => "", + "" => "", + "" => "", + "" => "", + "" => "", + "" => "", + "" => "", + "" => "", + "" => "", + "" => "", // The above doc points to unknown builtins for the following, so override them: "llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gathersiv4si", diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index 870e9f776a4f..a6cf99c62fff 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -1,5 +1,3 @@ -use std::cmp::Ordering; - use gccjit::{BinaryOp, RValue, Type, ToRValue}; use rustc_codegen_ssa::base::compare_simd_types; use rustc_codegen_ssa::common::{TypeKind, span_invalid_monomorphization_error}; @@ -309,117 +307,37 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, enum Style { Float, - Int(/* is signed? */ bool), + Int, Unsupported, } - let (in_style, in_width) = match in_elem.kind() { - // vectors of pointer-sized integers should've been - // disallowed before here, so this unwrap is safe. - ty::Int(i) => ( - Style::Int(true), - i.normalize(bx.tcx().sess.target.pointer_width).bit_width().unwrap(), - ), - ty::Uint(u) => ( - Style::Int(false), - u.normalize(bx.tcx().sess.target.pointer_width).bit_width().unwrap(), - ), - ty::Float(f) => (Style::Float, f.bit_width()), - _ => (Style::Unsupported, 0), - }; - let (out_style, out_width) = match out_elem.kind() { - ty::Int(i) => ( - Style::Int(true), - i.normalize(bx.tcx().sess.target.pointer_width).bit_width().unwrap(), - ), - ty::Uint(u) => ( - Style::Int(false), - u.normalize(bx.tcx().sess.target.pointer_width).bit_width().unwrap(), - ), - ty::Float(f) => (Style::Float, f.bit_width()), - _ => (Style::Unsupported, 0), - }; - - let extend = |in_type, out_type| { - let vector_type = bx.context.new_vector_type(out_type, 8); - let vector = args[0].immediate(); - let array_type = bx.context.new_array_type(None, in_type, 8); - // TODO(antoyo): switch to using new_vector_access or __builtin_convertvector for vector casting. - let array = bx.context.new_bitcast(None, vector, array_type); - - let cast_vec_element = |index| { - let index = bx.context.new_rvalue_from_int(bx.int_type, index); - bx.context.new_cast(None, bx.context.new_array_access(None, array, index).to_rvalue(), out_type) + let in_style = + match in_elem.kind() { + ty::Int(_) | ty::Uint(_) => Style::Int, + ty::Float(_) => Style::Float, + _ => Style::Unsupported, }; - bx.context.new_rvalue_from_vector(None, vector_type, &[ - cast_vec_element(0), - cast_vec_element(1), - cast_vec_element(2), - cast_vec_element(3), - cast_vec_element(4), - cast_vec_element(5), - cast_vec_element(6), - cast_vec_element(7), - ]) - }; + let out_style = + match out_elem.kind() { + ty::Int(_) | ty::Uint(_) => Style::Int, + ty::Float(_) => Style::Float, + _ => Style::Unsupported, + }; match (in_style, out_style) { - (Style::Int(in_is_signed), Style::Int(_)) => { - return Ok(match in_width.cmp(&out_width) { - Ordering::Greater => bx.trunc(args[0].immediate(), llret_ty), - Ordering::Equal => args[0].immediate(), - Ordering::Less => { - if in_is_signed { - match (in_width, out_width) { - // FIXME(antoyo): the function _mm_cvtepi8_epi16 should directly - // call an intrinsic equivalent to __builtin_ia32_pmovsxbw128 so that - // we can generate a call to it. - (8, 16) => extend(bx.i8_type, bx.i16_type), - (8, 32) => extend(bx.i8_type, bx.i32_type), - (8, 64) => extend(bx.i8_type, bx.i64_type), - (16, 32) => extend(bx.i16_type, bx.i32_type), - (32, 64) => extend(bx.i32_type, bx.i64_type), - (16, 64) => extend(bx.i16_type, bx.i64_type), - _ => unimplemented!("in: {}, out: {}", in_width, out_width), - } - } else { - match (in_width, out_width) { - (8, 16) => extend(bx.u8_type, bx.u16_type), - (8, 32) => extend(bx.u8_type, bx.u32_type), - (8, 64) => extend(bx.u8_type, bx.u64_type), - (16, 32) => extend(bx.u16_type, bx.u32_type), - (16, 64) => extend(bx.u16_type, bx.u64_type), - (32, 64) => extend(bx.u32_type, bx.u64_type), - _ => unimplemented!("in: {}, out: {}", in_width, out_width), - } - } - } - }); - } - (Style::Int(_), Style::Float) => { - // TODO: add support for internal functions in libgccjit to get access to IFN_VEC_CONVERT which is - // doing like __builtin_convertvector? - // Or maybe provide convert_vector as an API since it might not easy to get the - // types of internal functions. - unimplemented!(); - } - (Style::Float, Style::Int(_)) => { - unimplemented!(); - } - (Style::Float, Style::Float) => { - unimplemented!(); - } - _ => { /* Unsupported. Fallthrough. */ } + (Style::Unsupported, Style::Unsupported) => { + require!( + false, + "unsupported cast from `{}` with element `{}` to `{}` with element `{}`", + in_ty, + in_elem, + ret_ty, + out_elem + ); + }, + _ => return Ok(bx.context.convert_vector(None, args[0].immediate(), llret_ty)), } - require!( - false, - "unsupported cast from `{}` with element `{}` to `{}` with element `{}`", - in_ty, - in_elem, - ret_ty, - out_elem - ); } macro_rules! arith_binary { @@ -590,6 +508,8 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, ); } }; + // TODO(antoyo): don't use target specific builtins here. + // Not sure how easy it would be to avoid theme here. let builtin_name = match (signed, is_add, in_len, elem_width) { (true, true, 32, 8) => "__builtin_ia32_paddsb256", // TODO(antoyo): cast arguments to unsigned. From 4e802c84c587bf0524fe672ed81ed97e33afea9d Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 15 May 2022 10:49:09 -0400 Subject: [PATCH 102/356] Remove intrinsics that were adding by the updated script --- src/intrinsic/llvm.rs | 132 +++++++++++++++--------------------------- 1 file changed, 47 insertions(+), 85 deletions(-) diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 6b78157410b0..a4cd05a13c70 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -107,43 +107,53 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc args = new_args.into(); }, - "__builtin_ia32_addps512_mask" | "__builtin_ia32_addpd512_mask" - | "__builtin_ia32_subps512_mask" | "__builtin_ia32_subpd512_mask" - | "__builtin_ia32_mulps512_mask" | "__builtin_ia32_mulpd512_mask" - | "__builtin_ia32_divps512_mask" | "__builtin_ia32_divpd512_mask" => { - let mut new_args = args.to_vec(); - let last_arg = new_args.pop().expect("last arg"); - let arg3_type = gcc_func.get_param_type(2); - let undefined = builder.current_func().new_local(None, arg3_type, "undefined_for_intrinsic").to_rvalue(); - new_args.push(undefined); - let arg4_type = gcc_func.get_param_type(3); - let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); - new_args.push(minus_one); - new_args.push(last_arg); - args = new_args.into(); - }, - "__builtin_ia32_vfmaddsubps512_mask" | "__builtin_ia32_vfmaddsubpd512_mask" => { - let mut new_args = args.to_vec(); - let last_arg = new_args.pop().expect("last arg"); - let arg4_type = gcc_func.get_param_type(3); - let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); - new_args.push(minus_one); - new_args.push(last_arg); - args = new_args.into(); - }, - "__builtin_ia32_cvtdq2ps512_mask" | "__builtin_ia32_cvtudq2ps512_mask" => { - let mut new_args = args.to_vec(); - let last_arg = new_args.pop().expect("last arg"); - let arg2_type = gcc_func.get_param_type(1); - let undefined = builder.current_func().new_local(None, arg2_type, "undefined_for_intrinsic").to_rvalue(); - new_args.push(undefined); - let arg3_type = gcc_func.get_param_type(2); - let minus_one = builder.context.new_rvalue_from_int(arg3_type, -1); - new_args.push(minus_one); - new_args.push(last_arg); - args = new_args.into(); - }, - _ => (), + "__builtin_ia32_addps512_mask" | "__builtin_ia32_addpd512_mask" + | "__builtin_ia32_subps512_mask" | "__builtin_ia32_subpd512_mask" + | "__builtin_ia32_mulps512_mask" | "__builtin_ia32_mulpd512_mask" + | "__builtin_ia32_divps512_mask" | "__builtin_ia32_divpd512_mask" => { + let mut new_args = args.to_vec(); + let last_arg = new_args.pop().expect("last arg"); + let arg3_type = gcc_func.get_param_type(2); + let undefined = builder.current_func().new_local(None, arg3_type, "undefined_for_intrinsic").to_rvalue(); + new_args.push(undefined); + let arg4_type = gcc_func.get_param_type(3); + let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); + new_args.push(minus_one); + new_args.push(last_arg); + args = new_args.into(); + }, + "__builtin_ia32_prold512_mask" => { + let mut new_args = args.to_vec(); + let arg3_type = gcc_func.get_param_type(2); + let undefined = builder.current_func().new_local(None, arg3_type, "undefined_for_intrinsic").to_rvalue(); + new_args.push(undefined); + let arg4_type = gcc_func.get_param_type(3); + let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); + new_args.push(minus_one); + args = new_args.into(); + }, + "__builtin_ia32_vfmaddsubps512_mask" | "__builtin_ia32_vfmaddsubpd512_mask" => { + let mut new_args = args.to_vec(); + let last_arg = new_args.pop().expect("last arg"); + let arg4_type = gcc_func.get_param_type(3); + let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); + new_args.push(minus_one); + new_args.push(last_arg); + args = new_args.into(); + }, + "__builtin_ia32_cvtdq2ps512_mask" | "__builtin_ia32_cvtudq2ps512_mask" => { + let mut new_args = args.to_vec(); + let last_arg = new_args.pop().expect("last arg"); + let arg2_type = gcc_func.get_param_type(1); + let undefined = builder.current_func().new_local(None, arg2_type, "undefined_for_intrinsic").to_rvalue(); + new_args.push(undefined); + let arg3_type = gcc_func.get_param_type(2); + let minus_one = builder.context.new_rvalue_from_int(arg3_type, -1); + new_args.push(minus_one); + new_args.push(last_arg); + args = new_args.into(); + }, + _ => (), } } @@ -202,18 +212,10 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.sqrt.v2f64" => "__builtin_ia32_sqrtpd", "llvm.x86.avx512.pmul.dq.512" => "__builtin_ia32_pmuldq512_mask", "llvm.x86.avx512.pmulu.dq.512" => "__builtin_ia32_pmuludq512_mask", - "llvm.x86.avx512.mask.pmaxs.q.256" => "__builtin_ia32_pmaxsq256_mask", - "llvm.x86.avx512.mask.pmaxs.q.128" => "__builtin_ia32_pmaxsq128_mask", "llvm.x86.avx512.max.ps.512" => "__builtin_ia32_maxps512_mask", "llvm.x86.avx512.max.pd.512" => "__builtin_ia32_maxpd512_mask", - "llvm.x86.avx512.mask.pmaxu.q.256" => "__builtin_ia32_pmaxuq256_mask", - "llvm.x86.avx512.mask.pmaxu.q.128" => "__builtin_ia32_pmaxuq128_mask", - "llvm.x86.avx512.mask.pmins.q.256" => "__builtin_ia32_pminsq256_mask", - "llvm.x86.avx512.mask.pmins.q.128" => "__builtin_ia32_pminsq128_mask", "llvm.x86.avx512.min.ps.512" => "__builtin_ia32_minps512_mask", "llvm.x86.avx512.min.pd.512" => "__builtin_ia32_minpd512_mask", - "llvm.x86.avx512.mask.pminu.q.256" => "__builtin_ia32_pminuq256_mask", - "llvm.x86.avx512.mask.pminu.q.128" => "__builtin_ia32_pminuq128_mask", "llvm.fma.v16f32" => "__builtin_ia32_vfmaddps512_mask", "llvm.fma.v8f64" => "__builtin_ia32_vfmaddpd512_mask", "llvm.x86.avx512.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask", @@ -236,46 +238,6 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.avx512.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask", "llvm.x86.avx512.sitofp.round.v16f32.v16i32" => "__builtin_ia32_cvtdq2ps512_mask", "llvm.x86.avx512.uitofp.round.v16f32.v16i32" => "__builtin_ia32_cvtudq2ps512_mask", - "llvm.x86.avx512.mask.cvttps2dq.256" => "__builtin_ia32_cvttps2dq256_mask", - "llvm.x86.avx512.mask.cvttps2dq.128" => "__builtin_ia32_cvttps2dq128_mask", - "llvm.x86.avx512.mask.cvttpd2dq.256" => "__builtin_ia32_cvttpd2dq256_mask", - "llvm.x86.avx512.mask.compress.d.512" => "__builtin_ia32_compresssi512_mask", - "llvm.x86.avx512.mask.compress.d.256" => "__builtin_ia32_compresssi256_mask", - "llvm.x86.avx512.mask.compress.d.128" => "__builtin_ia32_compresssi128_mask", - "llvm.x86.avx512.mask.compress.q.512" => "__builtin_ia32_compressdi512_mask", - "llvm.x86.avx512.mask.compress.q.256" => "__builtin_ia32_compressdi256_mask", - "llvm.x86.avx512.mask.compress.q.128" => "__builtin_ia32_compressdi128_mask", - "llvm.x86.avx512.mask.compress.ps.512" => "__builtin_ia32_compresssf512_mask", - "llvm.x86.avx512.mask.compress.ps.256" => "__builtin_ia32_compresssf256_mask", - "llvm.x86.avx512.mask.compress.ps.128" => "__builtin_ia32_compresssf128_mask", - "llvm.x86.avx512.mask.compress.pd.512" => "__builtin_ia32_compressdf512_mask", - "llvm.x86.avx512.mask.compress.pd.256" => "__builtin_ia32_compressdf256_mask", - "llvm.x86.avx512.mask.compress.pd.128" => "__builtin_ia32_compressdf128_mask", - "llvm.x86.avx512.mask.compress.store.d.512" => "", - "llvm.x86.avx512.mask.compress.store.d.256" => "", - "llvm.x86.avx512.mask.compress.store.d.128" => "", - "llvm.x86.avx512.mask.compress.store.q.512" => "", - "llvm.x86.avx512.mask.compress.store.q.256" => "", - "llvm.x86.avx512.mask.compress.store.q.128" => "", - "llvm.x86.avx512.mask.compress.store.ps.512" => "", - "llvm.x86.avx512.mask.compress.store.ps.256" => "", - "llvm.x86.avx512.mask.compress.store.ps.128" => "", - "llvm.x86.avx512.mask.compress.store.pd.512" => "", - "llvm.x86.avx512.mask.compress.store.pd.256" => "", - "llvm.x86.avx512.mask.compress.store.pd.128" => "", - "llvm.x86.avx512.mask.expand.d.512" => "", - "llvm.x86.avx512.mask.expand.d.256" => "", - "llvm.x86.avx512.mask.expand.d.128" => "", - "llvm.x86.avx512.mask.expand.q.512" => "", - "" => "", - "" => "", - "" => "", - "" => "", - "" => "", - "" => "", - "" => "", - "" => "", - "" => "", // The above doc points to unknown builtins for the following, so override them: "llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gathersiv4si", From f59d345fc1979ff0b9dc14f4ffcf6a3bd3c6368f Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 15 May 2022 11:43:57 -0400 Subject: [PATCH 103/356] Refactor --- src/intrinsic/llvm.rs | 239 ++++++++++++++++++------------------------ 1 file changed, 100 insertions(+), 139 deletions(-) diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index a4cd05a13c70..2a6739e74b00 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -9,151 +9,112 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc // arguments here. if gcc_func.get_param_count() != args.len() { match &*func_name { - "__builtin_ia32_pmuldq512_mask" | "__builtin_ia32_pmuludq512_mask" - // FIXME(antoyo): the following intrinsics has 4 (or 5) arguments according to the doc, but is defined with 2 (or 3) arguments in library/stdarch/crates/core_arch/src/x86/avx512f.rs. + // NOTE: the following intrinsics have a different number of parameters in LLVM and GCC. + "__builtin_ia32_prold512_mask" | "__builtin_ia32_pmuldq512_mask" | "__builtin_ia32_pmuludq512_mask" | "__builtin_ia32_pmaxsd512_mask" | "__builtin_ia32_pmaxsq512_mask" | "__builtin_ia32_pmaxsq256_mask" - | "__builtin_ia32_pmaxsq128_mask" | "__builtin_ia32_maxps512_mask" | "__builtin_ia32_maxpd512_mask" - | "__builtin_ia32_pmaxud512_mask" | "__builtin_ia32_pmaxuq512_mask" | "__builtin_ia32_pmaxuq256_mask" - | "__builtin_ia32_pmaxuq128_mask" + | "__builtin_ia32_pmaxsq128_mask" | "__builtin_ia32_pmaxud512_mask" | "__builtin_ia32_pmaxuq512_mask" | "__builtin_ia32_pminsd512_mask" | "__builtin_ia32_pminsq512_mask" | "__builtin_ia32_pminsq256_mask" - | "__builtin_ia32_pminsq128_mask" | "__builtin_ia32_minps512_mask" | "__builtin_ia32_minpd512_mask" - | "__builtin_ia32_pminud512_mask" | "__builtin_ia32_pminuq512_mask" | "__builtin_ia32_pminuq256_mask" - | "__builtin_ia32_pminuq128_mask" | "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" + | "__builtin_ia32_pminsq128_mask" | "__builtin_ia32_pminud512_mask" | "__builtin_ia32_pminuq512_mask" => { - // TODO: refactor by separating those intrinsics outside of this branch. - let add_before_last_arg = - match &*func_name { - "__builtin_ia32_maxps512_mask" | "__builtin_ia32_maxpd512_mask" - | "__builtin_ia32_minps512_mask" | "__builtin_ia32_minpd512_mask" - | "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => true, - _ => false, - }; - let new_first_arg_is_zero = - match &*func_name { - "__builtin_ia32_pmaxuq256_mask" | "__builtin_ia32_pmaxuq128_mask" - | "__builtin_ia32_pminuq256_mask" | "__builtin_ia32_pminuq128_mask" => true, - _ => false - }; - let arg3_index = - match &*func_name { - "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => 1, - _ => 2, - }; - let mut new_args = args.to_vec(); - let arg3_type = gcc_func.get_param_type(arg3_index); - let first_arg = - if new_first_arg_is_zero { - let vector_type = arg3_type.dyncast_vector().expect("vector type"); - let zero = builder.context.new_rvalue_zero(vector_type.get_element_type()); - let num_units = vector_type.get_num_units(); - builder.context.new_rvalue_from_vector(None, arg3_type, &vec![zero; num_units]) - } - else { - builder.current_func().new_local(None, arg3_type, "undefined_for_intrinsic").to_rvalue() - }; - if add_before_last_arg { - new_args.insert(new_args.len() - 1, first_arg); - } - else { - new_args.push(first_arg); - } - let arg4_index = - match &*func_name { - "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => 2, - _ => 3, - }; - let arg4_type = gcc_func.get_param_type(arg4_index); - let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); - if add_before_last_arg { - new_args.insert(new_args.len() - 1, minus_one); - } - else { - new_args.push(minus_one); - } - args = new_args.into(); - }, - "__builtin_ia32_pternlogd512_mask" | "__builtin_ia32_pternlogd256_mask" - | "__builtin_ia32_pternlogd128_mask" | "__builtin_ia32_pternlogq512_mask" - | "__builtin_ia32_pternlogq256_mask" | "__builtin_ia32_pternlogq128_mask" => { - let mut new_args = args.to_vec(); + let mut new_args = args.to_vec(); + let arg3_type = gcc_func.get_param_type(2); + let first_arg = builder.current_func().new_local(None, arg3_type, "undefined_for_intrinsic").to_rvalue(); + new_args.push(first_arg); + let arg4_type = gcc_func.get_param_type(3); + let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); + new_args.push(minus_one); + args = new_args.into(); + }, + "__builtin_ia32_pmaxuq256_mask" | "__builtin_ia32_pmaxuq128_mask" + | "__builtin_ia32_pminuq256_mask" | "__builtin_ia32_pminuq128_mask" + => { + let mut new_args = args.to_vec(); + let arg3_type = gcc_func.get_param_type(2); + let vector_type = arg3_type.dyncast_vector().expect("vector type"); + let zero = builder.context.new_rvalue_zero(vector_type.get_element_type()); + let num_units = vector_type.get_num_units(); + let first_arg = builder.context.new_rvalue_from_vector(None, arg3_type, &vec![zero; num_units]); + new_args.push(first_arg); + let arg4_type = gcc_func.get_param_type(3); + let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); + new_args.push(minus_one); + args = new_args.into(); + }, + "__builtin_ia32_pternlogd512_mask" | "__builtin_ia32_pternlogd256_mask" + | "__builtin_ia32_pternlogd128_mask" | "__builtin_ia32_pternlogq512_mask" + | "__builtin_ia32_pternlogq256_mask" | "__builtin_ia32_pternlogq128_mask" => { + let mut new_args = args.to_vec(); + let arg5_type = gcc_func.get_param_type(4); + let minus_one = builder.context.new_rvalue_from_int(arg5_type, -1); + new_args.push(minus_one); + args = new_args.into(); + }, + "__builtin_ia32_vfmaddps512_mask" | "__builtin_ia32_vfmaddpd512_mask" => { + let mut new_args = args.to_vec(); + + let mut last_arg = None; + if args.len() == 4 { + last_arg = new_args.pop(); + } + + let arg4_type = gcc_func.get_param_type(3); + let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); + new_args.push(minus_one); + + if args.len() == 3 { + // Both llvm.fma.v16f32 and llvm.x86.avx512.vfmadd.ps.512 maps to + // the same GCC intrinsic, but the former has 3 parameters and the + // latter has 4 so it doesn't require this additional argument. let arg5_type = gcc_func.get_param_type(4); - let minus_one = builder.context.new_rvalue_from_int(arg5_type, -1); - new_args.push(minus_one); - args = new_args.into(); - }, - "__builtin_ia32_vfmaddps512_mask" | "__builtin_ia32_vfmaddpd512_mask" => { - let mut new_args = args.to_vec(); + new_args.push(builder.context.new_rvalue_from_int(arg5_type, 4)); + } - let mut last_arg = None; - if args.len() == 4 { - last_arg = new_args.pop(); - } - - let arg4_type = gcc_func.get_param_type(3); - let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); - new_args.push(minus_one); - - if args.len() == 3 { - // Both llvm.fma.v16f32 and llvm.x86.avx512.vfmadd.ps.512 maps to - // the same GCC intrinsic, but the former has 3 parameters and the - // latter has 4 so it doesn't require this additional argument. - let arg5_type = gcc_func.get_param_type(4); - new_args.push(builder.context.new_rvalue_from_int(arg5_type, 4)); - } - - if let Some(last_arg) = last_arg { - new_args.push(last_arg); - } - - args = new_args.into(); - }, - "__builtin_ia32_addps512_mask" | "__builtin_ia32_addpd512_mask" - | "__builtin_ia32_subps512_mask" | "__builtin_ia32_subpd512_mask" - | "__builtin_ia32_mulps512_mask" | "__builtin_ia32_mulpd512_mask" - | "__builtin_ia32_divps512_mask" | "__builtin_ia32_divpd512_mask" => { - let mut new_args = args.to_vec(); - let last_arg = new_args.pop().expect("last arg"); - let arg3_type = gcc_func.get_param_type(2); - let undefined = builder.current_func().new_local(None, arg3_type, "undefined_for_intrinsic").to_rvalue(); - new_args.push(undefined); - let arg4_type = gcc_func.get_param_type(3); - let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); - new_args.push(minus_one); + if let Some(last_arg) = last_arg { new_args.push(last_arg); - args = new_args.into(); - }, - "__builtin_ia32_prold512_mask" => { - let mut new_args = args.to_vec(); - let arg3_type = gcc_func.get_param_type(2); - let undefined = builder.current_func().new_local(None, arg3_type, "undefined_for_intrinsic").to_rvalue(); - new_args.push(undefined); - let arg4_type = gcc_func.get_param_type(3); - let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); - new_args.push(minus_one); - args = new_args.into(); - }, - "__builtin_ia32_vfmaddsubps512_mask" | "__builtin_ia32_vfmaddsubpd512_mask" => { - let mut new_args = args.to_vec(); - let last_arg = new_args.pop().expect("last arg"); - let arg4_type = gcc_func.get_param_type(3); - let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); - new_args.push(minus_one); - new_args.push(last_arg); - args = new_args.into(); - }, - "__builtin_ia32_cvtdq2ps512_mask" | "__builtin_ia32_cvtudq2ps512_mask" => { - let mut new_args = args.to_vec(); - let last_arg = new_args.pop().expect("last arg"); - let arg2_type = gcc_func.get_param_type(1); - let undefined = builder.current_func().new_local(None, arg2_type, "undefined_for_intrinsic").to_rvalue(); - new_args.push(undefined); - let arg3_type = gcc_func.get_param_type(2); - let minus_one = builder.context.new_rvalue_from_int(arg3_type, -1); - new_args.push(minus_one); - new_args.push(last_arg); - args = new_args.into(); - }, - _ => (), + } + + args = new_args.into(); + }, + "__builtin_ia32_addps512_mask" | "__builtin_ia32_addpd512_mask" + | "__builtin_ia32_subps512_mask" | "__builtin_ia32_subpd512_mask" + | "__builtin_ia32_mulps512_mask" | "__builtin_ia32_mulpd512_mask" + | "__builtin_ia32_divps512_mask" | "__builtin_ia32_divpd512_mask" + | "__builtin_ia32_maxps512_mask" | "__builtin_ia32_maxpd512_mask" + | "__builtin_ia32_minps512_mask" | "__builtin_ia32_minpd512_mask" => { + let mut new_args = args.to_vec(); + let last_arg = new_args.pop().expect("last arg"); + let arg3_type = gcc_func.get_param_type(2); + let undefined = builder.current_func().new_local(None, arg3_type, "undefined_for_intrinsic").to_rvalue(); + new_args.push(undefined); + let arg4_type = gcc_func.get_param_type(3); + let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); + new_args.push(minus_one); + new_args.push(last_arg); + args = new_args.into(); + }, + "__builtin_ia32_vfmaddsubps512_mask" | "__builtin_ia32_vfmaddsubpd512_mask" => { + let mut new_args = args.to_vec(); + let last_arg = new_args.pop().expect("last arg"); + let arg4_type = gcc_func.get_param_type(3); + let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); + new_args.push(minus_one); + new_args.push(last_arg); + args = new_args.into(); + }, + "__builtin_ia32_cvtdq2ps512_mask" | "__builtin_ia32_cvtudq2ps512_mask" + | "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => { + let mut new_args = args.to_vec(); + let last_arg = new_args.pop().expect("last arg"); + let arg2_type = gcc_func.get_param_type(1); + let undefined = builder.current_func().new_local(None, arg2_type, "undefined_for_intrinsic").to_rvalue(); + new_args.push(undefined); + let arg3_type = gcc_func.get_param_type(2); + let minus_one = builder.context.new_rvalue_from_int(arg3_type, -1); + new_args.push(minus_one); + new_args.push(last_arg); + args = new_args.into(); + }, + _ => (), } } From 2fa6a9080b5c3bc963f649832f1fdf9fbcd8abd2 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 15 May 2022 12:07:28 -0400 Subject: [PATCH 104/356] Add more SIMD --- src/intrinsic/llvm.rs | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 2a6739e74b00..241cff204590 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -15,6 +15,7 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc | "__builtin_ia32_pmaxsq128_mask" | "__builtin_ia32_pmaxud512_mask" | "__builtin_ia32_pmaxuq512_mask" | "__builtin_ia32_pminsd512_mask" | "__builtin_ia32_pminsq512_mask" | "__builtin_ia32_pminsq256_mask" | "__builtin_ia32_pminsq128_mask" | "__builtin_ia32_pminud512_mask" | "__builtin_ia32_pminuq512_mask" + | "__builtin_ia32_prolq512_mask" | "__builtin_ia32_prorq512_mask" => { let mut new_args = args.to_vec(); let arg3_type = gcc_func.get_param_type(2); @@ -25,8 +26,11 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc new_args.push(minus_one); args = new_args.into(); }, - "__builtin_ia32_pmaxuq256_mask" | "__builtin_ia32_pmaxuq128_mask" - | "__builtin_ia32_pminuq256_mask" | "__builtin_ia32_pminuq128_mask" + "__builtin_ia32_pmaxuq256_mask" | "__builtin_ia32_pmaxuq128_mask" | "__builtin_ia32_pminuq256_mask" + | "__builtin_ia32_pminuq128_mask" | "__builtin_ia32_prold256_mask" | "__builtin_ia32_prold128_mask" + | "__builtin_ia32_prord512_mask" | "__builtin_ia32_prord256_mask" | "__builtin_ia32_prord128_mask" + | "__builtin_ia32_prolq256_mask" | "__builtin_ia32_prolq128_mask" | "__builtin_ia32_prorq256_mask" + | "__builtin_ia32_prorq128_mask" => { let mut new_args = args.to_vec(); let arg3_type = gcc_func.get_param_type(2); From 06073c9dfc15dd07b611e3497539dcab547ce185 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 15 May 2022 20:55:51 -0400 Subject: [PATCH 105/356] Add more SIMD --- src/builder.rs | 6 +- src/intrinsic/llvm.rs | 213 ++++++++++++++++++++++++++++++++++++++- src/intrinsic/simd.rs | 226 ++++++++++++++++++++++++++++-------------- 3 files changed, 362 insertions(+), 83 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index e7adf29fed8e..b23d12cb0b6b 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -286,10 +286,12 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { if return_type != void_type { unsafe { RETURN_VALUE_COUNT += 1 }; - let result = current_func.new_local(None, return_type, &format!("ptrReturnValue{}", unsafe { RETURN_VALUE_COUNT })); let func_name = format!("{:?}", func_ptr); let args = llvm::adjust_intrinsic_arguments(&self, gcc_func, args, &func_name); - self.block.add_assignment(None, result, self.cx.context.new_call_through_ptr(None, func_ptr, &args)); + let return_value = self.cx.context.new_call_through_ptr(None, func_ptr, &args); + let return_value = llvm::adjust_intrinsic_return_value(&self, return_value, &func_name, &args); + let result = current_func.new_local(None, return_value.get_type(), &format!("ptrReturnValue{}", unsafe { RETURN_VALUE_COUNT })); + self.block.add_assignment(None, result, return_value); result.to_rvalue() } else { diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 241cff204590..0e75724122cf 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -15,7 +15,17 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc | "__builtin_ia32_pmaxsq128_mask" | "__builtin_ia32_pmaxud512_mask" | "__builtin_ia32_pmaxuq512_mask" | "__builtin_ia32_pminsd512_mask" | "__builtin_ia32_pminsq512_mask" | "__builtin_ia32_pminsq256_mask" | "__builtin_ia32_pminsq128_mask" | "__builtin_ia32_pminud512_mask" | "__builtin_ia32_pminuq512_mask" - | "__builtin_ia32_prolq512_mask" | "__builtin_ia32_prorq512_mask" + | "__builtin_ia32_prolq512_mask" | "__builtin_ia32_prorq512_mask" | "__builtin_ia32_pslldi512_mask" + | "__builtin_ia32_psrldi512_mask" | "__builtin_ia32_psllqi512_mask" | "__builtin_ia32_psrlqi512_mask" + | "__builtin_ia32_pslld512_mask" | "__builtin_ia32_psrld512_mask" | "__builtin_ia32_psllq512_mask" + | "__builtin_ia32_psrlq512_mask" | "__builtin_ia32_psrad512_mask" | "__builtin_ia32_psraq512_mask" + | "__builtin_ia32_psradi512_mask" | "__builtin_ia32_psraqi512_mask" | "__builtin_ia32_psrav16si_mask" + | "__builtin_ia32_psrav8di_mask" | "__builtin_ia32_prolvd512_mask" | "__builtin_ia32_prorvd512_mask" + | "__builtin_ia32_prolvq512_mask" | "__builtin_ia32_prorvq512_mask" | "__builtin_ia32_psllv16si_mask" + | "__builtin_ia32_psrlv16si_mask" | "__builtin_ia32_psllv8di_mask" | "__builtin_ia32_psrlv8di_mask" + | "__builtin_ia32_permvarsi512_mask" | "__builtin_ia32_vpermilvarps512_mask" + | "__builtin_ia32_vpermilvarpd512_mask" | "__builtin_ia32_permvardi512_mask" + | "__builtin_ia32_permvarsf512_mask" => { let mut new_args = args.to_vec(); let arg3_type = gcc_func.get_param_type(2); @@ -30,7 +40,12 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc | "__builtin_ia32_pminuq128_mask" | "__builtin_ia32_prold256_mask" | "__builtin_ia32_prold128_mask" | "__builtin_ia32_prord512_mask" | "__builtin_ia32_prord256_mask" | "__builtin_ia32_prord128_mask" | "__builtin_ia32_prolq256_mask" | "__builtin_ia32_prolq128_mask" | "__builtin_ia32_prorq256_mask" - | "__builtin_ia32_prorq128_mask" + | "__builtin_ia32_prorq128_mask" | "__builtin_ia32_psraq256_mask" | "__builtin_ia32_psraq128_mask" + | "__builtin_ia32_psraqi256_mask" | "__builtin_ia32_psraqi128_mask" | "__builtin_ia32_psravq256_mask" + | "__builtin_ia32_psravq128_mask" | "__builtin_ia32_prolvd256_mask" | "__builtin_ia32_prolvd128_mask" + | "__builtin_ia32_prorvd256_mask" | "__builtin_ia32_prorvd128_mask" | "__builtin_ia32_prolvq256_mask" + | "__builtin_ia32_prolvq128_mask" | "__builtin_ia32_prorvq256_mask" | "__builtin_ia32_prorvq128_mask" + | "__builtin_ia32_permvardi256_mask" | "__builtin_ia32_permvardf512_mask" | "__builtin_ia32_permvardf256_mask" => { let mut new_args = args.to_vec(); let arg3_type = gcc_func.get_param_type(2); @@ -105,6 +120,18 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc new_args.push(last_arg); args = new_args.into(); }, + "__builtin_ia32_vpermi2vard512_mask" | "__builtin_ia32_vpermi2vard256_mask" + | "__builtin_ia32_vpermi2vard128_mask" | "__builtin_ia32_vpermi2varq512_mask" + | "__builtin_ia32_vpermi2varq256_mask" | "__builtin_ia32_vpermi2varq128_mask" + | "__builtin_ia32_vpermi2varps512_mask" | "__builtin_ia32_vpermi2varps256_mask" + | "__builtin_ia32_vpermi2varps128_mask" | "__builtin_ia32_vpermi2varpd512_mask" + | "__builtin_ia32_vpermi2varpd256_mask" | "__builtin_ia32_vpermi2varpd128_mask" => { + let mut new_args = args.to_vec(); + let arg4_type = gcc_func.get_param_type(3); + let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); + new_args.push(minus_one); + args = new_args.into(); + }, "__builtin_ia32_cvtdq2ps512_mask" | "__builtin_ia32_cvtudq2ps512_mask" | "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => { let mut new_args = args.to_vec(); @@ -118,6 +145,52 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc new_args.push(last_arg); args = new_args.into(); }, + "__builtin_ia32_stmxcsr" => { + args = vec![].into(); + }, + "__builtin_ia32_addcarryx_u64" => { + let mut new_args = args.to_vec(); + let arg2_type = gcc_func.get_param_type(1); + let variable = builder.current_func().new_local(None, arg2_type, "addcarryResult"); + new_args.push(variable.get_address(None)); + args = new_args.into(); + }, + _ => (), + } + } + else { + match &*func_name { + "__builtin_ia32_rndscaless_mask_round" | "__builtin_ia32_rndscalesd_mask_round" => { + let new_args = args.to_vec(); + let arg3_type = gcc_func.get_param_type(2); + let arg3 = builder.context.new_cast(None, new_args[4], arg3_type); + let arg4_type = gcc_func.get_param_type(3); + let arg4 = builder.context.new_bitcast(None, new_args[2], arg4_type); + args = vec![new_args[0], new_args[1], arg3, arg4, new_args[3], new_args[5]].into(); + }, + // NOTE: the LLVM intrinsic receives 3 floats, but the GCC builtin requires 3 vectors. + // FIXME: the intrinsics like _mm_mask_fmadd_sd should probably directly call the GCC + // instrinsic to avoid this. + "__builtin_ia32_vfmaddss3_round" => { + let new_args = args.to_vec(); + let arg1_type = gcc_func.get_param_type(0); + let arg2_type = gcc_func.get_param_type(1); + let arg3_type = gcc_func.get_param_type(2); + let a = builder.context.new_rvalue_from_vector(None, arg1_type, &[new_args[0]; 4]); + let b = builder.context.new_rvalue_from_vector(None, arg2_type, &[new_args[1]; 4]); + let c = builder.context.new_rvalue_from_vector(None, arg3_type, &[new_args[2]; 4]); + args = vec![a, b, c, new_args[3]].into(); + }, + "__builtin_ia32_vfmaddsd3_round" => { + let new_args = args.to_vec(); + let arg1_type = gcc_func.get_param_type(0); + let arg2_type = gcc_func.get_param_type(1); + let arg3_type = gcc_func.get_param_type(2); + let a = builder.context.new_rvalue_from_vector(None, arg1_type, &[new_args[0]; 2]); + let b = builder.context.new_rvalue_from_vector(None, arg2_type, &[new_args[1]; 2]); + let c = builder.context.new_rvalue_from_vector(None, arg3_type, &[new_args[2]; 2]); + args = vec![a, b, c, new_args[3]].into(); + }, _ => (), } } @@ -125,11 +198,30 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc args } +pub fn adjust_intrinsic_return_value<'a, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc, 'tcx>, mut return_value: RValue<'gcc>, func_name: &str, args: &[RValue<'gcc>]) -> RValue<'gcc> { + match func_name { + "__builtin_ia32_vfmaddss3_round" | "__builtin_ia32_vfmaddsd3_round" => { + let zero = builder.context.new_rvalue_zero(builder.int_type); + return_value = builder.context.new_vector_access(None, return_value, zero).to_rvalue(); + }, + "__builtin_ia32_addcarryx_u64" => { + let last_arg = args.last().expect("last arg"); + let field1 = builder.context.new_field(None, builder.u8_type, "carryFlag"); + let field2 = builder.context.new_field(None, builder.ulonglong_type, "carryResult"); + let struct_type = builder.context.new_struct_type(None, "addcarryResult", &[field1, field2]); + return_value = builder.context.new_struct_constructor(None, struct_type.as_type(), None, &[return_value, last_arg.dereference(None).to_rvalue()]); + }, + _ => (), + } + + return_value +} + pub fn ignore_arg_cast(func_name: &str, index: usize, args_len: usize) -> bool { - // NOTE: these intrinsics have missing parameters before the last one, so ignore the - // last argument type check. // FIXME(antoyo): find a way to refactor in order to avoid this hack. match func_name { + // NOTE: these intrinsics have missing parameters before the last one, so ignore the + // last argument type check. "__builtin_ia32_maxps512_mask" | "__builtin_ia32_maxpd512_mask" | "__builtin_ia32_minps512_mask" | "__builtin_ia32_minpd512_mask" | "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" | "__builtin_ia32_addps512_mask" | "__builtin_ia32_addpd512_mask" @@ -142,6 +234,11 @@ pub fn ignore_arg_cast(func_name: &str, index: usize, args_len: usize) -> bool { return true; } }, + "__builtin_ia32_rndscaless_mask_round" | "__builtin_ia32_rndscalesd_mask_round" => { + if index == 2 || index == 3 { + return true; + } + }, "__builtin_ia32_vfmaddps512_mask" | "__builtin_ia32_vfmaddpd512_mask" => { // Since there are two LLVM intrinsics that map to each of these GCC builtins and only // one of them has a missing parameter before the last one, we check the number of @@ -150,6 +247,8 @@ pub fn ignore_arg_cast(func_name: &str, index: usize, args_len: usize) -> bool { return true; } }, + // NOTE: the LLVM intrinsic receives 3 floats, but the GCC builtin requires 3 vectors. + "__builtin_ia32_vfmaddss3_round" | "__builtin_ia32_vfmaddsd3_round" => return true, _ => (), } @@ -203,6 +302,47 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.avx512.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask", "llvm.x86.avx512.sitofp.round.v16f32.v16i32" => "__builtin_ia32_cvtdq2ps512_mask", "llvm.x86.avx512.uitofp.round.v16f32.v16i32" => "__builtin_ia32_cvtudq2ps512_mask", + "llvm.x86.avx512.mask.ucmp.d.512" => "__builtin_ia32_ucmpd512_mask", + "llvm.x86.avx512.mask.ucmp.d.256" => "__builtin_ia32_ucmpd256_mask", + "llvm.x86.avx512.mask.ucmp.d.128" => "__builtin_ia32_ucmpd128_mask", + "llvm.x86.avx512.mask.cmp.d.512" => "__builtin_ia32_cmpd512_mask", + "llvm.x86.avx512.mask.cmp.d.256" => "__builtin_ia32_cmpd256_mask", + "llvm.x86.avx512.mask.cmp.d.128" => "__builtin_ia32_cmpd128_mask", + "llvm.x86.avx512.mask.ucmp.q.512" => "__builtin_ia32_ucmpq512_mask", + "llvm.x86.avx512.mask.ucmp.q.256" => "__builtin_ia32_ucmpq256_mask", + "llvm.x86.avx512.mask.ucmp.q.128" => "__builtin_ia32_ucmpq128_mask", + "llvm.x86.avx512.mask.cmp.q.512" => "__builtin_ia32_cmpq512_mask", + "llvm.x86.avx512.mask.cmp.q.256" => "__builtin_ia32_cmpq256_mask", + "llvm.x86.avx512.mask.cmp.q.128" => "__builtin_ia32_cmpq128_mask", + "llvm.x86.avx512.mask.max.ss.round" => "__builtin_ia32_maxss_mask_round", + "llvm.x86.avx512.mask.max.sd.round" => "__builtin_ia32_maxsd_mask_round", + "llvm.x86.avx512.mask.min.ss.round" => "__builtin_ia32_minss_mask_round", + "llvm.x86.avx512.mask.min.sd.round" => "__builtin_ia32_minsd_mask_round", + "llvm.x86.avx512.mask.sqrt.ss" => "__builtin_ia32_sqrtss_mask_round", + "llvm.x86.avx512.mask.sqrt.sd" => "__builtin_ia32_sqrtsd_mask_round", + "llvm.x86.avx512.mask.getexp.ss" => "__builtin_ia32_getexpss_mask_round", + "llvm.x86.avx512.mask.getexp.sd" => "__builtin_ia32_getexpsd_mask_round", + "llvm.x86.avx512.mask.getmant.ss" => "__builtin_ia32_getmantss_mask_round", + "llvm.x86.avx512.mask.getmant.sd" => "__builtin_ia32_getmantsd_mask_round", + "llvm.x86.avx512.mask.rndscale.ss" => "__builtin_ia32_rndscaless_mask_round", + "llvm.x86.avx512.mask.rndscale.sd" => "__builtin_ia32_rndscalesd_mask_round", + "llvm.x86.avx512.mask.scalef.ss" => "__builtin_ia32_scalefss_mask_round", + "llvm.x86.avx512.mask.scalef.sd" => "__builtin_ia32_scalefsd_mask_round", + "llvm.x86.avx512.vfmadd.f32" => "__builtin_ia32_vfmaddss3_round", + "llvm.x86.avx512.vfmadd.f64" => "__builtin_ia32_vfmaddsd3_round", + "llvm.ceil.v4f64" => "__builtin_ia32_ceilpd256", + "llvm.ceil.v8f32" => "__builtin_ia32_ceilps256", + "llvm.floor.v4f64" => "__builtin_ia32_floorpd256", + "llvm.floor.v8f32" => "__builtin_ia32_floorps256", + "llvm.sqrt.v4f64" => "__builtin_ia32_sqrtpd256", + "llvm.x86.sse.stmxcsr" => "__builtin_ia32_stmxcsr", + "llvm.x86.sse.ldmxcsr" => "__builtin_ia32_ldmxcsr", + "llvm.ctpop.v16i32" => "__builtin_ia32_vpopcountd_v16si", + "llvm.ctpop.v8i32" => "__builtin_ia32_vpopcountd_v8si", + "llvm.ctpop.v4i32" => "__builtin_ia32_vpopcountd_v4si", + "llvm.ctpop.v8i64" => "__builtin_ia32_vpopcountq_v8di", + "llvm.ctpop.v4i64" => "__builtin_ia32_vpopcountq_v4di", + "llvm.ctpop.v2i64" => "__builtin_ia32_vpopcountq_v2di", // The above doc points to unknown builtins for the following, so override them: "llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gathersiv4si", @@ -221,7 +361,70 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.avx2.gather.q.q.256" => "__builtin_ia32_gatherdiv4di", "llvm.x86.avx2.gather.q.pd" => "__builtin_ia32_gatherdiv2df", "llvm.x86.avx2.gather.q.pd.256" => "__builtin_ia32_gatherdiv4df", - "" => "", + "llvm.x86.avx512.pslli.d.512" => "__builtin_ia32_pslldi512_mask", + "llvm.x86.avx512.psrli.d.512" => "__builtin_ia32_psrldi512_mask", + "llvm.x86.avx512.pslli.q.512" => "__builtin_ia32_psllqi512_mask", + "llvm.x86.avx512.psrli.q.512" => "__builtin_ia32_psrlqi512_mask", + "llvm.x86.avx512.psll.d.512" => "__builtin_ia32_pslld512_mask", + "llvm.x86.avx512.psrl.d.512" => "__builtin_ia32_psrld512_mask", + "llvm.x86.avx512.psll.q.512" => "__builtin_ia32_psllq512_mask", + "llvm.x86.avx512.psrl.q.512" => "__builtin_ia32_psrlq512_mask", + "llvm.x86.avx512.psra.d.512" => "__builtin_ia32_psrad512_mask", + "llvm.x86.avx512.psra.q.512" => "__builtin_ia32_psraq512_mask", + "llvm.x86.avx512.psra.q.256" => "__builtin_ia32_psraq256_mask", + "llvm.x86.avx512.psra.q.128" => "__builtin_ia32_psraq128_mask", + "llvm.x86.avx512.psrai.d.512" => "__builtin_ia32_psradi512_mask", + "llvm.x86.avx512.psrai.q.512" => "__builtin_ia32_psraqi512_mask", + "llvm.x86.avx512.psrai.q.256" => "__builtin_ia32_psraqi256_mask", + "llvm.x86.avx512.psrai.q.128" => "__builtin_ia32_psraqi128_mask", + "llvm.x86.avx512.psrav.d.512" => "__builtin_ia32_psrav16si_mask", + "llvm.x86.avx512.psrav.q.512" => "__builtin_ia32_psrav8di_mask", + "llvm.x86.avx512.psrav.q.256" => "__builtin_ia32_psravq256_mask", + "llvm.x86.avx512.psrav.q.128" => "__builtin_ia32_psravq128_mask", + "llvm.x86.avx512.psllv.d.512" => "__builtin_ia32_psllv16si_mask", + "llvm.x86.avx512.psrlv.d.512" => "__builtin_ia32_psrlv16si_mask", + "llvm.x86.avx512.psllv.q.512" => "__builtin_ia32_psllv8di_mask", + "llvm.x86.avx512.psrlv.q.512" => "__builtin_ia32_psrlv8di_mask", + "llvm.x86.avx512.permvar.si.512" => "__builtin_ia32_permvarsi512_mask", + "llvm.x86.avx512.vpermilvar.ps.512" => "__builtin_ia32_vpermilvarps512_mask", + "llvm.x86.avx512.vpermilvar.pd.512" => "__builtin_ia32_vpermilvarpd512_mask", + "llvm.x86.avx512.permvar.di.512" => "__builtin_ia32_permvardi512_mask", + "llvm.x86.avx512.permvar.di.256" => "__builtin_ia32_permvardi256_mask", + "llvm.x86.avx512.permvar.sf.512" => "__builtin_ia32_permvarsf512_mask", + "llvm.x86.avx512.permvar.df.512" => "__builtin_ia32_permvardf512_mask", + "llvm.x86.avx512.permvar.df.256" => "__builtin_ia32_permvardf256_mask", + "llvm.x86.avx512.vpermi2var.d.512" => "__builtin_ia32_vpermi2vard512_mask", + "llvm.x86.avx512.vpermi2var.d.256" => "__builtin_ia32_vpermi2vard256_mask", + "llvm.x86.avx512.vpermi2var.d.128" => "__builtin_ia32_vpermi2vard128_mask", + "llvm.x86.avx512.vpermi2var.q.512" => "__builtin_ia32_vpermi2varq512_mask", + "llvm.x86.avx512.vpermi2var.q.256" => "__builtin_ia32_vpermi2varq256_mask", + "llvm.x86.avx512.vpermi2var.q.128" => "__builtin_ia32_vpermi2varq128_mask", + "llvm.x86.avx512.vpermi2var.ps.512" => "__builtin_ia32_vpermi2varps512_mask", + "llvm.x86.avx512.vpermi2var.ps.256" => "__builtin_ia32_vpermi2varps256_mask", + "llvm.x86.avx512.vpermi2var.ps.128" => "__builtin_ia32_vpermi2varps128_mask", + "llvm.x86.avx512.vpermi2var.pd.512" => "__builtin_ia32_vpermi2varpd512_mask", + "llvm.x86.avx512.vpermi2var.pd.256" => "__builtin_ia32_vpermi2varpd256_mask", + "llvm.x86.avx512.vpermi2var.pd.128" => "__builtin_ia32_vpermi2varpd128_mask", + "llvm.x86.avx512.mask.add.ss.round" => "__builtin_ia32_addss_mask_round", + "llvm.x86.avx512.mask.add.sd.round" => "__builtin_ia32_addsd_mask_round", + "llvm.x86.avx512.mask.sub.ss.round" => "__builtin_ia32_subss_mask_round", + "llvm.x86.avx512.mask.sub.sd.round" => "__builtin_ia32_subsd_mask_round", + "llvm.x86.avx512.mask.mul.ss.round" => "__builtin_ia32_mulss_mask_round", + "llvm.x86.avx512.mask.mul.sd.round" => "__builtin_ia32_mulsd_mask_round", + "llvm.x86.avx512.mask.div.ss.round" => "__builtin_ia32_divss_mask_round", + "llvm.x86.avx512.mask.div.sd.round" => "__builtin_ia32_divsd_mask_round", + "llvm.x86.avx512.mask.cvtss2sd.round" => "__builtin_ia32_cvtss2sd_mask_round", + "llvm.x86.avx512.mask.cvtsd2ss.round" => "__builtin_ia32_cvtsd2ss_mask_round", + "llvm.x86.aesni.aesenc.256" => "__builtin_ia32_vaesenc_v32qi", + "llvm.x86.aesni.aesenclast.256" => "__builtin_ia32_vaesenclast_v32qi", + "llvm.x86.aesni.aesdec.256" => "__builtin_ia32_vaesdec_v32qi", + "llvm.x86.aesni.aesdeclast.256" => "__builtin_ia32_vaesdeclast_v32qi", + "llvm.x86.aesni.aesenc.512" => "__builtin_ia32_vaesenc_v64qi", + "llvm.x86.aesni.aesenclast.512" => "__builtin_ia32_vaesenclast_v64qi", + "llvm.x86.aesni.aesdec.512" => "__builtin_ia32_vaesdec_v64qi", + "llvm.x86.aesni.aesdeclast.512" => "__builtin_ia32_vaesdeclast_v64qi", + "llvm.x86.addcarry.64" => "__builtin_ia32_addcarryx_u64", + // NOTE: this file is generated by https://github.com/GuillaumeGomez/llvmint/blob/master/generate_list.py _ => include!("archs.rs"), }; diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index a6cf99c62fff..bf5d555736ae 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -1,4 +1,4 @@ -use gccjit::{BinaryOp, RValue, Type, ToRValue}; +use gccjit::{BinaryOp, RValue, Type, ToRValue, ComparisonOp, UnaryOp}; use rustc_codegen_ssa::base::compare_simd_types; use rustc_codegen_ssa::common::{TypeKind, span_invalid_monomorphization_error}; use rustc_codegen_ssa::mir::operand::OperandRef; @@ -213,48 +213,12 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let vector = args[0].immediate(); let index = args[1].immediate(); let value = args[2].immediate(); - // TODO(antoyo): use a recursive unqualified() here. - let vector_type = vector.get_type().unqualified().dyncast_vector().expect("vector type"); - let element_type = vector_type.get_element_type(); - // NOTE: we cannot cast to an array and assign to its element here because the value might - // not be an l-value. So, call a builtin to set the element. - // TODO(antoyo): perhaps we could create a new vector or maybe there's a GIMPLE instruction for that? - // TODO(antoyo): don't use target specific builtins here. - let func_name = - match in_len { - 2 => { - if element_type == bx.i64_type { - "__builtin_ia32_vec_set_v2di" - } - else { - unimplemented!(); - } - }, - 4 => { - if element_type == bx.i32_type { - "__builtin_ia32_vec_set_v4si" - } - else { - unimplemented!(); - } - }, - 8 => { - if element_type == bx.i16_type { - "__builtin_ia32_vec_set_v8hi" - } - else { - unimplemented!(); - } - }, - _ => unimplemented!("Len: {}", in_len), - }; - let builtin = bx.context.get_target_builtin_function(func_name); - let param1_type = builtin.get_param(0).to_rvalue().get_type(); - // TODO(antoyo): perhaps use __builtin_convertvector for vector casting. - let vector = bx.cx.bitcast_if_needed(vector, param1_type); - let result = bx.context.new_call(None, builtin, &[vector, value, bx.context.new_cast(None, index, bx.int_type)]); - // TODO(antoyo): perhaps use __builtin_convertvector for vector casting. - return Ok(bx.context.new_bitcast(None, result, vector.get_type())); + let variable = bx.current_func().new_local(None, vector.get_type(), "new_vector"); + bx.llbb().add_assignment(None, variable, vector); + let lvalue = bx.context.new_vector_access(None, variable.to_rvalue(), index); + // TODO: si simd_insert est constant, utiliser BIT_REF… + bx.llbb().add_assignment(None, lvalue, value); + return Ok(variable.to_rvalue()); } #[cfg(feature="master")] @@ -357,6 +321,67 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, } } + if name == sym::simd_bitmask { + // The `fn simd_bitmask(vector) -> unsigned integer` intrinsic takes a + // vector mask and returns the most significant bit (MSB) of each lane in the form + // of either: + // * an unsigned integer + // * an array of `u8` + // If the vector has less than 8 lanes, a u8 is returned with zeroed trailing bits. + // + // The bit order of the result depends on the byte endianness, LSB-first for little + // endian and MSB-first for big endian. + + let vector = args[0].immediate(); + let vector_type = vector.get_type().dyncast_vector().expect("vector type"); + let elem_type = vector_type.get_element_type(); + let mut shifts = vec![]; + let mut masks = vec![]; + let mut mask = 1; + for i in 0..in_len { + shifts.push(bx.context.new_rvalue_from_int(elem_type, i as i32)); + masks.push(bx.context.new_rvalue_from_int(elem_type, mask)); + mask <<= 1; + } + masks.reverse(); + let shifts = bx.context.new_rvalue_from_vector(None, vector.get_type(), &shifts); + let shifted = vector >> shifts; + let masks = bx.context.new_rvalue_from_vector(None, vector.get_type(), &masks); + let masked = shifted & masks; + let reduced = bx.vector_reduce_op(masked, BinaryOp::BitwiseOr); + + let expected_int_bits = in_len.max(8); + let expected_bytes = expected_int_bits / 8 + ((expected_int_bits % 8 > 0) as u64); + + match ret_ty.kind() { + ty::Uint(i) if i.bit_width() == Some(expected_int_bits) => { + // Zero-extend iN to the bitmask type: + return Ok(bx.zext(reduced, bx.type_ix(expected_int_bits))); + } + ty::Array(elem, len) + if matches!(elem.kind(), ty::Uint(ty::UintTy::U8)) + && len.try_eval_usize(bx.tcx, ty::ParamEnv::reveal_all()) + == Some(expected_bytes) => + { + // Zero-extend iN to the array length: + let ze = bx.zext(reduced, bx.type_ix(expected_bytes * 8)); + + // Convert the integer to a byte array + let ptr = bx.alloca(bx.type_ix(expected_bytes * 8), Align::ONE); + bx.store(ze, ptr, Align::ONE); + let array_ty = bx.type_array(bx.type_i8(), expected_bytes); + let ptr = bx.pointercast(ptr, bx.cx.type_ptr_to(array_ty)); + return Ok(bx.load(array_ty, ptr, Align::ONE)); + } + _ => return_error!( + "cannot return `{}`, expected `u{}` or `[u8; {}]`", + ret_ty, + expected_int_bits, + expected_bytes + ), + } + } + fn simd_simple_float_intrinsic<'gcc, 'tcx>( name: Symbol, in_elem: Ty<'_>, @@ -496,42 +521,91 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let rhs = args[1].immediate(); let is_add = name == sym::simd_saturating_add; let ptr_bits = bx.tcx().data_layout.pointer_size.bits() as _; - let (signed, elem_width, elem_ty) = match *in_elem.kind() { - ty::Int(i) => (true, i.bit_width().unwrap_or(ptr_bits), bx.cx.type_int_from_ty(i)), - ty::Uint(i) => (false, i.bit_width().unwrap_or(ptr_bits), bx.cx.type_uint_from_ty(i)), - _ => { - return_error!( - "expected element type `{}` of vector type `{}` \ + let (signed, elem_width, elem_ty) = + match *in_elem.kind() { + ty::Int(i) => (true, i.bit_width().unwrap_or(ptr_bits) / 8, bx.cx.type_int_from_ty(i)), + ty::Uint(i) => (false, i.bit_width().unwrap_or(ptr_bits) / 8, bx.cx.type_uint_from_ty(i)), + _ => { + return_error!( + "expected element type `{}` of vector type `{}` \ to be a signed or unsigned integer type", - arg_tys[0].simd_size_and_type(bx.tcx()).1, - arg_tys[0] - ); - } - }; - // TODO(antoyo): don't use target specific builtins here. - // Not sure how easy it would be to avoid theme here. - let builtin_name = - match (signed, is_add, in_len, elem_width) { - (true, true, 32, 8) => "__builtin_ia32_paddsb256", // TODO(antoyo): cast arguments to unsigned. - (false, true, 32, 8) => "__builtin_ia32_paddusb256", - (true, true, 16, 16) => "__builtin_ia32_paddsw256", - (false, true, 16, 16) => "__builtin_ia32_paddusw256", - (true, false, 16, 16) => "__builtin_ia32_psubsw256", - (false, false, 16, 16) => "__builtin_ia32_psubusw256", - (true, false, 32, 8) => "__builtin_ia32_psubsb256", - (false, false, 32, 8) => "__builtin_ia32_psubusb256", - _ => unimplemented!("signed: {}, is_add: {}, in_len: {}, elem_width: {}", signed, is_add, in_len, elem_width), + arg_tys[0].simd_size_and_type(bx.tcx()).1, + arg_tys[0] + ); + } }; - let vec_ty = bx.cx.type_vector(elem_ty, in_len as u64); - let func = bx.context.get_target_builtin_function(builtin_name); - let param1_type = func.get_param(0).to_rvalue().get_type(); - let param2_type = func.get_param(1).to_rvalue().get_type(); - let lhs = bx.cx.bitcast_if_needed(lhs, param1_type); - let rhs = bx.cx.bitcast_if_needed(rhs, param2_type); - let result = bx.context.new_call(None, func, &[lhs, rhs]); - // TODO(antoyo): perhaps use __builtin_convertvector for vector casting. - return Ok(bx.context.new_bitcast(None, result, vec_ty)); + let result = + match (signed, is_add) { + (false, true) => { + let res = lhs + rhs; + let cmp = bx.context.new_comparison(None, ComparisonOp::LessThan, res, lhs); + res | cmp + }, + (true, true) => { + // Algorithm from: https://codereview.stackexchange.com/questions/115869/saturated-signed-addition + // TODO: improve using conditional operators if possible. + let arg_type = lhs.get_type(); + // TODO: convert lhs and rhs to unsigned. + let sum = lhs + rhs; + let vector_type = arg_type.dyncast_vector().expect("vector type"); + let unit = vector_type.get_num_units(); + let a = bx.context.new_rvalue_from_int(elem_ty, ((elem_width as i32) << 3) - 1); + let width = bx.context.new_rvalue_from_vector(None, lhs.get_type(), &vec![a; unit]); + + let xor1 = lhs ^ rhs; + let xor2 = lhs ^ sum; + let and = bx.context.new_unary_op(None, UnaryOp::BitwiseNegate, arg_type, xor1) & xor2; + let mask = and >> width; + + let one = bx.context.new_rvalue_one(elem_ty); + let ones = bx.context.new_rvalue_from_vector(None, lhs.get_type(), &vec![one; unit]); + let shift1 = ones << width; + let shift2 = sum >> width; + let mask_min = shift1 ^ shift2; + + let and1 = bx.context.new_unary_op(None, UnaryOp::BitwiseNegate, arg_type, mask) & sum; + let and2 = mask & mask_min; + + and1 + and2 + }, + (false, false) => { + let res = lhs - rhs; + let cmp = bx.context.new_comparison(None, ComparisonOp::LessThanEquals, res, lhs); + res & cmp + }, + (true, false) => { + let arg_type = lhs.get_type(); + // TODO(antoyo): this uses the same algorithm from saturating add, but add the + // negative of the right operand. Find a proper subtraction algorithm. + let rhs = bx.context.new_unary_op(None, UnaryOp::Minus, arg_type, rhs); + + // TODO: convert lhs and rhs to unsigned. + let sum = lhs + rhs; + let vector_type = arg_type.dyncast_vector().expect("vector type"); + let unit = vector_type.get_num_units(); + let a = bx.context.new_rvalue_from_int(elem_ty, ((elem_width as i32) << 3) - 1); + let width = bx.context.new_rvalue_from_vector(None, lhs.get_type(), &vec![a; unit]); + + let xor1 = lhs ^ rhs; + let xor2 = lhs ^ sum; + let and = bx.context.new_unary_op(None, UnaryOp::BitwiseNegate, arg_type, xor1) & xor2; + let mask = and >> width; + + let one = bx.context.new_rvalue_one(elem_ty); + let ones = bx.context.new_rvalue_from_vector(None, lhs.get_type(), &vec![one; unit]); + let shift1 = ones << width; + let shift2 = sum >> width; + let mask_min = shift1 ^ shift2; + + let and1 = bx.context.new_unary_op(None, UnaryOp::BitwiseNegate, arg_type, mask) & sum; + let and2 = mask & mask_min; + + and1 + and2 + } + }; + + return Ok(result); } macro_rules! arith_red { From df85771b34b745d2f9228cd260da9002a4a6cb60 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 4 Jun 2022 00:32:01 -0400 Subject: [PATCH 106/356] Add more SIMD --- src/intrinsic/llvm.rs | 92 ++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 87 insertions(+), 5 deletions(-) diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 0e75724122cf..7154a89543c2 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -1,6 +1,6 @@ use std::borrow::Cow; -use gccjit::{Function, FunctionPtrType, RValue, ToRValue}; +use gccjit::{Function, FunctionPtrType, RValue, ToRValue, UnaryOp}; use crate::{context::CodegenCx, builder::Builder}; @@ -25,7 +25,10 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc | "__builtin_ia32_psrlv16si_mask" | "__builtin_ia32_psllv8di_mask" | "__builtin_ia32_psrlv8di_mask" | "__builtin_ia32_permvarsi512_mask" | "__builtin_ia32_vpermilvarps512_mask" | "__builtin_ia32_vpermilvarpd512_mask" | "__builtin_ia32_permvardi512_mask" - | "__builtin_ia32_permvarsf512_mask" + | "__builtin_ia32_permvarsf512_mask" | "__builtin_ia32_permvarqi512_mask" + | "__builtin_ia32_permvarqi256_mask" | "__builtin_ia32_permvarqi128_mask" + | "__builtin_ia32_vpmultishiftqb512_mask" | "__builtin_ia32_vpmultishiftqb256_mask" + | "__builtin_ia32_vpmultishiftqb128_mask" => { let mut new_args = args.to_vec(); let arg3_type = gcc_func.get_param_type(2); @@ -59,6 +62,23 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc new_args.push(minus_one); args = new_args.into(); }, + "__builtin_ia32_vplzcntd_512_mask" | "__builtin_ia32_vplzcntd_256_mask" | "__builtin_ia32_vplzcntd_128_mask" + | "__builtin_ia32_vplzcntq_512_mask" | "__builtin_ia32_vplzcntq_256_mask" | "__builtin_ia32_vplzcntq_128_mask" + | "__builtin_ia32_vpconflictsi_512_mask" | "__builtin_ia32_vpconflictsi_256_mask" + | "__builtin_ia32_vpconflictsi_128_mask" | "__builtin_ia32_vpconflictdi_512_mask" + | "__builtin_ia32_vpconflictdi_256_mask" | "__builtin_ia32_vpconflictdi_128_mask" => { + let mut new_args = args.to_vec(); + let arg2_type = gcc_func.get_param_type(1); + let vector_type = arg2_type.dyncast_vector().expect("vector type"); + let zero = builder.context.new_rvalue_zero(vector_type.get_element_type()); + let num_units = vector_type.get_num_units(); + let first_arg = builder.context.new_rvalue_from_vector(None, arg2_type, &vec![zero; num_units]); + new_args.push(first_arg); + let arg3_type = gcc_func.get_param_type(2); + let minus_one = builder.context.new_rvalue_from_int(arg3_type, -1); + new_args.push(minus_one); + args = new_args.into(); + }, "__builtin_ia32_pternlogd512_mask" | "__builtin_ia32_pternlogd256_mask" | "__builtin_ia32_pternlogd128_mask" | "__builtin_ia32_pternlogq512_mask" | "__builtin_ia32_pternlogq256_mask" | "__builtin_ia32_pternlogq128_mask" => { @@ -148,13 +168,20 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc "__builtin_ia32_stmxcsr" => { args = vec![].into(); }, - "__builtin_ia32_addcarryx_u64" => { + "__builtin_ia32_addcarryx_u64" | "__builtin_ia32_sbb_u64" => { let mut new_args = args.to_vec(); let arg2_type = gcc_func.get_param_type(1); let variable = builder.current_func().new_local(None, arg2_type, "addcarryResult"); new_args.push(variable.get_address(None)); args = new_args.into(); }, + "__builtin_ia32_vpermt2varqi512_mask" | "__builtin_ia32_vpermt2varqi256_mask" + | "__builtin_ia32_vpermt2varqi128_mask" => { + let mut new_args = args.to_vec(); + let arg4_type = gcc_func.get_param_type(3); + let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); + args = vec![new_args[1], new_args[0], new_args[2], minus_one].into(); + }, _ => (), } } @@ -191,6 +218,12 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc let c = builder.context.new_rvalue_from_vector(None, arg3_type, &[new_args[2]; 2]); args = vec![a, b, c, new_args[3]].into(); }, + "__builtin_ia32_vfmaddsubpd256" | "__builtin_ia32_vfmaddsubps" | "__builtin_ia32_vfmaddsubps256" => { + let mut new_args = args.to_vec(); + let arg3 = &mut new_args[2]; + *arg3 = builder.context.new_unary_op(None, UnaryOp::Minus, arg3.get_type(), *arg3); + args = new_args.into(); + }, _ => (), } } @@ -204,7 +237,7 @@ pub fn adjust_intrinsic_return_value<'a, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc, let zero = builder.context.new_rvalue_zero(builder.int_type); return_value = builder.context.new_vector_access(None, return_value, zero).to_rvalue(); }, - "__builtin_ia32_addcarryx_u64" => { + "__builtin_ia32_addcarryx_u64" | "__builtin_ia32_sbb_u64" => { let last_arg = args.last().expect("last arg"); let field1 = builder.context.new_field(None, builder.u8_type, "carryFlag"); let field2 = builder.context.new_field(None, builder.ulonglong_type, "carryResult"); @@ -343,6 +376,48 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.ctpop.v8i64" => "__builtin_ia32_vpopcountq_v8di", "llvm.ctpop.v4i64" => "__builtin_ia32_vpopcountq_v4di", "llvm.ctpop.v2i64" => "__builtin_ia32_vpopcountq_v2di", + "llvm.x86.addcarry.64" => "__builtin_ia32_addcarryx_u64", + "llvm.x86.subborrow.64" => "__builtin_ia32_sbb_u64", + "llvm.floor.v2f64" => "__builtin_ia32_floorpd", + "llvm.floor.v4f32" => "__builtin_ia32_floorps", + "llvm.ceil.v2f64" => "__builtin_ia32_ceilpd", + "llvm.ceil.v4f32" => "__builtin_ia32_ceilps", + "llvm.fma.v2f64" => "__builtin_ia32_vfmaddpd", + "llvm.fma.v4f64" => "__builtin_ia32_vfmaddpd256", + "llvm.fma.v4f32" => "__builtin_ia32_vfmaddps", + "llvm.fma.v8f32" => "__builtin_ia32_vfmaddps256", + "llvm.ctlz.v16i32" => "__builtin_ia32_vplzcntd_512_mask", + "llvm.ctlz.v8i32" => "__builtin_ia32_vplzcntd_256_mask", + "llvm.ctlz.v4i32" => "__builtin_ia32_vplzcntd_128_mask", + "llvm.ctlz.v8i64" => "__builtin_ia32_vplzcntq_512_mask", + "llvm.ctlz.v4i64" => "__builtin_ia32_vplzcntq_256_mask", + "llvm.ctlz.v2i64" => "__builtin_ia32_vplzcntq_128_mask", + "llvm.ctpop.v32i16" => "__builtin_ia32_vpopcountw_v32hi", + "llvm.x86.fma.vfmsub.sd" => "__builtin_ia32_vfmsubsd3", + "llvm.x86.fma.vfmsub.ss" => "__builtin_ia32_vfmsubss3", + "llvm.x86.fma.vfmsubadd.pd" => "__builtin_ia32_vfmaddsubpd", + "llvm.x86.fma.vfmsubadd.pd.256" => "__builtin_ia32_vfmaddsubpd256", + "llvm.x86.fma.vfmsubadd.ps" => "__builtin_ia32_vfmaddsubps", + "llvm.x86.fma.vfmsubadd.ps.256" => "__builtin_ia32_vfmaddsubps256", + "llvm.x86.fma.vfnmadd.sd" => "__builtin_ia32_vfnmaddsd3", + "llvm.x86.fma.vfnmadd.ss" => "__builtin_ia32_vfnmaddss3", + "llvm.x86.fma.vfnmsub.sd" => "__builtin_ia32_vfnmsubsd3", + "llvm.x86.fma.vfnmsub.ss" => "__builtin_ia32_vfnmsubss3", + "llvm.x86.avx512.conflict.d.512" => "__builtin_ia32_vpconflictsi_512_mask", + "llvm.x86.avx512.conflict.d.256" => "__builtin_ia32_vpconflictsi_256_mask", + "llvm.x86.avx512.conflict.d.128" => "__builtin_ia32_vpconflictsi_128_mask", + "llvm.x86.avx512.conflict.q.512" => "__builtin_ia32_vpconflictdi_512_mask", + "llvm.x86.avx512.conflict.q.256" => "__builtin_ia32_vpconflictdi_256_mask", + "llvm.x86.avx512.conflict.q.128" => "__builtin_ia32_vpconflictdi_128_mask", + "llvm.x86.avx512.vpermi2var.qi.512" => "__builtin_ia32_vpermt2varqi512_mask", + "llvm.x86.avx512.vpermi2var.qi.256" => "__builtin_ia32_vpermt2varqi256_mask", + "llvm.x86.avx512.vpermi2var.qi.128" => "__builtin_ia32_vpermt2varqi128_mask", + "llvm.x86.avx512.permvar.qi.512" => "__builtin_ia32_permvarqi512_mask", + "llvm.x86.avx512.permvar.qi.256" => "__builtin_ia32_permvarqi256_mask", + "llvm.x86.avx512.permvar.qi.128" => "__builtin_ia32_permvarqi128_mask", + "llvm.x86.avx512.pmultishift.qb.512" => "__builtin_ia32_vpmultishiftqb512_mask", + "llvm.x86.avx512.pmultishift.qb.256" => "__builtin_ia32_vpmultishiftqb256_mask", + "llvm.x86.avx512.pmultishift.qb.128" => "__builtin_ia32_vpmultishiftqb128_mask", // The above doc points to unknown builtins for the following, so override them: "llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gathersiv4si", @@ -423,7 +498,14 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.aesni.aesenclast.512" => "__builtin_ia32_vaesenclast_v64qi", "llvm.x86.aesni.aesdec.512" => "__builtin_ia32_vaesdec_v64qi", "llvm.x86.aesni.aesdeclast.512" => "__builtin_ia32_vaesdeclast_v64qi", - "llvm.x86.addcarry.64" => "__builtin_ia32_addcarryx_u64", + "llvm.x86.avx512bf16.cvtne2ps2bf16.128" => "__builtin_ia32_cvtne2ps2bf16_v8hi", + "llvm.x86.avx512bf16.cvtne2ps2bf16.256" => "__builtin_ia32_cvtne2ps2bf16_v16hi", + "llvm.x86.avx512bf16.cvtne2ps2bf16.512" => "__builtin_ia32_cvtne2ps2bf16_v32hi", + "llvm.x86.avx512bf16.cvtneps2bf16.256" => "__builtin_ia32_cvtneps2bf16_v8sf", + "llvm.x86.avx512bf16.cvtneps2bf16.512" => "__builtin_ia32_cvtneps2bf16_v16sf", + "llvm.x86.avx512bf16.dpbf16ps.128" => "__builtin_ia32_dpbf16ps_v4sf", + "llvm.x86.avx512bf16.dpbf16ps.256" => "__builtin_ia32_dpbf16ps_v8sf", + "llvm.x86.avx512bf16.dpbf16ps.512" => "__builtin_ia32_dpbf16ps_v16sf", // NOTE: this file is generated by https://github.com/GuillaumeGomez/llvmint/blob/master/generate_list.py _ => include!("archs.rs"), From fe606eb4449e07e21959a52ae07ca12be3955209 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 4 Jun 2022 23:03:03 -0400 Subject: [PATCH 107/356] Add more SIMD --- src/builder.rs | 8 ++++---- src/intrinsic/llvm.rs | 43 ++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 44 insertions(+), 7 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index b23d12cb0b6b..aefd4eecc0a0 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -275,19 +275,19 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { } fn function_ptr_call(&mut self, func_ptr: RValue<'gcc>, args: &[RValue<'gcc>], _funclet: Option<&Funclet>) -> RValue<'gcc> { - let args = self.check_ptr_call("call", func_ptr, args); + let gcc_func = func_ptr.get_type().dyncast_function_ptr_type().expect("function ptr"); + let func_name = format!("{:?}", func_ptr); + let args = llvm::adjust_intrinsic_arguments(&self, gcc_func, args.into(), &func_name); + let args = self.check_ptr_call("call", func_ptr, &*args); // gccjit requires to use the result of functions, even when it's not used. // That's why we assign the result to a local or call add_eval(). - let gcc_func = func_ptr.get_type().dyncast_function_ptr_type().expect("function ptr"); let return_type = gcc_func.get_return_type(); let void_type = self.context.new_type::<()>(); let current_func = self.block.get_function(); if return_type != void_type { unsafe { RETURN_VALUE_COUNT += 1 }; - let func_name = format!("{:?}", func_ptr); - let args = llvm::adjust_intrinsic_arguments(&self, gcc_func, args, &func_name); let return_value = self.cx.context.new_call_through_ptr(None, func_ptr, &args); let return_value = llvm::adjust_intrinsic_return_value(&self, return_value, &func_name, &args); let result = current_func.new_local(None, return_value.get_type(), &format!("ptrReturnValue{}", unsafe { RETURN_VALUE_COUNT })); diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 7154a89543c2..29387712dae3 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -49,6 +49,10 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc | "__builtin_ia32_prorvd256_mask" | "__builtin_ia32_prorvd128_mask" | "__builtin_ia32_prolvq256_mask" | "__builtin_ia32_prolvq128_mask" | "__builtin_ia32_prorvq256_mask" | "__builtin_ia32_prorvq128_mask" | "__builtin_ia32_permvardi256_mask" | "__builtin_ia32_permvardf512_mask" | "__builtin_ia32_permvardf256_mask" + | "__builtin_ia32_pmulhuw512_mask" | "__builtin_ia32_pmulhw512_mask" | "__builtin_ia32_pmulhrsw512_mask" + | "__builtin_ia32_pmaxuw512_mask" | "__builtin_ia32_pmaxub512_mask" | "__builtin_ia32_pmaxsw512_mask" + | "__builtin_ia32_pmaxsb512_mask" | "__builtin_ia32_pminuw512_mask" | "__builtin_ia32_pminub512_mask" + | "__builtin_ia32_pminsw512_mask" | "__builtin_ia32_pminsb512_mask" => { let mut new_args = args.to_vec(); let arg3_type = gcc_func.get_param_type(2); @@ -63,8 +67,22 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc args = new_args.into(); }, "__builtin_ia32_vplzcntd_512_mask" | "__builtin_ia32_vplzcntd_256_mask" | "__builtin_ia32_vplzcntd_128_mask" - | "__builtin_ia32_vplzcntq_512_mask" | "__builtin_ia32_vplzcntq_256_mask" | "__builtin_ia32_vplzcntq_128_mask" - | "__builtin_ia32_vpconflictsi_512_mask" | "__builtin_ia32_vpconflictsi_256_mask" + | "__builtin_ia32_vplzcntq_512_mask" | "__builtin_ia32_vplzcntq_256_mask" | "__builtin_ia32_vplzcntq_128_mask" => { + let mut new_args = args.to_vec(); + // Remove last arg as it doesn't seem to be used in GCC and is always false. + new_args.pop(); + let arg2_type = gcc_func.get_param_type(1); + let vector_type = arg2_type.dyncast_vector().expect("vector type"); + let zero = builder.context.new_rvalue_zero(vector_type.get_element_type()); + let num_units = vector_type.get_num_units(); + let first_arg = builder.context.new_rvalue_from_vector(None, arg2_type, &vec![zero; num_units]); + new_args.push(first_arg); + let arg3_type = gcc_func.get_param_type(2); + let minus_one = builder.context.new_rvalue_from_int(arg3_type, -1); + new_args.push(minus_one); + args = new_args.into(); + }, + "__builtin_ia32_vpconflictsi_512_mask" | "__builtin_ia32_vpconflictsi_256_mask" | "__builtin_ia32_vpconflictsi_128_mask" | "__builtin_ia32_vpconflictdi_512_mask" | "__builtin_ia32_vpconflictdi_256_mask" | "__builtin_ia32_vpconflictdi_128_mask" => { let mut new_args = args.to_vec(); @@ -177,7 +195,7 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc }, "__builtin_ia32_vpermt2varqi512_mask" | "__builtin_ia32_vpermt2varqi256_mask" | "__builtin_ia32_vpermt2varqi128_mask" => { - let mut new_args = args.to_vec(); + let new_args = args.to_vec(); let arg4_type = gcc_func.get_param_type(3); let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); args = vec![new_args[1], new_args[0], new_args[2], minus_one].into(); @@ -282,6 +300,12 @@ pub fn ignore_arg_cast(func_name: &str, index: usize, args_len: usize) -> bool { }, // NOTE: the LLVM intrinsic receives 3 floats, but the GCC builtin requires 3 vectors. "__builtin_ia32_vfmaddss3_round" | "__builtin_ia32_vfmaddsd3_round" => return true, + "__builtin_ia32_vplzcntd_512_mask" | "__builtin_ia32_vplzcntd_256_mask" | "__builtin_ia32_vplzcntd_128_mask" + | "__builtin_ia32_vplzcntq_512_mask" | "__builtin_ia32_vplzcntq_256_mask" | "__builtin_ia32_vplzcntq_128_mask" => { + if index == args_len - 1 { + return true; + } + }, _ => (), } @@ -418,6 +442,14 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.avx512.pmultishift.qb.512" => "__builtin_ia32_vpmultishiftqb512_mask", "llvm.x86.avx512.pmultishift.qb.256" => "__builtin_ia32_vpmultishiftqb256_mask", "llvm.x86.avx512.pmultishift.qb.128" => "__builtin_ia32_vpmultishiftqb128_mask", + "llvm.ctpop.v16i16" => "__builtin_ia32_vpopcountw_v16hi", + "llvm.ctpop.v8i16" => "__builtin_ia32_vpopcountw_v8hi", + "llvm.ctpop.v64i8" => "__builtin_ia32_vpopcountb_v64qi", + "llvm.ctpop.v32i8" => "__builtin_ia32_vpopcountb_v32qi", + "llvm.ctpop.v16i8" => "__builtin_ia32_vpopcountb_v16qi", + "llvm.x86.avx512.mask.vpshufbitqmb.512" => "__builtin_ia32_vpshufbitqmb512_mask", + "llvm.x86.avx512.mask.vpshufbitqmb.256" => "__builtin_ia32_vpshufbitqmb256_mask", + "llvm.x86.avx512.mask.vpshufbitqmb.128" => "__builtin_ia32_vpshufbitqmb128_mask", // The above doc points to unknown builtins for the following, so override them: "llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gathersiv4si", @@ -506,6 +538,11 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.avx512bf16.dpbf16ps.128" => "__builtin_ia32_dpbf16ps_v4sf", "llvm.x86.avx512bf16.dpbf16ps.256" => "__builtin_ia32_dpbf16ps_v8sf", "llvm.x86.avx512bf16.dpbf16ps.512" => "__builtin_ia32_dpbf16ps_v16sf", + "llvm.x86.pclmulqdq.512" => "__builtin_ia32_vpclmulqdq_v8di", + "llvm.x86.pclmulqdq.256" => "__builtin_ia32_vpclmulqdq_v4di", + "llvm.x86.avx512.pmulhu.w.512" => "__builtin_ia32_pmulhuw512_mask", + "llvm.x86.avx512.pmulh.w.512" => "__builtin_ia32_pmulhw512_mask", + "llvm.x86.avx512.pmul.hr.sw.512" => "__builtin_ia32_pmulhrsw512_mask", // NOTE: this file is generated by https://github.com/GuillaumeGomez/llvmint/blob/master/generate_list.py _ => include!("archs.rs"), From e5a1bb2f59c49a6a741b8ee5b20ad16b93f314c6 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 5 Jun 2022 13:36:17 -0400 Subject: [PATCH 108/356] Add more SIMD --- src/builder.rs | 4 +- src/intrinsic/llvm.rs | 105 ++++++++++++++++++++++++++++++++++++++---- 2 files changed, 99 insertions(+), 10 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index aefd4eecc0a0..3e1f56c183ac 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -277,7 +277,9 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { fn function_ptr_call(&mut self, func_ptr: RValue<'gcc>, args: &[RValue<'gcc>], _funclet: Option<&Funclet>) -> RValue<'gcc> { let gcc_func = func_ptr.get_type().dyncast_function_ptr_type().expect("function ptr"); let func_name = format!("{:?}", func_ptr); + let previous_arg_count = args.len(); let args = llvm::adjust_intrinsic_arguments(&self, gcc_func, args.into(), &func_name); + let args_adjusted = args.len() != previous_arg_count; let args = self.check_ptr_call("call", func_ptr, &*args); // gccjit requires to use the result of functions, even when it's not used. @@ -289,7 +291,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { if return_type != void_type { unsafe { RETURN_VALUE_COUNT += 1 }; let return_value = self.cx.context.new_call_through_ptr(None, func_ptr, &args); - let return_value = llvm::adjust_intrinsic_return_value(&self, return_value, &func_name, &args); + let return_value = llvm::adjust_intrinsic_return_value(&self, return_value, &func_name, &args, args_adjusted); let result = current_func.new_local(None, return_value.get_type(), &format!("ptrReturnValue{}", unsafe { RETURN_VALUE_COUNT })); self.block.add_assignment(None, result, return_value); result.to_rvalue() diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 29387712dae3..af6c121c337c 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -53,6 +53,15 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc | "__builtin_ia32_pmaxuw512_mask" | "__builtin_ia32_pmaxub512_mask" | "__builtin_ia32_pmaxsw512_mask" | "__builtin_ia32_pmaxsb512_mask" | "__builtin_ia32_pminuw512_mask" | "__builtin_ia32_pminub512_mask" | "__builtin_ia32_pminsw512_mask" | "__builtin_ia32_pminsb512_mask" + | "__builtin_ia32_pmaddwd512_mask" | "__builtin_ia32_pmaddubsw512_mask" | "__builtin_ia32_packssdw512_mask" + | "__builtin_ia32_packsswb512_mask" | "__builtin_ia32_packusdw512_mask" | "__builtin_ia32_packuswb512_mask" + | "__builtin_ia32_pavgw512_mask" | "__builtin_ia32_pavgb512_mask" | "__builtin_ia32_psllw512_mask" + | "__builtin_ia32_psllwi512_mask" | "__builtin_ia32_psllv32hi_mask" | "__builtin_ia32_psrlw512_mask" + | "__builtin_ia32_psrlwi512_mask" | "__builtin_ia32_psllv16hi_mask" | "__builtin_ia32_psllv8hi_mask" + | "__builtin_ia32_psrlv32hi_mask" | "__builtin_ia32_psraw512_mask" | "__builtin_ia32_psrawi512_mask" + | "__builtin_ia32_psrlv16hi_mask" | "__builtin_ia32_psrlv8hi_mask" | "__builtin_ia32_psrav32hi_mask" + | "__builtin_ia32_permvarhi512_mask" | "__builtin_ia32_pshufb512_mask" | "__builtin_ia32_psrav16hi_mask" + | "__builtin_ia32_psrav8hi_mask" | "__builtin_ia32_permvarhi256_mask" | "__builtin_ia32_permvarhi128_mask" => { let mut new_args = args.to_vec(); let arg3_type = gcc_func.get_param_type(2); @@ -66,6 +75,19 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc new_args.push(minus_one); args = new_args.into(); }, + "__builtin_ia32_dbpsadbw512_mask" | "__builtin_ia32_dbpsadbw256_mask" | "__builtin_ia32_dbpsadbw128_mask" => { + let mut new_args = args.to_vec(); + let arg4_type = gcc_func.get_param_type(3); + let vector_type = arg4_type.dyncast_vector().expect("vector type"); + let zero = builder.context.new_rvalue_zero(vector_type.get_element_type()); + let num_units = vector_type.get_num_units(); + let first_arg = builder.context.new_rvalue_from_vector(None, arg4_type, &vec![zero; num_units]); + new_args.push(first_arg); + let arg5_type = gcc_func.get_param_type(4); + let minus_one = builder.context.new_rvalue_from_int(arg5_type, -1); + new_args.push(minus_one); + args = new_args.into(); + }, "__builtin_ia32_vplzcntd_512_mask" | "__builtin_ia32_vplzcntd_256_mask" | "__builtin_ia32_vplzcntd_128_mask" | "__builtin_ia32_vplzcntq_512_mask" | "__builtin_ia32_vplzcntq_256_mask" | "__builtin_ia32_vplzcntq_128_mask" => { let mut new_args = args.to_vec(); @@ -186,7 +208,7 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc "__builtin_ia32_stmxcsr" => { args = vec![].into(); }, - "__builtin_ia32_addcarryx_u64" | "__builtin_ia32_sbb_u64" => { + "__builtin_ia32_addcarryx_u64" | "__builtin_ia32_sbb_u64" | "__builtin_ia32_addcarryx_u32" | "__builtin_ia32_sbb_u32" => { let mut new_args = args.to_vec(); let arg2_type = gcc_func.get_param_type(1); let variable = builder.current_func().new_local(None, arg2_type, "addcarryResult"); @@ -194,12 +216,22 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc args = new_args.into(); }, "__builtin_ia32_vpermt2varqi512_mask" | "__builtin_ia32_vpermt2varqi256_mask" - | "__builtin_ia32_vpermt2varqi128_mask" => { + | "__builtin_ia32_vpermt2varqi128_mask" | "__builtin_ia32_vpermt2varhi512_mask" + | "__builtin_ia32_vpermt2varhi256_mask" | "__builtin_ia32_vpermt2varhi128_mask" + => { let new_args = args.to_vec(); let arg4_type = gcc_func.get_param_type(3); let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); args = vec![new_args[1], new_args[0], new_args[2], minus_one].into(); }, + "__builtin_ia32_xrstor" | "__builtin_ia32_xsavec" => { + let new_args = args.to_vec(); + let thirty_two = builder.context.new_rvalue_from_int(new_args[1].get_type(), 32); + let arg2 = new_args[1] << thirty_two | new_args[2]; + let arg2_type = gcc_func.get_param_type(1); + let arg2 = builder.context.new_cast(None, arg2, arg2_type); + args = vec![new_args[0], arg2].into(); + }, _ => (), } } @@ -249,18 +281,24 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc args } -pub fn adjust_intrinsic_return_value<'a, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc, 'tcx>, mut return_value: RValue<'gcc>, func_name: &str, args: &[RValue<'gcc>]) -> RValue<'gcc> { +pub fn adjust_intrinsic_return_value<'a, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc, 'tcx>, mut return_value: RValue<'gcc>, func_name: &str, args: &[RValue<'gcc>], args_adjusted: bool) -> RValue<'gcc> { match func_name { "__builtin_ia32_vfmaddss3_round" | "__builtin_ia32_vfmaddsd3_round" => { let zero = builder.context.new_rvalue_zero(builder.int_type); return_value = builder.context.new_vector_access(None, return_value, zero).to_rvalue(); }, - "__builtin_ia32_addcarryx_u64" | "__builtin_ia32_sbb_u64" => { - let last_arg = args.last().expect("last arg"); - let field1 = builder.context.new_field(None, builder.u8_type, "carryFlag"); - let field2 = builder.context.new_field(None, builder.ulonglong_type, "carryResult"); - let struct_type = builder.context.new_struct_type(None, "addcarryResult", &[field1, field2]); - return_value = builder.context.new_struct_constructor(None, struct_type.as_type(), None, &[return_value, last_arg.dereference(None).to_rvalue()]); + "__builtin_ia32_addcarryx_u64" | "__builtin_ia32_sbb_u64" | "__builtin_ia32_addcarryx_u32" | "__builtin_ia32_sbb_u32" => { + // Both llvm.x86.addcarry.32 and llvm.x86.addcarryx.u32 points to the same GCC builtin, + // but only the former requires adjusting the return value. + // Those 2 LLVM intrinsics differ by their argument count, that's why we check if the + // arguments were adjusted. + if args_adjusted { + let last_arg = args.last().expect("last arg"); + let field1 = builder.context.new_field(None, builder.u8_type, "carryFlag"); + let field2 = builder.context.new_field(None, args[1].get_type(), "carryResult"); + let struct_type = builder.context.new_struct_type(None, "addcarryResult", &[field1, field2]); + return_value = builder.context.new_struct_constructor(None, struct_type.as_type(), None, &[return_value, last_arg.dereference(None).to_rvalue()]); + } }, _ => (), } @@ -450,6 +488,22 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.avx512.mask.vpshufbitqmb.512" => "__builtin_ia32_vpshufbitqmb512_mask", "llvm.x86.avx512.mask.vpshufbitqmb.256" => "__builtin_ia32_vpshufbitqmb256_mask", "llvm.x86.avx512.mask.vpshufbitqmb.128" => "__builtin_ia32_vpshufbitqmb128_mask", + "llvm.x86.avx512.mask.ucmp.w.512" => "__builtin_ia32_ucmpw512_mask", + "llvm.x86.avx512.mask.ucmp.w.256" => "__builtin_ia32_ucmpw256_mask", + "llvm.x86.avx512.mask.ucmp.w.128" => "__builtin_ia32_ucmpw128_mask", + "llvm.x86.avx512.mask.ucmp.b.512" => "__builtin_ia32_ucmpb512_mask", + "llvm.x86.avx512.mask.ucmp.b.256" => "__builtin_ia32_ucmpb256_mask", + "llvm.x86.avx512.mask.ucmp.b.128" => "__builtin_ia32_ucmpb128_mask", + "llvm.x86.avx512.mask.cmp.w.512" => "__builtin_ia32_cmpw512_mask", + "llvm.x86.avx512.mask.cmp.w.256" => "__builtin_ia32_cmpw256_mask", + "llvm.x86.avx512.mask.cmp.w.128" => "__builtin_ia32_cmpw128_mask", + "llvm.x86.avx512.mask.cmp.b.512" => "__builtin_ia32_cmpb512_mask", + "llvm.x86.avx512.mask.cmp.b.256" => "__builtin_ia32_cmpb256_mask", + "llvm.x86.avx512.mask.cmp.b.128" => "__builtin_ia32_cmpb128_mask", + "llvm.x86.xrstor" => "__builtin_ia32_xrstor", + "llvm.x86.xsavec" => "__builtin_ia32_xsavec", + "llvm.x86.addcarry.32" => "__builtin_ia32_addcarryx_u32", + "llvm.x86.subborrow.32" => "__builtin_ia32_sbb_u32", // The above doc points to unknown builtins for the following, so override them: "llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gathersiv4si", @@ -543,6 +597,39 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.avx512.pmulhu.w.512" => "__builtin_ia32_pmulhuw512_mask", "llvm.x86.avx512.pmulh.w.512" => "__builtin_ia32_pmulhw512_mask", "llvm.x86.avx512.pmul.hr.sw.512" => "__builtin_ia32_pmulhrsw512_mask", + "llvm.x86.avx512.pmaddw.d.512" => "__builtin_ia32_pmaddwd512_mask", + "llvm.x86.avx512.pmaddubs.w.512" => "__builtin_ia32_pmaddubsw512_mask", + "llvm.x86.avx512.packssdw.512" => "__builtin_ia32_packssdw512_mask", + "llvm.x86.avx512.packsswb.512" => "__builtin_ia32_packsswb512_mask", + "llvm.x86.avx512.packusdw.512" => "__builtin_ia32_packusdw512_mask", + "llvm.x86.avx512.packuswb.512" => "__builtin_ia32_packuswb512_mask", + "llvm.x86.avx512.pavg.w.512" => "__builtin_ia32_pavgw512_mask", + "llvm.x86.avx512.pavg.b.512" => "__builtin_ia32_pavgb512_mask", + "llvm.x86.avx512.psll.w.512" => "__builtin_ia32_psllw512_mask", + "llvm.x86.avx512.pslli.w.512" => "__builtin_ia32_psllwi512_mask", + "llvm.x86.avx512.psllv.w.512" => "__builtin_ia32_psllv32hi_mask", + "llvm.x86.avx512.psllv.w.256" => "__builtin_ia32_psllv16hi_mask", + "llvm.x86.avx512.psllv.w.128" => "__builtin_ia32_psllv8hi_mask", + "llvm.x86.avx512.psrl.w.512" => "__builtin_ia32_psrlw512_mask", + "llvm.x86.avx512.psrli.w.512" => "__builtin_ia32_psrlwi512_mask", + "llvm.x86.avx512.psrlv.w.512" => "__builtin_ia32_psrlv32hi_mask", + "llvm.x86.avx512.psrlv.w.256" => "__builtin_ia32_psrlv16hi_mask", + "llvm.x86.avx512.psrlv.w.128" => "__builtin_ia32_psrlv8hi_mask", + "llvm.x86.avx512.psra.w.512" => "__builtin_ia32_psraw512_mask", + "llvm.x86.avx512.psrai.w.512" => "__builtin_ia32_psrawi512_mask", + "llvm.x86.avx512.psrav.w.512" => "__builtin_ia32_psrav32hi_mask", + "llvm.x86.avx512.psrav.w.256" => "__builtin_ia32_psrav16hi_mask", + "llvm.x86.avx512.psrav.w.128" => "__builtin_ia32_psrav8hi_mask", + "llvm.x86.avx512.vpermi2var.hi.512" => "__builtin_ia32_vpermt2varhi512_mask", + "llvm.x86.avx512.vpermi2var.hi.256" => "__builtin_ia32_vpermt2varhi256_mask", + "llvm.x86.avx512.vpermi2var.hi.128" => "__builtin_ia32_vpermt2varhi128_mask", + "llvm.x86.avx512.permvar.hi.512" => "__builtin_ia32_permvarhi512_mask", + "llvm.x86.avx512.permvar.hi.256" => "__builtin_ia32_permvarhi256_mask", + "llvm.x86.avx512.permvar.hi.128" => "__builtin_ia32_permvarhi128_mask", + "llvm.x86.avx512.pshuf.b.512" => "__builtin_ia32_pshufb512_mask", + "llvm.x86.avx512.dbpsadbw.512" => "__builtin_ia32_dbpsadbw512_mask", + "llvm.x86.avx512.dbpsadbw.256" => "__builtin_ia32_dbpsadbw256_mask", + "llvm.x86.avx512.dbpsadbw.128" => "__builtin_ia32_dbpsadbw128_mask", // NOTE: this file is generated by https://github.com/GuillaumeGomez/llvmint/blob/master/generate_list.py _ => include!("archs.rs"), From b55bd956dc2ad488b890892e4d336ff6cdf3b128 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 5 Jun 2022 17:16:27 -0400 Subject: [PATCH 109/356] Add more SIMD --- src/intrinsic/llvm.rs | 46 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index af6c121c337c..14a7eaf49bbd 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -171,7 +171,10 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc new_args.push(last_arg); args = new_args.into(); }, - "__builtin_ia32_vfmaddsubps512_mask" | "__builtin_ia32_vfmaddsubpd512_mask" => { + "__builtin_ia32_vfmaddsubps512_mask" | "__builtin_ia32_vfmaddsubpd512_mask" | "__builtin_ia32_vpmadd52huq512_mask" + | "__builtin_ia32_vpmadd52luq512_mask" | "__builtin_ia32_vpmadd52huq256_mask" | "__builtin_ia32_vpmadd52luq256_mask" + | "__builtin_ia32_vpmadd52huq128_mask" + => { let mut new_args = args.to_vec(); let last_arg = new_args.pop().expect("last arg"); let arg4_type = gcc_func.get_param_type(3); @@ -504,6 +507,42 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.xsavec" => "__builtin_ia32_xsavec", "llvm.x86.addcarry.32" => "__builtin_ia32_addcarryx_u32", "llvm.x86.subborrow.32" => "__builtin_ia32_sbb_u32", + "llvm.x86.avx512.mask.compress.store.w.512" => "__builtin_ia32_compressstoreuhi512_mask", + "llvm.x86.avx512.mask.compress.store.w.256" => "__builtin_ia32_compressstoreuhi256_mask", + "llvm.x86.avx512.mask.compress.store.w.128" => "__builtin_ia32_compressstoreuhi128_mask", + "llvm.x86.avx512.mask.compress.store.b.512" => "__builtin_ia32_compressstoreuqi512_mask", + "llvm.x86.avx512.mask.compress.store.b.256" => "__builtin_ia32_compressstoreuqi256_mask", + "llvm.x86.avx512.mask.compress.store.b.128" => "__builtin_ia32_compressstoreuqi128_mask", + "llvm.x86.avx512.mask.compress.w.512" => "__builtin_ia32_compressstoreuhi512_mask", + "llvm.x86.avx512.mask.compress.w.256" => "__builtin_ia32_compresshi256_mask", + "llvm.x86.avx512.mask.compress.w.128" => "__builtin_ia32_compresshi128_mask", + "llvm.x86.avx512.mask.compress.b.512" => "__builtin_ia32_compressstoreuqi512_mask", + "llvm.x86.avx512.mask.compress.b.256" => "__builtin_ia32_compressqi256_mask", + "llvm.x86.avx512.mask.compress.b.128" => "__builtin_ia32_compressqi128_mask", + "llvm.x86.avx512.mask.expand.w.512" => "__builtin_ia32_expandhi512_mask", + "llvm.x86.avx512.mask.expand.w.256" => "__builtin_ia32_expandhi256_mask", + "llvm.x86.avx512.mask.expand.w.128" => "__builtin_ia32_expandhi128_mask", + "llvm.x86.avx512.mask.expand.b.512" => "__builtin_ia32_expandqi512_mask", + "llvm.x86.avx512.mask.expand.b.256" => "__builtin_ia32_expandqi256_mask", + "llvm.x86.avx512.mask.expand.b.128" => "__builtin_ia32_expandqi128_mask", + "llvm.fshl.v8i64" => "__builtin_ia32_vpshldv_v8di", + "llvm.fshl.v4i64" => "__builtin_ia32_vpshldv_v4di", + "llvm.fshl.v2i64" => "__builtin_ia32_vpshldv_v2di", + "llvm.fshl.v16i32" => "__builtin_ia32_vpshldv_v16si", + "llvm.fshl.v8i32" => "__builtin_ia32_vpshldv_v8si", + "llvm.fshl.v4i32" => "__builtin_ia32_vpshldv_v4si", + "llvm.fshl.v32i16" => "__builtin_ia32_vpshldv_v32hi", + "llvm.fshl.v16i16" => "__builtin_ia32_vpshldv_v16hi", + "llvm.fshl.v8i16" => "__builtin_ia32_vpshldv_v8hi", + "llvm.fshr.v8i64" => "__builtin_ia32_vpshrdv_v8di", + "llvm.fshr.v4i64" => "__builtin_ia32_vpshrdv_v4di", + "llvm.fshr.v2i64" => "__builtin_ia32_vpshrdv_v2di", + "llvm.fshr.v16i32" => "__builtin_ia32_vpshrdv_v16si", + "llvm.fshr.v8i32" => "__builtin_ia32_vpshrdv_v8si", + "llvm.fshr.v4i32" => "__builtin_ia32_vpshrdv_v4si", + "llvm.fshr.v32i16" => "__builtin_ia32_vpshrdv_v32hi", + "llvm.fshr.v16i16" => "__builtin_ia32_vpshrdv_v16hi", + "llvm.fshr.v8i16" => "__builtin_ia32_vpshrdv_v8hi", // The above doc points to unknown builtins for the following, so override them: "llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gathersiv4si", @@ -630,6 +669,11 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.avx512.dbpsadbw.512" => "__builtin_ia32_dbpsadbw512_mask", "llvm.x86.avx512.dbpsadbw.256" => "__builtin_ia32_dbpsadbw256_mask", "llvm.x86.avx512.dbpsadbw.128" => "__builtin_ia32_dbpsadbw128_mask", + "llvm.x86.avx512.vpmadd52h.uq.512" => "__builtin_ia32_vpmadd52huq512_mask", + "llvm.x86.avx512.vpmadd52l.uq.512" => "__builtin_ia32_vpmadd52luq512_mask", + "llvm.x86.avx512.vpmadd52h.uq.256" => "__builtin_ia32_vpmadd52huq256_mask", + "llvm.x86.avx512.vpmadd52l.uq.256" => "__builtin_ia32_vpmadd52luq256_mask", + "llvm.x86.avx512.vpmadd52h.uq.128" => "__builtin_ia32_vpmadd52huq128_mask", // NOTE: this file is generated by https://github.com/GuillaumeGomez/llvmint/blob/master/generate_list.py _ => include!("archs.rs"), From 13fa30c6c396a5ffe91423a028dc51547ec68d42 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 5 Jun 2022 18:53:30 -0400 Subject: [PATCH 110/356] Add more SIMD --- src/intrinsic/llvm.rs | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 14a7eaf49bbd..42cf06c8c7ab 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -171,10 +171,7 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc new_args.push(last_arg); args = new_args.into(); }, - "__builtin_ia32_vfmaddsubps512_mask" | "__builtin_ia32_vfmaddsubpd512_mask" | "__builtin_ia32_vpmadd52huq512_mask" - | "__builtin_ia32_vpmadd52luq512_mask" | "__builtin_ia32_vpmadd52huq256_mask" | "__builtin_ia32_vpmadd52luq256_mask" - | "__builtin_ia32_vpmadd52huq128_mask" - => { + "__builtin_ia32_vfmaddsubps512_mask" | "__builtin_ia32_vfmaddsubpd512_mask" => { let mut new_args = args.to_vec(); let last_arg = new_args.pop().expect("last arg"); let arg4_type = gcc_func.get_param_type(3); @@ -188,7 +185,10 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc | "__builtin_ia32_vpermi2varq256_mask" | "__builtin_ia32_vpermi2varq128_mask" | "__builtin_ia32_vpermi2varps512_mask" | "__builtin_ia32_vpermi2varps256_mask" | "__builtin_ia32_vpermi2varps128_mask" | "__builtin_ia32_vpermi2varpd512_mask" - | "__builtin_ia32_vpermi2varpd256_mask" | "__builtin_ia32_vpermi2varpd128_mask" => { + | "__builtin_ia32_vpermi2varpd256_mask" | "__builtin_ia32_vpermi2varpd128_mask" | "__builtin_ia32_vpmadd52huq512_mask" + | "__builtin_ia32_vpmadd52luq512_mask" | "__builtin_ia32_vpmadd52huq256_mask" | "__builtin_ia32_vpmadd52luq256_mask" + | "__builtin_ia32_vpmadd52huq128_mask" + => { let mut new_args = args.to_vec(); let arg4_type = gcc_func.get_param_type(3); let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); @@ -513,10 +513,10 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.avx512.mask.compress.store.b.512" => "__builtin_ia32_compressstoreuqi512_mask", "llvm.x86.avx512.mask.compress.store.b.256" => "__builtin_ia32_compressstoreuqi256_mask", "llvm.x86.avx512.mask.compress.store.b.128" => "__builtin_ia32_compressstoreuqi128_mask", - "llvm.x86.avx512.mask.compress.w.512" => "__builtin_ia32_compressstoreuhi512_mask", + "llvm.x86.avx512.mask.compress.w.512" => "__builtin_ia32_compresshi512_mask", "llvm.x86.avx512.mask.compress.w.256" => "__builtin_ia32_compresshi256_mask", "llvm.x86.avx512.mask.compress.w.128" => "__builtin_ia32_compresshi128_mask", - "llvm.x86.avx512.mask.compress.b.512" => "__builtin_ia32_compressstoreuqi512_mask", + "llvm.x86.avx512.mask.compress.b.512" => "__builtin_ia32_compressqi512_mask", "llvm.x86.avx512.mask.compress.b.256" => "__builtin_ia32_compressqi256_mask", "llvm.x86.avx512.mask.compress.b.128" => "__builtin_ia32_compressqi128_mask", "llvm.x86.avx512.mask.expand.w.512" => "__builtin_ia32_expandhi512_mask", @@ -674,6 +674,18 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.avx512.vpmadd52h.uq.256" => "__builtin_ia32_vpmadd52huq256_mask", "llvm.x86.avx512.vpmadd52l.uq.256" => "__builtin_ia32_vpmadd52luq256_mask", "llvm.x86.avx512.vpmadd52h.uq.128" => "__builtin_ia32_vpmadd52huq128_mask", + "llvm.x86.avx512.vpdpwssd.512" => "__builtin_ia32_vpdpwssd_v16si", + "llvm.x86.avx512.vpdpwssd.256" => "__builtin_ia32_vpdpwssd_v8si", + "llvm.x86.avx512.vpdpwssd.128" => "__builtin_ia32_vpdpwssd_v4si", + "llvm.x86.avx512.vpdpwssds.512" => "__builtin_ia32_vpdpwssds_v16si", + "llvm.x86.avx512.vpdpwssds.256" => "__builtin_ia32_vpdpwssds_v8si", + "llvm.x86.avx512.vpdpwssds.128" => "__builtin_ia32_vpdpwssds_v4si", + "llvm.x86.avx512.vpdpbusd.512" => "__builtin_ia32_vpdpbusd_v16si", + "llvm.x86.avx512.vpdpbusd.256" => "__builtin_ia32_vpdpbusd_v8si", + "llvm.x86.avx512.vpdpbusd.128" => "__builtin_ia32_vpdpbusd_v4si", + "llvm.x86.avx512.vpdpbusds.512" => "__builtin_ia32_vpdpbusds_v16si", + "llvm.x86.avx512.vpdpbusds.256" => "__builtin_ia32_vpdpbusds_v8si", + "llvm.x86.avx512.vpdpbusds.128" => "__builtin_ia32_vpdpbusds_v4si", // NOTE: this file is generated by https://github.com/GuillaumeGomez/llvmint/blob/master/generate_list.py _ => include!("archs.rs"), From 2ba5845c520c3fe6558b7047097a89003284bf9a Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 5 Jun 2022 19:00:34 -0400 Subject: [PATCH 111/356] Update Cargo files --- Cargo.toml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index 0e41bec8b762..211d19a8dc89 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -22,10 +22,10 @@ default = ["master"] master = ["gccjit/master"] [dependencies] -#gccjit = { git = "https://github.com/antoyo/gccjit.rs" } +gccjit = { git = "https://github.com/antoyo/gccjit.rs" } # Local copy. -gccjit = { path = "../gccjit.rs" } +#gccjit = { path = "../gccjit.rs" } target-lexicon = "0.10.0" From 558f124f96ab3e9bf2b5c4750bd88225712c27fe Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Thu, 9 Jun 2022 14:25:35 +0200 Subject: [PATCH 112/356] Use `llvm-tblgen` tool to generate more and better intrinsics output --- tools/generate_intrinsics.py | 91 ++++++++++++++++-------------------- 1 file changed, 40 insertions(+), 51 deletions(-) diff --git a/tools/generate_intrinsics.py b/tools/generate_intrinsics.py index 849c6e9c9816..e13e8b146698 100644 --- a/tools/generate_intrinsics.py +++ b/tools/generate_intrinsics.py @@ -13,7 +13,7 @@ def run_command(command, cwd=None): sys.exit(1) -def clone_repository(repo_name, path, repo_url, sub_path=None): +def clone_repository(repo_name, path, repo_url, sub_paths=None): if os.path.exists(path): while True: choice = input("There is already a `{}` folder, do you want to update it? [y/N]".format(path)) @@ -27,12 +27,12 @@ def clone_repository(repo_name, path, repo_url, sub_path=None): else: print("Didn't understand answer...") print("Cloning {} repository...".format(repo_name)) - if sub_path is None: + if sub_paths is None: run_command(["git", "clone", repo_url, "--depth", "1", path]) else: run_command(["git", "clone", repo_url, "--filter=tree:0", "--no-checkout", path]) run_command(["git", "sparse-checkout", "init"], cwd=path) - run_command(["git", "sparse-checkout", "set", "add", sub_path], cwd=path) + run_command(["git", "sparse-checkout", "set", *sub_paths], cwd=path) run_command(["git", "checkout"], cwd=path) @@ -40,56 +40,45 @@ def append_intrinsic(array, intrinsic_name, translation): array.append((intrinsic_name, translation)) -def extract_instrinsics(intrinsics, file): - print("Extracting intrinsics from `{}`...".format(file)) - with open(file, "r", encoding="utf8") as f: - content = f.read() - - lines = content.splitlines() - pos = 0 - current_arch = None - while pos < len(lines): - line = lines[pos].strip() - if line.startswith("let TargetPrefix ="): - current_arch = line.split('"')[1].strip() - if len(current_arch) == 0: - current_arch = None - elif current_arch is None: - pass - elif line == "}": - current_arch = None - elif line.startswith("def "): - content = "" - while not content.endswith(";") and not content.endswith("}") and pos < len(lines): - line = lines[pos].split(" // ")[0].strip() - content += line - pos += 1 - entries = re.findall('GCCBuiltin<"(\\w+)">', content) - if len(entries) > 0: - intrinsic = content.split("def ")[1].strip().split(":")[0].strip() - intrinsic = intrinsic.split("_") - if len(intrinsic) < 2 or intrinsic[0] != "int": - continue - intrinsic[0] = "llvm" - intrinsic = ".".join(intrinsic) - if current_arch not in intrinsics: - intrinsics[current_arch] = [] - for entry in entries: - append_intrinsic(intrinsics[current_arch], intrinsic, entry) - continue - pos += 1 - continue - print("Done!") +def convert_to_string(content): + if content.__class__.__name__ == 'bytes': + return content.decode('utf-8') + return content def extract_instrinsics_from_llvm(llvm_path, intrinsics): - files = [] - intrinsics_path = os.path.join(llvm_path, "llvm/include/llvm/IR") - for (dirpath, dirnames, filenames) in walk(intrinsics_path): - files.extend([os.path.join(intrinsics_path, f) for f in filenames if f.endswith(".td")]) - - for file in files: - extract_instrinsics(intrinsics, file) + p = subprocess.Popen( + ["llvm-tblgen", "llvm/IR/Intrinsics.td"], + cwd=os.path.join(llvm_path, "llvm/include"), + stdout=subprocess.PIPE) + output, err = p.communicate() + lines = convert_to_string(output).splitlines() + pos = 0 + while pos < len(lines): + line = lines[pos] + if not line.startswith("def "): + pos += 1 + continue + intrinsic = line.split(" ")[1].strip() + content = line + while pos < len(lines): + line = lines[pos].split(" // ")[0].strip() + content += line + pos += 1 + if line == "}": + break + entries = re.findall('string GCCBuiltinName = "(\\w+)";', content) + current_arch = re.findall('string TargetPrefix = "(\\w+)";', content) + if len(entries) == 1 and len(current_arch) == 1: + current_arch = current_arch[0] + intrinsic = intrinsic.split("_") + if len(intrinsic) < 2 or intrinsic[0] != "int": + continue + intrinsic[0] = "llvm" + intrinsic = ".".join(intrinsic) + if current_arch not in intrinsics: + intrinsics[current_arch] = [] + append_intrinsic(intrinsics[current_arch], intrinsic, entries[0]) def append_translation(json_data, p, array): @@ -219,7 +208,7 @@ def main(): "llvm-project", llvm_path, "https://github.com/llvm/llvm-project", - sub_path="llvm/include/llvm/IR", + sub_paths=["llvm/include/llvm/IR", "llvm/include/llvm/CodeGen/"], ) clone_repository( "llvmint", From c66055c193b0df2bbb5fbb21d17eca7c8d7ac5a5 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Thu, 9 Jun 2022 14:25:48 +0200 Subject: [PATCH 113/356] Generate new intrinsics --- src/intrinsic/archs.rs | 2247 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 2228 insertions(+), 19 deletions(-) diff --git a/src/intrinsic/archs.rs b/src/intrinsic/archs.rs index fb6c38fa0726..9375f0fc1ad5 100644 --- a/src/intrinsic/archs.rs +++ b/src/intrinsic/archs.rs @@ -93,6 +93,37 @@ match name { "llvm.amdgcn.lerp" => "__builtin_amdgcn_lerp", "llvm.amdgcn.mbcnt.hi" => "__builtin_amdgcn_mbcnt_hi", "llvm.amdgcn.mbcnt.lo" => "__builtin_amdgcn_mbcnt_lo", + "llvm.amdgcn.mfma.f32.16x16x16bf16.1k" => "__builtin_amdgcn_mfma_f32_16x16x16bf16_1k", + "llvm.amdgcn.mfma.f32.16x16x16f16" => "__builtin_amdgcn_mfma_f32_16x16x16f16", + "llvm.amdgcn.mfma.f32.16x16x1f32" => "__builtin_amdgcn_mfma_f32_16x16x1f32", + "llvm.amdgcn.mfma.f32.16x16x2bf16" => "__builtin_amdgcn_mfma_f32_16x16x2bf16", + "llvm.amdgcn.mfma.f32.16x16x4bf16.1k" => "__builtin_amdgcn_mfma_f32_16x16x4bf16_1k", + "llvm.amdgcn.mfma.f32.16x16x4f16" => "__builtin_amdgcn_mfma_f32_16x16x4f16", + "llvm.amdgcn.mfma.f32.16x16x4f32" => "__builtin_amdgcn_mfma_f32_16x16x4f32", + "llvm.amdgcn.mfma.f32.16x16x8.xf32" => "__builtin_amdgcn_mfma_f32_16x16x8_xf32", + "llvm.amdgcn.mfma.f32.16x16x8bf16" => "__builtin_amdgcn_mfma_f32_16x16x8bf16", + "llvm.amdgcn.mfma.f32.32x32x1f32" => "__builtin_amdgcn_mfma_f32_32x32x1f32", + "llvm.amdgcn.mfma.f32.32x32x2bf16" => "__builtin_amdgcn_mfma_f32_32x32x2bf16", + "llvm.amdgcn.mfma.f32.32x32x2f32" => "__builtin_amdgcn_mfma_f32_32x32x2f32", + "llvm.amdgcn.mfma.f32.32x32x4.xf32" => "__builtin_amdgcn_mfma_f32_32x32x4_xf32", + "llvm.amdgcn.mfma.f32.32x32x4bf16" => "__builtin_amdgcn_mfma_f32_32x32x4bf16", + "llvm.amdgcn.mfma.f32.32x32x4bf16.1k" => "__builtin_amdgcn_mfma_f32_32x32x4bf16_1k", + "llvm.amdgcn.mfma.f32.32x32x4f16" => "__builtin_amdgcn_mfma_f32_32x32x4f16", + "llvm.amdgcn.mfma.f32.32x32x8bf16.1k" => "__builtin_amdgcn_mfma_f32_32x32x8bf16_1k", + "llvm.amdgcn.mfma.f32.32x32x8f16" => "__builtin_amdgcn_mfma_f32_32x32x8f16", + "llvm.amdgcn.mfma.f32.4x4x1f32" => "__builtin_amdgcn_mfma_f32_4x4x1f32", + "llvm.amdgcn.mfma.f32.4x4x2bf16" => "__builtin_amdgcn_mfma_f32_4x4x2bf16", + "llvm.amdgcn.mfma.f32.4x4x4bf16.1k" => "__builtin_amdgcn_mfma_f32_4x4x4bf16_1k", + "llvm.amdgcn.mfma.f32.4x4x4f16" => "__builtin_amdgcn_mfma_f32_4x4x4f16", + "llvm.amdgcn.mfma.f64.16x16x4f64" => "__builtin_amdgcn_mfma_f64_16x16x4f64", + "llvm.amdgcn.mfma.f64.4x4x4f64" => "__builtin_amdgcn_mfma_f64_4x4x4f64", + "llvm.amdgcn.mfma.i32.16x16x16i8" => "__builtin_amdgcn_mfma_i32_16x16x16i8", + "llvm.amdgcn.mfma.i32.16x16x32.i8" => "__builtin_amdgcn_mfma_i32_16x16x32_i8", + "llvm.amdgcn.mfma.i32.16x16x4i8" => "__builtin_amdgcn_mfma_i32_16x16x4i8", + "llvm.amdgcn.mfma.i32.32x32x16.i8" => "__builtin_amdgcn_mfma_i32_32x32x16_i8", + "llvm.amdgcn.mfma.i32.32x32x4i8" => "__builtin_amdgcn_mfma_i32_32x32x4i8", + "llvm.amdgcn.mfma.i32.32x32x8i8" => "__builtin_amdgcn_mfma_i32_32x32x8i8", + "llvm.amdgcn.mfma.i32.4x4x4i8" => "__builtin_amdgcn_mfma_i32_4x4x4i8", "llvm.amdgcn.mqsad.pk.u16.u8" => "__builtin_amdgcn_mqsad_pk_u16_u8", "llvm.amdgcn.mqsad.u32.u8" => "__builtin_amdgcn_mqsad_u32_u8", "llvm.amdgcn.msad.u8" => "__builtin_amdgcn_msad_u8", @@ -130,11 +161,20 @@ match name { "llvm.amdgcn.sdot2" => "__builtin_amdgcn_sdot2", "llvm.amdgcn.sdot4" => "__builtin_amdgcn_sdot4", "llvm.amdgcn.sdot8" => "__builtin_amdgcn_sdot8", + "llvm.amdgcn.smfmac.f32.16x16x32.bf16" => "__builtin_amdgcn_smfmac_f32_16x16x32_bf16", + "llvm.amdgcn.smfmac.f32.16x16x32.f16" => "__builtin_amdgcn_smfmac_f32_16x16x32_f16", + "llvm.amdgcn.smfmac.f32.32x32x16.bf16" => "__builtin_amdgcn_smfmac_f32_32x32x16_bf16", + "llvm.amdgcn.smfmac.f32.32x32x16.f16" => "__builtin_amdgcn_smfmac_f32_32x32x16_f16", + "llvm.amdgcn.smfmac.i32.16x16x64.i8" => "__builtin_amdgcn_smfmac_i32_16x16x64_i8", + "llvm.amdgcn.smfmac.i32.32x32x32.i8" => "__builtin_amdgcn_smfmac_i32_32x32x32_i8", "llvm.amdgcn.udot2" => "__builtin_amdgcn_udot2", "llvm.amdgcn.udot4" => "__builtin_amdgcn_udot4", "llvm.amdgcn.udot8" => "__builtin_amdgcn_udot8", "llvm.amdgcn.wave.barrier" => "__builtin_amdgcn_wave_barrier", "llvm.amdgcn.wavefrontsize" => "__builtin_amdgcn_wavefrontsize", + "llvm.amdgcn.workgroup.id.x" => "__builtin_amdgcn_workgroup_id_x", + "llvm.amdgcn.workgroup.id.y" => "__builtin_amdgcn_workgroup_id_y", + "llvm.amdgcn.workgroup.id.z" => "__builtin_amdgcn_workgroup_id_z", "llvm.amdgcn.writelane" => "__builtin_amdgcn_writelane", // arm "llvm.arm.cdp" => "__builtin_arm_cdp", @@ -459,6 +499,11 @@ match name { "llvm.hexagon.A4.vrminuw" => "__builtin_HEXAGON_A4_vrminuw", "llvm.hexagon.A4.vrminw" => "__builtin_HEXAGON_A4_vrminw", "llvm.hexagon.A5.vaddhubs" => "__builtin_HEXAGON_A5_vaddhubs", + "llvm.hexagon.A6.vcmpbeq.notany" => "__builtin_HEXAGON_A6_vcmpbeq_notany", + "llvm.hexagon.A7.clip" => "__builtin_HEXAGON_A7_clip", + "llvm.hexagon.A7.croundd.ri" => "__builtin_HEXAGON_A7_croundd_ri", + "llvm.hexagon.A7.croundd.rr" => "__builtin_HEXAGON_A7_croundd_rr", + "llvm.hexagon.A7.vclip" => "__builtin_HEXAGON_A7_vclip", "llvm.hexagon.C2.all8" => "__builtin_HEXAGON_C2_all8", "llvm.hexagon.C2.and" => "__builtin_HEXAGON_C2_and", "llvm.hexagon.C2.andn" => "__builtin_HEXAGON_C2_andn", @@ -557,6 +602,10 @@ match name { "llvm.hexagon.F2.dfmax" => "__builtin_HEXAGON_F2_dfmax", "llvm.hexagon.F2.dfmin" => "__builtin_HEXAGON_F2_dfmin", "llvm.hexagon.F2.dfmpy" => "__builtin_HEXAGON_F2_dfmpy", + "llvm.hexagon.F2.dfmpyfix" => "__builtin_HEXAGON_F2_dfmpyfix", + "llvm.hexagon.F2.dfmpyhh" => "__builtin_HEXAGON_F2_dfmpyhh", + "llvm.hexagon.F2.dfmpylh" => "__builtin_HEXAGON_F2_dfmpylh", + "llvm.hexagon.F2.dfmpyll" => "__builtin_HEXAGON_F2_dfmpyll", "llvm.hexagon.F2.dfsub" => "__builtin_HEXAGON_F2_dfsub", "llvm.hexagon.F2.sfadd" => "__builtin_HEXAGON_F2_sfadd", "llvm.hexagon.F2.sfclass" => "__builtin_HEXAGON_F2_sfclass", @@ -578,6 +627,8 @@ match name { "llvm.hexagon.F2.sfmin" => "__builtin_HEXAGON_F2_sfmin", "llvm.hexagon.F2.sfmpy" => "__builtin_HEXAGON_F2_sfmpy", "llvm.hexagon.F2.sfsub" => "__builtin_HEXAGON_F2_sfsub", + "llvm.hexagon.L2.loadw.locked" => "__builtin_HEXAGON_L2_loadw_locked", + "llvm.hexagon.L4.loadd.locked" => "__builtin_HEXAGON_L4_loadd_locked", "llvm.hexagon.M2.acci" => "__builtin_HEXAGON_M2_acci", "llvm.hexagon.M2.accii" => "__builtin_HEXAGON_M2_accii", "llvm.hexagon.M2.cmaci.s0" => "__builtin_HEXAGON_M2_cmaci_s0", @@ -646,6 +697,7 @@ match name { "llvm.hexagon.M2.mmpyul.rs1" => "__builtin_HEXAGON_M2_mmpyul_rs1", "llvm.hexagon.M2.mmpyul.s0" => "__builtin_HEXAGON_M2_mmpyul_s0", "llvm.hexagon.M2.mmpyul.s1" => "__builtin_HEXAGON_M2_mmpyul_s1", + "llvm.hexagon.M2.mnaci" => "__builtin_HEXAGON_M2_mnaci", "llvm.hexagon.M2.mpy.acc.hh.s0" => "__builtin_HEXAGON_M2_mpy_acc_hh_s0", "llvm.hexagon.M2.mpy.acc.hh.s1" => "__builtin_HEXAGON_M2_mpy_acc_hh_s1", "llvm.hexagon.M2.mpy.acc.hl.s0" => "__builtin_HEXAGON_M2_mpy_acc_hl_s0", @@ -894,6 +946,24 @@ match name { "llvm.hexagon.M5.vrmpybuu" => "__builtin_HEXAGON_M5_vrmpybuu", "llvm.hexagon.M6.vabsdiffb" => "__builtin_HEXAGON_M6_vabsdiffb", "llvm.hexagon.M6.vabsdiffub" => "__builtin_HEXAGON_M6_vabsdiffub", + "llvm.hexagon.M7.dcmpyiw" => "__builtin_HEXAGON_M7_dcmpyiw", + "llvm.hexagon.M7.dcmpyiw.acc" => "__builtin_HEXAGON_M7_dcmpyiw_acc", + "llvm.hexagon.M7.dcmpyiwc" => "__builtin_HEXAGON_M7_dcmpyiwc", + "llvm.hexagon.M7.dcmpyiwc.acc" => "__builtin_HEXAGON_M7_dcmpyiwc_acc", + "llvm.hexagon.M7.dcmpyrw" => "__builtin_HEXAGON_M7_dcmpyrw", + "llvm.hexagon.M7.dcmpyrw.acc" => "__builtin_HEXAGON_M7_dcmpyrw_acc", + "llvm.hexagon.M7.dcmpyrwc" => "__builtin_HEXAGON_M7_dcmpyrwc", + "llvm.hexagon.M7.dcmpyrwc.acc" => "__builtin_HEXAGON_M7_dcmpyrwc_acc", + "llvm.hexagon.M7.vdmpy" => "__builtin_HEXAGON_M7_vdmpy", + "llvm.hexagon.M7.vdmpy.acc" => "__builtin_HEXAGON_M7_vdmpy_acc", + "llvm.hexagon.M7.wcmpyiw" => "__builtin_HEXAGON_M7_wcmpyiw", + "llvm.hexagon.M7.wcmpyiw.rnd" => "__builtin_HEXAGON_M7_wcmpyiw_rnd", + "llvm.hexagon.M7.wcmpyiwc" => "__builtin_HEXAGON_M7_wcmpyiwc", + "llvm.hexagon.M7.wcmpyiwc.rnd" => "__builtin_HEXAGON_M7_wcmpyiwc_rnd", + "llvm.hexagon.M7.wcmpyrw" => "__builtin_HEXAGON_M7_wcmpyrw", + "llvm.hexagon.M7.wcmpyrw.rnd" => "__builtin_HEXAGON_M7_wcmpyrw_rnd", + "llvm.hexagon.M7.wcmpyrwc" => "__builtin_HEXAGON_M7_wcmpyrwc", + "llvm.hexagon.M7.wcmpyrwc.rnd" => "__builtin_HEXAGON_M7_wcmpyrwc_rnd", "llvm.hexagon.S2.addasl.rrri" => "__builtin_HEXAGON_S2_addasl_rrri", "llvm.hexagon.S2.asl.i.p" => "__builtin_HEXAGON_S2_asl_i_p", "llvm.hexagon.S2.asl.i.p.acc" => "__builtin_HEXAGON_S2_asl_i_p_acc", @@ -1023,6 +1093,7 @@ match name { "llvm.hexagon.S2.lsr.r.r.or" => "__builtin_HEXAGON_S2_lsr_r_r_or", "llvm.hexagon.S2.lsr.r.vh" => "__builtin_HEXAGON_S2_lsr_r_vh", "llvm.hexagon.S2.lsr.r.vw" => "__builtin_HEXAGON_S2_lsr_r_vw", + "llvm.hexagon.S2.mask" => "__builtin_HEXAGON_S2_mask", "llvm.hexagon.S2.packhl" => "__builtin_HEXAGON_S2_packhl", "llvm.hexagon.S2.parityp" => "__builtin_HEXAGON_S2_parityp", "llvm.hexagon.S2.setbit.i" => "__builtin_HEXAGON_S2_setbit_i", @@ -1031,6 +1102,12 @@ match name { "llvm.hexagon.S2.shuffeh" => "__builtin_HEXAGON_S2_shuffeh", "llvm.hexagon.S2.shuffob" => "__builtin_HEXAGON_S2_shuffob", "llvm.hexagon.S2.shuffoh" => "__builtin_HEXAGON_S2_shuffoh", + "llvm.hexagon.S2.storerb.pbr" => "__builtin_brev_stb", + "llvm.hexagon.S2.storerd.pbr" => "__builtin_brev_std", + "llvm.hexagon.S2.storerf.pbr" => "__builtin_brev_sthhi", + "llvm.hexagon.S2.storerh.pbr" => "__builtin_brev_sth", + "llvm.hexagon.S2.storeri.pbr" => "__builtin_brev_stw", + "llvm.hexagon.S2.storew.locked" => "__builtin_HEXAGON_S2_storew_locked", "llvm.hexagon.S2.svsathb" => "__builtin_HEXAGON_S2_svsathb", "llvm.hexagon.S2.svsathub" => "__builtin_HEXAGON_S2_svsathub", "llvm.hexagon.S2.tableidxb.goodsyntax" => "__builtin_HEXAGON_S2_tableidxb_goodsyntax", @@ -1089,6 +1166,7 @@ match name { "llvm.hexagon.S4.ori.asl.ri" => "__builtin_HEXAGON_S4_ori_asl_ri", "llvm.hexagon.S4.ori.lsr.ri" => "__builtin_HEXAGON_S4_ori_lsr_ri", "llvm.hexagon.S4.parity" => "__builtin_HEXAGON_S4_parity", + "llvm.hexagon.S4.stored.locked" => "__builtin_HEXAGON_S4_stored_locked", "llvm.hexagon.S4.subaddi" => "__builtin_HEXAGON_S4_subaddi", "llvm.hexagon.S4.subi.asl.ri" => "__builtin_HEXAGON_S4_subi_asl_ri", "llvm.hexagon.S4.subi.lsr.ri" => "__builtin_HEXAGON_S4_subi_lsr_ri", @@ -1126,8 +1204,56 @@ match name { "llvm.hexagon.V6.hi.128B" => "__builtin_HEXAGON_V6_hi_128B", "llvm.hexagon.V6.lo" => "__builtin_HEXAGON_V6_lo", "llvm.hexagon.V6.lo.128B" => "__builtin_HEXAGON_V6_lo_128B", + "llvm.hexagon.V6.lvsplatb" => "__builtin_HEXAGON_V6_lvsplatb", + "llvm.hexagon.V6.lvsplatb.128B" => "__builtin_HEXAGON_V6_lvsplatb_128B", + "llvm.hexagon.V6.lvsplath" => "__builtin_HEXAGON_V6_lvsplath", + "llvm.hexagon.V6.lvsplath.128B" => "__builtin_HEXAGON_V6_lvsplath_128B", "llvm.hexagon.V6.lvsplatw" => "__builtin_HEXAGON_V6_lvsplatw", "llvm.hexagon.V6.lvsplatw.128B" => "__builtin_HEXAGON_V6_lvsplatw_128B", + "llvm.hexagon.V6.pred.and" => "__builtin_HEXAGON_V6_pred_and", + "llvm.hexagon.V6.pred.and.128B" => "__builtin_HEXAGON_V6_pred_and_128B", + "llvm.hexagon.V6.pred.and.n" => "__builtin_HEXAGON_V6_pred_and_n", + "llvm.hexagon.V6.pred.and.n.128B" => "__builtin_HEXAGON_V6_pred_and_n_128B", + "llvm.hexagon.V6.pred.not" => "__builtin_HEXAGON_V6_pred_not", + "llvm.hexagon.V6.pred.not.128B" => "__builtin_HEXAGON_V6_pred_not_128B", + "llvm.hexagon.V6.pred.or" => "__builtin_HEXAGON_V6_pred_or", + "llvm.hexagon.V6.pred.or.128B" => "__builtin_HEXAGON_V6_pred_or_128B", + "llvm.hexagon.V6.pred.or.n" => "__builtin_HEXAGON_V6_pred_or_n", + "llvm.hexagon.V6.pred.or.n.128B" => "__builtin_HEXAGON_V6_pred_or_n_128B", + "llvm.hexagon.V6.pred.scalar2" => "__builtin_HEXAGON_V6_pred_scalar2", + "llvm.hexagon.V6.pred.scalar2.128B" => "__builtin_HEXAGON_V6_pred_scalar2_128B", + "llvm.hexagon.V6.pred.scalar2v2" => "__builtin_HEXAGON_V6_pred_scalar2v2", + "llvm.hexagon.V6.pred.scalar2v2.128B" => "__builtin_HEXAGON_V6_pred_scalar2v2_128B", + "llvm.hexagon.V6.pred.xor" => "__builtin_HEXAGON_V6_pred_xor", + "llvm.hexagon.V6.pred.xor.128B" => "__builtin_HEXAGON_V6_pred_xor_128B", + "llvm.hexagon.V6.shuffeqh" => "__builtin_HEXAGON_V6_shuffeqh", + "llvm.hexagon.V6.shuffeqh.128B" => "__builtin_HEXAGON_V6_shuffeqh_128B", + "llvm.hexagon.V6.shuffeqw" => "__builtin_HEXAGON_V6_shuffeqw", + "llvm.hexagon.V6.shuffeqw.128B" => "__builtin_HEXAGON_V6_shuffeqw_128B", + "llvm.hexagon.V6.v6mpyhubs10" => "__builtin_HEXAGON_V6_v6mpyhubs10", + "llvm.hexagon.V6.v6mpyhubs10.128B" => "__builtin_HEXAGON_V6_v6mpyhubs10_128B", + "llvm.hexagon.V6.v6mpyhubs10.vxx" => "__builtin_HEXAGON_V6_v6mpyhubs10_vxx", + "llvm.hexagon.V6.v6mpyhubs10.vxx.128B" => "__builtin_HEXAGON_V6_v6mpyhubs10_vxx_128B", + "llvm.hexagon.V6.v6mpyvubs10" => "__builtin_HEXAGON_V6_v6mpyvubs10", + "llvm.hexagon.V6.v6mpyvubs10.128B" => "__builtin_HEXAGON_V6_v6mpyvubs10_128B", + "llvm.hexagon.V6.v6mpyvubs10.vxx" => "__builtin_HEXAGON_V6_v6mpyvubs10_vxx", + "llvm.hexagon.V6.v6mpyvubs10.vxx.128B" => "__builtin_HEXAGON_V6_v6mpyvubs10_vxx_128B", + "llvm.hexagon.V6.vS32b.nqpred.ai" => "__builtin_HEXAGON_V6_vS32b_nqpred_ai", + "llvm.hexagon.V6.vS32b.nqpred.ai.128B" => "__builtin_HEXAGON_V6_vS32b_nqpred_ai_128B", + "llvm.hexagon.V6.vS32b.nt.nqpred.ai" => "__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai", + "llvm.hexagon.V6.vS32b.nt.nqpred.ai.128B" => "__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai_128B", + "llvm.hexagon.V6.vS32b.nt.qpred.ai" => "__builtin_HEXAGON_V6_vS32b_nt_qpred_ai", + "llvm.hexagon.V6.vS32b.nt.qpred.ai.128B" => "__builtin_HEXAGON_V6_vS32b_nt_qpred_ai_128B", + "llvm.hexagon.V6.vS32b.qpred.ai" => "__builtin_HEXAGON_V6_vS32b_qpred_ai", + "llvm.hexagon.V6.vS32b.qpred.ai.128B" => "__builtin_HEXAGON_V6_vS32b_qpred_ai_128B", + "llvm.hexagon.V6.vabs.hf" => "__builtin_HEXAGON_V6_vabs_hf", + "llvm.hexagon.V6.vabs.hf.128B" => "__builtin_HEXAGON_V6_vabs_hf_128B", + "llvm.hexagon.V6.vabs.sf" => "__builtin_HEXAGON_V6_vabs_sf", + "llvm.hexagon.V6.vabs.sf.128B" => "__builtin_HEXAGON_V6_vabs_sf_128B", + "llvm.hexagon.V6.vabsb" => "__builtin_HEXAGON_V6_vabsb", + "llvm.hexagon.V6.vabsb.128B" => "__builtin_HEXAGON_V6_vabsb_128B", + "llvm.hexagon.V6.vabsb.sat" => "__builtin_HEXAGON_V6_vabsb_sat", + "llvm.hexagon.V6.vabsb.sat.128B" => "__builtin_HEXAGON_V6_vabsb_sat_128B", "llvm.hexagon.V6.vabsdiffh" => "__builtin_HEXAGON_V6_vabsdiffh", "llvm.hexagon.V6.vabsdiffh.128B" => "__builtin_HEXAGON_V6_vabsdiffh_128B", "llvm.hexagon.V6.vabsdiffub" => "__builtin_HEXAGON_V6_vabsdiffub", @@ -1144,36 +1270,88 @@ match name { "llvm.hexagon.V6.vabsw.128B" => "__builtin_HEXAGON_V6_vabsw_128B", "llvm.hexagon.V6.vabsw.sat" => "__builtin_HEXAGON_V6_vabsw_sat", "llvm.hexagon.V6.vabsw.sat.128B" => "__builtin_HEXAGON_V6_vabsw_sat_128B", + "llvm.hexagon.V6.vadd.hf" => "__builtin_HEXAGON_V6_vadd_hf", + "llvm.hexagon.V6.vadd.hf.128B" => "__builtin_HEXAGON_V6_vadd_hf_128B", + "llvm.hexagon.V6.vadd.hf.hf" => "__builtin_HEXAGON_V6_vadd_hf_hf", + "llvm.hexagon.V6.vadd.hf.hf.128B" => "__builtin_HEXAGON_V6_vadd_hf_hf_128B", + "llvm.hexagon.V6.vadd.qf16" => "__builtin_HEXAGON_V6_vadd_qf16", + "llvm.hexagon.V6.vadd.qf16.128B" => "__builtin_HEXAGON_V6_vadd_qf16_128B", + "llvm.hexagon.V6.vadd.qf16.mix" => "__builtin_HEXAGON_V6_vadd_qf16_mix", + "llvm.hexagon.V6.vadd.qf16.mix.128B" => "__builtin_HEXAGON_V6_vadd_qf16_mix_128B", + "llvm.hexagon.V6.vadd.qf32" => "__builtin_HEXAGON_V6_vadd_qf32", + "llvm.hexagon.V6.vadd.qf32.128B" => "__builtin_HEXAGON_V6_vadd_qf32_128B", + "llvm.hexagon.V6.vadd.qf32.mix" => "__builtin_HEXAGON_V6_vadd_qf32_mix", + "llvm.hexagon.V6.vadd.qf32.mix.128B" => "__builtin_HEXAGON_V6_vadd_qf32_mix_128B", + "llvm.hexagon.V6.vadd.sf" => "__builtin_HEXAGON_V6_vadd_sf", + "llvm.hexagon.V6.vadd.sf.128B" => "__builtin_HEXAGON_V6_vadd_sf_128B", + "llvm.hexagon.V6.vadd.sf.hf" => "__builtin_HEXAGON_V6_vadd_sf_hf", + "llvm.hexagon.V6.vadd.sf.hf.128B" => "__builtin_HEXAGON_V6_vadd_sf_hf_128B", + "llvm.hexagon.V6.vadd.sf.sf" => "__builtin_HEXAGON_V6_vadd_sf_sf", + "llvm.hexagon.V6.vadd.sf.sf.128B" => "__builtin_HEXAGON_V6_vadd_sf_sf_128B", "llvm.hexagon.V6.vaddb" => "__builtin_HEXAGON_V6_vaddb", "llvm.hexagon.V6.vaddb.128B" => "__builtin_HEXAGON_V6_vaddb_128B", "llvm.hexagon.V6.vaddb.dv" => "__builtin_HEXAGON_V6_vaddb_dv", "llvm.hexagon.V6.vaddb.dv.128B" => "__builtin_HEXAGON_V6_vaddb_dv_128B", + "llvm.hexagon.V6.vaddbnq" => "__builtin_HEXAGON_V6_vaddbnq", + "llvm.hexagon.V6.vaddbnq.128B" => "__builtin_HEXAGON_V6_vaddbnq_128B", + "llvm.hexagon.V6.vaddbq" => "__builtin_HEXAGON_V6_vaddbq", + "llvm.hexagon.V6.vaddbq.128B" => "__builtin_HEXAGON_V6_vaddbq_128B", + "llvm.hexagon.V6.vaddbsat" => "__builtin_HEXAGON_V6_vaddbsat", + "llvm.hexagon.V6.vaddbsat.128B" => "__builtin_HEXAGON_V6_vaddbsat_128B", + "llvm.hexagon.V6.vaddbsat.dv" => "__builtin_HEXAGON_V6_vaddbsat_dv", + "llvm.hexagon.V6.vaddbsat.dv.128B" => "__builtin_HEXAGON_V6_vaddbsat_dv_128B", + "llvm.hexagon.V6.vaddcarrysat" => "__builtin_HEXAGON_V6_vaddcarrysat", + "llvm.hexagon.V6.vaddcarrysat.128B" => "__builtin_HEXAGON_V6_vaddcarrysat_128B", + "llvm.hexagon.V6.vaddclbh" => "__builtin_HEXAGON_V6_vaddclbh", + "llvm.hexagon.V6.vaddclbh.128B" => "__builtin_HEXAGON_V6_vaddclbh_128B", + "llvm.hexagon.V6.vaddclbw" => "__builtin_HEXAGON_V6_vaddclbw", + "llvm.hexagon.V6.vaddclbw.128B" => "__builtin_HEXAGON_V6_vaddclbw_128B", "llvm.hexagon.V6.vaddh" => "__builtin_HEXAGON_V6_vaddh", "llvm.hexagon.V6.vaddh.128B" => "__builtin_HEXAGON_V6_vaddh_128B", "llvm.hexagon.V6.vaddh.dv" => "__builtin_HEXAGON_V6_vaddh_dv", "llvm.hexagon.V6.vaddh.dv.128B" => "__builtin_HEXAGON_V6_vaddh_dv_128B", + "llvm.hexagon.V6.vaddhnq" => "__builtin_HEXAGON_V6_vaddhnq", + "llvm.hexagon.V6.vaddhnq.128B" => "__builtin_HEXAGON_V6_vaddhnq_128B", + "llvm.hexagon.V6.vaddhq" => "__builtin_HEXAGON_V6_vaddhq", + "llvm.hexagon.V6.vaddhq.128B" => "__builtin_HEXAGON_V6_vaddhq_128B", "llvm.hexagon.V6.vaddhsat" => "__builtin_HEXAGON_V6_vaddhsat", "llvm.hexagon.V6.vaddhsat.128B" => "__builtin_HEXAGON_V6_vaddhsat_128B", "llvm.hexagon.V6.vaddhsat.dv" => "__builtin_HEXAGON_V6_vaddhsat_dv", "llvm.hexagon.V6.vaddhsat.dv.128B" => "__builtin_HEXAGON_V6_vaddhsat_dv_128B", "llvm.hexagon.V6.vaddhw" => "__builtin_HEXAGON_V6_vaddhw", "llvm.hexagon.V6.vaddhw.128B" => "__builtin_HEXAGON_V6_vaddhw_128B", + "llvm.hexagon.V6.vaddhw.acc" => "__builtin_HEXAGON_V6_vaddhw_acc", + "llvm.hexagon.V6.vaddhw.acc.128B" => "__builtin_HEXAGON_V6_vaddhw_acc_128B", "llvm.hexagon.V6.vaddubh" => "__builtin_HEXAGON_V6_vaddubh", "llvm.hexagon.V6.vaddubh.128B" => "__builtin_HEXAGON_V6_vaddubh_128B", + "llvm.hexagon.V6.vaddubh.acc" => "__builtin_HEXAGON_V6_vaddubh_acc", + "llvm.hexagon.V6.vaddubh.acc.128B" => "__builtin_HEXAGON_V6_vaddubh_acc_128B", "llvm.hexagon.V6.vaddubsat" => "__builtin_HEXAGON_V6_vaddubsat", "llvm.hexagon.V6.vaddubsat.128B" => "__builtin_HEXAGON_V6_vaddubsat_128B", "llvm.hexagon.V6.vaddubsat.dv" => "__builtin_HEXAGON_V6_vaddubsat_dv", "llvm.hexagon.V6.vaddubsat.dv.128B" => "__builtin_HEXAGON_V6_vaddubsat_dv_128B", + "llvm.hexagon.V6.vaddububb.sat" => "__builtin_HEXAGON_V6_vaddububb_sat", + "llvm.hexagon.V6.vaddububb.sat.128B" => "__builtin_HEXAGON_V6_vaddububb_sat_128B", "llvm.hexagon.V6.vadduhsat" => "__builtin_HEXAGON_V6_vadduhsat", "llvm.hexagon.V6.vadduhsat.128B" => "__builtin_HEXAGON_V6_vadduhsat_128B", "llvm.hexagon.V6.vadduhsat.dv" => "__builtin_HEXAGON_V6_vadduhsat_dv", "llvm.hexagon.V6.vadduhsat.dv.128B" => "__builtin_HEXAGON_V6_vadduhsat_dv_128B", "llvm.hexagon.V6.vadduhw" => "__builtin_HEXAGON_V6_vadduhw", "llvm.hexagon.V6.vadduhw.128B" => "__builtin_HEXAGON_V6_vadduhw_128B", + "llvm.hexagon.V6.vadduhw.acc" => "__builtin_HEXAGON_V6_vadduhw_acc", + "llvm.hexagon.V6.vadduhw.acc.128B" => "__builtin_HEXAGON_V6_vadduhw_acc_128B", + "llvm.hexagon.V6.vadduwsat" => "__builtin_HEXAGON_V6_vadduwsat", + "llvm.hexagon.V6.vadduwsat.128B" => "__builtin_HEXAGON_V6_vadduwsat_128B", + "llvm.hexagon.V6.vadduwsat.dv" => "__builtin_HEXAGON_V6_vadduwsat_dv", + "llvm.hexagon.V6.vadduwsat.dv.128B" => "__builtin_HEXAGON_V6_vadduwsat_dv_128B", "llvm.hexagon.V6.vaddw" => "__builtin_HEXAGON_V6_vaddw", "llvm.hexagon.V6.vaddw.128B" => "__builtin_HEXAGON_V6_vaddw_128B", "llvm.hexagon.V6.vaddw.dv" => "__builtin_HEXAGON_V6_vaddw_dv", "llvm.hexagon.V6.vaddw.dv.128B" => "__builtin_HEXAGON_V6_vaddw_dv_128B", + "llvm.hexagon.V6.vaddwnq" => "__builtin_HEXAGON_V6_vaddwnq", + "llvm.hexagon.V6.vaddwnq.128B" => "__builtin_HEXAGON_V6_vaddwnq_128B", + "llvm.hexagon.V6.vaddwq" => "__builtin_HEXAGON_V6_vaddwq", + "llvm.hexagon.V6.vaddwq.128B" => "__builtin_HEXAGON_V6_vaddwq_128B", "llvm.hexagon.V6.vaddwsat" => "__builtin_HEXAGON_V6_vaddwsat", "llvm.hexagon.V6.vaddwsat.128B" => "__builtin_HEXAGON_V6_vaddwsat_128B", "llvm.hexagon.V6.vaddwsat.dv" => "__builtin_HEXAGON_V6_vaddwsat_dv", @@ -1184,8 +1362,26 @@ match name { "llvm.hexagon.V6.valignbi.128B" => "__builtin_HEXAGON_V6_valignbi_128B", "llvm.hexagon.V6.vand" => "__builtin_HEXAGON_V6_vand", "llvm.hexagon.V6.vand.128B" => "__builtin_HEXAGON_V6_vand_128B", + "llvm.hexagon.V6.vandnqrt" => "__builtin_HEXAGON_V6_vandnqrt", + "llvm.hexagon.V6.vandnqrt.128B" => "__builtin_HEXAGON_V6_vandnqrt_128B", + "llvm.hexagon.V6.vandnqrt.acc" => "__builtin_HEXAGON_V6_vandnqrt_acc", + "llvm.hexagon.V6.vandnqrt.acc.128B" => "__builtin_HEXAGON_V6_vandnqrt_acc_128B", + "llvm.hexagon.V6.vandqrt" => "__builtin_HEXAGON_V6_vandqrt", + "llvm.hexagon.V6.vandqrt.128B" => "__builtin_HEXAGON_V6_vandqrt_128B", + "llvm.hexagon.V6.vandqrt.acc" => "__builtin_HEXAGON_V6_vandqrt_acc", + "llvm.hexagon.V6.vandqrt.acc.128B" => "__builtin_HEXAGON_V6_vandqrt_acc_128B", + "llvm.hexagon.V6.vandvnqv" => "__builtin_HEXAGON_V6_vandvnqv", + "llvm.hexagon.V6.vandvnqv.128B" => "__builtin_HEXAGON_V6_vandvnqv_128B", + "llvm.hexagon.V6.vandvqv" => "__builtin_HEXAGON_V6_vandvqv", + "llvm.hexagon.V6.vandvqv.128B" => "__builtin_HEXAGON_V6_vandvqv_128B", + "llvm.hexagon.V6.vandvrt" => "__builtin_HEXAGON_V6_vandvrt", + "llvm.hexagon.V6.vandvrt.128B" => "__builtin_HEXAGON_V6_vandvrt_128B", + "llvm.hexagon.V6.vandvrt.acc" => "__builtin_HEXAGON_V6_vandvrt_acc", + "llvm.hexagon.V6.vandvrt.acc.128B" => "__builtin_HEXAGON_V6_vandvrt_acc_128B", "llvm.hexagon.V6.vaslh" => "__builtin_HEXAGON_V6_vaslh", "llvm.hexagon.V6.vaslh.128B" => "__builtin_HEXAGON_V6_vaslh_128B", + "llvm.hexagon.V6.vaslh.acc" => "__builtin_HEXAGON_V6_vaslh_acc", + "llvm.hexagon.V6.vaslh.acc.128B" => "__builtin_HEXAGON_V6_vaslh_acc_128B", "llvm.hexagon.V6.vaslhv" => "__builtin_HEXAGON_V6_vaslhv", "llvm.hexagon.V6.vaslhv.128B" => "__builtin_HEXAGON_V6_vaslhv_128B", "llvm.hexagon.V6.vaslw" => "__builtin_HEXAGON_V6_vaslw", @@ -1194,16 +1390,38 @@ match name { "llvm.hexagon.V6.vaslw.acc.128B" => "__builtin_HEXAGON_V6_vaslw_acc_128B", "llvm.hexagon.V6.vaslwv" => "__builtin_HEXAGON_V6_vaslwv", "llvm.hexagon.V6.vaslwv.128B" => "__builtin_HEXAGON_V6_vaslwv_128B", + "llvm.hexagon.V6.vasr.into" => "__builtin_HEXAGON_V6_vasr_into", + "llvm.hexagon.V6.vasr.into.128B" => "__builtin_HEXAGON_V6_vasr_into_128B", "llvm.hexagon.V6.vasrh" => "__builtin_HEXAGON_V6_vasrh", "llvm.hexagon.V6.vasrh.128B" => "__builtin_HEXAGON_V6_vasrh_128B", + "llvm.hexagon.V6.vasrh.acc" => "__builtin_HEXAGON_V6_vasrh_acc", + "llvm.hexagon.V6.vasrh.acc.128B" => "__builtin_HEXAGON_V6_vasrh_acc_128B", "llvm.hexagon.V6.vasrhbrndsat" => "__builtin_HEXAGON_V6_vasrhbrndsat", "llvm.hexagon.V6.vasrhbrndsat.128B" => "__builtin_HEXAGON_V6_vasrhbrndsat_128B", + "llvm.hexagon.V6.vasrhbsat" => "__builtin_HEXAGON_V6_vasrhbsat", + "llvm.hexagon.V6.vasrhbsat.128B" => "__builtin_HEXAGON_V6_vasrhbsat_128B", "llvm.hexagon.V6.vasrhubrndsat" => "__builtin_HEXAGON_V6_vasrhubrndsat", "llvm.hexagon.V6.vasrhubrndsat.128B" => "__builtin_HEXAGON_V6_vasrhubrndsat_128B", "llvm.hexagon.V6.vasrhubsat" => "__builtin_HEXAGON_V6_vasrhubsat", "llvm.hexagon.V6.vasrhubsat.128B" => "__builtin_HEXAGON_V6_vasrhubsat_128B", "llvm.hexagon.V6.vasrhv" => "__builtin_HEXAGON_V6_vasrhv", "llvm.hexagon.V6.vasrhv.128B" => "__builtin_HEXAGON_V6_vasrhv_128B", + "llvm.hexagon.V6.vasruhubrndsat" => "__builtin_HEXAGON_V6_vasruhubrndsat", + "llvm.hexagon.V6.vasruhubrndsat.128B" => "__builtin_HEXAGON_V6_vasruhubrndsat_128B", + "llvm.hexagon.V6.vasruhubsat" => "__builtin_HEXAGON_V6_vasruhubsat", + "llvm.hexagon.V6.vasruhubsat.128B" => "__builtin_HEXAGON_V6_vasruhubsat_128B", + "llvm.hexagon.V6.vasruwuhrndsat" => "__builtin_HEXAGON_V6_vasruwuhrndsat", + "llvm.hexagon.V6.vasruwuhrndsat.128B" => "__builtin_HEXAGON_V6_vasruwuhrndsat_128B", + "llvm.hexagon.V6.vasruwuhsat" => "__builtin_HEXAGON_V6_vasruwuhsat", + "llvm.hexagon.V6.vasruwuhsat.128B" => "__builtin_HEXAGON_V6_vasruwuhsat_128B", + "llvm.hexagon.V6.vasrvuhubrndsat" => "__builtin_HEXAGON_V6_vasrvuhubrndsat", + "llvm.hexagon.V6.vasrvuhubrndsat.128B" => "__builtin_HEXAGON_V6_vasrvuhubrndsat_128B", + "llvm.hexagon.V6.vasrvuhubsat" => "__builtin_HEXAGON_V6_vasrvuhubsat", + "llvm.hexagon.V6.vasrvuhubsat.128B" => "__builtin_HEXAGON_V6_vasrvuhubsat_128B", + "llvm.hexagon.V6.vasrvwuhrndsat" => "__builtin_HEXAGON_V6_vasrvwuhrndsat", + "llvm.hexagon.V6.vasrvwuhrndsat.128B" => "__builtin_HEXAGON_V6_vasrvwuhrndsat_128B", + "llvm.hexagon.V6.vasrvwuhsat" => "__builtin_HEXAGON_V6_vasrvwuhsat", + "llvm.hexagon.V6.vasrvwuhsat.128B" => "__builtin_HEXAGON_V6_vasrvwuhsat_128B", "llvm.hexagon.V6.vasrw" => "__builtin_HEXAGON_V6_vasrw", "llvm.hexagon.V6.vasrw.128B" => "__builtin_HEXAGON_V6_vasrw_128B", "llvm.hexagon.V6.vasrw.acc" => "__builtin_HEXAGON_V6_vasrw_acc", @@ -1214,14 +1432,22 @@ match name { "llvm.hexagon.V6.vasrwhrndsat.128B" => "__builtin_HEXAGON_V6_vasrwhrndsat_128B", "llvm.hexagon.V6.vasrwhsat" => "__builtin_HEXAGON_V6_vasrwhsat", "llvm.hexagon.V6.vasrwhsat.128B" => "__builtin_HEXAGON_V6_vasrwhsat_128B", + "llvm.hexagon.V6.vasrwuhrndsat" => "__builtin_HEXAGON_V6_vasrwuhrndsat", + "llvm.hexagon.V6.vasrwuhrndsat.128B" => "__builtin_HEXAGON_V6_vasrwuhrndsat_128B", "llvm.hexagon.V6.vasrwuhsat" => "__builtin_HEXAGON_V6_vasrwuhsat", "llvm.hexagon.V6.vasrwuhsat.128B" => "__builtin_HEXAGON_V6_vasrwuhsat_128B", "llvm.hexagon.V6.vasrwv" => "__builtin_HEXAGON_V6_vasrwv", "llvm.hexagon.V6.vasrwv.128B" => "__builtin_HEXAGON_V6_vasrwv_128B", "llvm.hexagon.V6.vassign" => "__builtin_HEXAGON_V6_vassign", "llvm.hexagon.V6.vassign.128B" => "__builtin_HEXAGON_V6_vassign_128B", + "llvm.hexagon.V6.vassign.fp" => "__builtin_HEXAGON_V6_vassign_fp", + "llvm.hexagon.V6.vassign.fp.128B" => "__builtin_HEXAGON_V6_vassign_fp_128B", "llvm.hexagon.V6.vassignp" => "__builtin_HEXAGON_V6_vassignp", "llvm.hexagon.V6.vassignp.128B" => "__builtin_HEXAGON_V6_vassignp_128B", + "llvm.hexagon.V6.vavgb" => "__builtin_HEXAGON_V6_vavgb", + "llvm.hexagon.V6.vavgb.128B" => "__builtin_HEXAGON_V6_vavgb_128B", + "llvm.hexagon.V6.vavgbrnd" => "__builtin_HEXAGON_V6_vavgbrnd", + "llvm.hexagon.V6.vavgbrnd.128B" => "__builtin_HEXAGON_V6_vavgbrnd_128B", "llvm.hexagon.V6.vavgh" => "__builtin_HEXAGON_V6_vavgh", "llvm.hexagon.V6.vavgh.128B" => "__builtin_HEXAGON_V6_vavgh_128B", "llvm.hexagon.V6.vavghrnd" => "__builtin_HEXAGON_V6_vavghrnd", @@ -1234,6 +1460,10 @@ match name { "llvm.hexagon.V6.vavguh.128B" => "__builtin_HEXAGON_V6_vavguh_128B", "llvm.hexagon.V6.vavguhrnd" => "__builtin_HEXAGON_V6_vavguhrnd", "llvm.hexagon.V6.vavguhrnd.128B" => "__builtin_HEXAGON_V6_vavguhrnd_128B", + "llvm.hexagon.V6.vavguw" => "__builtin_HEXAGON_V6_vavguw", + "llvm.hexagon.V6.vavguw.128B" => "__builtin_HEXAGON_V6_vavguw_128B", + "llvm.hexagon.V6.vavguwrnd" => "__builtin_HEXAGON_V6_vavguwrnd", + "llvm.hexagon.V6.vavguwrnd.128B" => "__builtin_HEXAGON_V6_vavguwrnd_128B", "llvm.hexagon.V6.vavgw" => "__builtin_HEXAGON_V6_vavgw", "llvm.hexagon.V6.vavgw.128B" => "__builtin_HEXAGON_V6_vavgw_128B", "llvm.hexagon.V6.vavgwrnd" => "__builtin_HEXAGON_V6_vavgwrnd", @@ -1244,8 +1474,36 @@ match name { "llvm.hexagon.V6.vcl0w.128B" => "__builtin_HEXAGON_V6_vcl0w_128B", "llvm.hexagon.V6.vcombine" => "__builtin_HEXAGON_V6_vcombine", "llvm.hexagon.V6.vcombine.128B" => "__builtin_HEXAGON_V6_vcombine_128B", + "llvm.hexagon.V6.vconv.hf.qf16" => "__builtin_HEXAGON_V6_vconv_hf_qf16", + "llvm.hexagon.V6.vconv.hf.qf16.128B" => "__builtin_HEXAGON_V6_vconv_hf_qf16_128B", + "llvm.hexagon.V6.vconv.hf.qf32" => "__builtin_HEXAGON_V6_vconv_hf_qf32", + "llvm.hexagon.V6.vconv.hf.qf32.128B" => "__builtin_HEXAGON_V6_vconv_hf_qf32_128B", + "llvm.hexagon.V6.vconv.sf.qf32" => "__builtin_HEXAGON_V6_vconv_sf_qf32", + "llvm.hexagon.V6.vconv.sf.qf32.128B" => "__builtin_HEXAGON_V6_vconv_sf_qf32_128B", + "llvm.hexagon.V6.vcvt.b.hf" => "__builtin_HEXAGON_V6_vcvt_b_hf", + "llvm.hexagon.V6.vcvt.b.hf.128B" => "__builtin_HEXAGON_V6_vcvt_b_hf_128B", + "llvm.hexagon.V6.vcvt.h.hf" => "__builtin_HEXAGON_V6_vcvt_h_hf", + "llvm.hexagon.V6.vcvt.h.hf.128B" => "__builtin_HEXAGON_V6_vcvt_h_hf_128B", + "llvm.hexagon.V6.vcvt.hf.b" => "__builtin_HEXAGON_V6_vcvt_hf_b", + "llvm.hexagon.V6.vcvt.hf.b.128B" => "__builtin_HEXAGON_V6_vcvt_hf_b_128B", + "llvm.hexagon.V6.vcvt.hf.h" => "__builtin_HEXAGON_V6_vcvt_hf_h", + "llvm.hexagon.V6.vcvt.hf.h.128B" => "__builtin_HEXAGON_V6_vcvt_hf_h_128B", + "llvm.hexagon.V6.vcvt.hf.sf" => "__builtin_HEXAGON_V6_vcvt_hf_sf", + "llvm.hexagon.V6.vcvt.hf.sf.128B" => "__builtin_HEXAGON_V6_vcvt_hf_sf_128B", + "llvm.hexagon.V6.vcvt.hf.ub" => "__builtin_HEXAGON_V6_vcvt_hf_ub", + "llvm.hexagon.V6.vcvt.hf.ub.128B" => "__builtin_HEXAGON_V6_vcvt_hf_ub_128B", + "llvm.hexagon.V6.vcvt.hf.uh" => "__builtin_HEXAGON_V6_vcvt_hf_uh", + "llvm.hexagon.V6.vcvt.hf.uh.128B" => "__builtin_HEXAGON_V6_vcvt_hf_uh_128B", + "llvm.hexagon.V6.vcvt.sf.hf" => "__builtin_HEXAGON_V6_vcvt_sf_hf", + "llvm.hexagon.V6.vcvt.sf.hf.128B" => "__builtin_HEXAGON_V6_vcvt_sf_hf_128B", + "llvm.hexagon.V6.vcvt.ub.hf" => "__builtin_HEXAGON_V6_vcvt_ub_hf", + "llvm.hexagon.V6.vcvt.ub.hf.128B" => "__builtin_HEXAGON_V6_vcvt_ub_hf_128B", + "llvm.hexagon.V6.vcvt.uh.hf" => "__builtin_HEXAGON_V6_vcvt_uh_hf", + "llvm.hexagon.V6.vcvt.uh.hf.128B" => "__builtin_HEXAGON_V6_vcvt_uh_hf_128B", "llvm.hexagon.V6.vd0" => "__builtin_HEXAGON_V6_vd0", "llvm.hexagon.V6.vd0.128B" => "__builtin_HEXAGON_V6_vd0_128B", + "llvm.hexagon.V6.vdd0" => "__builtin_HEXAGON_V6_vdd0", + "llvm.hexagon.V6.vdd0.128B" => "__builtin_HEXAGON_V6_vdd0_128B", "llvm.hexagon.V6.vdealb" => "__builtin_HEXAGON_V6_vdealb", "llvm.hexagon.V6.vdealb.128B" => "__builtin_HEXAGON_V6_vdealb_128B", "llvm.hexagon.V6.vdealb4w" => "__builtin_HEXAGON_V6_vdealb4w", @@ -1256,6 +1514,10 @@ match name { "llvm.hexagon.V6.vdealvdd.128B" => "__builtin_HEXAGON_V6_vdealvdd_128B", "llvm.hexagon.V6.vdelta" => "__builtin_HEXAGON_V6_vdelta", "llvm.hexagon.V6.vdelta.128B" => "__builtin_HEXAGON_V6_vdelta_128B", + "llvm.hexagon.V6.vdmpy.sf.hf" => "__builtin_HEXAGON_V6_vdmpy_sf_hf", + "llvm.hexagon.V6.vdmpy.sf.hf.128B" => "__builtin_HEXAGON_V6_vdmpy_sf_hf_128B", + "llvm.hexagon.V6.vdmpy.sf.hf.acc" => "__builtin_HEXAGON_V6_vdmpy_sf_hf_acc", + "llvm.hexagon.V6.vdmpy.sf.hf.acc.128B" => "__builtin_HEXAGON_V6_vdmpy_sf_hf_acc_128B", "llvm.hexagon.V6.vdmpybus" => "__builtin_HEXAGON_V6_vdmpybus", "llvm.hexagon.V6.vdmpybus.128B" => "__builtin_HEXAGON_V6_vdmpybus_128B", "llvm.hexagon.V6.vdmpybus.acc" => "__builtin_HEXAGON_V6_vdmpybus_acc", @@ -1296,12 +1558,126 @@ match name { "llvm.hexagon.V6.vdsaduh.128B" => "__builtin_HEXAGON_V6_vdsaduh_128B", "llvm.hexagon.V6.vdsaduh.acc" => "__builtin_HEXAGON_V6_vdsaduh_acc", "llvm.hexagon.V6.vdsaduh.acc.128B" => "__builtin_HEXAGON_V6_vdsaduh_acc_128B", + "llvm.hexagon.V6.veqb" => "__builtin_HEXAGON_V6_veqb", + "llvm.hexagon.V6.veqb.128B" => "__builtin_HEXAGON_V6_veqb_128B", + "llvm.hexagon.V6.veqb.and" => "__builtin_HEXAGON_V6_veqb_and", + "llvm.hexagon.V6.veqb.and.128B" => "__builtin_HEXAGON_V6_veqb_and_128B", + "llvm.hexagon.V6.veqb.or" => "__builtin_HEXAGON_V6_veqb_or", + "llvm.hexagon.V6.veqb.or.128B" => "__builtin_HEXAGON_V6_veqb_or_128B", + "llvm.hexagon.V6.veqb.xor" => "__builtin_HEXAGON_V6_veqb_xor", + "llvm.hexagon.V6.veqb.xor.128B" => "__builtin_HEXAGON_V6_veqb_xor_128B", + "llvm.hexagon.V6.veqh" => "__builtin_HEXAGON_V6_veqh", + "llvm.hexagon.V6.veqh.128B" => "__builtin_HEXAGON_V6_veqh_128B", + "llvm.hexagon.V6.veqh.and" => "__builtin_HEXAGON_V6_veqh_and", + "llvm.hexagon.V6.veqh.and.128B" => "__builtin_HEXAGON_V6_veqh_and_128B", + "llvm.hexagon.V6.veqh.or" => "__builtin_HEXAGON_V6_veqh_or", + "llvm.hexagon.V6.veqh.or.128B" => "__builtin_HEXAGON_V6_veqh_or_128B", + "llvm.hexagon.V6.veqh.xor" => "__builtin_HEXAGON_V6_veqh_xor", + "llvm.hexagon.V6.veqh.xor.128B" => "__builtin_HEXAGON_V6_veqh_xor_128B", + "llvm.hexagon.V6.veqw" => "__builtin_HEXAGON_V6_veqw", + "llvm.hexagon.V6.veqw.128B" => "__builtin_HEXAGON_V6_veqw_128B", + "llvm.hexagon.V6.veqw.and" => "__builtin_HEXAGON_V6_veqw_and", + "llvm.hexagon.V6.veqw.and.128B" => "__builtin_HEXAGON_V6_veqw_and_128B", + "llvm.hexagon.V6.veqw.or" => "__builtin_HEXAGON_V6_veqw_or", + "llvm.hexagon.V6.veqw.or.128B" => "__builtin_HEXAGON_V6_veqw_or_128B", + "llvm.hexagon.V6.veqw.xor" => "__builtin_HEXAGON_V6_veqw_xor", + "llvm.hexagon.V6.veqw.xor.128B" => "__builtin_HEXAGON_V6_veqw_xor_128B", + "llvm.hexagon.V6.vfmax.hf" => "__builtin_HEXAGON_V6_vfmax_hf", + "llvm.hexagon.V6.vfmax.hf.128B" => "__builtin_HEXAGON_V6_vfmax_hf_128B", + "llvm.hexagon.V6.vfmax.sf" => "__builtin_HEXAGON_V6_vfmax_sf", + "llvm.hexagon.V6.vfmax.sf.128B" => "__builtin_HEXAGON_V6_vfmax_sf_128B", + "llvm.hexagon.V6.vfmin.hf" => "__builtin_HEXAGON_V6_vfmin_hf", + "llvm.hexagon.V6.vfmin.hf.128B" => "__builtin_HEXAGON_V6_vfmin_hf_128B", + "llvm.hexagon.V6.vfmin.sf" => "__builtin_HEXAGON_V6_vfmin_sf", + "llvm.hexagon.V6.vfmin.sf.128B" => "__builtin_HEXAGON_V6_vfmin_sf_128B", + "llvm.hexagon.V6.vfneg.hf" => "__builtin_HEXAGON_V6_vfneg_hf", + "llvm.hexagon.V6.vfneg.hf.128B" => "__builtin_HEXAGON_V6_vfneg_hf_128B", + "llvm.hexagon.V6.vfneg.sf" => "__builtin_HEXAGON_V6_vfneg_sf", + "llvm.hexagon.V6.vfneg.sf.128B" => "__builtin_HEXAGON_V6_vfneg_sf_128B", + "llvm.hexagon.V6.vgathermh" => "__builtin_HEXAGON_V6_vgathermh", + "llvm.hexagon.V6.vgathermh.128B" => "__builtin_HEXAGON_V6_vgathermh_128B", + "llvm.hexagon.V6.vgathermhq" => "__builtin_HEXAGON_V6_vgathermhq", + "llvm.hexagon.V6.vgathermhq.128B" => "__builtin_HEXAGON_V6_vgathermhq_128B", + "llvm.hexagon.V6.vgathermhw" => "__builtin_HEXAGON_V6_vgathermhw", + "llvm.hexagon.V6.vgathermhw.128B" => "__builtin_HEXAGON_V6_vgathermhw_128B", + "llvm.hexagon.V6.vgathermhwq" => "__builtin_HEXAGON_V6_vgathermhwq", + "llvm.hexagon.V6.vgathermhwq.128B" => "__builtin_HEXAGON_V6_vgathermhwq_128B", + "llvm.hexagon.V6.vgathermw" => "__builtin_HEXAGON_V6_vgathermw", + "llvm.hexagon.V6.vgathermw.128B" => "__builtin_HEXAGON_V6_vgathermw_128B", + "llvm.hexagon.V6.vgathermwq" => "__builtin_HEXAGON_V6_vgathermwq", + "llvm.hexagon.V6.vgathermwq.128B" => "__builtin_HEXAGON_V6_vgathermwq_128B", + "llvm.hexagon.V6.vgtb" => "__builtin_HEXAGON_V6_vgtb", + "llvm.hexagon.V6.vgtb.128B" => "__builtin_HEXAGON_V6_vgtb_128B", + "llvm.hexagon.V6.vgtb.and" => "__builtin_HEXAGON_V6_vgtb_and", + "llvm.hexagon.V6.vgtb.and.128B" => "__builtin_HEXAGON_V6_vgtb_and_128B", + "llvm.hexagon.V6.vgtb.or" => "__builtin_HEXAGON_V6_vgtb_or", + "llvm.hexagon.V6.vgtb.or.128B" => "__builtin_HEXAGON_V6_vgtb_or_128B", + "llvm.hexagon.V6.vgtb.xor" => "__builtin_HEXAGON_V6_vgtb_xor", + "llvm.hexagon.V6.vgtb.xor.128B" => "__builtin_HEXAGON_V6_vgtb_xor_128B", + "llvm.hexagon.V6.vgth" => "__builtin_HEXAGON_V6_vgth", + "llvm.hexagon.V6.vgth.128B" => "__builtin_HEXAGON_V6_vgth_128B", + "llvm.hexagon.V6.vgth.and" => "__builtin_HEXAGON_V6_vgth_and", + "llvm.hexagon.V6.vgth.and.128B" => "__builtin_HEXAGON_V6_vgth_and_128B", + "llvm.hexagon.V6.vgth.or" => "__builtin_HEXAGON_V6_vgth_or", + "llvm.hexagon.V6.vgth.or.128B" => "__builtin_HEXAGON_V6_vgth_or_128B", + "llvm.hexagon.V6.vgth.xor" => "__builtin_HEXAGON_V6_vgth_xor", + "llvm.hexagon.V6.vgth.xor.128B" => "__builtin_HEXAGON_V6_vgth_xor_128B", + "llvm.hexagon.V6.vgthf" => "__builtin_HEXAGON_V6_vgthf", + "llvm.hexagon.V6.vgthf.128B" => "__builtin_HEXAGON_V6_vgthf_128B", + "llvm.hexagon.V6.vgthf.and" => "__builtin_HEXAGON_V6_vgthf_and", + "llvm.hexagon.V6.vgthf.and.128B" => "__builtin_HEXAGON_V6_vgthf_and_128B", + "llvm.hexagon.V6.vgthf.or" => "__builtin_HEXAGON_V6_vgthf_or", + "llvm.hexagon.V6.vgthf.or.128B" => "__builtin_HEXAGON_V6_vgthf_or_128B", + "llvm.hexagon.V6.vgthf.xor" => "__builtin_HEXAGON_V6_vgthf_xor", + "llvm.hexagon.V6.vgthf.xor.128B" => "__builtin_HEXAGON_V6_vgthf_xor_128B", + "llvm.hexagon.V6.vgtsf" => "__builtin_HEXAGON_V6_vgtsf", + "llvm.hexagon.V6.vgtsf.128B" => "__builtin_HEXAGON_V6_vgtsf_128B", + "llvm.hexagon.V6.vgtsf.and" => "__builtin_HEXAGON_V6_vgtsf_and", + "llvm.hexagon.V6.vgtsf.and.128B" => "__builtin_HEXAGON_V6_vgtsf_and_128B", + "llvm.hexagon.V6.vgtsf.or" => "__builtin_HEXAGON_V6_vgtsf_or", + "llvm.hexagon.V6.vgtsf.or.128B" => "__builtin_HEXAGON_V6_vgtsf_or_128B", + "llvm.hexagon.V6.vgtsf.xor" => "__builtin_HEXAGON_V6_vgtsf_xor", + "llvm.hexagon.V6.vgtsf.xor.128B" => "__builtin_HEXAGON_V6_vgtsf_xor_128B", + "llvm.hexagon.V6.vgtub" => "__builtin_HEXAGON_V6_vgtub", + "llvm.hexagon.V6.vgtub.128B" => "__builtin_HEXAGON_V6_vgtub_128B", + "llvm.hexagon.V6.vgtub.and" => "__builtin_HEXAGON_V6_vgtub_and", + "llvm.hexagon.V6.vgtub.and.128B" => "__builtin_HEXAGON_V6_vgtub_and_128B", + "llvm.hexagon.V6.vgtub.or" => "__builtin_HEXAGON_V6_vgtub_or", + "llvm.hexagon.V6.vgtub.or.128B" => "__builtin_HEXAGON_V6_vgtub_or_128B", + "llvm.hexagon.V6.vgtub.xor" => "__builtin_HEXAGON_V6_vgtub_xor", + "llvm.hexagon.V6.vgtub.xor.128B" => "__builtin_HEXAGON_V6_vgtub_xor_128B", + "llvm.hexagon.V6.vgtuh" => "__builtin_HEXAGON_V6_vgtuh", + "llvm.hexagon.V6.vgtuh.128B" => "__builtin_HEXAGON_V6_vgtuh_128B", + "llvm.hexagon.V6.vgtuh.and" => "__builtin_HEXAGON_V6_vgtuh_and", + "llvm.hexagon.V6.vgtuh.and.128B" => "__builtin_HEXAGON_V6_vgtuh_and_128B", + "llvm.hexagon.V6.vgtuh.or" => "__builtin_HEXAGON_V6_vgtuh_or", + "llvm.hexagon.V6.vgtuh.or.128B" => "__builtin_HEXAGON_V6_vgtuh_or_128B", + "llvm.hexagon.V6.vgtuh.xor" => "__builtin_HEXAGON_V6_vgtuh_xor", + "llvm.hexagon.V6.vgtuh.xor.128B" => "__builtin_HEXAGON_V6_vgtuh_xor_128B", + "llvm.hexagon.V6.vgtuw" => "__builtin_HEXAGON_V6_vgtuw", + "llvm.hexagon.V6.vgtuw.128B" => "__builtin_HEXAGON_V6_vgtuw_128B", + "llvm.hexagon.V6.vgtuw.and" => "__builtin_HEXAGON_V6_vgtuw_and", + "llvm.hexagon.V6.vgtuw.and.128B" => "__builtin_HEXAGON_V6_vgtuw_and_128B", + "llvm.hexagon.V6.vgtuw.or" => "__builtin_HEXAGON_V6_vgtuw_or", + "llvm.hexagon.V6.vgtuw.or.128B" => "__builtin_HEXAGON_V6_vgtuw_or_128B", + "llvm.hexagon.V6.vgtuw.xor" => "__builtin_HEXAGON_V6_vgtuw_xor", + "llvm.hexagon.V6.vgtuw.xor.128B" => "__builtin_HEXAGON_V6_vgtuw_xor_128B", + "llvm.hexagon.V6.vgtw" => "__builtin_HEXAGON_V6_vgtw", + "llvm.hexagon.V6.vgtw.128B" => "__builtin_HEXAGON_V6_vgtw_128B", + "llvm.hexagon.V6.vgtw.and" => "__builtin_HEXAGON_V6_vgtw_and", + "llvm.hexagon.V6.vgtw.and.128B" => "__builtin_HEXAGON_V6_vgtw_and_128B", + "llvm.hexagon.V6.vgtw.or" => "__builtin_HEXAGON_V6_vgtw_or", + "llvm.hexagon.V6.vgtw.or.128B" => "__builtin_HEXAGON_V6_vgtw_or_128B", + "llvm.hexagon.V6.vgtw.xor" => "__builtin_HEXAGON_V6_vgtw_xor", + "llvm.hexagon.V6.vgtw.xor.128B" => "__builtin_HEXAGON_V6_vgtw_xor_128B", "llvm.hexagon.V6.vinsertwr" => "__builtin_HEXAGON_V6_vinsertwr", "llvm.hexagon.V6.vinsertwr.128B" => "__builtin_HEXAGON_V6_vinsertwr_128B", "llvm.hexagon.V6.vlalignb" => "__builtin_HEXAGON_V6_vlalignb", "llvm.hexagon.V6.vlalignb.128B" => "__builtin_HEXAGON_V6_vlalignb_128B", "llvm.hexagon.V6.vlalignbi" => "__builtin_HEXAGON_V6_vlalignbi", "llvm.hexagon.V6.vlalignbi.128B" => "__builtin_HEXAGON_V6_vlalignbi_128B", + "llvm.hexagon.V6.vlsrb" => "__builtin_HEXAGON_V6_vlsrb", + "llvm.hexagon.V6.vlsrb.128B" => "__builtin_HEXAGON_V6_vlsrb_128B", "llvm.hexagon.V6.vlsrh" => "__builtin_HEXAGON_V6_vlsrh", "llvm.hexagon.V6.vlsrh.128B" => "__builtin_HEXAGON_V6_vlsrh_128B", "llvm.hexagon.V6.vlsrhv" => "__builtin_HEXAGON_V6_vlsrhv", @@ -1310,6 +1686,8 @@ match name { "llvm.hexagon.V6.vlsrw.128B" => "__builtin_HEXAGON_V6_vlsrw_128B", "llvm.hexagon.V6.vlsrwv" => "__builtin_HEXAGON_V6_vlsrwv", "llvm.hexagon.V6.vlsrwv.128B" => "__builtin_HEXAGON_V6_vlsrwv_128B", + "llvm.hexagon.V6.vlut4" => "__builtin_HEXAGON_V6_vlut4", + "llvm.hexagon.V6.vlut4.128B" => "__builtin_HEXAGON_V6_vlut4_128B", "llvm.hexagon.V6.vlutb" => "__builtin_HEXAGON_V6_vlutb", "llvm.hexagon.V6.vlutb.128B" => "__builtin_HEXAGON_V6_vlutb_128B", "llvm.hexagon.V6.vlutb.acc" => "__builtin_HEXAGON_V6_vlutb_acc", @@ -1320,12 +1698,30 @@ match name { "llvm.hexagon.V6.vlutb.dv.acc.128B" => "__builtin_HEXAGON_V6_vlutb_dv_acc_128B", "llvm.hexagon.V6.vlutvvb" => "__builtin_HEXAGON_V6_vlutvvb", "llvm.hexagon.V6.vlutvvb.128B" => "__builtin_HEXAGON_V6_vlutvvb_128B", + "llvm.hexagon.V6.vlutvvb.nm" => "__builtin_HEXAGON_V6_vlutvvb_nm", + "llvm.hexagon.V6.vlutvvb.nm.128B" => "__builtin_HEXAGON_V6_vlutvvb_nm_128B", "llvm.hexagon.V6.vlutvvb.oracc" => "__builtin_HEXAGON_V6_vlutvvb_oracc", "llvm.hexagon.V6.vlutvvb.oracc.128B" => "__builtin_HEXAGON_V6_vlutvvb_oracc_128B", + "llvm.hexagon.V6.vlutvvb.oracci" => "__builtin_HEXAGON_V6_vlutvvb_oracci", + "llvm.hexagon.V6.vlutvvb.oracci.128B" => "__builtin_HEXAGON_V6_vlutvvb_oracci_128B", + "llvm.hexagon.V6.vlutvvbi" => "__builtin_HEXAGON_V6_vlutvvbi", + "llvm.hexagon.V6.vlutvvbi.128B" => "__builtin_HEXAGON_V6_vlutvvbi_128B", "llvm.hexagon.V6.vlutvwh" => "__builtin_HEXAGON_V6_vlutvwh", "llvm.hexagon.V6.vlutvwh.128B" => "__builtin_HEXAGON_V6_vlutvwh_128B", + "llvm.hexagon.V6.vlutvwh.nm" => "__builtin_HEXAGON_V6_vlutvwh_nm", + "llvm.hexagon.V6.vlutvwh.nm.128B" => "__builtin_HEXAGON_V6_vlutvwh_nm_128B", "llvm.hexagon.V6.vlutvwh.oracc" => "__builtin_HEXAGON_V6_vlutvwh_oracc", "llvm.hexagon.V6.vlutvwh.oracc.128B" => "__builtin_HEXAGON_V6_vlutvwh_oracc_128B", + "llvm.hexagon.V6.vlutvwh.oracci" => "__builtin_HEXAGON_V6_vlutvwh_oracci", + "llvm.hexagon.V6.vlutvwh.oracci.128B" => "__builtin_HEXAGON_V6_vlutvwh_oracci_128B", + "llvm.hexagon.V6.vlutvwhi" => "__builtin_HEXAGON_V6_vlutvwhi", + "llvm.hexagon.V6.vlutvwhi.128B" => "__builtin_HEXAGON_V6_vlutvwhi_128B", + "llvm.hexagon.V6.vmax.hf" => "__builtin_HEXAGON_V6_vmax_hf", + "llvm.hexagon.V6.vmax.hf.128B" => "__builtin_HEXAGON_V6_vmax_hf_128B", + "llvm.hexagon.V6.vmax.sf" => "__builtin_HEXAGON_V6_vmax_sf", + "llvm.hexagon.V6.vmax.sf.128B" => "__builtin_HEXAGON_V6_vmax_sf_128B", + "llvm.hexagon.V6.vmaxb" => "__builtin_HEXAGON_V6_vmaxb", + "llvm.hexagon.V6.vmaxb.128B" => "__builtin_HEXAGON_V6_vmaxb_128B", "llvm.hexagon.V6.vmaxh" => "__builtin_HEXAGON_V6_vmaxh", "llvm.hexagon.V6.vmaxh.128B" => "__builtin_HEXAGON_V6_vmaxh_128B", "llvm.hexagon.V6.vmaxub" => "__builtin_HEXAGON_V6_vmaxub", @@ -1334,6 +1730,12 @@ match name { "llvm.hexagon.V6.vmaxuh.128B" => "__builtin_HEXAGON_V6_vmaxuh_128B", "llvm.hexagon.V6.vmaxw" => "__builtin_HEXAGON_V6_vmaxw", "llvm.hexagon.V6.vmaxw.128B" => "__builtin_HEXAGON_V6_vmaxw_128B", + "llvm.hexagon.V6.vmin.hf" => "__builtin_HEXAGON_V6_vmin_hf", + "llvm.hexagon.V6.vmin.hf.128B" => "__builtin_HEXAGON_V6_vmin_hf_128B", + "llvm.hexagon.V6.vmin.sf" => "__builtin_HEXAGON_V6_vmin_sf", + "llvm.hexagon.V6.vmin.sf.128B" => "__builtin_HEXAGON_V6_vmin_sf_128B", + "llvm.hexagon.V6.vminb" => "__builtin_HEXAGON_V6_vminb", + "llvm.hexagon.V6.vminb.128B" => "__builtin_HEXAGON_V6_vminb_128B", "llvm.hexagon.V6.vminh" => "__builtin_HEXAGON_V6_vminh", "llvm.hexagon.V6.vminh.128B" => "__builtin_HEXAGON_V6_vminh_128B", "llvm.hexagon.V6.vminub" => "__builtin_HEXAGON_V6_vminub", @@ -1348,12 +1750,52 @@ match name { "llvm.hexagon.V6.vmpabus.acc.128B" => "__builtin_HEXAGON_V6_vmpabus_acc_128B", "llvm.hexagon.V6.vmpabusv" => "__builtin_HEXAGON_V6_vmpabusv", "llvm.hexagon.V6.vmpabusv.128B" => "__builtin_HEXAGON_V6_vmpabusv_128B", + "llvm.hexagon.V6.vmpabuu" => "__builtin_HEXAGON_V6_vmpabuu", + "llvm.hexagon.V6.vmpabuu.128B" => "__builtin_HEXAGON_V6_vmpabuu_128B", + "llvm.hexagon.V6.vmpabuu.acc" => "__builtin_HEXAGON_V6_vmpabuu_acc", + "llvm.hexagon.V6.vmpabuu.acc.128B" => "__builtin_HEXAGON_V6_vmpabuu_acc_128B", "llvm.hexagon.V6.vmpabuuv" => "__builtin_HEXAGON_V6_vmpabuuv", "llvm.hexagon.V6.vmpabuuv.128B" => "__builtin_HEXAGON_V6_vmpabuuv_128B", "llvm.hexagon.V6.vmpahb" => "__builtin_HEXAGON_V6_vmpahb", "llvm.hexagon.V6.vmpahb.128B" => "__builtin_HEXAGON_V6_vmpahb_128B", "llvm.hexagon.V6.vmpahb.acc" => "__builtin_HEXAGON_V6_vmpahb_acc", "llvm.hexagon.V6.vmpahb.acc.128B" => "__builtin_HEXAGON_V6_vmpahb_acc_128B", + "llvm.hexagon.V6.vmpahhsat" => "__builtin_HEXAGON_V6_vmpahhsat", + "llvm.hexagon.V6.vmpahhsat.128B" => "__builtin_HEXAGON_V6_vmpahhsat_128B", + "llvm.hexagon.V6.vmpauhb" => "__builtin_HEXAGON_V6_vmpauhb", + "llvm.hexagon.V6.vmpauhb.128B" => "__builtin_HEXAGON_V6_vmpauhb_128B", + "llvm.hexagon.V6.vmpauhb.acc" => "__builtin_HEXAGON_V6_vmpauhb_acc", + "llvm.hexagon.V6.vmpauhb.acc.128B" => "__builtin_HEXAGON_V6_vmpauhb_acc_128B", + "llvm.hexagon.V6.vmpauhuhsat" => "__builtin_HEXAGON_V6_vmpauhuhsat", + "llvm.hexagon.V6.vmpauhuhsat.128B" => "__builtin_HEXAGON_V6_vmpauhuhsat_128B", + "llvm.hexagon.V6.vmpsuhuhsat" => "__builtin_HEXAGON_V6_vmpsuhuhsat", + "llvm.hexagon.V6.vmpsuhuhsat.128B" => "__builtin_HEXAGON_V6_vmpsuhuhsat_128B", + "llvm.hexagon.V6.vmpy.hf.hf" => "__builtin_HEXAGON_V6_vmpy_hf_hf", + "llvm.hexagon.V6.vmpy.hf.hf.128B" => "__builtin_HEXAGON_V6_vmpy_hf_hf_128B", + "llvm.hexagon.V6.vmpy.hf.hf.acc" => "__builtin_HEXAGON_V6_vmpy_hf_hf_acc", + "llvm.hexagon.V6.vmpy.hf.hf.acc.128B" => "__builtin_HEXAGON_V6_vmpy_hf_hf_acc_128B", + "llvm.hexagon.V6.vmpy.qf16" => "__builtin_HEXAGON_V6_vmpy_qf16", + "llvm.hexagon.V6.vmpy.qf16.128B" => "__builtin_HEXAGON_V6_vmpy_qf16_128B", + "llvm.hexagon.V6.vmpy.qf16.hf" => "__builtin_HEXAGON_V6_vmpy_qf16_hf", + "llvm.hexagon.V6.vmpy.qf16.hf.128B" => "__builtin_HEXAGON_V6_vmpy_qf16_hf_128B", + "llvm.hexagon.V6.vmpy.qf16.mix.hf" => "__builtin_HEXAGON_V6_vmpy_qf16_mix_hf", + "llvm.hexagon.V6.vmpy.qf16.mix.hf.128B" => "__builtin_HEXAGON_V6_vmpy_qf16_mix_hf_128B", + "llvm.hexagon.V6.vmpy.qf32" => "__builtin_HEXAGON_V6_vmpy_qf32", + "llvm.hexagon.V6.vmpy.qf32.128B" => "__builtin_HEXAGON_V6_vmpy_qf32_128B", + "llvm.hexagon.V6.vmpy.qf32.hf" => "__builtin_HEXAGON_V6_vmpy_qf32_hf", + "llvm.hexagon.V6.vmpy.qf32.hf.128B" => "__builtin_HEXAGON_V6_vmpy_qf32_hf_128B", + "llvm.hexagon.V6.vmpy.qf32.mix.hf" => "__builtin_HEXAGON_V6_vmpy_qf32_mix_hf", + "llvm.hexagon.V6.vmpy.qf32.mix.hf.128B" => "__builtin_HEXAGON_V6_vmpy_qf32_mix_hf_128B", + "llvm.hexagon.V6.vmpy.qf32.qf16" => "__builtin_HEXAGON_V6_vmpy_qf32_qf16", + "llvm.hexagon.V6.vmpy.qf32.qf16.128B" => "__builtin_HEXAGON_V6_vmpy_qf32_qf16_128B", + "llvm.hexagon.V6.vmpy.qf32.sf" => "__builtin_HEXAGON_V6_vmpy_qf32_sf", + "llvm.hexagon.V6.vmpy.qf32.sf.128B" => "__builtin_HEXAGON_V6_vmpy_qf32_sf_128B", + "llvm.hexagon.V6.vmpy.sf.hf" => "__builtin_HEXAGON_V6_vmpy_sf_hf", + "llvm.hexagon.V6.vmpy.sf.hf.128B" => "__builtin_HEXAGON_V6_vmpy_sf_hf_128B", + "llvm.hexagon.V6.vmpy.sf.hf.acc" => "__builtin_HEXAGON_V6_vmpy_sf_hf_acc", + "llvm.hexagon.V6.vmpy.sf.hf.acc.128B" => "__builtin_HEXAGON_V6_vmpy_sf_hf_acc_128B", + "llvm.hexagon.V6.vmpy.sf.sf" => "__builtin_HEXAGON_V6_vmpy_sf_sf", + "llvm.hexagon.V6.vmpy.sf.sf.128B" => "__builtin_HEXAGON_V6_vmpy_sf_sf_128B", "llvm.hexagon.V6.vmpybus" => "__builtin_HEXAGON_V6_vmpybus", "llvm.hexagon.V6.vmpybus.128B" => "__builtin_HEXAGON_V6_vmpybus_128B", "llvm.hexagon.V6.vmpybus.acc" => "__builtin_HEXAGON_V6_vmpybus_acc", @@ -1368,8 +1810,12 @@ match name { "llvm.hexagon.V6.vmpybv.acc.128B" => "__builtin_HEXAGON_V6_vmpybv_acc_128B", "llvm.hexagon.V6.vmpyewuh" => "__builtin_HEXAGON_V6_vmpyewuh", "llvm.hexagon.V6.vmpyewuh.128B" => "__builtin_HEXAGON_V6_vmpyewuh_128B", + "llvm.hexagon.V6.vmpyewuh.64" => "__builtin_HEXAGON_V6_vmpyewuh_64", + "llvm.hexagon.V6.vmpyewuh.64.128B" => "__builtin_HEXAGON_V6_vmpyewuh_64_128B", "llvm.hexagon.V6.vmpyh" => "__builtin_HEXAGON_V6_vmpyh", "llvm.hexagon.V6.vmpyh.128B" => "__builtin_HEXAGON_V6_vmpyh_128B", + "llvm.hexagon.V6.vmpyh.acc" => "__builtin_HEXAGON_V6_vmpyh_acc", + "llvm.hexagon.V6.vmpyh.acc.128B" => "__builtin_HEXAGON_V6_vmpyh_acc_128B", "llvm.hexagon.V6.vmpyhsat.acc" => "__builtin_HEXAGON_V6_vmpyhsat_acc", "llvm.hexagon.V6.vmpyhsat.acc.128B" => "__builtin_HEXAGON_V6_vmpyhsat_acc_128B", "llvm.hexagon.V6.vmpyhsrs" => "__builtin_HEXAGON_V6_vmpyhsrs", @@ -1412,8 +1858,14 @@ match name { "llvm.hexagon.V6.vmpyiwh.128B" => "__builtin_HEXAGON_V6_vmpyiwh_128B", "llvm.hexagon.V6.vmpyiwh.acc" => "__builtin_HEXAGON_V6_vmpyiwh_acc", "llvm.hexagon.V6.vmpyiwh.acc.128B" => "__builtin_HEXAGON_V6_vmpyiwh_acc_128B", + "llvm.hexagon.V6.vmpyiwub" => "__builtin_HEXAGON_V6_vmpyiwub", + "llvm.hexagon.V6.vmpyiwub.128B" => "__builtin_HEXAGON_V6_vmpyiwub_128B", + "llvm.hexagon.V6.vmpyiwub.acc" => "__builtin_HEXAGON_V6_vmpyiwub_acc", + "llvm.hexagon.V6.vmpyiwub.acc.128B" => "__builtin_HEXAGON_V6_vmpyiwub_acc_128B", "llvm.hexagon.V6.vmpyowh" => "__builtin_HEXAGON_V6_vmpyowh", "llvm.hexagon.V6.vmpyowh.128B" => "__builtin_HEXAGON_V6_vmpyowh_128B", + "llvm.hexagon.V6.vmpyowh.64.acc" => "__builtin_HEXAGON_V6_vmpyowh_64_acc", + "llvm.hexagon.V6.vmpyowh.64.acc.128B" => "__builtin_HEXAGON_V6_vmpyowh_64_acc_128B", "llvm.hexagon.V6.vmpyowh.rnd" => "__builtin_HEXAGON_V6_vmpyowh_rnd", "llvm.hexagon.V6.vmpyowh.rnd.128B" => "__builtin_HEXAGON_V6_vmpyowh_rnd_128B", "llvm.hexagon.V6.vmpyowh.rnd.sacc" => "__builtin_HEXAGON_V6_vmpyowh_rnd_sacc", @@ -1432,10 +1884,20 @@ match name { "llvm.hexagon.V6.vmpyuh.128B" => "__builtin_HEXAGON_V6_vmpyuh_128B", "llvm.hexagon.V6.vmpyuh.acc" => "__builtin_HEXAGON_V6_vmpyuh_acc", "llvm.hexagon.V6.vmpyuh.acc.128B" => "__builtin_HEXAGON_V6_vmpyuh_acc_128B", + "llvm.hexagon.V6.vmpyuhe" => "__builtin_HEXAGON_V6_vmpyuhe", + "llvm.hexagon.V6.vmpyuhe.128B" => "__builtin_HEXAGON_V6_vmpyuhe_128B", + "llvm.hexagon.V6.vmpyuhe.acc" => "__builtin_HEXAGON_V6_vmpyuhe_acc", + "llvm.hexagon.V6.vmpyuhe.acc.128B" => "__builtin_HEXAGON_V6_vmpyuhe_acc_128B", "llvm.hexagon.V6.vmpyuhv" => "__builtin_HEXAGON_V6_vmpyuhv", "llvm.hexagon.V6.vmpyuhv.128B" => "__builtin_HEXAGON_V6_vmpyuhv_128B", "llvm.hexagon.V6.vmpyuhv.acc" => "__builtin_HEXAGON_V6_vmpyuhv_acc", "llvm.hexagon.V6.vmpyuhv.acc.128B" => "__builtin_HEXAGON_V6_vmpyuhv_acc_128B", + "llvm.hexagon.V6.vmpyuhvs" => "__builtin_HEXAGON_V6_vmpyuhvs", + "llvm.hexagon.V6.vmpyuhvs.128B" => "__builtin_HEXAGON_V6_vmpyuhvs_128B", + "llvm.hexagon.V6.vmux" => "__builtin_HEXAGON_V6_vmux", + "llvm.hexagon.V6.vmux.128B" => "__builtin_HEXAGON_V6_vmux_128B", + "llvm.hexagon.V6.vnavgb" => "__builtin_HEXAGON_V6_vnavgb", + "llvm.hexagon.V6.vnavgb.128B" => "__builtin_HEXAGON_V6_vnavgb_128B", "llvm.hexagon.V6.vnavgh" => "__builtin_HEXAGON_V6_vnavgh", "llvm.hexagon.V6.vnavgh.128B" => "__builtin_HEXAGON_V6_vnavgh_128B", "llvm.hexagon.V6.vnavgub" => "__builtin_HEXAGON_V6_vnavgub", @@ -1468,8 +1930,18 @@ match name { "llvm.hexagon.V6.vpackwuh.sat.128B" => "__builtin_HEXAGON_V6_vpackwuh_sat_128B", "llvm.hexagon.V6.vpopcounth" => "__builtin_HEXAGON_V6_vpopcounth", "llvm.hexagon.V6.vpopcounth.128B" => "__builtin_HEXAGON_V6_vpopcounth_128B", + "llvm.hexagon.V6.vprefixqb" => "__builtin_HEXAGON_V6_vprefixqb", + "llvm.hexagon.V6.vprefixqb.128B" => "__builtin_HEXAGON_V6_vprefixqb_128B", + "llvm.hexagon.V6.vprefixqh" => "__builtin_HEXAGON_V6_vprefixqh", + "llvm.hexagon.V6.vprefixqh.128B" => "__builtin_HEXAGON_V6_vprefixqh_128B", + "llvm.hexagon.V6.vprefixqw" => "__builtin_HEXAGON_V6_vprefixqw", + "llvm.hexagon.V6.vprefixqw.128B" => "__builtin_HEXAGON_V6_vprefixqw_128B", "llvm.hexagon.V6.vrdelta" => "__builtin_HEXAGON_V6_vrdelta", "llvm.hexagon.V6.vrdelta.128B" => "__builtin_HEXAGON_V6_vrdelta_128B", + "llvm.hexagon.V6.vrmpybub.rtt" => "__builtin_HEXAGON_V6_vrmpybub_rtt", + "llvm.hexagon.V6.vrmpybub.rtt.128B" => "__builtin_HEXAGON_V6_vrmpybub_rtt_128B", + "llvm.hexagon.V6.vrmpybub.rtt.acc" => "__builtin_HEXAGON_V6_vrmpybub_rtt_acc", + "llvm.hexagon.V6.vrmpybub.rtt.acc.128B" => "__builtin_HEXAGON_V6_vrmpybub_rtt_acc_128B", "llvm.hexagon.V6.vrmpybus" => "__builtin_HEXAGON_V6_vrmpybus", "llvm.hexagon.V6.vrmpybus.128B" => "__builtin_HEXAGON_V6_vrmpybus_128B", "llvm.hexagon.V6.vrmpybus.acc" => "__builtin_HEXAGON_V6_vrmpybus_acc", @@ -1490,6 +1962,10 @@ match name { "llvm.hexagon.V6.vrmpyub.128B" => "__builtin_HEXAGON_V6_vrmpyub_128B", "llvm.hexagon.V6.vrmpyub.acc" => "__builtin_HEXAGON_V6_vrmpyub_acc", "llvm.hexagon.V6.vrmpyub.acc.128B" => "__builtin_HEXAGON_V6_vrmpyub_acc_128B", + "llvm.hexagon.V6.vrmpyub.rtt" => "__builtin_HEXAGON_V6_vrmpyub_rtt", + "llvm.hexagon.V6.vrmpyub.rtt.128B" => "__builtin_HEXAGON_V6_vrmpyub_rtt_128B", + "llvm.hexagon.V6.vrmpyub.rtt.acc" => "__builtin_HEXAGON_V6_vrmpyub_rtt_acc", + "llvm.hexagon.V6.vrmpyub.rtt.acc.128B" => "__builtin_HEXAGON_V6_vrmpyub_rtt_acc_128B", "llvm.hexagon.V6.vrmpyubi" => "__builtin_HEXAGON_V6_vrmpyubi", "llvm.hexagon.V6.vrmpyubi.128B" => "__builtin_HEXAGON_V6_vrmpyubi_128B", "llvm.hexagon.V6.vrmpyubi.acc" => "__builtin_HEXAGON_V6_vrmpyubi_acc", @@ -1500,10 +1976,16 @@ match name { "llvm.hexagon.V6.vrmpyubv.acc.128B" => "__builtin_HEXAGON_V6_vrmpyubv_acc_128B", "llvm.hexagon.V6.vror" => "__builtin_HEXAGON_V6_vror", "llvm.hexagon.V6.vror.128B" => "__builtin_HEXAGON_V6_vror_128B", + "llvm.hexagon.V6.vrotr" => "__builtin_HEXAGON_V6_vrotr", + "llvm.hexagon.V6.vrotr.128B" => "__builtin_HEXAGON_V6_vrotr_128B", "llvm.hexagon.V6.vroundhb" => "__builtin_HEXAGON_V6_vroundhb", "llvm.hexagon.V6.vroundhb.128B" => "__builtin_HEXAGON_V6_vroundhb_128B", "llvm.hexagon.V6.vroundhub" => "__builtin_HEXAGON_V6_vroundhub", "llvm.hexagon.V6.vroundhub.128B" => "__builtin_HEXAGON_V6_vroundhub_128B", + "llvm.hexagon.V6.vrounduhub" => "__builtin_HEXAGON_V6_vrounduhub", + "llvm.hexagon.V6.vrounduhub.128B" => "__builtin_HEXAGON_V6_vrounduhub_128B", + "llvm.hexagon.V6.vrounduwuh" => "__builtin_HEXAGON_V6_vrounduwuh", + "llvm.hexagon.V6.vrounduwuh.128B" => "__builtin_HEXAGON_V6_vrounduwuh_128B", "llvm.hexagon.V6.vroundwh" => "__builtin_HEXAGON_V6_vroundwh", "llvm.hexagon.V6.vroundwh.128B" => "__builtin_HEXAGON_V6_vroundwh_128B", "llvm.hexagon.V6.vroundwuh" => "__builtin_HEXAGON_V6_vroundwuh", @@ -1512,12 +1994,34 @@ match name { "llvm.hexagon.V6.vrsadubi.128B" => "__builtin_HEXAGON_V6_vrsadubi_128B", "llvm.hexagon.V6.vrsadubi.acc" => "__builtin_HEXAGON_V6_vrsadubi_acc", "llvm.hexagon.V6.vrsadubi.acc.128B" => "__builtin_HEXAGON_V6_vrsadubi_acc_128B", + "llvm.hexagon.V6.vsatdw" => "__builtin_HEXAGON_V6_vsatdw", + "llvm.hexagon.V6.vsatdw.128B" => "__builtin_HEXAGON_V6_vsatdw_128B", "llvm.hexagon.V6.vsathub" => "__builtin_HEXAGON_V6_vsathub", "llvm.hexagon.V6.vsathub.128B" => "__builtin_HEXAGON_V6_vsathub_128B", + "llvm.hexagon.V6.vsatuwuh" => "__builtin_HEXAGON_V6_vsatuwuh", + "llvm.hexagon.V6.vsatuwuh.128B" => "__builtin_HEXAGON_V6_vsatuwuh_128B", "llvm.hexagon.V6.vsatwh" => "__builtin_HEXAGON_V6_vsatwh", "llvm.hexagon.V6.vsatwh.128B" => "__builtin_HEXAGON_V6_vsatwh_128B", "llvm.hexagon.V6.vsb" => "__builtin_HEXAGON_V6_vsb", "llvm.hexagon.V6.vsb.128B" => "__builtin_HEXAGON_V6_vsb_128B", + "llvm.hexagon.V6.vscattermh" => "__builtin_HEXAGON_V6_vscattermh", + "llvm.hexagon.V6.vscattermh.128B" => "__builtin_HEXAGON_V6_vscattermh_128B", + "llvm.hexagon.V6.vscattermh.add" => "__builtin_HEXAGON_V6_vscattermh_add", + "llvm.hexagon.V6.vscattermh.add.128B" => "__builtin_HEXAGON_V6_vscattermh_add_128B", + "llvm.hexagon.V6.vscattermhq" => "__builtin_HEXAGON_V6_vscattermhq", + "llvm.hexagon.V6.vscattermhq.128B" => "__builtin_HEXAGON_V6_vscattermhq_128B", + "llvm.hexagon.V6.vscattermhw" => "__builtin_HEXAGON_V6_vscattermhw", + "llvm.hexagon.V6.vscattermhw.128B" => "__builtin_HEXAGON_V6_vscattermhw_128B", + "llvm.hexagon.V6.vscattermhw.add" => "__builtin_HEXAGON_V6_vscattermhw_add", + "llvm.hexagon.V6.vscattermhw.add.128B" => "__builtin_HEXAGON_V6_vscattermhw_add_128B", + "llvm.hexagon.V6.vscattermhwq" => "__builtin_HEXAGON_V6_vscattermhwq", + "llvm.hexagon.V6.vscattermhwq.128B" => "__builtin_HEXAGON_V6_vscattermhwq_128B", + "llvm.hexagon.V6.vscattermw" => "__builtin_HEXAGON_V6_vscattermw", + "llvm.hexagon.V6.vscattermw.128B" => "__builtin_HEXAGON_V6_vscattermw_128B", + "llvm.hexagon.V6.vscattermw.add" => "__builtin_HEXAGON_V6_vscattermw_add", + "llvm.hexagon.V6.vscattermw.add.128B" => "__builtin_HEXAGON_V6_vscattermw_add_128B", + "llvm.hexagon.V6.vscattermwq" => "__builtin_HEXAGON_V6_vscattermwq", + "llvm.hexagon.V6.vscattermwq.128B" => "__builtin_HEXAGON_V6_vscattermwq_128B", "llvm.hexagon.V6.vsh" => "__builtin_HEXAGON_V6_vsh", "llvm.hexagon.V6.vsh.128B" => "__builtin_HEXAGON_V6_vsh_128B", "llvm.hexagon.V6.vshufeh" => "__builtin_HEXAGON_V6_vshufeh", @@ -1538,14 +2042,44 @@ match name { "llvm.hexagon.V6.vshufoeh.128B" => "__builtin_HEXAGON_V6_vshufoeh_128B", "llvm.hexagon.V6.vshufoh" => "__builtin_HEXAGON_V6_vshufoh", "llvm.hexagon.V6.vshufoh.128B" => "__builtin_HEXAGON_V6_vshufoh_128B", + "llvm.hexagon.V6.vsub.hf" => "__builtin_HEXAGON_V6_vsub_hf", + "llvm.hexagon.V6.vsub.hf.128B" => "__builtin_HEXAGON_V6_vsub_hf_128B", + "llvm.hexagon.V6.vsub.hf.hf" => "__builtin_HEXAGON_V6_vsub_hf_hf", + "llvm.hexagon.V6.vsub.hf.hf.128B" => "__builtin_HEXAGON_V6_vsub_hf_hf_128B", + "llvm.hexagon.V6.vsub.qf16" => "__builtin_HEXAGON_V6_vsub_qf16", + "llvm.hexagon.V6.vsub.qf16.128B" => "__builtin_HEXAGON_V6_vsub_qf16_128B", + "llvm.hexagon.V6.vsub.qf16.mix" => "__builtin_HEXAGON_V6_vsub_qf16_mix", + "llvm.hexagon.V6.vsub.qf16.mix.128B" => "__builtin_HEXAGON_V6_vsub_qf16_mix_128B", + "llvm.hexagon.V6.vsub.qf32" => "__builtin_HEXAGON_V6_vsub_qf32", + "llvm.hexagon.V6.vsub.qf32.128B" => "__builtin_HEXAGON_V6_vsub_qf32_128B", + "llvm.hexagon.V6.vsub.qf32.mix" => "__builtin_HEXAGON_V6_vsub_qf32_mix", + "llvm.hexagon.V6.vsub.qf32.mix.128B" => "__builtin_HEXAGON_V6_vsub_qf32_mix_128B", + "llvm.hexagon.V6.vsub.sf" => "__builtin_HEXAGON_V6_vsub_sf", + "llvm.hexagon.V6.vsub.sf.128B" => "__builtin_HEXAGON_V6_vsub_sf_128B", + "llvm.hexagon.V6.vsub.sf.hf" => "__builtin_HEXAGON_V6_vsub_sf_hf", + "llvm.hexagon.V6.vsub.sf.hf.128B" => "__builtin_HEXAGON_V6_vsub_sf_hf_128B", + "llvm.hexagon.V6.vsub.sf.sf" => "__builtin_HEXAGON_V6_vsub_sf_sf", + "llvm.hexagon.V6.vsub.sf.sf.128B" => "__builtin_HEXAGON_V6_vsub_sf_sf_128B", "llvm.hexagon.V6.vsubb" => "__builtin_HEXAGON_V6_vsubb", "llvm.hexagon.V6.vsubb.128B" => "__builtin_HEXAGON_V6_vsubb_128B", "llvm.hexagon.V6.vsubb.dv" => "__builtin_HEXAGON_V6_vsubb_dv", "llvm.hexagon.V6.vsubb.dv.128B" => "__builtin_HEXAGON_V6_vsubb_dv_128B", + "llvm.hexagon.V6.vsubbnq" => "__builtin_HEXAGON_V6_vsubbnq", + "llvm.hexagon.V6.vsubbnq.128B" => "__builtin_HEXAGON_V6_vsubbnq_128B", + "llvm.hexagon.V6.vsubbq" => "__builtin_HEXAGON_V6_vsubbq", + "llvm.hexagon.V6.vsubbq.128B" => "__builtin_HEXAGON_V6_vsubbq_128B", + "llvm.hexagon.V6.vsubbsat" => "__builtin_HEXAGON_V6_vsubbsat", + "llvm.hexagon.V6.vsubbsat.128B" => "__builtin_HEXAGON_V6_vsubbsat_128B", + "llvm.hexagon.V6.vsubbsat.dv" => "__builtin_HEXAGON_V6_vsubbsat_dv", + "llvm.hexagon.V6.vsubbsat.dv.128B" => "__builtin_HEXAGON_V6_vsubbsat_dv_128B", "llvm.hexagon.V6.vsubh" => "__builtin_HEXAGON_V6_vsubh", "llvm.hexagon.V6.vsubh.128B" => "__builtin_HEXAGON_V6_vsubh_128B", "llvm.hexagon.V6.vsubh.dv" => "__builtin_HEXAGON_V6_vsubh_dv", "llvm.hexagon.V6.vsubh.dv.128B" => "__builtin_HEXAGON_V6_vsubh_dv_128B", + "llvm.hexagon.V6.vsubhnq" => "__builtin_HEXAGON_V6_vsubhnq", + "llvm.hexagon.V6.vsubhnq.128B" => "__builtin_HEXAGON_V6_vsubhnq_128B", + "llvm.hexagon.V6.vsubhq" => "__builtin_HEXAGON_V6_vsubhq", + "llvm.hexagon.V6.vsubhq.128B" => "__builtin_HEXAGON_V6_vsubhq_128B", "llvm.hexagon.V6.vsubhsat" => "__builtin_HEXAGON_V6_vsubhsat", "llvm.hexagon.V6.vsubhsat.128B" => "__builtin_HEXAGON_V6_vsubhsat_128B", "llvm.hexagon.V6.vsubhsat.dv" => "__builtin_HEXAGON_V6_vsubhsat_dv", @@ -1558,20 +2092,32 @@ match name { "llvm.hexagon.V6.vsububsat.128B" => "__builtin_HEXAGON_V6_vsububsat_128B", "llvm.hexagon.V6.vsububsat.dv" => "__builtin_HEXAGON_V6_vsububsat_dv", "llvm.hexagon.V6.vsububsat.dv.128B" => "__builtin_HEXAGON_V6_vsububsat_dv_128B", + "llvm.hexagon.V6.vsubububb.sat" => "__builtin_HEXAGON_V6_vsubububb_sat", + "llvm.hexagon.V6.vsubububb.sat.128B" => "__builtin_HEXAGON_V6_vsubububb_sat_128B", "llvm.hexagon.V6.vsubuhsat" => "__builtin_HEXAGON_V6_vsubuhsat", "llvm.hexagon.V6.vsubuhsat.128B" => "__builtin_HEXAGON_V6_vsubuhsat_128B", "llvm.hexagon.V6.vsubuhsat.dv" => "__builtin_HEXAGON_V6_vsubuhsat_dv", "llvm.hexagon.V6.vsubuhsat.dv.128B" => "__builtin_HEXAGON_V6_vsubuhsat_dv_128B", "llvm.hexagon.V6.vsubuhw" => "__builtin_HEXAGON_V6_vsubuhw", "llvm.hexagon.V6.vsubuhw.128B" => "__builtin_HEXAGON_V6_vsubuhw_128B", + "llvm.hexagon.V6.vsubuwsat" => "__builtin_HEXAGON_V6_vsubuwsat", + "llvm.hexagon.V6.vsubuwsat.128B" => "__builtin_HEXAGON_V6_vsubuwsat_128B", + "llvm.hexagon.V6.vsubuwsat.dv" => "__builtin_HEXAGON_V6_vsubuwsat_dv", + "llvm.hexagon.V6.vsubuwsat.dv.128B" => "__builtin_HEXAGON_V6_vsubuwsat_dv_128B", "llvm.hexagon.V6.vsubw" => "__builtin_HEXAGON_V6_vsubw", "llvm.hexagon.V6.vsubw.128B" => "__builtin_HEXAGON_V6_vsubw_128B", "llvm.hexagon.V6.vsubw.dv" => "__builtin_HEXAGON_V6_vsubw_dv", "llvm.hexagon.V6.vsubw.dv.128B" => "__builtin_HEXAGON_V6_vsubw_dv_128B", + "llvm.hexagon.V6.vsubwnq" => "__builtin_HEXAGON_V6_vsubwnq", + "llvm.hexagon.V6.vsubwnq.128B" => "__builtin_HEXAGON_V6_vsubwnq_128B", + "llvm.hexagon.V6.vsubwq" => "__builtin_HEXAGON_V6_vsubwq", + "llvm.hexagon.V6.vsubwq.128B" => "__builtin_HEXAGON_V6_vsubwq_128B", "llvm.hexagon.V6.vsubwsat" => "__builtin_HEXAGON_V6_vsubwsat", "llvm.hexagon.V6.vsubwsat.128B" => "__builtin_HEXAGON_V6_vsubwsat_128B", "llvm.hexagon.V6.vsubwsat.dv" => "__builtin_HEXAGON_V6_vsubwsat_dv", "llvm.hexagon.V6.vsubwsat.dv.128B" => "__builtin_HEXAGON_V6_vsubwsat_dv_128B", + "llvm.hexagon.V6.vswap" => "__builtin_HEXAGON_V6_vswap", + "llvm.hexagon.V6.vswap.128B" => "__builtin_HEXAGON_V6_vswap_128B", "llvm.hexagon.V6.vtmpyb" => "__builtin_HEXAGON_V6_vtmpyb", "llvm.hexagon.V6.vtmpyb.128B" => "__builtin_HEXAGON_V6_vtmpyb_128B", "llvm.hexagon.V6.vtmpyb.acc" => "__builtin_HEXAGON_V6_vtmpyb_acc", @@ -1602,6 +2148,19 @@ match name { "llvm.hexagon.V6.vzb.128B" => "__builtin_HEXAGON_V6_vzb_128B", "llvm.hexagon.V6.vzh" => "__builtin_HEXAGON_V6_vzh", "llvm.hexagon.V6.vzh.128B" => "__builtin_HEXAGON_V6_vzh_128B", + "llvm.hexagon.Y2.dccleana" => "__builtin_HEXAGON_Y2_dccleana", + "llvm.hexagon.Y2.dccleaninva" => "__builtin_HEXAGON_Y2_dccleaninva", + "llvm.hexagon.Y2.dcfetch" => "__builtin_HEXAGON_Y2_dcfetch", + "llvm.hexagon.Y2.dcinva" => "__builtin_HEXAGON_Y2_dcinva", + "llvm.hexagon.Y2.dczeroa" => "__builtin_HEXAGON_Y2_dczeroa", + "llvm.hexagon.Y4.l2fetch" => "__builtin_HEXAGON_Y4_l2fetch", + "llvm.hexagon.Y5.l2fetch" => "__builtin_HEXAGON_Y5_l2fetch", + "llvm.hexagon.Y6.dmlink" => "__builtin_HEXAGON_Y6_dmlink", + "llvm.hexagon.Y6.dmpause" => "__builtin_HEXAGON_Y6_dmpause", + "llvm.hexagon.Y6.dmpoll" => "__builtin_HEXAGON_Y6_dmpoll", + "llvm.hexagon.Y6.dmresume" => "__builtin_HEXAGON_Y6_dmresume", + "llvm.hexagon.Y6.dmstart" => "__builtin_HEXAGON_Y6_dmstart", + "llvm.hexagon.Y6.dmwait" => "__builtin_HEXAGON_Y6_dmwait", "llvm.hexagon.brev.ldb" => "__builtin_brev_ldb", "llvm.hexagon.brev.ldd" => "__builtin_brev_ldd", "llvm.hexagon.brev.ldh" => "__builtin_brev_ldh", @@ -1626,6 +2185,8 @@ match name { "llvm.hexagon.circ.stw" => "__builtin_circ_stw", "llvm.hexagon.mm256i.vaddw" => "__builtin__mm256i_vaddw", "llvm.hexagon.prefetch" => "__builtin_HEXAGON_prefetch", + "llvm.hexagon.vmemcpy" => "__builtin_hexagon_vmemcpy", + "llvm.hexagon.vmemset" => "__builtin_hexagon_vmemset", // mips "llvm.mips.absq.s.ph" => "__builtin_mips_absq_s_ph", "llvm.mips.absq.s.qb" => "__builtin_mips_absq_s_qb", @@ -2299,6 +2860,8 @@ match name { "llvm.mips.xor.v" => "__builtin_msa_xor_v", "llvm.mips.xori.b" => "__builtin_msa_xori_b", // nvvm + "llvm.nvvm.abs.bf16" => "__nvvm_abs_bf16", + "llvm.nvvm.abs.bf16x2" => "__nvvm_abs_bf16x2", "llvm.nvvm.abs.i" => "__nvvm_abs_i", "llvm.nvvm.abs.ll" => "__nvvm_abs_ll", "llvm.nvvm.add.rm.d" => "__nvvm_add_rm_d", @@ -2314,8 +2877,13 @@ match name { "llvm.nvvm.add.rz.f" => "__nvvm_add_rz_f", "llvm.nvvm.add.rz.ftz.f" => "__nvvm_add_rz_ftz_f", "llvm.nvvm.bar.sync" => "__nvvm_bar_sync", - "llvm.nvvm.barrier0" => "__nvvm_bar0", - // [DUPLICATE]: "llvm.nvvm.barrier0" => "__syncthreads", + "llvm.nvvm.bar.warp.sync" => "__nvvm_bar_warp_sync", + "llvm.nvvm.barrier" => "__nvvm_bar", + "llvm.nvvm.barrier.n" => "__nvvm_bar_n", + "llvm.nvvm.barrier.sync" => "__nvvm_barrier_sync", + "llvm.nvvm.barrier.sync.cnt" => "__nvvm_barrier_sync_cnt", + "llvm.nvvm.barrier0" => "__syncthreads", + // [DUPLICATE]: "llvm.nvvm.barrier0" => "__nvvm_bar0", "llvm.nvvm.barrier0.and" => "__nvvm_bar0_and", "llvm.nvvm.barrier0.or" => "__nvvm_bar0_or", "llvm.nvvm.barrier0.popc" => "__nvvm_bar0_popc", @@ -2332,6 +2900,17 @@ match name { "llvm.nvvm.clz.ll" => "__nvvm_clz_ll", "llvm.nvvm.cos.approx.f" => "__nvvm_cos_approx_f", "llvm.nvvm.cos.approx.ftz.f" => "__nvvm_cos_approx_ftz_f", + "llvm.nvvm.cp.async.ca.shared.global.16" => "__nvvm_cp_async_ca_shared_global_16", + "llvm.nvvm.cp.async.ca.shared.global.4" => "__nvvm_cp_async_ca_shared_global_4", + "llvm.nvvm.cp.async.ca.shared.global.8" => "__nvvm_cp_async_ca_shared_global_8", + "llvm.nvvm.cp.async.cg.shared.global.16" => "__nvvm_cp_async_cg_shared_global_16", + "llvm.nvvm.cp.async.commit.group" => "__nvvm_cp_async_commit_group", + "llvm.nvvm.cp.async.mbarrier.arrive" => "__nvvm_cp_async_mbarrier_arrive", + "llvm.nvvm.cp.async.mbarrier.arrive.noinc" => "__nvvm_cp_async_mbarrier_arrive_noinc", + "llvm.nvvm.cp.async.mbarrier.arrive.noinc.shared" => "__nvvm_cp_async_mbarrier_arrive_noinc_shared", + "llvm.nvvm.cp.async.mbarrier.arrive.shared" => "__nvvm_cp_async_mbarrier_arrive_shared", + "llvm.nvvm.cp.async.wait.all" => "__nvvm_cp_async_wait_all", + "llvm.nvvm.cp.async.wait.group" => "__nvvm_cp_async_wait_group", "llvm.nvvm.d2f.rm" => "__nvvm_d2f_rm", "llvm.nvvm.d2f.rm.ftz" => "__nvvm_d2f_rm_ftz", "llvm.nvvm.d2f.rn" => "__nvvm_d2f_rn", @@ -2374,7 +2953,13 @@ match name { "llvm.nvvm.div.rz.ftz.f" => "__nvvm_div_rz_ftz_f", "llvm.nvvm.ex2.approx.d" => "__nvvm_ex2_approx_d", "llvm.nvvm.ex2.approx.f" => "__nvvm_ex2_approx_f", + "llvm.nvvm.ex2.approx.f16" => "__nvvm_ex2_approx_f16", + "llvm.nvvm.ex2.approx.f16x2" => "__nvvm_ex2_approx_f16x2", "llvm.nvvm.ex2.approx.ftz.f" => "__nvvm_ex2_approx_ftz_f", + "llvm.nvvm.f2bf16.rn" => "__nvvm_f2bf16_rn", + "llvm.nvvm.f2bf16.rn.relu" => "__nvvm_f2bf16_rn_relu", + "llvm.nvvm.f2bf16.rz" => "__nvvm_f2bf16_rz", + "llvm.nvvm.f2bf16.rz.relu" => "__nvvm_f2bf16_rz_relu", "llvm.nvvm.f2h.rn" => "__nvvm_f2h_rn", "llvm.nvvm.f2h.rn.ftz" => "__nvvm_f2h_rn_ftz", "llvm.nvvm.f2i.rm" => "__nvvm_f2i_rm", @@ -2393,6 +2978,7 @@ match name { "llvm.nvvm.f2ll.rp.ftz" => "__nvvm_f2ll_rp_ftz", "llvm.nvvm.f2ll.rz" => "__nvvm_f2ll_rz", "llvm.nvvm.f2ll.rz.ftz" => "__nvvm_f2ll_rz_ftz", + "llvm.nvvm.f2tf32.rna" => "__nvvm_f2tf32_rna", "llvm.nvvm.f2ui.rm" => "__nvvm_f2ui_rm", "llvm.nvvm.f2ui.rm.ftz" => "__nvvm_f2ui_rm_ftz", "llvm.nvvm.f2ui.rn" => "__nvvm_f2ui_rn", @@ -2412,27 +2998,112 @@ match name { "llvm.nvvm.fabs.d" => "__nvvm_fabs_d", "llvm.nvvm.fabs.f" => "__nvvm_fabs_f", "llvm.nvvm.fabs.ftz.f" => "__nvvm_fabs_ftz_f", + "llvm.nvvm.ff2bf16x2.rn" => "__nvvm_ff2bf16x2_rn", + "llvm.nvvm.ff2bf16x2.rn.relu" => "__nvvm_ff2bf16x2_rn_relu", + "llvm.nvvm.ff2bf16x2.rz" => "__nvvm_ff2bf16x2_rz", + "llvm.nvvm.ff2bf16x2.rz.relu" => "__nvvm_ff2bf16x2_rz_relu", + "llvm.nvvm.ff2f16x2.rn" => "__nvvm_ff2f16x2_rn", + "llvm.nvvm.ff2f16x2.rn.relu" => "__nvvm_ff2f16x2_rn_relu", + "llvm.nvvm.ff2f16x2.rz" => "__nvvm_ff2f16x2_rz", + "llvm.nvvm.ff2f16x2.rz.relu" => "__nvvm_ff2f16x2_rz_relu", "llvm.nvvm.floor.d" => "__nvvm_floor_d", "llvm.nvvm.floor.f" => "__nvvm_floor_f", "llvm.nvvm.floor.ftz.f" => "__nvvm_floor_ftz_f", "llvm.nvvm.fma.rm.d" => "__nvvm_fma_rm_d", "llvm.nvvm.fma.rm.f" => "__nvvm_fma_rm_f", "llvm.nvvm.fma.rm.ftz.f" => "__nvvm_fma_rm_ftz_f", + "llvm.nvvm.fma.rn.bf16" => "__nvvm_fma_rn_bf16", + "llvm.nvvm.fma.rn.bf16x2" => "__nvvm_fma_rn_bf16x2", "llvm.nvvm.fma.rn.d" => "__nvvm_fma_rn_d", "llvm.nvvm.fma.rn.f" => "__nvvm_fma_rn_f", + "llvm.nvvm.fma.rn.f16" => "__nvvm_fma_rn_f16", + "llvm.nvvm.fma.rn.f16x2" => "__nvvm_fma_rn_f16x2", "llvm.nvvm.fma.rn.ftz.f" => "__nvvm_fma_rn_ftz_f", + "llvm.nvvm.fma.rn.ftz.f16" => "__nvvm_fma_rn_ftz_f16", + "llvm.nvvm.fma.rn.ftz.f16x2" => "__nvvm_fma_rn_ftz_f16x2", + "llvm.nvvm.fma.rn.ftz.relu.f16" => "__nvvm_fma_rn_ftz_relu_f16", + "llvm.nvvm.fma.rn.ftz.relu.f16x2" => "__nvvm_fma_rn_ftz_relu_f16x2", + "llvm.nvvm.fma.rn.ftz.sat.f16" => "__nvvm_fma_rn_ftz_sat_f16", + "llvm.nvvm.fma.rn.ftz.sat.f16x2" => "__nvvm_fma_rn_ftz_sat_f16x2", + "llvm.nvvm.fma.rn.relu.bf16" => "__nvvm_fma_rn_relu_bf16", + "llvm.nvvm.fma.rn.relu.bf16x2" => "__nvvm_fma_rn_relu_bf16x2", + "llvm.nvvm.fma.rn.relu.f16" => "__nvvm_fma_rn_relu_f16", + "llvm.nvvm.fma.rn.relu.f16x2" => "__nvvm_fma_rn_relu_f16x2", + "llvm.nvvm.fma.rn.sat.f16" => "__nvvm_fma_rn_sat_f16", + "llvm.nvvm.fma.rn.sat.f16x2" => "__nvvm_fma_rn_sat_f16x2", "llvm.nvvm.fma.rp.d" => "__nvvm_fma_rp_d", "llvm.nvvm.fma.rp.f" => "__nvvm_fma_rp_f", "llvm.nvvm.fma.rp.ftz.f" => "__nvvm_fma_rp_ftz_f", "llvm.nvvm.fma.rz.d" => "__nvvm_fma_rz_d", "llvm.nvvm.fma.rz.f" => "__nvvm_fma_rz_f", "llvm.nvvm.fma.rz.ftz.f" => "__nvvm_fma_rz_ftz_f", + "llvm.nvvm.fmax.bf16" => "__nvvm_fmax_bf16", + "llvm.nvvm.fmax.bf16x2" => "__nvvm_fmax_bf16x2", "llvm.nvvm.fmax.d" => "__nvvm_fmax_d", "llvm.nvvm.fmax.f" => "__nvvm_fmax_f", + "llvm.nvvm.fmax.f16" => "__nvvm_fmax_f16", + "llvm.nvvm.fmax.f16x2" => "__nvvm_fmax_f16x2", "llvm.nvvm.fmax.ftz.f" => "__nvvm_fmax_ftz_f", + "llvm.nvvm.fmax.ftz.f16" => "__nvvm_fmax_ftz_f16", + "llvm.nvvm.fmax.ftz.f16x2" => "__nvvm_fmax_ftz_f16x2", + "llvm.nvvm.fmax.ftz.nan.f" => "__nvvm_fmax_ftz_nan_f", + "llvm.nvvm.fmax.ftz.nan.f16" => "__nvvm_fmax_ftz_nan_f16", + "llvm.nvvm.fmax.ftz.nan.f16x2" => "__nvvm_fmax_ftz_nan_f16x2", + "llvm.nvvm.fmax.ftz.nan.xorsign.abs.f" => "__nvvm_fmax_ftz_nan_xorsign_abs_f", + "llvm.nvvm.fmax.ftz.nan.xorsign.abs.f16" => "__nvvm_fmax_ftz_nan_xorsign_abs_f16", + "llvm.nvvm.fmax.ftz.nan.xorsign.abs.f16x2" => "__nvvm_fmax_ftz_nan_xorsign_abs_f16x2", + "llvm.nvvm.fmax.ftz.xorsign.abs.f" => "__nvvm_fmax_ftz_xorsign_abs_f", + "llvm.nvvm.fmax.ftz.xorsign.abs.f16" => "__nvvm_fmax_ftz_xorsign_abs_f16", + "llvm.nvvm.fmax.ftz.xorsign.abs.f16x2" => "__nvvm_fmax_ftz_xorsign_abs_f16x2", + "llvm.nvvm.fmax.nan.bf16" => "__nvvm_fmax_nan_bf16", + "llvm.nvvm.fmax.nan.bf16x2" => "__nvvm_fmax_nan_bf16x2", + "llvm.nvvm.fmax.nan.f" => "__nvvm_fmax_nan_f", + "llvm.nvvm.fmax.nan.f16" => "__nvvm_fmax_nan_f16", + "llvm.nvvm.fmax.nan.f16x2" => "__nvvm_fmax_nan_f16x2", + "llvm.nvvm.fmax.nan.xorsign.abs.bf16" => "__nvvm_fmax_nan_xorsign_abs_bf16", + "llvm.nvvm.fmax.nan.xorsign.abs.bf16x2" => "__nvvm_fmax_nan_xorsign_abs_bf16x2", + "llvm.nvvm.fmax.nan.xorsign.abs.f" => "__nvvm_fmax_nan_xorsign_abs_f", + "llvm.nvvm.fmax.nan.xorsign.abs.f16" => "__nvvm_fmax_nan_xorsign_abs_f16", + "llvm.nvvm.fmax.nan.xorsign.abs.f16x2" => "__nvvm_fmax_nan_xorsign_abs_f16x2", + "llvm.nvvm.fmax.xorsign.abs.bf16" => "__nvvm_fmax_xorsign_abs_bf16", + "llvm.nvvm.fmax.xorsign.abs.bf16x2" => "__nvvm_fmax_xorsign_abs_bf16x2", + "llvm.nvvm.fmax.xorsign.abs.f" => "__nvvm_fmax_xorsign_abs_f", + "llvm.nvvm.fmax.xorsign.abs.f16" => "__nvvm_fmax_xorsign_abs_f16", + "llvm.nvvm.fmax.xorsign.abs.f16x2" => "__nvvm_fmax_xorsign_abs_f16x2", + "llvm.nvvm.fmin.bf16" => "__nvvm_fmin_bf16", + "llvm.nvvm.fmin.bf16x2" => "__nvvm_fmin_bf16x2", "llvm.nvvm.fmin.d" => "__nvvm_fmin_d", "llvm.nvvm.fmin.f" => "__nvvm_fmin_f", + "llvm.nvvm.fmin.f16" => "__nvvm_fmin_f16", + "llvm.nvvm.fmin.f16x2" => "__nvvm_fmin_f16x2", "llvm.nvvm.fmin.ftz.f" => "__nvvm_fmin_ftz_f", + "llvm.nvvm.fmin.ftz.f16" => "__nvvm_fmin_ftz_f16", + "llvm.nvvm.fmin.ftz.f16x2" => "__nvvm_fmin_ftz_f16x2", + "llvm.nvvm.fmin.ftz.nan.f" => "__nvvm_fmin_ftz_nan_f", + "llvm.nvvm.fmin.ftz.nan.f16" => "__nvvm_fmin_ftz_nan_f16", + "llvm.nvvm.fmin.ftz.nan.f16x2" => "__nvvm_fmin_ftz_nan_f16x2", + "llvm.nvvm.fmin.ftz.nan.xorsign.abs.f" => "__nvvm_fmin_ftz_nan_xorsign_abs_f", + "llvm.nvvm.fmin.ftz.nan.xorsign.abs.f16" => "__nvvm_fmin_ftz_nan_xorsign_abs_f16", + "llvm.nvvm.fmin.ftz.nan.xorsign.abs.f16x2" => "__nvvm_fmin_ftz_nan_xorsign_abs_f16x2", + "llvm.nvvm.fmin.ftz.xorsign.abs.f" => "__nvvm_fmin_ftz_xorsign_abs_f", + "llvm.nvvm.fmin.ftz.xorsign.abs.f16" => "__nvvm_fmin_ftz_xorsign_abs_f16", + "llvm.nvvm.fmin.ftz.xorsign.abs.f16x2" => "__nvvm_fmin_ftz_xorsign_abs_f16x2", + "llvm.nvvm.fmin.nan.bf16" => "__nvvm_fmin_nan_bf16", + "llvm.nvvm.fmin.nan.bf16x2" => "__nvvm_fmin_nan_bf16x2", + "llvm.nvvm.fmin.nan.f" => "__nvvm_fmin_nan_f", + "llvm.nvvm.fmin.nan.f16" => "__nvvm_fmin_nan_f16", + "llvm.nvvm.fmin.nan.f16x2" => "__nvvm_fmin_nan_f16x2", + "llvm.nvvm.fmin.nan.xorsign.abs.bf16" => "__nvvm_fmin_nan_xorsign_abs_bf16", + "llvm.nvvm.fmin.nan.xorsign.abs.bf16x2" => "__nvvm_fmin_nan_xorsign_abs_bf16x2", + "llvm.nvvm.fmin.nan.xorsign.abs.f" => "__nvvm_fmin_nan_xorsign_abs_f", + "llvm.nvvm.fmin.nan.xorsign.abs.f16" => "__nvvm_fmin_nan_xorsign_abs_f16", + "llvm.nvvm.fmin.nan.xorsign.abs.f16x2" => "__nvvm_fmin_nan_xorsign_abs_f16x2", + "llvm.nvvm.fmin.xorsign.abs.bf16" => "__nvvm_fmin_xorsign_abs_bf16", + "llvm.nvvm.fmin.xorsign.abs.bf16x2" => "__nvvm_fmin_xorsign_abs_bf16x2", + "llvm.nvvm.fmin.xorsign.abs.f" => "__nvvm_fmin_xorsign_abs_f", + "llvm.nvvm.fmin.xorsign.abs.f16" => "__nvvm_fmin_xorsign_abs_f16", + "llvm.nvvm.fmin.xorsign.abs.f16x2" => "__nvvm_fmin_xorsign_abs_f16x2", + "llvm.nvvm.fns" => "__nvvm_fns", "llvm.nvvm.h2f" => "__nvvm_h2f", "llvm.nvvm.i2d.rm" => "__nvvm_i2d_rm", "llvm.nvvm.i2d.rn" => "__nvvm_i2d_rn", @@ -2461,10 +3132,27 @@ match name { "llvm.nvvm.ll2f.rp" => "__nvvm_ll2f_rp", "llvm.nvvm.ll2f.rz" => "__nvvm_ll2f_rz", "llvm.nvvm.lohi.i2d" => "__nvvm_lohi_i2d", + "llvm.nvvm.match.any.sync.i32" => "__nvvm_match_any_sync_i32", + "llvm.nvvm.match.any.sync.i64" => "__nvvm_match_any_sync_i64", "llvm.nvvm.max.i" => "__nvvm_max_i", "llvm.nvvm.max.ll" => "__nvvm_max_ll", "llvm.nvvm.max.ui" => "__nvvm_max_ui", "llvm.nvvm.max.ull" => "__nvvm_max_ull", + "llvm.nvvm.mbarrier.arrive" => "__nvvm_mbarrier_arrive", + "llvm.nvvm.mbarrier.arrive.drop" => "__nvvm_mbarrier_arrive_drop", + "llvm.nvvm.mbarrier.arrive.drop.noComplete" => "__nvvm_mbarrier_arrive_drop_noComplete", + "llvm.nvvm.mbarrier.arrive.drop.noComplete.shared" => "__nvvm_mbarrier_arrive_drop_noComplete_shared", + "llvm.nvvm.mbarrier.arrive.drop.shared" => "__nvvm_mbarrier_arrive_drop_shared", + "llvm.nvvm.mbarrier.arrive.noComplete" => "__nvvm_mbarrier_arrive_noComplete", + "llvm.nvvm.mbarrier.arrive.noComplete.shared" => "__nvvm_mbarrier_arrive_noComplete_shared", + "llvm.nvvm.mbarrier.arrive.shared" => "__nvvm_mbarrier_arrive_shared", + "llvm.nvvm.mbarrier.init" => "__nvvm_mbarrier_init", + "llvm.nvvm.mbarrier.init.shared" => "__nvvm_mbarrier_init_shared", + "llvm.nvvm.mbarrier.inval" => "__nvvm_mbarrier_inval", + "llvm.nvvm.mbarrier.inval.shared" => "__nvvm_mbarrier_inval_shared", + "llvm.nvvm.mbarrier.pending.count" => "__nvvm_mbarrier_pending_count", + "llvm.nvvm.mbarrier.test.wait" => "__nvvm_mbarrier_test_wait", + "llvm.nvvm.mbarrier.test.wait.shared" => "__nvvm_mbarrier_test_wait_shared", "llvm.nvvm.membar.cta" => "__nvvm_membar_cta", "llvm.nvvm.membar.gl" => "__nvvm_membar_gl", "llvm.nvvm.membar.sys" => "__nvvm_membar_sys", @@ -2490,10 +3178,13 @@ match name { "llvm.nvvm.mulhi.ll" => "__nvvm_mulhi_ll", "llvm.nvvm.mulhi.ui" => "__nvvm_mulhi_ui", "llvm.nvvm.mulhi.ull" => "__nvvm_mulhi_ull", + "llvm.nvvm.neg.bf16" => "__nvvm_neg_bf16", + "llvm.nvvm.neg.bf16x2" => "__nvvm_neg_bf16x2", "llvm.nvvm.popc.i" => "__nvvm_popc_i", "llvm.nvvm.popc.ll" => "__nvvm_popc_ll", "llvm.nvvm.prmt" => "__nvvm_prmt", "llvm.nvvm.rcp.approx.ftz.d" => "__nvvm_rcp_approx_ftz_d", + "llvm.nvvm.rcp.approx.ftz.f" => "__nvvm_rcp_approx_ftz_f", "llvm.nvvm.rcp.rm.d" => "__nvvm_rcp_rm_d", "llvm.nvvm.rcp.rm.f" => "__nvvm_rcp_rm_f", "llvm.nvvm.rcp.rm.ftz.f" => "__nvvm_rcp_rm_ftz_f", @@ -2506,8 +3197,11 @@ match name { "llvm.nvvm.rcp.rz.d" => "__nvvm_rcp_rz_d", "llvm.nvvm.rcp.rz.f" => "__nvvm_rcp_rz_f", "llvm.nvvm.rcp.rz.ftz.f" => "__nvvm_rcp_rz_ftz_f", - "llvm.nvvm.read.ptx.sreg.clock" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.clock64" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.clock" => "__nvvm_read_ptx_sreg_clock", + // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.clock" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.clock64" => "__nvvm_read_ptx_sreg_clock64", + // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.clock64" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.ctaid.w" => "__nvvm_read_ptx_sreg_ctaid_w", "llvm.nvvm.read.ptx.sreg.ctaid.x" => "__nvvm_read_ptx_sreg_ctaid_x", "llvm.nvvm.read.ptx.sreg.ctaid.y" => "__nvvm_read_ptx_sreg_ctaid_y", "llvm.nvvm.read.ptx.sreg.ctaid.z" => "__nvvm_read_ptx_sreg_ctaid_z", @@ -2543,32 +3237,58 @@ match name { "llvm.nvvm.read.ptx.sreg.envreg7" => "__nvvm_read_ptx_sreg_envreg7", "llvm.nvvm.read.ptx.sreg.envreg8" => "__nvvm_read_ptx_sreg_envreg8", "llvm.nvvm.read.ptx.sreg.envreg9" => "__nvvm_read_ptx_sreg_envreg9", - "llvm.nvvm.read.ptx.sreg.gridid" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.laneid" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.lanemask.eq" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.lanemask.ge" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.lanemask.gt" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.lanemask.le" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.lanemask.lt" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.gridid" => "__nvvm_read_ptx_sreg_gridid", + // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.gridid" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.laneid" => "__nvvm_read_ptx_sreg_laneid", + // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.laneid" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.lanemask.eq" => "__nvvm_read_ptx_sreg_lanemask_eq", + // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.lanemask.eq" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.lanemask.ge" => "__nvvm_read_ptx_sreg_lanemask_ge", + // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.lanemask.ge" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.lanemask.gt" => "__nvvm_read_ptx_sreg_lanemask_gt", + // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.lanemask.gt" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.lanemask.le" => "__nvvm_read_ptx_sreg_lanemask_le", + // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.lanemask.le" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.lanemask.lt" => "__nvvm_read_ptx_sreg_lanemask_lt", + // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.lanemask.lt" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.nctaid.w" => "__nvvm_read_ptx_sreg_nctaid_w", "llvm.nvvm.read.ptx.sreg.nctaid.x" => "__nvvm_read_ptx_sreg_nctaid_x", "llvm.nvvm.read.ptx.sreg.nctaid.y" => "__nvvm_read_ptx_sreg_nctaid_y", "llvm.nvvm.read.ptx.sreg.nctaid.z" => "__nvvm_read_ptx_sreg_nctaid_z", - "llvm.nvvm.read.ptx.sreg.nsmid" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.nsmid" => "__nvvm_read_ptx_sreg_nsmid", + // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.nsmid" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.ntid.w" => "__nvvm_read_ptx_sreg_ntid_w", "llvm.nvvm.read.ptx.sreg.ntid.x" => "__nvvm_read_ptx_sreg_ntid_x", "llvm.nvvm.read.ptx.sreg.ntid.y" => "__nvvm_read_ptx_sreg_ntid_y", "llvm.nvvm.read.ptx.sreg.ntid.z" => "__nvvm_read_ptx_sreg_ntid_z", - "llvm.nvvm.read.ptx.sreg.nwarpid" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.pm0" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.pm1" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.pm2" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.pm3" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.smid" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.nwarpid" => "__nvvm_read_ptx_sreg_nwarpid", + // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.nwarpid" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.pm0" => "__nvvm_read_ptx_sreg_pm0", + // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.pm0" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.pm1" => "__nvvm_read_ptx_sreg_pm1", + // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.pm1" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.pm2" => "__nvvm_read_ptx_sreg_pm2", + // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.pm2" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.pm3" => "__nvvm_read_ptx_sreg_pm3", + // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.pm3" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.smid" => "__nvvm_read_ptx_sreg_smid", + // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.smid" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.tid.w" => "__nvvm_read_ptx_sreg_tid_w", "llvm.nvvm.read.ptx.sreg.tid.x" => "__nvvm_read_ptx_sreg_tid_x", "llvm.nvvm.read.ptx.sreg.tid.y" => "__nvvm_read_ptx_sreg_tid_y", "llvm.nvvm.read.ptx.sreg.tid.z" => "__nvvm_read_ptx_sreg_tid_z", - "llvm.nvvm.read.ptx.sreg.warpid" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.read.ptx.sreg.warpid" => "__nvvm_read_ptx_sreg_warpid", + // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.warpid" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.warpsize" => "__nvvm_read_ptx_sreg_warpsize", // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.warpsize" => "__nvvm_read_ptx_sreg_", + "llvm.nvvm.redux.sync.add" => "__nvvm_redux_sync_add", + "llvm.nvvm.redux.sync.and" => "__nvvm_redux_sync_and", + "llvm.nvvm.redux.sync.max" => "__nvvm_redux_sync_max", + "llvm.nvvm.redux.sync.min" => "__nvvm_redux_sync_min", + "llvm.nvvm.redux.sync.or" => "__nvvm_redux_sync_or", + "llvm.nvvm.redux.sync.umax" => "__nvvm_redux_sync_umax", + "llvm.nvvm.redux.sync.umin" => "__nvvm_redux_sync_umin", + "llvm.nvvm.redux.sync.xor" => "__nvvm_redux_sync_xor", "llvm.nvvm.rotate.b32" => "__nvvm_rotate_b32", "llvm.nvvm.rotate.b64" => "__nvvm_rotate_b64", "llvm.nvvm.rotate.right.b64" => "__nvvm_rotate_right_b64", @@ -2589,6 +3309,14 @@ match name { "llvm.nvvm.shfl.down.i32" => "__nvvm_shfl_down_i32", "llvm.nvvm.shfl.idx.f32" => "__nvvm_shfl_idx_f32", "llvm.nvvm.shfl.idx.i32" => "__nvvm_shfl_idx_i32", + "llvm.nvvm.shfl.sync.bfly.f32" => "__nvvm_shfl_sync_bfly_f32", + "llvm.nvvm.shfl.sync.bfly.i32" => "__nvvm_shfl_sync_bfly_i32", + "llvm.nvvm.shfl.sync.down.f32" => "__nvvm_shfl_sync_down_f32", + "llvm.nvvm.shfl.sync.down.i32" => "__nvvm_shfl_sync_down_i32", + "llvm.nvvm.shfl.sync.idx.f32" => "__nvvm_shfl_sync_idx_f32", + "llvm.nvvm.shfl.sync.idx.i32" => "__nvvm_shfl_sync_idx_i32", + "llvm.nvvm.shfl.sync.up.f32" => "__nvvm_shfl_sync_up_f32", + "llvm.nvvm.shfl.sync.up.i32" => "__nvvm_shfl_sync_up_i32", "llvm.nvvm.shfl.up.f32" => "__nvvm_shfl_up_f32", "llvm.nvvm.shfl.up.i32" => "__nvvm_shfl_up_i32", "llvm.nvvm.sin.approx.f" => "__nvvm_sin_approx_f", @@ -2852,6 +3580,14 @@ match name { "llvm.nvvm.ull2f.rn" => "__nvvm_ull2f_rn", "llvm.nvvm.ull2f.rp" => "__nvvm_ull2f_rp", "llvm.nvvm.ull2f.rz" => "__nvvm_ull2f_rz", + "llvm.nvvm.vote.all" => "__nvvm_vote_all", + "llvm.nvvm.vote.all.sync" => "__nvvm_vote_all_sync", + "llvm.nvvm.vote.any" => "__nvvm_vote_any", + "llvm.nvvm.vote.any.sync" => "__nvvm_vote_any_sync", + "llvm.nvvm.vote.ballot" => "__nvvm_vote_ballot", + "llvm.nvvm.vote.ballot.sync" => "__nvvm_vote_ballot_sync", + "llvm.nvvm.vote.uni" => "__nvvm_vote_uni", + "llvm.nvvm.vote.uni.sync" => "__nvvm_vote_uni_sync", // ppc "llvm.ppc.addex" => "__builtin_ppc_addex", "llvm.ppc.addf128.round.to.odd" => "__builtin_addf128_round_to_odd", @@ -2881,6 +3617,10 @@ match name { "llvm.ppc.altivec.mtvsrhm" => "__builtin_altivec_mtvsrhm", "llvm.ppc.altivec.mtvsrqm" => "__builtin_altivec_mtvsrqm", "llvm.ppc.altivec.mtvsrwm" => "__builtin_altivec_mtvsrwm", + "llvm.ppc.altivec.vabsdub" => "__builtin_altivec_vabsdub", + "llvm.ppc.altivec.vabsduh" => "__builtin_altivec_vabsduh", + "llvm.ppc.altivec.vabsduw" => "__builtin_altivec_vabsduw", + "llvm.ppc.altivec.vaddcuq" => "__builtin_altivec_vaddcuq", "llvm.ppc.altivec.vaddcuw" => "__builtin_altivec_vaddcuw", "llvm.ppc.altivec.vaddecuq" => "__builtin_altivec_vaddecuq", "llvm.ppc.altivec.vaddeuqm" => "__builtin_altivec_vaddeuqm", @@ -2963,6 +3703,12 @@ match name { "llvm.ppc.altivec.vctuxs" => "__builtin_altivec_vctuxs", "llvm.ppc.altivec.vctzdm" => "__builtin_altivec_vctzdm", "llvm.ppc.altivec.vctzlsbb" => "__builtin_altivec_vctzlsbb", + "llvm.ppc.altivec.vdivesd" => "__builtin_altivec_vdivesd", + "llvm.ppc.altivec.vdivesq" => "__builtin_altivec_vdivesq", + "llvm.ppc.altivec.vdivesw" => "__builtin_altivec_vdivesw", + "llvm.ppc.altivec.vdiveud" => "__builtin_altivec_vdiveud", + "llvm.ppc.altivec.vdiveuq" => "__builtin_altivec_vdiveuq", + "llvm.ppc.altivec.vdiveuw" => "__builtin_altivec_vdiveuw", "llvm.ppc.altivec.vexpandbm" => "__builtin_altivec_vexpandbm", "llvm.ppc.altivec.vexpanddm" => "__builtin_altivec_vexpanddm", "llvm.ppc.altivec.vexpandhm" => "__builtin_altivec_vexpandhm", @@ -3036,15 +3782,23 @@ match name { "llvm.ppc.altivec.vmsumuhm" => "__builtin_altivec_vmsumuhm", "llvm.ppc.altivec.vmsumuhs" => "__builtin_altivec_vmsumuhs", "llvm.ppc.altivec.vmulesb" => "__builtin_altivec_vmulesb", + "llvm.ppc.altivec.vmulesd" => "__builtin_altivec_vmulesd", "llvm.ppc.altivec.vmulesh" => "__builtin_altivec_vmulesh", "llvm.ppc.altivec.vmulesw" => "__builtin_altivec_vmulesw", "llvm.ppc.altivec.vmuleub" => "__builtin_altivec_vmuleub", + "llvm.ppc.altivec.vmuleud" => "__builtin_altivec_vmuleud", "llvm.ppc.altivec.vmuleuh" => "__builtin_altivec_vmuleuh", "llvm.ppc.altivec.vmuleuw" => "__builtin_altivec_vmuleuw", + "llvm.ppc.altivec.vmulhsd" => "__builtin_altivec_vmulhsd", + "llvm.ppc.altivec.vmulhsw" => "__builtin_altivec_vmulhsw", + "llvm.ppc.altivec.vmulhud" => "__builtin_altivec_vmulhud", + "llvm.ppc.altivec.vmulhuw" => "__builtin_altivec_vmulhuw", "llvm.ppc.altivec.vmulosb" => "__builtin_altivec_vmulosb", + "llvm.ppc.altivec.vmulosd" => "__builtin_altivec_vmulosd", "llvm.ppc.altivec.vmulosh" => "__builtin_altivec_vmulosh", "llvm.ppc.altivec.vmulosw" => "__builtin_altivec_vmulosw", "llvm.ppc.altivec.vmuloub" => "__builtin_altivec_vmuloub", + "llvm.ppc.altivec.vmuloud" => "__builtin_altivec_vmuloud", "llvm.ppc.altivec.vmulouh" => "__builtin_altivec_vmulouh", "llvm.ppc.altivec.vmulouw" => "__builtin_altivec_vmulouw", "llvm.ppc.altivec.vnmsubfp" => "__builtin_altivec_vnmsubfp", @@ -3071,8 +3825,14 @@ match name { "llvm.ppc.altivec.vrfiz" => "__builtin_altivec_vrfiz", "llvm.ppc.altivec.vrlb" => "__builtin_altivec_vrlb", "llvm.ppc.altivec.vrld" => "__builtin_altivec_vrld", + "llvm.ppc.altivec.vrldmi" => "__builtin_altivec_vrldmi", + "llvm.ppc.altivec.vrldnm" => "__builtin_altivec_vrldnm", "llvm.ppc.altivec.vrlh" => "__builtin_altivec_vrlh", + "llvm.ppc.altivec.vrlqmi" => "__builtin_altivec_vrlqmi", + "llvm.ppc.altivec.vrlqnm" => "__builtin_altivec_vrlqnm", "llvm.ppc.altivec.vrlw" => "__builtin_altivec_vrlw", + "llvm.ppc.altivec.vrlwmi" => "__builtin_altivec_vrlwmi", + "llvm.ppc.altivec.vrlwnm" => "__builtin_altivec_vrlwnm", "llvm.ppc.altivec.vrsqrtefp" => "__builtin_altivec_vrsqrtefp", "llvm.ppc.altivec.vsel" => "__builtin_altivec_vsel_4si", "llvm.ppc.altivec.vsl" => "__builtin_altivec_vsl", @@ -3080,6 +3840,7 @@ match name { "llvm.ppc.altivec.vsldbi" => "__builtin_altivec_vsldbi", "llvm.ppc.altivec.vslh" => "__builtin_altivec_vslh", "llvm.ppc.altivec.vslo" => "__builtin_altivec_vslo", + "llvm.ppc.altivec.vslv" => "__builtin_altivec_vslv", "llvm.ppc.altivec.vslw" => "__builtin_altivec_vslw", "llvm.ppc.altivec.vsr" => "__builtin_altivec_vsr", "llvm.ppc.altivec.vsrab" => "__builtin_altivec_vsrab", @@ -3089,6 +3850,7 @@ match name { "llvm.ppc.altivec.vsrdbi" => "__builtin_altivec_vsrdbi", "llvm.ppc.altivec.vsrh" => "__builtin_altivec_vsrh", "llvm.ppc.altivec.vsro" => "__builtin_altivec_vsro", + "llvm.ppc.altivec.vsrv" => "__builtin_altivec_vsrv", "llvm.ppc.altivec.vsrw" => "__builtin_altivec_vsrw", "llvm.ppc.altivec.vstribl" => "__builtin_altivec_vstribl", "llvm.ppc.altivec.vstribl.p" => "__builtin_altivec_vstribl_p", @@ -3098,6 +3860,7 @@ match name { "llvm.ppc.altivec.vstrihl.p" => "__builtin_altivec_vstrihl_p", "llvm.ppc.altivec.vstrihr" => "__builtin_altivec_vstrihr", "llvm.ppc.altivec.vstrihr.p" => "__builtin_altivec_vstrihr_p", + "llvm.ppc.altivec.vsubcuq" => "__builtin_altivec_vsubcuq", "llvm.ppc.altivec.vsubcuw" => "__builtin_altivec_vsubcuw", "llvm.ppc.altivec.vsubecuq" => "__builtin_altivec_vsubecuq", "llvm.ppc.altivec.vsubeuqm" => "__builtin_altivec_vsubeuqm", @@ -3165,6 +3928,8 @@ match name { "llvm.ppc.fmaf128.round.to.odd" => "__builtin_fmaf128_round_to_odd", "llvm.ppc.fmsub" => "__builtin_ppc_fmsub", "llvm.ppc.fmsubs" => "__builtin_ppc_fmsubs", + "llvm.ppc.fnabs" => "__builtin_ppc_fnabs", + "llvm.ppc.fnabss" => "__builtin_ppc_fnabss", "llvm.ppc.fnmadd" => "__builtin_ppc_fnmadd", "llvm.ppc.fnmadds" => "__builtin_ppc_fnmadds", "llvm.ppc.fre" => "__builtin_ppc_fre", @@ -3341,8 +4106,24 @@ match name { "llvm.ppc.vsx.xvcmpgtdp.p" => "__builtin_vsx_xvcmpgtdp_p", "llvm.ppc.vsx.xvcmpgtsp" => "__builtin_vsx_xvcmpgtsp", "llvm.ppc.vsx.xvcmpgtsp.p" => "__builtin_vsx_xvcmpgtsp_p", + "llvm.ppc.vsx.xvcvbf16spn" => "__builtin_vsx_xvcvbf16spn", + "llvm.ppc.vsx.xvcvdpsp" => "__builtin_vsx_xvcvdpsp", + "llvm.ppc.vsx.xvcvdpsxws" => "__builtin_vsx_xvcvdpsxws", + "llvm.ppc.vsx.xvcvdpuxws" => "__builtin_vsx_xvcvdpuxws", + "llvm.ppc.vsx.xvcvhpsp" => "__builtin_vsx_xvcvhpsp", + "llvm.ppc.vsx.xvcvspbf16" => "__builtin_vsx_xvcvspbf16", + "llvm.ppc.vsx.xvcvspdp" => "__builtin_vsx_xvcvspdp", + "llvm.ppc.vsx.xvcvsphp" => "__builtin_vsx_xvcvsphp", + "llvm.ppc.vsx.xvcvspsxds" => "__builtin_vsx_xvcvspsxds", + "llvm.ppc.vsx.xvcvspuxds" => "__builtin_vsx_xvcvspuxds", + "llvm.ppc.vsx.xvcvsxdsp" => "__builtin_vsx_xvcvsxdsp", + "llvm.ppc.vsx.xvcvsxwdp" => "__builtin_vsx_xvcvsxwdp", + "llvm.ppc.vsx.xvcvuxdsp" => "__builtin_vsx_xvcvuxdsp", + "llvm.ppc.vsx.xvcvuxwdp" => "__builtin_vsx_xvcvuxwdp", "llvm.ppc.vsx.xvdivdp" => "__builtin_vsx_xvdivdp", "llvm.ppc.vsx.xvdivsp" => "__builtin_vsx_xvdivsp", + "llvm.ppc.vsx.xviexpdp" => "__builtin_vsx_xviexpdp", + "llvm.ppc.vsx.xviexpsp" => "__builtin_vsx_xviexpsp", "llvm.ppc.vsx.xvmaxdp" => "__builtin_vsx_xvmaxdp", "llvm.ppc.vsx.xvmaxsp" => "__builtin_vsx_xvmaxsp", "llvm.ppc.vsx.xvmindp" => "__builtin_vsx_xvmindp", @@ -3351,10 +4132,28 @@ match name { "llvm.ppc.vsx.xvresp" => "__builtin_vsx_xvresp", "llvm.ppc.vsx.xvrsqrtedp" => "__builtin_vsx_xvrsqrtedp", "llvm.ppc.vsx.xvrsqrtesp" => "__builtin_vsx_xvrsqrtesp", + "llvm.ppc.vsx.xvtdivdp" => "__builtin_vsx_xvtdivdp", + "llvm.ppc.vsx.xvtdivsp" => "__builtin_vsx_xvtdivsp", + "llvm.ppc.vsx.xvtlsbb" => "__builtin_vsx_xvtlsbb", + "llvm.ppc.vsx.xvtsqrtdp" => "__builtin_vsx_xvtsqrtdp", + "llvm.ppc.vsx.xvtsqrtsp" => "__builtin_vsx_xvtsqrtsp", + "llvm.ppc.vsx.xvtstdcdp" => "__builtin_vsx_xvtstdcdp", + "llvm.ppc.vsx.xvtstdcsp" => "__builtin_vsx_xvtstdcsp", + "llvm.ppc.vsx.xvxexpdp" => "__builtin_vsx_xvxexpdp", + "llvm.ppc.vsx.xvxexpsp" => "__builtin_vsx_xvxexpsp", + "llvm.ppc.vsx.xvxsigdp" => "__builtin_vsx_xvxsigdp", + "llvm.ppc.vsx.xvxsigsp" => "__builtin_vsx_xvxsigsp", "llvm.ppc.vsx.xxblendvb" => "__builtin_vsx_xxblendvb", "llvm.ppc.vsx.xxblendvd" => "__builtin_vsx_xxblendvd", "llvm.ppc.vsx.xxblendvh" => "__builtin_vsx_xxblendvh", "llvm.ppc.vsx.xxblendvw" => "__builtin_vsx_xxblendvw", + "llvm.ppc.vsx.xxeval" => "__builtin_vsx_xxeval", + "llvm.ppc.vsx.xxextractuw" => "__builtin_vsx_xxextractuw", + "llvm.ppc.vsx.xxgenpcvbm" => "__builtin_vsx_xxgenpcvbm", + "llvm.ppc.vsx.xxgenpcvdm" => "__builtin_vsx_xxgenpcvdm", + "llvm.ppc.vsx.xxgenpcvhm" => "__builtin_vsx_xxgenpcvhm", + "llvm.ppc.vsx.xxgenpcvwm" => "__builtin_vsx_xxgenpcvwm", + "llvm.ppc.vsx.xxinsertw" => "__builtin_vsx_xxinsertw", "llvm.ppc.vsx.xxleqv" => "__builtin_vsx_xxleqv", "llvm.ppc.vsx.xxpermx" => "__builtin_vsx_xxpermx", // ptx @@ -3376,6 +4175,19 @@ match name { "llvm.ptx.read.pm3" => "__builtin_ptx_read_pm3", "llvm.ptx.read.smid" => "__builtin_ptx_read_smid", "llvm.ptx.read.warpid" => "__builtin_ptx_read_warpid", + // r600 + "llvm.r600.group.barrier" => "__builtin_r600_group_barrier", + "llvm.r600.implicitarg.ptr" => "__builtin_r600_implicitarg_ptr", + "llvm.r600.rat.store.typed" => "__builtin_r600_rat_store_typed", + "llvm.r600.read.global.size.x" => "__builtin_r600_read_global_size_x", + "llvm.r600.read.global.size.y" => "__builtin_r600_read_global_size_y", + "llvm.r600.read.global.size.z" => "__builtin_r600_read_global_size_z", + "llvm.r600.read.ngroups.x" => "__builtin_r600_read_ngroups_x", + "llvm.r600.read.ngroups.y" => "__builtin_r600_read_ngroups_y", + "llvm.r600.read.ngroups.z" => "__builtin_r600_read_ngroups_z", + "llvm.r600.read.tgid.x" => "__builtin_r600_read_tgid_x", + "llvm.r600.read.tgid.y" => "__builtin_r600_read_tgid_y", + "llvm.r600.read.tgid.z" => "__builtin_r600_read_tgid_z", // s390 "llvm.s390.efpc" => "__builtin_s390_efpc", "llvm.s390.etnd" => "__builtin_tx_nesting_depth", @@ -3383,29 +4195,1426 @@ match name { "llvm.s390.ppa.txassist" => "__builtin_tx_assist", "llvm.s390.sfpc" => "__builtin_s390_sfpc", "llvm.s390.tend" => "__builtin_tend", + "llvm.s390.vaccb" => "__builtin_s390_vaccb", + "llvm.s390.vacccq" => "__builtin_s390_vacccq", + "llvm.s390.vaccf" => "__builtin_s390_vaccf", + "llvm.s390.vaccg" => "__builtin_s390_vaccg", + "llvm.s390.vacch" => "__builtin_s390_vacch", + "llvm.s390.vaccq" => "__builtin_s390_vaccq", + "llvm.s390.vacq" => "__builtin_s390_vacq", + "llvm.s390.vaq" => "__builtin_s390_vaq", + "llvm.s390.vavgb" => "__builtin_s390_vavgb", + "llvm.s390.vavgf" => "__builtin_s390_vavgf", + "llvm.s390.vavgg" => "__builtin_s390_vavgg", + "llvm.s390.vavgh" => "__builtin_s390_vavgh", + "llvm.s390.vavglb" => "__builtin_s390_vavglb", + "llvm.s390.vavglf" => "__builtin_s390_vavglf", + "llvm.s390.vavglg" => "__builtin_s390_vavglg", + "llvm.s390.vavglh" => "__builtin_s390_vavglh", + "llvm.s390.vbperm" => "__builtin_s390_vbperm", "llvm.s390.vcfn" => "__builtin_s390_vcfn", + "llvm.s390.vcksm" => "__builtin_s390_vcksm", "llvm.s390.vclfnhs" => "__builtin_s390_vclfnhs", "llvm.s390.vclfnls" => "__builtin_s390_vclfnls", "llvm.s390.vcnf" => "__builtin_s390_vcnf", "llvm.s390.vcrnfs" => "__builtin_s390_vcrnfs", + "llvm.s390.verimb" => "__builtin_s390_verimb", + "llvm.s390.verimf" => "__builtin_s390_verimf", + "llvm.s390.verimg" => "__builtin_s390_verimg", + "llvm.s390.verimh" => "__builtin_s390_verimh", + "llvm.s390.verllb" => "__builtin_s390_verllb", + "llvm.s390.verllf" => "__builtin_s390_verllf", + "llvm.s390.verllg" => "__builtin_s390_verllg", + "llvm.s390.verllh" => "__builtin_s390_verllh", + "llvm.s390.verllvb" => "__builtin_s390_verllvb", + "llvm.s390.verllvf" => "__builtin_s390_verllvf", + "llvm.s390.verllvg" => "__builtin_s390_verllvg", + "llvm.s390.verllvh" => "__builtin_s390_verllvh", + "llvm.s390.vfaeb" => "__builtin_s390_vfaeb", + "llvm.s390.vfaef" => "__builtin_s390_vfaef", + "llvm.s390.vfaeh" => "__builtin_s390_vfaeh", + "llvm.s390.vfaezb" => "__builtin_s390_vfaezb", + "llvm.s390.vfaezf" => "__builtin_s390_vfaezf", + "llvm.s390.vfaezh" => "__builtin_s390_vfaezh", + "llvm.s390.vfeeb" => "__builtin_s390_vfeeb", + "llvm.s390.vfeef" => "__builtin_s390_vfeef", + "llvm.s390.vfeeh" => "__builtin_s390_vfeeh", + "llvm.s390.vfeezb" => "__builtin_s390_vfeezb", + "llvm.s390.vfeezf" => "__builtin_s390_vfeezf", + "llvm.s390.vfeezh" => "__builtin_s390_vfeezh", + "llvm.s390.vfeneb" => "__builtin_s390_vfeneb", + "llvm.s390.vfenef" => "__builtin_s390_vfenef", + "llvm.s390.vfeneh" => "__builtin_s390_vfeneh", + "llvm.s390.vfenezb" => "__builtin_s390_vfenezb", + "llvm.s390.vfenezf" => "__builtin_s390_vfenezf", + "llvm.s390.vfenezh" => "__builtin_s390_vfenezh", + "llvm.s390.vgfmab" => "__builtin_s390_vgfmab", + "llvm.s390.vgfmaf" => "__builtin_s390_vgfmaf", + "llvm.s390.vgfmag" => "__builtin_s390_vgfmag", + "llvm.s390.vgfmah" => "__builtin_s390_vgfmah", + "llvm.s390.vgfmb" => "__builtin_s390_vgfmb", + "llvm.s390.vgfmf" => "__builtin_s390_vgfmf", + "llvm.s390.vgfmg" => "__builtin_s390_vgfmg", + "llvm.s390.vgfmh" => "__builtin_s390_vgfmh", + "llvm.s390.vistrb" => "__builtin_s390_vistrb", + "llvm.s390.vistrf" => "__builtin_s390_vistrf", + "llvm.s390.vistrh" => "__builtin_s390_vistrh", "llvm.s390.vlbb" => "__builtin_s390_vlbb", "llvm.s390.vll" => "__builtin_s390_vll", "llvm.s390.vlrl" => "__builtin_s390_vlrl", + "llvm.s390.vmaeb" => "__builtin_s390_vmaeb", + "llvm.s390.vmaef" => "__builtin_s390_vmaef", + "llvm.s390.vmaeh" => "__builtin_s390_vmaeh", + "llvm.s390.vmahb" => "__builtin_s390_vmahb", + "llvm.s390.vmahf" => "__builtin_s390_vmahf", + "llvm.s390.vmahh" => "__builtin_s390_vmahh", + "llvm.s390.vmaleb" => "__builtin_s390_vmaleb", + "llvm.s390.vmalef" => "__builtin_s390_vmalef", + "llvm.s390.vmaleh" => "__builtin_s390_vmaleh", + "llvm.s390.vmalhb" => "__builtin_s390_vmalhb", + "llvm.s390.vmalhf" => "__builtin_s390_vmalhf", + "llvm.s390.vmalhh" => "__builtin_s390_vmalhh", + "llvm.s390.vmalob" => "__builtin_s390_vmalob", + "llvm.s390.vmalof" => "__builtin_s390_vmalof", + "llvm.s390.vmaloh" => "__builtin_s390_vmaloh", + "llvm.s390.vmaob" => "__builtin_s390_vmaob", + "llvm.s390.vmaof" => "__builtin_s390_vmaof", + "llvm.s390.vmaoh" => "__builtin_s390_vmaoh", + "llvm.s390.vmeb" => "__builtin_s390_vmeb", + "llvm.s390.vmef" => "__builtin_s390_vmef", + "llvm.s390.vmeh" => "__builtin_s390_vmeh", + "llvm.s390.vmhb" => "__builtin_s390_vmhb", + "llvm.s390.vmhf" => "__builtin_s390_vmhf", + "llvm.s390.vmhh" => "__builtin_s390_vmhh", + "llvm.s390.vmleb" => "__builtin_s390_vmleb", + "llvm.s390.vmlef" => "__builtin_s390_vmlef", + "llvm.s390.vmleh" => "__builtin_s390_vmleh", + "llvm.s390.vmlhb" => "__builtin_s390_vmlhb", + "llvm.s390.vmlhf" => "__builtin_s390_vmlhf", + "llvm.s390.vmlhh" => "__builtin_s390_vmlhh", + "llvm.s390.vmlob" => "__builtin_s390_vmlob", + "llvm.s390.vmlof" => "__builtin_s390_vmlof", + "llvm.s390.vmloh" => "__builtin_s390_vmloh", + "llvm.s390.vmob" => "__builtin_s390_vmob", + "llvm.s390.vmof" => "__builtin_s390_vmof", + "llvm.s390.vmoh" => "__builtin_s390_vmoh", "llvm.s390.vmslg" => "__builtin_s390_vmslg", "llvm.s390.vpdi" => "__builtin_s390_vpdi", "llvm.s390.vperm" => "__builtin_s390_vperm", + "llvm.s390.vpklsf" => "__builtin_s390_vpklsf", + "llvm.s390.vpklsg" => "__builtin_s390_vpklsg", + "llvm.s390.vpklsh" => "__builtin_s390_vpklsh", + "llvm.s390.vpksf" => "__builtin_s390_vpksf", + "llvm.s390.vpksg" => "__builtin_s390_vpksg", + "llvm.s390.vpksh" => "__builtin_s390_vpksh", + "llvm.s390.vsbcbiq" => "__builtin_s390_vsbcbiq", + "llvm.s390.vsbiq" => "__builtin_s390_vsbiq", + "llvm.s390.vscbib" => "__builtin_s390_vscbib", + "llvm.s390.vscbif" => "__builtin_s390_vscbif", + "llvm.s390.vscbig" => "__builtin_s390_vscbig", + "llvm.s390.vscbih" => "__builtin_s390_vscbih", + "llvm.s390.vscbiq" => "__builtin_s390_vscbiq", + "llvm.s390.vsl" => "__builtin_s390_vsl", + "llvm.s390.vslb" => "__builtin_s390_vslb", "llvm.s390.vsld" => "__builtin_s390_vsld", "llvm.s390.vsldb" => "__builtin_s390_vsldb", + "llvm.s390.vsq" => "__builtin_s390_vsq", + "llvm.s390.vsra" => "__builtin_s390_vsra", + "llvm.s390.vsrab" => "__builtin_s390_vsrab", "llvm.s390.vsrd" => "__builtin_s390_vsrd", + "llvm.s390.vsrl" => "__builtin_s390_vsrl", + "llvm.s390.vsrlb" => "__builtin_s390_vsrlb", "llvm.s390.vstl" => "__builtin_s390_vstl", + "llvm.s390.vstrcb" => "__builtin_s390_vstrcb", + "llvm.s390.vstrcf" => "__builtin_s390_vstrcf", + "llvm.s390.vstrch" => "__builtin_s390_vstrch", + "llvm.s390.vstrczb" => "__builtin_s390_vstrczb", + "llvm.s390.vstrczf" => "__builtin_s390_vstrczf", + "llvm.s390.vstrczh" => "__builtin_s390_vstrczh", "llvm.s390.vstrl" => "__builtin_s390_vstrl", + "llvm.s390.vsumb" => "__builtin_s390_vsumb", + "llvm.s390.vsumgf" => "__builtin_s390_vsumgf", + "llvm.s390.vsumgh" => "__builtin_s390_vsumgh", + "llvm.s390.vsumh" => "__builtin_s390_vsumh", + "llvm.s390.vsumqf" => "__builtin_s390_vsumqf", + "llvm.s390.vsumqg" => "__builtin_s390_vsumqg", + "llvm.s390.vtm" => "__builtin_s390_vtm", + "llvm.s390.vuphb" => "__builtin_s390_vuphb", + "llvm.s390.vuphf" => "__builtin_s390_vuphf", + "llvm.s390.vuphh" => "__builtin_s390_vuphh", + "llvm.s390.vuplb" => "__builtin_s390_vuplb", + "llvm.s390.vuplf" => "__builtin_s390_vuplf", + "llvm.s390.vuplhb" => "__builtin_s390_vuplhb", + "llvm.s390.vuplhf" => "__builtin_s390_vuplhf", + "llvm.s390.vuplhh" => "__builtin_s390_vuplhh", + "llvm.s390.vuplhw" => "__builtin_s390_vuplhw", + "llvm.s390.vupllb" => "__builtin_s390_vupllb", + "llvm.s390.vupllf" => "__builtin_s390_vupllf", + "llvm.s390.vupllh" => "__builtin_s390_vupllh", // ve + "llvm.ve.vl.andm.MMM" => "__builtin_ve_vl_andm_MMM", + "llvm.ve.vl.andm.mmm" => "__builtin_ve_vl_andm_mmm", + "llvm.ve.vl.eqvm.MMM" => "__builtin_ve_vl_eqvm_MMM", + "llvm.ve.vl.eqvm.mmm" => "__builtin_ve_vl_eqvm_mmm", "llvm.ve.vl.extract.vm512l" => "__builtin_ve_vl_extract_vm512l", "llvm.ve.vl.extract.vm512u" => "__builtin_ve_vl_extract_vm512u", + "llvm.ve.vl.fencec.s" => "__builtin_ve_vl_fencec_s", + "llvm.ve.vl.fencei" => "__builtin_ve_vl_fencei", + "llvm.ve.vl.fencem.s" => "__builtin_ve_vl_fencem_s", + "llvm.ve.vl.fidcr.sss" => "__builtin_ve_vl_fidcr_sss", "llvm.ve.vl.insert.vm512l" => "__builtin_ve_vl_insert_vm512l", "llvm.ve.vl.insert.vm512u" => "__builtin_ve_vl_insert_vm512u", + "llvm.ve.vl.lcr.sss" => "__builtin_ve_vl_lcr_sss", + "llvm.ve.vl.lsv.vvss" => "__builtin_ve_vl_lsv_vvss", + "llvm.ve.vl.lvm.MMss" => "__builtin_ve_vl_lvm_MMss", + "llvm.ve.vl.lvm.mmss" => "__builtin_ve_vl_lvm_mmss", + "llvm.ve.vl.lvsd.svs" => "__builtin_ve_vl_lvsd_svs", + "llvm.ve.vl.lvsl.svs" => "__builtin_ve_vl_lvsl_svs", + "llvm.ve.vl.lvss.svs" => "__builtin_ve_vl_lvss_svs", + "llvm.ve.vl.lzvm.sml" => "__builtin_ve_vl_lzvm_sml", + "llvm.ve.vl.negm.MM" => "__builtin_ve_vl_negm_MM", + "llvm.ve.vl.negm.mm" => "__builtin_ve_vl_negm_mm", + "llvm.ve.vl.nndm.MMM" => "__builtin_ve_vl_nndm_MMM", + "llvm.ve.vl.nndm.mmm" => "__builtin_ve_vl_nndm_mmm", + "llvm.ve.vl.orm.MMM" => "__builtin_ve_vl_orm_MMM", + "llvm.ve.vl.orm.mmm" => "__builtin_ve_vl_orm_mmm", "llvm.ve.vl.pack.f32a" => "__builtin_ve_vl_pack_f32a", "llvm.ve.vl.pack.f32p" => "__builtin_ve_vl_pack_f32p", + "llvm.ve.vl.pcvm.sml" => "__builtin_ve_vl_pcvm_sml", + "llvm.ve.vl.pfchv.ssl" => "__builtin_ve_vl_pfchv_ssl", + "llvm.ve.vl.pfchvnc.ssl" => "__builtin_ve_vl_pfchvnc_ssl", + "llvm.ve.vl.pvadds.vsvMvl" => "__builtin_ve_vl_pvadds_vsvMvl", + "llvm.ve.vl.pvadds.vsvl" => "__builtin_ve_vl_pvadds_vsvl", + "llvm.ve.vl.pvadds.vsvvl" => "__builtin_ve_vl_pvadds_vsvvl", + "llvm.ve.vl.pvadds.vvvMvl" => "__builtin_ve_vl_pvadds_vvvMvl", + "llvm.ve.vl.pvadds.vvvl" => "__builtin_ve_vl_pvadds_vvvl", + "llvm.ve.vl.pvadds.vvvvl" => "__builtin_ve_vl_pvadds_vvvvl", + "llvm.ve.vl.pvaddu.vsvMvl" => "__builtin_ve_vl_pvaddu_vsvMvl", + "llvm.ve.vl.pvaddu.vsvl" => "__builtin_ve_vl_pvaddu_vsvl", + "llvm.ve.vl.pvaddu.vsvvl" => "__builtin_ve_vl_pvaddu_vsvvl", + "llvm.ve.vl.pvaddu.vvvMvl" => "__builtin_ve_vl_pvaddu_vvvMvl", + "llvm.ve.vl.pvaddu.vvvl" => "__builtin_ve_vl_pvaddu_vvvl", + "llvm.ve.vl.pvaddu.vvvvl" => "__builtin_ve_vl_pvaddu_vvvvl", + "llvm.ve.vl.pvand.vsvMvl" => "__builtin_ve_vl_pvand_vsvMvl", + "llvm.ve.vl.pvand.vsvl" => "__builtin_ve_vl_pvand_vsvl", + "llvm.ve.vl.pvand.vsvvl" => "__builtin_ve_vl_pvand_vsvvl", + "llvm.ve.vl.pvand.vvvMvl" => "__builtin_ve_vl_pvand_vvvMvl", + "llvm.ve.vl.pvand.vvvl" => "__builtin_ve_vl_pvand_vvvl", + "llvm.ve.vl.pvand.vvvvl" => "__builtin_ve_vl_pvand_vvvvl", + "llvm.ve.vl.pvbrd.vsMvl" => "__builtin_ve_vl_pvbrd_vsMvl", + "llvm.ve.vl.pvbrd.vsl" => "__builtin_ve_vl_pvbrd_vsl", + "llvm.ve.vl.pvbrd.vsvl" => "__builtin_ve_vl_pvbrd_vsvl", + "llvm.ve.vl.pvbrv.vvMvl" => "__builtin_ve_vl_pvbrv_vvMvl", + "llvm.ve.vl.pvbrv.vvl" => "__builtin_ve_vl_pvbrv_vvl", + "llvm.ve.vl.pvbrv.vvvl" => "__builtin_ve_vl_pvbrv_vvvl", + "llvm.ve.vl.pvbrvlo.vvl" => "__builtin_ve_vl_pvbrvlo_vvl", + "llvm.ve.vl.pvbrvlo.vvmvl" => "__builtin_ve_vl_pvbrvlo_vvmvl", + "llvm.ve.vl.pvbrvlo.vvvl" => "__builtin_ve_vl_pvbrvlo_vvvl", + "llvm.ve.vl.pvbrvup.vvl" => "__builtin_ve_vl_pvbrvup_vvl", + "llvm.ve.vl.pvbrvup.vvmvl" => "__builtin_ve_vl_pvbrvup_vvmvl", + "llvm.ve.vl.pvbrvup.vvvl" => "__builtin_ve_vl_pvbrvup_vvvl", + "llvm.ve.vl.pvcmps.vsvMvl" => "__builtin_ve_vl_pvcmps_vsvMvl", + "llvm.ve.vl.pvcmps.vsvl" => "__builtin_ve_vl_pvcmps_vsvl", + "llvm.ve.vl.pvcmps.vsvvl" => "__builtin_ve_vl_pvcmps_vsvvl", + "llvm.ve.vl.pvcmps.vvvMvl" => "__builtin_ve_vl_pvcmps_vvvMvl", + "llvm.ve.vl.pvcmps.vvvl" => "__builtin_ve_vl_pvcmps_vvvl", + "llvm.ve.vl.pvcmps.vvvvl" => "__builtin_ve_vl_pvcmps_vvvvl", + "llvm.ve.vl.pvcmpu.vsvMvl" => "__builtin_ve_vl_pvcmpu_vsvMvl", + "llvm.ve.vl.pvcmpu.vsvl" => "__builtin_ve_vl_pvcmpu_vsvl", + "llvm.ve.vl.pvcmpu.vsvvl" => "__builtin_ve_vl_pvcmpu_vsvvl", + "llvm.ve.vl.pvcmpu.vvvMvl" => "__builtin_ve_vl_pvcmpu_vvvMvl", + "llvm.ve.vl.pvcmpu.vvvl" => "__builtin_ve_vl_pvcmpu_vvvl", + "llvm.ve.vl.pvcmpu.vvvvl" => "__builtin_ve_vl_pvcmpu_vvvvl", + "llvm.ve.vl.pvcvtsw.vvl" => "__builtin_ve_vl_pvcvtsw_vvl", + "llvm.ve.vl.pvcvtsw.vvvl" => "__builtin_ve_vl_pvcvtsw_vvvl", + "llvm.ve.vl.pvcvtws.vvMvl" => "__builtin_ve_vl_pvcvtws_vvMvl", + "llvm.ve.vl.pvcvtws.vvl" => "__builtin_ve_vl_pvcvtws_vvl", + "llvm.ve.vl.pvcvtws.vvvl" => "__builtin_ve_vl_pvcvtws_vvvl", + "llvm.ve.vl.pvcvtwsrz.vvMvl" => "__builtin_ve_vl_pvcvtwsrz_vvMvl", + "llvm.ve.vl.pvcvtwsrz.vvl" => "__builtin_ve_vl_pvcvtwsrz_vvl", + "llvm.ve.vl.pvcvtwsrz.vvvl" => "__builtin_ve_vl_pvcvtwsrz_vvvl", + "llvm.ve.vl.pveqv.vsvMvl" => "__builtin_ve_vl_pveqv_vsvMvl", + "llvm.ve.vl.pveqv.vsvl" => "__builtin_ve_vl_pveqv_vsvl", + "llvm.ve.vl.pveqv.vsvvl" => "__builtin_ve_vl_pveqv_vsvvl", + "llvm.ve.vl.pveqv.vvvMvl" => "__builtin_ve_vl_pveqv_vvvMvl", + "llvm.ve.vl.pveqv.vvvl" => "__builtin_ve_vl_pveqv_vvvl", + "llvm.ve.vl.pveqv.vvvvl" => "__builtin_ve_vl_pveqv_vvvvl", + "llvm.ve.vl.pvfadd.vsvMvl" => "__builtin_ve_vl_pvfadd_vsvMvl", + "llvm.ve.vl.pvfadd.vsvl" => "__builtin_ve_vl_pvfadd_vsvl", + "llvm.ve.vl.pvfadd.vsvvl" => "__builtin_ve_vl_pvfadd_vsvvl", + "llvm.ve.vl.pvfadd.vvvMvl" => "__builtin_ve_vl_pvfadd_vvvMvl", + "llvm.ve.vl.pvfadd.vvvl" => "__builtin_ve_vl_pvfadd_vvvl", + "llvm.ve.vl.pvfadd.vvvvl" => "__builtin_ve_vl_pvfadd_vvvvl", + "llvm.ve.vl.pvfcmp.vsvMvl" => "__builtin_ve_vl_pvfcmp_vsvMvl", + "llvm.ve.vl.pvfcmp.vsvl" => "__builtin_ve_vl_pvfcmp_vsvl", + "llvm.ve.vl.pvfcmp.vsvvl" => "__builtin_ve_vl_pvfcmp_vsvvl", + "llvm.ve.vl.pvfcmp.vvvMvl" => "__builtin_ve_vl_pvfcmp_vvvMvl", + "llvm.ve.vl.pvfcmp.vvvl" => "__builtin_ve_vl_pvfcmp_vvvl", + "llvm.ve.vl.pvfcmp.vvvvl" => "__builtin_ve_vl_pvfcmp_vvvvl", + "llvm.ve.vl.pvfmad.vsvvMvl" => "__builtin_ve_vl_pvfmad_vsvvMvl", + "llvm.ve.vl.pvfmad.vsvvl" => "__builtin_ve_vl_pvfmad_vsvvl", + "llvm.ve.vl.pvfmad.vsvvvl" => "__builtin_ve_vl_pvfmad_vsvvvl", + "llvm.ve.vl.pvfmad.vvsvMvl" => "__builtin_ve_vl_pvfmad_vvsvMvl", + "llvm.ve.vl.pvfmad.vvsvl" => "__builtin_ve_vl_pvfmad_vvsvl", + "llvm.ve.vl.pvfmad.vvsvvl" => "__builtin_ve_vl_pvfmad_vvsvvl", + "llvm.ve.vl.pvfmad.vvvvMvl" => "__builtin_ve_vl_pvfmad_vvvvMvl", + "llvm.ve.vl.pvfmad.vvvvl" => "__builtin_ve_vl_pvfmad_vvvvl", + "llvm.ve.vl.pvfmad.vvvvvl" => "__builtin_ve_vl_pvfmad_vvvvvl", + "llvm.ve.vl.pvfmax.vsvMvl" => "__builtin_ve_vl_pvfmax_vsvMvl", + "llvm.ve.vl.pvfmax.vsvl" => "__builtin_ve_vl_pvfmax_vsvl", + "llvm.ve.vl.pvfmax.vsvvl" => "__builtin_ve_vl_pvfmax_vsvvl", + "llvm.ve.vl.pvfmax.vvvMvl" => "__builtin_ve_vl_pvfmax_vvvMvl", + "llvm.ve.vl.pvfmax.vvvl" => "__builtin_ve_vl_pvfmax_vvvl", + "llvm.ve.vl.pvfmax.vvvvl" => "__builtin_ve_vl_pvfmax_vvvvl", + "llvm.ve.vl.pvfmin.vsvMvl" => "__builtin_ve_vl_pvfmin_vsvMvl", + "llvm.ve.vl.pvfmin.vsvl" => "__builtin_ve_vl_pvfmin_vsvl", + "llvm.ve.vl.pvfmin.vsvvl" => "__builtin_ve_vl_pvfmin_vsvvl", + "llvm.ve.vl.pvfmin.vvvMvl" => "__builtin_ve_vl_pvfmin_vvvMvl", + "llvm.ve.vl.pvfmin.vvvl" => "__builtin_ve_vl_pvfmin_vvvl", + "llvm.ve.vl.pvfmin.vvvvl" => "__builtin_ve_vl_pvfmin_vvvvl", + "llvm.ve.vl.pvfmkaf.Ml" => "__builtin_ve_vl_pvfmkaf_Ml", + "llvm.ve.vl.pvfmkat.Ml" => "__builtin_ve_vl_pvfmkat_Ml", + "llvm.ve.vl.pvfmkseq.MvMl" => "__builtin_ve_vl_pvfmkseq_MvMl", + "llvm.ve.vl.pvfmkseq.Mvl" => "__builtin_ve_vl_pvfmkseq_Mvl", + "llvm.ve.vl.pvfmkseqnan.MvMl" => "__builtin_ve_vl_pvfmkseqnan_MvMl", + "llvm.ve.vl.pvfmkseqnan.Mvl" => "__builtin_ve_vl_pvfmkseqnan_Mvl", + "llvm.ve.vl.pvfmksge.MvMl" => "__builtin_ve_vl_pvfmksge_MvMl", + "llvm.ve.vl.pvfmksge.Mvl" => "__builtin_ve_vl_pvfmksge_Mvl", + "llvm.ve.vl.pvfmksgenan.MvMl" => "__builtin_ve_vl_pvfmksgenan_MvMl", + "llvm.ve.vl.pvfmksgenan.Mvl" => "__builtin_ve_vl_pvfmksgenan_Mvl", + "llvm.ve.vl.pvfmksgt.MvMl" => "__builtin_ve_vl_pvfmksgt_MvMl", + "llvm.ve.vl.pvfmksgt.Mvl" => "__builtin_ve_vl_pvfmksgt_Mvl", + "llvm.ve.vl.pvfmksgtnan.MvMl" => "__builtin_ve_vl_pvfmksgtnan_MvMl", + "llvm.ve.vl.pvfmksgtnan.Mvl" => "__builtin_ve_vl_pvfmksgtnan_Mvl", + "llvm.ve.vl.pvfmksle.MvMl" => "__builtin_ve_vl_pvfmksle_MvMl", + "llvm.ve.vl.pvfmksle.Mvl" => "__builtin_ve_vl_pvfmksle_Mvl", + "llvm.ve.vl.pvfmkslenan.MvMl" => "__builtin_ve_vl_pvfmkslenan_MvMl", + "llvm.ve.vl.pvfmkslenan.Mvl" => "__builtin_ve_vl_pvfmkslenan_Mvl", + "llvm.ve.vl.pvfmksloeq.mvl" => "__builtin_ve_vl_pvfmksloeq_mvl", + "llvm.ve.vl.pvfmksloeq.mvml" => "__builtin_ve_vl_pvfmksloeq_mvml", + "llvm.ve.vl.pvfmksloeqnan.mvl" => "__builtin_ve_vl_pvfmksloeqnan_mvl", + "llvm.ve.vl.pvfmksloeqnan.mvml" => "__builtin_ve_vl_pvfmksloeqnan_mvml", + "llvm.ve.vl.pvfmksloge.mvl" => "__builtin_ve_vl_pvfmksloge_mvl", + "llvm.ve.vl.pvfmksloge.mvml" => "__builtin_ve_vl_pvfmksloge_mvml", + "llvm.ve.vl.pvfmkslogenan.mvl" => "__builtin_ve_vl_pvfmkslogenan_mvl", + "llvm.ve.vl.pvfmkslogenan.mvml" => "__builtin_ve_vl_pvfmkslogenan_mvml", + "llvm.ve.vl.pvfmkslogt.mvl" => "__builtin_ve_vl_pvfmkslogt_mvl", + "llvm.ve.vl.pvfmkslogt.mvml" => "__builtin_ve_vl_pvfmkslogt_mvml", + "llvm.ve.vl.pvfmkslogtnan.mvl" => "__builtin_ve_vl_pvfmkslogtnan_mvl", + "llvm.ve.vl.pvfmkslogtnan.mvml" => "__builtin_ve_vl_pvfmkslogtnan_mvml", + "llvm.ve.vl.pvfmkslole.mvl" => "__builtin_ve_vl_pvfmkslole_mvl", + "llvm.ve.vl.pvfmkslole.mvml" => "__builtin_ve_vl_pvfmkslole_mvml", + "llvm.ve.vl.pvfmkslolenan.mvl" => "__builtin_ve_vl_pvfmkslolenan_mvl", + "llvm.ve.vl.pvfmkslolenan.mvml" => "__builtin_ve_vl_pvfmkslolenan_mvml", + "llvm.ve.vl.pvfmkslolt.mvl" => "__builtin_ve_vl_pvfmkslolt_mvl", + "llvm.ve.vl.pvfmkslolt.mvml" => "__builtin_ve_vl_pvfmkslolt_mvml", + "llvm.ve.vl.pvfmksloltnan.mvl" => "__builtin_ve_vl_pvfmksloltnan_mvl", + "llvm.ve.vl.pvfmksloltnan.mvml" => "__builtin_ve_vl_pvfmksloltnan_mvml", + "llvm.ve.vl.pvfmkslonan.mvl" => "__builtin_ve_vl_pvfmkslonan_mvl", + "llvm.ve.vl.pvfmkslonan.mvml" => "__builtin_ve_vl_pvfmkslonan_mvml", + "llvm.ve.vl.pvfmkslone.mvl" => "__builtin_ve_vl_pvfmkslone_mvl", + "llvm.ve.vl.pvfmkslone.mvml" => "__builtin_ve_vl_pvfmkslone_mvml", + "llvm.ve.vl.pvfmkslonenan.mvl" => "__builtin_ve_vl_pvfmkslonenan_mvl", + "llvm.ve.vl.pvfmkslonenan.mvml" => "__builtin_ve_vl_pvfmkslonenan_mvml", + "llvm.ve.vl.pvfmkslonum.mvl" => "__builtin_ve_vl_pvfmkslonum_mvl", + "llvm.ve.vl.pvfmkslonum.mvml" => "__builtin_ve_vl_pvfmkslonum_mvml", + "llvm.ve.vl.pvfmkslt.MvMl" => "__builtin_ve_vl_pvfmkslt_MvMl", + "llvm.ve.vl.pvfmkslt.Mvl" => "__builtin_ve_vl_pvfmkslt_Mvl", + "llvm.ve.vl.pvfmksltnan.MvMl" => "__builtin_ve_vl_pvfmksltnan_MvMl", + "llvm.ve.vl.pvfmksltnan.Mvl" => "__builtin_ve_vl_pvfmksltnan_Mvl", + "llvm.ve.vl.pvfmksnan.MvMl" => "__builtin_ve_vl_pvfmksnan_MvMl", + "llvm.ve.vl.pvfmksnan.Mvl" => "__builtin_ve_vl_pvfmksnan_Mvl", + "llvm.ve.vl.pvfmksne.MvMl" => "__builtin_ve_vl_pvfmksne_MvMl", + "llvm.ve.vl.pvfmksne.Mvl" => "__builtin_ve_vl_pvfmksne_Mvl", + "llvm.ve.vl.pvfmksnenan.MvMl" => "__builtin_ve_vl_pvfmksnenan_MvMl", + "llvm.ve.vl.pvfmksnenan.Mvl" => "__builtin_ve_vl_pvfmksnenan_Mvl", + "llvm.ve.vl.pvfmksnum.MvMl" => "__builtin_ve_vl_pvfmksnum_MvMl", + "llvm.ve.vl.pvfmksnum.Mvl" => "__builtin_ve_vl_pvfmksnum_Mvl", + "llvm.ve.vl.pvfmksupeq.mvl" => "__builtin_ve_vl_pvfmksupeq_mvl", + "llvm.ve.vl.pvfmksupeq.mvml" => "__builtin_ve_vl_pvfmksupeq_mvml", + "llvm.ve.vl.pvfmksupeqnan.mvl" => "__builtin_ve_vl_pvfmksupeqnan_mvl", + "llvm.ve.vl.pvfmksupeqnan.mvml" => "__builtin_ve_vl_pvfmksupeqnan_mvml", + "llvm.ve.vl.pvfmksupge.mvl" => "__builtin_ve_vl_pvfmksupge_mvl", + "llvm.ve.vl.pvfmksupge.mvml" => "__builtin_ve_vl_pvfmksupge_mvml", + "llvm.ve.vl.pvfmksupgenan.mvl" => "__builtin_ve_vl_pvfmksupgenan_mvl", + "llvm.ve.vl.pvfmksupgenan.mvml" => "__builtin_ve_vl_pvfmksupgenan_mvml", + "llvm.ve.vl.pvfmksupgt.mvl" => "__builtin_ve_vl_pvfmksupgt_mvl", + "llvm.ve.vl.pvfmksupgt.mvml" => "__builtin_ve_vl_pvfmksupgt_mvml", + "llvm.ve.vl.pvfmksupgtnan.mvl" => "__builtin_ve_vl_pvfmksupgtnan_mvl", + "llvm.ve.vl.pvfmksupgtnan.mvml" => "__builtin_ve_vl_pvfmksupgtnan_mvml", + "llvm.ve.vl.pvfmksuple.mvl" => "__builtin_ve_vl_pvfmksuple_mvl", + "llvm.ve.vl.pvfmksuple.mvml" => "__builtin_ve_vl_pvfmksuple_mvml", + "llvm.ve.vl.pvfmksuplenan.mvl" => "__builtin_ve_vl_pvfmksuplenan_mvl", + "llvm.ve.vl.pvfmksuplenan.mvml" => "__builtin_ve_vl_pvfmksuplenan_mvml", + "llvm.ve.vl.pvfmksuplt.mvl" => "__builtin_ve_vl_pvfmksuplt_mvl", + "llvm.ve.vl.pvfmksuplt.mvml" => "__builtin_ve_vl_pvfmksuplt_mvml", + "llvm.ve.vl.pvfmksupltnan.mvl" => "__builtin_ve_vl_pvfmksupltnan_mvl", + "llvm.ve.vl.pvfmksupltnan.mvml" => "__builtin_ve_vl_pvfmksupltnan_mvml", + "llvm.ve.vl.pvfmksupnan.mvl" => "__builtin_ve_vl_pvfmksupnan_mvl", + "llvm.ve.vl.pvfmksupnan.mvml" => "__builtin_ve_vl_pvfmksupnan_mvml", + "llvm.ve.vl.pvfmksupne.mvl" => "__builtin_ve_vl_pvfmksupne_mvl", + "llvm.ve.vl.pvfmksupne.mvml" => "__builtin_ve_vl_pvfmksupne_mvml", + "llvm.ve.vl.pvfmksupnenan.mvl" => "__builtin_ve_vl_pvfmksupnenan_mvl", + "llvm.ve.vl.pvfmksupnenan.mvml" => "__builtin_ve_vl_pvfmksupnenan_mvml", + "llvm.ve.vl.pvfmksupnum.mvl" => "__builtin_ve_vl_pvfmksupnum_mvl", + "llvm.ve.vl.pvfmksupnum.mvml" => "__builtin_ve_vl_pvfmksupnum_mvml", + "llvm.ve.vl.pvfmkweq.MvMl" => "__builtin_ve_vl_pvfmkweq_MvMl", + "llvm.ve.vl.pvfmkweq.Mvl" => "__builtin_ve_vl_pvfmkweq_Mvl", + "llvm.ve.vl.pvfmkweqnan.MvMl" => "__builtin_ve_vl_pvfmkweqnan_MvMl", + "llvm.ve.vl.pvfmkweqnan.Mvl" => "__builtin_ve_vl_pvfmkweqnan_Mvl", + "llvm.ve.vl.pvfmkwge.MvMl" => "__builtin_ve_vl_pvfmkwge_MvMl", + "llvm.ve.vl.pvfmkwge.Mvl" => "__builtin_ve_vl_pvfmkwge_Mvl", + "llvm.ve.vl.pvfmkwgenan.MvMl" => "__builtin_ve_vl_pvfmkwgenan_MvMl", + "llvm.ve.vl.pvfmkwgenan.Mvl" => "__builtin_ve_vl_pvfmkwgenan_Mvl", + "llvm.ve.vl.pvfmkwgt.MvMl" => "__builtin_ve_vl_pvfmkwgt_MvMl", + "llvm.ve.vl.pvfmkwgt.Mvl" => "__builtin_ve_vl_pvfmkwgt_Mvl", + "llvm.ve.vl.pvfmkwgtnan.MvMl" => "__builtin_ve_vl_pvfmkwgtnan_MvMl", + "llvm.ve.vl.pvfmkwgtnan.Mvl" => "__builtin_ve_vl_pvfmkwgtnan_Mvl", + "llvm.ve.vl.pvfmkwle.MvMl" => "__builtin_ve_vl_pvfmkwle_MvMl", + "llvm.ve.vl.pvfmkwle.Mvl" => "__builtin_ve_vl_pvfmkwle_Mvl", + "llvm.ve.vl.pvfmkwlenan.MvMl" => "__builtin_ve_vl_pvfmkwlenan_MvMl", + "llvm.ve.vl.pvfmkwlenan.Mvl" => "__builtin_ve_vl_pvfmkwlenan_Mvl", + "llvm.ve.vl.pvfmkwloeq.mvl" => "__builtin_ve_vl_pvfmkwloeq_mvl", + "llvm.ve.vl.pvfmkwloeq.mvml" => "__builtin_ve_vl_pvfmkwloeq_mvml", + "llvm.ve.vl.pvfmkwloeqnan.mvl" => "__builtin_ve_vl_pvfmkwloeqnan_mvl", + "llvm.ve.vl.pvfmkwloeqnan.mvml" => "__builtin_ve_vl_pvfmkwloeqnan_mvml", + "llvm.ve.vl.pvfmkwloge.mvl" => "__builtin_ve_vl_pvfmkwloge_mvl", + "llvm.ve.vl.pvfmkwloge.mvml" => "__builtin_ve_vl_pvfmkwloge_mvml", + "llvm.ve.vl.pvfmkwlogenan.mvl" => "__builtin_ve_vl_pvfmkwlogenan_mvl", + "llvm.ve.vl.pvfmkwlogenan.mvml" => "__builtin_ve_vl_pvfmkwlogenan_mvml", + "llvm.ve.vl.pvfmkwlogt.mvl" => "__builtin_ve_vl_pvfmkwlogt_mvl", + "llvm.ve.vl.pvfmkwlogt.mvml" => "__builtin_ve_vl_pvfmkwlogt_mvml", + "llvm.ve.vl.pvfmkwlogtnan.mvl" => "__builtin_ve_vl_pvfmkwlogtnan_mvl", + "llvm.ve.vl.pvfmkwlogtnan.mvml" => "__builtin_ve_vl_pvfmkwlogtnan_mvml", + "llvm.ve.vl.pvfmkwlole.mvl" => "__builtin_ve_vl_pvfmkwlole_mvl", + "llvm.ve.vl.pvfmkwlole.mvml" => "__builtin_ve_vl_pvfmkwlole_mvml", + "llvm.ve.vl.pvfmkwlolenan.mvl" => "__builtin_ve_vl_pvfmkwlolenan_mvl", + "llvm.ve.vl.pvfmkwlolenan.mvml" => "__builtin_ve_vl_pvfmkwlolenan_mvml", + "llvm.ve.vl.pvfmkwlolt.mvl" => "__builtin_ve_vl_pvfmkwlolt_mvl", + "llvm.ve.vl.pvfmkwlolt.mvml" => "__builtin_ve_vl_pvfmkwlolt_mvml", + "llvm.ve.vl.pvfmkwloltnan.mvl" => "__builtin_ve_vl_pvfmkwloltnan_mvl", + "llvm.ve.vl.pvfmkwloltnan.mvml" => "__builtin_ve_vl_pvfmkwloltnan_mvml", + "llvm.ve.vl.pvfmkwlonan.mvl" => "__builtin_ve_vl_pvfmkwlonan_mvl", + "llvm.ve.vl.pvfmkwlonan.mvml" => "__builtin_ve_vl_pvfmkwlonan_mvml", + "llvm.ve.vl.pvfmkwlone.mvl" => "__builtin_ve_vl_pvfmkwlone_mvl", + "llvm.ve.vl.pvfmkwlone.mvml" => "__builtin_ve_vl_pvfmkwlone_mvml", + "llvm.ve.vl.pvfmkwlonenan.mvl" => "__builtin_ve_vl_pvfmkwlonenan_mvl", + "llvm.ve.vl.pvfmkwlonenan.mvml" => "__builtin_ve_vl_pvfmkwlonenan_mvml", + "llvm.ve.vl.pvfmkwlonum.mvl" => "__builtin_ve_vl_pvfmkwlonum_mvl", + "llvm.ve.vl.pvfmkwlonum.mvml" => "__builtin_ve_vl_pvfmkwlonum_mvml", + "llvm.ve.vl.pvfmkwlt.MvMl" => "__builtin_ve_vl_pvfmkwlt_MvMl", + "llvm.ve.vl.pvfmkwlt.Mvl" => "__builtin_ve_vl_pvfmkwlt_Mvl", + "llvm.ve.vl.pvfmkwltnan.MvMl" => "__builtin_ve_vl_pvfmkwltnan_MvMl", + "llvm.ve.vl.pvfmkwltnan.Mvl" => "__builtin_ve_vl_pvfmkwltnan_Mvl", + "llvm.ve.vl.pvfmkwnan.MvMl" => "__builtin_ve_vl_pvfmkwnan_MvMl", + "llvm.ve.vl.pvfmkwnan.Mvl" => "__builtin_ve_vl_pvfmkwnan_Mvl", + "llvm.ve.vl.pvfmkwne.MvMl" => "__builtin_ve_vl_pvfmkwne_MvMl", + "llvm.ve.vl.pvfmkwne.Mvl" => "__builtin_ve_vl_pvfmkwne_Mvl", + "llvm.ve.vl.pvfmkwnenan.MvMl" => "__builtin_ve_vl_pvfmkwnenan_MvMl", + "llvm.ve.vl.pvfmkwnenan.Mvl" => "__builtin_ve_vl_pvfmkwnenan_Mvl", + "llvm.ve.vl.pvfmkwnum.MvMl" => "__builtin_ve_vl_pvfmkwnum_MvMl", + "llvm.ve.vl.pvfmkwnum.Mvl" => "__builtin_ve_vl_pvfmkwnum_Mvl", + "llvm.ve.vl.pvfmkwupeq.mvl" => "__builtin_ve_vl_pvfmkwupeq_mvl", + "llvm.ve.vl.pvfmkwupeq.mvml" => "__builtin_ve_vl_pvfmkwupeq_mvml", + "llvm.ve.vl.pvfmkwupeqnan.mvl" => "__builtin_ve_vl_pvfmkwupeqnan_mvl", + "llvm.ve.vl.pvfmkwupeqnan.mvml" => "__builtin_ve_vl_pvfmkwupeqnan_mvml", + "llvm.ve.vl.pvfmkwupge.mvl" => "__builtin_ve_vl_pvfmkwupge_mvl", + "llvm.ve.vl.pvfmkwupge.mvml" => "__builtin_ve_vl_pvfmkwupge_mvml", + "llvm.ve.vl.pvfmkwupgenan.mvl" => "__builtin_ve_vl_pvfmkwupgenan_mvl", + "llvm.ve.vl.pvfmkwupgenan.mvml" => "__builtin_ve_vl_pvfmkwupgenan_mvml", + "llvm.ve.vl.pvfmkwupgt.mvl" => "__builtin_ve_vl_pvfmkwupgt_mvl", + "llvm.ve.vl.pvfmkwupgt.mvml" => "__builtin_ve_vl_pvfmkwupgt_mvml", + "llvm.ve.vl.pvfmkwupgtnan.mvl" => "__builtin_ve_vl_pvfmkwupgtnan_mvl", + "llvm.ve.vl.pvfmkwupgtnan.mvml" => "__builtin_ve_vl_pvfmkwupgtnan_mvml", + "llvm.ve.vl.pvfmkwuple.mvl" => "__builtin_ve_vl_pvfmkwuple_mvl", + "llvm.ve.vl.pvfmkwuple.mvml" => "__builtin_ve_vl_pvfmkwuple_mvml", + "llvm.ve.vl.pvfmkwuplenan.mvl" => "__builtin_ve_vl_pvfmkwuplenan_mvl", + "llvm.ve.vl.pvfmkwuplenan.mvml" => "__builtin_ve_vl_pvfmkwuplenan_mvml", + "llvm.ve.vl.pvfmkwuplt.mvl" => "__builtin_ve_vl_pvfmkwuplt_mvl", + "llvm.ve.vl.pvfmkwuplt.mvml" => "__builtin_ve_vl_pvfmkwuplt_mvml", + "llvm.ve.vl.pvfmkwupltnan.mvl" => "__builtin_ve_vl_pvfmkwupltnan_mvl", + "llvm.ve.vl.pvfmkwupltnan.mvml" => "__builtin_ve_vl_pvfmkwupltnan_mvml", + "llvm.ve.vl.pvfmkwupnan.mvl" => "__builtin_ve_vl_pvfmkwupnan_mvl", + "llvm.ve.vl.pvfmkwupnan.mvml" => "__builtin_ve_vl_pvfmkwupnan_mvml", + "llvm.ve.vl.pvfmkwupne.mvl" => "__builtin_ve_vl_pvfmkwupne_mvl", + "llvm.ve.vl.pvfmkwupne.mvml" => "__builtin_ve_vl_pvfmkwupne_mvml", + "llvm.ve.vl.pvfmkwupnenan.mvl" => "__builtin_ve_vl_pvfmkwupnenan_mvl", + "llvm.ve.vl.pvfmkwupnenan.mvml" => "__builtin_ve_vl_pvfmkwupnenan_mvml", + "llvm.ve.vl.pvfmkwupnum.mvl" => "__builtin_ve_vl_pvfmkwupnum_mvl", + "llvm.ve.vl.pvfmkwupnum.mvml" => "__builtin_ve_vl_pvfmkwupnum_mvml", + "llvm.ve.vl.pvfmsb.vsvvMvl" => "__builtin_ve_vl_pvfmsb_vsvvMvl", + "llvm.ve.vl.pvfmsb.vsvvl" => "__builtin_ve_vl_pvfmsb_vsvvl", + "llvm.ve.vl.pvfmsb.vsvvvl" => "__builtin_ve_vl_pvfmsb_vsvvvl", + "llvm.ve.vl.pvfmsb.vvsvMvl" => "__builtin_ve_vl_pvfmsb_vvsvMvl", + "llvm.ve.vl.pvfmsb.vvsvl" => "__builtin_ve_vl_pvfmsb_vvsvl", + "llvm.ve.vl.pvfmsb.vvsvvl" => "__builtin_ve_vl_pvfmsb_vvsvvl", + "llvm.ve.vl.pvfmsb.vvvvMvl" => "__builtin_ve_vl_pvfmsb_vvvvMvl", + "llvm.ve.vl.pvfmsb.vvvvl" => "__builtin_ve_vl_pvfmsb_vvvvl", + "llvm.ve.vl.pvfmsb.vvvvvl" => "__builtin_ve_vl_pvfmsb_vvvvvl", + "llvm.ve.vl.pvfmul.vsvMvl" => "__builtin_ve_vl_pvfmul_vsvMvl", + "llvm.ve.vl.pvfmul.vsvl" => "__builtin_ve_vl_pvfmul_vsvl", + "llvm.ve.vl.pvfmul.vsvvl" => "__builtin_ve_vl_pvfmul_vsvvl", + "llvm.ve.vl.pvfmul.vvvMvl" => "__builtin_ve_vl_pvfmul_vvvMvl", + "llvm.ve.vl.pvfmul.vvvl" => "__builtin_ve_vl_pvfmul_vvvl", + "llvm.ve.vl.pvfmul.vvvvl" => "__builtin_ve_vl_pvfmul_vvvvl", + "llvm.ve.vl.pvfnmad.vsvvMvl" => "__builtin_ve_vl_pvfnmad_vsvvMvl", + "llvm.ve.vl.pvfnmad.vsvvl" => "__builtin_ve_vl_pvfnmad_vsvvl", + "llvm.ve.vl.pvfnmad.vsvvvl" => "__builtin_ve_vl_pvfnmad_vsvvvl", + "llvm.ve.vl.pvfnmad.vvsvMvl" => "__builtin_ve_vl_pvfnmad_vvsvMvl", + "llvm.ve.vl.pvfnmad.vvsvl" => "__builtin_ve_vl_pvfnmad_vvsvl", + "llvm.ve.vl.pvfnmad.vvsvvl" => "__builtin_ve_vl_pvfnmad_vvsvvl", + "llvm.ve.vl.pvfnmad.vvvvMvl" => "__builtin_ve_vl_pvfnmad_vvvvMvl", + "llvm.ve.vl.pvfnmad.vvvvl" => "__builtin_ve_vl_pvfnmad_vvvvl", + "llvm.ve.vl.pvfnmad.vvvvvl" => "__builtin_ve_vl_pvfnmad_vvvvvl", + "llvm.ve.vl.pvfnmsb.vsvvMvl" => "__builtin_ve_vl_pvfnmsb_vsvvMvl", + "llvm.ve.vl.pvfnmsb.vsvvl" => "__builtin_ve_vl_pvfnmsb_vsvvl", + "llvm.ve.vl.pvfnmsb.vsvvvl" => "__builtin_ve_vl_pvfnmsb_vsvvvl", + "llvm.ve.vl.pvfnmsb.vvsvMvl" => "__builtin_ve_vl_pvfnmsb_vvsvMvl", + "llvm.ve.vl.pvfnmsb.vvsvl" => "__builtin_ve_vl_pvfnmsb_vvsvl", + "llvm.ve.vl.pvfnmsb.vvsvvl" => "__builtin_ve_vl_pvfnmsb_vvsvvl", + "llvm.ve.vl.pvfnmsb.vvvvMvl" => "__builtin_ve_vl_pvfnmsb_vvvvMvl", + "llvm.ve.vl.pvfnmsb.vvvvl" => "__builtin_ve_vl_pvfnmsb_vvvvl", + "llvm.ve.vl.pvfnmsb.vvvvvl" => "__builtin_ve_vl_pvfnmsb_vvvvvl", + "llvm.ve.vl.pvfsub.vsvMvl" => "__builtin_ve_vl_pvfsub_vsvMvl", + "llvm.ve.vl.pvfsub.vsvl" => "__builtin_ve_vl_pvfsub_vsvl", + "llvm.ve.vl.pvfsub.vsvvl" => "__builtin_ve_vl_pvfsub_vsvvl", + "llvm.ve.vl.pvfsub.vvvMvl" => "__builtin_ve_vl_pvfsub_vvvMvl", + "llvm.ve.vl.pvfsub.vvvl" => "__builtin_ve_vl_pvfsub_vvvl", + "llvm.ve.vl.pvfsub.vvvvl" => "__builtin_ve_vl_pvfsub_vvvvl", + "llvm.ve.vl.pvldz.vvMvl" => "__builtin_ve_vl_pvldz_vvMvl", + "llvm.ve.vl.pvldz.vvl" => "__builtin_ve_vl_pvldz_vvl", + "llvm.ve.vl.pvldz.vvvl" => "__builtin_ve_vl_pvldz_vvvl", + "llvm.ve.vl.pvldzlo.vvl" => "__builtin_ve_vl_pvldzlo_vvl", + "llvm.ve.vl.pvldzlo.vvmvl" => "__builtin_ve_vl_pvldzlo_vvmvl", + "llvm.ve.vl.pvldzlo.vvvl" => "__builtin_ve_vl_pvldzlo_vvvl", + "llvm.ve.vl.pvldzup.vvl" => "__builtin_ve_vl_pvldzup_vvl", + "llvm.ve.vl.pvldzup.vvmvl" => "__builtin_ve_vl_pvldzup_vvmvl", + "llvm.ve.vl.pvldzup.vvvl" => "__builtin_ve_vl_pvldzup_vvvl", + "llvm.ve.vl.pvmaxs.vsvMvl" => "__builtin_ve_vl_pvmaxs_vsvMvl", + "llvm.ve.vl.pvmaxs.vsvl" => "__builtin_ve_vl_pvmaxs_vsvl", + "llvm.ve.vl.pvmaxs.vsvvl" => "__builtin_ve_vl_pvmaxs_vsvvl", + "llvm.ve.vl.pvmaxs.vvvMvl" => "__builtin_ve_vl_pvmaxs_vvvMvl", + "llvm.ve.vl.pvmaxs.vvvl" => "__builtin_ve_vl_pvmaxs_vvvl", + "llvm.ve.vl.pvmaxs.vvvvl" => "__builtin_ve_vl_pvmaxs_vvvvl", + "llvm.ve.vl.pvmins.vsvMvl" => "__builtin_ve_vl_pvmins_vsvMvl", + "llvm.ve.vl.pvmins.vsvl" => "__builtin_ve_vl_pvmins_vsvl", + "llvm.ve.vl.pvmins.vsvvl" => "__builtin_ve_vl_pvmins_vsvvl", + "llvm.ve.vl.pvmins.vvvMvl" => "__builtin_ve_vl_pvmins_vvvMvl", + "llvm.ve.vl.pvmins.vvvl" => "__builtin_ve_vl_pvmins_vvvl", + "llvm.ve.vl.pvmins.vvvvl" => "__builtin_ve_vl_pvmins_vvvvl", + "llvm.ve.vl.pvor.vsvMvl" => "__builtin_ve_vl_pvor_vsvMvl", + "llvm.ve.vl.pvor.vsvl" => "__builtin_ve_vl_pvor_vsvl", + "llvm.ve.vl.pvor.vsvvl" => "__builtin_ve_vl_pvor_vsvvl", + "llvm.ve.vl.pvor.vvvMvl" => "__builtin_ve_vl_pvor_vvvMvl", + "llvm.ve.vl.pvor.vvvl" => "__builtin_ve_vl_pvor_vvvl", + "llvm.ve.vl.pvor.vvvvl" => "__builtin_ve_vl_pvor_vvvvl", + "llvm.ve.vl.pvpcnt.vvMvl" => "__builtin_ve_vl_pvpcnt_vvMvl", + "llvm.ve.vl.pvpcnt.vvl" => "__builtin_ve_vl_pvpcnt_vvl", + "llvm.ve.vl.pvpcnt.vvvl" => "__builtin_ve_vl_pvpcnt_vvvl", + "llvm.ve.vl.pvpcntlo.vvl" => "__builtin_ve_vl_pvpcntlo_vvl", + "llvm.ve.vl.pvpcntlo.vvmvl" => "__builtin_ve_vl_pvpcntlo_vvmvl", + "llvm.ve.vl.pvpcntlo.vvvl" => "__builtin_ve_vl_pvpcntlo_vvvl", + "llvm.ve.vl.pvpcntup.vvl" => "__builtin_ve_vl_pvpcntup_vvl", + "llvm.ve.vl.pvpcntup.vvmvl" => "__builtin_ve_vl_pvpcntup_vvmvl", + "llvm.ve.vl.pvpcntup.vvvl" => "__builtin_ve_vl_pvpcntup_vvvl", + "llvm.ve.vl.pvrcp.vvl" => "__builtin_ve_vl_pvrcp_vvl", + "llvm.ve.vl.pvrcp.vvvl" => "__builtin_ve_vl_pvrcp_vvvl", + "llvm.ve.vl.pvrsqrt.vvl" => "__builtin_ve_vl_pvrsqrt_vvl", + "llvm.ve.vl.pvrsqrt.vvvl" => "__builtin_ve_vl_pvrsqrt_vvvl", + "llvm.ve.vl.pvrsqrtnex.vvl" => "__builtin_ve_vl_pvrsqrtnex_vvl", + "llvm.ve.vl.pvrsqrtnex.vvvl" => "__builtin_ve_vl_pvrsqrtnex_vvvl", + "llvm.ve.vl.pvseq.vl" => "__builtin_ve_vl_pvseq_vl", + "llvm.ve.vl.pvseq.vvl" => "__builtin_ve_vl_pvseq_vvl", + "llvm.ve.vl.pvseqlo.vl" => "__builtin_ve_vl_pvseqlo_vl", + "llvm.ve.vl.pvseqlo.vvl" => "__builtin_ve_vl_pvseqlo_vvl", + "llvm.ve.vl.pvsequp.vl" => "__builtin_ve_vl_pvsequp_vl", + "llvm.ve.vl.pvsequp.vvl" => "__builtin_ve_vl_pvsequp_vvl", + "llvm.ve.vl.pvsla.vvsMvl" => "__builtin_ve_vl_pvsla_vvsMvl", + "llvm.ve.vl.pvsla.vvsl" => "__builtin_ve_vl_pvsla_vvsl", + "llvm.ve.vl.pvsla.vvsvl" => "__builtin_ve_vl_pvsla_vvsvl", + "llvm.ve.vl.pvsla.vvvMvl" => "__builtin_ve_vl_pvsla_vvvMvl", + "llvm.ve.vl.pvsla.vvvl" => "__builtin_ve_vl_pvsla_vvvl", + "llvm.ve.vl.pvsla.vvvvl" => "__builtin_ve_vl_pvsla_vvvvl", + "llvm.ve.vl.pvsll.vvsMvl" => "__builtin_ve_vl_pvsll_vvsMvl", + "llvm.ve.vl.pvsll.vvsl" => "__builtin_ve_vl_pvsll_vvsl", + "llvm.ve.vl.pvsll.vvsvl" => "__builtin_ve_vl_pvsll_vvsvl", + "llvm.ve.vl.pvsll.vvvMvl" => "__builtin_ve_vl_pvsll_vvvMvl", + "llvm.ve.vl.pvsll.vvvl" => "__builtin_ve_vl_pvsll_vvvl", + "llvm.ve.vl.pvsll.vvvvl" => "__builtin_ve_vl_pvsll_vvvvl", + "llvm.ve.vl.pvsra.vvsMvl" => "__builtin_ve_vl_pvsra_vvsMvl", + "llvm.ve.vl.pvsra.vvsl" => "__builtin_ve_vl_pvsra_vvsl", + "llvm.ve.vl.pvsra.vvsvl" => "__builtin_ve_vl_pvsra_vvsvl", + "llvm.ve.vl.pvsra.vvvMvl" => "__builtin_ve_vl_pvsra_vvvMvl", + "llvm.ve.vl.pvsra.vvvl" => "__builtin_ve_vl_pvsra_vvvl", + "llvm.ve.vl.pvsra.vvvvl" => "__builtin_ve_vl_pvsra_vvvvl", + "llvm.ve.vl.pvsrl.vvsMvl" => "__builtin_ve_vl_pvsrl_vvsMvl", + "llvm.ve.vl.pvsrl.vvsl" => "__builtin_ve_vl_pvsrl_vvsl", + "llvm.ve.vl.pvsrl.vvsvl" => "__builtin_ve_vl_pvsrl_vvsvl", + "llvm.ve.vl.pvsrl.vvvMvl" => "__builtin_ve_vl_pvsrl_vvvMvl", + "llvm.ve.vl.pvsrl.vvvl" => "__builtin_ve_vl_pvsrl_vvvl", + "llvm.ve.vl.pvsrl.vvvvl" => "__builtin_ve_vl_pvsrl_vvvvl", + "llvm.ve.vl.pvsubs.vsvMvl" => "__builtin_ve_vl_pvsubs_vsvMvl", + "llvm.ve.vl.pvsubs.vsvl" => "__builtin_ve_vl_pvsubs_vsvl", + "llvm.ve.vl.pvsubs.vsvvl" => "__builtin_ve_vl_pvsubs_vsvvl", + "llvm.ve.vl.pvsubs.vvvMvl" => "__builtin_ve_vl_pvsubs_vvvMvl", + "llvm.ve.vl.pvsubs.vvvl" => "__builtin_ve_vl_pvsubs_vvvl", + "llvm.ve.vl.pvsubs.vvvvl" => "__builtin_ve_vl_pvsubs_vvvvl", + "llvm.ve.vl.pvsubu.vsvMvl" => "__builtin_ve_vl_pvsubu_vsvMvl", + "llvm.ve.vl.pvsubu.vsvl" => "__builtin_ve_vl_pvsubu_vsvl", + "llvm.ve.vl.pvsubu.vsvvl" => "__builtin_ve_vl_pvsubu_vsvvl", + "llvm.ve.vl.pvsubu.vvvMvl" => "__builtin_ve_vl_pvsubu_vvvMvl", + "llvm.ve.vl.pvsubu.vvvl" => "__builtin_ve_vl_pvsubu_vvvl", + "llvm.ve.vl.pvsubu.vvvvl" => "__builtin_ve_vl_pvsubu_vvvvl", + "llvm.ve.vl.pvxor.vsvMvl" => "__builtin_ve_vl_pvxor_vsvMvl", + "llvm.ve.vl.pvxor.vsvl" => "__builtin_ve_vl_pvxor_vsvl", + "llvm.ve.vl.pvxor.vsvvl" => "__builtin_ve_vl_pvxor_vsvvl", + "llvm.ve.vl.pvxor.vvvMvl" => "__builtin_ve_vl_pvxor_vvvMvl", + "llvm.ve.vl.pvxor.vvvl" => "__builtin_ve_vl_pvxor_vvvl", + "llvm.ve.vl.pvxor.vvvvl" => "__builtin_ve_vl_pvxor_vvvvl", + "llvm.ve.vl.scr.sss" => "__builtin_ve_vl_scr_sss", + "llvm.ve.vl.svm.sMs" => "__builtin_ve_vl_svm_sMs", + "llvm.ve.vl.svm.sms" => "__builtin_ve_vl_svm_sms", + "llvm.ve.vl.svob" => "__builtin_ve_vl_svob", + "llvm.ve.vl.tovm.sml" => "__builtin_ve_vl_tovm_sml", + "llvm.ve.vl.tscr.ssss" => "__builtin_ve_vl_tscr_ssss", + "llvm.ve.vl.vaddsl.vsvl" => "__builtin_ve_vl_vaddsl_vsvl", + "llvm.ve.vl.vaddsl.vsvmvl" => "__builtin_ve_vl_vaddsl_vsvmvl", + "llvm.ve.vl.vaddsl.vsvvl" => "__builtin_ve_vl_vaddsl_vsvvl", + "llvm.ve.vl.vaddsl.vvvl" => "__builtin_ve_vl_vaddsl_vvvl", + "llvm.ve.vl.vaddsl.vvvmvl" => "__builtin_ve_vl_vaddsl_vvvmvl", + "llvm.ve.vl.vaddsl.vvvvl" => "__builtin_ve_vl_vaddsl_vvvvl", + "llvm.ve.vl.vaddswsx.vsvl" => "__builtin_ve_vl_vaddswsx_vsvl", + "llvm.ve.vl.vaddswsx.vsvmvl" => "__builtin_ve_vl_vaddswsx_vsvmvl", + "llvm.ve.vl.vaddswsx.vsvvl" => "__builtin_ve_vl_vaddswsx_vsvvl", + "llvm.ve.vl.vaddswsx.vvvl" => "__builtin_ve_vl_vaddswsx_vvvl", + "llvm.ve.vl.vaddswsx.vvvmvl" => "__builtin_ve_vl_vaddswsx_vvvmvl", + "llvm.ve.vl.vaddswsx.vvvvl" => "__builtin_ve_vl_vaddswsx_vvvvl", + "llvm.ve.vl.vaddswzx.vsvl" => "__builtin_ve_vl_vaddswzx_vsvl", + "llvm.ve.vl.vaddswzx.vsvmvl" => "__builtin_ve_vl_vaddswzx_vsvmvl", + "llvm.ve.vl.vaddswzx.vsvvl" => "__builtin_ve_vl_vaddswzx_vsvvl", + "llvm.ve.vl.vaddswzx.vvvl" => "__builtin_ve_vl_vaddswzx_vvvl", + "llvm.ve.vl.vaddswzx.vvvmvl" => "__builtin_ve_vl_vaddswzx_vvvmvl", + "llvm.ve.vl.vaddswzx.vvvvl" => "__builtin_ve_vl_vaddswzx_vvvvl", + "llvm.ve.vl.vaddul.vsvl" => "__builtin_ve_vl_vaddul_vsvl", + "llvm.ve.vl.vaddul.vsvmvl" => "__builtin_ve_vl_vaddul_vsvmvl", + "llvm.ve.vl.vaddul.vsvvl" => "__builtin_ve_vl_vaddul_vsvvl", + "llvm.ve.vl.vaddul.vvvl" => "__builtin_ve_vl_vaddul_vvvl", + "llvm.ve.vl.vaddul.vvvmvl" => "__builtin_ve_vl_vaddul_vvvmvl", + "llvm.ve.vl.vaddul.vvvvl" => "__builtin_ve_vl_vaddul_vvvvl", + "llvm.ve.vl.vadduw.vsvl" => "__builtin_ve_vl_vadduw_vsvl", + "llvm.ve.vl.vadduw.vsvmvl" => "__builtin_ve_vl_vadduw_vsvmvl", + "llvm.ve.vl.vadduw.vsvvl" => "__builtin_ve_vl_vadduw_vsvvl", + "llvm.ve.vl.vadduw.vvvl" => "__builtin_ve_vl_vadduw_vvvl", + "llvm.ve.vl.vadduw.vvvmvl" => "__builtin_ve_vl_vadduw_vvvmvl", + "llvm.ve.vl.vadduw.vvvvl" => "__builtin_ve_vl_vadduw_vvvvl", + "llvm.ve.vl.vand.vsvl" => "__builtin_ve_vl_vand_vsvl", + "llvm.ve.vl.vand.vsvmvl" => "__builtin_ve_vl_vand_vsvmvl", + "llvm.ve.vl.vand.vsvvl" => "__builtin_ve_vl_vand_vsvvl", + "llvm.ve.vl.vand.vvvl" => "__builtin_ve_vl_vand_vvvl", + "llvm.ve.vl.vand.vvvmvl" => "__builtin_ve_vl_vand_vvvmvl", + "llvm.ve.vl.vand.vvvvl" => "__builtin_ve_vl_vand_vvvvl", + "llvm.ve.vl.vbrdd.vsl" => "__builtin_ve_vl_vbrdd_vsl", + "llvm.ve.vl.vbrdd.vsmvl" => "__builtin_ve_vl_vbrdd_vsmvl", + "llvm.ve.vl.vbrdd.vsvl" => "__builtin_ve_vl_vbrdd_vsvl", + "llvm.ve.vl.vbrdl.vsl" => "__builtin_ve_vl_vbrdl_vsl", + "llvm.ve.vl.vbrdl.vsmvl" => "__builtin_ve_vl_vbrdl_vsmvl", + "llvm.ve.vl.vbrdl.vsvl" => "__builtin_ve_vl_vbrdl_vsvl", + "llvm.ve.vl.vbrds.vsl" => "__builtin_ve_vl_vbrds_vsl", + "llvm.ve.vl.vbrds.vsmvl" => "__builtin_ve_vl_vbrds_vsmvl", + "llvm.ve.vl.vbrds.vsvl" => "__builtin_ve_vl_vbrds_vsvl", + "llvm.ve.vl.vbrdw.vsl" => "__builtin_ve_vl_vbrdw_vsl", + "llvm.ve.vl.vbrdw.vsmvl" => "__builtin_ve_vl_vbrdw_vsmvl", + "llvm.ve.vl.vbrdw.vsvl" => "__builtin_ve_vl_vbrdw_vsvl", + "llvm.ve.vl.vbrv.vvl" => "__builtin_ve_vl_vbrv_vvl", + "llvm.ve.vl.vbrv.vvmvl" => "__builtin_ve_vl_vbrv_vvmvl", + "llvm.ve.vl.vbrv.vvvl" => "__builtin_ve_vl_vbrv_vvvl", + "llvm.ve.vl.vcmpsl.vsvl" => "__builtin_ve_vl_vcmpsl_vsvl", + "llvm.ve.vl.vcmpsl.vsvmvl" => "__builtin_ve_vl_vcmpsl_vsvmvl", + "llvm.ve.vl.vcmpsl.vsvvl" => "__builtin_ve_vl_vcmpsl_vsvvl", + "llvm.ve.vl.vcmpsl.vvvl" => "__builtin_ve_vl_vcmpsl_vvvl", + "llvm.ve.vl.vcmpsl.vvvmvl" => "__builtin_ve_vl_vcmpsl_vvvmvl", + "llvm.ve.vl.vcmpsl.vvvvl" => "__builtin_ve_vl_vcmpsl_vvvvl", + "llvm.ve.vl.vcmpswsx.vsvl" => "__builtin_ve_vl_vcmpswsx_vsvl", + "llvm.ve.vl.vcmpswsx.vsvmvl" => "__builtin_ve_vl_vcmpswsx_vsvmvl", + "llvm.ve.vl.vcmpswsx.vsvvl" => "__builtin_ve_vl_vcmpswsx_vsvvl", + "llvm.ve.vl.vcmpswsx.vvvl" => "__builtin_ve_vl_vcmpswsx_vvvl", + "llvm.ve.vl.vcmpswsx.vvvmvl" => "__builtin_ve_vl_vcmpswsx_vvvmvl", + "llvm.ve.vl.vcmpswsx.vvvvl" => "__builtin_ve_vl_vcmpswsx_vvvvl", + "llvm.ve.vl.vcmpswzx.vsvl" => "__builtin_ve_vl_vcmpswzx_vsvl", + "llvm.ve.vl.vcmpswzx.vsvmvl" => "__builtin_ve_vl_vcmpswzx_vsvmvl", + "llvm.ve.vl.vcmpswzx.vsvvl" => "__builtin_ve_vl_vcmpswzx_vsvvl", + "llvm.ve.vl.vcmpswzx.vvvl" => "__builtin_ve_vl_vcmpswzx_vvvl", + "llvm.ve.vl.vcmpswzx.vvvmvl" => "__builtin_ve_vl_vcmpswzx_vvvmvl", + "llvm.ve.vl.vcmpswzx.vvvvl" => "__builtin_ve_vl_vcmpswzx_vvvvl", + "llvm.ve.vl.vcmpul.vsvl" => "__builtin_ve_vl_vcmpul_vsvl", + "llvm.ve.vl.vcmpul.vsvmvl" => "__builtin_ve_vl_vcmpul_vsvmvl", + "llvm.ve.vl.vcmpul.vsvvl" => "__builtin_ve_vl_vcmpul_vsvvl", + "llvm.ve.vl.vcmpul.vvvl" => "__builtin_ve_vl_vcmpul_vvvl", + "llvm.ve.vl.vcmpul.vvvmvl" => "__builtin_ve_vl_vcmpul_vvvmvl", + "llvm.ve.vl.vcmpul.vvvvl" => "__builtin_ve_vl_vcmpul_vvvvl", + "llvm.ve.vl.vcmpuw.vsvl" => "__builtin_ve_vl_vcmpuw_vsvl", + "llvm.ve.vl.vcmpuw.vsvmvl" => "__builtin_ve_vl_vcmpuw_vsvmvl", + "llvm.ve.vl.vcmpuw.vsvvl" => "__builtin_ve_vl_vcmpuw_vsvvl", + "llvm.ve.vl.vcmpuw.vvvl" => "__builtin_ve_vl_vcmpuw_vvvl", + "llvm.ve.vl.vcmpuw.vvvmvl" => "__builtin_ve_vl_vcmpuw_vvvmvl", + "llvm.ve.vl.vcmpuw.vvvvl" => "__builtin_ve_vl_vcmpuw_vvvvl", + "llvm.ve.vl.vcp.vvmvl" => "__builtin_ve_vl_vcp_vvmvl", + "llvm.ve.vl.vcvtdl.vvl" => "__builtin_ve_vl_vcvtdl_vvl", + "llvm.ve.vl.vcvtdl.vvvl" => "__builtin_ve_vl_vcvtdl_vvvl", + "llvm.ve.vl.vcvtds.vvl" => "__builtin_ve_vl_vcvtds_vvl", + "llvm.ve.vl.vcvtds.vvvl" => "__builtin_ve_vl_vcvtds_vvvl", + "llvm.ve.vl.vcvtdw.vvl" => "__builtin_ve_vl_vcvtdw_vvl", + "llvm.ve.vl.vcvtdw.vvvl" => "__builtin_ve_vl_vcvtdw_vvvl", + "llvm.ve.vl.vcvtld.vvl" => "__builtin_ve_vl_vcvtld_vvl", + "llvm.ve.vl.vcvtld.vvmvl" => "__builtin_ve_vl_vcvtld_vvmvl", + "llvm.ve.vl.vcvtld.vvvl" => "__builtin_ve_vl_vcvtld_vvvl", + "llvm.ve.vl.vcvtldrz.vvl" => "__builtin_ve_vl_vcvtldrz_vvl", + "llvm.ve.vl.vcvtldrz.vvmvl" => "__builtin_ve_vl_vcvtldrz_vvmvl", + "llvm.ve.vl.vcvtldrz.vvvl" => "__builtin_ve_vl_vcvtldrz_vvvl", + "llvm.ve.vl.vcvtsd.vvl" => "__builtin_ve_vl_vcvtsd_vvl", + "llvm.ve.vl.vcvtsd.vvvl" => "__builtin_ve_vl_vcvtsd_vvvl", + "llvm.ve.vl.vcvtsw.vvl" => "__builtin_ve_vl_vcvtsw_vvl", + "llvm.ve.vl.vcvtsw.vvvl" => "__builtin_ve_vl_vcvtsw_vvvl", + "llvm.ve.vl.vcvtwdsx.vvl" => "__builtin_ve_vl_vcvtwdsx_vvl", + "llvm.ve.vl.vcvtwdsx.vvmvl" => "__builtin_ve_vl_vcvtwdsx_vvmvl", + "llvm.ve.vl.vcvtwdsx.vvvl" => "__builtin_ve_vl_vcvtwdsx_vvvl", + "llvm.ve.vl.vcvtwdsxrz.vvl" => "__builtin_ve_vl_vcvtwdsxrz_vvl", + "llvm.ve.vl.vcvtwdsxrz.vvmvl" => "__builtin_ve_vl_vcvtwdsxrz_vvmvl", + "llvm.ve.vl.vcvtwdsxrz.vvvl" => "__builtin_ve_vl_vcvtwdsxrz_vvvl", + "llvm.ve.vl.vcvtwdzx.vvl" => "__builtin_ve_vl_vcvtwdzx_vvl", + "llvm.ve.vl.vcvtwdzx.vvmvl" => "__builtin_ve_vl_vcvtwdzx_vvmvl", + "llvm.ve.vl.vcvtwdzx.vvvl" => "__builtin_ve_vl_vcvtwdzx_vvvl", + "llvm.ve.vl.vcvtwdzxrz.vvl" => "__builtin_ve_vl_vcvtwdzxrz_vvl", + "llvm.ve.vl.vcvtwdzxrz.vvmvl" => "__builtin_ve_vl_vcvtwdzxrz_vvmvl", + "llvm.ve.vl.vcvtwdzxrz.vvvl" => "__builtin_ve_vl_vcvtwdzxrz_vvvl", + "llvm.ve.vl.vcvtwssx.vvl" => "__builtin_ve_vl_vcvtwssx_vvl", + "llvm.ve.vl.vcvtwssx.vvmvl" => "__builtin_ve_vl_vcvtwssx_vvmvl", + "llvm.ve.vl.vcvtwssx.vvvl" => "__builtin_ve_vl_vcvtwssx_vvvl", + "llvm.ve.vl.vcvtwssxrz.vvl" => "__builtin_ve_vl_vcvtwssxrz_vvl", + "llvm.ve.vl.vcvtwssxrz.vvmvl" => "__builtin_ve_vl_vcvtwssxrz_vvmvl", + "llvm.ve.vl.vcvtwssxrz.vvvl" => "__builtin_ve_vl_vcvtwssxrz_vvvl", + "llvm.ve.vl.vcvtwszx.vvl" => "__builtin_ve_vl_vcvtwszx_vvl", + "llvm.ve.vl.vcvtwszx.vvmvl" => "__builtin_ve_vl_vcvtwszx_vvmvl", + "llvm.ve.vl.vcvtwszx.vvvl" => "__builtin_ve_vl_vcvtwszx_vvvl", + "llvm.ve.vl.vcvtwszxrz.vvl" => "__builtin_ve_vl_vcvtwszxrz_vvl", + "llvm.ve.vl.vcvtwszxrz.vvmvl" => "__builtin_ve_vl_vcvtwszxrz_vvmvl", + "llvm.ve.vl.vcvtwszxrz.vvvl" => "__builtin_ve_vl_vcvtwszxrz_vvvl", + "llvm.ve.vl.vdivsl.vsvl" => "__builtin_ve_vl_vdivsl_vsvl", + "llvm.ve.vl.vdivsl.vsvmvl" => "__builtin_ve_vl_vdivsl_vsvmvl", + "llvm.ve.vl.vdivsl.vsvvl" => "__builtin_ve_vl_vdivsl_vsvvl", + "llvm.ve.vl.vdivsl.vvsl" => "__builtin_ve_vl_vdivsl_vvsl", + "llvm.ve.vl.vdivsl.vvsmvl" => "__builtin_ve_vl_vdivsl_vvsmvl", + "llvm.ve.vl.vdivsl.vvsvl" => "__builtin_ve_vl_vdivsl_vvsvl", + "llvm.ve.vl.vdivsl.vvvl" => "__builtin_ve_vl_vdivsl_vvvl", + "llvm.ve.vl.vdivsl.vvvmvl" => "__builtin_ve_vl_vdivsl_vvvmvl", + "llvm.ve.vl.vdivsl.vvvvl" => "__builtin_ve_vl_vdivsl_vvvvl", + "llvm.ve.vl.vdivswsx.vsvl" => "__builtin_ve_vl_vdivswsx_vsvl", + "llvm.ve.vl.vdivswsx.vsvmvl" => "__builtin_ve_vl_vdivswsx_vsvmvl", + "llvm.ve.vl.vdivswsx.vsvvl" => "__builtin_ve_vl_vdivswsx_vsvvl", + "llvm.ve.vl.vdivswsx.vvsl" => "__builtin_ve_vl_vdivswsx_vvsl", + "llvm.ve.vl.vdivswsx.vvsmvl" => "__builtin_ve_vl_vdivswsx_vvsmvl", + "llvm.ve.vl.vdivswsx.vvsvl" => "__builtin_ve_vl_vdivswsx_vvsvl", + "llvm.ve.vl.vdivswsx.vvvl" => "__builtin_ve_vl_vdivswsx_vvvl", + "llvm.ve.vl.vdivswsx.vvvmvl" => "__builtin_ve_vl_vdivswsx_vvvmvl", + "llvm.ve.vl.vdivswsx.vvvvl" => "__builtin_ve_vl_vdivswsx_vvvvl", + "llvm.ve.vl.vdivswzx.vsvl" => "__builtin_ve_vl_vdivswzx_vsvl", + "llvm.ve.vl.vdivswzx.vsvmvl" => "__builtin_ve_vl_vdivswzx_vsvmvl", + "llvm.ve.vl.vdivswzx.vsvvl" => "__builtin_ve_vl_vdivswzx_vsvvl", + "llvm.ve.vl.vdivswzx.vvsl" => "__builtin_ve_vl_vdivswzx_vvsl", + "llvm.ve.vl.vdivswzx.vvsmvl" => "__builtin_ve_vl_vdivswzx_vvsmvl", + "llvm.ve.vl.vdivswzx.vvsvl" => "__builtin_ve_vl_vdivswzx_vvsvl", + "llvm.ve.vl.vdivswzx.vvvl" => "__builtin_ve_vl_vdivswzx_vvvl", + "llvm.ve.vl.vdivswzx.vvvmvl" => "__builtin_ve_vl_vdivswzx_vvvmvl", + "llvm.ve.vl.vdivswzx.vvvvl" => "__builtin_ve_vl_vdivswzx_vvvvl", + "llvm.ve.vl.vdivul.vsvl" => "__builtin_ve_vl_vdivul_vsvl", + "llvm.ve.vl.vdivul.vsvmvl" => "__builtin_ve_vl_vdivul_vsvmvl", + "llvm.ve.vl.vdivul.vsvvl" => "__builtin_ve_vl_vdivul_vsvvl", + "llvm.ve.vl.vdivul.vvsl" => "__builtin_ve_vl_vdivul_vvsl", + "llvm.ve.vl.vdivul.vvsmvl" => "__builtin_ve_vl_vdivul_vvsmvl", + "llvm.ve.vl.vdivul.vvsvl" => "__builtin_ve_vl_vdivul_vvsvl", + "llvm.ve.vl.vdivul.vvvl" => "__builtin_ve_vl_vdivul_vvvl", + "llvm.ve.vl.vdivul.vvvmvl" => "__builtin_ve_vl_vdivul_vvvmvl", + "llvm.ve.vl.vdivul.vvvvl" => "__builtin_ve_vl_vdivul_vvvvl", + "llvm.ve.vl.vdivuw.vsvl" => "__builtin_ve_vl_vdivuw_vsvl", + "llvm.ve.vl.vdivuw.vsvmvl" => "__builtin_ve_vl_vdivuw_vsvmvl", + "llvm.ve.vl.vdivuw.vsvvl" => "__builtin_ve_vl_vdivuw_vsvvl", + "llvm.ve.vl.vdivuw.vvsl" => "__builtin_ve_vl_vdivuw_vvsl", + "llvm.ve.vl.vdivuw.vvsmvl" => "__builtin_ve_vl_vdivuw_vvsmvl", + "llvm.ve.vl.vdivuw.vvsvl" => "__builtin_ve_vl_vdivuw_vvsvl", + "llvm.ve.vl.vdivuw.vvvl" => "__builtin_ve_vl_vdivuw_vvvl", + "llvm.ve.vl.vdivuw.vvvmvl" => "__builtin_ve_vl_vdivuw_vvvmvl", + "llvm.ve.vl.vdivuw.vvvvl" => "__builtin_ve_vl_vdivuw_vvvvl", + "llvm.ve.vl.veqv.vsvl" => "__builtin_ve_vl_veqv_vsvl", + "llvm.ve.vl.veqv.vsvmvl" => "__builtin_ve_vl_veqv_vsvmvl", + "llvm.ve.vl.veqv.vsvvl" => "__builtin_ve_vl_veqv_vsvvl", + "llvm.ve.vl.veqv.vvvl" => "__builtin_ve_vl_veqv_vvvl", + "llvm.ve.vl.veqv.vvvmvl" => "__builtin_ve_vl_veqv_vvvmvl", + "llvm.ve.vl.veqv.vvvvl" => "__builtin_ve_vl_veqv_vvvvl", + "llvm.ve.vl.vex.vvmvl" => "__builtin_ve_vl_vex_vvmvl", + "llvm.ve.vl.vfaddd.vsvl" => "__builtin_ve_vl_vfaddd_vsvl", + "llvm.ve.vl.vfaddd.vsvmvl" => "__builtin_ve_vl_vfaddd_vsvmvl", + "llvm.ve.vl.vfaddd.vsvvl" => "__builtin_ve_vl_vfaddd_vsvvl", + "llvm.ve.vl.vfaddd.vvvl" => "__builtin_ve_vl_vfaddd_vvvl", + "llvm.ve.vl.vfaddd.vvvmvl" => "__builtin_ve_vl_vfaddd_vvvmvl", + "llvm.ve.vl.vfaddd.vvvvl" => "__builtin_ve_vl_vfaddd_vvvvl", + "llvm.ve.vl.vfadds.vsvl" => "__builtin_ve_vl_vfadds_vsvl", + "llvm.ve.vl.vfadds.vsvmvl" => "__builtin_ve_vl_vfadds_vsvmvl", + "llvm.ve.vl.vfadds.vsvvl" => "__builtin_ve_vl_vfadds_vsvvl", + "llvm.ve.vl.vfadds.vvvl" => "__builtin_ve_vl_vfadds_vvvl", + "llvm.ve.vl.vfadds.vvvmvl" => "__builtin_ve_vl_vfadds_vvvmvl", + "llvm.ve.vl.vfadds.vvvvl" => "__builtin_ve_vl_vfadds_vvvvl", + "llvm.ve.vl.vfcmpd.vsvl" => "__builtin_ve_vl_vfcmpd_vsvl", + "llvm.ve.vl.vfcmpd.vsvmvl" => "__builtin_ve_vl_vfcmpd_vsvmvl", + "llvm.ve.vl.vfcmpd.vsvvl" => "__builtin_ve_vl_vfcmpd_vsvvl", + "llvm.ve.vl.vfcmpd.vvvl" => "__builtin_ve_vl_vfcmpd_vvvl", + "llvm.ve.vl.vfcmpd.vvvmvl" => "__builtin_ve_vl_vfcmpd_vvvmvl", + "llvm.ve.vl.vfcmpd.vvvvl" => "__builtin_ve_vl_vfcmpd_vvvvl", + "llvm.ve.vl.vfcmps.vsvl" => "__builtin_ve_vl_vfcmps_vsvl", + "llvm.ve.vl.vfcmps.vsvmvl" => "__builtin_ve_vl_vfcmps_vsvmvl", + "llvm.ve.vl.vfcmps.vsvvl" => "__builtin_ve_vl_vfcmps_vsvvl", + "llvm.ve.vl.vfcmps.vvvl" => "__builtin_ve_vl_vfcmps_vvvl", + "llvm.ve.vl.vfcmps.vvvmvl" => "__builtin_ve_vl_vfcmps_vvvmvl", + "llvm.ve.vl.vfcmps.vvvvl" => "__builtin_ve_vl_vfcmps_vvvvl", + "llvm.ve.vl.vfdivd.vsvl" => "__builtin_ve_vl_vfdivd_vsvl", + "llvm.ve.vl.vfdivd.vsvmvl" => "__builtin_ve_vl_vfdivd_vsvmvl", + "llvm.ve.vl.vfdivd.vsvvl" => "__builtin_ve_vl_vfdivd_vsvvl", + "llvm.ve.vl.vfdivd.vvvl" => "__builtin_ve_vl_vfdivd_vvvl", + "llvm.ve.vl.vfdivd.vvvmvl" => "__builtin_ve_vl_vfdivd_vvvmvl", + "llvm.ve.vl.vfdivd.vvvvl" => "__builtin_ve_vl_vfdivd_vvvvl", + "llvm.ve.vl.vfdivs.vsvl" => "__builtin_ve_vl_vfdivs_vsvl", + "llvm.ve.vl.vfdivs.vsvmvl" => "__builtin_ve_vl_vfdivs_vsvmvl", + "llvm.ve.vl.vfdivs.vsvvl" => "__builtin_ve_vl_vfdivs_vsvvl", + "llvm.ve.vl.vfdivs.vvvl" => "__builtin_ve_vl_vfdivs_vvvl", + "llvm.ve.vl.vfdivs.vvvmvl" => "__builtin_ve_vl_vfdivs_vvvmvl", + "llvm.ve.vl.vfdivs.vvvvl" => "__builtin_ve_vl_vfdivs_vvvvl", + "llvm.ve.vl.vfmadd.vsvvl" => "__builtin_ve_vl_vfmadd_vsvvl", + "llvm.ve.vl.vfmadd.vsvvmvl" => "__builtin_ve_vl_vfmadd_vsvvmvl", + "llvm.ve.vl.vfmadd.vsvvvl" => "__builtin_ve_vl_vfmadd_vsvvvl", + "llvm.ve.vl.vfmadd.vvsvl" => "__builtin_ve_vl_vfmadd_vvsvl", + "llvm.ve.vl.vfmadd.vvsvmvl" => "__builtin_ve_vl_vfmadd_vvsvmvl", + "llvm.ve.vl.vfmadd.vvsvvl" => "__builtin_ve_vl_vfmadd_vvsvvl", + "llvm.ve.vl.vfmadd.vvvvl" => "__builtin_ve_vl_vfmadd_vvvvl", + "llvm.ve.vl.vfmadd.vvvvmvl" => "__builtin_ve_vl_vfmadd_vvvvmvl", + "llvm.ve.vl.vfmadd.vvvvvl" => "__builtin_ve_vl_vfmadd_vvvvvl", + "llvm.ve.vl.vfmads.vsvvl" => "__builtin_ve_vl_vfmads_vsvvl", + "llvm.ve.vl.vfmads.vsvvmvl" => "__builtin_ve_vl_vfmads_vsvvmvl", + "llvm.ve.vl.vfmads.vsvvvl" => "__builtin_ve_vl_vfmads_vsvvvl", + "llvm.ve.vl.vfmads.vvsvl" => "__builtin_ve_vl_vfmads_vvsvl", + "llvm.ve.vl.vfmads.vvsvmvl" => "__builtin_ve_vl_vfmads_vvsvmvl", + "llvm.ve.vl.vfmads.vvsvvl" => "__builtin_ve_vl_vfmads_vvsvvl", + "llvm.ve.vl.vfmads.vvvvl" => "__builtin_ve_vl_vfmads_vvvvl", + "llvm.ve.vl.vfmads.vvvvmvl" => "__builtin_ve_vl_vfmads_vvvvmvl", + "llvm.ve.vl.vfmads.vvvvvl" => "__builtin_ve_vl_vfmads_vvvvvl", + "llvm.ve.vl.vfmaxd.vsvl" => "__builtin_ve_vl_vfmaxd_vsvl", + "llvm.ve.vl.vfmaxd.vsvmvl" => "__builtin_ve_vl_vfmaxd_vsvmvl", + "llvm.ve.vl.vfmaxd.vsvvl" => "__builtin_ve_vl_vfmaxd_vsvvl", + "llvm.ve.vl.vfmaxd.vvvl" => "__builtin_ve_vl_vfmaxd_vvvl", + "llvm.ve.vl.vfmaxd.vvvmvl" => "__builtin_ve_vl_vfmaxd_vvvmvl", + "llvm.ve.vl.vfmaxd.vvvvl" => "__builtin_ve_vl_vfmaxd_vvvvl", + "llvm.ve.vl.vfmaxs.vsvl" => "__builtin_ve_vl_vfmaxs_vsvl", + "llvm.ve.vl.vfmaxs.vsvmvl" => "__builtin_ve_vl_vfmaxs_vsvmvl", + "llvm.ve.vl.vfmaxs.vsvvl" => "__builtin_ve_vl_vfmaxs_vsvvl", + "llvm.ve.vl.vfmaxs.vvvl" => "__builtin_ve_vl_vfmaxs_vvvl", + "llvm.ve.vl.vfmaxs.vvvmvl" => "__builtin_ve_vl_vfmaxs_vvvmvl", + "llvm.ve.vl.vfmaxs.vvvvl" => "__builtin_ve_vl_vfmaxs_vvvvl", + "llvm.ve.vl.vfmind.vsvl" => "__builtin_ve_vl_vfmind_vsvl", + "llvm.ve.vl.vfmind.vsvmvl" => "__builtin_ve_vl_vfmind_vsvmvl", + "llvm.ve.vl.vfmind.vsvvl" => "__builtin_ve_vl_vfmind_vsvvl", + "llvm.ve.vl.vfmind.vvvl" => "__builtin_ve_vl_vfmind_vvvl", + "llvm.ve.vl.vfmind.vvvmvl" => "__builtin_ve_vl_vfmind_vvvmvl", + "llvm.ve.vl.vfmind.vvvvl" => "__builtin_ve_vl_vfmind_vvvvl", + "llvm.ve.vl.vfmins.vsvl" => "__builtin_ve_vl_vfmins_vsvl", + "llvm.ve.vl.vfmins.vsvmvl" => "__builtin_ve_vl_vfmins_vsvmvl", + "llvm.ve.vl.vfmins.vsvvl" => "__builtin_ve_vl_vfmins_vsvvl", + "llvm.ve.vl.vfmins.vvvl" => "__builtin_ve_vl_vfmins_vvvl", + "llvm.ve.vl.vfmins.vvvmvl" => "__builtin_ve_vl_vfmins_vvvmvl", + "llvm.ve.vl.vfmins.vvvvl" => "__builtin_ve_vl_vfmins_vvvvl", + "llvm.ve.vl.vfmkdeq.mvl" => "__builtin_ve_vl_vfmkdeq_mvl", + "llvm.ve.vl.vfmkdeq.mvml" => "__builtin_ve_vl_vfmkdeq_mvml", + "llvm.ve.vl.vfmkdeqnan.mvl" => "__builtin_ve_vl_vfmkdeqnan_mvl", + "llvm.ve.vl.vfmkdeqnan.mvml" => "__builtin_ve_vl_vfmkdeqnan_mvml", + "llvm.ve.vl.vfmkdge.mvl" => "__builtin_ve_vl_vfmkdge_mvl", + "llvm.ve.vl.vfmkdge.mvml" => "__builtin_ve_vl_vfmkdge_mvml", + "llvm.ve.vl.vfmkdgenan.mvl" => "__builtin_ve_vl_vfmkdgenan_mvl", + "llvm.ve.vl.vfmkdgenan.mvml" => "__builtin_ve_vl_vfmkdgenan_mvml", + "llvm.ve.vl.vfmkdgt.mvl" => "__builtin_ve_vl_vfmkdgt_mvl", + "llvm.ve.vl.vfmkdgt.mvml" => "__builtin_ve_vl_vfmkdgt_mvml", + "llvm.ve.vl.vfmkdgtnan.mvl" => "__builtin_ve_vl_vfmkdgtnan_mvl", + "llvm.ve.vl.vfmkdgtnan.mvml" => "__builtin_ve_vl_vfmkdgtnan_mvml", + "llvm.ve.vl.vfmkdle.mvl" => "__builtin_ve_vl_vfmkdle_mvl", + "llvm.ve.vl.vfmkdle.mvml" => "__builtin_ve_vl_vfmkdle_mvml", + "llvm.ve.vl.vfmkdlenan.mvl" => "__builtin_ve_vl_vfmkdlenan_mvl", + "llvm.ve.vl.vfmkdlenan.mvml" => "__builtin_ve_vl_vfmkdlenan_mvml", + "llvm.ve.vl.vfmkdlt.mvl" => "__builtin_ve_vl_vfmkdlt_mvl", + "llvm.ve.vl.vfmkdlt.mvml" => "__builtin_ve_vl_vfmkdlt_mvml", + "llvm.ve.vl.vfmkdltnan.mvl" => "__builtin_ve_vl_vfmkdltnan_mvl", + "llvm.ve.vl.vfmkdltnan.mvml" => "__builtin_ve_vl_vfmkdltnan_mvml", + "llvm.ve.vl.vfmkdnan.mvl" => "__builtin_ve_vl_vfmkdnan_mvl", + "llvm.ve.vl.vfmkdnan.mvml" => "__builtin_ve_vl_vfmkdnan_mvml", + "llvm.ve.vl.vfmkdne.mvl" => "__builtin_ve_vl_vfmkdne_mvl", + "llvm.ve.vl.vfmkdne.mvml" => "__builtin_ve_vl_vfmkdne_mvml", + "llvm.ve.vl.vfmkdnenan.mvl" => "__builtin_ve_vl_vfmkdnenan_mvl", + "llvm.ve.vl.vfmkdnenan.mvml" => "__builtin_ve_vl_vfmkdnenan_mvml", + "llvm.ve.vl.vfmkdnum.mvl" => "__builtin_ve_vl_vfmkdnum_mvl", + "llvm.ve.vl.vfmkdnum.mvml" => "__builtin_ve_vl_vfmkdnum_mvml", + "llvm.ve.vl.vfmklaf.ml" => "__builtin_ve_vl_vfmklaf_ml", + "llvm.ve.vl.vfmklat.ml" => "__builtin_ve_vl_vfmklat_ml", + "llvm.ve.vl.vfmkleq.mvl" => "__builtin_ve_vl_vfmkleq_mvl", + "llvm.ve.vl.vfmkleq.mvml" => "__builtin_ve_vl_vfmkleq_mvml", + "llvm.ve.vl.vfmkleqnan.mvl" => "__builtin_ve_vl_vfmkleqnan_mvl", + "llvm.ve.vl.vfmkleqnan.mvml" => "__builtin_ve_vl_vfmkleqnan_mvml", + "llvm.ve.vl.vfmklge.mvl" => "__builtin_ve_vl_vfmklge_mvl", + "llvm.ve.vl.vfmklge.mvml" => "__builtin_ve_vl_vfmklge_mvml", + "llvm.ve.vl.vfmklgenan.mvl" => "__builtin_ve_vl_vfmklgenan_mvl", + "llvm.ve.vl.vfmklgenan.mvml" => "__builtin_ve_vl_vfmklgenan_mvml", + "llvm.ve.vl.vfmklgt.mvl" => "__builtin_ve_vl_vfmklgt_mvl", + "llvm.ve.vl.vfmklgt.mvml" => "__builtin_ve_vl_vfmklgt_mvml", + "llvm.ve.vl.vfmklgtnan.mvl" => "__builtin_ve_vl_vfmklgtnan_mvl", + "llvm.ve.vl.vfmklgtnan.mvml" => "__builtin_ve_vl_vfmklgtnan_mvml", + "llvm.ve.vl.vfmklle.mvl" => "__builtin_ve_vl_vfmklle_mvl", + "llvm.ve.vl.vfmklle.mvml" => "__builtin_ve_vl_vfmklle_mvml", + "llvm.ve.vl.vfmkllenan.mvl" => "__builtin_ve_vl_vfmkllenan_mvl", + "llvm.ve.vl.vfmkllenan.mvml" => "__builtin_ve_vl_vfmkllenan_mvml", + "llvm.ve.vl.vfmkllt.mvl" => "__builtin_ve_vl_vfmkllt_mvl", + "llvm.ve.vl.vfmkllt.mvml" => "__builtin_ve_vl_vfmkllt_mvml", + "llvm.ve.vl.vfmklltnan.mvl" => "__builtin_ve_vl_vfmklltnan_mvl", + "llvm.ve.vl.vfmklltnan.mvml" => "__builtin_ve_vl_vfmklltnan_mvml", + "llvm.ve.vl.vfmklnan.mvl" => "__builtin_ve_vl_vfmklnan_mvl", + "llvm.ve.vl.vfmklnan.mvml" => "__builtin_ve_vl_vfmklnan_mvml", + "llvm.ve.vl.vfmklne.mvl" => "__builtin_ve_vl_vfmklne_mvl", + "llvm.ve.vl.vfmklne.mvml" => "__builtin_ve_vl_vfmklne_mvml", + "llvm.ve.vl.vfmklnenan.mvl" => "__builtin_ve_vl_vfmklnenan_mvl", + "llvm.ve.vl.vfmklnenan.mvml" => "__builtin_ve_vl_vfmklnenan_mvml", + "llvm.ve.vl.vfmklnum.mvl" => "__builtin_ve_vl_vfmklnum_mvl", + "llvm.ve.vl.vfmklnum.mvml" => "__builtin_ve_vl_vfmklnum_mvml", + "llvm.ve.vl.vfmkseq.mvl" => "__builtin_ve_vl_vfmkseq_mvl", + "llvm.ve.vl.vfmkseq.mvml" => "__builtin_ve_vl_vfmkseq_mvml", + "llvm.ve.vl.vfmkseqnan.mvl" => "__builtin_ve_vl_vfmkseqnan_mvl", + "llvm.ve.vl.vfmkseqnan.mvml" => "__builtin_ve_vl_vfmkseqnan_mvml", + "llvm.ve.vl.vfmksge.mvl" => "__builtin_ve_vl_vfmksge_mvl", + "llvm.ve.vl.vfmksge.mvml" => "__builtin_ve_vl_vfmksge_mvml", + "llvm.ve.vl.vfmksgenan.mvl" => "__builtin_ve_vl_vfmksgenan_mvl", + "llvm.ve.vl.vfmksgenan.mvml" => "__builtin_ve_vl_vfmksgenan_mvml", + "llvm.ve.vl.vfmksgt.mvl" => "__builtin_ve_vl_vfmksgt_mvl", + "llvm.ve.vl.vfmksgt.mvml" => "__builtin_ve_vl_vfmksgt_mvml", + "llvm.ve.vl.vfmksgtnan.mvl" => "__builtin_ve_vl_vfmksgtnan_mvl", + "llvm.ve.vl.vfmksgtnan.mvml" => "__builtin_ve_vl_vfmksgtnan_mvml", + "llvm.ve.vl.vfmksle.mvl" => "__builtin_ve_vl_vfmksle_mvl", + "llvm.ve.vl.vfmksle.mvml" => "__builtin_ve_vl_vfmksle_mvml", + "llvm.ve.vl.vfmkslenan.mvl" => "__builtin_ve_vl_vfmkslenan_mvl", + "llvm.ve.vl.vfmkslenan.mvml" => "__builtin_ve_vl_vfmkslenan_mvml", + "llvm.ve.vl.vfmkslt.mvl" => "__builtin_ve_vl_vfmkslt_mvl", + "llvm.ve.vl.vfmkslt.mvml" => "__builtin_ve_vl_vfmkslt_mvml", + "llvm.ve.vl.vfmksltnan.mvl" => "__builtin_ve_vl_vfmksltnan_mvl", + "llvm.ve.vl.vfmksltnan.mvml" => "__builtin_ve_vl_vfmksltnan_mvml", + "llvm.ve.vl.vfmksnan.mvl" => "__builtin_ve_vl_vfmksnan_mvl", + "llvm.ve.vl.vfmksnan.mvml" => "__builtin_ve_vl_vfmksnan_mvml", + "llvm.ve.vl.vfmksne.mvl" => "__builtin_ve_vl_vfmksne_mvl", + "llvm.ve.vl.vfmksne.mvml" => "__builtin_ve_vl_vfmksne_mvml", + "llvm.ve.vl.vfmksnenan.mvl" => "__builtin_ve_vl_vfmksnenan_mvl", + "llvm.ve.vl.vfmksnenan.mvml" => "__builtin_ve_vl_vfmksnenan_mvml", + "llvm.ve.vl.vfmksnum.mvl" => "__builtin_ve_vl_vfmksnum_mvl", + "llvm.ve.vl.vfmksnum.mvml" => "__builtin_ve_vl_vfmksnum_mvml", + "llvm.ve.vl.vfmkweq.mvl" => "__builtin_ve_vl_vfmkweq_mvl", + "llvm.ve.vl.vfmkweq.mvml" => "__builtin_ve_vl_vfmkweq_mvml", + "llvm.ve.vl.vfmkweqnan.mvl" => "__builtin_ve_vl_vfmkweqnan_mvl", + "llvm.ve.vl.vfmkweqnan.mvml" => "__builtin_ve_vl_vfmkweqnan_mvml", + "llvm.ve.vl.vfmkwge.mvl" => "__builtin_ve_vl_vfmkwge_mvl", + "llvm.ve.vl.vfmkwge.mvml" => "__builtin_ve_vl_vfmkwge_mvml", + "llvm.ve.vl.vfmkwgenan.mvl" => "__builtin_ve_vl_vfmkwgenan_mvl", + "llvm.ve.vl.vfmkwgenan.mvml" => "__builtin_ve_vl_vfmkwgenan_mvml", + "llvm.ve.vl.vfmkwgt.mvl" => "__builtin_ve_vl_vfmkwgt_mvl", + "llvm.ve.vl.vfmkwgt.mvml" => "__builtin_ve_vl_vfmkwgt_mvml", + "llvm.ve.vl.vfmkwgtnan.mvl" => "__builtin_ve_vl_vfmkwgtnan_mvl", + "llvm.ve.vl.vfmkwgtnan.mvml" => "__builtin_ve_vl_vfmkwgtnan_mvml", + "llvm.ve.vl.vfmkwle.mvl" => "__builtin_ve_vl_vfmkwle_mvl", + "llvm.ve.vl.vfmkwle.mvml" => "__builtin_ve_vl_vfmkwle_mvml", + "llvm.ve.vl.vfmkwlenan.mvl" => "__builtin_ve_vl_vfmkwlenan_mvl", + "llvm.ve.vl.vfmkwlenan.mvml" => "__builtin_ve_vl_vfmkwlenan_mvml", + "llvm.ve.vl.vfmkwlt.mvl" => "__builtin_ve_vl_vfmkwlt_mvl", + "llvm.ve.vl.vfmkwlt.mvml" => "__builtin_ve_vl_vfmkwlt_mvml", + "llvm.ve.vl.vfmkwltnan.mvl" => "__builtin_ve_vl_vfmkwltnan_mvl", + "llvm.ve.vl.vfmkwltnan.mvml" => "__builtin_ve_vl_vfmkwltnan_mvml", + "llvm.ve.vl.vfmkwnan.mvl" => "__builtin_ve_vl_vfmkwnan_mvl", + "llvm.ve.vl.vfmkwnan.mvml" => "__builtin_ve_vl_vfmkwnan_mvml", + "llvm.ve.vl.vfmkwne.mvl" => "__builtin_ve_vl_vfmkwne_mvl", + "llvm.ve.vl.vfmkwne.mvml" => "__builtin_ve_vl_vfmkwne_mvml", + "llvm.ve.vl.vfmkwnenan.mvl" => "__builtin_ve_vl_vfmkwnenan_mvl", + "llvm.ve.vl.vfmkwnenan.mvml" => "__builtin_ve_vl_vfmkwnenan_mvml", + "llvm.ve.vl.vfmkwnum.mvl" => "__builtin_ve_vl_vfmkwnum_mvl", + "llvm.ve.vl.vfmkwnum.mvml" => "__builtin_ve_vl_vfmkwnum_mvml", + "llvm.ve.vl.vfmsbd.vsvvl" => "__builtin_ve_vl_vfmsbd_vsvvl", + "llvm.ve.vl.vfmsbd.vsvvmvl" => "__builtin_ve_vl_vfmsbd_vsvvmvl", + "llvm.ve.vl.vfmsbd.vsvvvl" => "__builtin_ve_vl_vfmsbd_vsvvvl", + "llvm.ve.vl.vfmsbd.vvsvl" => "__builtin_ve_vl_vfmsbd_vvsvl", + "llvm.ve.vl.vfmsbd.vvsvmvl" => "__builtin_ve_vl_vfmsbd_vvsvmvl", + "llvm.ve.vl.vfmsbd.vvsvvl" => "__builtin_ve_vl_vfmsbd_vvsvvl", + "llvm.ve.vl.vfmsbd.vvvvl" => "__builtin_ve_vl_vfmsbd_vvvvl", + "llvm.ve.vl.vfmsbd.vvvvmvl" => "__builtin_ve_vl_vfmsbd_vvvvmvl", + "llvm.ve.vl.vfmsbd.vvvvvl" => "__builtin_ve_vl_vfmsbd_vvvvvl", + "llvm.ve.vl.vfmsbs.vsvvl" => "__builtin_ve_vl_vfmsbs_vsvvl", + "llvm.ve.vl.vfmsbs.vsvvmvl" => "__builtin_ve_vl_vfmsbs_vsvvmvl", + "llvm.ve.vl.vfmsbs.vsvvvl" => "__builtin_ve_vl_vfmsbs_vsvvvl", + "llvm.ve.vl.vfmsbs.vvsvl" => "__builtin_ve_vl_vfmsbs_vvsvl", + "llvm.ve.vl.vfmsbs.vvsvmvl" => "__builtin_ve_vl_vfmsbs_vvsvmvl", + "llvm.ve.vl.vfmsbs.vvsvvl" => "__builtin_ve_vl_vfmsbs_vvsvvl", + "llvm.ve.vl.vfmsbs.vvvvl" => "__builtin_ve_vl_vfmsbs_vvvvl", + "llvm.ve.vl.vfmsbs.vvvvmvl" => "__builtin_ve_vl_vfmsbs_vvvvmvl", + "llvm.ve.vl.vfmsbs.vvvvvl" => "__builtin_ve_vl_vfmsbs_vvvvvl", + "llvm.ve.vl.vfmuld.vsvl" => "__builtin_ve_vl_vfmuld_vsvl", + "llvm.ve.vl.vfmuld.vsvmvl" => "__builtin_ve_vl_vfmuld_vsvmvl", + "llvm.ve.vl.vfmuld.vsvvl" => "__builtin_ve_vl_vfmuld_vsvvl", + "llvm.ve.vl.vfmuld.vvvl" => "__builtin_ve_vl_vfmuld_vvvl", + "llvm.ve.vl.vfmuld.vvvmvl" => "__builtin_ve_vl_vfmuld_vvvmvl", + "llvm.ve.vl.vfmuld.vvvvl" => "__builtin_ve_vl_vfmuld_vvvvl", + "llvm.ve.vl.vfmuls.vsvl" => "__builtin_ve_vl_vfmuls_vsvl", + "llvm.ve.vl.vfmuls.vsvmvl" => "__builtin_ve_vl_vfmuls_vsvmvl", + "llvm.ve.vl.vfmuls.vsvvl" => "__builtin_ve_vl_vfmuls_vsvvl", + "llvm.ve.vl.vfmuls.vvvl" => "__builtin_ve_vl_vfmuls_vvvl", + "llvm.ve.vl.vfmuls.vvvmvl" => "__builtin_ve_vl_vfmuls_vvvmvl", + "llvm.ve.vl.vfmuls.vvvvl" => "__builtin_ve_vl_vfmuls_vvvvl", + "llvm.ve.vl.vfnmadd.vsvvl" => "__builtin_ve_vl_vfnmadd_vsvvl", + "llvm.ve.vl.vfnmadd.vsvvmvl" => "__builtin_ve_vl_vfnmadd_vsvvmvl", + "llvm.ve.vl.vfnmadd.vsvvvl" => "__builtin_ve_vl_vfnmadd_vsvvvl", + "llvm.ve.vl.vfnmadd.vvsvl" => "__builtin_ve_vl_vfnmadd_vvsvl", + "llvm.ve.vl.vfnmadd.vvsvmvl" => "__builtin_ve_vl_vfnmadd_vvsvmvl", + "llvm.ve.vl.vfnmadd.vvsvvl" => "__builtin_ve_vl_vfnmadd_vvsvvl", + "llvm.ve.vl.vfnmadd.vvvvl" => "__builtin_ve_vl_vfnmadd_vvvvl", + "llvm.ve.vl.vfnmadd.vvvvmvl" => "__builtin_ve_vl_vfnmadd_vvvvmvl", + "llvm.ve.vl.vfnmadd.vvvvvl" => "__builtin_ve_vl_vfnmadd_vvvvvl", + "llvm.ve.vl.vfnmads.vsvvl" => "__builtin_ve_vl_vfnmads_vsvvl", + "llvm.ve.vl.vfnmads.vsvvmvl" => "__builtin_ve_vl_vfnmads_vsvvmvl", + "llvm.ve.vl.vfnmads.vsvvvl" => "__builtin_ve_vl_vfnmads_vsvvvl", + "llvm.ve.vl.vfnmads.vvsvl" => "__builtin_ve_vl_vfnmads_vvsvl", + "llvm.ve.vl.vfnmads.vvsvmvl" => "__builtin_ve_vl_vfnmads_vvsvmvl", + "llvm.ve.vl.vfnmads.vvsvvl" => "__builtin_ve_vl_vfnmads_vvsvvl", + "llvm.ve.vl.vfnmads.vvvvl" => "__builtin_ve_vl_vfnmads_vvvvl", + "llvm.ve.vl.vfnmads.vvvvmvl" => "__builtin_ve_vl_vfnmads_vvvvmvl", + "llvm.ve.vl.vfnmads.vvvvvl" => "__builtin_ve_vl_vfnmads_vvvvvl", + "llvm.ve.vl.vfnmsbd.vsvvl" => "__builtin_ve_vl_vfnmsbd_vsvvl", + "llvm.ve.vl.vfnmsbd.vsvvmvl" => "__builtin_ve_vl_vfnmsbd_vsvvmvl", + "llvm.ve.vl.vfnmsbd.vsvvvl" => "__builtin_ve_vl_vfnmsbd_vsvvvl", + "llvm.ve.vl.vfnmsbd.vvsvl" => "__builtin_ve_vl_vfnmsbd_vvsvl", + "llvm.ve.vl.vfnmsbd.vvsvmvl" => "__builtin_ve_vl_vfnmsbd_vvsvmvl", + "llvm.ve.vl.vfnmsbd.vvsvvl" => "__builtin_ve_vl_vfnmsbd_vvsvvl", + "llvm.ve.vl.vfnmsbd.vvvvl" => "__builtin_ve_vl_vfnmsbd_vvvvl", + "llvm.ve.vl.vfnmsbd.vvvvmvl" => "__builtin_ve_vl_vfnmsbd_vvvvmvl", + "llvm.ve.vl.vfnmsbd.vvvvvl" => "__builtin_ve_vl_vfnmsbd_vvvvvl", + "llvm.ve.vl.vfnmsbs.vsvvl" => "__builtin_ve_vl_vfnmsbs_vsvvl", + "llvm.ve.vl.vfnmsbs.vsvvmvl" => "__builtin_ve_vl_vfnmsbs_vsvvmvl", + "llvm.ve.vl.vfnmsbs.vsvvvl" => "__builtin_ve_vl_vfnmsbs_vsvvvl", + "llvm.ve.vl.vfnmsbs.vvsvl" => "__builtin_ve_vl_vfnmsbs_vvsvl", + "llvm.ve.vl.vfnmsbs.vvsvmvl" => "__builtin_ve_vl_vfnmsbs_vvsvmvl", + "llvm.ve.vl.vfnmsbs.vvsvvl" => "__builtin_ve_vl_vfnmsbs_vvsvvl", + "llvm.ve.vl.vfnmsbs.vvvvl" => "__builtin_ve_vl_vfnmsbs_vvvvl", + "llvm.ve.vl.vfnmsbs.vvvvmvl" => "__builtin_ve_vl_vfnmsbs_vvvvmvl", + "llvm.ve.vl.vfnmsbs.vvvvvl" => "__builtin_ve_vl_vfnmsbs_vvvvvl", + "llvm.ve.vl.vfrmaxdfst.vvl" => "__builtin_ve_vl_vfrmaxdfst_vvl", + "llvm.ve.vl.vfrmaxdfst.vvvl" => "__builtin_ve_vl_vfrmaxdfst_vvvl", + "llvm.ve.vl.vfrmaxdlst.vvl" => "__builtin_ve_vl_vfrmaxdlst_vvl", + "llvm.ve.vl.vfrmaxdlst.vvvl" => "__builtin_ve_vl_vfrmaxdlst_vvvl", + "llvm.ve.vl.vfrmaxsfst.vvl" => "__builtin_ve_vl_vfrmaxsfst_vvl", + "llvm.ve.vl.vfrmaxsfst.vvvl" => "__builtin_ve_vl_vfrmaxsfst_vvvl", + "llvm.ve.vl.vfrmaxslst.vvl" => "__builtin_ve_vl_vfrmaxslst_vvl", + "llvm.ve.vl.vfrmaxslst.vvvl" => "__builtin_ve_vl_vfrmaxslst_vvvl", + "llvm.ve.vl.vfrmindfst.vvl" => "__builtin_ve_vl_vfrmindfst_vvl", + "llvm.ve.vl.vfrmindfst.vvvl" => "__builtin_ve_vl_vfrmindfst_vvvl", + "llvm.ve.vl.vfrmindlst.vvl" => "__builtin_ve_vl_vfrmindlst_vvl", + "llvm.ve.vl.vfrmindlst.vvvl" => "__builtin_ve_vl_vfrmindlst_vvvl", + "llvm.ve.vl.vfrminsfst.vvl" => "__builtin_ve_vl_vfrminsfst_vvl", + "llvm.ve.vl.vfrminsfst.vvvl" => "__builtin_ve_vl_vfrminsfst_vvvl", + "llvm.ve.vl.vfrminslst.vvl" => "__builtin_ve_vl_vfrminslst_vvl", + "llvm.ve.vl.vfrminslst.vvvl" => "__builtin_ve_vl_vfrminslst_vvvl", + "llvm.ve.vl.vfsqrtd.vvl" => "__builtin_ve_vl_vfsqrtd_vvl", + "llvm.ve.vl.vfsqrtd.vvvl" => "__builtin_ve_vl_vfsqrtd_vvvl", + "llvm.ve.vl.vfsqrts.vvl" => "__builtin_ve_vl_vfsqrts_vvl", + "llvm.ve.vl.vfsqrts.vvvl" => "__builtin_ve_vl_vfsqrts_vvvl", + "llvm.ve.vl.vfsubd.vsvl" => "__builtin_ve_vl_vfsubd_vsvl", + "llvm.ve.vl.vfsubd.vsvmvl" => "__builtin_ve_vl_vfsubd_vsvmvl", + "llvm.ve.vl.vfsubd.vsvvl" => "__builtin_ve_vl_vfsubd_vsvvl", + "llvm.ve.vl.vfsubd.vvvl" => "__builtin_ve_vl_vfsubd_vvvl", + "llvm.ve.vl.vfsubd.vvvmvl" => "__builtin_ve_vl_vfsubd_vvvmvl", + "llvm.ve.vl.vfsubd.vvvvl" => "__builtin_ve_vl_vfsubd_vvvvl", + "llvm.ve.vl.vfsubs.vsvl" => "__builtin_ve_vl_vfsubs_vsvl", + "llvm.ve.vl.vfsubs.vsvmvl" => "__builtin_ve_vl_vfsubs_vsvmvl", + "llvm.ve.vl.vfsubs.vsvvl" => "__builtin_ve_vl_vfsubs_vsvvl", + "llvm.ve.vl.vfsubs.vvvl" => "__builtin_ve_vl_vfsubs_vvvl", + "llvm.ve.vl.vfsubs.vvvmvl" => "__builtin_ve_vl_vfsubs_vvvmvl", + "llvm.ve.vl.vfsubs.vvvvl" => "__builtin_ve_vl_vfsubs_vvvvl", + "llvm.ve.vl.vfsumd.vvl" => "__builtin_ve_vl_vfsumd_vvl", + "llvm.ve.vl.vfsumd.vvml" => "__builtin_ve_vl_vfsumd_vvml", + "llvm.ve.vl.vfsums.vvl" => "__builtin_ve_vl_vfsums_vvl", + "llvm.ve.vl.vfsums.vvml" => "__builtin_ve_vl_vfsums_vvml", + "llvm.ve.vl.vgt.vvssl" => "__builtin_ve_vl_vgt_vvssl", + "llvm.ve.vl.vgt.vvssml" => "__builtin_ve_vl_vgt_vvssml", + "llvm.ve.vl.vgt.vvssmvl" => "__builtin_ve_vl_vgt_vvssmvl", + "llvm.ve.vl.vgt.vvssvl" => "__builtin_ve_vl_vgt_vvssvl", + "llvm.ve.vl.vgtlsx.vvssl" => "__builtin_ve_vl_vgtlsx_vvssl", + "llvm.ve.vl.vgtlsx.vvssml" => "__builtin_ve_vl_vgtlsx_vvssml", + "llvm.ve.vl.vgtlsx.vvssmvl" => "__builtin_ve_vl_vgtlsx_vvssmvl", + "llvm.ve.vl.vgtlsx.vvssvl" => "__builtin_ve_vl_vgtlsx_vvssvl", + "llvm.ve.vl.vgtlsxnc.vvssl" => "__builtin_ve_vl_vgtlsxnc_vvssl", + "llvm.ve.vl.vgtlsxnc.vvssml" => "__builtin_ve_vl_vgtlsxnc_vvssml", + "llvm.ve.vl.vgtlsxnc.vvssmvl" => "__builtin_ve_vl_vgtlsxnc_vvssmvl", + "llvm.ve.vl.vgtlsxnc.vvssvl" => "__builtin_ve_vl_vgtlsxnc_vvssvl", + "llvm.ve.vl.vgtlzx.vvssl" => "__builtin_ve_vl_vgtlzx_vvssl", + "llvm.ve.vl.vgtlzx.vvssml" => "__builtin_ve_vl_vgtlzx_vvssml", + "llvm.ve.vl.vgtlzx.vvssmvl" => "__builtin_ve_vl_vgtlzx_vvssmvl", + "llvm.ve.vl.vgtlzx.vvssvl" => "__builtin_ve_vl_vgtlzx_vvssvl", + "llvm.ve.vl.vgtlzxnc.vvssl" => "__builtin_ve_vl_vgtlzxnc_vvssl", + "llvm.ve.vl.vgtlzxnc.vvssml" => "__builtin_ve_vl_vgtlzxnc_vvssml", + "llvm.ve.vl.vgtlzxnc.vvssmvl" => "__builtin_ve_vl_vgtlzxnc_vvssmvl", + "llvm.ve.vl.vgtlzxnc.vvssvl" => "__builtin_ve_vl_vgtlzxnc_vvssvl", + "llvm.ve.vl.vgtnc.vvssl" => "__builtin_ve_vl_vgtnc_vvssl", + "llvm.ve.vl.vgtnc.vvssml" => "__builtin_ve_vl_vgtnc_vvssml", + "llvm.ve.vl.vgtnc.vvssmvl" => "__builtin_ve_vl_vgtnc_vvssmvl", + "llvm.ve.vl.vgtnc.vvssvl" => "__builtin_ve_vl_vgtnc_vvssvl", + "llvm.ve.vl.vgtu.vvssl" => "__builtin_ve_vl_vgtu_vvssl", + "llvm.ve.vl.vgtu.vvssml" => "__builtin_ve_vl_vgtu_vvssml", + "llvm.ve.vl.vgtu.vvssmvl" => "__builtin_ve_vl_vgtu_vvssmvl", + "llvm.ve.vl.vgtu.vvssvl" => "__builtin_ve_vl_vgtu_vvssvl", + "llvm.ve.vl.vgtunc.vvssl" => "__builtin_ve_vl_vgtunc_vvssl", + "llvm.ve.vl.vgtunc.vvssml" => "__builtin_ve_vl_vgtunc_vvssml", + "llvm.ve.vl.vgtunc.vvssmvl" => "__builtin_ve_vl_vgtunc_vvssmvl", + "llvm.ve.vl.vgtunc.vvssvl" => "__builtin_ve_vl_vgtunc_vvssvl", + "llvm.ve.vl.vld.vssl" => "__builtin_ve_vl_vld_vssl", + "llvm.ve.vl.vld.vssvl" => "__builtin_ve_vl_vld_vssvl", + "llvm.ve.vl.vld2d.vssl" => "__builtin_ve_vl_vld2d_vssl", + "llvm.ve.vl.vld2d.vssvl" => "__builtin_ve_vl_vld2d_vssvl", + "llvm.ve.vl.vld2dnc.vssl" => "__builtin_ve_vl_vld2dnc_vssl", + "llvm.ve.vl.vld2dnc.vssvl" => "__builtin_ve_vl_vld2dnc_vssvl", + "llvm.ve.vl.vldl2dsx.vssl" => "__builtin_ve_vl_vldl2dsx_vssl", + "llvm.ve.vl.vldl2dsx.vssvl" => "__builtin_ve_vl_vldl2dsx_vssvl", + "llvm.ve.vl.vldl2dsxnc.vssl" => "__builtin_ve_vl_vldl2dsxnc_vssl", + "llvm.ve.vl.vldl2dsxnc.vssvl" => "__builtin_ve_vl_vldl2dsxnc_vssvl", + "llvm.ve.vl.vldl2dzx.vssl" => "__builtin_ve_vl_vldl2dzx_vssl", + "llvm.ve.vl.vldl2dzx.vssvl" => "__builtin_ve_vl_vldl2dzx_vssvl", + "llvm.ve.vl.vldl2dzxnc.vssl" => "__builtin_ve_vl_vldl2dzxnc_vssl", + "llvm.ve.vl.vldl2dzxnc.vssvl" => "__builtin_ve_vl_vldl2dzxnc_vssvl", + "llvm.ve.vl.vldlsx.vssl" => "__builtin_ve_vl_vldlsx_vssl", + "llvm.ve.vl.vldlsx.vssvl" => "__builtin_ve_vl_vldlsx_vssvl", + "llvm.ve.vl.vldlsxnc.vssl" => "__builtin_ve_vl_vldlsxnc_vssl", + "llvm.ve.vl.vldlsxnc.vssvl" => "__builtin_ve_vl_vldlsxnc_vssvl", + "llvm.ve.vl.vldlzx.vssl" => "__builtin_ve_vl_vldlzx_vssl", + "llvm.ve.vl.vldlzx.vssvl" => "__builtin_ve_vl_vldlzx_vssvl", + "llvm.ve.vl.vldlzxnc.vssl" => "__builtin_ve_vl_vldlzxnc_vssl", + "llvm.ve.vl.vldlzxnc.vssvl" => "__builtin_ve_vl_vldlzxnc_vssvl", + "llvm.ve.vl.vldnc.vssl" => "__builtin_ve_vl_vldnc_vssl", + "llvm.ve.vl.vldnc.vssvl" => "__builtin_ve_vl_vldnc_vssvl", + "llvm.ve.vl.vldu.vssl" => "__builtin_ve_vl_vldu_vssl", + "llvm.ve.vl.vldu.vssvl" => "__builtin_ve_vl_vldu_vssvl", + "llvm.ve.vl.vldu2d.vssl" => "__builtin_ve_vl_vldu2d_vssl", + "llvm.ve.vl.vldu2d.vssvl" => "__builtin_ve_vl_vldu2d_vssvl", + "llvm.ve.vl.vldu2dnc.vssl" => "__builtin_ve_vl_vldu2dnc_vssl", + "llvm.ve.vl.vldu2dnc.vssvl" => "__builtin_ve_vl_vldu2dnc_vssvl", + "llvm.ve.vl.vldunc.vssl" => "__builtin_ve_vl_vldunc_vssl", + "llvm.ve.vl.vldunc.vssvl" => "__builtin_ve_vl_vldunc_vssvl", + "llvm.ve.vl.vldz.vvl" => "__builtin_ve_vl_vldz_vvl", + "llvm.ve.vl.vldz.vvmvl" => "__builtin_ve_vl_vldz_vvmvl", + "llvm.ve.vl.vldz.vvvl" => "__builtin_ve_vl_vldz_vvvl", + "llvm.ve.vl.vmaxsl.vsvl" => "__builtin_ve_vl_vmaxsl_vsvl", + "llvm.ve.vl.vmaxsl.vsvmvl" => "__builtin_ve_vl_vmaxsl_vsvmvl", + "llvm.ve.vl.vmaxsl.vsvvl" => "__builtin_ve_vl_vmaxsl_vsvvl", + "llvm.ve.vl.vmaxsl.vvvl" => "__builtin_ve_vl_vmaxsl_vvvl", + "llvm.ve.vl.vmaxsl.vvvmvl" => "__builtin_ve_vl_vmaxsl_vvvmvl", + "llvm.ve.vl.vmaxsl.vvvvl" => "__builtin_ve_vl_vmaxsl_vvvvl", + "llvm.ve.vl.vmaxswsx.vsvl" => "__builtin_ve_vl_vmaxswsx_vsvl", + "llvm.ve.vl.vmaxswsx.vsvmvl" => "__builtin_ve_vl_vmaxswsx_vsvmvl", + "llvm.ve.vl.vmaxswsx.vsvvl" => "__builtin_ve_vl_vmaxswsx_vsvvl", + "llvm.ve.vl.vmaxswsx.vvvl" => "__builtin_ve_vl_vmaxswsx_vvvl", + "llvm.ve.vl.vmaxswsx.vvvmvl" => "__builtin_ve_vl_vmaxswsx_vvvmvl", + "llvm.ve.vl.vmaxswsx.vvvvl" => "__builtin_ve_vl_vmaxswsx_vvvvl", + "llvm.ve.vl.vmaxswzx.vsvl" => "__builtin_ve_vl_vmaxswzx_vsvl", + "llvm.ve.vl.vmaxswzx.vsvmvl" => "__builtin_ve_vl_vmaxswzx_vsvmvl", + "llvm.ve.vl.vmaxswzx.vsvvl" => "__builtin_ve_vl_vmaxswzx_vsvvl", + "llvm.ve.vl.vmaxswzx.vvvl" => "__builtin_ve_vl_vmaxswzx_vvvl", + "llvm.ve.vl.vmaxswzx.vvvmvl" => "__builtin_ve_vl_vmaxswzx_vvvmvl", + "llvm.ve.vl.vmaxswzx.vvvvl" => "__builtin_ve_vl_vmaxswzx_vvvvl", + "llvm.ve.vl.vminsl.vsvl" => "__builtin_ve_vl_vminsl_vsvl", + "llvm.ve.vl.vminsl.vsvmvl" => "__builtin_ve_vl_vminsl_vsvmvl", + "llvm.ve.vl.vminsl.vsvvl" => "__builtin_ve_vl_vminsl_vsvvl", + "llvm.ve.vl.vminsl.vvvl" => "__builtin_ve_vl_vminsl_vvvl", + "llvm.ve.vl.vminsl.vvvmvl" => "__builtin_ve_vl_vminsl_vvvmvl", + "llvm.ve.vl.vminsl.vvvvl" => "__builtin_ve_vl_vminsl_vvvvl", + "llvm.ve.vl.vminswsx.vsvl" => "__builtin_ve_vl_vminswsx_vsvl", + "llvm.ve.vl.vminswsx.vsvmvl" => "__builtin_ve_vl_vminswsx_vsvmvl", + "llvm.ve.vl.vminswsx.vsvvl" => "__builtin_ve_vl_vminswsx_vsvvl", + "llvm.ve.vl.vminswsx.vvvl" => "__builtin_ve_vl_vminswsx_vvvl", + "llvm.ve.vl.vminswsx.vvvmvl" => "__builtin_ve_vl_vminswsx_vvvmvl", + "llvm.ve.vl.vminswsx.vvvvl" => "__builtin_ve_vl_vminswsx_vvvvl", + "llvm.ve.vl.vminswzx.vsvl" => "__builtin_ve_vl_vminswzx_vsvl", + "llvm.ve.vl.vminswzx.vsvmvl" => "__builtin_ve_vl_vminswzx_vsvmvl", + "llvm.ve.vl.vminswzx.vsvvl" => "__builtin_ve_vl_vminswzx_vsvvl", + "llvm.ve.vl.vminswzx.vvvl" => "__builtin_ve_vl_vminswzx_vvvl", + "llvm.ve.vl.vminswzx.vvvmvl" => "__builtin_ve_vl_vminswzx_vvvmvl", + "llvm.ve.vl.vminswzx.vvvvl" => "__builtin_ve_vl_vminswzx_vvvvl", + "llvm.ve.vl.vmrg.vsvml" => "__builtin_ve_vl_vmrg_vsvml", + "llvm.ve.vl.vmrg.vsvmvl" => "__builtin_ve_vl_vmrg_vsvmvl", + "llvm.ve.vl.vmrg.vvvml" => "__builtin_ve_vl_vmrg_vvvml", + "llvm.ve.vl.vmrg.vvvmvl" => "__builtin_ve_vl_vmrg_vvvmvl", + "llvm.ve.vl.vmrgw.vsvMl" => "__builtin_ve_vl_vmrgw_vsvMl", + "llvm.ve.vl.vmrgw.vsvMvl" => "__builtin_ve_vl_vmrgw_vsvMvl", + "llvm.ve.vl.vmrgw.vvvMl" => "__builtin_ve_vl_vmrgw_vvvMl", + "llvm.ve.vl.vmrgw.vvvMvl" => "__builtin_ve_vl_vmrgw_vvvMvl", + "llvm.ve.vl.vmulsl.vsvl" => "__builtin_ve_vl_vmulsl_vsvl", + "llvm.ve.vl.vmulsl.vsvmvl" => "__builtin_ve_vl_vmulsl_vsvmvl", + "llvm.ve.vl.vmulsl.vsvvl" => "__builtin_ve_vl_vmulsl_vsvvl", + "llvm.ve.vl.vmulsl.vvvl" => "__builtin_ve_vl_vmulsl_vvvl", + "llvm.ve.vl.vmulsl.vvvmvl" => "__builtin_ve_vl_vmulsl_vvvmvl", + "llvm.ve.vl.vmulsl.vvvvl" => "__builtin_ve_vl_vmulsl_vvvvl", + "llvm.ve.vl.vmulslw.vsvl" => "__builtin_ve_vl_vmulslw_vsvl", + "llvm.ve.vl.vmulslw.vsvvl" => "__builtin_ve_vl_vmulslw_vsvvl", + "llvm.ve.vl.vmulslw.vvvl" => "__builtin_ve_vl_vmulslw_vvvl", + "llvm.ve.vl.vmulslw.vvvvl" => "__builtin_ve_vl_vmulslw_vvvvl", + "llvm.ve.vl.vmulswsx.vsvl" => "__builtin_ve_vl_vmulswsx_vsvl", + "llvm.ve.vl.vmulswsx.vsvmvl" => "__builtin_ve_vl_vmulswsx_vsvmvl", + "llvm.ve.vl.vmulswsx.vsvvl" => "__builtin_ve_vl_vmulswsx_vsvvl", + "llvm.ve.vl.vmulswsx.vvvl" => "__builtin_ve_vl_vmulswsx_vvvl", + "llvm.ve.vl.vmulswsx.vvvmvl" => "__builtin_ve_vl_vmulswsx_vvvmvl", + "llvm.ve.vl.vmulswsx.vvvvl" => "__builtin_ve_vl_vmulswsx_vvvvl", + "llvm.ve.vl.vmulswzx.vsvl" => "__builtin_ve_vl_vmulswzx_vsvl", + "llvm.ve.vl.vmulswzx.vsvmvl" => "__builtin_ve_vl_vmulswzx_vsvmvl", + "llvm.ve.vl.vmulswzx.vsvvl" => "__builtin_ve_vl_vmulswzx_vsvvl", + "llvm.ve.vl.vmulswzx.vvvl" => "__builtin_ve_vl_vmulswzx_vvvl", + "llvm.ve.vl.vmulswzx.vvvmvl" => "__builtin_ve_vl_vmulswzx_vvvmvl", + "llvm.ve.vl.vmulswzx.vvvvl" => "__builtin_ve_vl_vmulswzx_vvvvl", + "llvm.ve.vl.vmulul.vsvl" => "__builtin_ve_vl_vmulul_vsvl", + "llvm.ve.vl.vmulul.vsvmvl" => "__builtin_ve_vl_vmulul_vsvmvl", + "llvm.ve.vl.vmulul.vsvvl" => "__builtin_ve_vl_vmulul_vsvvl", + "llvm.ve.vl.vmulul.vvvl" => "__builtin_ve_vl_vmulul_vvvl", + "llvm.ve.vl.vmulul.vvvmvl" => "__builtin_ve_vl_vmulul_vvvmvl", + "llvm.ve.vl.vmulul.vvvvl" => "__builtin_ve_vl_vmulul_vvvvl", + "llvm.ve.vl.vmuluw.vsvl" => "__builtin_ve_vl_vmuluw_vsvl", + "llvm.ve.vl.vmuluw.vsvmvl" => "__builtin_ve_vl_vmuluw_vsvmvl", + "llvm.ve.vl.vmuluw.vsvvl" => "__builtin_ve_vl_vmuluw_vsvvl", + "llvm.ve.vl.vmuluw.vvvl" => "__builtin_ve_vl_vmuluw_vvvl", + "llvm.ve.vl.vmuluw.vvvmvl" => "__builtin_ve_vl_vmuluw_vvvmvl", + "llvm.ve.vl.vmuluw.vvvvl" => "__builtin_ve_vl_vmuluw_vvvvl", + "llvm.ve.vl.vmv.vsvl" => "__builtin_ve_vl_vmv_vsvl", + "llvm.ve.vl.vmv.vsvmvl" => "__builtin_ve_vl_vmv_vsvmvl", + "llvm.ve.vl.vmv.vsvvl" => "__builtin_ve_vl_vmv_vsvvl", + "llvm.ve.vl.vor.vsvl" => "__builtin_ve_vl_vor_vsvl", + "llvm.ve.vl.vor.vsvmvl" => "__builtin_ve_vl_vor_vsvmvl", + "llvm.ve.vl.vor.vsvvl" => "__builtin_ve_vl_vor_vsvvl", + "llvm.ve.vl.vor.vvvl" => "__builtin_ve_vl_vor_vvvl", + "llvm.ve.vl.vor.vvvmvl" => "__builtin_ve_vl_vor_vvvmvl", + "llvm.ve.vl.vor.vvvvl" => "__builtin_ve_vl_vor_vvvvl", + "llvm.ve.vl.vpcnt.vvl" => "__builtin_ve_vl_vpcnt_vvl", + "llvm.ve.vl.vpcnt.vvmvl" => "__builtin_ve_vl_vpcnt_vvmvl", + "llvm.ve.vl.vpcnt.vvvl" => "__builtin_ve_vl_vpcnt_vvvl", + "llvm.ve.vl.vrand.vvl" => "__builtin_ve_vl_vrand_vvl", + "llvm.ve.vl.vrand.vvml" => "__builtin_ve_vl_vrand_vvml", + "llvm.ve.vl.vrcpd.vvl" => "__builtin_ve_vl_vrcpd_vvl", + "llvm.ve.vl.vrcpd.vvvl" => "__builtin_ve_vl_vrcpd_vvvl", + "llvm.ve.vl.vrcps.vvl" => "__builtin_ve_vl_vrcps_vvl", + "llvm.ve.vl.vrcps.vvvl" => "__builtin_ve_vl_vrcps_vvvl", + "llvm.ve.vl.vrmaxslfst.vvl" => "__builtin_ve_vl_vrmaxslfst_vvl", + "llvm.ve.vl.vrmaxslfst.vvvl" => "__builtin_ve_vl_vrmaxslfst_vvvl", + "llvm.ve.vl.vrmaxsllst.vvl" => "__builtin_ve_vl_vrmaxsllst_vvl", + "llvm.ve.vl.vrmaxsllst.vvvl" => "__builtin_ve_vl_vrmaxsllst_vvvl", + "llvm.ve.vl.vrmaxswfstsx.vvl" => "__builtin_ve_vl_vrmaxswfstsx_vvl", + "llvm.ve.vl.vrmaxswfstsx.vvvl" => "__builtin_ve_vl_vrmaxswfstsx_vvvl", + "llvm.ve.vl.vrmaxswfstzx.vvl" => "__builtin_ve_vl_vrmaxswfstzx_vvl", + "llvm.ve.vl.vrmaxswfstzx.vvvl" => "__builtin_ve_vl_vrmaxswfstzx_vvvl", + "llvm.ve.vl.vrmaxswlstsx.vvl" => "__builtin_ve_vl_vrmaxswlstsx_vvl", + "llvm.ve.vl.vrmaxswlstsx.vvvl" => "__builtin_ve_vl_vrmaxswlstsx_vvvl", + "llvm.ve.vl.vrmaxswlstzx.vvl" => "__builtin_ve_vl_vrmaxswlstzx_vvl", + "llvm.ve.vl.vrmaxswlstzx.vvvl" => "__builtin_ve_vl_vrmaxswlstzx_vvvl", + "llvm.ve.vl.vrminslfst.vvl" => "__builtin_ve_vl_vrminslfst_vvl", + "llvm.ve.vl.vrminslfst.vvvl" => "__builtin_ve_vl_vrminslfst_vvvl", + "llvm.ve.vl.vrminsllst.vvl" => "__builtin_ve_vl_vrminsllst_vvl", + "llvm.ve.vl.vrminsllst.vvvl" => "__builtin_ve_vl_vrminsllst_vvvl", + "llvm.ve.vl.vrminswfstsx.vvl" => "__builtin_ve_vl_vrminswfstsx_vvl", + "llvm.ve.vl.vrminswfstsx.vvvl" => "__builtin_ve_vl_vrminswfstsx_vvvl", + "llvm.ve.vl.vrminswfstzx.vvl" => "__builtin_ve_vl_vrminswfstzx_vvl", + "llvm.ve.vl.vrminswfstzx.vvvl" => "__builtin_ve_vl_vrminswfstzx_vvvl", + "llvm.ve.vl.vrminswlstsx.vvl" => "__builtin_ve_vl_vrminswlstsx_vvl", + "llvm.ve.vl.vrminswlstsx.vvvl" => "__builtin_ve_vl_vrminswlstsx_vvvl", + "llvm.ve.vl.vrminswlstzx.vvl" => "__builtin_ve_vl_vrminswlstzx_vvl", + "llvm.ve.vl.vrminswlstzx.vvvl" => "__builtin_ve_vl_vrminswlstzx_vvvl", + "llvm.ve.vl.vror.vvl" => "__builtin_ve_vl_vror_vvl", + "llvm.ve.vl.vror.vvml" => "__builtin_ve_vl_vror_vvml", + "llvm.ve.vl.vrsqrtd.vvl" => "__builtin_ve_vl_vrsqrtd_vvl", + "llvm.ve.vl.vrsqrtd.vvvl" => "__builtin_ve_vl_vrsqrtd_vvvl", + "llvm.ve.vl.vrsqrtdnex.vvl" => "__builtin_ve_vl_vrsqrtdnex_vvl", + "llvm.ve.vl.vrsqrtdnex.vvvl" => "__builtin_ve_vl_vrsqrtdnex_vvvl", + "llvm.ve.vl.vrsqrts.vvl" => "__builtin_ve_vl_vrsqrts_vvl", + "llvm.ve.vl.vrsqrts.vvvl" => "__builtin_ve_vl_vrsqrts_vvvl", + "llvm.ve.vl.vrsqrtsnex.vvl" => "__builtin_ve_vl_vrsqrtsnex_vvl", + "llvm.ve.vl.vrsqrtsnex.vvvl" => "__builtin_ve_vl_vrsqrtsnex_vvvl", + "llvm.ve.vl.vrxor.vvl" => "__builtin_ve_vl_vrxor_vvl", + "llvm.ve.vl.vrxor.vvml" => "__builtin_ve_vl_vrxor_vvml", + "llvm.ve.vl.vsc.vvssl" => "__builtin_ve_vl_vsc_vvssl", + "llvm.ve.vl.vsc.vvssml" => "__builtin_ve_vl_vsc_vvssml", + "llvm.ve.vl.vscl.vvssl" => "__builtin_ve_vl_vscl_vvssl", + "llvm.ve.vl.vscl.vvssml" => "__builtin_ve_vl_vscl_vvssml", + "llvm.ve.vl.vsclnc.vvssl" => "__builtin_ve_vl_vsclnc_vvssl", + "llvm.ve.vl.vsclnc.vvssml" => "__builtin_ve_vl_vsclnc_vvssml", + "llvm.ve.vl.vsclncot.vvssl" => "__builtin_ve_vl_vsclncot_vvssl", + "llvm.ve.vl.vsclncot.vvssml" => "__builtin_ve_vl_vsclncot_vvssml", + "llvm.ve.vl.vsclot.vvssl" => "__builtin_ve_vl_vsclot_vvssl", + "llvm.ve.vl.vsclot.vvssml" => "__builtin_ve_vl_vsclot_vvssml", + "llvm.ve.vl.vscnc.vvssl" => "__builtin_ve_vl_vscnc_vvssl", + "llvm.ve.vl.vscnc.vvssml" => "__builtin_ve_vl_vscnc_vvssml", + "llvm.ve.vl.vscncot.vvssl" => "__builtin_ve_vl_vscncot_vvssl", + "llvm.ve.vl.vscncot.vvssml" => "__builtin_ve_vl_vscncot_vvssml", + "llvm.ve.vl.vscot.vvssl" => "__builtin_ve_vl_vscot_vvssl", + "llvm.ve.vl.vscot.vvssml" => "__builtin_ve_vl_vscot_vvssml", + "llvm.ve.vl.vscu.vvssl" => "__builtin_ve_vl_vscu_vvssl", + "llvm.ve.vl.vscu.vvssml" => "__builtin_ve_vl_vscu_vvssml", + "llvm.ve.vl.vscunc.vvssl" => "__builtin_ve_vl_vscunc_vvssl", + "llvm.ve.vl.vscunc.vvssml" => "__builtin_ve_vl_vscunc_vvssml", + "llvm.ve.vl.vscuncot.vvssl" => "__builtin_ve_vl_vscuncot_vvssl", + "llvm.ve.vl.vscuncot.vvssml" => "__builtin_ve_vl_vscuncot_vvssml", + "llvm.ve.vl.vscuot.vvssl" => "__builtin_ve_vl_vscuot_vvssl", + "llvm.ve.vl.vscuot.vvssml" => "__builtin_ve_vl_vscuot_vvssml", + "llvm.ve.vl.vseq.vl" => "__builtin_ve_vl_vseq_vl", + "llvm.ve.vl.vseq.vvl" => "__builtin_ve_vl_vseq_vvl", + "llvm.ve.vl.vsfa.vvssl" => "__builtin_ve_vl_vsfa_vvssl", + "llvm.ve.vl.vsfa.vvssmvl" => "__builtin_ve_vl_vsfa_vvssmvl", + "llvm.ve.vl.vsfa.vvssvl" => "__builtin_ve_vl_vsfa_vvssvl", + "llvm.ve.vl.vshf.vvvsl" => "__builtin_ve_vl_vshf_vvvsl", + "llvm.ve.vl.vshf.vvvsvl" => "__builtin_ve_vl_vshf_vvvsvl", + "llvm.ve.vl.vslal.vvsl" => "__builtin_ve_vl_vslal_vvsl", + "llvm.ve.vl.vslal.vvsmvl" => "__builtin_ve_vl_vslal_vvsmvl", + "llvm.ve.vl.vslal.vvsvl" => "__builtin_ve_vl_vslal_vvsvl", + "llvm.ve.vl.vslal.vvvl" => "__builtin_ve_vl_vslal_vvvl", + "llvm.ve.vl.vslal.vvvmvl" => "__builtin_ve_vl_vslal_vvvmvl", + "llvm.ve.vl.vslal.vvvvl" => "__builtin_ve_vl_vslal_vvvvl", + "llvm.ve.vl.vslawsx.vvsl" => "__builtin_ve_vl_vslawsx_vvsl", + "llvm.ve.vl.vslawsx.vvsmvl" => "__builtin_ve_vl_vslawsx_vvsmvl", + "llvm.ve.vl.vslawsx.vvsvl" => "__builtin_ve_vl_vslawsx_vvsvl", + "llvm.ve.vl.vslawsx.vvvl" => "__builtin_ve_vl_vslawsx_vvvl", + "llvm.ve.vl.vslawsx.vvvmvl" => "__builtin_ve_vl_vslawsx_vvvmvl", + "llvm.ve.vl.vslawsx.vvvvl" => "__builtin_ve_vl_vslawsx_vvvvl", + "llvm.ve.vl.vslawzx.vvsl" => "__builtin_ve_vl_vslawzx_vvsl", + "llvm.ve.vl.vslawzx.vvsmvl" => "__builtin_ve_vl_vslawzx_vvsmvl", + "llvm.ve.vl.vslawzx.vvsvl" => "__builtin_ve_vl_vslawzx_vvsvl", + "llvm.ve.vl.vslawzx.vvvl" => "__builtin_ve_vl_vslawzx_vvvl", + "llvm.ve.vl.vslawzx.vvvmvl" => "__builtin_ve_vl_vslawzx_vvvmvl", + "llvm.ve.vl.vslawzx.vvvvl" => "__builtin_ve_vl_vslawzx_vvvvl", + "llvm.ve.vl.vsll.vvsl" => "__builtin_ve_vl_vsll_vvsl", + "llvm.ve.vl.vsll.vvsmvl" => "__builtin_ve_vl_vsll_vvsmvl", + "llvm.ve.vl.vsll.vvsvl" => "__builtin_ve_vl_vsll_vvsvl", + "llvm.ve.vl.vsll.vvvl" => "__builtin_ve_vl_vsll_vvvl", + "llvm.ve.vl.vsll.vvvmvl" => "__builtin_ve_vl_vsll_vvvmvl", + "llvm.ve.vl.vsll.vvvvl" => "__builtin_ve_vl_vsll_vvvvl", + "llvm.ve.vl.vsral.vvsl" => "__builtin_ve_vl_vsral_vvsl", + "llvm.ve.vl.vsral.vvsmvl" => "__builtin_ve_vl_vsral_vvsmvl", + "llvm.ve.vl.vsral.vvsvl" => "__builtin_ve_vl_vsral_vvsvl", + "llvm.ve.vl.vsral.vvvl" => "__builtin_ve_vl_vsral_vvvl", + "llvm.ve.vl.vsral.vvvmvl" => "__builtin_ve_vl_vsral_vvvmvl", + "llvm.ve.vl.vsral.vvvvl" => "__builtin_ve_vl_vsral_vvvvl", + "llvm.ve.vl.vsrawsx.vvsl" => "__builtin_ve_vl_vsrawsx_vvsl", + "llvm.ve.vl.vsrawsx.vvsmvl" => "__builtin_ve_vl_vsrawsx_vvsmvl", + "llvm.ve.vl.vsrawsx.vvsvl" => "__builtin_ve_vl_vsrawsx_vvsvl", + "llvm.ve.vl.vsrawsx.vvvl" => "__builtin_ve_vl_vsrawsx_vvvl", + "llvm.ve.vl.vsrawsx.vvvmvl" => "__builtin_ve_vl_vsrawsx_vvvmvl", + "llvm.ve.vl.vsrawsx.vvvvl" => "__builtin_ve_vl_vsrawsx_vvvvl", + "llvm.ve.vl.vsrawzx.vvsl" => "__builtin_ve_vl_vsrawzx_vvsl", + "llvm.ve.vl.vsrawzx.vvsmvl" => "__builtin_ve_vl_vsrawzx_vvsmvl", + "llvm.ve.vl.vsrawzx.vvsvl" => "__builtin_ve_vl_vsrawzx_vvsvl", + "llvm.ve.vl.vsrawzx.vvvl" => "__builtin_ve_vl_vsrawzx_vvvl", + "llvm.ve.vl.vsrawzx.vvvmvl" => "__builtin_ve_vl_vsrawzx_vvvmvl", + "llvm.ve.vl.vsrawzx.vvvvl" => "__builtin_ve_vl_vsrawzx_vvvvl", + "llvm.ve.vl.vsrl.vvsl" => "__builtin_ve_vl_vsrl_vvsl", + "llvm.ve.vl.vsrl.vvsmvl" => "__builtin_ve_vl_vsrl_vvsmvl", + "llvm.ve.vl.vsrl.vvsvl" => "__builtin_ve_vl_vsrl_vvsvl", + "llvm.ve.vl.vsrl.vvvl" => "__builtin_ve_vl_vsrl_vvvl", + "llvm.ve.vl.vsrl.vvvmvl" => "__builtin_ve_vl_vsrl_vvvmvl", + "llvm.ve.vl.vsrl.vvvvl" => "__builtin_ve_vl_vsrl_vvvvl", + "llvm.ve.vl.vst.vssl" => "__builtin_ve_vl_vst_vssl", + "llvm.ve.vl.vst.vssml" => "__builtin_ve_vl_vst_vssml", + "llvm.ve.vl.vst2d.vssl" => "__builtin_ve_vl_vst2d_vssl", + "llvm.ve.vl.vst2d.vssml" => "__builtin_ve_vl_vst2d_vssml", + "llvm.ve.vl.vst2dnc.vssl" => "__builtin_ve_vl_vst2dnc_vssl", + "llvm.ve.vl.vst2dnc.vssml" => "__builtin_ve_vl_vst2dnc_vssml", + "llvm.ve.vl.vst2dncot.vssl" => "__builtin_ve_vl_vst2dncot_vssl", + "llvm.ve.vl.vst2dncot.vssml" => "__builtin_ve_vl_vst2dncot_vssml", + "llvm.ve.vl.vst2dot.vssl" => "__builtin_ve_vl_vst2dot_vssl", + "llvm.ve.vl.vst2dot.vssml" => "__builtin_ve_vl_vst2dot_vssml", + "llvm.ve.vl.vstl.vssl" => "__builtin_ve_vl_vstl_vssl", + "llvm.ve.vl.vstl.vssml" => "__builtin_ve_vl_vstl_vssml", + "llvm.ve.vl.vstl2d.vssl" => "__builtin_ve_vl_vstl2d_vssl", + "llvm.ve.vl.vstl2d.vssml" => "__builtin_ve_vl_vstl2d_vssml", + "llvm.ve.vl.vstl2dnc.vssl" => "__builtin_ve_vl_vstl2dnc_vssl", + "llvm.ve.vl.vstl2dnc.vssml" => "__builtin_ve_vl_vstl2dnc_vssml", + "llvm.ve.vl.vstl2dncot.vssl" => "__builtin_ve_vl_vstl2dncot_vssl", + "llvm.ve.vl.vstl2dncot.vssml" => "__builtin_ve_vl_vstl2dncot_vssml", + "llvm.ve.vl.vstl2dot.vssl" => "__builtin_ve_vl_vstl2dot_vssl", + "llvm.ve.vl.vstl2dot.vssml" => "__builtin_ve_vl_vstl2dot_vssml", + "llvm.ve.vl.vstlnc.vssl" => "__builtin_ve_vl_vstlnc_vssl", + "llvm.ve.vl.vstlnc.vssml" => "__builtin_ve_vl_vstlnc_vssml", + "llvm.ve.vl.vstlncot.vssl" => "__builtin_ve_vl_vstlncot_vssl", + "llvm.ve.vl.vstlncot.vssml" => "__builtin_ve_vl_vstlncot_vssml", + "llvm.ve.vl.vstlot.vssl" => "__builtin_ve_vl_vstlot_vssl", + "llvm.ve.vl.vstlot.vssml" => "__builtin_ve_vl_vstlot_vssml", + "llvm.ve.vl.vstnc.vssl" => "__builtin_ve_vl_vstnc_vssl", + "llvm.ve.vl.vstnc.vssml" => "__builtin_ve_vl_vstnc_vssml", + "llvm.ve.vl.vstncot.vssl" => "__builtin_ve_vl_vstncot_vssl", + "llvm.ve.vl.vstncot.vssml" => "__builtin_ve_vl_vstncot_vssml", + "llvm.ve.vl.vstot.vssl" => "__builtin_ve_vl_vstot_vssl", + "llvm.ve.vl.vstot.vssml" => "__builtin_ve_vl_vstot_vssml", + "llvm.ve.vl.vstu.vssl" => "__builtin_ve_vl_vstu_vssl", + "llvm.ve.vl.vstu.vssml" => "__builtin_ve_vl_vstu_vssml", + "llvm.ve.vl.vstu2d.vssl" => "__builtin_ve_vl_vstu2d_vssl", + "llvm.ve.vl.vstu2d.vssml" => "__builtin_ve_vl_vstu2d_vssml", + "llvm.ve.vl.vstu2dnc.vssl" => "__builtin_ve_vl_vstu2dnc_vssl", + "llvm.ve.vl.vstu2dnc.vssml" => "__builtin_ve_vl_vstu2dnc_vssml", + "llvm.ve.vl.vstu2dncot.vssl" => "__builtin_ve_vl_vstu2dncot_vssl", + "llvm.ve.vl.vstu2dncot.vssml" => "__builtin_ve_vl_vstu2dncot_vssml", + "llvm.ve.vl.vstu2dot.vssl" => "__builtin_ve_vl_vstu2dot_vssl", + "llvm.ve.vl.vstu2dot.vssml" => "__builtin_ve_vl_vstu2dot_vssml", + "llvm.ve.vl.vstunc.vssl" => "__builtin_ve_vl_vstunc_vssl", + "llvm.ve.vl.vstunc.vssml" => "__builtin_ve_vl_vstunc_vssml", + "llvm.ve.vl.vstuncot.vssl" => "__builtin_ve_vl_vstuncot_vssl", + "llvm.ve.vl.vstuncot.vssml" => "__builtin_ve_vl_vstuncot_vssml", + "llvm.ve.vl.vstuot.vssl" => "__builtin_ve_vl_vstuot_vssl", + "llvm.ve.vl.vstuot.vssml" => "__builtin_ve_vl_vstuot_vssml", + "llvm.ve.vl.vsubsl.vsvl" => "__builtin_ve_vl_vsubsl_vsvl", + "llvm.ve.vl.vsubsl.vsvmvl" => "__builtin_ve_vl_vsubsl_vsvmvl", + "llvm.ve.vl.vsubsl.vsvvl" => "__builtin_ve_vl_vsubsl_vsvvl", + "llvm.ve.vl.vsubsl.vvvl" => "__builtin_ve_vl_vsubsl_vvvl", + "llvm.ve.vl.vsubsl.vvvmvl" => "__builtin_ve_vl_vsubsl_vvvmvl", + "llvm.ve.vl.vsubsl.vvvvl" => "__builtin_ve_vl_vsubsl_vvvvl", + "llvm.ve.vl.vsubswsx.vsvl" => "__builtin_ve_vl_vsubswsx_vsvl", + "llvm.ve.vl.vsubswsx.vsvmvl" => "__builtin_ve_vl_vsubswsx_vsvmvl", + "llvm.ve.vl.vsubswsx.vsvvl" => "__builtin_ve_vl_vsubswsx_vsvvl", + "llvm.ve.vl.vsubswsx.vvvl" => "__builtin_ve_vl_vsubswsx_vvvl", + "llvm.ve.vl.vsubswsx.vvvmvl" => "__builtin_ve_vl_vsubswsx_vvvmvl", + "llvm.ve.vl.vsubswsx.vvvvl" => "__builtin_ve_vl_vsubswsx_vvvvl", + "llvm.ve.vl.vsubswzx.vsvl" => "__builtin_ve_vl_vsubswzx_vsvl", + "llvm.ve.vl.vsubswzx.vsvmvl" => "__builtin_ve_vl_vsubswzx_vsvmvl", + "llvm.ve.vl.vsubswzx.vsvvl" => "__builtin_ve_vl_vsubswzx_vsvvl", + "llvm.ve.vl.vsubswzx.vvvl" => "__builtin_ve_vl_vsubswzx_vvvl", + "llvm.ve.vl.vsubswzx.vvvmvl" => "__builtin_ve_vl_vsubswzx_vvvmvl", + "llvm.ve.vl.vsubswzx.vvvvl" => "__builtin_ve_vl_vsubswzx_vvvvl", + "llvm.ve.vl.vsubul.vsvl" => "__builtin_ve_vl_vsubul_vsvl", + "llvm.ve.vl.vsubul.vsvmvl" => "__builtin_ve_vl_vsubul_vsvmvl", + "llvm.ve.vl.vsubul.vsvvl" => "__builtin_ve_vl_vsubul_vsvvl", + "llvm.ve.vl.vsubul.vvvl" => "__builtin_ve_vl_vsubul_vvvl", + "llvm.ve.vl.vsubul.vvvmvl" => "__builtin_ve_vl_vsubul_vvvmvl", + "llvm.ve.vl.vsubul.vvvvl" => "__builtin_ve_vl_vsubul_vvvvl", + "llvm.ve.vl.vsubuw.vsvl" => "__builtin_ve_vl_vsubuw_vsvl", + "llvm.ve.vl.vsubuw.vsvmvl" => "__builtin_ve_vl_vsubuw_vsvmvl", + "llvm.ve.vl.vsubuw.vsvvl" => "__builtin_ve_vl_vsubuw_vsvvl", + "llvm.ve.vl.vsubuw.vvvl" => "__builtin_ve_vl_vsubuw_vvvl", + "llvm.ve.vl.vsubuw.vvvmvl" => "__builtin_ve_vl_vsubuw_vvvmvl", + "llvm.ve.vl.vsubuw.vvvvl" => "__builtin_ve_vl_vsubuw_vvvvl", + "llvm.ve.vl.vsuml.vvl" => "__builtin_ve_vl_vsuml_vvl", + "llvm.ve.vl.vsuml.vvml" => "__builtin_ve_vl_vsuml_vvml", + "llvm.ve.vl.vsumwsx.vvl" => "__builtin_ve_vl_vsumwsx_vvl", + "llvm.ve.vl.vsumwsx.vvml" => "__builtin_ve_vl_vsumwsx_vvml", + "llvm.ve.vl.vsumwzx.vvl" => "__builtin_ve_vl_vsumwzx_vvl", + "llvm.ve.vl.vsumwzx.vvml" => "__builtin_ve_vl_vsumwzx_vvml", + "llvm.ve.vl.vxor.vsvl" => "__builtin_ve_vl_vxor_vsvl", + "llvm.ve.vl.vxor.vsvmvl" => "__builtin_ve_vl_vxor_vsvmvl", + "llvm.ve.vl.vxor.vsvvl" => "__builtin_ve_vl_vxor_vsvvl", + "llvm.ve.vl.vxor.vvvl" => "__builtin_ve_vl_vxor_vvvl", + "llvm.ve.vl.vxor.vvvmvl" => "__builtin_ve_vl_vxor_vvvmvl", + "llvm.ve.vl.vxor.vvvvl" => "__builtin_ve_vl_vxor_vvvvl", + "llvm.ve.vl.xorm.MMM" => "__builtin_ve_vl_xorm_MMM", + "llvm.ve.vl.xorm.mmm" => "__builtin_ve_vl_xorm_mmm", // x86 "llvm.x86.3dnow.pavgusb" => "__builtin_ia32_pavgusb", "llvm.x86.3dnow.pf2id" => "__builtin_ia32_pf2id", From ee4755afdbd8123333513931747d295021561b97 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Thu, 9 Jun 2022 21:11:30 -0400 Subject: [PATCH 114/356] Add more SIMD --- Readme.md | 4 ++++ src/base.rs | 12 +++++++++--- src/builder.rs | 8 +++++--- src/intrinsic/llvm.rs | 5 ++++- src/intrinsic/simd.rs | 3 ++- 5 files changed, 24 insertions(+), 8 deletions(-) diff --git a/Readme.md b/Readme.md index fe23a2676966..5bbd29fceba2 100644 --- a/Readme.md +++ b/Readme.md @@ -127,6 +127,10 @@ To get the `rustc` command to run in `gdb`, add the `--verbose` flag to `cargo b * Build the stage2 compiler (`rustup toolchain link debug-current build/x86_64-unknown-linux-gnu/stage2`). * Clean and rebuild the codegen with `debug-current` in the file `rust-toolchain`. +### How to use [mem-trace](https://github.com/antoyo/mem-trace) + +`rustc` needs to be built without `jemalloc` so that `mem-trace` can overload `malloc` since `jemalloc` is linked statically, so a `LD_PRELOAD`-ed library won't a chance to intercept the calls to `malloc`. + ### How to build a cross-compiling libgccjit #### Building libgccjit diff --git a/src/base.rs b/src/base.rs index e4ecbd46f0c4..19c981309d75 100644 --- a/src/base.rs +++ b/src/base.rs @@ -81,11 +81,17 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ // TODO(antoyo): only add the following cli argument if the feature is supported. context.add_command_line_option("-msse2"); context.add_command_line_option("-mavx2"); - context.add_command_line_option("-msha"); - context.add_command_line_option("-mpclmul"); // FIXME(antoyo): the following causes an illegal instruction on vmovdqu64 in std_example on my CPU. // Only add if the CPU supports it. - //context.add_command_line_option("-mavx512f"); + /*context.add_command_line_option("-mavx512f"); + context.add_command_line_option("-msha"); + context.add_command_line_option("-mpclmul"); + context.add_command_line_option("-mfma"); + context.add_command_line_option("-mfma4"); + context.add_command_line_option("-mavx512vpopcntdq"); + context.add_command_line_option("-mavx512vl"); + context.add_command_line_option("-m64"); + context.add_command_line_option("-mbmi");*/ for arg in &tcx.sess.opts.cg.llvm_args { context.add_command_line_option(arg); } diff --git a/src/builder.rs b/src/builder.rs index 3e1f56c183ac..3804a958e691 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -213,7 +213,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let actual_ty = actual_val.get_type(); if expected_ty != actual_ty { - if !actual_ty.is_vector() && !expected_ty.is_vector() && actual_ty.is_integral() && expected_ty.is_integral() && actual_ty.get_size() != expected_ty.get_size() { + if !actual_ty.is_vector() && !expected_ty.is_vector() && actual_ty.is_integral() && expected_ty.is_integral() { self.context.new_cast(None, actual_val, expected_ty) } else if on_stack_param_indices.contains(&index) { @@ -1390,18 +1390,20 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { where F: Fn(RValue<'gcc>, RValue<'gcc>, &'gcc Context<'gcc>) -> RValue<'gcc> { let vector_type = src.get_type().unqualified().dyncast_vector().expect("vector type"); + let element_type = vector_type.get_element_type(); + let mask_element_type = self.type_ix(element_type.get_size() as u64 * 8); let element_count = vector_type.get_num_units(); let mut vector_elements = vec![]; for i in 0..element_count { vector_elements.push(i); } - let mask_type = self.context.new_vector_type(self.int_type, element_count as u64); + let mask_type = self.context.new_vector_type(mask_element_type, element_count as u64); let mut shift = 1; let mut res = src; while shift < element_count { let vector_elements: Vec<_> = vector_elements.iter() - .map(|i| self.context.new_rvalue_from_int(self.int_type, ((i + shift) % element_count) as i32)) + .map(|i| self.context.new_rvalue_from_int(mask_element_type, ((i + shift) % element_count) as i32)) .collect(); let mask = self.context.new_rvalue_from_vector(None, mask_type, &vector_elements); let shifted = self.context.new_rvalue_vector_perm(None, res, res, mask); diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 42cf06c8c7ab..f2faae070284 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -288,7 +288,10 @@ pub fn adjust_intrinsic_return_value<'a, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc, match func_name { "__builtin_ia32_vfmaddss3_round" | "__builtin_ia32_vfmaddsd3_round" => { let zero = builder.context.new_rvalue_zero(builder.int_type); - return_value = builder.context.new_vector_access(None, return_value, zero).to_rvalue(); + #[cfg(feature="master")] + { + return_value = builder.context.new_vector_access(None, return_value, zero).to_rvalue(); + } }, "__builtin_ia32_addcarryx_u64" | "__builtin_ia32_sbb_u64" | "__builtin_ia32_addcarryx_u32" | "__builtin_ia32_sbb_u32" => { // Both llvm.x86.addcarry.32 and llvm.x86.addcarryx.u32 points to the same GCC builtin, diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index bf5d555736ae..8f9862414e60 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -216,7 +216,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let variable = bx.current_func().new_local(None, vector.get_type(), "new_vector"); bx.llbb().add_assignment(None, variable, vector); let lvalue = bx.context.new_vector_access(None, variable.to_rvalue(), index); - // TODO: si simd_insert est constant, utiliser BIT_REF… + // TODO: if simd_insert is constant, use BIT_REF. bx.llbb().add_assignment(None, lvalue, value); return Ok(variable.to_rvalue()); } @@ -252,6 +252,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, return Ok(bx.vector_select(args[0].immediate(), args[1].immediate(), args[2].immediate())); } + #[cfg(feature="master")] if name == sym::simd_cast { require_simd!(ret_ty, "return"); let (out_len, out_elem) = ret_ty.simd_size_and_type(bx.tcx()); From 8ac2af17cafa34cef317b20fa075e15e84bc96e1 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Fri, 10 Jun 2022 08:02:24 -0400 Subject: [PATCH 115/356] Update cross-compiling instructions --- Readme.md | 1 - 1 file changed, 1 deletion(-) diff --git a/Readme.md b/Readme.md index 5bbd29fceba2..aa3626db4ef5 100644 --- a/Readme.md +++ b/Readme.md @@ -146,6 +146,5 @@ To get the `rustc` command to run in `gdb`, add the `--verbose` flag to `cargo b * Since rustc doesn't support this architecture yet, set it back to `TARGET_TRIPLE="mips-unknown-linux-gnu"` (or another target having the same attributes). Alternatively, create a [target specification file](https://book.avr-rust.com/005.1-the-target-specification-json-file.html) (note that the `arch` specified in this file must be supported by the rust compiler). * Set `linker='-Clinker=m68k-linux-gcc'`. * Set the path to the cross-compiling libgccjit in `gcc_path`. - * Disable the 128-bit integer types if the target doesn't support them by using `let i128_type = context.new_type::();` in `context.rs` (same for u128_type). * Comment the line: `context.add_command_line_option("-masm=intel");` in src/base.rs. * (might not be necessary) Disable the compilation of libstd.so (and possibly libcore.so?). From c297534d94e430315199446ab33f19b2692e948a Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Thu, 9 Jun 2022 17:19:09 +0200 Subject: [PATCH 116/356] Add tool to check duplicates between manual and auto code for intrinsics --- tools/check_intrinsics_duplicates.py | 67 ++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 tools/check_intrinsics_duplicates.py diff --git a/tools/check_intrinsics_duplicates.py b/tools/check_intrinsics_duplicates.py new file mode 100644 index 000000000000..c09fb3c759f3 --- /dev/null +++ b/tools/check_intrinsics_duplicates.py @@ -0,0 +1,67 @@ +import sys + + +def check_duplicates(): + auto_content = "" + manual_content = "" + + with open("src/intrinsic/llvm.rs", "r", encoding="utf8") as f: + manual_content = f.read() + with open("src/intrinsic/archs.rs", "r", encoding="utf8") as f: + auto_content = f.read() + + intrinsics_map = {} + for line in auto_content.splitlines(): + line = line.strip() + if not line.startswith('"'): + continue + parts = line.split('"') + if len(parts) != 5: + continue + intrinsics_map[parts[1]] = parts[3] + + if len(intrinsics_map) == 0: + print("No intrinsics found in auto code... Aborting.") + return 1 + print("Found {} intrinsics in auto code".format(len(intrinsics_map))) + errors = [] + lines = manual_content.splitlines() + pos = 0 + found = 0 + while pos < len(lines): + line = lines[pos].strip() + # This is our marker. + if line == "let gcc_name = match name {": + while pos < len(lines): + line = lines[pos].strip() + pos += 1 + if line == "};": + # We're done! + if found == 0: + print("No intrinsics found in manual code even though we found the " + "marker... Aborting...") + return 1 + for error in errors: + print("ERROR => {}".format(error)) + return 1 if len(errors) != 0 else 0 + parts = line.split('"') + if len(parts) != 5: + continue + found += 1 + if parts[1] in intrinsics_map: + if parts[3] != intrinsics_map[parts[1]]: + print("Same intrinsics (`{}` at line {}) but different GCC " + "translations: `{}` != `{}`".format( + parts[1], pos, intrinsics_map[parts[1]], parts[3])) + else: + errors.append("Duplicated intrinsics: `{}` at line {}. Please remove it " + " from manual code".format(parts[1], pos)) + # Weird but whatever... + return 1 if len(errors) != 0 else 0 + pos += 1 + print("No intrinsics found in manual code... Aborting") + return 1 + + +if __name__ == "__main__": + sys.exit(check_duplicates()) From 8d253b9f735ea8fa1b1574bbef09b59037d3970d Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Thu, 9 Jun 2022 17:33:13 +0200 Subject: [PATCH 117/356] Add new workflow to check for duplicated intrinsics --- .github/workflows/ci.yml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 8ebdabe82610..d62ac47dedb6 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -129,3 +129,9 @@ jobs: export RUN_RUNS=2 ./test.sh --release --no-default-features + + duplicates: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - run: python tools/check_intrinsics_duplicates.py From 08df4751b7439ad4598f4cc2429d323f0529cce5 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Thu, 23 Jun 2022 13:27:34 +0200 Subject: [PATCH 118/356] Update extraction of builtins from llvm-project --- tools/generate_intrinsics.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/generate_intrinsics.py b/tools/generate_intrinsics.py index e13e8b146698..49d5969470ef 100644 --- a/tools/generate_intrinsics.py +++ b/tools/generate_intrinsics.py @@ -67,7 +67,7 @@ def extract_instrinsics_from_llvm(llvm_path, intrinsics): pos += 1 if line == "}": break - entries = re.findall('string GCCBuiltinName = "(\\w+)";', content) + entries = re.findall('string ClangBuiltinName = "(\\w+)";', content) current_arch = re.findall('string TargetPrefix = "(\\w+)";', content) if len(entries) == 1 and len(current_arch) == 1: current_arch = current_arch[0] From 48347715fb387916343494ef2c1a45b8c66f0da8 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Thu, 23 Jun 2022 13:28:38 +0200 Subject: [PATCH 119/356] Regen intrinsics --- src/intrinsic/archs.rs | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/intrinsic/archs.rs b/src/intrinsic/archs.rs index 9375f0fc1ad5..3f2db6431053 100644 --- a/src/intrinsic/archs.rs +++ b/src/intrinsic/archs.rs @@ -65,6 +65,7 @@ match name { "llvm.amdgcn.cvt.pknorm.u16" => "__builtin_amdgcn_cvt_pknorm_u16", "llvm.amdgcn.cvt.pkrtz" => "__builtin_amdgcn_cvt_pkrtz", "llvm.amdgcn.dispatch.id" => "__builtin_amdgcn_dispatch_id", + "llvm.amdgcn.ds.add.gs.reg.rtn" => "__builtin_amdgcn_ds_add_gs_reg_rtn", "llvm.amdgcn.ds.bpermute" => "__builtin_amdgcn_ds_bpermute", "llvm.amdgcn.ds.fadd.v2bf16" => "__builtin_amdgcn_ds_atomic_fadd_v2bf16", "llvm.amdgcn.ds.gws.barrier" => "__builtin_amdgcn_ds_gws_barrier", @@ -74,9 +75,13 @@ match name { "llvm.amdgcn.ds.gws.sema.release.all" => "__builtin_amdgcn_ds_gws_sema_release_all", "llvm.amdgcn.ds.gws.sema.v" => "__builtin_amdgcn_ds_gws_sema_v", "llvm.amdgcn.ds.permute" => "__builtin_amdgcn_ds_permute", + "llvm.amdgcn.ds.sub.gs.reg.rtn" => "__builtin_amdgcn_ds_sub_gs_reg_rtn", "llvm.amdgcn.ds.swizzle" => "__builtin_amdgcn_ds_swizzle", "llvm.amdgcn.endpgm" => "__builtin_amdgcn_endpgm", "llvm.amdgcn.fdot2" => "__builtin_amdgcn_fdot2", + "llvm.amdgcn.fdot2.bf16.bf16" => "__builtin_amdgcn_fdot2_bf16_bf16", + "llvm.amdgcn.fdot2.f16.f16" => "__builtin_amdgcn_fdot2_f16_f16", + "llvm.amdgcn.fdot2.f32.bf16" => "__builtin_amdgcn_fdot2_f32_bf16", "llvm.amdgcn.fmed3" => "__builtin_amdgcn_fmed3", "llvm.amdgcn.fmul.legacy" => "__builtin_amdgcn_fmul_legacy", "llvm.amdgcn.groupstaticsize" => "__builtin_amdgcn_groupstaticsize", @@ -167,6 +172,8 @@ match name { "llvm.amdgcn.smfmac.f32.32x32x16.f16" => "__builtin_amdgcn_smfmac_f32_32x32x16_f16", "llvm.amdgcn.smfmac.i32.16x16x64.i8" => "__builtin_amdgcn_smfmac_i32_16x16x64_i8", "llvm.amdgcn.smfmac.i32.32x32x32.i8" => "__builtin_amdgcn_smfmac_i32_32x32x32_i8", + "llvm.amdgcn.sudot4" => "__builtin_amdgcn_sudot4", + "llvm.amdgcn.sudot8" => "__builtin_amdgcn_sudot8", "llvm.amdgcn.udot2" => "__builtin_amdgcn_udot2", "llvm.amdgcn.udot4" => "__builtin_amdgcn_udot4", "llvm.amdgcn.udot8" => "__builtin_amdgcn_udot8", From 2581f7e284a1c1ae484e00c6e5ecf5ba9d7c8e62 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Thu, 23 Jun 2022 13:38:52 +0200 Subject: [PATCH 120/356] Don't generate `*_round_mask*` intrinsics as the GCC equivalent is different --- tools/generate_intrinsics.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/generate_intrinsics.py b/tools/generate_intrinsics.py index e13e8b146698..e2fbee762045 100644 --- a/tools/generate_intrinsics.py +++ b/tools/generate_intrinsics.py @@ -182,6 +182,8 @@ def update_intrinsics(llvm_path, llvmint, llvmint2): for entry in intrinsics[arch]: if entry[2] == True: # if it is a duplicate out.write(' // [DUPLICATE]: "{}" => "{}",\n'.format(entry[0], entry[1])) + elif "_round_mask" in entry[1]: + out.write(' // [INVALID CONVERSION]: "{}" => "{}",\n'.format(entry[0], entry[1])) else: out.write(' "{}" => "{}",\n'.format(entry[0], entry[1])) out.write(' _ => unimplemented!("***** unsupported LLVM intrinsic {}", name),\n') From 94b345705ac48479ad92b736c0e0e1a56f7563d7 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Thu, 23 Jun 2022 13:39:24 +0200 Subject: [PATCH 121/356] Regen without invalid conversion intrinsics --- src/intrinsic/archs.rs | 88 +++++++++++++++++++++--------------------- 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/src/intrinsic/archs.rs b/src/intrinsic/archs.rs index 9375f0fc1ad5..21a21719e615 100644 --- a/src/intrinsic/archs.rs +++ b/src/intrinsic/archs.rs @@ -5988,8 +5988,8 @@ match name { "llvm.x86.avx512.mask.add.ps.128" => "__builtin_ia32_addps128_mask", "llvm.x86.avx512.mask.add.ps.256" => "__builtin_ia32_addps256_mask", "llvm.x86.avx512.mask.add.ps.512" => "__builtin_ia32_addps512_mask", - "llvm.x86.avx512.mask.add.sd.round" => "__builtin_ia32_addsd_round_mask", - "llvm.x86.avx512.mask.add.ss.round" => "__builtin_ia32_addss_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.add.sd.round" => "__builtin_ia32_addsd_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.add.ss.round" => "__builtin_ia32_addss_round_mask", "llvm.x86.avx512.mask.and.pd.128" => "__builtin_ia32_andpd128_mask", "llvm.x86.avx512.mask.and.pd.256" => "__builtin_ia32_andpd256_mask", "llvm.x86.avx512.mask.and.pd.512" => "__builtin_ia32_andpd512_mask", @@ -6103,8 +6103,8 @@ match name { "llvm.x86.avx512.mask.cvtqq2ps.128" => "__builtin_ia32_cvtqq2ps128_mask", "llvm.x86.avx512.mask.cvtqq2ps.256" => "__builtin_ia32_cvtqq2ps256_mask", "llvm.x86.avx512.mask.cvtqq2ps.512" => "__builtin_ia32_cvtqq2ps512_mask", - "llvm.x86.avx512.mask.cvtsd2ss.round" => "__builtin_ia32_cvtsd2ss_round_mask", - "llvm.x86.avx512.mask.cvtss2sd.round" => "__builtin_ia32_cvtss2sd_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.cvtsd2ss.round" => "__builtin_ia32_cvtsd2ss_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.cvtss2sd.round" => "__builtin_ia32_cvtss2sd_round_mask", "llvm.x86.avx512.mask.cvttpd2dq.128" => "__builtin_ia32_cvttpd2dq128_mask", "llvm.x86.avx512.mask.cvttpd2dq.256" => "__builtin_ia32_cvttpd2dq256_mask", "llvm.x86.avx512.mask.cvttpd2dq.512" => "__builtin_ia32_cvttpd2dq512_mask", @@ -6150,8 +6150,8 @@ match name { "llvm.x86.avx512.mask.div.ps.128" => "__builtin_ia32_divps_mask", "llvm.x86.avx512.mask.div.ps.256" => "__builtin_ia32_divps256_mask", "llvm.x86.avx512.mask.div.ps.512" => "__builtin_ia32_divps512_mask", - "llvm.x86.avx512.mask.div.sd.round" => "__builtin_ia32_divsd_round_mask", - "llvm.x86.avx512.mask.div.ss.round" => "__builtin_ia32_divss_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.div.sd.round" => "__builtin_ia32_divsd_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.div.ss.round" => "__builtin_ia32_divss_round_mask", "llvm.x86.avx512.mask.expand.d.128" => "__builtin_ia32_expandsi128_mask", "llvm.x86.avx512.mask.expand.d.256" => "__builtin_ia32_expandsi256_mask", "llvm.x86.avx512.mask.expand.d.512" => "__builtin_ia32_expandsi512_mask", @@ -6198,16 +6198,16 @@ match name { "llvm.x86.avx512.mask.getexp.ps.128" => "__builtin_ia32_getexpps128_mask", "llvm.x86.avx512.mask.getexp.ps.256" => "__builtin_ia32_getexpps256_mask", "llvm.x86.avx512.mask.getexp.ps.512" => "__builtin_ia32_getexpps512_mask", - "llvm.x86.avx512.mask.getexp.sd" => "__builtin_ia32_getexpsd128_round_mask", - "llvm.x86.avx512.mask.getexp.ss" => "__builtin_ia32_getexpss128_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.getexp.sd" => "__builtin_ia32_getexpsd128_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.getexp.ss" => "__builtin_ia32_getexpss128_round_mask", "llvm.x86.avx512.mask.getmant.pd.128" => "__builtin_ia32_getmantpd128_mask", "llvm.x86.avx512.mask.getmant.pd.256" => "__builtin_ia32_getmantpd256_mask", "llvm.x86.avx512.mask.getmant.pd.512" => "__builtin_ia32_getmantpd512_mask", "llvm.x86.avx512.mask.getmant.ps.128" => "__builtin_ia32_getmantps128_mask", "llvm.x86.avx512.mask.getmant.ps.256" => "__builtin_ia32_getmantps256_mask", "llvm.x86.avx512.mask.getmant.ps.512" => "__builtin_ia32_getmantps512_mask", - "llvm.x86.avx512.mask.getmant.sd" => "__builtin_ia32_getmantsd_round_mask", - "llvm.x86.avx512.mask.getmant.ss" => "__builtin_ia32_getmantss_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.getmant.sd" => "__builtin_ia32_getmantsd_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.getmant.ss" => "__builtin_ia32_getmantss_round_mask", "llvm.x86.avx512.mask.insertf32x4.256" => "__builtin_ia32_insertf32x4_256_mask", "llvm.x86.avx512.mask.insertf32x4.512" => "__builtin_ia32_insertf32x4_mask", "llvm.x86.avx512.mask.insertf32x8.512" => "__builtin_ia32_insertf32x8_mask", @@ -6232,16 +6232,16 @@ match name { "llvm.x86.avx512.mask.max.ps.128" => "__builtin_ia32_maxps_mask", "llvm.x86.avx512.mask.max.ps.256" => "__builtin_ia32_maxps256_mask", "llvm.x86.avx512.mask.max.ps.512" => "__builtin_ia32_maxps512_mask", - "llvm.x86.avx512.mask.max.sd.round" => "__builtin_ia32_maxsd_round_mask", - "llvm.x86.avx512.mask.max.ss.round" => "__builtin_ia32_maxss_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.max.sd.round" => "__builtin_ia32_maxsd_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.max.ss.round" => "__builtin_ia32_maxss_round_mask", "llvm.x86.avx512.mask.min.pd.128" => "__builtin_ia32_minpd_mask", "llvm.x86.avx512.mask.min.pd.256" => "__builtin_ia32_minpd256_mask", "llvm.x86.avx512.mask.min.pd.512" => "__builtin_ia32_minpd512_mask", "llvm.x86.avx512.mask.min.ps.128" => "__builtin_ia32_minps_mask", "llvm.x86.avx512.mask.min.ps.256" => "__builtin_ia32_minps256_mask", "llvm.x86.avx512.mask.min.ps.512" => "__builtin_ia32_minps512_mask", - "llvm.x86.avx512.mask.min.sd.round" => "__builtin_ia32_minsd_round_mask", - "llvm.x86.avx512.mask.min.ss.round" => "__builtin_ia32_minss_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.min.sd.round" => "__builtin_ia32_minsd_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.min.ss.round" => "__builtin_ia32_minss_round_mask", "llvm.x86.avx512.mask.move.sd" => "__builtin_ia32_movsd_mask", "llvm.x86.avx512.mask.move.ss" => "__builtin_ia32_movss_mask", "llvm.x86.avx512.mask.mul.pd.128" => "__builtin_ia32_mulpd_mask", @@ -6250,8 +6250,8 @@ match name { "llvm.x86.avx512.mask.mul.ps.128" => "__builtin_ia32_mulps_mask", "llvm.x86.avx512.mask.mul.ps.256" => "__builtin_ia32_mulps256_mask", "llvm.x86.avx512.mask.mul.ps.512" => "__builtin_ia32_mulps512_mask", - "llvm.x86.avx512.mask.mul.sd.round" => "__builtin_ia32_mulsd_round_mask", - "llvm.x86.avx512.mask.mul.ss.round" => "__builtin_ia32_mulss_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.mul.sd.round" => "__builtin_ia32_mulsd_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.mul.ss.round" => "__builtin_ia32_mulss_round_mask", "llvm.x86.avx512.mask.or.pd.128" => "__builtin_ia32_orpd128_mask", "llvm.x86.avx512.mask.or.pd.256" => "__builtin_ia32_orpd256_mask", "llvm.x86.avx512.mask.or.pd.512" => "__builtin_ia32_orpd512_mask", @@ -6736,8 +6736,8 @@ match name { "llvm.x86.avx512.mask.range.ps.128" => "__builtin_ia32_rangeps128_mask", "llvm.x86.avx512.mask.range.ps.256" => "__builtin_ia32_rangeps256_mask", "llvm.x86.avx512.mask.range.ps.512" => "__builtin_ia32_rangeps512_mask", - "llvm.x86.avx512.mask.range.sd" => "__builtin_ia32_rangesd128_round_mask", - "llvm.x86.avx512.mask.range.ss" => "__builtin_ia32_rangess128_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.range.sd" => "__builtin_ia32_rangesd128_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.range.ss" => "__builtin_ia32_rangess128_round_mask", "llvm.x86.avx512.mask.reduce.pd.128" => "__builtin_ia32_reducepd128_mask", "llvm.x86.avx512.mask.reduce.pd.256" => "__builtin_ia32_reducepd256_mask", "llvm.x86.avx512.mask.reduce.pd.512" => "__builtin_ia32_reducepd512_mask", @@ -6752,16 +6752,16 @@ match name { "llvm.x86.avx512.mask.rndscale.ps.128" => "__builtin_ia32_rndscaleps_128_mask", "llvm.x86.avx512.mask.rndscale.ps.256" => "__builtin_ia32_rndscaleps_256_mask", "llvm.x86.avx512.mask.rndscale.ps.512" => "__builtin_ia32_rndscaleps_mask", - "llvm.x86.avx512.mask.rndscale.sd" => "__builtin_ia32_rndscalesd_round_mask", - "llvm.x86.avx512.mask.rndscale.ss" => "__builtin_ia32_rndscaless_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.rndscale.sd" => "__builtin_ia32_rndscalesd_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.rndscale.ss" => "__builtin_ia32_rndscaless_round_mask", "llvm.x86.avx512.mask.scalef.pd.128" => "__builtin_ia32_scalefpd128_mask", "llvm.x86.avx512.mask.scalef.pd.256" => "__builtin_ia32_scalefpd256_mask", "llvm.x86.avx512.mask.scalef.pd.512" => "__builtin_ia32_scalefpd512_mask", "llvm.x86.avx512.mask.scalef.ps.128" => "__builtin_ia32_scalefps128_mask", "llvm.x86.avx512.mask.scalef.ps.256" => "__builtin_ia32_scalefps256_mask", "llvm.x86.avx512.mask.scalef.ps.512" => "__builtin_ia32_scalefps512_mask", - "llvm.x86.avx512.mask.scalef.sd" => "__builtin_ia32_scalefsd_round_mask", - "llvm.x86.avx512.mask.scalef.ss" => "__builtin_ia32_scalefss_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.scalef.sd" => "__builtin_ia32_scalefsd_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.scalef.ss" => "__builtin_ia32_scalefss_round_mask", "llvm.x86.avx512.mask.shuf.f32x4" => "__builtin_ia32_shuf_f32x4_mask", "llvm.x86.avx512.mask.shuf.f32x4.256" => "__builtin_ia32_shuf_f32x4_256_mask", "llvm.x86.avx512.mask.shuf.f64x2" => "__builtin_ia32_shuf_f64x2_mask", @@ -6782,8 +6782,8 @@ match name { "llvm.x86.avx512.mask.sqrt.ps.128" => "__builtin_ia32_sqrtps128_mask", "llvm.x86.avx512.mask.sqrt.ps.256" => "__builtin_ia32_sqrtps256_mask", "llvm.x86.avx512.mask.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask", - "llvm.x86.avx512.mask.sqrt.sd" => "__builtin_ia32_sqrtsd_round_mask", - "llvm.x86.avx512.mask.sqrt.ss" => "__builtin_ia32_sqrtss_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.sqrt.sd" => "__builtin_ia32_sqrtsd_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.sqrt.ss" => "__builtin_ia32_sqrtss_round_mask", "llvm.x86.avx512.mask.store.ss" => "__builtin_ia32_storess_mask", "llvm.x86.avx512.mask.storeu.d.512" => "__builtin_ia32_storedqusi512_mask", "llvm.x86.avx512.mask.storeu.pd.512" => "__builtin_ia32_storeupd512_mask", @@ -6795,8 +6795,8 @@ match name { "llvm.x86.avx512.mask.sub.ps.128" => "__builtin_ia32_subps128_mask", "llvm.x86.avx512.mask.sub.ps.256" => "__builtin_ia32_subps256_mask", "llvm.x86.avx512.mask.sub.ps.512" => "__builtin_ia32_subps512_mask", - "llvm.x86.avx512.mask.sub.sd.round" => "__builtin_ia32_subsd_round_mask", - "llvm.x86.avx512.mask.sub.ss.round" => "__builtin_ia32_subss_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.sub.sd.round" => "__builtin_ia32_subsd_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.mask.sub.ss.round" => "__builtin_ia32_subss_round_mask", "llvm.x86.avx512.mask.valign.d.128" => "__builtin_ia32_alignd128_mask", "llvm.x86.avx512.mask.valign.d.256" => "__builtin_ia32_alignd256_mask", "llvm.x86.avx512.mask.valign.d.512" => "__builtin_ia32_alignd512_mask", @@ -7114,9 +7114,9 @@ match name { "llvm.x86.avx512.rcp14.ss" => "__builtin_ia32_rcp14ss_mask", "llvm.x86.avx512.rcp28.pd" => "__builtin_ia32_rcp28pd_mask", "llvm.x86.avx512.rcp28.ps" => "__builtin_ia32_rcp28ps_mask", - "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_round_mask", // [DUPLICATE]: "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_mask", - "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_round_mask", // [DUPLICATE]: "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_mask", "llvm.x86.avx512.rndscale.sd" => "__builtin_ia32_rndscalesd", "llvm.x86.avx512.rndscale.ss" => "__builtin_ia32_rndscaless", @@ -7130,9 +7130,9 @@ match name { "llvm.x86.avx512.rsqrt14.ss" => "__builtin_ia32_rsqrt14ss_mask", "llvm.x86.avx512.rsqrt28.pd" => "__builtin_ia32_rsqrt28pd_mask", "llvm.x86.avx512.rsqrt28.ps" => "__builtin_ia32_rsqrt28ps_mask", - "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_round_mask", // [DUPLICATE]: "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_mask", - "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_round_mask", // [DUPLICATE]: "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_mask", "llvm.x86.avx512.scatter.dpd.512" => "__builtin_ia32_scattersiv8df", "llvm.x86.avx512.scatter.dpi.512" => "__builtin_ia32_scattersiv16si", @@ -7230,21 +7230,21 @@ match name { "llvm.x86.avx512bf16.dpbf16ps.512" => "__builtin_ia32_dpbf16ps_512", "llvm.x86.avx512fp16.add.ph.512" => "__builtin_ia32_addph512", "llvm.x86.avx512fp16.div.ph.512" => "__builtin_ia32_divph512", - "llvm.x86.avx512fp16.mask.add.sh.round" => "__builtin_ia32_addsh_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.add.sh.round" => "__builtin_ia32_addsh_round_mask", "llvm.x86.avx512fp16.mask.cmp.sh" => "__builtin_ia32_cmpsh_mask", - "llvm.x86.avx512fp16.mask.div.sh.round" => "__builtin_ia32_divsh_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.div.sh.round" => "__builtin_ia32_divsh_round_mask", "llvm.x86.avx512fp16.mask.fpclass.sh" => "__builtin_ia32_fpclasssh_mask", "llvm.x86.avx512fp16.mask.getexp.ph.128" => "__builtin_ia32_getexpph128_mask", "llvm.x86.avx512fp16.mask.getexp.ph.256" => "__builtin_ia32_getexpph256_mask", "llvm.x86.avx512fp16.mask.getexp.ph.512" => "__builtin_ia32_getexpph512_mask", - "llvm.x86.avx512fp16.mask.getexp.sh" => "__builtin_ia32_getexpsh128_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.getexp.sh" => "__builtin_ia32_getexpsh128_round_mask", "llvm.x86.avx512fp16.mask.getmant.ph.128" => "__builtin_ia32_getmantph128_mask", "llvm.x86.avx512fp16.mask.getmant.ph.256" => "__builtin_ia32_getmantph256_mask", "llvm.x86.avx512fp16.mask.getmant.ph.512" => "__builtin_ia32_getmantph512_mask", - "llvm.x86.avx512fp16.mask.getmant.sh" => "__builtin_ia32_getmantsh_round_mask", - "llvm.x86.avx512fp16.mask.max.sh.round" => "__builtin_ia32_maxsh_round_mask", - "llvm.x86.avx512fp16.mask.min.sh.round" => "__builtin_ia32_minsh_round_mask", - "llvm.x86.avx512fp16.mask.mul.sh.round" => "__builtin_ia32_mulsh_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.getmant.sh" => "__builtin_ia32_getmantsh_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.max.sh.round" => "__builtin_ia32_maxsh_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.min.sh.round" => "__builtin_ia32_minsh_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.mul.sh.round" => "__builtin_ia32_mulsh_round_mask", "llvm.x86.avx512fp16.mask.rcp.ph.128" => "__builtin_ia32_rcpph128_mask", "llvm.x86.avx512fp16.mask.rcp.ph.256" => "__builtin_ia32_rcpph256_mask", "llvm.x86.avx512fp16.mask.rcp.ph.512" => "__builtin_ia32_rcpph512_mask", @@ -7256,7 +7256,7 @@ match name { "llvm.x86.avx512fp16.mask.rndscale.ph.128" => "__builtin_ia32_rndscaleph_128_mask", "llvm.x86.avx512fp16.mask.rndscale.ph.256" => "__builtin_ia32_rndscaleph_256_mask", "llvm.x86.avx512fp16.mask.rndscale.ph.512" => "__builtin_ia32_rndscaleph_mask", - "llvm.x86.avx512fp16.mask.rndscale.sh" => "__builtin_ia32_rndscalesh_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.rndscale.sh" => "__builtin_ia32_rndscalesh_round_mask", "llvm.x86.avx512fp16.mask.rsqrt.ph.128" => "__builtin_ia32_rsqrtph128_mask", "llvm.x86.avx512fp16.mask.rsqrt.ph.256" => "__builtin_ia32_rsqrtph256_mask", "llvm.x86.avx512fp16.mask.rsqrt.ph.512" => "__builtin_ia32_rsqrtph512_mask", @@ -7264,8 +7264,8 @@ match name { "llvm.x86.avx512fp16.mask.scalef.ph.128" => "__builtin_ia32_scalefph128_mask", "llvm.x86.avx512fp16.mask.scalef.ph.256" => "__builtin_ia32_scalefph256_mask", "llvm.x86.avx512fp16.mask.scalef.ph.512" => "__builtin_ia32_scalefph512_mask", - "llvm.x86.avx512fp16.mask.scalef.sh" => "__builtin_ia32_scalefsh_round_mask", - "llvm.x86.avx512fp16.mask.sub.sh.round" => "__builtin_ia32_subsh_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.scalef.sh" => "__builtin_ia32_scalefsh_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.sub.sh.round" => "__builtin_ia32_subsh_round_mask", "llvm.x86.avx512fp16.mask.vcvtdq2ph.128" => "__builtin_ia32_vcvtdq2ph128_mask", "llvm.x86.avx512fp16.mask.vcvtpd2ph.128" => "__builtin_ia32_vcvtpd2ph128_mask", "llvm.x86.avx512fp16.mask.vcvtpd2ph.256" => "__builtin_ia32_vcvtpd2ph256_mask", @@ -7299,10 +7299,10 @@ match name { "llvm.x86.avx512fp16.mask.vcvtps2phx.512" => "__builtin_ia32_vcvtps2phx512_mask", "llvm.x86.avx512fp16.mask.vcvtqq2ph.128" => "__builtin_ia32_vcvtqq2ph128_mask", "llvm.x86.avx512fp16.mask.vcvtqq2ph.256" => "__builtin_ia32_vcvtqq2ph256_mask", - "llvm.x86.avx512fp16.mask.vcvtsd2sh.round" => "__builtin_ia32_vcvtsd2sh_round_mask", - "llvm.x86.avx512fp16.mask.vcvtsh2sd.round" => "__builtin_ia32_vcvtsh2sd_round_mask", - "llvm.x86.avx512fp16.mask.vcvtsh2ss.round" => "__builtin_ia32_vcvtsh2ss_round_mask", - "llvm.x86.avx512fp16.mask.vcvtss2sh.round" => "__builtin_ia32_vcvtss2sh_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.vcvtsd2sh.round" => "__builtin_ia32_vcvtsd2sh_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.vcvtsh2sd.round" => "__builtin_ia32_vcvtsh2sd_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.vcvtsh2ss.round" => "__builtin_ia32_vcvtsh2ss_round_mask", + // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.vcvtss2sh.round" => "__builtin_ia32_vcvtss2sh_round_mask", "llvm.x86.avx512fp16.mask.vcvttph2dq.128" => "__builtin_ia32_vcvttph2dq128_mask", "llvm.x86.avx512fp16.mask.vcvttph2dq.256" => "__builtin_ia32_vcvttph2dq256_mask", "llvm.x86.avx512fp16.mask.vcvttph2dq.512" => "__builtin_ia32_vcvttph2dq512_mask", From 4dc0bbf40ec60d895a1167257b2ea18d04a616ed Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Wed, 22 Jun 2022 21:10:47 -0400 Subject: [PATCH 122/356] Add dummy fast math implementation --- src/builder.rs | 50 ++++++++++++++++++++++++++++++++++++++++---------- test.sh | 1 + 2 files changed, 41 insertions(+), 10 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index 3804a958e691..9f6ffb9a610f 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -530,6 +530,31 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn frem(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { + // TODO(antoyo): add check in libgccjit since using the binary operator % causes the following error: + // during RTL pass: expand + // libgccjit.so: error: in expmed_mode_index, at expmed.h:240 + // 0x7f0101d58dc6 expmed_mode_index + // ../../../gcc/gcc/expmed.h:240 + // 0x7f0101d58e35 expmed_op_cost_ptr + // ../../../gcc/gcc/expmed.h:262 + // 0x7f0101d594a1 sdiv_cost_ptr + // ../../../gcc/gcc/expmed.h:531 + // 0x7f0101d594f3 sdiv_cost + // ../../../gcc/gcc/expmed.h:549 + // 0x7f0101d6af7e expand_divmod(int, tree_code, machine_mode, rtx_def*, rtx_def*, rtx_def*, int, optab_methods) + // ../../../gcc/gcc/expmed.cc:4356 + // 0x7f0101d94f9e expand_expr_divmod + // ../../../gcc/gcc/expr.cc:8929 + // 0x7f0101d97a26 expand_expr_real_2(separate_ops*, rtx_def*, machine_mode, expand_modifier) + // ../../../gcc/gcc/expr.cc:9566 + // 0x7f0101bef6ef expand_gimple_stmt_1 + // ../../../gcc/gcc/cfgexpand.cc:3967 + // 0x7f0101bef910 expand_gimple_stmt + // ../../../gcc/gcc/cfgexpand.cc:4028 + // 0x7f0101bf6ee7 expand_gimple_basic_block + // ../../../gcc/gcc/cfgexpand.cc:6069 + // 0x7f0101bf9194 execute + // ../../../gcc/gcc/cfgexpand.cc:6795 if a.get_type().is_compatible_with(self.cx.float_type) { let fmodf = self.context.get_builtin_function("fmodf"); // FIXME(antoyo): this seems to produce the wrong result. @@ -604,24 +629,29 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { a * b } - fn fadd_fast(&mut self, _lhs: RValue<'gcc>, _rhs: RValue<'gcc>) -> RValue<'gcc> { - unimplemented!(); + fn fadd_fast(&mut self, lhs: RValue<'gcc>, rhs: RValue<'gcc>) -> RValue<'gcc> { + // NOTE: it seems like we cannot enable fast-mode for a single operation in GCC. + lhs + rhs } - fn fsub_fast(&mut self, _lhs: RValue<'gcc>, _rhs: RValue<'gcc>) -> RValue<'gcc> { - unimplemented!(); + fn fsub_fast(&mut self, lhs: RValue<'gcc>, rhs: RValue<'gcc>) -> RValue<'gcc> { + // NOTE: it seems like we cannot enable fast-mode for a single operation in GCC. + lhs - rhs } - fn fmul_fast(&mut self, _lhs: RValue<'gcc>, _rhs: RValue<'gcc>) -> RValue<'gcc> { - unimplemented!(); + fn fmul_fast(&mut self, lhs: RValue<'gcc>, rhs: RValue<'gcc>) -> RValue<'gcc> { + // NOTE: it seems like we cannot enable fast-mode for a single operation in GCC. + lhs * rhs } - fn fdiv_fast(&mut self, _lhs: RValue<'gcc>, _rhs: RValue<'gcc>) -> RValue<'gcc> { - unimplemented!(); + fn fdiv_fast(&mut self, lhs: RValue<'gcc>, rhs: RValue<'gcc>) -> RValue<'gcc> { + // NOTE: it seems like we cannot enable fast-mode for a single operation in GCC. + lhs / rhs } - fn frem_fast(&mut self, _lhs: RValue<'gcc>, _rhs: RValue<'gcc>) -> RValue<'gcc> { - unimplemented!(); + fn frem_fast(&mut self, lhs: RValue<'gcc>, rhs: RValue<'gcc>) -> RValue<'gcc> { + // NOTE: it seems like we cannot enable fast-mode for a single operation in GCC. + self.frem(lhs, rhs) } fn checked_binop(&mut self, oop: OverflowOp, typ: Ty<'_>, lhs: Self::Value, rhs: Self::Value) -> (Self::Value, Self::Value) { diff --git a/test.sh b/test.sh index 8b390f95a4b9..f2721c9c92c6 100755 --- a/test.sh +++ b/test.sh @@ -265,6 +265,7 @@ EOF for test in $(rg --files-with-matches "catch_unwind|should_panic|thread|lto" src/test/ui); do rm $test done + git checkout src/test/ui/lto/auxiliary/dylib.rs git checkout src/test/ui/type-alias-impl-trait/auxiliary/cross_crate_ice.rs git checkout src/test/ui/type-alias-impl-trait/auxiliary/cross_crate_ice2.rs From f7a3dffc0b755c7e4791656238bb862c118747cb Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Fri, 24 Jun 2022 17:25:09 +0200 Subject: [PATCH 123/356] Add missing intrinsics conversions for ignored invalid LLVM intrinsics --- src/intrinsic/llvm.rs | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index f2faae070284..f623bc5fb10c 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -618,6 +618,25 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.avx512.mask.div.sd.round" => "__builtin_ia32_divsd_mask_round", "llvm.x86.avx512.mask.cvtss2sd.round" => "__builtin_ia32_cvtss2sd_mask_round", "llvm.x86.avx512.mask.cvtsd2ss.round" => "__builtin_ia32_cvtsd2ss_mask_round", + "llvm.x86.avx512.mask.range.ss" => "__builtin_ia32_rangess128_mask_round", + "llvm.x86.avx512.mask.range.sd" => "__builtin_ia32_rangesd128_mask_round", + "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_mask_round", + "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_mask_round", + "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_mask_round", + "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_mask_round", + "llvm.x86.avx512fp16.mask.add.sh.round" => "__builtin_ia32_addsh_mask_round", + "llvm.x86.avx512fp16.mask.div.sh.round" => "__builtin_ia32_divsh_mask_round", + "llvm.x86.avx512fp16.mask.getmant.sh" => "__builtin_ia32_getmantsh_mask_round", + "llvm.x86.avx512fp16.mask.max.sh.round" => "__builtin_ia32_maxsh_mask_round", + "llvm.x86.avx512fp16.mask.min.sh.round" => "__builtin_ia32_minsh_mask_round", + "llvm.x86.avx512fp16.mask.mul.sh.round" => "__builtin_ia32_mulsh_mask_round", + "llvm.x86.avx512fp16.mask.rndscale.sh" => "__builtin_ia32_rndscalesh_mask_round", + "llvm.x86.avx512fp16.mask.scalef.sh" => "__builtin_ia32_scalefsh_mask_round", + "llvm.x86.avx512fp16.mask.sub.sh.round" => "__builtin_ia32_subsh_mask_round", + "llvm.x86.avx512fp16.mask.vcvtsd2sh.round" => "__builtin_ia32_vcvtsd2sh_mask_round", + "llvm.x86.avx512fp16.mask.vcvtsh2sd.round" => "__builtin_ia32_vcvtsh2sd_mask_round", + "llvm.x86.avx512fp16.mask.vcvtsh2ss.round" => "__builtin_ia32_vcvtsh2ss_mask_round", + "llvm.x86.avx512fp16.mask.vcvtss2sh.round" => "__builtin_ia32_vcvtss2sh_mask_round", "llvm.x86.aesni.aesenc.256" => "__builtin_ia32_vaesenc_v32qi", "llvm.x86.aesni.aesenclast.256" => "__builtin_ia32_vaesenclast_v32qi", "llvm.x86.aesni.aesdec.256" => "__builtin_ia32_vaesdec_v32qi", From 5e6a3be56c60935e31dc71a93e7166ea4d427a82 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Fri, 24 Jun 2022 21:47:37 +0200 Subject: [PATCH 124/356] Merge duplicated rules --- test.sh | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/test.sh b/test.sh index 8b390f95a4b9..9e69d14c0626 100755 --- a/test.sh +++ b/test.sh @@ -24,6 +24,7 @@ while [[ $# -gt 0 ]]; do case $1 in --release) codegen_channel=release + channel="release" shift ;; --release-sysroot) @@ -40,10 +41,6 @@ while [[ $# -gt 0 ]]; do flags="$flags --features $1" shift ;; - --release) - channel="release" - shift - ;; "--test-rustc") func=test_rustc shift From 161ccb36b1c1c6a98af153637c7ea244635c8e90 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Fri, 24 Jun 2022 19:27:53 -0400 Subject: [PATCH 125/356] Disable UI tests that fail on the rustc side --- test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test.sh b/test.sh index f2721c9c92c6..635641980d74 100755 --- a/test.sh +++ b/test.sh @@ -261,7 +261,7 @@ EOF git checkout -- src/test/ui/issues/auxiliary/issue-3136-a.rs # contains //~ERROR, but shouldn't be removed - rm -r src/test/ui/{abi*,extern/,panic-runtime/,panics/,unsized-locals/,proc-macro/,threads-sendsync/,thinlto/,borrowck/,test*,*lto*.rs} || true + rm -r src/test/ui/{abi*,extern/,panic-runtime/,panics/,unsized-locals/,proc-macro/,threads-sendsync/,thinlto/,borrowck/,chalkify/bugs/,test*,*lto*.rs,consts/const-float-bits-reject-conv.rs,consts/issue-miri-1910.rs} || true for test in $(rg --files-with-matches "catch_unwind|should_panic|thread|lto" src/test/ui); do rm $test done From ed37ed7cb8dcb2855cd95166d45b753ffab112dc Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Fri, 24 Jun 2022 21:47:55 +0200 Subject: [PATCH 126/356] Simplify github actions conf --- .github/workflows/ci.yml | 52 +++++++++++++++++++++++++--------------- test.sh | 29 +++++++++++++++------- 2 files changed, 53 insertions(+), 28 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index d62ac47dedb6..3dbf8d922152 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -11,7 +11,10 @@ jobs: strategy: fail-fast: false matrix: - libgccjit_version: ["libgccjit.so", "libgccjit_without_int128.so", "libgccjit12.so"] + libgccjit_version: + - { gcc: "libgccjit.so", extra: "" } + - { gcc: "libgccjit_without_int128.so", extra: "" } + - { gcc: "libgccjit12.so", extra: "--no-default-features" } steps: - uses: actions/checkout@v2 @@ -28,7 +31,7 @@ jobs: uses: dawidd6/action-download-artifact@v2 with: workflow: main.yml - name: ${{ matrix.libgccjit_version }} + name: ${{ matrix.libgccjit_version.gcc }} path: gcc-build repo: antoyo/gcc search_artifacts: true # Because, instead, the action only check the last job ran and that won't work since we want multiple artifacts. @@ -78,19 +81,10 @@ jobs: key: ${{ runner.os }}-cargo-build-target-${{ hashFiles('rust-toolchain') }} - name: Build - if: matrix.libgccjit_version != 'libgccjit12.so' run: | ./prepare_build.sh - ./build.sh - cargo test - ./clean_all.sh - - - name: Build - if: matrix.libgccjit_version == 'libgccjit12.so' - run: | - ./prepare_build.sh - ./build.sh --no-default-features - cargo test --no-default-features + ./build.sh ${{ matrix.libgccjit_version.extra }} + cargo test ${{ matrix.libgccjit_version.extra }} ./clean_all.sh - name: Prepare dependencies @@ -106,8 +100,7 @@ jobs: command: build args: --release - - name: Test - if: matrix.libgccjit_version != 'libgccjit12.so' + - name: Test std_tests run: | # Enable backtraces for easier debugging export RUST_BACKTRACE=1 @@ -116,10 +109,9 @@ jobs: export COMPILE_RUNS=2 export RUN_RUNS=2 - ./test.sh --release + ./test.sh --release --clean --build-sysroot --std-tests ${{ matrix.libgccjit_version.extra }} - - name: Test - if: matrix.libgccjit_version == 'libgccjit12.so' + - name: Test test_libcore run: | # Enable backtraces for easier debugging export RUST_BACKTRACE=1 @@ -128,7 +120,29 @@ jobs: export COMPILE_RUNS=2 export RUN_RUNS=2 - ./test.sh --release --no-default-features + ./test.sh --release --test-libcore ${{ matrix.libgccjit_version.extra }} + + - name: Test extended_sysroot_tests + run: | + # Enable backtraces for easier debugging + export RUST_BACKTRACE=1 + + # Reduce amount of benchmark runs as they are slow + export COMPILE_RUNS=2 + export RUN_RUNS=2 + + ./test.sh --release --extended-tests ${{ matrix.libgccjit_version.extra }} + + - name: Test test_rustc + run: | + # Enable backtraces for easier debugging + export RUST_BACKTRACE=1 + + # Reduce amount of benchmark runs as they are slow + export COMPILE_RUNS=2 + export RUN_RUNS=2 + + ./test.sh --release --test-rustc ${{ matrix.libgccjit_version.extra }} duplicates: runs-on: ubuntu-latest diff --git a/test.sh b/test.sh index 9e69d14c0626..b4d10fa6e4d2 100755 --- a/test.sh +++ b/test.sh @@ -17,7 +17,7 @@ export LIBRARY_PATH="$GCC_PATH" flags= gcc_master_branch=1 channel="debug" -func=all +funcs=() build_only=0 while [[ $# -gt 0 ]]; do @@ -42,32 +42,36 @@ while [[ $# -gt 0 ]]; do shift ;; "--test-rustc") - func=test_rustc + funcs+=(test_rustc) shift ;; "--test-libcore") - func=test_libcore + funcs+=(test_libcore) shift ;; "--clean-ui-tests") - func=clean_ui_tests + funcs+=(clean_ui_tests) + shift + ;; + "--clean") + funcs+=(clean) shift ;; "--std-tests") - func=std_tests + funcs+=(std_tests) shift ;; "--extended-tests") - func=extended_sysroot_tests + funcs+=(extended_sysroot_tests) shift ;; "--build-sysroot") - func=build_sysroot + funcs+=(build_sysroot) shift ;; "--build") @@ -84,7 +88,6 @@ done if [[ $channel == "release" ]]; then export CHANNEL='release' CARGO_INCREMENTAL=1 cargo rustc --release $flags - shift else echo $LD_LIBRARY_PATH export CHANNEL='debug' @@ -92,6 +95,7 @@ else fi if (( $build_only == 1 )); then + echo "Since it's `build-only`, exiting..." exit fi @@ -285,4 +289,11 @@ function all() { test_rustc } -$func +if [ ${#funcs[@]} -eq 0 ]; then + echo "No command passed, running `--all`..." + all +else + for t in ${funcs[@]}; do + $t + done +fi From 9a42e6b47412d09faaab685ab0a0706fbe13ba2e Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Wed, 29 Jun 2022 15:38:13 +0200 Subject: [PATCH 127/356] Clean up environment variables --- .github/workflows/ci.yml | 32 ++++---------------------------- 1 file changed, 4 insertions(+), 28 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 3dbf8d922152..97ce8e31f879 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -4,6 +4,10 @@ on: - push - pull_request +env: + # Enable backtraces for easier debugging + RUST_BACKTRACE: 1 + jobs: build: runs-on: ubuntu-latest @@ -102,46 +106,18 @@ jobs: - name: Test std_tests run: | - # Enable backtraces for easier debugging - export RUST_BACKTRACE=1 - - # Reduce amount of benchmark runs as they are slow - export COMPILE_RUNS=2 - export RUN_RUNS=2 - ./test.sh --release --clean --build-sysroot --std-tests ${{ matrix.libgccjit_version.extra }} - name: Test test_libcore run: | - # Enable backtraces for easier debugging - export RUST_BACKTRACE=1 - - # Reduce amount of benchmark runs as they are slow - export COMPILE_RUNS=2 - export RUN_RUNS=2 - ./test.sh --release --test-libcore ${{ matrix.libgccjit_version.extra }} - name: Test extended_sysroot_tests run: | - # Enable backtraces for easier debugging - export RUST_BACKTRACE=1 - - # Reduce amount of benchmark runs as they are slow - export COMPILE_RUNS=2 - export RUN_RUNS=2 - ./test.sh --release --extended-tests ${{ matrix.libgccjit_version.extra }} - name: Test test_rustc run: | - # Enable backtraces for easier debugging - export RUST_BACKTRACE=1 - - # Reduce amount of benchmark runs as they are slow - export COMPILE_RUNS=2 - export RUN_RUNS=2 - ./test.sh --release --test-rustc ${{ matrix.libgccjit_version.extra }} duplicates: From 4ef0d19becccb2ae84e1971bb440b0fb74e0f8b5 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Wed, 29 Jun 2022 15:40:11 +0200 Subject: [PATCH 128/356] Add --mini-tests option and run mini-tests in CI --- .github/workflows/ci.yml | 6 +++++- test.sh | 4 ++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 97ce8e31f879..4e2647dd4273 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -104,9 +104,13 @@ jobs: command: build args: --release + - name: Test mini_tests + run: | + ./test.sh --release --clean --build-sysroot --mini-tests ${{ matrix.libgccjit_version.extra }} + - name: Test std_tests run: | - ./test.sh --release --clean --build-sysroot --std-tests ${{ matrix.libgccjit_version.extra }} + ./test.sh --release --std-tests ${{ matrix.libgccjit_version.extra }} - name: Test test_libcore run: | diff --git a/test.sh b/test.sh index b4d10fa6e4d2..904434807c46 100755 --- a/test.sh +++ b/test.sh @@ -69,6 +69,10 @@ while [[ $# -gt 0 ]]; do funcs+=(extended_sysroot_tests) shift ;; + "--mini-tests") + funcs+=(mini_tests) + shift + ;; "--build-sysroot") funcs+=(build_sysroot) From 18350b70abdce808c611d5c1e68752c8302c55a3 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Wed, 29 Jun 2022 17:35:57 +0200 Subject: [PATCH 129/356] Parallelize CI tests --- .github/workflows/ci.yml | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 4e2647dd4273..4867db02b3fd 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -19,6 +19,13 @@ jobs: - { gcc: "libgccjit.so", extra: "" } - { gcc: "libgccjit_without_int128.so", extra: "" } - { gcc: "libgccjit12.so", extra: "--no-default-features" } + commands: [ + "--mini-tests", + "--std-tests", + "--test-libcore", + "--extended-tests", + "--test-rustc", + ] steps: - uses: actions/checkout@v2 @@ -104,25 +111,9 @@ jobs: command: build args: --release - - name: Test mini_tests + - name: Run tests run: | - ./test.sh --release --clean --build-sysroot --mini-tests ${{ matrix.libgccjit_version.extra }} - - - name: Test std_tests - run: | - ./test.sh --release --std-tests ${{ matrix.libgccjit_version.extra }} - - - name: Test test_libcore - run: | - ./test.sh --release --test-libcore ${{ matrix.libgccjit_version.extra }} - - - name: Test extended_sysroot_tests - run: | - ./test.sh --release --extended-tests ${{ matrix.libgccjit_version.extra }} - - - name: Test test_rustc - run: | - ./test.sh --release --test-rustc ${{ matrix.libgccjit_version.extra }} + ./test.sh --release --clean --build-sysroot ${{ matrix.commands }} ${{ matrix.libgccjit_version.extra }} duplicates: runs-on: ubuntu-latest From 9edaf82a0389aa3465659c4d0769bf2269975e07 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 26 Jun 2022 10:28:44 -0400 Subject: [PATCH 130/356] Add comment --- src/builder.rs | 2 ++ src/lib.rs | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/builder.rs b/src/builder.rs index 9f6ffb9a610f..4aad171cb78e 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -222,6 +222,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { else { assert!(!((actual_ty.is_vector() && !expected_ty.is_vector()) || (!actual_ty.is_vector() && expected_ty.is_vector())), "{:?} ({}) -> {:?} ({}), index: {:?}[{}]", actual_ty, actual_ty.is_vector(), expected_ty, expected_ty.is_vector(), func_ptr, index); // TODO(antoyo): perhaps use __builtin_convertvector for vector casting. + // TODO: remove bitcast now that vector types can be compared? self.bitcast(actual_val, expected_ty) } } @@ -1497,6 +1498,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { // NOTE: sometimes, the type of else_val can be different than the type of then_val in // libgccjit (vector of int vs vector of int32_t), but they should be the same for the AND // operation to work. + // TODO: remove bitcast now that vector types can be compared? let else_val = self.context.new_bitcast(None, else_val, then_val.get_type()); let else_vals = inverted_masks & else_val; diff --git a/src/lib.rs b/src/lib.rs index 5bfdeb8b93a4..b8db4c9540b7 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -1,7 +1,7 @@ /* * TODO(antoyo): implement equality in libgccjit based on https://zpz.github.io/blog/overloading-equality-operator-in-cpp-class-hierarchy/ (for type equality?) * TODO(antoyo): support #[inline] attributes. - * TODO(antoyo): support LTO (gcc's equivalent to Thin LTO is enabled by -fwhopr: https://stackoverflow.com/questions/64954525/does-gcc-have-thin-lto). + * TODO(antoyo): support LTO (gcc's equivalent to Full LTO is -flto -flto-partition=one — https://documentation.suse.com/sbp/all/html/SBP-GCC-10/index.html). * * TODO(antoyo): remove the patches. */ From 0ba53c821127f2b05f77f1a35f70d757272f0b54 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Thu, 30 Jun 2022 16:35:53 +0200 Subject: [PATCH 131/356] Split rustc tests in two --- .github/workflows/ci.yml | 7 ++++- failing-ui-tests.txt | 55 ++++++++++++++++++++++++++++++++++++++++ failing-ui-tests12.txt | 17 +++++++++++++ test.sh | 31 +++++++++++++++++++++- 4 files changed, 108 insertions(+), 2 deletions(-) create mode 100644 failing-ui-tests.txt create mode 100644 failing-ui-tests12.txt diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 4867db02b3fd..2e69168dda8c 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -24,7 +24,8 @@ jobs: "--std-tests", "--test-libcore", "--extended-tests", - "--test-rustc", + "--test-successful-rustc", + "--test-failing-rustc", ] steps: @@ -111,6 +112,10 @@ jobs: command: build args: --release + - name: Add more failing tests for GCC 12 + if: ${{ matrix.libgccjit_version.gcc == 'libgccjit12.so' }} + run: cat failing-ui-tests12.txt >> failing-ui-tests.txt + - name: Run tests run: | ./test.sh --release --clean --build-sysroot ${{ matrix.commands }} ${{ matrix.libgccjit_version.extra }} diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt new file mode 100644 index 000000000000..717d0d39331f --- /dev/null +++ b/failing-ui-tests.txt @@ -0,0 +1,55 @@ +src/test/ui/alloc-error/default-alloc-error-hook.rs +src/test/ui/allocator/custom-in-block.rs +src/test/ui/allocator/custom-in-submodule.rs +src/test/ui/allocator/custom.rs +src/test/ui/allocator/hygiene.rs +src/test/ui/allocator/no_std-alloc-error-handler-custom.rs +src/test/ui/allocator/no_std-alloc-error-handler-default.rs +src/test/ui/allocator/xcrate-use.rs +src/test/ui/allocator/xcrate-use2.rs +src/test/ui/asm/may_unwind.rs +src/test/ui/asm/x86_64/const.rs +src/test/ui/asm/x86_64/multiple-clobber-abi.rs +src/test/ui/async-await/async-fn-size-moved-locals.rs +src/test/ui/async-await/async-fn-size-uninit-locals.rs +src/test/ui/backtrace.rs +src/test/ui/cfg/cfg-panic.rs +src/test/ui/debuginfo/debuginfo-emit-llvm-ir-and-split-debuginfo.rs +src/test/ui/functions-closures/parallel-codegen-closures.rs +src/test/ui/generator/size-moved-locals.rs +src/test/ui/issues/issue-32518.rs +src/test/ui/issues/issue-47364.rs +src/test/ui/issues/issue-74564-if-expr-stack-overflow.rs +src/test/ui/linkage-attr/linkage1.rs +src/test/ui/lto/dylib-works.rs +src/test/ui/mir/mir_heavy_promoted.rs +src/test/ui/numbers-arithmetic/saturating-float-casts.rs +src/test/ui/polymorphization/promoted-function.rs +src/test/ui/runtime/rt-explody-panic-payloads.rs +src/test/ui/sepcomp/sepcomp-cci.rs +src/test/ui/sepcomp/sepcomp-extern.rs +src/test/ui/sepcomp/sepcomp-fns-backwards.rs +src/test/ui/sepcomp/sepcomp-fns.rs +src/test/ui/sepcomp/sepcomp-lib.rs +src/test/ui/sepcomp/sepcomp-statics.rs +src/test/ui/simd/generics.rs +src/test/ui/simd/intrinsic/float-math-pass.rs +src/test/ui/simd/intrinsic/float-minmax-pass.rs +src/test/ui/simd/intrinsic/generic-arithmetic-pass.rs +src/test/ui/simd/intrinsic/generic-as.rs +src/test/ui/simd/intrinsic/generic-bitmask-pass.rs +src/test/ui/simd/intrinsic/generic-comparison-pass.rs +src/test/ui/simd/intrinsic/generic-gather-pass.rs +src/test/ui/simd/intrinsic/generic-reduction-pass.rs +src/test/ui/simd/intrinsic/generic-select-pass.rs +src/test/ui/simd/issue-17170.rs +src/test/ui/simd/issue-39720.rs +src/test/ui/simd/issue-85915-simd-ptrs.rs +src/test/ui/simd/issue-89193.rs +src/test/ui/simd/libm_std_can_float.rs +src/test/ui/simd/simd-bitmask.rs +src/test/ui/simd/type-generic-monomorphisation-extern-nonnull-ptr.rs +src/test/ui/sse2.rs +src/test/ui/statics/issue-91050-1.rs +src/test/ui/statics/issue-91050-2.rs +src/test/ui/target-feature/missing-plusminus.rs diff --git a/failing-ui-tests12.txt b/failing-ui-tests12.txt new file mode 100644 index 000000000000..0a50c0a2ce13 --- /dev/null +++ b/failing-ui-tests12.txt @@ -0,0 +1,17 @@ +src/test/ui/intrinsics/const-eval-select-x86_64.rs +src/test/ui/packed/packed-struct-drop-aligned.rs +src/test/ui/packed/packed-struct-generic-layout.rs +src/test/ui/packed/packed-struct-layout.rs +src/test/ui/packed/packed-struct-optimized-enum.rs +src/test/ui/packed/packed-struct-size.rs +src/test/ui/packed/packed-struct-vec.rs +src/test/ui/packed/packed-tuple-struct-layout.rs +src/test/ui/simd/array-type.rs +src/test/ui/simd/intrinsic/generic-arithmetic-saturating-pass.rs +src/test/ui/simd/intrinsic/generic-cast-pass.rs +src/test/ui/simd/intrinsic/generic-cast-pointer-width.rs +src/test/ui/simd/intrinsic/generic-elements-pass.rs +src/test/ui/simd/intrinsic/inlining-issue67557-ice.rs +src/test/ui/simd/intrinsic/inlining-issue67557.rs +src/test/ui/simd/monomorphize-shuffle-index.rs +src/test/ui/simd/shuffle.rs diff --git a/test.sh b/test.sh index 4815704f10b7..32fe8cf0586b 100755 --- a/test.sh +++ b/test.sh @@ -42,7 +42,15 @@ while [[ $# -gt 0 ]]; do shift ;; "--test-rustc") - funcs+=(test_rustc) + funcs=(test_rustc) + shift + ;; + "--test-successful-rustc") + funcs+=(test_successful_rustc) + shift + ;; + "--test-failing-rustc") + funcs+=(test_failing_rustc) shift ;; @@ -276,10 +284,31 @@ EOF RUSTC_ARGS="-Zpanic-abort-tests -Csymbol-mangling-version=v0 -Zcodegen-backend="$(pwd)"/../target/"$CHANNEL"/librustc_codegen_gcc."$dylib_ext" --sysroot "$(pwd)"/../build_sysroot/sysroot -Cpanic=abort" + if [ $# -eq 0 ]; then + # No argument supplied to the function. Doing nothing. + echo "No argument provided. Keeping all UI tests" + elif [ $1 = "0" ]; then + # Removing the failing tests. + xargs -a ../failing-ui-tests.txt -d'\n' rm + else + # Removing all tests. + find src/test/ui -type f -name '*.rs' -exec rm {} \; + # Putting back only the failing ones. + xargs -a ../failing-ui-tests.txt -d'\n' git checkout -- + fi + echo "[TEST] rustc test suite" COMPILETEST_FORCE_STAGE0=1 ./x.py test --run always --stage 0 src/test/ui/ --rustc-args "$RUSTC_ARGS" } +function test_failing_rustc() { + test_rustc "1" +} + +function test_successful_rustc() { + test_rustc "0" +} + function clean_ui_tests() { find rust/build/x86_64-unknown-linux-gnu/test/ui/ -name stamp -exec rm -rf {} \; } From a69770308c195c88c14c2e3ff98a1adeecb9990a Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Thu, 9 Jun 2022 22:14:33 -0400 Subject: [PATCH 132/356] Add patch to allow testing stdarch --- ...1-Add-stdarch-Cargo.toml-for-testing.patch | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 patches/0001-Add-stdarch-Cargo.toml-for-testing.patch diff --git a/patches/0001-Add-stdarch-Cargo.toml-for-testing.patch b/patches/0001-Add-stdarch-Cargo.toml-for-testing.patch new file mode 100644 index 000000000000..93c63b5dcacf --- /dev/null +++ b/patches/0001-Add-stdarch-Cargo.toml-for-testing.patch @@ -0,0 +1,39 @@ +From c3821e02fbd6cb5ad6e06d759fccdc9073712375 Mon Sep 17 00:00:00 2001 +From: Antoni Boucher +Date: Tue, 7 Jun 2022 21:40:13 -0400 +Subject: [PATCH] Add stdarch Cargo.toml for testing + +--- + library/stdarch/Cargo.toml | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + create mode 100644 library/stdarch/Cargo.toml + +diff --git a/library/stdarch/Cargo.toml b/library/stdarch/Cargo.toml +new file mode 100644 +index 0000000..fbe0a95 +--- /dev/null ++++ b/library/stdarch/Cargo.toml +@@ -0,0 +1,20 @@ ++[workspace] ++members = [ ++ "crates/core_arch", ++ "crates/std_detect", ++ "crates/stdarch-gen", ++ "examples/" ++] ++exclude = [ ++ "crates/wasm-assert-instr-tests" ++] ++ ++[profile.release] ++debug = true ++opt-level = 3 ++incremental = true ++ ++[profile.bench] ++debug = 1 ++opt-level = 3 ++incremental = true +-- +2.26.2.7.g19db9cfb68.dirty + From 1777cdd644c67d82f306142ef77cce6f33719f54 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Thu, 9 Jun 2022 22:15:24 -0400 Subject: [PATCH 133/356] Add antoyo in TODOs --- src/intrinsic/simd.rs | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index 8f9862414e60..842b4a92080c 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -216,7 +216,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let variable = bx.current_func().new_local(None, vector.get_type(), "new_vector"); bx.llbb().add_assignment(None, variable, vector); let lvalue = bx.context.new_vector_access(None, variable.to_rvalue(), index); - // TODO: if simd_insert is constant, use BIT_REF. + // TODO(antoyo): if simd_insert is constant, use BIT_REF. bx.llbb().add_assignment(None, lvalue, value); return Ok(variable.to_rvalue()); } @@ -545,9 +545,9 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, }, (true, true) => { // Algorithm from: https://codereview.stackexchange.com/questions/115869/saturated-signed-addition - // TODO: improve using conditional operators if possible. + // TODO(antoyo): improve using conditional operators if possible. let arg_type = lhs.get_type(); - // TODO: convert lhs and rhs to unsigned. + // TODO(antoyo): convert lhs and rhs to unsigned. let sum = lhs + rhs; let vector_type = arg_type.dyncast_vector().expect("vector type"); let unit = vector_type.get_num_units(); @@ -581,7 +581,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, // negative of the right operand. Find a proper subtraction algorithm. let rhs = bx.context.new_unary_op(None, UnaryOp::Minus, arg_type, rhs); - // TODO: convert lhs and rhs to unsigned. + // TODO(antoyo): convert lhs and rhs to unsigned. let sum = lhs + rhs; let vector_type = arg_type.dyncast_vector().expect("vector type"); let unit = vector_type.get_num_units(); From 910ec42566c08819de7732bea910fa53f99fd530 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 19 Jun 2022 18:58:08 -0400 Subject: [PATCH 134/356] Fixes to make stdarch tests compile --- src/base.rs | 22 ++++++++++++++++++++-- src/builder.rs | 2 +- src/common.rs | 14 ++++++++++++-- 3 files changed, 33 insertions(+), 5 deletions(-) diff --git a/src/base.rs b/src/base.rs index 19c981309d75..2f688fd66b2a 100644 --- a/src/base.rs +++ b/src/base.rs @@ -83,7 +83,7 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ context.add_command_line_option("-mavx2"); // FIXME(antoyo): the following causes an illegal instruction on vmovdqu64 in std_example on my CPU. // Only add if the CPU supports it. - /*context.add_command_line_option("-mavx512f"); + context.add_command_line_option("-mavx512f"); context.add_command_line_option("-msha"); context.add_command_line_option("-mpclmul"); context.add_command_line_option("-mfma"); @@ -91,7 +91,25 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ context.add_command_line_option("-mavx512vpopcntdq"); context.add_command_line_option("-mavx512vl"); context.add_command_line_option("-m64"); - context.add_command_line_option("-mbmi");*/ + context.add_command_line_option("-mbmi"); + context.add_command_line_option("-mgfni"); + context.add_command_line_option("-mavxvnni"); + context.add_command_line_option("-mavx512vnni"); + context.add_command_line_option("-mavx512bw"); + context.add_command_line_option("-mf16c"); + context.add_command_line_option("-mavx512bitalg"); + context.add_command_line_option("-maes"); + context.add_command_line_option("-mxsavec"); + context.add_command_line_option("-mbmi2"); + context.add_command_line_option("-mavx512bf16"); + context.add_command_line_option("-mrtm"); + context.add_command_line_option("-mvaes"); + context.add_command_line_option("-mvpclmulqdq"); + context.add_command_line_option("-mavx"); + context.add_command_line_option("-mavx512vbmi2"); + context.add_command_line_option("-mavx512vbmi"); + context.add_command_line_option("-mavx512ifma"); + context.add_command_line_option("-mavx512cd"); for arg in &tcx.sess.opts.cg.llvm_args { context.add_command_line_option(arg); } diff --git a/src/builder.rs b/src/builder.rs index 4aad171cb78e..08930387ccb2 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -213,7 +213,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let actual_ty = actual_val.get_type(); if expected_ty != actual_ty { - if !actual_ty.is_vector() && !expected_ty.is_vector() && actual_ty.is_integral() && expected_ty.is_integral() { + if !actual_ty.is_vector() && !expected_ty.is_vector() && (actual_ty.is_integral() && expected_ty.is_integral()) || (actual_ty.get_pointee().is_some() && expected_ty.get_pointee().is_some()) { self.context.new_cast(None, actual_val, expected_ty) } else if on_stack_param_indices.contains(&index) { diff --git a/src/common.rs b/src/common.rs index ce341406eaf4..e0e35bea782b 100644 --- a/src/common.rs +++ b/src/common.rs @@ -177,8 +177,18 @@ impl<'gcc, 'tcx> ConstMethods<'tcx> for CodegenCx<'gcc, 'tcx> { } let value = self.const_uint_big(self.type_ix(bitsize), data); - // TODO(bjorn3): assert size is correct - self.const_bitcast(value, ty) + let bytesize = layout.size(self).bytes(); + if bitsize > 1 && ty.is_integral() && bytesize as u32 == ty.get_size() { + // NOTE: since the intrinsic _xabort is called with a bitcast, which + // is non-const, but expects a constant, do a normal cast instead of a bitcast. + // FIXME(antoyo): fix bitcast to work in constant contexts. + // TODO: perhaps only use bitcast for pointers? + self.context.new_cast(None, value, ty) + } + else { + // TODO(bjorn3): assert size is correct + self.const_bitcast(value, ty) + } } Scalar::Ptr(ptr, _size) => { let (alloc_id, offset) = ptr.into_parts(); From 4094923789f99cc64b5a8c9353d232a22b820a93 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 19 Jun 2022 20:19:26 -0400 Subject: [PATCH 135/356] Disable avx512 --- src/base.rs | 22 +++++++++++----------- src/lib.rs | 2 +- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/base.rs b/src/base.rs index 2f688fd66b2a..943001423844 100644 --- a/src/base.rs +++ b/src/base.rs @@ -83,33 +83,33 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ context.add_command_line_option("-mavx2"); // FIXME(antoyo): the following causes an illegal instruction on vmovdqu64 in std_example on my CPU. // Only add if the CPU supports it. - context.add_command_line_option("-mavx512f"); + //context.add_command_line_option("-mavx512f"); context.add_command_line_option("-msha"); context.add_command_line_option("-mpclmul"); context.add_command_line_option("-mfma"); context.add_command_line_option("-mfma4"); - context.add_command_line_option("-mavx512vpopcntdq"); - context.add_command_line_option("-mavx512vl"); + //context.add_command_line_option("-mavx512vpopcntdq"); + //context.add_command_line_option("-mavx512vl"); context.add_command_line_option("-m64"); context.add_command_line_option("-mbmi"); context.add_command_line_option("-mgfni"); context.add_command_line_option("-mavxvnni"); - context.add_command_line_option("-mavx512vnni"); - context.add_command_line_option("-mavx512bw"); + //context.add_command_line_option("-mavx512vnni"); + //context.add_command_line_option("-mavx512bw"); context.add_command_line_option("-mf16c"); - context.add_command_line_option("-mavx512bitalg"); + //context.add_command_line_option("-mavx512bitalg"); context.add_command_line_option("-maes"); context.add_command_line_option("-mxsavec"); context.add_command_line_option("-mbmi2"); - context.add_command_line_option("-mavx512bf16"); + //context.add_command_line_option("-mavx512bf16"); context.add_command_line_option("-mrtm"); context.add_command_line_option("-mvaes"); context.add_command_line_option("-mvpclmulqdq"); context.add_command_line_option("-mavx"); - context.add_command_line_option("-mavx512vbmi2"); - context.add_command_line_option("-mavx512vbmi"); - context.add_command_line_option("-mavx512ifma"); - context.add_command_line_option("-mavx512cd"); + //context.add_command_line_option("-mavx512vbmi2"); + //context.add_command_line_option("-mavx512vbmi"); + //context.add_command_line_option("-mavx512ifma"); + //context.add_command_line_option("-mavx512cd"); for arg in &tcx.sess.opts.cg.llvm_args { context.add_command_line_option(arg); } diff --git a/src/lib.rs b/src/lib.rs index b8db4c9540b7..f83c1e536357 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -304,7 +304,7 @@ pub fn target_features(sess: &Session) -> Vec { // Probably using the equivalent of __builtin_cpu_supports. #[cfg(feature="master")] { - _feature.contains("sse") || _feature.contains("avx") + (_feature.contains("sse") || _feature.contains("avx")) && !_feature.contains("avx512") } #[cfg(not(feature="master"))] { From 1c4ca283df4e918ce2fdba1c5826c957a8daad3d Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Wed, 22 Jun 2022 17:48:54 -0400 Subject: [PATCH 136/356] Support #[target(enable)] function attribute --- Cargo.lock | 9 +++- Cargo.toml | 5 +- src/attributes.rs | 114 ++++++++++++++++++++++++++++++++++++++++++++++ src/base.rs | 28 +++++++----- src/callee.rs | 7 ++- src/declare.rs | 5 +- src/lib.rs | 22 +++++++++ src/mono_item.rs | 5 +- 8 files changed, 174 insertions(+), 21 deletions(-) create mode 100644 src/attributes.rs diff --git a/Cargo.lock b/Cargo.lock index 6df2102470fe..e52e742ec6ce 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -41,7 +41,6 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" -source = "git+https://github.com/antoyo/gccjit.rs#bdb86fb5092895ff5589726b33250010c64d93f6" dependencies = [ "gccjit_sys", ] @@ -49,7 +48,6 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" -source = "git+https://github.com/antoyo/gccjit.rs#bdb86fb5092895ff5589726b33250010c64d93f6" dependencies = [ "libc 0.1.12", ] @@ -215,6 +213,7 @@ dependencies = [ "ar", "gccjit", "lang_tester", + "smallvec", "target-lexicon", "tempfile", ] @@ -228,6 +227,12 @@ dependencies = [ "winapi-util", ] +[[package]] +name = "smallvec" +version = "1.8.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f2dd574626839106c320a323308629dcb1acfc96e32a8cba364ddc61ac23ee83" + [[package]] name = "target-lexicon" version = "0.10.0" diff --git a/Cargo.toml b/Cargo.toml index 211d19a8dc89..26a0e92923d5 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -22,11 +22,12 @@ default = ["master"] master = ["gccjit/master"] [dependencies] -gccjit = { git = "https://github.com/antoyo/gccjit.rs" } +#gccjit = { git = "https://github.com/antoyo/gccjit.rs" } # Local copy. -#gccjit = { path = "../gccjit.rs" } +gccjit = { path = "../gccjit.rs" } +smallvec = { version = "1.6.1", features = ["union", "may_dangle"] } target-lexicon = "0.10.0" ar = "0.8.0" diff --git a/src/attributes.rs b/src/attributes.rs new file mode 100644 index 000000000000..c52b10ee20a8 --- /dev/null +++ b/src/attributes.rs @@ -0,0 +1,114 @@ +use gccjit::{FnAttribute, Function}; +use rustc_attr::InstructionSetAttr; +use rustc_codegen_ssa::target_features::tied_target_features; +use rustc_data_structures::fx::FxHashMap; +use rustc_middle::ty; +use rustc_session::Session; +use rustc_span::symbol::sym; +use smallvec::{smallvec, SmallVec}; + +use crate::context::CodegenCx; + +// Given a map from target_features to whether they are enabled or disabled, +// ensure only valid combinations are allowed. +pub fn check_tied_features( + sess: &Session, + features: &FxHashMap<&str, bool>, +) -> Option<&'static [&'static str]> { + for tied in tied_target_features(sess) { + // Tied features must be set to the same value, or not set at all + let mut tied_iter = tied.iter(); + let enabled = features.get(tied_iter.next().unwrap()); + if tied_iter.any(|f| enabled != features.get(f)) { + return Some(tied); + } + } + None +} + +// TODO: maybe move to a new module gcc_util. +// To find a list of GCC's names, check https://gcc.gnu.org/onlinedocs/gcc/Function-Attributes.html +fn to_gcc_features<'a>(sess: &Session, s: &'a str) -> SmallVec<[&'a str; 2]> { + let arch = if sess.target.arch == "x86_64" { "x86" } else { &*sess.target.arch }; + match (arch, s) { + ("x86", "sse4.2") => smallvec!["sse4.2", "crc32"], + ("x86", "pclmulqdq") => smallvec!["pclmul"], + ("x86", "rdrand") => smallvec!["rdrnd"], + ("x86", "bmi1") => smallvec!["bmi"], + ("x86", "cmpxchg16b") => smallvec!["cx16"], + ("x86", "avx512vaes") => smallvec!["vaes"], + ("x86", "avx512gfni") => smallvec!["gfni"], + ("x86", "avx512vpclmulqdq") => smallvec!["vpclmulqdq"], + // NOTE: seems like GCC requires 'avx512bw' for 'avx512vbmi2'. + ("x86", "avx512vbmi2") => smallvec!["avx512vbmi2", "avx512bw"], + // NOTE: seems like GCC requires 'avx512bw' for 'avx512bitalg'. + ("x86", "avx512bitalg") => smallvec!["avx512bitalg", "avx512bw"], + ("aarch64", "rcpc2") => smallvec!["rcpc-immo"], + ("aarch64", "dpb") => smallvec!["ccpp"], + ("aarch64", "dpb2") => smallvec!["ccdp"], + ("aarch64", "frintts") => smallvec!["fptoint"], + ("aarch64", "fcma") => smallvec!["complxnum"], + ("aarch64", "pmuv3") => smallvec!["perfmon"], + ("aarch64", "paca") => smallvec!["pauth"], + ("aarch64", "pacg") => smallvec!["pauth"], + // Rust ties fp and neon together. In LLVM neon implicitly enables fp, + // but we manually enable neon when a feature only implicitly enables fp + ("aarch64", "f32mm") => smallvec!["f32mm", "neon"], + ("aarch64", "f64mm") => smallvec!["f64mm", "neon"], + ("aarch64", "fhm") => smallvec!["fp16fml", "neon"], + ("aarch64", "fp16") => smallvec!["fullfp16", "neon"], + ("aarch64", "jsconv") => smallvec!["jsconv", "neon"], + ("aarch64", "sve") => smallvec!["sve", "neon"], + ("aarch64", "sve2") => smallvec!["sve2", "neon"], + ("aarch64", "sve2-aes") => smallvec!["sve2-aes", "neon"], + ("aarch64", "sve2-sm4") => smallvec!["sve2-sm4", "neon"], + ("aarch64", "sve2-sha3") => smallvec!["sve2-sha3", "neon"], + ("aarch64", "sve2-bitperm") => smallvec!["sve2-bitperm", "neon"], + (_, s) => smallvec![s], + } +} + +/// Composite function which sets GCC attributes for function depending on its AST (`#[attribute]`) +/// attributes. +pub fn from_fn_attrs<'gcc, 'tcx>( + cx: &CodegenCx<'gcc, 'tcx>, + func: Function<'gcc>, + instance: ty::Instance<'tcx>, +) { + let codegen_fn_attrs = cx.tcx.codegen_fn_attrs(instance.def_id()); + + let function_features = + codegen_fn_attrs.target_features.iter().map(|f| f.as_str()).collect::>(); + + if let Some(f) = check_tied_features(cx.tcx.sess, &function_features.iter().map(|f| (*f, true)).collect()) { + let span = cx.tcx + .get_attr(instance.def_id(), sym::target_feature) + .map_or_else(|| cx.tcx.def_span(instance.def_id()), |a| a.span); + let msg = format!( + "the target features {} must all be either enabled or disabled together", + f.join(", ") + ); + let mut err = cx.tcx.sess.struct_span_err(span, &msg); + err.help("add the missing features in a `target_feature` attribute"); + err.emit(); + return; + } + + let mut function_features = function_features + .iter() + .flat_map(|feat| to_gcc_features(cx.tcx.sess, feat).into_iter()) + .chain(codegen_fn_attrs.instruction_set.iter().map(|x| match x { + InstructionSetAttr::ArmA32 => "-thumb-mode", // TODO: support removing feature. + InstructionSetAttr::ArmT32 => "thumb-mode", + })) + .collect::>(); + + // TODO(antoyo): check if we really need global backend features. (Maybe they could be applied + // globally?) + let mut global_features = cx.tcx.global_backend_features(()).iter().map(|s| s.as_str()); + function_features.extend(&mut global_features); + let target_features = function_features.join(","); + if !target_features.is_empty() { + func.add_attribute(FnAttribute::Target, &target_features); + } +} diff --git a/src/base.rs b/src/base.rs index 943001423844..2f77978df1ed 100644 --- a/src/base.rs +++ b/src/base.rs @@ -79,37 +79,41 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ // TODO(antoyo): only set on x86 platforms. context.add_command_line_option("-masm=intel"); // TODO(antoyo): only add the following cli argument if the feature is supported. - context.add_command_line_option("-msse2"); + /*context.add_command_line_option("-msse2"); context.add_command_line_option("-mavx2"); // FIXME(antoyo): the following causes an illegal instruction on vmovdqu64 in std_example on my CPU. // Only add if the CPU supports it. - //context.add_command_line_option("-mavx512f"); context.add_command_line_option("-msha"); context.add_command_line_option("-mpclmul"); context.add_command_line_option("-mfma"); context.add_command_line_option("-mfma4"); - //context.add_command_line_option("-mavx512vpopcntdq"); - //context.add_command_line_option("-mavx512vl"); context.add_command_line_option("-m64"); context.add_command_line_option("-mbmi"); context.add_command_line_option("-mgfni"); context.add_command_line_option("-mavxvnni"); - //context.add_command_line_option("-mavx512vnni"); - //context.add_command_line_option("-mavx512bw"); context.add_command_line_option("-mf16c"); - //context.add_command_line_option("-mavx512bitalg"); context.add_command_line_option("-maes"); context.add_command_line_option("-mxsavec"); context.add_command_line_option("-mbmi2"); - //context.add_command_line_option("-mavx512bf16"); context.add_command_line_option("-mrtm"); context.add_command_line_option("-mvaes"); context.add_command_line_option("-mvpclmulqdq"); context.add_command_line_option("-mavx"); - //context.add_command_line_option("-mavx512vbmi2"); - //context.add_command_line_option("-mavx512vbmi"); - //context.add_command_line_option("-mavx512ifma"); - //context.add_command_line_option("-mavx512cd"); + + if env::var("CG_GCCJIT_ENABLE_AVX512").as_deref() == Ok("1") { + context.add_command_line_option("-mavx512f"); + context.add_command_line_option("-mavx512vpopcntdq"); + context.add_command_line_option("-mavx512vl"); + context.add_command_line_option("-mavx512vnni"); + context.add_command_line_option("-mavx512bw"); + context.add_command_line_option("-mavx512bitalg"); + context.add_command_line_option("-mavx512bf16"); + context.add_command_line_option("-mavx512vbmi2"); + context.add_command_line_option("-mavx512vbmi"); + context.add_command_line_option("-mavx512ifma"); + context.add_command_line_option("-mavx512cd"); + }*/ + for arg in &tcx.sess.opts.cg.llvm_args { context.add_command_line_option(arg); } diff --git a/src/callee.rs b/src/callee.rs index 76419b103d04..5557f886b287 100644 --- a/src/callee.rs +++ b/src/callee.rs @@ -4,6 +4,7 @@ use rustc_middle::ty::{self, Instance, TypeFoldable}; use rustc_middle::ty::layout::{FnAbiOf, HasTyCtxt}; use crate::abi::FnAbiGccExt; +use crate::attributes; use crate::context::CodegenCx; /// Codegens a reference to a fn/method item, monomorphizing and @@ -67,8 +68,12 @@ pub fn get_fn<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, instance: Instance<'tcx>) cx.linkage.set(FunctionType::Extern); let func = cx.declare_fn(&sym, &fn_abi); + attributes::from_fn_attrs(cx, func, instance); + // TODO(antoyo): set linkage and attributes. - func + + // FIXME(antoyo): this is a wrong cast. That requires changing the compiler API. + unsafe { std::mem::transmute(func) } }; cx.function_instances.borrow_mut().insert(instance, func); diff --git a/src/declare.rs b/src/declare.rs index a619e2f77125..5f6360a7da53 100644 --- a/src/declare.rs +++ b/src/declare.rs @@ -79,12 +79,11 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { unsafe { std::mem::transmute(func) } } - pub fn declare_fn(&self, name: &str, fn_abi: &FnAbi<'tcx, Ty<'tcx>>) -> RValue<'gcc> { + pub fn declare_fn(&self, name: &str, fn_abi: &FnAbi<'tcx, Ty<'tcx>>) -> Function<'gcc> { let (return_type, params, variadic, on_stack_param_indices) = fn_abi.gcc_type(self); let func = declare_raw_fn(self, name, () /*fn_abi.llvm_cconv()*/, return_type, ¶ms, variadic); self.on_stack_function_params.borrow_mut().insert(func, on_stack_param_indices); - // FIXME(antoyo): this is a wrong cast. That requires changing the compiler API. - unsafe { std::mem::transmute(func) } + func } pub fn define_global(&self, name: &str, ty: Type<'gcc>, is_tls: bool, link_section: Option) -> LValue<'gcc> { diff --git a/src/lib.rs b/src/lib.rs index f83c1e536357..1ca2394abdc2 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -13,6 +13,7 @@ #![warn(unused_lifetimes)] extern crate rustc_ast; +extern crate rustc_attr; extern crate rustc_codegen_ssa; extern crate rustc_data_structures; extern crate rustc_errors; @@ -32,6 +33,7 @@ mod abi; mod allocator; mod archive; mod asm; +mod attributes; mod back; mod base; mod builder; @@ -188,6 +190,24 @@ pub struct GccContext { context: Context<'static>, } +impl GccContext { + fn new<'tcx>(tcx: TyCtxt<'tcx>) -> Self { + let context = create_context(tcx); + Self { + context, + } + } +} + +fn create_context<'gcc, 'tcx>(tcx: TyCtxt<'tcx>) -> Context<'gcc> { + let context = Context::default(); + if tcx.sess.target.is_builtin { + //let features = global_gcc_features(sess, false); + println!("Features: {:?}", tcx.sess.opts.cg.target_feature); + } + context +} + unsafe impl Send for GccContext {} // FIXME(antoyo): that shouldn't be Sync. Parallel compilation is currently disabled with "-Zno-parallel-llvm". Try to disable it here. unsafe impl Sync for GccContext {} @@ -302,6 +322,8 @@ pub fn target_features(sess: &Session) -> Vec { .filter(|_feature| { // TODO(antoyo): implement a way to get enabled feature in libgccjit. // Probably using the equivalent of __builtin_cpu_supports. + // TODO: maybe use whatever outputs the following command: + // gcc -march=native -Q --help=target #[cfg(feature="master")] { (_feature.contains("sse") || _feature.contains("avx")) && !_feature.contains("avx512") diff --git a/src/mono_item.rs b/src/mono_item.rs index e21d40b6c37e..60a42846bd3d 100644 --- a/src/mono_item.rs +++ b/src/mono_item.rs @@ -5,6 +5,7 @@ use rustc_middle::ty::{self, Instance, TypeFoldable}; use rustc_middle::ty::layout::{FnAbiOf, LayoutOf}; use rustc_span::def_id::DefId; +use crate::attributes; use crate::base; use crate::context::CodegenCx; use crate::type_of::LayoutGccExt; @@ -28,9 +29,11 @@ impl<'gcc, 'tcx> PreDefineMethods<'tcx> for CodegenCx<'gcc, 'tcx> { let fn_abi = self.fn_abi_of_instance(instance, ty::List::empty()); self.linkage.set(base::linkage_to_gcc(linkage)); - let _decl = self.declare_fn(symbol_name, &fn_abi); + let decl = self.declare_fn(symbol_name, &fn_abi); //let attrs = self.tcx.codegen_fn_attrs(instance.def_id()); + attributes::from_fn_attrs(self, decl, instance); + // TODO(antoyo): call set_link_section() to allow initializing argc/argv. // TODO(antoyo): set unique comdat. // TODO(antoyo): use inline attribute from there in linkage.set() above. From 6205f1a0c590381bef30a6faf6bd55ba13d9c05a Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 26 Jun 2022 11:00:04 -0400 Subject: [PATCH 137/356] Reenable target flags --- src/base.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/base.rs b/src/base.rs index 2f77978df1ed..84d48d8591a7 100644 --- a/src/base.rs +++ b/src/base.rs @@ -79,7 +79,7 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ // TODO(antoyo): only set on x86 platforms. context.add_command_line_option("-masm=intel"); // TODO(antoyo): only add the following cli argument if the feature is supported. - /*context.add_command_line_option("-msse2"); + context.add_command_line_option("-msse2"); context.add_command_line_option("-mavx2"); // FIXME(antoyo): the following causes an illegal instruction on vmovdqu64 in std_example on my CPU. // Only add if the CPU supports it. @@ -112,7 +112,7 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ context.add_command_line_option("-mavx512vbmi"); context.add_command_line_option("-mavx512ifma"); context.add_command_line_option("-mavx512cd"); - }*/ + } for arg in &tcx.sess.opts.cg.llvm_args { context.add_command_line_option(arg); From 9db55d2f54e869be328c2f0926786f8fd0ec84a4 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 26 Jun 2022 14:28:06 -0400 Subject: [PATCH 138/356] Fix vector comparison now returning a vector of integers --- src/builder.rs | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/builder.rs b/src/builder.rs index 08930387ccb2..867fd531f504 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1490,6 +1490,9 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let zeros = self.context.new_rvalue_from_vector(None, cond_type, &zeros); let masks = self.context.new_comparison(None, ComparisonOp::NotEquals, cond, zeros); + // NOTE: masks is a vector of integers, but the values can be vectors of floats, so use bitcast to make + // the & operation work. + let masks = self.bitcast_if_needed(masks, then_val.get_type()); let then_vals = masks & then_val; let ones = vec![self.context.new_rvalue_one(element_type); num_units]; @@ -1509,6 +1512,16 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { fn difference_or_zero<'gcc>(a: RValue<'gcc>, b: RValue<'gcc>, context: &'gcc Context<'gcc>) -> RValue<'gcc> { let difference = a - b; let masks = context.new_comparison(None, ComparisonOp::GreaterThanEquals, b, a); + // NOTE: masks is a vector of integers, but the values can be vectors of floats, so use bitcast to make + // the & operation work. + let a_type = a.get_type(); + let masks = + if masks.get_type() != a_type { + context.new_bitcast(None, masks, a_type) + } + else { + masks + }; difference & masks } From 85036a5afaa0fc7926c91e8d3f557661864833f1 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Wed, 29 Jun 2022 21:05:40 -0400 Subject: [PATCH 139/356] Use gccjit from repo --- Cargo.lock | 2 ++ Cargo.toml | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index e52e742ec6ce..ff09a08b5afe 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -41,6 +41,7 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" +source = "git+https://github.com/antoyo/gccjit.rs#a8997afb665dc467c1bdbddf04877143683f0cce" dependencies = [ "gccjit_sys", ] @@ -48,6 +49,7 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" +source = "git+https://github.com/antoyo/gccjit.rs#a8997afb665dc467c1bdbddf04877143683f0cce" dependencies = [ "libc 0.1.12", ] diff --git a/Cargo.toml b/Cargo.toml index 26a0e92923d5..3ac354ea4942 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -22,10 +22,10 @@ default = ["master"] master = ["gccjit/master"] [dependencies] -#gccjit = { git = "https://github.com/antoyo/gccjit.rs" } +gccjit = { git = "https://github.com/antoyo/gccjit.rs" } # Local copy. -gccjit = { path = "../gccjit.rs" } +#gccjit = { path = "../gccjit.rs" } smallvec = { version = "1.6.1", features = ["union", "may_dangle"] } target-lexicon = "0.10.0" From 16ca66d66439a29b38369e60ba7259b338fbedfc Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Wed, 29 Jun 2022 21:06:00 -0400 Subject: [PATCH 140/356] Fix build only --- test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test.sh b/test.sh index 32fe8cf0586b..5258775a6d51 100755 --- a/test.sh +++ b/test.sh @@ -107,7 +107,7 @@ else fi if (( $build_only == 1 )); then - echo "Since it's `build-only`, exiting..." + echo "Since it's 'build-only', exiting..." exit fi From d19a5ea868968ddf1ad65fee1e7a85191388aa69 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Wed, 29 Jun 2022 21:10:20 -0400 Subject: [PATCH 141/356] Fix all command --- test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test.sh b/test.sh index 5258775a6d51..594b63dfd0d8 100755 --- a/test.sh +++ b/test.sh @@ -324,7 +324,7 @@ function all() { } if [ ${#funcs[@]} -eq 0 ]; then - echo "No command passed, running `--all`..." + echo "No command passed, running '--all'..." all else for t in ${funcs[@]}; do From fea51f391ed91c487dda81d50389474b768441c7 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Wed, 29 Jun 2022 21:31:02 -0400 Subject: [PATCH 142/356] Fix warnings --- src/attributes.rs | 6 +++++- src/base.rs | 14 -------------- src/intrinsic/llvm.rs | 2 +- src/intrinsic/simd.rs | 4 +++- src/lib.rs | 18 ------------------ 5 files changed, 9 insertions(+), 35 deletions(-) diff --git a/src/attributes.rs b/src/attributes.rs index c52b10ee20a8..c9ba0ecb877a 100644 --- a/src/attributes.rs +++ b/src/attributes.rs @@ -1,4 +1,6 @@ -use gccjit::{FnAttribute, Function}; +#[cfg_attr(not(feature="master"), allow(unused_imports))] +use gccjit::FnAttribute; +use gccjit::Function; use rustc_attr::InstructionSetAttr; use rustc_codegen_ssa::target_features::tied_target_features; use rustc_data_structures::fx::FxHashMap; @@ -72,6 +74,7 @@ fn to_gcc_features<'a>(sess: &Session, s: &'a str) -> SmallVec<[&'a str; 2]> { /// attributes. pub fn from_fn_attrs<'gcc, 'tcx>( cx: &CodegenCx<'gcc, 'tcx>, + #[cfg_attr(not(feature="master"), allow(unused_variables))] func: Function<'gcc>, instance: ty::Instance<'tcx>, ) { @@ -109,6 +112,7 @@ pub fn from_fn_attrs<'gcc, 'tcx>( function_features.extend(&mut global_features); let target_features = function_features.join(","); if !target_features.is_empty() { + #[cfg(feature="master")] func.add_attribute(FnAttribute::Target, &target_features); } } diff --git a/src/base.rs b/src/base.rs index 84d48d8591a7..9d81a01e7a61 100644 --- a/src/base.rs +++ b/src/base.rs @@ -100,20 +100,6 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ context.add_command_line_option("-mvpclmulqdq"); context.add_command_line_option("-mavx"); - if env::var("CG_GCCJIT_ENABLE_AVX512").as_deref() == Ok("1") { - context.add_command_line_option("-mavx512f"); - context.add_command_line_option("-mavx512vpopcntdq"); - context.add_command_line_option("-mavx512vl"); - context.add_command_line_option("-mavx512vnni"); - context.add_command_line_option("-mavx512bw"); - context.add_command_line_option("-mavx512bitalg"); - context.add_command_line_option("-mavx512bf16"); - context.add_command_line_option("-mavx512vbmi2"); - context.add_command_line_option("-mavx512vbmi"); - context.add_command_line_option("-mavx512ifma"); - context.add_command_line_option("-mavx512cd"); - } - for arg in &tcx.sess.opts.cg.llvm_args { context.add_command_line_option(arg); } diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index f623bc5fb10c..f00c1b301097 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -287,9 +287,9 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc pub fn adjust_intrinsic_return_value<'a, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc, 'tcx>, mut return_value: RValue<'gcc>, func_name: &str, args: &[RValue<'gcc>], args_adjusted: bool) -> RValue<'gcc> { match func_name { "__builtin_ia32_vfmaddss3_round" | "__builtin_ia32_vfmaddsd3_round" => { - let zero = builder.context.new_rvalue_zero(builder.int_type); #[cfg(feature="master")] { + let zero = builder.context.new_rvalue_zero(builder.int_type); return_value = builder.context.new_vector_access(None, return_value, zero).to_rvalue(); } }, diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index 842b4a92080c..9c2a1401a154 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -1,4 +1,6 @@ -use gccjit::{BinaryOp, RValue, Type, ToRValue, ComparisonOp, UnaryOp}; +#[cfg_attr(not(feature="master"), allow(unused_imports))] +use gccjit::{ToRValue, ComparisonOp, UnaryOp}; +use gccjit::{BinaryOp, RValue, Type}; use rustc_codegen_ssa::base::compare_simd_types; use rustc_codegen_ssa::common::{TypeKind, span_invalid_monomorphization_error}; use rustc_codegen_ssa::mir::operand::OperandRef; diff --git a/src/lib.rs b/src/lib.rs index 1ca2394abdc2..cb1d848eb670 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -190,24 +190,6 @@ pub struct GccContext { context: Context<'static>, } -impl GccContext { - fn new<'tcx>(tcx: TyCtxt<'tcx>) -> Self { - let context = create_context(tcx); - Self { - context, - } - } -} - -fn create_context<'gcc, 'tcx>(tcx: TyCtxt<'tcx>) -> Context<'gcc> { - let context = Context::default(); - if tcx.sess.target.is_builtin { - //let features = global_gcc_features(sess, false); - println!("Features: {:?}", tcx.sess.opts.cg.target_feature); - } - context -} - unsafe impl Send for GccContext {} // FIXME(antoyo): that shouldn't be Sync. Parallel compilation is currently disabled with "-Zno-parallel-llvm". Try to disable it here. unsafe impl Sync for GccContext {} From b14b440f3aa54eb4a58d803a28fe19cf9abf7734 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Thu, 30 Jun 2022 17:19:01 -0400 Subject: [PATCH 143/356] Format --- src/attributes.rs | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/src/attributes.rs b/src/attributes.rs index c9ba0ecb877a..4937e475944c 100644 --- a/src/attributes.rs +++ b/src/attributes.rs @@ -13,15 +13,12 @@ use crate::context::CodegenCx; // Given a map from target_features to whether they are enabled or disabled, // ensure only valid combinations are allowed. -pub fn check_tied_features( - sess: &Session, - features: &FxHashMap<&str, bool>, -) -> Option<&'static [&'static str]> { +pub fn check_tied_features(sess: &Session, features: &FxHashMap<&str, bool>) -> Option<&'static [&'static str]> { for tied in tied_target_features(sess) { // Tied features must be set to the same value, or not set at all let mut tied_iter = tied.iter(); let enabled = features.get(tied_iter.next().unwrap()); - if tied_iter.any(|f| enabled != features.get(f)) { + if tied_iter.any(|feature| enabled != features.get(feature)) { return Some(tied); } } @@ -81,16 +78,13 @@ pub fn from_fn_attrs<'gcc, 'tcx>( let codegen_fn_attrs = cx.tcx.codegen_fn_attrs(instance.def_id()); let function_features = - codegen_fn_attrs.target_features.iter().map(|f| f.as_str()).collect::>(); + codegen_fn_attrs.target_features.iter().map(|features| features.as_str()).collect::>(); - if let Some(f) = check_tied_features(cx.tcx.sess, &function_features.iter().map(|f| (*f, true)).collect()) { + if let Some(features) = check_tied_features(cx.tcx.sess, &function_features.iter().map(|features| (*features, true)).collect()) { let span = cx.tcx .get_attr(instance.def_id(), sym::target_feature) .map_or_else(|| cx.tcx.def_span(instance.def_id()), |a| a.span); - let msg = format!( - "the target features {} must all be either enabled or disabled together", - f.join(", ") - ); + let msg = format!("the target features {} must all be either enabled or disabled together", features.join(", ")); let mut err = cx.tcx.sess.struct_span_err(span, &msg); err.help("add the missing features in a `target_feature` attribute"); err.emit(); From 5f4777e55da380a97336d09ca61ea615ef1dd315 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Wed, 6 Jul 2022 23:05:14 -0400 Subject: [PATCH 144/356] Add name in TODO --- src/attributes.rs | 4 ++-- src/common.rs | 2 +- src/lib.rs | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/attributes.rs b/src/attributes.rs index 4937e475944c..e570b583decb 100644 --- a/src/attributes.rs +++ b/src/attributes.rs @@ -25,7 +25,7 @@ pub fn check_tied_features(sess: &Session, features: &FxHashMap<&str, bool>) -> None } -// TODO: maybe move to a new module gcc_util. +// TODO(antoyo): maybe move to a new module gcc_util. // To find a list of GCC's names, check https://gcc.gnu.org/onlinedocs/gcc/Function-Attributes.html fn to_gcc_features<'a>(sess: &Session, s: &'a str) -> SmallVec<[&'a str; 2]> { let arch = if sess.target.arch == "x86_64" { "x86" } else { &*sess.target.arch }; @@ -95,7 +95,7 @@ pub fn from_fn_attrs<'gcc, 'tcx>( .iter() .flat_map(|feat| to_gcc_features(cx.tcx.sess, feat).into_iter()) .chain(codegen_fn_attrs.instruction_set.iter().map(|x| match x { - InstructionSetAttr::ArmA32 => "-thumb-mode", // TODO: support removing feature. + InstructionSetAttr::ArmA32 => "-thumb-mode", // TODO(antoyo): support removing feature. InstructionSetAttr::ArmT32 => "thumb-mode", })) .collect::>(); diff --git a/src/common.rs b/src/common.rs index e0e35bea782b..d55ad87e19bf 100644 --- a/src/common.rs +++ b/src/common.rs @@ -182,7 +182,7 @@ impl<'gcc, 'tcx> ConstMethods<'tcx> for CodegenCx<'gcc, 'tcx> { // NOTE: since the intrinsic _xabort is called with a bitcast, which // is non-const, but expects a constant, do a normal cast instead of a bitcast. // FIXME(antoyo): fix bitcast to work in constant contexts. - // TODO: perhaps only use bitcast for pointers? + // TODO(antoyo): perhaps only use bitcast for pointers? self.context.new_cast(None, value, ty) } else { diff --git a/src/lib.rs b/src/lib.rs index cb1d848eb670..b3cbf344ad13 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -304,7 +304,7 @@ pub fn target_features(sess: &Session) -> Vec { .filter(|_feature| { // TODO(antoyo): implement a way to get enabled feature in libgccjit. // Probably using the equivalent of __builtin_cpu_supports. - // TODO: maybe use whatever outputs the following command: + // TODO(antoyo): maybe use whatever outputs the following command: // gcc -march=native -Q --help=target #[cfg(feature="master")] { From 50f359c8a189c55e6db5842cb7ec16e801912e68 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Thu, 7 Jul 2022 21:34:38 +0200 Subject: [PATCH 145/356] Split tests to have faster CI --- .github/workflows/ci.yml | 7 +++- test.sh | 82 ++++++++++++++++++++++++++++++++++------ 2 files changed, 76 insertions(+), 13 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 2e69168dda8c..22f67a04e0b8 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -23,8 +23,11 @@ jobs: "--mini-tests", "--std-tests", "--test-libcore", - "--extended-tests", - "--test-successful-rustc", + "--extended-rand-tests", + "--extended-regex-example-tests", + "--extended-regex-tests", + "--test-successful-rustc --nb-parts 2 --current-part 0", + "--test-successful-rustc --nb-parts 2 --current-part 1", "--test-failing-rustc", ] diff --git a/test.sh b/test.sh index 594b63dfd0d8..dea9fe412e9a 100755 --- a/test.sh +++ b/test.sh @@ -19,6 +19,8 @@ gcc_master_branch=1 channel="debug" funcs=() build_only=0 +nb_parts=0 +current_part=0 while [[ $# -gt 0 ]]; do case $1 in @@ -77,6 +79,19 @@ while [[ $# -gt 0 ]]; do funcs+=(extended_sysroot_tests) shift ;; + "--extended-rand-tests") + funcs+=(extended_rand_tests) + shift + ;; + "--extended-regex-example-tests") + funcs+=(extended_regex_example_tests) + shift + ;; + "--extended-regex-tests") + funcs+=(extended_regex_tests) + shift + ;; + "--mini-tests") funcs+=(mini_tests) shift @@ -90,6 +105,16 @@ while [[ $# -gt 0 ]]; do build_only=1 shift ;; + "--nb-parts") + shift + nb_parts=$1 + shift + ;; + "--current-part") + shift + current_part=$1 + shift + ;; *) echo "Unknown option $1" exit 1 @@ -200,7 +225,7 @@ function test_libcore() { #echo "[BENCH RUN] mod_bench" #hyperfine --runs ${RUN_RUNS:-10} ./target/out/mod_bench{,_inline} ./target/out/mod_bench_llvm_* -function extended_sysroot_tests() { +function extended_rand_tests() { if (( $gcc_master_branch == 0 )); then return fi @@ -210,17 +235,12 @@ function extended_sysroot_tests() { echo "[TEST] rust-random/rand" ../cargo.sh test --workspace popd +} - #pushd simple-raytracer - #echo "[BENCH COMPILE] ebobby/simple-raytracer" - #hyperfine --runs "${RUN_RUNS:-10}" --warmup 1 --prepare "cargo clean" \ - #"RUSTC=rustc RUSTFLAGS='' cargo build" \ - #"../cargo.sh build" - - #echo "[BENCH RUN] ebobby/simple-raytracer" - #cp ./target/debug/main ./raytracer_cg_gcc - #hyperfine --runs "${RUN_RUNS:-10}" ./raytracer_cg_llvm ./raytracer_cg_gcc - #popd +function extended_regex_example_tests() { + if (( $gcc_master_branch == 0 )); then + return + fi pushd regex echo "[TEST] rust-lang/regex example shootout-regex-dna" @@ -232,12 +252,38 @@ function extended_sysroot_tests() { | ../cargo.sh run --example shootout-regex-dna \ | grep -v "Spawned thread" > res.txt diff -u res.txt examples/regexdna-output.txt + popd +} +function extended_regex_tests() { + if (( $gcc_master_branch == 0 )); then + return + fi + + pushd regex echo "[TEST] rust-lang/regex tests" + export CG_RUSTFLAGS="--cap-lints warn" # newer aho_corasick versions throw a deprecation warning ../cargo.sh test --tests -- --exclude-should-panic --test-threads 1 -Zunstable-options -q popd } +function extended_sysroot_tests() { + #pushd simple-raytracer + #echo "[BENCH COMPILE] ebobby/simple-raytracer" + #hyperfine --runs "${RUN_RUNS:-10}" --warmup 1 --prepare "cargo clean" \ + #"RUSTC=rustc RUSTFLAGS='' cargo build" \ + #"../cargo.sh build" + + #echo "[BENCH RUN] ebobby/simple-raytracer" + #cp ./target/debug/main ./raytracer_cg_gcc + #hyperfine --runs "${RUN_RUNS:-10}" ./raytracer_cg_llvm ./raytracer_cg_gcc + #popd + + extended_rand_tests + extended_regex_example_tests + extended_regex_tests +} + function test_rustc() { echo echo "[TEST] rust-lang/rust" @@ -297,6 +343,20 @@ EOF xargs -a ../failing-ui-tests.txt -d'\n' git checkout -- fi + if [ $nb_parts -gt 0 ]; then + echo "Splitting ui_test into $nb_parts parts (and running part $current_part)" + find src/test/ui -type f -name '*.rs' -not -path "*/auxiliary/*" > ui_tests + count=$((`wc -l < ui_tests` / $nb_parts)) + # We increment the number of tests by one because if this is an odd number, we would skip + # one test. + count=$((count + 1)) + split -d -l $count -a 1 ui_tests ui_tests.split + # Removing all tests. + find src/test/ui -type f -name '*.rs' -not -path "*/auxiliary/*" -exec rm {} \; + # Putting back only the ones we want to test. + xargs -a "ui_tests.split$current_part" -d'\n' git checkout -- + fi + echo "[TEST] rustc test suite" COMPILETEST_FORCE_STAGE0=1 ./x.py test --run always --stage 0 src/test/ui/ --rustc-args "$RUSTC_ARGS" } From 96d103b9f9a597cde9128a9429bfc6d516c8e030 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Fri, 8 Jul 2022 16:19:48 +0200 Subject: [PATCH 146/356] Sort ui_tests to ensure they remain coherent across different jobs --- test.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/test.sh b/test.sh index dea9fe412e9a..06f608ad422a 100755 --- a/test.sh +++ b/test.sh @@ -346,6 +346,8 @@ EOF if [ $nb_parts -gt 0 ]; then echo "Splitting ui_test into $nb_parts parts (and running part $current_part)" find src/test/ui -type f -name '*.rs' -not -path "*/auxiliary/*" > ui_tests + # To ensure it'll be always the same sub files, we sort the content. + sort ui_tests -o ui_tests count=$((`wc -l < ui_tests` / $nb_parts)) # We increment the number of tests by one because if this is an odd number, we would skip # one test. From 28b11119e720f1af0e9f3dd854ee2e4618ff185d Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Sat, 9 Jul 2022 21:36:23 +0200 Subject: [PATCH 147/356] Add cache for rust repository --- .github/workflows/ci.yml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 22f67a04e0b8..8b36fa0c1c7c 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -95,6 +95,15 @@ jobs: path: target key: ${{ runner.os }}-cargo-build-target-${{ hashFiles('rust-toolchain') }} + - name: Cache rust repository + # We only clone the rust repository for rustc tests + if: ${{ contains(matrix.commands, 'rustc') }} + uses: actions/cache@v2 + id: cache-rust-repository + with: + path: rust + key: ${{ runner.os }}-packages-${{ hashFiles('rust/.git/HEAD') }} + - name: Build run: | ./prepare_build.sh From 5f630f3c81583b7be15a230d47d48de0178b5da8 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 23 Jul 2022 19:12:35 -0400 Subject: [PATCH 148/356] Cleanup regarding handling of recursive types --- src/asm.rs | 10 +++++----- src/builder.rs | 4 ++-- src/common.rs | 4 ++-- src/consts.rs | 8 ++++---- src/context.rs | 5 +---- src/intrinsic/mod.rs | 4 ++-- src/mono_item.rs | 2 +- src/type_.rs | 2 +- src/type_of.rs | 32 ++++++++++++-------------------- 9 files changed, 30 insertions(+), 41 deletions(-) diff --git a/src/asm.rs b/src/asm.rs index 52fd66af0659..fa40aa80804a 100644 --- a/src/asm.rs +++ b/src/asm.rs @@ -156,7 +156,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { use ConstraintOrRegister::*; let (constraint, ty) = match (reg_to_gcc(reg), place) { - (Constraint(constraint), Some(place)) => (constraint, place.layout.gcc_type(self.cx, false)), + (Constraint(constraint), Some(place)) => (constraint, place.layout.gcc_type(self.cx)), // When `reg` is a class and not an explicit register but the out place is not specified, // we need to create an unused output variable to assign the output to. This var // needs to be of a type that's "compatible" with the register class, but specific type @@ -225,7 +225,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { // This decision is also backed by the fact that LLVM needs in and out // values to be of *exactly the same type*, not just "compatible". // I'm not sure if GCC is so picky too, but better safe than sorry. - let ty = in_value.layout.gcc_type(self.cx, false); + let ty = in_value.layout.gcc_type(self.cx); let tmp_var = self.current_func().new_local(None, ty, "output_register"); // If the out_place is None (i.e `inout(reg) _` syntax was used), we translate @@ -285,7 +285,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { continue }; - let ty = out_place.layout.gcc_type(self.cx, false); + let ty = out_place.layout.gcc_type(self.cx); let tmp_var = self.current_func().new_local(None, ty, "output_register"); tmp_var.set_register_name(reg_name); @@ -305,7 +305,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { // `in("explicit register") var` InlineAsmOperandRef::In { reg, value } => { if let ConstraintOrRegister::Register(reg_name) = reg_to_gcc(reg) { - let ty = value.layout.gcc_type(self.cx, false); + let ty = value.layout.gcc_type(self.cx); let reg_var = self.current_func().new_local(None, ty, "input_register"); reg_var.set_register_name(reg_name); self.llbb().add_assignment(None, reg_var, value.immediate()); @@ -324,7 +324,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { InlineAsmOperandRef::InOut { reg, late, in_value, out_place } => { if let ConstraintOrRegister::Register(reg_name) = reg_to_gcc(reg) { // See explanation in the first pass. - let ty = in_value.layout.gcc_type(self.cx, false); + let ty = in_value.layout.gcc_type(self.cx); let tmp_var = self.current_func().new_local(None, ty, "output_register"); tmp_var.set_register_name(reg_name); diff --git a/src/builder.rs b/src/builder.rs index 867fd531f504..616fc01b00c9 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -745,7 +745,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } else if place.layout.is_gcc_immediate() { let load = self.load( - place.layout.gcc_type(self, false), + place.layout.gcc_type(self), place.llval, place.align, ); @@ -756,7 +756,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } else if let abi::Abi::ScalarPair(ref a, ref b) = place.layout.abi { let b_offset = a.size(self).align_to(b.align(self).abi); - let pair_type = place.layout.gcc_type(self, false); + let pair_type = place.layout.gcc_type(self); let mut load = |i, scalar: &abi::Scalar, align| { let llptr = self.struct_gep(pair_type, place.llval, i as u64); diff --git a/src/common.rs b/src/common.rs index d55ad87e19bf..9c55692dea12 100644 --- a/src/common.rs +++ b/src/common.rs @@ -132,7 +132,7 @@ impl<'gcc, 'tcx> ConstMethods<'tcx> for CodegenCx<'gcc, 'tcx> { }); let len = s_str.len(); let cs = self.const_ptrcast(str_global.get_address(None), - self.type_ptr_to(self.layout_of(self.tcx.types.str_).gcc_type(self, true)), + self.type_ptr_to(self.layout_of(self.tcx.types.str_).gcc_type(self)), ); (cs, self.const_usize(len as u64)) } @@ -235,7 +235,7 @@ impl<'gcc, 'tcx> ConstMethods<'tcx> for CodegenCx<'gcc, 'tcx> { fn from_const_alloc(&self, layout: TyAndLayout<'tcx>, alloc: ConstAllocation<'tcx>, offset: Size) -> PlaceRef<'tcx, RValue<'gcc>> { assert_eq!(alloc.inner().align, layout.align.abi); - let ty = self.type_ptr_to(layout.gcc_type(self, true)); + let ty = self.type_ptr_to(layout.gcc_type(self)); let value = if layout.size == Size::ZERO { let value = self.const_usize(alloc.inner().align.bytes()); diff --git a/src/consts.rs b/src/consts.rs index c0b8d21818f8..e83cf53f48ef 100644 --- a/src/consts.rs +++ b/src/consts.rs @@ -80,7 +80,7 @@ impl<'gcc, 'tcx> StaticMethods for CodegenCx<'gcc, 'tcx> { let instance = Instance::mono(self.tcx, def_id); let ty = instance.ty(self.tcx, ty::ParamEnv::reveal_all()); - let gcc_type = self.layout_of(ty).gcc_type(self, true); + let gcc_type = self.layout_of(ty).gcc_type(self); // TODO(antoyo): set alignment. @@ -211,7 +211,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { let global = if let Some(def_id) = def_id.as_local() { let id = self.tcx.hir().local_def_id_to_hir_id(def_id); - let llty = self.layout_of(ty).gcc_type(self, true); + let llty = self.layout_of(ty).gcc_type(self); // FIXME: refactor this to work without accessing the HIR let global = match self.tcx.hir().get(id) { Node::Item(&hir::Item { span, kind: hir::ItemKind::Static(..), .. }) => { @@ -356,7 +356,7 @@ pub fn codegen_static_initializer<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, def_id fn check_and_apply_linkage<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, attrs: &CodegenFnAttrs, ty: Ty<'tcx>, sym: &str, span: Span) -> LValue<'gcc> { let is_tls = attrs.flags.contains(CodegenFnAttrFlags::THREAD_LOCAL); - let llty = cx.layout_of(ty).gcc_type(cx, true); + let llty = cx.layout_of(ty).gcc_type(cx); if let Some(linkage) = attrs.linkage { // If this is a static with a linkage specified, then we need to handle // it a little specially. The typesystem prevents things like &T and @@ -365,7 +365,7 @@ fn check_and_apply_linkage<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, attrs: &Codeg // that the static actually has a null value. let llty2 = if let ty::RawPtr(ref mt) = ty.kind() { - cx.layout_of(mt.ty).gcc_type(cx, true) + cx.layout_of(mt.ty).gcc_type(cx) } else { cx.sess().span_fatal( diff --git a/src/context.rs b/src/context.rs index 44f36cfa4cad..9879e31c2ea5 100644 --- a/src/context.rs +++ b/src/context.rs @@ -1,6 +1,6 @@ use std::cell::{Cell, RefCell}; -use gccjit::{Block, CType, Context, Function, FunctionPtrType, FunctionType, LValue, RValue, Struct, Type}; +use gccjit::{Block, CType, Context, Function, FunctionPtrType, FunctionType, LValue, RValue, Type}; use rustc_codegen_ssa::base::wants_msvc_seh; use rustc_codegen_ssa::traits::{ BackendTypes, @@ -78,8 +78,6 @@ pub struct CodegenCx<'gcc, 'tcx> { pub struct_types: RefCell>, Type<'gcc>>>, - pub types_with_fields_to_set: RefCell, (Struct<'gcc>, TyAndLayout<'tcx>)>>, - /// Cache instances of monomorphic and polymorphic items pub instances: RefCell, LValue<'gcc>>>, /// Cache function instances of monomorphic and polymorphic items @@ -243,7 +241,6 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { types: Default::default(), tcx, struct_types: Default::default(), - types_with_fields_to_set: Default::default(), local_gen_sym_counter: Cell::new(0), eh_personality: Cell::new(None), pointee_infos: Default::default(), diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index c6681de68e26..1315edf0891e 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -90,7 +90,7 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { let name = tcx.item_name(def_id); let name_str = name.as_str(); - let llret_ty = self.layout_of(ret_ty).gcc_type(self, true); + let llret_ty = self.layout_of(ret_ty).gcc_type(self); let result = PlaceRef::new_sized(llresult, fn_abi.ret.layout); let simple = get_simple_intrinsic(self, name); @@ -389,7 +389,7 @@ impl<'gcc, 'tcx> ArgAbiExt<'gcc, 'tcx> for ArgAbi<'tcx, Ty<'tcx>> { /// Gets the LLVM type for a place of the original Rust type of /// this argument/return, i.e., the result of `type_of::type_of`. fn memory_ty(&self, cx: &CodegenCx<'gcc, 'tcx>) -> Type<'gcc> { - self.layout.gcc_type(cx, true) + self.layout.gcc_type(cx) } /// Stores a direct/indirect value described by this ArgAbi into a diff --git a/src/mono_item.rs b/src/mono_item.rs index 60a42846bd3d..454c7538edb9 100644 --- a/src/mono_item.rs +++ b/src/mono_item.rs @@ -15,7 +15,7 @@ impl<'gcc, 'tcx> PreDefineMethods<'tcx> for CodegenCx<'gcc, 'tcx> { let attrs = self.tcx.codegen_fn_attrs(def_id); let instance = Instance::mono(self.tcx, def_id); let ty = instance.ty(self.tcx, ty::ParamEnv::reveal_all()); - let gcc_type = self.layout_of(ty).gcc_type(self, true); + let gcc_type = self.layout_of(ty).gcc_type(self); let is_tls = attrs.flags.contains(CodegenFnAttrFlags::THREAD_LOCAL); let global = self.define_global(symbol_name, gcc_type, is_tls, attrs.link_section); diff --git a/src/type_.rs b/src/type_.rs index 002b95db36de..b85aad7c00b3 100644 --- a/src/type_.rs +++ b/src/type_.rs @@ -273,7 +273,7 @@ pub fn struct_fields<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, layout: TyAndLayout assert_eq!(offset.align_to(padding_align) + padding, target_offset); result.push(cx.type_padding_filler(padding, padding_align)); - result.push(field.gcc_type(cx, !field.ty.is_any_ptr())); // FIXME(antoyo): might need to check if the type is inside another, like Box. + result.push(field.gcc_type(cx)); offset = target_offset + field.size; prev_effective_align = effective_field_align; } diff --git a/src/type_of.rs b/src/type_of.rs index 569ee2925b13..c7aa4239c7fa 100644 --- a/src/type_of.rs +++ b/src/type_of.rs @@ -50,7 +50,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { } } -pub fn uncached_gcc_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, layout: TyAndLayout<'tcx>, defer: &mut Option<(Struct<'gcc>, TyAndLayout<'tcx>)>) -> Type<'gcc> { +fn uncached_gcc_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, layout: TyAndLayout<'tcx>, defer: &mut Option<(Struct<'gcc>, TyAndLayout<'tcx>)>) -> Type<'gcc> { match layout.abi { Abi::Scalar(_) => bug!("handled elsewhere"), Abi::Vector { ref element, count } => { @@ -114,7 +114,7 @@ pub fn uncached_gcc_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, layout: TyAndLa }, } } - FieldsShape::Array { count, .. } => cx.type_array(layout.field(cx, 0).gcc_type(cx, true), count), + FieldsShape::Array { count, .. } => cx.type_array(layout.field(cx, 0).gcc_type(cx), count), FieldsShape::Arbitrary { .. } => match name { None => { @@ -133,7 +133,7 @@ pub fn uncached_gcc_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, layout: TyAndLa pub trait LayoutGccExt<'tcx> { fn is_gcc_immediate(&self) -> bool; fn is_gcc_scalar_pair(&self) -> bool; - fn gcc_type<'gcc>(&self, cx: &CodegenCx<'gcc, 'tcx>, set_fields: bool) -> Type<'gcc>; + fn gcc_type<'gcc>(&self, cx: &CodegenCx<'gcc, 'tcx>) -> Type<'gcc>; fn immediate_gcc_type<'gcc>(&self, cx: &CodegenCx<'gcc, 'tcx>) -> Type<'gcc>; fn scalar_gcc_type_at<'gcc>(&self, cx: &CodegenCx<'gcc, 'tcx>, scalar: &abi::Scalar, offset: Size) -> Type<'gcc>; fn scalar_pair_element_gcc_type<'gcc>(&self, cx: &CodegenCx<'gcc, 'tcx>, index: usize, immediate: bool) -> Type<'gcc>; @@ -168,8 +168,7 @@ impl<'tcx> LayoutGccExt<'tcx> for TyAndLayout<'tcx> { /// with the inner-most trailing unsized field using the "minimal unit" /// of that field's type - this is useful for taking the address of /// that field and ensuring the struct has the right alignment. - //TODO(antoyo): do we still need the set_fields parameter? - fn gcc_type<'gcc>(&self, cx: &CodegenCx<'gcc, 'tcx>, set_fields: bool) -> Type<'gcc> { + fn gcc_type<'gcc>(&self, cx: &CodegenCx<'gcc, 'tcx>) -> Type<'gcc> { if let Abi::Scalar(ref scalar) = self.abi { // Use a different cache for scalars because pointers to DSTs // can be either fat or thin (data pointers of fat pointers). @@ -179,10 +178,10 @@ impl<'tcx> LayoutGccExt<'tcx> for TyAndLayout<'tcx> { let ty = match *self.ty.kind() { ty::Ref(_, ty, _) | ty::RawPtr(ty::TypeAndMut { ty, .. }) => { - cx.type_ptr_to(cx.layout_of(ty).gcc_type(cx, set_fields)) + cx.type_ptr_to(cx.layout_of(ty).gcc_type(cx)) } ty::Adt(def, _) if def.is_box() => { - cx.type_ptr_to(cx.layout_of(self.ty.boxed_ty()).gcc_type(cx, true)) + cx.type_ptr_to(cx.layout_of(self.ty.boxed_ty()).gcc_type(cx)) } ty::FnPtr(sig) => cx.fn_ptr_backend_type(&cx.fn_abi_of_fn_ptr(sig, ty::List::empty())), _ => self.scalar_gcc_type_at(cx, scalar, Size::ZERO), @@ -199,13 +198,6 @@ impl<'tcx> LayoutGccExt<'tcx> for TyAndLayout<'tcx> { }; let cached_type = cx.types.borrow().get(&(self.ty, variant_index)).cloned(); if let Some(ty) = cached_type { - let type_to_set_fields = cx.types_with_fields_to_set.borrow_mut().remove(&ty); - if let Some((struct_type, layout)) = type_to_set_fields { - // Since we might be trying to generate a type containing another type which is not - // completely generated yet, we deferred setting the fields until now. - let (fields, packed) = struct_fields(cx, layout); - cx.set_struct_body(struct_type, &fields, packed); - } return ty; } @@ -222,7 +214,7 @@ impl<'tcx> LayoutGccExt<'tcx> for TyAndLayout<'tcx> { if let Some(v) = variant_index { layout = layout.for_variant(cx, v); } - layout.gcc_type(cx, true) + layout.gcc_type(cx) } else { uncached_gcc_type(cx, *self, &mut defer) @@ -230,9 +222,9 @@ impl<'tcx> LayoutGccExt<'tcx> for TyAndLayout<'tcx> { cx.types.borrow_mut().insert((self.ty, variant_index), ty); - if let Some((ty, layout)) = defer { + if let Some((deferred_ty, layout)) = defer { let (fields, packed) = struct_fields(cx, layout); - cx.set_struct_body(ty, &fields, packed); + cx.set_struct_body(deferred_ty, &fields, packed); } ty @@ -244,7 +236,7 @@ impl<'tcx> LayoutGccExt<'tcx> for TyAndLayout<'tcx> { return cx.type_i1(); } } - self.gcc_type(cx, true) + self.gcc_type(cx) } fn scalar_gcc_type_at<'gcc>(&self, cx: &CodegenCx<'gcc, 'tcx>, scalar: &abi::Scalar, offset: Size) -> Type<'gcc> { @@ -273,7 +265,7 @@ impl<'tcx> LayoutGccExt<'tcx> for TyAndLayout<'tcx> { // pointee types, to avoid bitcasting every `OperandRef::deref`. match self.ty.kind() { ty::Ref(..) | ty::RawPtr(_) => { - return self.field(cx, index).gcc_type(cx, true); + return self.field(cx, index).gcc_type(cx); } // only wide pointer boxes are handled as pointers // thin pointer boxes with scalar allocators are handled by the general logic below @@ -343,7 +335,7 @@ impl<'tcx> LayoutGccExt<'tcx> for TyAndLayout<'tcx> { impl<'gcc, 'tcx> LayoutTypeMethods<'tcx> for CodegenCx<'gcc, 'tcx> { fn backend_type(&self, layout: TyAndLayout<'tcx>) -> Type<'gcc> { - layout.gcc_type(self, true) + layout.gcc_type(self) } fn immediate_backend_type(&self, layout: TyAndLayout<'tcx>) -> Type<'gcc> { From 672eec3055c9c96420987dba18cf12aafaf7e3d6 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 24 Jul 2022 17:33:38 -0400 Subject: [PATCH 149/356] Support symbol visibility --- Cargo.lock | 4 +-- src/allocator.rs | 16 +++++++-- src/attributes.rs | 4 +-- src/base.rs | 11 ++++++ src/callee.rs | 91 +++++++++++++++++++++++++++++++++++++++++++++++ src/mono_item.rs | 30 +++++++++++++--- 6 files changed, 145 insertions(+), 11 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index ff09a08b5afe..3245f5843e54 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -41,7 +41,7 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" -source = "git+https://github.com/antoyo/gccjit.rs#a8997afb665dc467c1bdbddf04877143683f0cce" +source = "git+https://github.com/antoyo/gccjit.rs#1a60fe3918a5b3b0983c1ea09f4b9445001a6468" dependencies = [ "gccjit_sys", ] @@ -49,7 +49,7 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" -source = "git+https://github.com/antoyo/gccjit.rs#a8997afb665dc467c1bdbddf04877143683f0cce" +source = "git+https://github.com/antoyo/gccjit.rs#1a60fe3918a5b3b0983c1ea09f4b9445001a6468" dependencies = [ "libc 0.1.12", ] diff --git a/src/allocator.rs b/src/allocator.rs index c761e5aabd10..60985003a9e0 100644 --- a/src/allocator.rs +++ b/src/allocator.rs @@ -1,3 +1,5 @@ +#[cfg(feature="master")] +use gccjit::FnAttribute; use gccjit::{FunctionType, GlobalKind, ToRValue}; use rustc_ast::expand::allocator::{AllocatorKind, AllocatorTy, ALLOCATOR_METHODS}; use rustc_middle::bug; @@ -50,7 +52,8 @@ pub(crate) unsafe fn codegen(tcx: TyCtxt<'_>, mods: &mut GccContext, _module_nam let func = context.new_function(None, FunctionType::Exported, output.unwrap_or(void), &args, name, false); if tcx.sess.target.options.default_hidden_visibility { - // TODO(antoyo): set visibility. + #[cfg(feature="master")] + func.add_attribute(FnAttribute::Visibility(gccjit::Visibility::Hidden)); } if tcx.sess.must_emit_unwind_tables() { // TODO(antoyo): emit unwind tables. @@ -61,7 +64,8 @@ pub(crate) unsafe fn codegen(tcx: TyCtxt<'_>, mods: &mut GccContext, _module_nam .map(|(index, typ)| context.new_parameter(None, *typ, &format!("param{}", index))) .collect(); let callee = context.new_function(None, FunctionType::Extern, output.unwrap_or(void), &args, callee, false); - // TODO(antoyo): set visibility. + #[cfg(feature="master")] + callee.add_attribute(FnAttribute::Visibility(gccjit::Visibility::Hidden)); let block = func.new_block("entry"); @@ -90,6 +94,11 @@ pub(crate) unsafe fn codegen(tcx: TyCtxt<'_>, mods: &mut GccContext, _module_nam .collect(); let func = context.new_function(None, FunctionType::Exported, void, &args, name, false); + if tcx.sess.target.default_hidden_visibility { + #[cfg(feature="master")] + func.add_attribute(FnAttribute::Visibility(gccjit::Visibility::Hidden)); + } + let kind = if has_alloc_error_handler { AllocatorKind::Global @@ -102,7 +111,8 @@ pub(crate) unsafe fn codegen(tcx: TyCtxt<'_>, mods: &mut GccContext, _module_nam .map(|(index, typ)| context.new_parameter(None, *typ, &format!("param{}", index))) .collect(); let callee = context.new_function(None, FunctionType::Extern, void, &args, callee, false); - //llvm::LLVMRustSetVisibility(callee, llvm::Visibility::Hidden); + #[cfg(feature="master")] + callee.add_attribute(FnAttribute::Visibility(gccjit::Visibility::Hidden)); let block = func.new_block("entry"); diff --git a/src/attributes.rs b/src/attributes.rs index e570b583decb..243a1a36dd09 100644 --- a/src/attributes.rs +++ b/src/attributes.rs @@ -1,4 +1,4 @@ -#[cfg_attr(not(feature="master"), allow(unused_imports))] +#[cfg(feature="master")] use gccjit::FnAttribute; use gccjit::Function; use rustc_attr::InstructionSetAttr; @@ -107,6 +107,6 @@ pub fn from_fn_attrs<'gcc, 'tcx>( let target_features = function_features.join(","); if !target_features.is_empty() { #[cfg(feature="master")] - func.add_attribute(FnAttribute::Target, &target_features); + func.add_attribute(FnAttribute::Target(&target_features)); } } diff --git a/src/base.rs b/src/base.rs index 9d81a01e7a61..42194b526e64 100644 --- a/src/base.rs +++ b/src/base.rs @@ -8,6 +8,8 @@ use gccjit::{ }; use rustc_middle::dep_graph; use rustc_middle::ty::TyCtxt; +#[cfg(feature="master")] +use rustc_middle::mir::mono::Visibility; use rustc_middle::mir::mono::Linkage; use rustc_codegen_ssa::{ModuleCodegen, ModuleKind}; use rustc_codegen_ssa::base::maybe_create_entry_wrapper; @@ -20,6 +22,15 @@ use crate::GccContext; use crate::builder::Builder; use crate::context::CodegenCx; +#[cfg(feature="master")] +pub fn visibility_to_gcc(linkage: Visibility) -> gccjit::Visibility { + match linkage { + Visibility::Default => gccjit::Visibility::Default, + Visibility::Hidden => gccjit::Visibility::Hidden, + Visibility::Protected => gccjit::Visibility::Protected, + } +} + pub fn global_linkage_to_gcc(linkage: Linkage) -> GlobalKind { match linkage { Linkage::External => GlobalKind::Imported, diff --git a/src/callee.rs b/src/callee.rs index 5557f886b287..d7bbf1d34ef1 100644 --- a/src/callee.rs +++ b/src/callee.rs @@ -1,3 +1,5 @@ +#[cfg(feature="master")] +use gccjit::{FnAttribute, Visibility}; use gccjit::{FunctionType, RValue}; use rustc_codegen_ssa::traits::BaseTypeMethods; use rustc_middle::ty::{self, Instance, TypeFoldable}; @@ -70,8 +72,97 @@ pub fn get_fn<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, instance: Instance<'tcx>) attributes::from_fn_attrs(cx, func, instance); + let instance_def_id = instance.def_id(); + // TODO(antoyo): set linkage and attributes. + // Apply an appropriate linkage/visibility value to our item that we + // just declared. + // + // This is sort of subtle. Inside our codegen unit we started off + // compilation by predefining all our own `MonoItem` instances. That + // is, everything we're codegenning ourselves is already defined. That + // means that anything we're actually codegenning in this codegen unit + // will have hit the above branch in `get_declared_value`. As a result, + // we're guaranteed here that we're declaring a symbol that won't get + // defined, or in other words we're referencing a value from another + // codegen unit or even another crate. + // + // So because this is a foreign value we blanket apply an external + // linkage directive because it's coming from a different object file. + // The visibility here is where it gets tricky. This symbol could be + // referencing some foreign crate or foreign library (an `extern` + // block) in which case we want to leave the default visibility. We may + // also, though, have multiple codegen units. It could be a + // monomorphization, in which case its expected visibility depends on + // whether we are sharing generics or not. The important thing here is + // that the visibility we apply to the declaration is the same one that + // has been applied to the definition (wherever that definition may be). + let is_generic = instance.substs.non_erasable_generics().next().is_some(); + + if is_generic { + // This is a monomorphization. Its expected visibility depends + // on whether we are in share-generics mode. + + if cx.tcx.sess.opts.share_generics() { + // We are in share_generics mode. + + if let Some(instance_def_id) = instance_def_id.as_local() { + // This is a definition from the current crate. If the + // definition is unreachable for downstream crates or + // the current crate does not re-export generics, the + // definition of the instance will have been declared + // as `hidden`. + if cx.tcx.is_unreachable_local_definition(instance_def_id) + || !cx.tcx.local_crate_exports_generics() + { + #[cfg(feature="master")] + func.add_attribute(FnAttribute::Visibility(Visibility::Hidden)); + } + } else { + // This is a monomorphization of a generic function + // defined in an upstream crate. + if instance.upstream_monomorphization(tcx).is_some() { + // This is instantiated in another crate. It cannot + // be `hidden`. + } else { + // This is a local instantiation of an upstream definition. + // If the current crate does not re-export it + // (because it is a C library or an executable), it + // will have been declared `hidden`. + if !cx.tcx.local_crate_exports_generics() { + #[cfg(feature="master")] + func.add_attribute(FnAttribute::Visibility(Visibility::Hidden)); + } + } + } + } else { + // When not sharing generics, all instances are in the same + // crate and have hidden visibility + #[cfg(feature="master")] + func.add_attribute(FnAttribute::Visibility(Visibility::Hidden)); + } + } else { + // This is a non-generic function + if cx.tcx.is_codegened_item(instance_def_id) { + // This is a function that is instantiated in the local crate + + if instance_def_id.is_local() { + // This is function that is defined in the local crate. + // If it is not reachable, it is hidden. + if !cx.tcx.is_reachable_non_generic(instance_def_id) { + #[cfg(feature="master")] + func.add_attribute(FnAttribute::Visibility(Visibility::Hidden)); + } + } else { + // This is a function from an upstream crate that has + // been instantiated here. These are always hidden. + #[cfg(feature="master")] + func.add_attribute(FnAttribute::Visibility(Visibility::Hidden)); + } + } + } + // FIXME(antoyo): this is a wrong cast. That requires changing the compiler API. unsafe { std::mem::transmute(func) } }; diff --git a/src/mono_item.rs b/src/mono_item.rs index 454c7538edb9..d0d6b9b5bfe3 100644 --- a/src/mono_item.rs +++ b/src/mono_item.rs @@ -1,9 +1,11 @@ +#[cfg(feature="master")] +use gccjit::{VarAttribute, FnAttribute}; use rustc_codegen_ssa::traits::PreDefineMethods; +use rustc_hir::def_id::{DefId, LOCAL_CRATE}; use rustc_middle::middle::codegen_fn_attrs::CodegenFnAttrFlags; use rustc_middle::mir::mono::{Linkage, Visibility}; use rustc_middle::ty::{self, Instance, TypeFoldable}; use rustc_middle::ty::layout::{FnAbiOf, LayoutOf}; -use rustc_span::def_id::DefId; use crate::attributes; use crate::base; @@ -11,7 +13,8 @@ use crate::context::CodegenCx; use crate::type_of::LayoutGccExt; impl<'gcc, 'tcx> PreDefineMethods<'tcx> for CodegenCx<'gcc, 'tcx> { - fn predefine_static(&self, def_id: DefId, _linkage: Linkage, _visibility: Visibility, symbol_name: &str) { + #[cfg_attr(not(feature="master"), allow(unused_variables))] + fn predefine_static(&self, def_id: DefId, _linkage: Linkage, visibility: Visibility, symbol_name: &str) { let attrs = self.tcx.codegen_fn_attrs(def_id); let instance = Instance::mono(self.tcx, def_id); let ty = instance.ty(self.tcx, ty::ParamEnv::reveal_all()); @@ -19,12 +22,15 @@ impl<'gcc, 'tcx> PreDefineMethods<'tcx> for CodegenCx<'gcc, 'tcx> { let is_tls = attrs.flags.contains(CodegenFnAttrFlags::THREAD_LOCAL); let global = self.define_global(symbol_name, gcc_type, is_tls, attrs.link_section); + #[cfg(feature="master")] + global.add_attribute(VarAttribute::Visibility(base::visibility_to_gcc(visibility))); - // TODO(antoyo): set linkage and visibility. + // TODO(antoyo): set linkage. self.instances.borrow_mut().insert(instance, global); } - fn predefine_fn(&self, instance: Instance<'tcx>, linkage: Linkage, _visibility: Visibility, symbol_name: &str) { + #[cfg_attr(not(feature="master"), allow(unused_variables))] + fn predefine_fn(&self, instance: Instance<'tcx>, linkage: Linkage, visibility: Visibility, symbol_name: &str) { assert!(!instance.substs.needs_infer()); let fn_abi = self.fn_abi_of_instance(instance, ty::List::empty()); @@ -34,6 +40,22 @@ impl<'gcc, 'tcx> PreDefineMethods<'tcx> for CodegenCx<'gcc, 'tcx> { attributes::from_fn_attrs(self, decl, instance); + // If we're compiling the compiler-builtins crate, e.g., the equivalent of + // compiler-rt, then we want to implicitly compile everything with hidden + // visibility as we're going to link this object all over the place but + // don't want the symbols to get exported. + if linkage != Linkage::Internal + && linkage != Linkage::Private + && self.tcx.is_compiler_builtins(LOCAL_CRATE) + { + #[cfg(feature="master")] + decl.add_attribute(FnAttribute::Visibility(gccjit::Visibility::Hidden)); + } + else { + #[cfg(feature="master")] + decl.add_attribute(FnAttribute::Visibility(base::visibility_to_gcc(visibility))); + } + // TODO(antoyo): call set_link_section() to allow initializing argc/argv. // TODO(antoyo): set unique comdat. // TODO(antoyo): use inline attribute from there in linkage.set() above. From deedd2888175224b48b00eec4c74f0ab8625eb1e Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Thu, 4 Aug 2022 20:11:36 -0400 Subject: [PATCH 150/356] Fix the mxcsr builtins --- src/builder.rs | 3 ++- src/intrinsic/llvm.rs | 24 +++++++++++++++++++++++- 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index 616fc01b00c9..bcbaad39044d 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -279,6 +279,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let gcc_func = func_ptr.get_type().dyncast_function_ptr_type().expect("function ptr"); let func_name = format!("{:?}", func_ptr); let previous_arg_count = args.len(); + let orig_args = args; let args = llvm::adjust_intrinsic_arguments(&self, gcc_func, args.into(), &func_name); let args_adjusted = args.len() != previous_arg_count; let args = self.check_ptr_call("call", func_ptr, &*args); @@ -292,7 +293,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { if return_type != void_type { unsafe { RETURN_VALUE_COUNT += 1 }; let return_value = self.cx.context.new_call_through_ptr(None, func_ptr, &args); - let return_value = llvm::adjust_intrinsic_return_value(&self, return_value, &func_name, &args, args_adjusted); + let return_value = llvm::adjust_intrinsic_return_value(&self, return_value, &func_name, &args, args_adjusted, orig_args); let result = current_func.new_local(None, return_value.get_type(), &format!("ptrReturnValue{}", unsafe { RETURN_VALUE_COUNT })); self.block.add_assignment(None, result, return_value); result.to_rvalue() diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index f00c1b301097..20f500e34e90 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -1,6 +1,7 @@ use std::borrow::Cow; use gccjit::{Function, FunctionPtrType, RValue, ToRValue, UnaryOp}; +use rustc_codegen_ssa::traits::BuilderMethods; use crate::{context::CodegenCx, builder::Builder}; @@ -277,6 +278,15 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc *arg3 = builder.context.new_unary_op(None, UnaryOp::Minus, arg3.get_type(), *arg3); args = new_args.into(); }, + "__builtin_ia32_ldmxcsr" => { + // The builtin __builtin_ia32_ldmxcsr takes an integer value while llvm.x86.sse.ldmxcsr takes a pointer, + // so dereference the pointer. + let mut new_args = args.to_vec(); + let uint_ptr_type = builder.uint_type.make_pointer(); + let arg1 = builder.context.new_cast(None, args[0], uint_ptr_type); + new_args[0] = arg1.dereference(None).to_rvalue(); + args = new_args.into(); + }, _ => (), } } @@ -284,7 +294,7 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc args } -pub fn adjust_intrinsic_return_value<'a, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc, 'tcx>, mut return_value: RValue<'gcc>, func_name: &str, args: &[RValue<'gcc>], args_adjusted: bool) -> RValue<'gcc> { +pub fn adjust_intrinsic_return_value<'a, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc, 'tcx>, mut return_value: RValue<'gcc>, func_name: &str, args: &[RValue<'gcc>], args_adjusted: bool, orig_args: &[RValue<'gcc>]) -> RValue<'gcc> { match func_name { "__builtin_ia32_vfmaddss3_round" | "__builtin_ia32_vfmaddsd3_round" => { #[cfg(feature="master")] @@ -306,6 +316,18 @@ pub fn adjust_intrinsic_return_value<'a, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc, return_value = builder.context.new_struct_constructor(None, struct_type.as_type(), None, &[return_value, last_arg.dereference(None).to_rvalue()]); } }, + "__builtin_ia32_stmxcsr" => { + // The builtin __builtin_ia32_stmxcsr returns a value while llvm.x86.sse.stmxcsr writes + // the result in its pointer argument. + // We removed the argument since __builtin_ia32_stmxcsr takes no arguments, so we need + // to get back the original argument to get the pointer we need to write the result to. + let uint_ptr_type = builder.uint_type.make_pointer(); + let ptr = builder.context.new_cast(None, orig_args[0], uint_ptr_type); + builder.llbb().add_assignment(None, ptr.dereference(None), return_value); + // The return value was assigned to the result pointer above. In order to not call the + // builtin twice, we overwrite the return value with a dummy value. + return_value = builder.context.new_rvalue_zero(builder.int_type); + }, _ => (), } From 9a6b75515e64d943d0812c4ace5eab570dfded78 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 27 Aug 2022 09:22:17 -0400 Subject: [PATCH 151/356] Fix merge conflicts --- .github/workflows/ci.yml | 5 ++ example/mini_core.rs | 57 +++++++++++++------ ...0024-core-Disable-portable-simd-test.patch | 24 ++++---- rust-toolchain | 2 +- src/builder.rs | 9 +++ 5 files changed, 70 insertions(+), 27 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 4be75efd73a4..8b36fa0c1c7c 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -56,11 +56,13 @@ jobs: echo $(readlink -f gcc-build) > gcc_path # NOTE: the filename is still libgccjit.so even when the artifact name is different. ln gcc-build/libgccjit.so gcc-build/libgccjit.so.0 + - name: Set env run: | echo "LIBRARY_PATH=$(cat gcc_path)" >> $GITHUB_ENV echo "LD_LIBRARY_PATH=$(cat gcc_path)" >> $GITHUB_ENV echo "workspace="$GITHUB_WORKSPACE >> $GITHUB_ENV + - name: Set RUST_COMPILER_RT_ROOT run: echo "RUST_COMPILER_RT_ROOT="${{ env.workspace }}/llvm/compiler-rt >> $GITHUB_ENV @@ -108,11 +110,13 @@ jobs: ./build.sh ${{ matrix.libgccjit_version.extra }} cargo test ${{ matrix.libgccjit_version.extra }} ./clean_all.sh + - name: Prepare dependencies run: | git config --global user.email "user@example.com" git config --global user.name "User" ./prepare.sh + # Compile is a separate step, as the actions-rs/cargo action supports error annotations - name: Compile uses: actions-rs/cargo@v1.0.3 @@ -127,6 +131,7 @@ jobs: - name: Run tests run: | ./test.sh --release --clean --build-sysroot ${{ matrix.commands }} ${{ matrix.libgccjit_version.extra }} + duplicates: runs-on: ubuntu-latest steps: diff --git a/example/mini_core.rs b/example/mini_core.rs index ddcbb0d9fc7e..b23ecda35d3e 100644 --- a/example/mini_core.rs +++ b/example/mini_core.rs @@ -1,6 +1,6 @@ #![feature( no_core, lang_items, intrinsics, unboxed_closures, type_ascription, extern_types, - untagged_unions, decl_macro, rustc_attrs, transparent_unions, auto_traits, + decl_macro, rustc_attrs, transparent_unions, auto_traits, thread_local )] #![no_core] @@ -39,14 +39,14 @@ impl<'a, T: ?Sized+Unsize, U: ?Sized> DispatchFromDyn<&'a mut U> for &'a mut impl, U: ?Sized> DispatchFromDyn<*const U> for *const T {} // *mut T -> *mut U impl, U: ?Sized> DispatchFromDyn<*mut U> for *mut T {} -impl, U: ?Sized> DispatchFromDyn> for Box {} +impl, U: ?Sized> DispatchFromDyn> for Box {} #[lang = "receiver"] pub trait Receiver {} impl Receiver for &T {} impl Receiver for &mut T {} -impl Receiver for Box {} +impl Receiver for Box {} #[lang = "copy"] pub unsafe trait Copy {} @@ -411,7 +411,15 @@ pub trait FnMut: FnOnce { #[lang = "panic"] #[track_caller] -pub fn panic(_msg: &str) -> ! { +pub fn panic(_msg: &'static str) -> ! { + unsafe { + libc::puts("Panicking\n\0" as *const str as *const u8); + intrinsics::abort(); + } +} + +#[lang = "panic_no_unwind"] +fn panic_no_unwind() -> ! { unsafe { libc::puts("Panicking\n\0" as *const str as *const u8); intrinsics::abort(); @@ -450,17 +458,32 @@ pub trait Deref { pub trait Allocator { } +impl Allocator for () {} + pub struct Global; impl Allocator for Global {} -#[lang = "owned_box"] -pub struct Box< - T: ?Sized, - A: Allocator = Global, ->(*mut T, A); +#[repr(transparent)] +#[rustc_layout_scalar_valid_range_start(1)] +#[rustc_nonnull_optimization_guaranteed] +pub struct NonNull(pub *const T); -impl, U: ?Sized> CoerceUnsized> for Box {} +impl CoerceUnsized> for NonNull where T: Unsize {} +impl DispatchFromDyn> for NonNull where T: Unsize {} + +pub struct Unique { + pub pointer: NonNull, + pub _marker: PhantomData, +} + +impl CoerceUnsized> for Unique where T: Unsize {} +impl DispatchFromDyn> for Unique where T: Unsize {} + +#[lang = "owned_box"] +pub struct Box(Unique, A); + +impl, U: ?Sized, A: Allocator> CoerceUnsized> for Box {} impl Drop for Box { fn drop(&mut self) { @@ -468,7 +491,7 @@ impl Drop for Box { } } -impl Deref for Box { +impl Deref for Box { type Target = T; fn deref(&self) -> &Self::Target { @@ -482,8 +505,8 @@ unsafe fn allocate(size: usize, _align: usize) -> *mut u8 { } #[lang = "box_free"] -unsafe fn box_free(ptr: *mut T, alloc: A) { - libc::free(ptr as *mut u8); +unsafe fn box_free(ptr: Unique, _alloc: ()) { + libc::free(ptr.pointer.0 as *mut u8); } #[lang = "drop"] @@ -505,16 +528,18 @@ pub union MaybeUninit { } pub mod intrinsics { + use crate::Sized; + extern "rust-intrinsic" { pub fn abort() -> !; pub fn size_of() -> usize; - pub fn size_of_val(val: *const T) -> usize; + pub fn size_of_val(val: *const T) -> usize; pub fn min_align_of() -> usize; - pub fn min_align_of_val(val: *const T) -> usize; + pub fn min_align_of_val(val: *const T) -> usize; pub fn copy(src: *const T, dst: *mut T, count: usize); pub fn transmute(e: T) -> U; pub fn ctlz_nonzero(x: T) -> T; - pub fn needs_drop() -> bool; + pub fn needs_drop() -> bool; pub fn bitreverse(x: T) -> T; pub fn bswap(x: T) -> T; pub fn write_bytes(dst: *mut T, val: u8, count: usize); diff --git a/patches/0024-core-Disable-portable-simd-test.patch b/patches/0024-core-Disable-portable-simd-test.patch index c59a40df0398..7ea0eebe6a12 100644 --- a/patches/0024-core-Disable-portable-simd-test.patch +++ b/patches/0024-core-Disable-portable-simd-test.patch @@ -1,24 +1,25 @@ -From b1ae000f6da1abd3b8e9b80c40bc11c89b8ae93c Mon Sep 17 00:00:00 2001 -From: bjorn3 -Date: Thu, 30 Dec 2021 16:54:40 +0100 -Subject: [PATCH] [core] Disable portable-simd test +From f845df4056f5ba16b9f5bd703460c4ac40ea03b9 Mon Sep 17 00:00:00 2001 +From: Antoni Boucher +Date: Fri, 26 Aug 2022 20:38:58 -0400 +Subject: [PATCH] Edit --- - library/core/tests/lib.rs | 1 - - 1 file changed, 1 deletion(-) + library/core/tests/lib.rs | 2 -- + 1 file changed, 2 deletions(-) diff --git a/library/core/tests/lib.rs b/library/core/tests/lib.rs -index 06c7be0..359e2e7 100644 +index 59510d3..179bf26 100644 --- a/library/core/tests/lib.rs +++ b/library/core/tests/lib.rs -@@ -75,7 +75,6 @@ - #![feature(never_type)] +@@ -77,7 +77,6 @@ #![feature(unwrap_infallible)] + #![feature(result_into_ok_or_err)] + #![feature(pointer_byte_offsets)] -#![feature(portable_simd)] #![feature(ptr_metadata)] #![feature(once_cell)] #![feature(option_result_contains)] -@@ -127,7 +126,6 @@ mod pin; +@@ -135,7 +134,6 @@ mod pin; mod pin_macro; mod ptr; mod result; @@ -26,3 +27,6 @@ index 06c7be0..359e2e7 100644 mod slice; mod str; mod str_lossy; +-- +2.26.2.7.g19db9cfb68.dirty + diff --git a/rust-toolchain b/rust-toolchain index b20aeb979ad7..775d9906bf41 100644 --- a/rust-toolchain +++ b/rust-toolchain @@ -1,3 +1,3 @@ [toolchain] -channel = "nightly-2022-06-06" +channel = "nightly-2022-08-26" components = ["rust-src", "rustc-dev", "llvm-tools-preview"] diff --git a/src/builder.rs b/src/builder.rs index 3608b97fcf6e..41df7e647b5f 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1185,6 +1185,15 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { fn atomic_cmpxchg(&mut self, dst: RValue<'gcc>, cmp: RValue<'gcc>, src: RValue<'gcc>, order: AtomicOrdering, failure_order: AtomicOrdering, weak: bool) -> RValue<'gcc> { let expected = self.current_func().new_local(None, cmp.get_type(), "expected"); self.llbb().add_assignment(None, expected, cmp); + // NOTE: gcc doesn't support a failure memory model that is stronger than the success + // memory model. + let order = + if failure_order as i32 > order as i32 { + failure_order + } + else { + order + }; let success = self.compare_exchange(dst, expected, src, order, failure_order, weak); let pair_type = self.cx.type_struct(&[src.get_type(), self.bool_type], false); From 7d01d51e9f77ce1416ff1268831c8a201492dae1 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 27 Aug 2022 09:32:45 -0400 Subject: [PATCH 152/356] Fix tests --- tests/run/array.rs | 2 +- tests/run/assign.rs | 2 +- tests/run/closure.rs | 2 +- tests/run/condition.rs | 2 +- tests/run/fun_ptr.rs | 2 +- tests/run/int_overflow.rs | 2 +- tests/run/mut_ref.rs | 2 +- tests/run/operations.rs | 2 +- tests/run/ptr_cast.rs | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/tests/run/array.rs b/tests/run/array.rs index 8b621d8a3530..c53d98340f04 100644 --- a/tests/run/array.rs +++ b/tests/run/array.rs @@ -79,7 +79,7 @@ pub unsafe fn drop_in_place(to_drop: *mut T) { #[lang = "panic"] #[track_caller] #[no_mangle] -pub fn panic(_msg: &str) -> ! { +pub fn panic(_msg: &'static str) -> ! { unsafe { libc::puts("Panicking\0" as *const str as *const u8); intrinsics::abort(); diff --git a/tests/run/assign.rs b/tests/run/assign.rs index eb38a8a38357..b95a7b714153 100644 --- a/tests/run/assign.rs +++ b/tests/run/assign.rs @@ -64,7 +64,7 @@ mod intrinsics { #[lang = "panic"] #[track_caller] #[no_mangle] -pub fn panic(_msg: &str) -> ! { +pub fn panic(_msg: &'static str) -> ! { unsafe { libc::puts("Panicking\0" as *const str as *const u8); libc::fflush(libc::stdout); diff --git a/tests/run/closure.rs b/tests/run/closure.rs index 7121a5f0d522..4d01d879dc1d 100644 --- a/tests/run/closure.rs +++ b/tests/run/closure.rs @@ -177,7 +177,7 @@ impl Add for isize { #[lang = "panic"] #[track_caller] #[no_mangle] -pub fn panic(_msg: &str) -> ! { +pub fn panic(_msg: &'static str) -> ! { unsafe { libc::puts("Panicking\0" as *const str as *const u8); intrinsics::abort(); diff --git a/tests/run/condition.rs b/tests/run/condition.rs index 6a2e2d5bb11a..38b3084cb6c7 100644 --- a/tests/run/condition.rs +++ b/tests/run/condition.rs @@ -82,7 +82,7 @@ pub unsafe fn drop_in_place(to_drop: *mut T) { #[lang = "panic"] #[track_caller] #[no_mangle] -pub fn panic(_msg: &str) -> ! { +pub fn panic(_msg: &'static str) -> ! { unsafe { libc::puts("Panicking\0" as *const str as *const u8); intrinsics::abort(); diff --git a/tests/run/fun_ptr.rs b/tests/run/fun_ptr.rs index a226fff79e51..995fc5ca5d23 100644 --- a/tests/run/fun_ptr.rs +++ b/tests/run/fun_ptr.rs @@ -76,7 +76,7 @@ pub unsafe fn drop_in_place(to_drop: *mut T) { #[lang = "panic"] #[track_caller] #[no_mangle] -pub fn panic(_msg: &str) -> ! { +pub fn panic(_msg: &'static str) -> ! { unsafe { libc::puts("Panicking\0" as *const str as *const u8); intrinsics::abort(); diff --git a/tests/run/int_overflow.rs b/tests/run/int_overflow.rs index ea2c5add962a..4ca623625395 100644 --- a/tests/run/int_overflow.rs +++ b/tests/run/int_overflow.rs @@ -62,7 +62,7 @@ mod intrinsics { #[lang = "panic"] #[track_caller] #[no_mangle] -pub fn panic(_msg: &str) -> ! { +pub fn panic(_msg: &'static str) -> ! { unsafe { // Panicking is expected iff overflow checking is enabled. #[cfg(debug_assertions)] diff --git a/tests/run/mut_ref.rs b/tests/run/mut_ref.rs index 52de20021f3e..814bb1a612e4 100644 --- a/tests/run/mut_ref.rs +++ b/tests/run/mut_ref.rs @@ -66,7 +66,7 @@ mod intrinsics { #[lang = "panic"] #[track_caller] #[no_mangle] -pub fn panic(_msg: &str) -> ! { +pub fn panic(_msg: &'static str) -> ! { unsafe { libc::puts("Panicking\0" as *const str as *const u8); libc::fflush(libc::stdout); diff --git a/tests/run/operations.rs b/tests/run/operations.rs index e078b37b4aba..affe12067ffe 100644 --- a/tests/run/operations.rs +++ b/tests/run/operations.rs @@ -72,7 +72,7 @@ mod intrinsics { #[lang = "panic"] #[track_caller] #[no_mangle] -pub fn panic(_msg: &str) -> ! { +pub fn panic(_msg: &'static str) -> ! { unsafe { libc::puts("Panicking\0" as *const str as *const u8); libc::fflush(libc::stdout); diff --git a/tests/run/ptr_cast.rs b/tests/run/ptr_cast.rs index 6ac099ea145c..08481739a7f9 100644 --- a/tests/run/ptr_cast.rs +++ b/tests/run/ptr_cast.rs @@ -76,7 +76,7 @@ pub unsafe fn drop_in_place(to_drop: *mut T) { #[lang = "panic"] #[track_caller] #[no_mangle] -pub fn panic(_msg: &str) -> ! { +pub fn panic(_msg: &'static str) -> ! { unsafe { libc::puts("Panicking\0" as *const str as *const u8); intrinsics::abort(); From eed6603c0ade362b00d129330c689ec27ca0a500 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 27 Aug 2022 11:10:34 -0400 Subject: [PATCH 153/356] Fix tests --- failing-ui-tests.txt | 10 +++++----- test.sh | 7 ++++--- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index 717d0d39331f..0e34110a0603 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -9,28 +9,28 @@ src/test/ui/allocator/xcrate-use.rs src/test/ui/allocator/xcrate-use2.rs src/test/ui/asm/may_unwind.rs src/test/ui/asm/x86_64/const.rs +src/test/ui/asm/x86_64/issue-96797.rs src/test/ui/asm/x86_64/multiple-clobber-abi.rs src/test/ui/async-await/async-fn-size-moved-locals.rs src/test/ui/async-await/async-fn-size-uninit-locals.rs -src/test/ui/backtrace.rs src/test/ui/cfg/cfg-panic.rs src/test/ui/debuginfo/debuginfo-emit-llvm-ir-and-split-debuginfo.rs src/test/ui/functions-closures/parallel-codegen-closures.rs src/test/ui/generator/size-moved-locals.rs -src/test/ui/issues/issue-32518.rs +src/test/ui/issues/issue-40883.rs src/test/ui/issues/issue-47364.rs -src/test/ui/issues/issue-74564-if-expr-stack-overflow.rs src/test/ui/linkage-attr/linkage1.rs src/test/ui/lto/dylib-works.rs -src/test/ui/mir/mir_heavy_promoted.rs +src/test/ui/macros/rfc-2011-nicer-assert-messages/all-not-available-cases.rs +src/test/ui/macros/rfc-2011-nicer-assert-messages/assert-without-captures-does-not-create-unnecessary-code.rs src/test/ui/numbers-arithmetic/saturating-float-casts.rs src/test/ui/polymorphization/promoted-function.rs +src/test/ui/process/nofile-limit.rs src/test/ui/runtime/rt-explody-panic-payloads.rs src/test/ui/sepcomp/sepcomp-cci.rs src/test/ui/sepcomp/sepcomp-extern.rs src/test/ui/sepcomp/sepcomp-fns-backwards.rs src/test/ui/sepcomp/sepcomp-fns.rs -src/test/ui/sepcomp/sepcomp-lib.rs src/test/ui/sepcomp/sepcomp-statics.rs src/test/ui/simd/generics.rs src/test/ui/simd/intrinsic/float-math-pass.rs diff --git a/test.sh b/test.sh index 06f608ad422a..392c07f9f626 100755 --- a/test.sh +++ b/test.sh @@ -327,6 +327,7 @@ EOF git checkout src/test/ui/lto/auxiliary/dylib.rs git checkout src/test/ui/type-alias-impl-trait/auxiliary/cross_crate_ice.rs git checkout src/test/ui/type-alias-impl-trait/auxiliary/cross_crate_ice2.rs + git checkout src/test/ui/macros/rfc-2011-nicer-assert-messages/auxiliary/common.rs RUSTC_ARGS="-Zpanic-abort-tests -Csymbol-mangling-version=v0 -Zcodegen-backend="$(pwd)"/../target/"$CHANNEL"/librustc_codegen_gcc."$dylib_ext" --sysroot "$(pwd)"/../build_sysroot/sysroot -Cpanic=abort" @@ -338,7 +339,7 @@ EOF xargs -a ../failing-ui-tests.txt -d'\n' rm else # Removing all tests. - find src/test/ui -type f -name '*.rs' -exec rm {} \; + find src/test/ui -type f -name '*.rs' -not -path '*/auxiliary/*' -delete # Putting back only the failing ones. xargs -a ../failing-ui-tests.txt -d'\n' git checkout -- fi @@ -354,7 +355,7 @@ EOF count=$((count + 1)) split -d -l $count -a 1 ui_tests ui_tests.split # Removing all tests. - find src/test/ui -type f -name '*.rs' -not -path "*/auxiliary/*" -exec rm {} \; + find src/test/ui -type f -name '*.rs' -not -path "*/auxiliary/*" -delete # Putting back only the ones we want to test. xargs -a "ui_tests.split$current_part" -d'\n' git checkout -- fi @@ -372,7 +373,7 @@ function test_successful_rustc() { } function clean_ui_tests() { - find rust/build/x86_64-unknown-linux-gnu/test/ui/ -name stamp -exec rm -rf {} \; + find rust/build/x86_64-unknown-linux-gnu/test/ui/ -name stamp -delete } function all() { From 61a7b96c800c7f0a338b3f8f4b5b1e89f82b1668 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 27 Aug 2022 11:44:21 -0400 Subject: [PATCH 154/356] Disable test mir_heavy_promoted --- test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/test.sh b/test.sh index 392c07f9f626..ed43c645bd2d 100755 --- a/test.sh +++ b/test.sh @@ -321,6 +321,7 @@ EOF git checkout -- src/test/ui/issues/auxiliary/issue-3136-a.rs # contains //~ERROR, but shouldn't be removed rm -r src/test/ui/{abi*,extern/,panic-runtime/,panics/,unsized-locals/,proc-macro/,threads-sendsync/,thinlto/,borrowck/,chalkify/bugs/,test*,*lto*.rs,consts/const-float-bits-reject-conv.rs,consts/issue-miri-1910.rs} || true + rm src/test/ui/mir/mir_heavy_promoted.rs # this tests is oom-killed in the CI. for test in $(rg --files-with-matches "catch_unwind|should_panic|thread|lto" src/test/ui); do rm $test done From 4df874f73d329e2aa3ffa7800f26476499302ec6 Mon Sep 17 00:00:00 2001 From: Andy Sadler Date: Sun, 12 Jun 2022 01:06:58 -0500 Subject: [PATCH 155/356] simd: Implement missing reduction intrinsics Implements the following simd reduction intrinsics: - simd_reduce_add_ordered - simd_reduce_mul_ordered - simd_reduce_min_nanless - simd_reduce_max_nanless - simd_reduce_xor - simd_reduce_any - simd_reduce_all Also fixes the ordering of simd_reduce_min and simd_reduce_max, which were tested to be flipped. Both simd_reduce_min_nanless and simd_reduce_max_nanless are identical to their non-nanless variants for the time being. An attempt was made at a more optimal codegen solution based on vector_reduce_op. However, this approach ran into masking issues for floating-point vector types, which appears to be broken for the same reason that comparison operations such as simd_lt are broken for floating-point vector types. More investigation is required, however, to determine a root cause and appropriate fix. This should be enough to pass the generic-reduction-pass.rs ui tests with the 'master' feature enabled. Signed-off-by: Andy Sadler --- failing-ui-tests.txt | 1 - failing-ui-tests12.txt | 1 + src/builder.rs | 77 ++++++++++++++++++++++++++++++++++++++++-- src/intrinsic/simd.rs | 39 +++++++++++++++------ src/type_.rs | 4 --- 5 files changed, 105 insertions(+), 17 deletions(-) diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index 0e34110a0603..6d36c9630134 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -40,7 +40,6 @@ src/test/ui/simd/intrinsic/generic-as.rs src/test/ui/simd/intrinsic/generic-bitmask-pass.rs src/test/ui/simd/intrinsic/generic-comparison-pass.rs src/test/ui/simd/intrinsic/generic-gather-pass.rs -src/test/ui/simd/intrinsic/generic-reduction-pass.rs src/test/ui/simd/intrinsic/generic-select-pass.rs src/test/ui/simd/issue-17170.rs src/test/ui/simd/issue-39720.rs diff --git a/failing-ui-tests12.txt b/failing-ui-tests12.txt index 0a50c0a2ce13..d0d8a08421ac 100644 --- a/failing-ui-tests12.txt +++ b/failing-ui-tests12.txt @@ -11,6 +11,7 @@ src/test/ui/simd/intrinsic/generic-arithmetic-saturating-pass.rs src/test/ui/simd/intrinsic/generic-cast-pass.rs src/test/ui/simd/intrinsic/generic-cast-pointer-width.rs src/test/ui/simd/intrinsic/generic-elements-pass.rs +src/test/ui/simd/intrinsic/generic-reduction-pass.rs src/test/ui/simd/intrinsic/inlining-issue67557-ice.rs src/test/ui/simd/intrinsic/inlining-issue67557.rs src/test/ui/simd/monomorphize-shuffle-index.rs diff --git a/src/builder.rs b/src/builder.rs index 41df7e647b5f..899eff064120 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1460,15 +1460,47 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { unimplemented!(); } + #[cfg(feature="master")] + pub fn vector_reduce_fadd(&mut self, acc: RValue<'gcc>, src: RValue<'gcc>) -> RValue<'gcc> { + let vector_type = src.get_type().unqualified().dyncast_vector().expect("vector type"); + let element_count = vector_type.get_num_units(); + (0..element_count).into_iter() + .map(|i| self.context + .new_vector_access(None, src, self.context.new_rvalue_from_int(self.int_type, i as _)) + .to_rvalue()) + .fold(acc, |x, i| x + i) + } + + #[cfg(not(feature="master"))] + pub fn vector_reduce_fadd(&mut self, _acc: RValue<'gcc>, _src: RValue<'gcc>) -> RValue<'gcc> { + unimplemented!(); + } + pub fn vector_reduce_fmul_fast(&mut self, _acc: RValue<'gcc>, _src: RValue<'gcc>) -> RValue<'gcc> { unimplemented!(); } + #[cfg(feature="master")] + pub fn vector_reduce_fmul(&mut self, acc: RValue<'gcc>, src: RValue<'gcc>) -> RValue<'gcc> { + let vector_type = src.get_type().unqualified().dyncast_vector().expect("vector type"); + let element_count = vector_type.get_num_units(); + (0..element_count).into_iter() + .map(|i| self.context + .new_vector_access(None, src, self.context.new_rvalue_from_int(self.int_type, i as _)) + .to_rvalue()) + .fold(acc, |x, i| x * i) + } + + #[cfg(not(feature="master"))] + pub fn vector_reduce_fmul(&mut self, _acc: RValue<'gcc>, _src: RValue<'gcc>) -> RValue<'gcc> { + unimplemented!() + } + // Inspired by Hacker's Delight min implementation. pub fn vector_reduce_min(&mut self, src: RValue<'gcc>) -> RValue<'gcc> { self.vector_reduce(src, |a, b, context| { let differences_or_zeros = difference_or_zero(a, b, context); - context.new_binary_op(None, BinaryOp::Minus, a.get_type(), a, differences_or_zeros) + context.new_binary_op(None, BinaryOp::Plus, b.get_type(), b, differences_or_zeros) }) } @@ -1476,10 +1508,51 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { pub fn vector_reduce_max(&mut self, src: RValue<'gcc>) -> RValue<'gcc> { self.vector_reduce(src, |a, b, context| { let differences_or_zeros = difference_or_zero(a, b, context); - context.new_binary_op(None, BinaryOp::Plus, b.get_type(), b, differences_or_zeros) + context.new_binary_op(None, BinaryOp::Minus, a.get_type(), a, differences_or_zeros) }) } + #[cfg(feature="master")] + pub fn vector_reduce_fmin(&mut self, src: RValue<'gcc>) -> RValue<'gcc> { + let vector_type = src.get_type().unqualified().dyncast_vector().expect("vector type"); + let element_count = vector_type.get_num_units(); + let mut acc = self.context.new_vector_access(None, src, self.context.new_rvalue_zero(self.int_type)).to_rvalue(); + for i in 1..element_count { + let elem = self.context + .new_vector_access(None, src, self.context.new_rvalue_from_int(self.int_type, i as _)) + .to_rvalue(); + let cmp = self.context.new_comparison(None, ComparisonOp::LessThan, acc, elem); + acc = self.select(cmp, acc, elem); + } + acc + } + + #[cfg(not(feature="master"))] + pub fn vector_reduce_fmin(&mut self, _src: RValue<'gcc>) -> RValue<'gcc> { + unimplemented!(); + } + + #[cfg(feature="master")] + pub fn vector_reduce_fmax(&mut self, src: RValue<'gcc>) -> RValue<'gcc> { + let vector_type = src.get_type().unqualified().dyncast_vector().expect("vector type"); + let element_count = vector_type.get_num_units(); + let mut acc = self.context.new_vector_access(None, src, self.context.new_rvalue_zero(self.int_type)).to_rvalue(); + for i in 1..element_count { + let elem = self.context + .new_vector_access(None, src, self.context.new_rvalue_from_int(self.int_type, i as _)) + .to_rvalue(); + let cmp = self.context.new_comparison(None, ComparisonOp::GreaterThan, acc, elem); + acc = self.select(cmp, acc, elem); + } + acc + } + + #[cfg(not(feature="master"))] + pub fn vector_reduce_fmax(&mut self, _src: RValue<'gcc>) -> RValue<'gcc> { + unimplemented!(); + } + + pub fn vector_select(&mut self, cond: RValue<'gcc>, then_val: RValue<'gcc>, else_val: RValue<'gcc>) -> RValue<'gcc> { // cond is a vector of integers, not of bools. let cond_type = cond.get_type(); diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index dbf6ee6d285d..8aed06869a90 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -2,7 +2,7 @@ use gccjit::{ToRValue, ComparisonOp, UnaryOp}; use gccjit::{BinaryOp, RValue, Type}; use rustc_codegen_ssa::base::compare_simd_types; -use rustc_codegen_ssa::common::{TypeKind, span_invalid_monomorphization_error}; +use rustc_codegen_ssa::common::{IntPredicate, TypeKind, span_invalid_monomorphization_error}; use rustc_codegen_ssa::mir::operand::OperandRef; use rustc_codegen_ssa::mir::place::PlaceRef; use rustc_codegen_ssa::traits::{BaseTypeMethods, BuilderMethods}; @@ -667,9 +667,24 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, mul, 1.0 ); + arith_red!( + simd_reduce_add_ordered: BinaryOp::Plus, + vector_reduce_fadd, + true, + add, + 0.0 + ); + arith_red!( + simd_reduce_mul_ordered: BinaryOp::Mult, + vector_reduce_fmul, + true, + mul, + 1.0 + ); + macro_rules! minmax_red { - ($name:ident: $reduction:ident) => { + ($name:ident: $int_red:ident, $float_red:ident) => { if name == sym::$name { require!( ret_ty == in_elem, @@ -679,7 +694,8 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, ret_ty ); return match in_elem.kind() { - ty::Int(_) | ty::Uint(_) | ty::Float(_) => Ok(bx.$reduction(args[0].immediate())), + ty::Int(_) | ty::Uint(_) => Ok(bx.$int_red(args[0].immediate())), + ty::Float(_) => Ok(bx.$float_red(args[0].immediate())), _ => return_error!( "unsupported {} from `{}` with element `{}` to `{}`", sym::$name, @@ -692,8 +708,11 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, }; } - minmax_red!(simd_reduce_min: vector_reduce_min); - minmax_red!(simd_reduce_max: vector_reduce_max); + minmax_red!(simd_reduce_min: vector_reduce_min, vector_reduce_fmin); + minmax_red!(simd_reduce_max: vector_reduce_max, vector_reduce_fmax); + // TODO(sadlerap): revisit these intrinsics to generate more optimal reductions + minmax_red!(simd_reduce_min_nanless: vector_reduce_min, vector_reduce_fmin); + minmax_red!(simd_reduce_max_nanless: vector_reduce_max, vector_reduce_fmax); macro_rules! bitwise_red { ($name:ident : $op:expr, $boolean:expr) => { @@ -719,15 +738,12 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, ), } - // boolean reductions operate on vectors of i1s: - let i1 = bx.type_i1(); - let i1xn = bx.type_vector(i1, in_len as u64); - bx.trunc(args[0].immediate(), i1xn) + args[0].immediate() }; return match in_elem.kind() { ty::Int(_) | ty::Uint(_) => { let r = bx.vector_reduce_op(input, $op); - Ok(if !$boolean { r } else { bx.zext(r, bx.type_bool()) }) + Ok(if !$boolean { r } else { bx.icmp(IntPredicate::IntNE, r, bx.context.new_rvalue_zero(r.get_type())) }) } _ => return_error!( "unsupported {} from `{}` with element `{}` to `{}`", @@ -743,6 +759,9 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, bitwise_red!(simd_reduce_and: BinaryOp::BitwiseAnd, false); bitwise_red!(simd_reduce_or: BinaryOp::BitwiseOr, false); + bitwise_red!(simd_reduce_xor: BinaryOp::BitwiseXor, false); + bitwise_red!(simd_reduce_all: BinaryOp::BitwiseAnd, true); + bitwise_red!(simd_reduce_any: BinaryOp::BitwiseOr, true); unimplemented!("simd {}", name); } diff --git a/src/type_.rs b/src/type_.rs index c97e9586005b..d7eca2a33df7 100644 --- a/src/type_.rs +++ b/src/type_.rs @@ -247,10 +247,6 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { self.context.new_array_type(None, ty, len) } - - pub fn type_bool(&self) -> Type<'gcc> { - self.context.new_type::() - } } pub fn struct_fields<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, layout: TyAndLayout<'tcx>) -> (Vec>, bool) { From e82c6a07fff616ffa0661dd3a6cee3e018a21588 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Thu, 25 Aug 2022 16:19:10 +0200 Subject: [PATCH 156/356] Regen intrinsics --- src/intrinsic/archs.rs | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/src/intrinsic/archs.rs b/src/intrinsic/archs.rs index 9d674eb87eb3..3879fcb1d982 100644 --- a/src/intrinsic/archs.rs +++ b/src/intrinsic/archs.rs @@ -58,12 +58,20 @@ match name { "llvm.amdgcn.cubema" => "__builtin_amdgcn_cubema", "llvm.amdgcn.cubesc" => "__builtin_amdgcn_cubesc", "llvm.amdgcn.cubetc" => "__builtin_amdgcn_cubetc", + "llvm.amdgcn.cvt.f32.bf8" => "__builtin_amdgcn_cvt_f32_bf8", + "llvm.amdgcn.cvt.f32.fp8" => "__builtin_amdgcn_cvt_f32_fp8", + "llvm.amdgcn.cvt.pk.bf8.f32" => "__builtin_amdgcn_cvt_pk_bf8_f32", + "llvm.amdgcn.cvt.pk.f32.bf8" => "__builtin_amdgcn_cvt_pk_f32_bf8", + "llvm.amdgcn.cvt.pk.f32.fp8" => "__builtin_amdgcn_cvt_pk_f32_fp8", + "llvm.amdgcn.cvt.pk.fp8.f32" => "__builtin_amdgcn_cvt_pk_fp8_f32", "llvm.amdgcn.cvt.pk.i16" => "__builtin_amdgcn_cvt_pk_i16", "llvm.amdgcn.cvt.pk.u16" => "__builtin_amdgcn_cvt_pk_u16", "llvm.amdgcn.cvt.pk.u8.f32" => "__builtin_amdgcn_cvt_pk_u8_f32", "llvm.amdgcn.cvt.pknorm.i16" => "__builtin_amdgcn_cvt_pknorm_i16", "llvm.amdgcn.cvt.pknorm.u16" => "__builtin_amdgcn_cvt_pknorm_u16", "llvm.amdgcn.cvt.pkrtz" => "__builtin_amdgcn_cvt_pkrtz", + "llvm.amdgcn.cvt.sr.bf8.f32" => "__builtin_amdgcn_cvt_sr_bf8_f32", + "llvm.amdgcn.cvt.sr.fp8.f32" => "__builtin_amdgcn_cvt_sr_fp8_f32", "llvm.amdgcn.dispatch.id" => "__builtin_amdgcn_dispatch_id", "llvm.amdgcn.ds.add.gs.reg.rtn" => "__builtin_amdgcn_ds_add_gs_reg_rtn", "llvm.amdgcn.ds.bpermute" => "__builtin_amdgcn_ds_bpermute", @@ -85,6 +93,7 @@ match name { "llvm.amdgcn.fmed3" => "__builtin_amdgcn_fmed3", "llvm.amdgcn.fmul.legacy" => "__builtin_amdgcn_fmul_legacy", "llvm.amdgcn.groupstaticsize" => "__builtin_amdgcn_groupstaticsize", + "llvm.amdgcn.iglp.opt" => "__builtin_amdgcn_iglp_opt", "llvm.amdgcn.implicit.buffer.ptr" => "__builtin_amdgcn_implicit_buffer_ptr", "llvm.amdgcn.implicitarg.ptr" => "__builtin_amdgcn_implicitarg_ptr", "llvm.amdgcn.interp.mov" => "__builtin_amdgcn_interp_mov", @@ -102,11 +111,19 @@ match name { "llvm.amdgcn.mfma.f32.16x16x16f16" => "__builtin_amdgcn_mfma_f32_16x16x16f16", "llvm.amdgcn.mfma.f32.16x16x1f32" => "__builtin_amdgcn_mfma_f32_16x16x1f32", "llvm.amdgcn.mfma.f32.16x16x2bf16" => "__builtin_amdgcn_mfma_f32_16x16x2bf16", + "llvm.amdgcn.mfma.f32.16x16x32.bf8.bf8" => "__builtin_amdgcn_mfma_f32_16x16x32_bf8_bf8", + "llvm.amdgcn.mfma.f32.16x16x32.bf8.fp8" => "__builtin_amdgcn_mfma_f32_16x16x32_bf8_fp8", + "llvm.amdgcn.mfma.f32.16x16x32.fp8.bf8" => "__builtin_amdgcn_mfma_f32_16x16x32_fp8_bf8", + "llvm.amdgcn.mfma.f32.16x16x32.fp8.fp8" => "__builtin_amdgcn_mfma_f32_16x16x32_fp8_fp8", "llvm.amdgcn.mfma.f32.16x16x4bf16.1k" => "__builtin_amdgcn_mfma_f32_16x16x4bf16_1k", "llvm.amdgcn.mfma.f32.16x16x4f16" => "__builtin_amdgcn_mfma_f32_16x16x4f16", "llvm.amdgcn.mfma.f32.16x16x4f32" => "__builtin_amdgcn_mfma_f32_16x16x4f32", "llvm.amdgcn.mfma.f32.16x16x8.xf32" => "__builtin_amdgcn_mfma_f32_16x16x8_xf32", "llvm.amdgcn.mfma.f32.16x16x8bf16" => "__builtin_amdgcn_mfma_f32_16x16x8bf16", + "llvm.amdgcn.mfma.f32.32x32x16.bf8.bf8" => "__builtin_amdgcn_mfma_f32_32x32x16_bf8_bf8", + "llvm.amdgcn.mfma.f32.32x32x16.bf8.fp8" => "__builtin_amdgcn_mfma_f32_32x32x16_bf8_fp8", + "llvm.amdgcn.mfma.f32.32x32x16.fp8.bf8" => "__builtin_amdgcn_mfma_f32_32x32x16_fp8_bf8", + "llvm.amdgcn.mfma.f32.32x32x16.fp8.fp8" => "__builtin_amdgcn_mfma_f32_32x32x16_fp8_fp8", "llvm.amdgcn.mfma.f32.32x32x1f32" => "__builtin_amdgcn_mfma_f32_32x32x1f32", "llvm.amdgcn.mfma.f32.32x32x2bf16" => "__builtin_amdgcn_mfma_f32_32x32x2bf16", "llvm.amdgcn.mfma.f32.32x32x2f32" => "__builtin_amdgcn_mfma_f32_32x32x2f32", @@ -163,13 +180,22 @@ match name { "llvm.amdgcn.sad.u16" => "__builtin_amdgcn_sad_u16", "llvm.amdgcn.sad.u8" => "__builtin_amdgcn_sad_u8", "llvm.amdgcn.sched.barrier" => "__builtin_amdgcn_sched_barrier", + "llvm.amdgcn.sched.group.barrier" => "__builtin_amdgcn_sched_group_barrier", "llvm.amdgcn.sdot2" => "__builtin_amdgcn_sdot2", "llvm.amdgcn.sdot4" => "__builtin_amdgcn_sdot4", "llvm.amdgcn.sdot8" => "__builtin_amdgcn_sdot8", "llvm.amdgcn.smfmac.f32.16x16x32.bf16" => "__builtin_amdgcn_smfmac_f32_16x16x32_bf16", "llvm.amdgcn.smfmac.f32.16x16x32.f16" => "__builtin_amdgcn_smfmac_f32_16x16x32_f16", + "llvm.amdgcn.smfmac.f32.16x16x64.bf8.bf8" => "__builtin_amdgcn_smfmac_f32_16x16x64_bf8_bf8", + "llvm.amdgcn.smfmac.f32.16x16x64.bf8.fp8" => "__builtin_amdgcn_smfmac_f32_16x16x64_bf8_fp8", + "llvm.amdgcn.smfmac.f32.16x16x64.fp8.bf8" => "__builtin_amdgcn_smfmac_f32_16x16x64_fp8_bf8", + "llvm.amdgcn.smfmac.f32.16x16x64.fp8.fp8" => "__builtin_amdgcn_smfmac_f32_16x16x64_fp8_fp8", "llvm.amdgcn.smfmac.f32.32x32x16.bf16" => "__builtin_amdgcn_smfmac_f32_32x32x16_bf16", "llvm.amdgcn.smfmac.f32.32x32x16.f16" => "__builtin_amdgcn_smfmac_f32_32x32x16_f16", + "llvm.amdgcn.smfmac.f32.32x32x32.bf8.bf8" => "__builtin_amdgcn_smfmac_f32_32x32x32_bf8_bf8", + "llvm.amdgcn.smfmac.f32.32x32x32.bf8.fp8" => "__builtin_amdgcn_smfmac_f32_32x32x32_bf8_fp8", + "llvm.amdgcn.smfmac.f32.32x32x32.fp8.bf8" => "__builtin_amdgcn_smfmac_f32_32x32x32_fp8_bf8", + "llvm.amdgcn.smfmac.f32.32x32x32.fp8.fp8" => "__builtin_amdgcn_smfmac_f32_32x32x32_fp8_fp8", "llvm.amdgcn.smfmac.i32.16x16x64.i8" => "__builtin_amdgcn_smfmac_i32_16x16x64_i8", "llvm.amdgcn.smfmac.i32.32x32x32.i8" => "__builtin_amdgcn_smfmac_i32_32x32x32_i8", "llvm.amdgcn.sudot4" => "__builtin_amdgcn_sudot4", @@ -296,6 +322,8 @@ match name { "llvm.bpf.pseudo" => "__builtin_bpf_pseudo", // cuda "llvm.cuda.syncthreads" => "__syncthreads", + // dx + "llvm.dx.create.handle" => "__builtin_hlsl_create_handle", // hexagon "llvm.hexagon.A2.abs" => "__builtin_HEXAGON_A2_abs", "llvm.hexagon.A2.absp" => "__builtin_HEXAGON_A2_absp", @@ -7545,6 +7573,7 @@ match name { "llvm.x86.rdpid" => "__builtin_ia32_rdpid", "llvm.x86.rdpkru" => "__builtin_ia32_rdpkru", "llvm.x86.rdpmc" => "__builtin_ia32_rdpmc", + "llvm.x86.rdpru" => "__builtin_ia32_rdpru", "llvm.x86.rdsspd" => "__builtin_ia32_rdsspd", "llvm.x86.rdsspq" => "__builtin_ia32_rdsspq", "llvm.x86.rdtsc" => "__builtin_ia32_rdtsc", From 5c2dec038c21de940b6080203d8e4281a7f2c912 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 27 Aug 2022 15:39:23 -0400 Subject: [PATCH 157/356] Add used function attribute from inline asm --- Cargo.lock | 4 ++-- src/asm.rs | 3 +++ src/consts.rs | 15 ++++++++++++--- 3 files changed, 17 insertions(+), 5 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 3245f5843e54..10d2542f8b5a 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -41,7 +41,7 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" -source = "git+https://github.com/antoyo/gccjit.rs#1a60fe3918a5b3b0983c1ea09f4b9445001a6468" +source = "git+https://github.com/antoyo/gccjit.rs#f30cc2bd330f4fda3d625f305bdfd7e523e2d8f8" dependencies = [ "gccjit_sys", ] @@ -49,7 +49,7 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" -source = "git+https://github.com/antoyo/gccjit.rs#1a60fe3918a5b3b0983c1ea09f4b9445001a6468" +source = "git+https://github.com/antoyo/gccjit.rs#f30cc2bd330f4fda3d625f305bdfd7e523e2d8f8" dependencies = [ "libc 0.1.12", ] diff --git a/src/asm.rs b/src/asm.rs index fa40aa80804a..eb37488a6c5c 100644 --- a/src/asm.rs +++ b/src/asm.rs @@ -718,6 +718,8 @@ impl<'gcc, 'tcx> AsmMethods<'tcx> for CodegenCx<'gcc, 'tcx> { } GlobalAsmOperandRef::SymFn { instance } => { + let function = self.rvalue_as_function(get_fn(self, instance)); + self.add_used_function(function); // TODO(@Amanieu): Additional mangling is needed on // some targets to add a leading underscore (Mach-O) // or byte count suffixes (x86 Windows). @@ -726,6 +728,7 @@ impl<'gcc, 'tcx> AsmMethods<'tcx> for CodegenCx<'gcc, 'tcx> { } GlobalAsmOperandRef::SymStatic { def_id } => { + // TODO(antoyo): set the global variable as used. // TODO(@Amanieu): Additional mangling is needed on // some targets to add a leading underscore (Mach-O). let instance = Instance::mono(self.tcx, def_id); diff --git a/src/consts.rs b/src/consts.rs index e83cf53f48ef..9307d280f61c 100644 --- a/src/consts.rs +++ b/src/consts.rs @@ -1,4 +1,6 @@ -use gccjit::{GlobalKind, LValue, RValue, ToRValue, Type}; +#[cfg(feature = "master")] +use gccjit::FnAttribute; +use gccjit::{Function, GlobalKind, LValue, RValue, ToRValue, Type}; use rustc_codegen_ssa::traits::{BaseTypeMethods, ConstMethods, DerivedTypeMethods, StaticMethods}; use rustc_hir as hir; use rustc_hir::Node; @@ -159,12 +161,19 @@ impl<'gcc, 'tcx> StaticMethods for CodegenCx<'gcc, 'tcx> { // TODO(antoyo) } - fn add_compiler_used_global(&self, _global: RValue<'gcc>) { - // TODO(antoyo) + fn add_compiler_used_global(&self, global: RValue<'gcc>) { + // NOTE: seems like GCC does not make the distinction between compiler.used and used. + self.add_used_global(global); } } impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { + #[cfg_attr(not(feature="master"), allow(unused_variables))] + pub fn add_used_function(&self, function: Function<'gcc>) { + #[cfg(feature = "master")] + function.add_attribute(FnAttribute::Used); + } + pub fn static_addr_of_mut(&self, cv: RValue<'gcc>, align: Align, kind: Option<&str>) -> RValue<'gcc> { let global = match kind { From fc56c544165d02e589369a97076ec64fe627a6b5 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 27 Aug 2022 12:12:06 -0400 Subject: [PATCH 158/356] Remove extra newline in asm --- failing-ui-tests.txt | 2 -- failing-ui-tests12.txt | 1 + src/asm.rs | 19 +++++++++---------- 3 files changed, 10 insertions(+), 12 deletions(-) diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index 6d36c9630134..9e88859593d4 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -8,8 +8,6 @@ src/test/ui/allocator/no_std-alloc-error-handler-default.rs src/test/ui/allocator/xcrate-use.rs src/test/ui/allocator/xcrate-use2.rs src/test/ui/asm/may_unwind.rs -src/test/ui/asm/x86_64/const.rs -src/test/ui/asm/x86_64/issue-96797.rs src/test/ui/asm/x86_64/multiple-clobber-abi.rs src/test/ui/async-await/async-fn-size-moved-locals.rs src/test/ui/async-await/async-fn-size-uninit-locals.rs diff --git a/failing-ui-tests12.txt b/failing-ui-tests12.txt index d0d8a08421ac..2aab9c80f8fb 100644 --- a/failing-ui-tests12.txt +++ b/failing-ui-tests12.txt @@ -1,3 +1,4 @@ +src/test/ui/asm/x86_64/issue-96797.rs src/test/ui/intrinsics/const-eval-select-x86_64.rs src/test/ui/packed/packed-struct-drop-aligned.rs src/test/ui/packed/packed-struct-generic-layout.rs diff --git a/src/asm.rs b/src/asm.rs index eb37488a6c5c..9d9b6a23d074 100644 --- a/src/asm.rs +++ b/src/asm.rs @@ -695,17 +695,16 @@ impl<'gcc, 'tcx> AsmMethods<'tcx> for CodegenCx<'gcc, 'tcx> { for piece in template { match *piece { InlineAsmTemplatePiece::String(ref string) => { - for line in string.lines() { + let mut index = 0; + while index < string.len() { // NOTE: gcc does not allow inline comment, so remove them. - let line = - if let Some(index) = line.rfind("//") { - &line[..index] - } - else { - line - }; - template_str.push_str(line); - template_str.push('\n'); + let comment_index = string[index..].find("//") + .map(|comment_index| comment_index + index) + .unwrap_or(string.len()); + template_str.push_str(&string[index..comment_index]); + index = string[comment_index..].find('\n') + .map(|index| index + comment_index) + .unwrap_or(string.len()); } }, InlineAsmTemplatePiece::Placeholder { operand_idx, modifier: _, span: _ } => { From 45ec5f267689ad71677abde6403c98a9fd6a3e82 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 28 Aug 2022 20:58:11 -0400 Subject: [PATCH 159/356] Fix bitcast to a type of a different size --- src/builder.rs | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index 899eff064120..d9b24b2dc350 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1364,22 +1364,17 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { vector_elements.push(self.context.new_rvalue_zero(mask_element_type)); } - let array_type = self.context.new_array_type(None, element_type, vec_num_units as i32); let result_type = self.context.new_vector_type(element_type, mask_num_units as u64); let (v1, v2) = if vec_num_units < mask_num_units { // NOTE: the mask needs to be the same length as the input vectors, so join the 2 // vectors and create a dummy second vector. - // TODO(antoyo): switch to using new_vector_access. - let array = self.context.new_bitcast(None, v1, array_type); let mut elements = vec![]; for i in 0..vec_num_units { - elements.push(self.context.new_array_access(None, array, self.context.new_rvalue_from_int(self.int_type, i as i32)).to_rvalue()); + elements.push(self.context.new_vector_access(None, v1, self.context.new_rvalue_from_int(self.int_type, i as i32)).to_rvalue()); } - // TODO(antoyo): switch to using new_vector_access. - let array = self.context.new_bitcast(None, v2, array_type); for i in 0..(mask_num_units - vec_num_units) { - elements.push(self.context.new_array_access(None, array, self.context.new_rvalue_from_int(self.int_type, i as i32)).to_rvalue()); + elements.push(self.context.new_vector_access(None, v2, self.context.new_rvalue_from_int(self.int_type, i as i32)).to_rvalue()); } let v1 = self.context.new_rvalue_from_vector(None, result_type, &elements); let zero = self.context.new_rvalue_zero(element_type); @@ -1399,10 +1394,8 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { // NOTE: if padding was added, only select the number of elements of the masks to // remove that padding in the result. let mut elements = vec![]; - // TODO(antoyo): switch to using new_vector_access. - let array = self.context.new_bitcast(None, result, array_type); for i in 0..mask_num_units { - elements.push(self.context.new_array_access(None, array, self.context.new_rvalue_from_int(self.int_type, i as i32)).to_rvalue()); + elements.push(self.context.new_vector_access(None, result, self.context.new_rvalue_from_int(self.int_type, i as i32)).to_rvalue()); } self.context.new_rvalue_from_vector(None, result_type, &elements) } From 1d3ca135d055dbda6c255227084296f3552b99a9 Mon Sep 17 00:00:00 2001 From: Andy Sadler Date: Tue, 30 Aug 2022 17:33:55 -0500 Subject: [PATCH 160/356] simd: implement simd_fmin/fmax This implements simd_fmin/fmax in a largely-optimal method. Signed-off-by: Andy Sadler --- failing-ui-tests.txt | 1 - failing-ui-tests12.txt | 1 + src/builder.rs | 32 ++++++++++++++++++++++++++++++++ src/intrinsic/simd.rs | 2 ++ 4 files changed, 35 insertions(+), 1 deletion(-) diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index 9e88859593d4..fc6dcfc7bc7b 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -32,7 +32,6 @@ src/test/ui/sepcomp/sepcomp-fns.rs src/test/ui/sepcomp/sepcomp-statics.rs src/test/ui/simd/generics.rs src/test/ui/simd/intrinsic/float-math-pass.rs -src/test/ui/simd/intrinsic/float-minmax-pass.rs src/test/ui/simd/intrinsic/generic-arithmetic-pass.rs src/test/ui/simd/intrinsic/generic-as.rs src/test/ui/simd/intrinsic/generic-bitmask-pass.rs diff --git a/failing-ui-tests12.txt b/failing-ui-tests12.txt index 2aab9c80f8fb..e7952f524124 100644 --- a/failing-ui-tests12.txt +++ b/failing-ui-tests12.txt @@ -8,6 +8,7 @@ src/test/ui/packed/packed-struct-size.rs src/test/ui/packed/packed-struct-vec.rs src/test/ui/packed/packed-tuple-struct-layout.rs src/test/ui/simd/array-type.rs +src/test/ui/simd/intrinsic/float-minmax-pass.rs src/test/ui/simd/intrinsic/generic-arithmetic-saturating-pass.rs src/test/ui/simd/intrinsic/generic-cast-pass.rs src/test/ui/simd/intrinsic/generic-cast-pointer-width.rs diff --git a/src/builder.rs b/src/builder.rs index d9b24b2dc350..52a4854aca3a 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1505,6 +1505,34 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { }) } + fn vector_extremum(&mut self, a: RValue<'gcc>, b: RValue<'gcc>, direction: ExtremumOperation) -> RValue<'gcc> { + let vector_type = a.get_type(); + + // mask out the NaNs in b and replace them with the corresponding lane in a, so when a and + // b get compared & spliced together, we get the numeric values instead of NaNs. + let b_nan_mask = self.context.new_comparison(None, ComparisonOp::NotEquals, b, b); + let mask_type = b_nan_mask.get_type(); + let b_nan_mask_inverted = self.context.new_unary_op(None, UnaryOp::BitwiseNegate, mask_type, b_nan_mask); + let a_cast = self.context.new_bitcast(None, a, mask_type); + let b_cast = self.context.new_bitcast(None, b, mask_type); + let res = (b_nan_mask & a_cast) | (b_nan_mask_inverted & b_cast); + let b = self.context.new_bitcast(None, res, vector_type); + + // now do the actual comparison + let comparison_op = match direction { + ExtremumOperation::Min => ComparisonOp::LessThan, + ExtremumOperation::Max => ComparisonOp::GreaterThan, + }; + let cmp = self.context.new_comparison(None, comparison_op, a, b); + let cmp_inverted = self.context.new_unary_op(None, UnaryOp::BitwiseNegate, cmp.get_type(), cmp); + let res = (cmp & a_cast) | (cmp_inverted & res); + self.context.new_bitcast(None, res, vector_type) + } + + pub fn vector_fmin(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { + self.vector_extremum(a, b, ExtremumOperation::Min) + } + #[cfg(feature="master")] pub fn vector_reduce_fmin(&mut self, src: RValue<'gcc>) -> RValue<'gcc> { let vector_type = src.get_type().unqualified().dyncast_vector().expect("vector type"); @@ -1525,6 +1553,10 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { unimplemented!(); } + pub fn vector_fmax(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> { + self.vector_extremum(a, b, ExtremumOperation::Max) + } + #[cfg(feature="master")] pub fn vector_reduce_fmax(&mut self, src: RValue<'gcc>) -> RValue<'gcc> { let vector_type = src.get_type().unqualified().dyncast_vector().expect("vector type"); diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index 8aed06869a90..36b5ab12b172 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -492,6 +492,8 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, simd_and: Uint, Int => and; simd_or: Uint, Int => or; // FIXME(antoyo): calling `or` might not work on vectors. simd_xor: Uint, Int => xor; + simd_fmin: Float => vector_fmin; + simd_fmax: Float => vector_fmax; } macro_rules! arith_unary { From 9560cb13fe99f47b091e15bc03ae48a96044d833 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 4 Sep 2022 19:29:34 -0400 Subject: [PATCH 161/356] Add IRC channel in the readme --- Readme.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Readme.md b/Readme.md index aa3626db4ef5..b6dc421e259f 100644 --- a/Readme.md +++ b/Readme.md @@ -1,5 +1,7 @@ # WIP libgccjit codegen backend for rust +[![IRC channel](https://img.shields.io/badge/irc.libera.chat-%23rustc__codegen__gcc-blue.svg)](irc://irc.libera.chat/rustc_codegen_gcc) + This is a GCC codegen for rustc, which means it can be loaded by the existing rustc frontend, but benefits from GCC: more architectures are supported and GCC's optimizations are used. **Despite its name, libgccjit can be used for ahead-of-time compilation, as is used here.** From 2ecd620acb56c1f834bc4b7c50b2ac4fe8fac0c5 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 4 Sep 2022 19:34:24 -0400 Subject: [PATCH 162/356] Fix IRC badge --- Readme.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Readme.md b/Readme.md index b6dc421e259f..cdd7f55dcdec 100644 --- a/Readme.md +++ b/Readme.md @@ -1,6 +1,6 @@ # WIP libgccjit codegen backend for rust -[![IRC channel](https://img.shields.io/badge/irc.libera.chat-%23rustc__codegen__gcc-blue.svg)](irc://irc.libera.chat/rustc_codegen_gcc) +[![Chat on IRC](https://img.shields.io/badge/irc.libera.chat-%23rustc__codegen__gcc-blue.svg)](https://web.libera.chat/#rustc_codegen_gcc) This is a GCC codegen for rustc, which means it can be loaded by the existing rustc frontend, but benefits from GCC: more architectures are supported and GCC's optimizations are used. From d7d820fc47a5987566550ef9ede2ea18b0d1ff05 Mon Sep 17 00:00:00 2001 From: Andy Sadler Date: Wed, 7 Sep 2022 21:32:34 -0500 Subject: [PATCH 163/356] simd: impl extract_element for vector types This fixes some tests that needed vector element extraction. Signed-off-by: Andy Sadler --- failing-ui-tests.txt | 2 -- failing-ui-tests12.txt | 1 + src/builder.rs | 15 +++++++++++++-- 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index fc6dcfc7bc7b..7fe9e084940a 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -30,12 +30,10 @@ src/test/ui/sepcomp/sepcomp-extern.rs src/test/ui/sepcomp/sepcomp-fns-backwards.rs src/test/ui/sepcomp/sepcomp-fns.rs src/test/ui/sepcomp/sepcomp-statics.rs -src/test/ui/simd/generics.rs src/test/ui/simd/intrinsic/float-math-pass.rs src/test/ui/simd/intrinsic/generic-arithmetic-pass.rs src/test/ui/simd/intrinsic/generic-as.rs src/test/ui/simd/intrinsic/generic-bitmask-pass.rs -src/test/ui/simd/intrinsic/generic-comparison-pass.rs src/test/ui/simd/intrinsic/generic-gather-pass.rs src/test/ui/simd/intrinsic/generic-select-pass.rs src/test/ui/simd/issue-17170.rs diff --git a/failing-ui-tests12.txt b/failing-ui-tests12.txt index e7952f524124..7826875f04ed 100644 --- a/failing-ui-tests12.txt +++ b/failing-ui-tests12.txt @@ -12,6 +12,7 @@ src/test/ui/simd/intrinsic/float-minmax-pass.rs src/test/ui/simd/intrinsic/generic-arithmetic-saturating-pass.rs src/test/ui/simd/intrinsic/generic-cast-pass.rs src/test/ui/simd/intrinsic/generic-cast-pointer-width.rs +src/test/ui/simd/intrinsic/generic-comparison-pass.rs src/test/ui/simd/intrinsic/generic-elements-pass.rs src/test/ui/simd/intrinsic/generic-reduction-pass.rs src/test/ui/simd/intrinsic/inlining-issue67557-ice.rs diff --git a/src/builder.rs b/src/builder.rs index 52a4854aca3a..95080e024fc9 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1059,8 +1059,19 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { unimplemented!(); } - fn extract_element(&mut self, _vec: RValue<'gcc>, _idx: RValue<'gcc>) -> RValue<'gcc> { - unimplemented!(); + #[cfg(feature="master")] + fn extract_element(&mut self, vec: RValue<'gcc>, idx: RValue<'gcc>) -> RValue<'gcc> { + self.context.new_vector_access(None, vec, idx).to_rvalue() + } + + #[cfg(not(feature="master"))] + fn extract_element(&mut self, vec: RValue<'gcc>, idx: RValue<'gcc>) -> RValue<'gcc> { + let vector_type = vec.get_type().unqualified().dyncast_vector().expect("Called extract_element on a non-vector type"); + let element_type = vector_type.get_element_type(); + let vec_num_units = vector_type.get_num_units(); + let array_type = self.context.new_array_type(None, element_type, vec_num_units as i32); + let array = self.context.new_bitcast(None, vec, array_type).to_rvalue(); + self.context.new_array_access(None, array, idx).to_rvalue() } fn vector_splat(&mut self, _num_elts: usize, _elt: RValue<'gcc>) -> RValue<'gcc> { From 3e6710962e6cec6b64e71c9fe458bed17ba4ed78 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Wed, 14 Sep 2022 08:26:03 -0400 Subject: [PATCH 164/356] Fix build of release sysroot in test.sh --- test.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test.sh b/test.sh index ed43c645bd2d..2bdf362ab40d 100755 --- a/test.sh +++ b/test.sh @@ -30,7 +30,7 @@ while [[ $# -gt 0 ]]; do shift ;; --release-sysroot) - sysroot_channel=release + sysroot_channel="--release" shift ;; --no-default-features) @@ -157,7 +157,7 @@ function mini_tests() { function build_sysroot() { echo "[BUILD] sysroot" - time ./build_sysroot/build_sysroot.sh + time ./build_sysroot/build_sysroot.sh $sysroot_channel } function std_tests() { From d9edc8e8691d3b65665a9fb12d4dcd1a3fe4cab6 Mon Sep 17 00:00:00 2001 From: Pietro Albini Date: Mon, 26 Sep 2022 12:21:51 +0200 Subject: [PATCH 165/356] harden ci configuration --- .github/workflows/ci.yml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 8b36fa0c1c7c..412344cfa3da 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -4,6 +4,9 @@ on: - push - pull_request +permissions: + contents: read + env: # Enable backtraces for easier debugging RUST_BACKTRACE: 1 @@ -16,9 +19,9 @@ jobs: fail-fast: false matrix: libgccjit_version: - - { gcc: "libgccjit.so", extra: "" } - - { gcc: "libgccjit_without_int128.so", extra: "" } - - { gcc: "libgccjit12.so", extra: "--no-default-features" } + - { gcc: "libgccjit.so", extra: "", artifacts_branch: "master" } + - { gcc: "libgccjit_without_int128.so", extra: "", artifacts_branch: "master-without-128bit-integers" } + - { gcc: "libgccjit12.so", extra: "--no-default-features", artifacts_branch: "gcc12" } commands: [ "--mini-tests", "--std-tests", @@ -49,6 +52,8 @@ jobs: name: ${{ matrix.libgccjit_version.gcc }} path: gcc-build repo: antoyo/gcc + branch: ${{ matrix.libgccjit_version.artifacts_branch }} + event: push search_artifacts: true # Because, instead, the action only check the last job ran and that won't work since we want multiple artifacts. - name: Setup path to libgccjit From 688f7426580d44ab4451c4d8eb3345f296e29e51 Mon Sep 17 00:00:00 2001 From: Andy Sadler Date: Fri, 16 Sep 2022 16:49:56 -0500 Subject: [PATCH 166/356] simd: implement float math intrinsics Implements the intrinsics required to pass float-math-pass and libm_std_can_float ui tests. Signed-off-by: Andy Sadler --- failing-ui-tests.txt | 2 -- src/intrinsic/simd.rs | 66 +++++++++++++++++++++++++++---------------- 2 files changed, 42 insertions(+), 26 deletions(-) diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index 7fe9e084940a..8b740cff4f58 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -30,7 +30,6 @@ src/test/ui/sepcomp/sepcomp-extern.rs src/test/ui/sepcomp/sepcomp-fns-backwards.rs src/test/ui/sepcomp/sepcomp-fns.rs src/test/ui/sepcomp/sepcomp-statics.rs -src/test/ui/simd/intrinsic/float-math-pass.rs src/test/ui/simd/intrinsic/generic-arithmetic-pass.rs src/test/ui/simd/intrinsic/generic-as.rs src/test/ui/simd/intrinsic/generic-bitmask-pass.rs @@ -40,7 +39,6 @@ src/test/ui/simd/issue-17170.rs src/test/ui/simd/issue-39720.rs src/test/ui/simd/issue-85915-simd-ptrs.rs src/test/ui/simd/issue-89193.rs -src/test/ui/simd/libm_std_can_float.rs src/test/ui/simd/simd-bitmask.rs src/test/ui/simd/type-generic-monomorphisation-extern-nonnull-ptr.rs src/test/ui/sse2.rs diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index 36b5ab12b172..6d6009972832 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -14,7 +14,6 @@ use rustc_span::{Span, Symbol, sym}; use rustc_target::abi::Align; use crate::builder::Builder; -use crate::intrinsic; pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, name: Symbol, callee_ty: Ty<'tcx>, args: &[OperandRef<'tcx, RValue<'gcc>>], ret_ty: Ty<'tcx>, llret_ty: Type<'gcc>, span: Span) -> Result, ()> { // macros for error handling: @@ -415,8 +414,8 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, if let ty::Float(f) = in_elem.kind() { let elem_ty = bx.cx.type_float_from_ty(*f); match f.bit_width() { - 32 => ("f32", elem_ty), - 64 => ("f64", elem_ty), + 32 => ("f", elem_ty), + 64 => ("", elem_ty), _ => { return_error!( "unsupported element type `{}` of floating-point vector `{}`", @@ -432,30 +431,49 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let vec_ty = bx.cx.type_vector(elem_ty, in_len); - let (intr_name, fn_ty) = + let intr_name = match name { - sym::simd_ceil => ("ceil", bx.type_func(&[vec_ty], vec_ty)), - sym::simd_fabs => ("fabs", bx.type_func(&[vec_ty], vec_ty)), // TODO(antoyo): pand with 170141183420855150465331762880109871103 - sym::simd_fcos => ("cos", bx.type_func(&[vec_ty], vec_ty)), - sym::simd_fexp2 => ("exp2", bx.type_func(&[vec_ty], vec_ty)), - sym::simd_fexp => ("exp", bx.type_func(&[vec_ty], vec_ty)), - sym::simd_flog10 => ("log10", bx.type_func(&[vec_ty], vec_ty)), - sym::simd_flog2 => ("log2", bx.type_func(&[vec_ty], vec_ty)), - sym::simd_flog => ("log", bx.type_func(&[vec_ty], vec_ty)), - sym::simd_floor => ("floor", bx.type_func(&[vec_ty], vec_ty)), - sym::simd_fma => ("fma", bx.type_func(&[vec_ty, vec_ty, vec_ty], vec_ty)), - sym::simd_fpowi => ("powi", bx.type_func(&[vec_ty, bx.type_i32()], vec_ty)), - sym::simd_fpow => ("pow", bx.type_func(&[vec_ty, vec_ty], vec_ty)), - sym::simd_fsin => ("sin", bx.type_func(&[vec_ty], vec_ty)), - sym::simd_fsqrt => ("sqrt", bx.type_func(&[vec_ty], vec_ty)), - sym::simd_round => ("round", bx.type_func(&[vec_ty], vec_ty)), - sym::simd_trunc => ("trunc", bx.type_func(&[vec_ty], vec_ty)), + sym::simd_ceil => "ceil", + sym::simd_fabs => "fabs", // TODO(antoyo): pand with 170141183420855150465331762880109871103 + sym::simd_fcos => "cos", + sym::simd_fexp2 => "exp2", + sym::simd_fexp => "exp", + sym::simd_flog10 => "log10", + sym::simd_flog2 => "log2", + sym::simd_flog => "log", + sym::simd_floor => "floor", + sym::simd_fma => "fma", + sym::simd_fpowi => "__builtin_powi", + sym::simd_fpow => "pow", + sym::simd_fsin => "sin", + sym::simd_fsqrt => "sqrt", + sym::simd_round => "round", + sym::simd_trunc => "trunc", _ => return_error!("unrecognized intrinsic `{}`", name), }; - let llvm_name = &format!("llvm.{0}.v{1}{2}", intr_name, in_len, elem_ty_str); - let function = intrinsic::llvm::intrinsic(llvm_name, &bx.cx); - let function: RValue<'gcc> = unsafe { std::mem::transmute(function) }; - let c = bx.call(fn_ty, function, &args.iter().map(|arg| arg.immediate()).collect::>(), None); + let builtin_name = format!("{}{}", intr_name, elem_ty_str); + let funcs = bx.cx.functions.borrow(); + let function = funcs.get(&builtin_name).unwrap_or_else(|| panic!("unable to find builtin function {}", builtin_name)); + + // TODO(antoyo): add platform-specific behavior here for architectures that have these + // intrinsics as instructions (for instance, gpus) + let mut vector_elements = vec![]; + for i in 0..in_len { + let index = bx.context.new_rvalue_from_long(bx.ulong_type, i as i64); + // we have to treat fpowi specially, since fpowi's second argument is always an i32 + let arguments = if name == sym::simd_fpowi { + vec![ + bx.extract_element(args[0].immediate(), index).to_rvalue(), + args[1].immediate(), + ] + } else { + args.iter() + .map(|arg| bx.extract_element(arg.immediate(), index).to_rvalue()) + .collect() + }; + vector_elements.push(bx.context.new_call(None, *function, &arguments)); + } + let c = bx.context.new_rvalue_from_vector(None, vec_ty, &vector_elements); Ok(c) } From af28dec7d151de3e0e00928ce66d51d8aaa3fbdb Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Fri, 30 Sep 2022 17:53:06 -0400 Subject: [PATCH 167/356] Add CI tests with a sysroot compiled in release mode --- .github/workflows/release.yml | 112 ++++++++++++++++++++++++++++++++++ test.sh | 2 +- 2 files changed, 113 insertions(+), 1 deletion(-) create mode 100644 .github/workflows/release.yml diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml new file mode 100644 index 000000000000..25db3779a9cb --- /dev/null +++ b/.github/workflows/release.yml @@ -0,0 +1,112 @@ +name: CI with sysroot compiled in release mode + +on: + - push + - pull_request + +permissions: + contents: read + +env: + # Enable backtraces for easier debugging + RUST_BACKTRACE: 1 + +jobs: + build: + runs-on: ubuntu-latest + + strategy: + fail-fast: false + matrix: + libgccjit_version: + - { gcc: "libgccjit.so", artifacts_branch: "master" } + + steps: + - uses: actions/checkout@v2 + + - uses: actions/checkout@v2 + with: + repository: llvm/llvm-project + path: llvm + + - name: Install packages + run: sudo apt-get install ninja-build ripgrep + + - name: Download artifact + uses: dawidd6/action-download-artifact@v2 + with: + workflow: main.yml + name: ${{ matrix.libgccjit_version.gcc }} + path: gcc-build + repo: antoyo/gcc + branch: ${{ matrix.libgccjit_version.artifacts_branch }} + event: push + search_artifacts: true # Because, instead, the action only check the last job ran and that won't work since we want multiple artifacts. + + - name: Setup path to libgccjit + run: | + echo $(readlink -f gcc-build) > gcc_path + # NOTE: the filename is still libgccjit.so even when the artifact name is different. + ln gcc-build/libgccjit.so gcc-build/libgccjit.so.0 + + - name: Set env + run: | + echo "LIBRARY_PATH=$(cat gcc_path)" >> $GITHUB_ENV + echo "LD_LIBRARY_PATH=$(cat gcc_path)" >> $GITHUB_ENV + echo "workspace="$GITHUB_WORKSPACE >> $GITHUB_ENV + + - name: Set RUST_COMPILER_RT_ROOT + run: echo "RUST_COMPILER_RT_ROOT="${{ env.workspace }}/llvm/compiler-rt >> $GITHUB_ENV + + # https://github.com/actions/cache/issues/133 + - name: Fixup owner of ~/.cargo/ + # Don't remove the trailing /. It is necessary to follow the symlink. + run: sudo chown -R $(whoami):$(id -ng) ~/.cargo/ + + - name: Cache cargo installed crates + uses: actions/cache@v1.1.2 + with: + path: ~/.cargo/bin + key: cargo-installed-crates2-ubuntu-latest + + - name: Cache cargo registry + uses: actions/cache@v1 + with: + path: ~/.cargo/registry + key: ${{ runner.os }}-cargo-registry2-${{ hashFiles('**/Cargo.lock') }} + + - name: Cache cargo index + uses: actions/cache@v1 + with: + path: ~/.cargo/git + key: ${{ runner.os }}-cargo-index-${{ hashFiles('**/Cargo.lock') }} + + - name: Cache cargo target dir + uses: actions/cache@v1.1.2 + with: + path: target + key: ${{ runner.os }}-cargo-build-target-${{ hashFiles('rust-toolchain') }} + + - name: Build + run: | + ./prepare_build.sh + ./build.sh --release --release-sysroot + cargo test + ./clean_all.sh + + - name: Prepare dependencies + run: | + git config --global user.email "user@example.com" + git config --global user.name "User" + ./prepare.sh + + # Compile is a separate step, as the actions-rs/cargo action supports error annotations + - name: Compile + uses: actions-rs/cargo@v1.0.3 + with: + command: build + args: --release + + - name: Run tests + run: | + ./test.sh --release --clean --release-sysroot --build-sysroot --mini-tests --std-tests --test-libcore diff --git a/test.sh b/test.sh index 2bdf362ab40d..4841922416c7 100755 --- a/test.sh +++ b/test.sh @@ -44,7 +44,7 @@ while [[ $# -gt 0 ]]; do shift ;; "--test-rustc") - funcs=(test_rustc) + funcs+=(test_rustc) shift ;; "--test-successful-rustc") From 12105bc0d7664998f8caa45252cf8e8d1c2b38fc Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Fri, 30 Sep 2022 17:45:31 -0400 Subject: [PATCH 168/356] Fix pointer comparison --- src/int.rs | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/src/int.rs b/src/int.rs index 0c5dab004668..0cf1204791d3 100644 --- a/src/int.rs +++ b/src/int.rs @@ -389,18 +389,22 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { }; self.context.new_comparison(None, op, cmp, self.context.new_rvalue_from_int(self.int_type, limit)) } + else if a_type.get_pointee().is_some() && b_type.get_pointee().is_some() { + // NOTE: gcc cannot compare pointers to different objects, but rustc does that, so cast them to usize. + lhs = self.context.new_bitcast(None, lhs, self.usize_type); + rhs = self.context.new_bitcast(None, rhs, self.usize_type); + self.context.new_comparison(None, op.to_gcc_comparison(), lhs, rhs) + } else { - let left_type = lhs.get_type(); - let right_type = rhs.get_type(); - if left_type != right_type { + if a_type != b_type { // NOTE: because libgccjit cannot compare function pointers. - if left_type.dyncast_function_ptr_type().is_some() && right_type.dyncast_function_ptr_type().is_some() { + if a_type.dyncast_function_ptr_type().is_some() && b_type.dyncast_function_ptr_type().is_some() { lhs = self.context.new_cast(None, lhs, self.usize_type.make_pointer()); rhs = self.context.new_cast(None, rhs, self.usize_type.make_pointer()); } // NOTE: hack because we try to cast a vector type to the same vector type. - else if format!("{:?}", left_type) != format!("{:?}", right_type) { - rhs = self.context.new_cast(None, rhs, left_type); + else if format!("{:?}", a_type) != format!("{:?}", b_type) { + rhs = self.context.new_cast(None, rhs, a_type); } } self.context.new_comparison(None, op.to_gcc_comparison(), lhs, rhs) From ed570f6678dbb9994dee0fd42b1432d86dbcc1a2 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Fri, 30 Sep 2022 17:45:42 -0400 Subject: [PATCH 169/356] Fix gep --- src/builder.rs | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index 95080e024fc9..aa4c6f2f8372 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -858,16 +858,25 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn gep(&mut self, _typ: Type<'gcc>, ptr: RValue<'gcc>, indices: &[RValue<'gcc>]) -> RValue<'gcc> { - let mut result = ptr; + let ptr_type = ptr.get_type(); + let mut pointee_type = ptr.get_type(); + // NOTE: we cannot use array indexing here like in inbounds_gep because array indexing is + // always considered in bounds in GCC (TODO(antoyo): to be verified). + // So, we have to cast to a number. + let mut result = self.context.new_bitcast(None, ptr, self.sizet_type); + // FIXME(antoyo): if there were more than 1 index, this code is probably wrong and would + // require dereferencing the pointer. for index in indices { - result = self.context.new_array_access(None, result, *index).get_address(None).to_rvalue(); + pointee_type = pointee_type.get_pointee().expect("pointee type"); + let pointee_size = self.context.new_rvalue_from_int(index.get_type(), pointee_type.get_size() as i32); + result = result + self.gcc_int_cast(*index * pointee_size, self.sizet_type); } - result + self.context.new_bitcast(None, result, ptr_type) } fn inbounds_gep(&mut self, _typ: Type<'gcc>, ptr: RValue<'gcc>, indices: &[RValue<'gcc>]) -> RValue<'gcc> { - // FIXME(antoyo): would be safer if doing the same thing (loop) as gep. - // TODO(antoyo): specify inbounds somehow. + // NOTE: array indexing is always considered in bounds in GCC (TODO(antoyo): to be verified). + // TODO: replace with a loop like gep. match indices.len() { 1 => { self.context.new_array_access(None, ptr, indices[0]).get_address(None) From 6b7e16f87e2ea143d7c64cf101684b781385c23a Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Fri, 30 Sep 2022 17:45:53 -0400 Subject: [PATCH 170/356] Add more debugging options --- src/back/write.rs | 1 + src/base.rs | 3 +++ 2 files changed, 4 insertions(+) diff --git a/src/back/write.rs b/src/back/write.rs index efcf18d31eb0..5f54ac4ebc69 100644 --- a/src/back/write.rs +++ b/src/back/write.rs @@ -57,6 +57,7 @@ pub(crate) unsafe fn codegen(cgcx: &CodegenContext, _diag_han if env::var("CG_GCCJIT_DUMP_TO_FILE").as_deref() == Ok("1") { let _ = fs::create_dir("/tmp/gccjit_dumps"); let path = &format!("/tmp/gccjit_dumps/{}.c", module.name); + context.set_debug_info(true); context.dump_to_file(path, true); } context.compile_to_file(OutputKind::ObjectFile, obj_out.to_str().expect("path to str")); diff --git a/src/base.rs b/src/base.rs index 8cc9581e842c..b60382496c2a 100644 --- a/src/base.rs +++ b/src/base.rs @@ -126,6 +126,9 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ context.add_command_line_option("-fdata-sections"); } + if env::var("CG_GCCJIT_DUMP_TREE_ALL").as_deref() == Ok("1") { + context.add_command_line_option("-fdump-tree-all"); + } if env::var("CG_GCCJIT_DUMP_CODE").as_deref() == Ok("1") { context.set_dump_code_on_compile(true); } From 090cde9811ff6d14e3af334109214e58356f7457 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Fri, 30 Sep 2022 21:10:37 -0400 Subject: [PATCH 171/356] Disable libcore tests because some fail --- .github/workflows/release.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml index 25db3779a9cb..26b26e3f8410 100644 --- a/.github/workflows/release.yml +++ b/.github/workflows/release.yml @@ -109,4 +109,4 @@ jobs: - name: Run tests run: | - ./test.sh --release --clean --release-sysroot --build-sysroot --mini-tests --std-tests --test-libcore + ./test.sh --release --clean --release-sysroot --build-sysroot --mini-tests --std-tests # --test-libcore # FIXME(antoyo): libcore tests fail. From 908304e2571e5f58937a98fd9a5adc37f660c62a Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 1 Oct 2022 11:55:24 -0400 Subject: [PATCH 172/356] Rewrite inbounds_gep with a loop --- src/builder.rs | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index aa4c6f2f8372..f0582fdcef2d 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -876,17 +876,13 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { fn inbounds_gep(&mut self, _typ: Type<'gcc>, ptr: RValue<'gcc>, indices: &[RValue<'gcc>]) -> RValue<'gcc> { // NOTE: array indexing is always considered in bounds in GCC (TODO(antoyo): to be verified). - // TODO: replace with a loop like gep. - match indices.len() { - 1 => { - self.context.new_array_access(None, ptr, indices[0]).get_address(None) - }, - 2 => { - let array = ptr.dereference(None); // TODO(antoyo): assert that first index is 0? - self.context.new_array_access(None, array, indices[1]).get_address(None) - }, - _ => unimplemented!(), + let mut indices = indices.into_iter(); + let index = indices.next().expect("first index in inbounds_gep"); + let mut result = self.context.new_array_access(None, ptr, *index); + for index in indices { + result = self.context.new_array_access(None, result, *index); } + result.get_address(None) } fn struct_gep(&mut self, value_type: Type<'gcc>, ptr: RValue<'gcc>, idx: u64) -> RValue<'gcc> { From a0654b398b7947ee4e7e632e219f98faf1a6c215 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 1 Oct 2022 15:18:30 -0400 Subject: [PATCH 173/356] Implement llvm.prefetch --- src/intrinsic/llvm.rs | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 20f500e34e90..5d10119e85e4 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -236,6 +236,11 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc let arg2 = builder.context.new_cast(None, arg2, arg2_type); args = vec![new_args[0], arg2].into(); }, + "__builtin_prefetch" => { + let mut new_args = args.to_vec(); + new_args.pop(); + args = new_args.into(); + }, _ => (), } } @@ -393,6 +398,16 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function #[cfg(feature="master")] pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function<'gcc> { + match name { + "llvm.prefetch" => { + let gcc_name = "__builtin_prefetch"; + let func = cx.context.get_builtin_function(gcc_name); + cx.functions.borrow_mut().insert(gcc_name.to_string(), func); + return func + }, + _ => (), + } + let gcc_name = match name { "llvm.x86.xgetbv" => "__builtin_ia32_xgetbv", // NOTE: this doc specifies the equivalent GCC builtins: http://huonw.github.io/llvmint/llvmint/x86/index.html From a28618d2efbbc903c66689e12d47f6f341c6c0f8 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 1 Oct 2022 19:53:14 -0400 Subject: [PATCH 174/356] Fix warnings --- example/alloc_example.rs | 8 ++------ example/mini_core_hello_world.rs | 1 + example/mod_bench.rs | 6 ++---- example/std_example.rs | 1 + 4 files changed, 6 insertions(+), 10 deletions(-) diff --git a/example/alloc_example.rs b/example/alloc_example.rs index 74ea7ec4ede6..c327b93f1bbd 100644 --- a/example/alloc_example.rs +++ b/example/alloc_example.rs @@ -18,16 +18,12 @@ extern "C" { #[panic_handler] fn panic_handler(_: &core::panic::PanicInfo) -> ! { - unsafe { - core::intrinsics::abort(); - } + core::intrinsics::abort(); } #[alloc_error_handler] fn alloc_error_handler(_: alloc::alloc::Layout) -> ! { - unsafe { - core::intrinsics::abort(); - } + core::intrinsics::abort(); } #[start] diff --git a/example/mini_core_hello_world.rs b/example/mini_core_hello_world.rs index 14fd9eeffa6a..7b10425e800f 100644 --- a/example/mini_core_hello_world.rs +++ b/example/mini_core_hello_world.rs @@ -228,6 +228,7 @@ fn main() { } as Box; const FUNC_REF: Option = Some(main); + #[allow(unreachable_code)] match FUNC_REF { Some(_) => {}, None => assert!(false), diff --git a/example/mod_bench.rs b/example/mod_bench.rs index 2e2b0052dee8..95bcad2cd173 100644 --- a/example/mod_bench.rs +++ b/example/mod_bench.rs @@ -6,9 +6,7 @@ extern {} #[panic_handler] fn panic_handler(_: &core::panic::PanicInfo) -> ! { - unsafe { - core::intrinsics::abort(); - } + core::intrinsics::abort(); } #[lang="eh_personality"] @@ -32,6 +30,6 @@ fn main(_argc: isize, _argv: *const *const u8) -> isize { #[inline(never)] fn black_box(i: u32) { if i != 1 { - unsafe { core::intrinsics::abort(); } + core::intrinsics::abort(); } } diff --git a/example/std_example.rs b/example/std_example.rs index 31069058aea3..5c171c49fd19 100644 --- a/example/std_example.rs +++ b/example/std_example.rs @@ -1,5 +1,6 @@ #![feature(core_intrinsics, generators, generator_trait, is_sorted)] +#[cfg(feature="master")] use std::arch::x86_64::*; use std::io::Write; use std::ops::Generator; From 436710fa9bf5ea9a601705c2bd276e18751f2c24 Mon Sep 17 00:00:00 2001 From: Andy Sadler Date: Sun, 2 Oct 2022 18:29:51 -0500 Subject: [PATCH 175/356] simd: enable simd_as intrinsic The method context.convert_vector, added to libgccjit for simd_cast, appears to give the correct behavior for simd_as. Instead of special-casing simd_as, re-use simd_cast's impl for simd_as. Signed-off-by: Andy Sadler --- failing-ui-tests.txt | 1 - failing-ui-tests12.txt | 1 + src/intrinsic/simd.rs | 2 +- 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index 8b740cff4f58..6acd38084457 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -31,7 +31,6 @@ src/test/ui/sepcomp/sepcomp-fns-backwards.rs src/test/ui/sepcomp/sepcomp-fns.rs src/test/ui/sepcomp/sepcomp-statics.rs src/test/ui/simd/intrinsic/generic-arithmetic-pass.rs -src/test/ui/simd/intrinsic/generic-as.rs src/test/ui/simd/intrinsic/generic-bitmask-pass.rs src/test/ui/simd/intrinsic/generic-gather-pass.rs src/test/ui/simd/intrinsic/generic-select-pass.rs diff --git a/failing-ui-tests12.txt b/failing-ui-tests12.txt index 7826875f04ed..027c929d2f3d 100644 --- a/failing-ui-tests12.txt +++ b/failing-ui-tests12.txt @@ -10,6 +10,7 @@ src/test/ui/packed/packed-tuple-struct-layout.rs src/test/ui/simd/array-type.rs src/test/ui/simd/intrinsic/float-minmax-pass.rs src/test/ui/simd/intrinsic/generic-arithmetic-saturating-pass.rs +src/test/ui/simd/intrinsic/generic-as.rs src/test/ui/simd/intrinsic/generic-cast-pass.rs src/test/ui/simd/intrinsic/generic-cast-pointer-width.rs src/test/ui/simd/intrinsic/generic-comparison-pass.rs diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index 6d6009972832..00c541a8af75 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -254,7 +254,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, } #[cfg(feature="master")] - if name == sym::simd_cast { + if name == sym::simd_cast || name == sym::simd_as { require_simd!(ret_ty, "return"); let (out_len, out_elem) = ret_ty.simd_size_and_type(bx.tcx()); require!( From 23a1a868350fb8cea1db26b68035e07144d041b0 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 8 Oct 2022 14:37:19 -0400 Subject: [PATCH 176/356] More debug options --- src/base.rs | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/base.rs b/src/base.rs index b60382496c2a..6e1ad9f53151 100644 --- a/src/base.rs +++ b/src/base.rs @@ -126,6 +126,9 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ context.add_command_line_option("-fdata-sections"); } + if env::var("CG_GCCJIT_DUMP_RTL").as_deref() == Ok("1") { + context.add_command_line_option("-fdump-rtl-vregs"); + } if env::var("CG_GCCJIT_DUMP_TREE_ALL").as_deref() == Ok("1") { context.add_command_line_option("-fdump-tree-all"); } From c5736218121542d6fedfe027c6438b8b80cf5a6f Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 8 Oct 2022 14:37:36 -0400 Subject: [PATCH 177/356] Fix some vfmaddsub intrinsics --- src/builder.rs | 6 +++++- src/context.rs | 3 +++ src/intrinsic/llvm.rs | 24 ++++++++++++++++++------ 3 files changed, 26 insertions(+), 7 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index f0582fdcef2d..f3933a2d7061 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -280,7 +280,11 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let func_name = format!("{:?}", func_ptr); let previous_arg_count = args.len(); let orig_args = args; - let args = llvm::adjust_intrinsic_arguments(&self, gcc_func, args.into(), &func_name); + let args = { + let function_address_names = self.function_address_names.borrow(); + let original_function_name = function_address_names.get(&func_ptr); + llvm::adjust_intrinsic_arguments(&self, gcc_func, args.into(), &func_name, original_function_name) + }; let args_adjusted = args.len() != previous_arg_count; let args = self.check_ptr_call("call", func_ptr, &*args); diff --git a/src/context.rs b/src/context.rs index 2699559dc2ad..5f34ddd92bac 100644 --- a/src/context.rs +++ b/src/context.rs @@ -33,6 +33,7 @@ pub struct CodegenCx<'gcc, 'tcx> { // TODO(bjorn3): Can this field be removed? pub current_func: RefCell>>, pub normal_function_addresses: RefCell>>, + pub function_address_names: RefCell, String>>, pub functions: RefCell>>, pub intrinsics: RefCell>>, @@ -192,6 +193,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { context, current_func: RefCell::new(None), normal_function_addresses: Default::default(), + function_address_names: Default::default(), functions: RefCell::new(functions), intrinsics: RefCell::new(FxHashMap::default()), @@ -345,6 +347,7 @@ impl<'gcc, 'tcx> MiscMethods<'tcx> for CodegenCx<'gcc, 'tcx> { // FIXME(antoyo): the rustc API seems to call get_fn_addr() when not needed (e.g. for FFI). self.normal_function_addresses.borrow_mut().insert(ptr); + self.function_address_names.borrow_mut().insert(ptr, func_name.to_string()); ptr } diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 5d10119e85e4..3de018abf2eb 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -5,7 +5,7 @@ use rustc_codegen_ssa::traits::BuilderMethods; use crate::{context::CodegenCx, builder::Builder}; -pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc, 'tcx>, gcc_func: FunctionPtrType<'gcc>, mut args: Cow<'b, [RValue<'gcc>]>, func_name: &str) -> Cow<'b, [RValue<'gcc>]> { +pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc, 'tcx>, gcc_func: FunctionPtrType<'gcc>, mut args: Cow<'b, [RValue<'gcc>]>, func_name: &str, original_function_name: Option<&String>) -> Cow<'b, [RValue<'gcc>]> { // Some LLVM intrinsics do not map 1-to-1 to GCC intrinsics, so we add the missing // arguments here. if gcc_func.get_param_count() != args.len() { @@ -277,11 +277,23 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc let c = builder.context.new_rvalue_from_vector(None, arg3_type, &[new_args[2]; 2]); args = vec![a, b, c, new_args[3]].into(); }, - "__builtin_ia32_vfmaddsubpd256" | "__builtin_ia32_vfmaddsubps" | "__builtin_ia32_vfmaddsubps256" => { - let mut new_args = args.to_vec(); - let arg3 = &mut new_args[2]; - *arg3 = builder.context.new_unary_op(None, UnaryOp::Minus, arg3.get_type(), *arg3); - args = new_args.into(); + "__builtin_ia32_vfmaddsubpd256" | "__builtin_ia32_vfmaddsubps" | "__builtin_ia32_vfmaddsubps256" + | "__builtin_ia32_vfmaddsubpd" => { + if let Some(original_function_name) = original_function_name { + match &**original_function_name { + "llvm.x86.fma.vfmsubadd.pd.256" | "llvm.x86.fma.vfmsubadd.ps" | "llvm.x86.fma.vfmsubadd.ps.256" + | "llvm.x86.fma.vfmsubadd.pd" => { + // NOTE: since both llvm.x86.fma.vfmsubadd.ps and llvm.x86.fma.vfmaddsub.ps maps to + // __builtin_ia32_vfmaddsubps, only add minus if this comes from a + // subadd LLVM intrinsic, e.g. _mm256_fmsubadd_pd. + let mut new_args = args.to_vec(); + let arg3 = &mut new_args[2]; + *arg3 = builder.context.new_unary_op(None, UnaryOp::Minus, arg3.get_type(), *arg3); + args = new_args.into(); + }, + _ => (), + } + } }, "__builtin_ia32_ldmxcsr" => { // The builtin __builtin_ia32_ldmxcsr takes an integer value while llvm.x86.sse.ldmxcsr takes a pointer, From 74dac5d970fa3f5c070d7d656622068cadfb0feb Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 8 Oct 2022 15:05:23 -0400 Subject: [PATCH 178/356] Fix vfmadd --- src/intrinsic/llvm.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 3de018abf2eb..621ef328a8cf 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -595,6 +595,8 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.fshr.v32i16" => "__builtin_ia32_vpshrdv_v32hi", "llvm.fshr.v16i16" => "__builtin_ia32_vpshrdv_v16hi", "llvm.fshr.v8i16" => "__builtin_ia32_vpshrdv_v8hi", + "llvm.x86.fma.vfmadd.sd" => "__builtin_ia32_vfmaddsd3", + "llvm.x86.fma.vfmadd.ss" => "__builtin_ia32_vfmaddss3", // The above doc points to unknown builtins for the following, so override them: "llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gathersiv4si", From 1fa8b264267abebce9ae991ac1f982d9c43b1721 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 9 Oct 2022 11:25:40 -0400 Subject: [PATCH 179/356] Fix vector_select --- src/builder.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index f3933a2d7061..ee9983830ff8 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1613,9 +1613,9 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let masks = self.bitcast_if_needed(masks, then_val.get_type()); let then_vals = masks & then_val; - let ones = vec![self.context.new_rvalue_one(element_type); num_units]; - let ones = self.context.new_rvalue_from_vector(None, cond_type, &ones); - let inverted_masks = masks + ones; + let minus_ones = vec![self.context.new_rvalue_from_int(element_type, -1); num_units]; + let minus_ones = self.context.new_rvalue_from_vector(None, cond_type, &minus_ones); + let inverted_masks = masks ^ minus_ones; // NOTE: sometimes, the type of else_val can be different than the type of then_val in // libgccjit (vector of int vs vector of int32_t), but they should be the same for the AND // operation to work. From f73dea7e55dcd14f36963f37a24dc9764c584252 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 9 Oct 2022 11:25:49 -0400 Subject: [PATCH 180/356] Fix simd_bitmask --- failing-ui-tests.txt | 1 - failing-ui-tests12.txt | 1 + src/intrinsic/simd.rs | 35 +++++++++++++++++++---------------- 3 files changed, 20 insertions(+), 17 deletions(-) diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index 6acd38084457..8a780e881478 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -38,7 +38,6 @@ src/test/ui/simd/issue-17170.rs src/test/ui/simd/issue-39720.rs src/test/ui/simd/issue-85915-simd-ptrs.rs src/test/ui/simd/issue-89193.rs -src/test/ui/simd/simd-bitmask.rs src/test/ui/simd/type-generic-monomorphisation-extern-nonnull-ptr.rs src/test/ui/sse2.rs src/test/ui/statics/issue-91050-1.rs diff --git a/failing-ui-tests12.txt b/failing-ui-tests12.txt index 027c929d2f3d..00cd42d8e9dc 100644 --- a/failing-ui-tests12.txt +++ b/failing-ui-tests12.txt @@ -20,3 +20,4 @@ src/test/ui/simd/intrinsic/inlining-issue67557-ice.rs src/test/ui/simd/intrinsic/inlining-issue67557.rs src/test/ui/simd/monomorphize-shuffle-index.rs src/test/ui/simd/shuffle.rs +src/test/ui/simd/simd-bitmask.rs diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index 00c541a8af75..7d7890098265 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -337,28 +337,31 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let vector = args[0].immediate(); let vector_type = vector.get_type().dyncast_vector().expect("vector type"); let elem_type = vector_type.get_element_type(); - let mut shifts = vec![]; - let mut masks = vec![]; - let mut mask = 1; - for i in 0..in_len { - shifts.push(bx.context.new_rvalue_from_int(elem_type, i as i32)); - masks.push(bx.context.new_rvalue_from_int(elem_type, mask)); - mask <<= 1; - } - masks.reverse(); - let shifts = bx.context.new_rvalue_from_vector(None, vector.get_type(), &shifts); - let shifted = vector >> shifts; - let masks = bx.context.new_rvalue_from_vector(None, vector.get_type(), &masks); - let masked = shifted & masks; - let reduced = bx.vector_reduce_op(masked, BinaryOp::BitwiseOr); let expected_int_bits = in_len.max(8); let expected_bytes = expected_int_bits / 8 + ((expected_int_bits % 8 > 0) as u64); + // FIXME(antoyo): that's not going to work for masks bigger than 128 bits. + let result_type = bx.type_ix(expected_int_bits); + let mut result = bx.context.new_rvalue_zero(result_type); + + let elem_size = elem_type.get_size() * 8; + let sign_shift = bx.context.new_rvalue_from_int(elem_type, elem_size as i32); + let one = bx.context.new_rvalue_one(elem_type); + + let mut shift = 0; + for i in 0..in_len { + let elem = bx.extract_element(vector, bx.context.new_rvalue_from_int(bx.int_type, i as i32)); + let shifted = elem >> sign_shift; + let masked = shifted & one; + result = result | (bx.context.new_cast(None, masked, result_type) << bx.context.new_rvalue_from_int(result_type, shift)); + shift += 1; + } + match ret_ty.kind() { ty::Uint(i) if i.bit_width() == Some(expected_int_bits) => { // Zero-extend iN to the bitmask type: - return Ok(bx.zext(reduced, bx.type_ix(expected_int_bits))); + return Ok(result); } ty::Array(elem, len) if matches!(elem.kind(), ty::Uint(ty::UintTy::U8)) @@ -366,7 +369,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, == Some(expected_bytes) => { // Zero-extend iN to the array length: - let ze = bx.zext(reduced, bx.type_ix(expected_bytes * 8)); + let ze = bx.zext(result, bx.type_ix(expected_bytes * 8)); // Convert the integer to a byte array let ptr = bx.alloca(bx.type_ix(expected_bytes * 8), Align::ONE); From e5ce7a9846ee9479549d153101351f917f858f02 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 9 Oct 2022 14:05:44 -0400 Subject: [PATCH 181/356] Fix simd_select_bitmask --- src/builder.rs | 8 +++++--- src/intrinsic/simd.rs | 9 +++++++-- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index ee9983830ff8..adcd6235b709 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1597,7 +1597,6 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { unimplemented!(); } - pub fn vector_select(&mut self, cond: RValue<'gcc>, then_val: RValue<'gcc>, else_val: RValue<'gcc>) -> RValue<'gcc> { // cond is a vector of integers, not of bools. let cond_type = cond.get_type(); @@ -1607,10 +1606,12 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let zeros = vec![self.context.new_rvalue_zero(element_type); num_units]; let zeros = self.context.new_rvalue_from_vector(None, cond_type, &zeros); + let result_type = then_val.get_type(); + let masks = self.context.new_comparison(None, ComparisonOp::NotEquals, cond, zeros); // NOTE: masks is a vector of integers, but the values can be vectors of floats, so use bitcast to make // the & operation work. - let masks = self.bitcast_if_needed(masks, then_val.get_type()); + let then_val = self.bitcast_if_needed(then_val, masks.get_type()); let then_vals = masks & then_val; let minus_ones = vec![self.context.new_rvalue_from_int(element_type, -1); num_units]; @@ -1623,7 +1624,8 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let else_val = self.context.new_bitcast(None, else_val, then_val.get_type()); let else_vals = inverted_masks & else_val; - then_vals | else_vals + let res = then_vals | else_vals; + self.bitcast_if_needed(res, result_type) } } diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index 7d7890098265..fbfcebe46a13 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -93,14 +93,19 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let arg1_vector_type = arg1_type.unqualified().dyncast_vector().expect("vector type"); let arg1_element_type = arg1_vector_type.get_element_type(); + // NOTE: since the arguments can be vectors of floats, make sure the mask is a vector of + // integer. + let mask_element_type = bx.type_ix(arg1_element_type.get_size() as u64 * 8); + let vector_mask_type = bx.context.new_vector_type(mask_element_type, arg1_vector_type.get_num_units() as u64); + let mut elements = vec![]; let one = bx.context.new_rvalue_one(mask.get_type()); for _ in 0..len { - let element = bx.context.new_cast(None, mask & one, arg1_element_type); + let element = bx.context.new_cast(None, mask & one, mask_element_type); elements.push(element); mask = mask >> one; } - let vector_mask = bx.context.new_rvalue_from_vector(None, arg1_type, &elements); + let vector_mask = bx.context.new_rvalue_from_vector(None, vector_mask_type, &elements); return Ok(bx.vector_select(vector_mask, arg1, args[2].immediate())); } From 173db39f916a1ae33b15543cd42a88113cf3114f Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 9 Oct 2022 14:15:45 -0400 Subject: [PATCH 182/356] Fix simd_select --- failing-ui-tests.txt | 1 - failing-ui-tests12.txt | 1 + src/builder.rs | 25 +++++++++++++++++++++++-- 3 files changed, 24 insertions(+), 3 deletions(-) diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index 8a780e881478..5b3166113e77 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -33,7 +33,6 @@ src/test/ui/sepcomp/sepcomp-statics.rs src/test/ui/simd/intrinsic/generic-arithmetic-pass.rs src/test/ui/simd/intrinsic/generic-bitmask-pass.rs src/test/ui/simd/intrinsic/generic-gather-pass.rs -src/test/ui/simd/intrinsic/generic-select-pass.rs src/test/ui/simd/issue-17170.rs src/test/ui/simd/issue-39720.rs src/test/ui/simd/issue-85915-simd-ptrs.rs diff --git a/failing-ui-tests12.txt b/failing-ui-tests12.txt index 00cd42d8e9dc..32feb2c886b2 100644 --- a/failing-ui-tests12.txt +++ b/failing-ui-tests12.txt @@ -16,6 +16,7 @@ src/test/ui/simd/intrinsic/generic-cast-pointer-width.rs src/test/ui/simd/intrinsic/generic-comparison-pass.rs src/test/ui/simd/intrinsic/generic-elements-pass.rs src/test/ui/simd/intrinsic/generic-reduction-pass.rs +src/test/ui/simd/intrinsic/generic-select-pass.rs src/test/ui/simd/intrinsic/inlining-issue67557-ice.rs src/test/ui/simd/intrinsic/inlining-issue67557.rs src/test/ui/simd/monomorphize-shuffle-index.rs diff --git a/src/builder.rs b/src/builder.rs index adcd6235b709..b7342f507168 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1599,10 +1599,31 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { pub fn vector_select(&mut self, cond: RValue<'gcc>, then_val: RValue<'gcc>, else_val: RValue<'gcc>) -> RValue<'gcc> { // cond is a vector of integers, not of bools. - let cond_type = cond.get_type(); - let vector_type = cond_type.unqualified().dyncast_vector().expect("vector type"); + let vector_type = cond.get_type().unqualified().dyncast_vector().expect("vector type"); let num_units = vector_type.get_num_units(); let element_type = vector_type.get_element_type(); + + #[cfg(feature="master")] + let (cond, element_type) = { + let then_val_vector_type = then_val.get_type().dyncast_vector().expect("vector type"); + let then_val_element_type = then_val_vector_type.get_element_type(); + let then_val_element_size = then_val_element_type.get_size(); + + // NOTE: the mask needs to be of the same size as the other arguments in order for the & + // operation to work. + if then_val_element_size != element_type.get_size() { + let new_element_type = self.type_ix(then_val_element_size as u64 * 8); + let new_vector_type = self.context.new_vector_type(new_element_type, num_units as u64); + let cond = self.context.convert_vector(None, cond, new_vector_type); + (cond, new_element_type) + } + else { + (cond, element_type) + } + }; + + let cond_type = cond.get_type(); + let zeros = vec![self.context.new_rvalue_zero(element_type); num_units]; let zeros = self.context.new_rvalue_from_vector(None, cond_type, &zeros); From 12bfb01b91d94d51a92b49049cb8edc28f2818fd Mon Sep 17 00:00:00 2001 From: Paul Cacheux Date: Sat, 15 Oct 2022 14:39:43 +0200 Subject: [PATCH 183/356] bump actions for node16 --- .github/workflows/ci.yml | 16 ++++++++-------- .github/workflows/release.yml | 12 ++++++------ 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 412344cfa3da..147b00ff72f7 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -35,9 +35,9 @@ jobs: ] steps: - - uses: actions/checkout@v2 + - uses: actions/checkout@v3 - - uses: actions/checkout@v2 + - uses: actions/checkout@v3 with: repository: llvm/llvm-project path: llvm @@ -77,25 +77,25 @@ jobs: run: sudo chown -R $(whoami):$(id -ng) ~/.cargo/ - name: Cache cargo installed crates - uses: actions/cache@v1.1.2 + uses: actions/cache@v3 with: path: ~/.cargo/bin key: cargo-installed-crates2-ubuntu-latest - name: Cache cargo registry - uses: actions/cache@v1 + uses: actions/cache@v3 with: path: ~/.cargo/registry key: ${{ runner.os }}-cargo-registry2-${{ hashFiles('**/Cargo.lock') }} - name: Cache cargo index - uses: actions/cache@v1 + uses: actions/cache@v3 with: path: ~/.cargo/git key: ${{ runner.os }}-cargo-index-${{ hashFiles('**/Cargo.lock') }} - name: Cache cargo target dir - uses: actions/cache@v1.1.2 + uses: actions/cache@v3 with: path: target key: ${{ runner.os }}-cargo-build-target-${{ hashFiles('rust-toolchain') }} @@ -103,7 +103,7 @@ jobs: - name: Cache rust repository # We only clone the rust repository for rustc tests if: ${{ contains(matrix.commands, 'rustc') }} - uses: actions/cache@v2 + uses: actions/cache@v3 id: cache-rust-repository with: path: rust @@ -140,5 +140,5 @@ jobs: duplicates: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v2 + - uses: actions/checkout@v3 - run: python tools/check_intrinsics_duplicates.py diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml index 26b26e3f8410..0d9b93b53224 100644 --- a/.github/workflows/release.yml +++ b/.github/workflows/release.yml @@ -22,9 +22,9 @@ jobs: - { gcc: "libgccjit.so", artifacts_branch: "master" } steps: - - uses: actions/checkout@v2 + - uses: actions/checkout@v3 - - uses: actions/checkout@v2 + - uses: actions/checkout@v3 with: repository: llvm/llvm-project path: llvm @@ -64,25 +64,25 @@ jobs: run: sudo chown -R $(whoami):$(id -ng) ~/.cargo/ - name: Cache cargo installed crates - uses: actions/cache@v1.1.2 + uses: actions/cache@v3 with: path: ~/.cargo/bin key: cargo-installed-crates2-ubuntu-latest - name: Cache cargo registry - uses: actions/cache@v1 + uses: actions/cache@v3 with: path: ~/.cargo/registry key: ${{ runner.os }}-cargo-registry2-${{ hashFiles('**/Cargo.lock') }} - name: Cache cargo index - uses: actions/cache@v1 + uses: actions/cache@v3 with: path: ~/.cargo/git key: ${{ runner.os }}-cargo-index-${{ hashFiles('**/Cargo.lock') }} - name: Cache cargo target dir - uses: actions/cache@v1.1.2 + uses: actions/cache@v3 with: path: target key: ${{ runner.os }}-cargo-build-target-${{ hashFiles('rust-toolchain') }} From cd01e8db68ece972255b8ca283672de8510e5570 Mon Sep 17 00:00:00 2001 From: Paul Cacheux Date: Sat, 15 Oct 2022 14:40:01 +0200 Subject: [PATCH 184/356] remove cargo cache fixups --- .github/workflows/ci.yml | 5 ----- .github/workflows/release.yml | 5 ----- 2 files changed, 10 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 147b00ff72f7..a75a770550ce 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -71,11 +71,6 @@ jobs: - name: Set RUST_COMPILER_RT_ROOT run: echo "RUST_COMPILER_RT_ROOT="${{ env.workspace }}/llvm/compiler-rt >> $GITHUB_ENV - # https://github.com/actions/cache/issues/133 - - name: Fixup owner of ~/.cargo/ - # Don't remove the trailing /. It is necessary to follow the symlink. - run: sudo chown -R $(whoami):$(id -ng) ~/.cargo/ - - name: Cache cargo installed crates uses: actions/cache@v3 with: diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml index 0d9b93b53224..dd24db5e7073 100644 --- a/.github/workflows/release.yml +++ b/.github/workflows/release.yml @@ -58,11 +58,6 @@ jobs: - name: Set RUST_COMPILER_RT_ROOT run: echo "RUST_COMPILER_RT_ROOT="${{ env.workspace }}/llvm/compiler-rt >> $GITHUB_ENV - # https://github.com/actions/cache/issues/133 - - name: Fixup owner of ~/.cargo/ - # Don't remove the trailing /. It is necessary to follow the symlink. - run: sudo chown -R $(whoami):$(id -ng) ~/.cargo/ - - name: Cache cargo installed crates uses: actions/cache@v3 with: From 94d58b1bd3c95cb465ed126990e3117f1c94b439 Mon Sep 17 00:00:00 2001 From: Paul Cacheux Date: Sat, 15 Oct 2022 15:24:06 +0200 Subject: [PATCH 185/356] remove not applicable rustc patch --- rustc_patches/.gitkeep | 0 rustc_patches/compile_test.patch | 14 -------------- test.sh | 2 -- 3 files changed, 16 deletions(-) create mode 100644 rustc_patches/.gitkeep delete mode 100644 rustc_patches/compile_test.patch diff --git a/rustc_patches/.gitkeep b/rustc_patches/.gitkeep new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/rustc_patches/compile_test.patch b/rustc_patches/compile_test.patch deleted file mode 100644 index 59143eac37b3..000000000000 --- a/rustc_patches/compile_test.patch +++ /dev/null @@ -1,14 +0,0 @@ -diff --git a/src/tools/compiletest/src/header.rs b/src/tools/compiletest/src/header.rs -index 887d27fd6dca4..2c2239f2b83d1 100644 ---- a/src/tools/compiletest/src/header.rs -+++ b/src/tools/compiletest/src/header.rs -@@ -806,8 +806,8 @@ pub fn make_test_description( - cfg: Option<&str>, - ) -> test::TestDesc { - let mut ignore = false; - #[cfg(not(bootstrap))] -- let ignore_message: Option = None; -+ let ignore_message: Option<&str> = None; - let mut should_fail = false; - - let rustc_has_profiler_support = env::var_os("RUSTC_PROFILER_SUPPORT").is_some(); diff --git a/test.sh b/test.sh index 4841922416c7..612ded3e8720 100755 --- a/test.sh +++ b/test.sh @@ -296,8 +296,6 @@ function test_rustc() { git checkout $(rustc -V | cut -d' ' -f3 | tr -d '(') export RUSTFLAGS= - git apply ../rustc_patches/compile_test.patch || true - rm config.toml || true cat > config.toml < Date: Mon, 17 Oct 2022 09:42:33 +0200 Subject: [PATCH 186/356] remove empty directory --- rustc_patches/.gitkeep | 0 1 file changed, 0 insertions(+), 0 deletions(-) delete mode 100644 rustc_patches/.gitkeep diff --git a/rustc_patches/.gitkeep b/rustc_patches/.gitkeep deleted file mode 100644 index e69de29bb2d1..000000000000 From 25d482856e3042b862d6741cfdac56f244fac04a Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Mon, 17 Oct 2022 23:47:18 +0200 Subject: [PATCH 187/356] Improve installation documentation --- Readme.md | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Readme.md b/Readme.md index cdd7f55dcdec..274538a0e638 100644 --- a/Readme.md +++ b/Readme.md @@ -18,6 +18,21 @@ The patches in [this repository](https://github.com/antoyo/libgccjit-patches) ne (Those patches should work when applied on master, but in case it doesn't work, they are known to work when applied on 079c23cfe079f203d5df83fea8e92a60c7d7e878.) You can also use my [fork of gcc](https://github.com/antoyo/gcc) which already includes these patches.** +To build it (most of these instructions come from [here](https://gcc.gnu.org/onlinedocs/jit/internals/index.html), so don't hesitate to take a look there if you encounter an issue): + +```bash +$ cd gcc +$ ./contrib/download_prerequisites +$ sudo apt install flex libmpfr-dev libgmp-dev libmpc3 libmpc-dev +$ ./configure \ + --enable-host-shared \ + --enable-languages=jit \ + --disable-bootstrap \ + --enable-checking=release \ + --prefix=$(pwd)/install \ + --disable-multilib +``` + **Put the path to your custom build of libgccjit in the file `gcc_path`.** ```bash From b3198c72dbaa42fc1e238141ea68fcdf11041805 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Thu, 13 Oct 2022 21:43:07 +0200 Subject: [PATCH 188/356] Add missing register class conversion for inline asm --- src/asm.rs | 75 ++++++++++++++++++++++++++++++++---------------------- 1 file changed, 45 insertions(+), 30 deletions(-) diff --git a/src/asm.rs b/src/asm.rs index 9d9b6a23d074..3e1b54dcf3bd 100644 --- a/src/asm.rs +++ b/src/asm.rs @@ -564,39 +564,52 @@ fn reg_to_gcc(reg: InlineAsmRegOrRegClass) -> ConstraintOrRegister { _ => unimplemented!(), } }, + // They can be retrieved from https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html InlineAsmRegOrRegClass::RegClass(reg) => match reg { - InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => unimplemented!(), - InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::reg) => unimplemented!(), - InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg) => unimplemented!(), - InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => unimplemented!(), - InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => unimplemented!(), + InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::reg) => "r", + InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg) => "w", + InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => "x", + InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => { + unreachable!("clobber-only") + } + InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => "r", InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg) | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low16) - | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low8) => unimplemented!(), - InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16) + | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low8) + | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16) | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low8) - | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => unimplemented!(), - InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg) - | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => unimplemented!(), - InlineAsmRegClass::Avr(_) => unimplemented!(), - InlineAsmRegClass::Bpf(_) => unimplemented!(), - InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => unimplemented!(), - InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => unimplemented!(), - InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => unimplemented!(), - InlineAsmRegClass::Msp430(_) => unimplemented!(), - InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => unimplemented!(), - InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => unimplemented!(), - InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => unimplemented!(), - InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg) => unimplemented!(), - InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => unimplemented!(), - InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::freg) => unimplemented!(), + | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) + | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg) + | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => "t", + InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg) => "r", + InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper) => "d", + InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair) => "r", + InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_iw) => "w", + InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_ptr) => "e", + InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => "r", + InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => "w", + InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => "r", + InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => "d", // more specific than "r" + InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => "f", + InlineAsmRegClass::Msp430(Msp430InlineAsmRegClass::reg) => "r", + // https://github.com/gcc-mirror/gcc/blob/master/gcc/config/nvptx/nvptx.md -> look for + // "define_constraint". + InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => "h", + InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => "r", + InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => "l", + + InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg) => "r", + InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => "b", + InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::freg) => "f", InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::cr) | InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::xer) => { unreachable!("clobber-only") }, - InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => unimplemented!(), - InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => unimplemented!(), - InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::vreg) => unimplemented!(), + InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => "r", + InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => "f", + InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::vreg) => { + unreachable!("clobber-only") + } InlineAsmRegClass::X86(X86InlineAsmRegClass::reg) => "r", InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd) => "Q", InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_byte) => "q", @@ -604,16 +617,18 @@ fn reg_to_gcc(reg: InlineAsmRegOrRegClass) -> ConstraintOrRegister { | InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg) => "x", InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => "v", InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => "Yk", - InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg0) => unimplemented!(), - InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => unimplemented!(), InlineAsmRegClass::X86( - X86InlineAsmRegClass::x87_reg | X86InlineAsmRegClass::mmx_reg | X86InlineAsmRegClass::tmm_reg, + X86InlineAsmRegClass::kreg0 + | X86InlineAsmRegClass::x87_reg + | X86InlineAsmRegClass::mmx_reg + | X86InlineAsmRegClass::tmm_reg, ) => unreachable!("clobber-only"), InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => { bug!("GCC backend does not support SPIR-V") } - InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg) => unimplemented!(), - InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg) => unimplemented!(), + InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => "r", + InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg) => "r", + InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg) => "f", InlineAsmRegClass::Err => unreachable!(), } }; From ccfe7d889814cce1b24ad34097e0161b3436d30f Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Fri, 14 Oct 2022 16:38:09 +0200 Subject: [PATCH 189/356] Add asm test suite --- test.sh | 64 ++++++++++++++++++++++++++++++++++++--------------------- 1 file changed, 41 insertions(+), 23 deletions(-) diff --git a/test.sh b/test.sh index 612ded3e8720..737d87a90694 100755 --- a/test.sh +++ b/test.sh @@ -75,6 +75,11 @@ while [[ $# -gt 0 ]]; do shift ;; + "--asm-tests") + funcs+=(asm_tests) + shift + ;; + "--extended-tests") funcs+=(extended_sysroot_tests) shift @@ -197,6 +202,40 @@ function std_tests() { $RUSTC example/mod_bench.rs --crate-type bin --target $TARGET_TRIPLE } +function setup_rustc() { + rust_toolchain=$(cat rust-toolchain | grep channel | sed 's/channel = "\(.*\)"/\1/') + + git clone https://github.com/rust-lang/rust.git || true + cd rust + git fetch + git checkout $(rustc -V | cut -d' ' -f3 | tr -d '(') + export RUSTFLAGS= + + rm config.toml || true + + cat > config.toml < config.toml < Date: Fri, 14 Oct 2022 16:38:49 +0200 Subject: [PATCH 190/356] Run assembly tests in the CI --- .github/workflows/ci.yml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index a75a770550ce..347e170b3adf 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -13,7 +13,7 @@ env: jobs: build: - runs-on: ubuntu-latest + runs-on: ubuntu-20.04 strategy: fail-fast: false @@ -24,7 +24,7 @@ jobs: - { gcc: "libgccjit12.so", extra: "--no-default-features", artifacts_branch: "gcc12" } commands: [ "--mini-tests", - "--std-tests", + "--std-tests --asm-tests", "--test-libcore", "--extended-rand-tests", "--extended-regex-example-tests", @@ -43,7 +43,8 @@ jobs: path: llvm - name: Install packages - run: sudo apt-get install ninja-build ripgrep + # `llvm-10-tools` is needed to install the `FileCheck` binary which is used for asm tests. + run: sudo apt-get install ninja-build ripgrep llvm-10-tools - name: Download artifact uses: dawidd6/action-download-artifact@v2 From 94a4a4c350ad13a9c8b6ed7029310825b25935e2 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Fri, 14 Oct 2022 17:13:17 +0200 Subject: [PATCH 191/356] Convert llvm-arg `--x86-asm-syntax` into GCC arg `-masm` --- src/base.rs | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/base.rs b/src/base.rs index 6e1ad9f53151..788d4d9ae362 100644 --- a/src/base.rs +++ b/src/base.rs @@ -112,7 +112,13 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ context.add_command_line_option("-mavx"); for arg in &tcx.sess.opts.cg.llvm_args { - context.add_command_line_option(arg); + if arg.starts_with("--x86-asm-syntax=") { + // LLVM uses the two same arguments as GCC: `att` and `intel`. + let syntax = arg.splitn(2, '=').skip(1).next().expect("missing argument"); + context.add_command_line_option(&format!("-masm={}", syntax)); + } else { + context.add_command_line_option(arg); + } } // NOTE: This is needed to compile the file src/intrinsic/archs.rs during a bootstrap of rustc. context.add_command_line_option("-fno-var-tracking-assignments"); From 549fbe8ecb00543463e0c750bbfa32b61d206167 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Sun, 16 Oct 2022 20:26:32 +0200 Subject: [PATCH 192/356] Set llvm-filecheck binary path into rustc config --- test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/test.sh b/test.sh index 737d87a90694..9cfb8eb0d078 100755 --- a/test.sh +++ b/test.sh @@ -222,6 +222,9 @@ deny-warnings = false cargo = "$(which cargo)" local-rebuild = true rustc = "$HOME/.rustup/toolchains/$rust_toolchain-$TARGET_TRIPLE/bin/rustc" + +[target.x86_64-unknown-linux-gnu] +llvm-filecheck = "`which FileCheck-10 || which FileCheck-11 || which FileCheck-12 || which FileCheck-13 || which FileCheck-14`" EOF rustc -V | cut -d' ' -f3 | tr -d '(' From 1b60286103affa47bc28b2c505c78a0b5d16e4dc Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Sun, 16 Oct 2022 21:22:23 +0200 Subject: [PATCH 193/356] Implement constraits modifiers --- src/asm.rs | 62 ++++++++++++++++++++++++++++++++++++------------------ 1 file changed, 41 insertions(+), 21 deletions(-) diff --git a/src/asm.rs b/src/asm.rs index 3e1b54dcf3bd..486c7a3f5cb7 100644 --- a/src/asm.rs +++ b/src/asm.rs @@ -768,34 +768,41 @@ impl<'gcc, 'tcx> AsmMethods<'tcx> for CodegenCx<'gcc, 'tcx> { } fn modifier_to_gcc(arch: InlineAsmArch, reg: InlineAsmRegClass, modifier: Option) -> Option { + // The modifiers can be retrieved from + // https://gcc.gnu.org/onlinedocs/gcc/Modifiers.html#Modifiers match reg { InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::reg) => modifier, - InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => modifier, InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg) | InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => { - unimplemented!() + if modifier == Some('v') { None } else { modifier } } - InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => unimplemented!(), + InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => { + unreachable!("clobber-only") + } + InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => None, InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg) - | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16) => unimplemented!(), + | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16) => None, InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg) | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low16) - | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low8) => unimplemented!(), + | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low8) => Some('P'), InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low8) | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => { - unimplemented!() + if modifier.is_none() { + Some('q') + } else { + modifier + } } - InlineAsmRegClass::Avr(_) => unimplemented!(), - InlineAsmRegClass::Bpf(_) => unimplemented!(), - InlineAsmRegClass::Hexagon(_) => unimplemented!(), - InlineAsmRegClass::Mips(_) => unimplemented!(), - InlineAsmRegClass::Msp430(_) => unimplemented!(), - InlineAsmRegClass::Nvptx(_) => unimplemented!(), - InlineAsmRegClass::PowerPC(_) => unimplemented!(), + InlineAsmRegClass::Hexagon(_) => None, + InlineAsmRegClass::Mips(_) => None, + InlineAsmRegClass::Nvptx(_) => None, + InlineAsmRegClass::PowerPC(_) => None, InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) - | InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => unimplemented!(), - InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::vreg) => unimplemented!(), + | InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => None, + InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::vreg) => { + unreachable!("clobber-only") + } InlineAsmRegClass::X86(X86InlineAsmRegClass::reg) | InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd) => match modifier { None => if arch == InlineAsmArch::X86_64 { Some('q') } else { Some('k') }, @@ -819,16 +826,29 @@ fn modifier_to_gcc(arch: InlineAsmArch, reg: InlineAsmRegClass, modifier: Option _ => unreachable!(), }, InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => None, - InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg0) => None, - InlineAsmRegClass::X86(X86InlineAsmRegClass::x87_reg | X86InlineAsmRegClass::mmx_reg | X86InlineAsmRegClass::tmm_reg) => { + InlineAsmRegClass::X86( + X86InlineAsmRegClass::x87_reg + | X86InlineAsmRegClass::mmx_reg + | X86InlineAsmRegClass::kreg0 + | X86InlineAsmRegClass::tmm_reg, + ) => { unreachable!("clobber-only") } - InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => unimplemented!(), + InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => None, + InlineAsmRegClass::Bpf(_) => None, + InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair) + | InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_iw) + | InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_ptr) => match modifier { + Some('h') => Some('B'), + Some('l') => Some('A'), + _ => None, + }, + InlineAsmRegClass::Avr(_) => None, + InlineAsmRegClass::S390x(_) => None, + InlineAsmRegClass::Msp430(_) => None, InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => { bug!("LLVM backend does not support SPIR-V") - }, - InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg) => unimplemented!(), - InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg) => unimplemented!(), + } InlineAsmRegClass::Err => unreachable!(), } } From 5484c131a5edbaee9a88bb4c7e9f14cced5afc8d Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Tue, 18 Oct 2022 22:45:22 +0200 Subject: [PATCH 194/356] Don't override -masm option if set in the command arguments --- src/base.rs | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/base.rs b/src/base.rs index 788d4d9ae362..c19a62a6cdc7 100644 --- a/src/base.rs +++ b/src/base.rs @@ -87,8 +87,6 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ // Instantiate monomorphizations without filling out definitions yet... //let llvm_module = ModuleLlvm::new(tcx, &cgu_name.as_str()); let context = Context::default(); - // TODO(antoyo): only set on x86 platforms. - context.add_command_line_option("-masm=intel"); // TODO(antoyo): only add the following cli argument if the feature is supported. context.add_command_line_option("-msse2"); context.add_command_line_option("-mavx2"); @@ -111,15 +109,21 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ context.add_command_line_option("-mvpclmulqdq"); context.add_command_line_option("-mavx"); + let mut has_set_asm_syntax = false; for arg in &tcx.sess.opts.cg.llvm_args { if arg.starts_with("--x86-asm-syntax=") { // LLVM uses the two same arguments as GCC: `att` and `intel`. let syntax = arg.splitn(2, '=').skip(1).next().expect("missing argument"); context.add_command_line_option(&format!("-masm={}", syntax)); + has_set_asm_syntax = true; } else { context.add_command_line_option(arg); } } + if !has_set_asm_syntax { + // TODO(antoyo): only set on x86 platforms. + context.add_command_line_option("-masm=intel"); + } // NOTE: This is needed to compile the file src/intrinsic/archs.rs during a bootstrap of rustc. context.add_command_line_option("-fno-var-tracking-assignments"); // NOTE: an optimization (https://github.com/rust-lang/rustc_codegen_gcc/issues/53). From f150ab3277c5ce2b154201e2205cd2e10cb8eb36 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Tue, 18 Oct 2022 23:11:46 +0200 Subject: [PATCH 195/356] Improve code generating inline ASM --- src/asm.rs | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/src/asm.rs b/src/asm.rs index 486c7a3f5cb7..6dea20e40081 100644 --- a/src/asm.rs +++ b/src/asm.rs @@ -706,7 +706,10 @@ impl<'gcc, 'tcx> AsmMethods<'tcx> for CodegenCx<'gcc, 'tcx> { && options.contains(InlineAsmOptions::ATT_SYNTAX); // Build the template string - let mut template_str = String::new(); + let mut template_str = ".pushsection .text\n".to_owned(); + if att_dialect { + template_str.push_str(".att_syntax\n"); + } for piece in template { match *piece { InlineAsmTemplatePiece::String(ref string) => { @@ -754,15 +757,11 @@ impl<'gcc, 'tcx> AsmMethods<'tcx> for CodegenCx<'gcc, 'tcx> { } } - let template_str = - if att_dialect { - format!(".att_syntax\n\t{}\n\t.intel_syntax noprefix", template_str) - } - else { - template_str - }; + if att_dialect { + template_str.push_str("\n\t.intel_syntax noprefix"); + } // NOTE: seems like gcc will put the asm in the wrong section, so set it to .text manually. - let template_str = format!(".pushsection .text\n{}\n.popsection", template_str); + template_str.push_str("\n.popsection"); self.context.add_top_level_asm(None, &template_str); } } From 994a669e264e635daded0ecd8deff6fede51b0a6 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Tue, 18 Oct 2022 23:35:47 +0200 Subject: [PATCH 196/356] Make the asm test suite run on its own --- .github/workflows/ci.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 347e170b3adf..ff9ea0454012 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -24,7 +24,8 @@ jobs: - { gcc: "libgccjit12.so", extra: "--no-default-features", artifacts_branch: "gcc12" } commands: [ "--mini-tests", - "--std-tests --asm-tests", + "--std-tests", + "--asm-tests", "--test-libcore", "--extended-rand-tests", "--extended-regex-example-tests", From c89e3e9b0c9e1566b88465b738dcc699993551e5 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Tue, 18 Oct 2022 17:29:15 +0200 Subject: [PATCH 197/356] Update Readme.md --- Readme.md | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/Readme.md b/Readme.md index 274538a0e638..7a29986739aa 100644 --- a/Readme.md +++ b/Readme.md @@ -21,8 +21,8 @@ You can also use my [fork of gcc](https://github.com/antoyo/gcc) which already i To build it (most of these instructions come from [here](https://gcc.gnu.org/onlinedocs/jit/internals/index.html), so don't hesitate to take a look there if you encounter an issue): ```bash +$ git clone https://github.com/antoyo/gcc $ cd gcc -$ ./contrib/download_prerequisites $ sudo apt install flex libmpfr-dev libgmp-dev libmpc3 libmpc-dev $ ./configure \ --enable-host-shared \ @@ -31,23 +31,33 @@ $ ./configure \ --enable-checking=release \ --prefix=$(pwd)/install \ --disable-multilib +$ make -j4 # You can replace `4` with another number depending on how many cores you have. +$ cd .. ``` **Put the path to your custom build of libgccjit in the file `gcc_path`.** ```bash -$ git clone https://github.com/rust-lang/rustc_codegen_gcc.git -$ cd rustc_codegen_gcc +$ dirname $(readlink -f `find . -name libgccjit.so`) > gcc_path +``` + +You can set also set RUST_COMPILER_RT_ROOT: + +```bash $ git clone https://github.com/llvm/llvm-project llvm --depth 1 --single-branch $ export RUST_COMPILER_RT_ROOT="$PWD/llvm/compiler-rt" -$ ./prepare_build.sh # download and patch sysroot src -$ ./build.sh --release +``` + +Then you can run commands like this: + +```bash +$ ./prepare.sh # download and patch sysroot src and install hyperfine for benchmarking +$ LIBRARY_PATH=$(cat gcc_path) LD_LIBRARY_PATH=$(cat gcc_path) ./build.sh --release ``` To run the tests: ```bash -$ ./prepare.sh # download and patch sysroot src and install hyperfine for benchmarking $ ./test.sh --release ``` From ea52df463b8d826fcc2086485ed71d3d5eb1430e Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Wed, 19 Oct 2022 23:47:42 +0200 Subject: [PATCH 198/356] Fix typo --- Readme.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Readme.md b/Readme.md index 7a29986739aa..4d776b6c7a3f 100644 --- a/Readme.md +++ b/Readme.md @@ -41,7 +41,7 @@ $ cd .. $ dirname $(readlink -f `find . -name libgccjit.so`) > gcc_path ``` -You can set also set RUST_COMPILER_RT_ROOT: +You also need to set RUST_COMPILER_RT_ROOT: ```bash $ git clone https://github.com/llvm/llvm-project llvm --depth 1 --single-branch From 78f960be32d32414dabaf90bdb997cb3fd226ad5 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Mon, 24 Oct 2022 16:47:55 +0200 Subject: [PATCH 199/356] Disable asm tests in CI --- .github/workflows/ci.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index ff9ea0454012..915d4a9a8a7d 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -25,7 +25,8 @@ jobs: commands: [ "--mini-tests", "--std-tests", - "--asm-tests", + # FIXME: re-enable asm tests when GCC can emit in the right syntax. + # "--asm-tests", "--test-libcore", "--extended-rand-tests", "--extended-regex-example-tests", From 1a2c8b01cbc53322845607af8cc041133d37f36a Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Sun, 23 Oct 2022 21:43:00 +0200 Subject: [PATCH 200/356] Fix gcc build instructions --- Readme.md | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/Readme.md b/Readme.md index 4d776b6c7a3f..c681e3ca3bcd 100644 --- a/Readme.md +++ b/Readme.md @@ -22,17 +22,32 @@ To build it (most of these instructions come from [here](https://gcc.gnu.org/onl ```bash $ git clone https://github.com/antoyo/gcc -$ cd gcc $ sudo apt install flex libmpfr-dev libgmp-dev libmpc3 libmpc-dev -$ ./configure \ - --enable-host-shared \ - --enable-languages=jit \ - --disable-bootstrap \ - --enable-checking=release \ - --prefix=$(pwd)/install \ - --disable-multilib +$ mkdir gcc-build gcc-install +$ cd gcc-build +$ ../gcc/configure \ + --enable-host-shared \ + --enable-languages=jit \ + --enable-checking=release \ # it enables extra checks which allow to find bugs + --disable-bootstrap \ + --disable-multilib \ + --prefix=$(pwd)/../gcc-install $ make -j4 # You can replace `4` with another number depending on how many cores you have. -$ cd .. +``` + +If you want to run libgccjit tests, you will need to also enable the C++ language in the `configure`: + +```bash +--enable-languages=jit,c++ +``` + +Then to run libgccjit tests: + +```bash +$ cd gcc # from the `gcc-build` folder +$ make check-jit +# To run one specific test: +$ make check-jit RUNTESTFLAGS="-v -v -v jit.exp=jit.dg/test-asm.cc" ``` **Put the path to your custom build of libgccjit in the file `gcc_path`.** From bf3ef4ce1ae3f9b015c530c29eea01aa7312a1ec Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Wed, 26 Oct 2022 17:04:58 +0200 Subject: [PATCH 201/356] Revert changes in argument parsing for setting asm syntax --- src/base.rs | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/src/base.rs b/src/base.rs index c19a62a6cdc7..6e1ad9f53151 100644 --- a/src/base.rs +++ b/src/base.rs @@ -87,6 +87,8 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ // Instantiate monomorphizations without filling out definitions yet... //let llvm_module = ModuleLlvm::new(tcx, &cgu_name.as_str()); let context = Context::default(); + // TODO(antoyo): only set on x86 platforms. + context.add_command_line_option("-masm=intel"); // TODO(antoyo): only add the following cli argument if the feature is supported. context.add_command_line_option("-msse2"); context.add_command_line_option("-mavx2"); @@ -109,20 +111,8 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ context.add_command_line_option("-mvpclmulqdq"); context.add_command_line_option("-mavx"); - let mut has_set_asm_syntax = false; for arg in &tcx.sess.opts.cg.llvm_args { - if arg.starts_with("--x86-asm-syntax=") { - // LLVM uses the two same arguments as GCC: `att` and `intel`. - let syntax = arg.splitn(2, '=').skip(1).next().expect("missing argument"); - context.add_command_line_option(&format!("-masm={}", syntax)); - has_set_asm_syntax = true; - } else { - context.add_command_line_option(arg); - } - } - if !has_set_asm_syntax { - // TODO(antoyo): only set on x86 platforms. - context.add_command_line_option("-masm=intel"); + context.add_command_line_option(arg); } // NOTE: This is needed to compile the file src/intrinsic/archs.rs during a bootstrap of rustc. context.add_command_line_option("-fno-var-tracking-assignments"); From 15fcca80a40e2e9bfc658b6a98bfb9856d122d14 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Thu, 24 Nov 2022 12:52:11 -0500 Subject: [PATCH 202/356] Escape { and } in inline asm --- src/asm.rs | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/src/asm.rs b/src/asm.rs index 6dea20e40081..0d5c343ffe36 100644 --- a/src/asm.rs +++ b/src/asm.rs @@ -381,15 +381,19 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { for piece in template { match *piece { InlineAsmTemplatePiece::String(ref string) => { - // TODO(@Commeownist): switch to `Iterator::intersperse` once it's stable - let mut iter = string.split('%'); - if let Some(s) = iter.next() { - template_str.push_str(s); - } - - for s in iter { - template_str.push_str("%%"); - template_str.push_str(s); + for char in string.chars() { + // TODO(antoyo): might also need to escape | if rustc doesn't do it. + let escaped_char = + match char { + '%' => "%%", + '{' => "%{", + '}' => "%}", + _ => { + template_str.push(char); + continue; + }, + }; + template_str.push_str(escaped_char); } } InlineAsmTemplatePiece::Placeholder { operand_idx, modifier, span: _ } => { From 76991ba26fb76bc7903a41865acac3162bbefa93 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Thu, 24 Nov 2022 16:30:21 -0500 Subject: [PATCH 203/356] Fix simd_bitmask --- failing-ui-tests.txt | 1 - src/intrinsic/simd.rs | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index 5b3166113e77..6182353599b2 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -31,7 +31,6 @@ src/test/ui/sepcomp/sepcomp-fns-backwards.rs src/test/ui/sepcomp/sepcomp-fns.rs src/test/ui/sepcomp/sepcomp-statics.rs src/test/ui/simd/intrinsic/generic-arithmetic-pass.rs -src/test/ui/simd/intrinsic/generic-bitmask-pass.rs src/test/ui/simd/intrinsic/generic-gather-pass.rs src/test/ui/simd/issue-17170.rs src/test/ui/simd/issue-39720.rs diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index fbfcebe46a13..a4f35c061f0a 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -351,7 +351,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let mut result = bx.context.new_rvalue_zero(result_type); let elem_size = elem_type.get_size() * 8; - let sign_shift = bx.context.new_rvalue_from_int(elem_type, elem_size as i32); + let sign_shift = bx.context.new_rvalue_from_int(elem_type, elem_size as i32 - 1); let one = bx.context.new_rvalue_one(elem_type); let mut shift = 0; From bbc0c2650842455eaca855b7082494c54eb0c411 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Fri, 13 May 2022 17:40:02 -0400 Subject: [PATCH 204/356] Download libgccjit-12-dev package in the CI --- .github/workflows/ci.yml | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 915d4a9a8a7d..2fd27654dc41 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -13,7 +13,7 @@ env: jobs: build: - runs-on: ubuntu-20.04 + runs-on: ubuntu-22.04 strategy: fail-fast: false @@ -45,10 +45,15 @@ jobs: path: llvm - name: Install packages - # `llvm-10-tools` is needed to install the `FileCheck` binary which is used for asm tests. - run: sudo apt-get install ninja-build ripgrep llvm-10-tools + # `llvm-14-tools` is needed to install the `FileCheck` binary which is used for asm tests. + run: sudo apt-get install ninja-build ripgrep llvm-14-tools + + - name: Install libgccjit12 + if: matrix.libgccjit_version.gcc == 'libgccjit12.so' + run: sudo apt-get install libgccjit-12-dev - name: Download artifact + if: matrix.libgccjit_version.gcc != 'libgccjit12.so' uses: dawidd6/action-download-artifact@v2 with: workflow: main.yml @@ -60,6 +65,11 @@ jobs: search_artifacts: true # Because, instead, the action only check the last job ran and that won't work since we want multiple artifacts. - name: Setup path to libgccjit + if: matrix.libgccjit_version.gcc == 'libgccjit12.so' + run: echo /usr/lib/gcc/x86_64-linux-gnu/12 > gcc_path + + - name: Setup path to libgccjit + if: matrix.libgccjit_version.gcc != 'libgccjit12.so' run: | echo $(readlink -f gcc-build) > gcc_path # NOTE: the filename is still libgccjit.so even when the artifact name is different. From 69341c44cced1fe7a8dac8ac7ffb2b9c3e63e48a Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Thu, 24 Nov 2022 18:32:17 -0500 Subject: [PATCH 205/356] Fix the argument order for some AVX-512 intrinsics --- src/intrinsic/llvm.rs | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 621ef328a8cf..4552ab95e537 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -304,6 +304,15 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc new_args[0] = arg1.dereference(None).to_rvalue(); args = new_args.into(); }, + "__builtin_ia32_rcp14sd_mask" | "__builtin_ia32_rcp14ss_mask" | "__builtin_ia32_rsqrt14sd_mask" + | "__builtin_ia32_rsqrt14ss_mask" => { + let new_args = args.to_vec(); + args = vec![new_args[1], new_args[0], new_args[2], new_args[3]].into(); + }, + "__builtin_ia32_sqrtsd_mask_round" | "__builtin_ia32_sqrtss_mask_round" => { + let new_args = args.to_vec(); + args = vec![new_args[1], new_args[0], new_args[2], new_args[3], new_args[4]].into(); + }, _ => (), } } From 3791646c0211f561fbcc52ac55a4b36ddb6d94e8 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 1 Oct 2022 13:08:16 -0400 Subject: [PATCH 206/356] Run stdarch tests in the CI --- .github/workflows/release.yml | 5 +++++ src/base.rs | 2 +- src/lib.rs | 3 ++- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml index dd24db5e7073..2e81442298c6 100644 --- a/.github/workflows/release.yml +++ b/.github/workflows/release.yml @@ -105,3 +105,8 @@ jobs: - name: Run tests run: | ./test.sh --release --clean --release-sysroot --build-sysroot --mini-tests --std-tests # --test-libcore # FIXME(antoyo): libcore tests fail. + + - name: Run stdarch tests + run: | + cd build_sysroot/sysroot_src/library/stdarch/ + CHANNEL=release TARGET=x86_64-unknown-linux-gnu ../../../../cargo.sh test diff --git a/src/base.rs b/src/base.rs index 6e1ad9f53151..ed3daddf43e9 100644 --- a/src/base.rs +++ b/src/base.rs @@ -101,7 +101,7 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ context.add_command_line_option("-m64"); context.add_command_line_option("-mbmi"); context.add_command_line_option("-mgfni"); - context.add_command_line_option("-mavxvnni"); + //context.add_command_line_option("-mavxvnni"); // The CI doesn't support this option. context.add_command_line_option("-mf16c"); context.add_command_line_option("-maes"); context.add_command_line_option("-mxsavec"); diff --git a/src/lib.rs b/src/lib.rs index e43ee5cf21dc..e52ee4818f3e 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -316,7 +316,8 @@ pub fn target_features(sess: &Session, allow_unstable: bool) -> Vec { // gcc -march=native -Q --help=target #[cfg(feature="master")] { - (_feature.contains("sse") || _feature.contains("avx")) && !_feature.contains("avx512") + // NOTE: the CPU in the CI doesn't support sse4a, so disable it to make the stdarch tests pass in the CI. + (_feature.contains("sse") || _feature.contains("avx")) && !_feature.contains("avx512") && !_feature.contains("sse4a") } #[cfg(not(feature="master"))] { From 054696e4a3c8e91ed5e880f41a0c42632d8b19b7 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Fri, 25 Nov 2022 11:20:17 -0500 Subject: [PATCH 207/356] Disable stdarch examples which require unwinding --- patches/0001-Disable-examples.patch | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 patches/0001-Disable-examples.patch diff --git a/patches/0001-Disable-examples.patch b/patches/0001-Disable-examples.patch new file mode 100644 index 000000000000..1b71df1ca8df --- /dev/null +++ b/patches/0001-Disable-examples.patch @@ -0,0 +1,25 @@ +From a2d53a324a02c04b76c0e9d39dc15cd443a3b8b2 Mon Sep 17 00:00:00 2001 +From: Antoni Boucher +Date: Fri, 25 Nov 2022 11:18:11 -0500 +Subject: [PATCH] Disable examples + +--- + library/stdarch/Cargo.toml | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/library/stdarch/Cargo.toml b/library/stdarch/Cargo.toml +index fbe0a95..748d72d 100644 +--- a/library/stdarch/Cargo.toml ++++ b/library/stdarch/Cargo.toml +@@ -3,7 +3,7 @@ members = [ + "crates/core_arch", + "crates/std_detect", + "crates/stdarch-gen", +- "examples/" ++ #"examples/" + ] + exclude = [ + "crates/wasm-assert-instr-tests" +-- +2.26.2.7.g19db9cfb68.dirty + From 889a33a500982cfc2c79ceff1b2caf86c0adbeaa Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Wed, 19 Oct 2022 09:23:23 -0400 Subject: [PATCH 208/356] WIP: Implement unwinding --- Cargo.lock | 2 - Cargo.toml | 4 +- Readme.md | 8 ++ build_sysroot/build_sysroot.sh | 2 +- config.sh | 2 +- src/asm.rs | 5 +- src/base.rs | 11 +++ src/builder.rs | 96 +++++++++++++++++---- src/callee.rs | 32 +++++-- src/context.rs | 108 +++++++++++++++-------- src/declare.rs | 32 ++++--- src/intrinsic/mod.rs | 153 +++++++++++++++++++++++++++++++-- src/mono_item.rs | 11 ++- 13 files changed, 379 insertions(+), 87 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 10d2542f8b5a..e52e742ec6ce 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -41,7 +41,6 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" -source = "git+https://github.com/antoyo/gccjit.rs#f30cc2bd330f4fda3d625f305bdfd7e523e2d8f8" dependencies = [ "gccjit_sys", ] @@ -49,7 +48,6 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" -source = "git+https://github.com/antoyo/gccjit.rs#f30cc2bd330f4fda3d625f305bdfd7e523e2d8f8" dependencies = [ "libc 0.1.12", ] diff --git a/Cargo.toml b/Cargo.toml index 3ac354ea4942..26a0e92923d5 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -22,10 +22,10 @@ default = ["master"] master = ["gccjit/master"] [dependencies] -gccjit = { git = "https://github.com/antoyo/gccjit.rs" } +#gccjit = { git = "https://github.com/antoyo/gccjit.rs" } # Local copy. -#gccjit = { path = "../gccjit.rs" } +gccjit = { path = "../gccjit.rs" } smallvec = { version = "1.6.1", features = ["union", "may_dangle"] } target-lexicon = "0.10.0" diff --git a/Readme.md b/Readme.md index c681e3ca3bcd..a74750228ba0 100644 --- a/Readme.md +++ b/Readme.md @@ -162,6 +162,14 @@ To print a debug representation of a tree: debug_tree(expr); ``` +(defined in print-tree.h) + +To print a debug reprensentation of a gimple struct: + +```c +debug_gimple_stmt(gimple_struct) +``` + To get the `rustc` command to run in `gdb`, add the `--verbose` flag to `cargo build`. ### How to use a custom-build rustc diff --git a/build_sysroot/build_sysroot.sh b/build_sysroot/build_sysroot.sh index f293192a099d..9d692d599f6b 100755 --- a/build_sysroot/build_sysroot.sh +++ b/build_sysroot/build_sysroot.sh @@ -16,7 +16,7 @@ rm Cargo.lock test_target/Cargo.lock 2>/dev/null || true rm -r sysroot/ 2>/dev/null || true # Build libs -export RUSTFLAGS="$RUSTFLAGS -Z force-unstable-if-unmarked -Cpanic=abort" +export RUSTFLAGS="$RUSTFLAGS -Z force-unstable-if-unmarked" if [[ "$1" == "--release" ]]; then sysroot_channel='release' RUSTFLAGS="$RUSTFLAGS -Zmir-opt-level=3" cargo build --target $TARGET_TRIPLE --release diff --git a/config.sh b/config.sh index b25e215fb9ee..6bad0586c5ba 100644 --- a/config.sh +++ b/config.sh @@ -38,7 +38,7 @@ if [[ "$HOST_TRIPLE" != "$TARGET_TRIPLE" ]]; then fi fi -export RUSTFLAGS="$CG_RUSTFLAGS $linker -Cpanic=abort -Csymbol-mangling-version=v0 -Cdebuginfo=2 -Clto=off -Zpanic-abort-tests -Zcodegen-backend=$(pwd)/target/${CHANNEL:-debug}/librustc_codegen_gcc.$dylib_ext --sysroot $(pwd)/build_sysroot/sysroot" +export RUSTFLAGS="$CG_RUSTFLAGS $linker -Csymbol-mangling-version=v0 -Cdebuginfo=2 -Clto=off -Zcodegen-backend=$(pwd)/target/${CHANNEL:-debug}/librustc_codegen_gcc.$dylib_ext --sysroot $(pwd)/build_sysroot/sysroot" # FIXME(antoyo): remove once the atomic shim is gone if [[ `uname` == 'Darwin' ]]; then diff --git a/src/asm.rs b/src/asm.rs index 0d5c343ffe36..b937f7e69ace 100644 --- a/src/asm.rs +++ b/src/asm.rs @@ -352,8 +352,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { inputs.push(AsmInOperand { constraint: "X".into(), rust_idx, - val: self.cx.rvalue_as_function(get_fn(self.cx, instance)) - .get_address(None), + val: get_fn(self.cx, instance, false).get_address(None), }); } @@ -739,7 +738,7 @@ impl<'gcc, 'tcx> AsmMethods<'tcx> for CodegenCx<'gcc, 'tcx> { } GlobalAsmOperandRef::SymFn { instance } => { - let function = self.rvalue_as_function(get_fn(self, instance)); + let function = get_fn(self, instance, false); self.add_used_function(function); // TODO(@Amanieu): Additional mangling is needed on // some targets to add a leading underscore (Mach-O) diff --git a/src/base.rs b/src/base.rs index ed3daddf43e9..0e98166a7cc8 100644 --- a/src/base.rs +++ b/src/base.rs @@ -87,6 +87,16 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ // Instantiate monomorphizations without filling out definitions yet... //let llvm_module = ModuleLlvm::new(tcx, &cgu_name.as_str()); let context = Context::default(); + + context.add_command_line_option("-fexceptions"); + context.add_driver_option("-fexceptions"); + + /*context.add_command_line_option("-fasynchronous-unwind-tables"); + context.add_driver_option("-fasynchronous-unwind-tables"); + + context.add_command_line_option("-funwind-tables"); + context.add_driver_option("-funwind-tables");*/ + // TODO(antoyo): only set on x86 platforms. context.add_command_line_option("-masm=intel"); // TODO(antoyo): only add the following cli argument if the feature is supported. @@ -147,6 +157,7 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ } // TODO(bjorn3): Remove once unwinding is properly implemented + // TODO: remove. context.set_allow_unreachable_blocks(true); { diff --git a/src/builder.rs b/src/builder.rs index b7342f507168..68b664a3ba26 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -13,7 +13,7 @@ use gccjit::{ RValue, ToRValue, Type, - UnaryOp, + UnaryOp, FunctionType, }; use rustc_codegen_ssa::MemFlags; use rustc_codegen_ssa::common::{AtomicOrdering, AtomicRmwBinOp, IntPredicate, RealPredicate, SynchronizationScope}; @@ -372,10 +372,11 @@ impl<'tcx> FnAbiOfHelpers<'tcx> for Builder<'_, '_, 'tcx> { } } -impl<'gcc, 'tcx> Deref for Builder<'_, 'gcc, 'tcx> { +impl<'a, 'gcc, 'tcx> Deref for Builder<'a, 'gcc, 'tcx> { type Target = CodegenCx<'gcc, 'tcx>; - fn deref(&self) -> &Self::Target { + fn deref<'b>(&'b self) -> &'a Self::Target + { self.cx } } @@ -393,7 +394,7 @@ impl<'gcc, 'tcx> BackendTypes for Builder<'_, 'gcc, 'tcx> { } impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { - fn build(cx: &'a CodegenCx<'gcc, 'tcx>, block: Block<'gcc>) -> Self { + fn build(cx: &'a CodegenCx<'gcc, 'tcx>, block: Block<'gcc>) -> Builder<'a, 'gcc, 'tcx> { Builder::with_cx(cx, block) } @@ -450,8 +451,36 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { self.block.end_with_switch(None, value, default_block, &gcc_cases); } + #[cfg(feature="master")] + fn invoke(&mut self, typ: Type<'gcc>, func: RValue<'gcc>, args: &[RValue<'gcc>], then: Block<'gcc>, catch: Block<'gcc>, _funclet: Option<&Funclet>) -> RValue<'gcc> { + let try_block = self.current_func().new_block("try"); + + let current_block = self.block.clone(); + self.block = try_block; + let call = self.call(typ, func, args, None); // TODO: use funclet here? + self.block = current_block; + + let return_value = self.current_func() + .new_local(None, call.get_type(), "invokeResult"); + + try_block.add_assignment(None, return_value, call); + + try_block.end_with_jump(None, then); + + self.block.add_try_catch(None, try_block, catch); + + self.block.end_with_jump(None, then); + + // NOTE: since jumps were added in a place rustc does not expect, the current blocks in the + // state need to be updated. + // FIXME: not sure it's actually needed. + self.switch_to_block(then); + + return_value.to_rvalue() + } + + #[cfg(not(feature="master"))] fn invoke(&mut self, typ: Type<'gcc>, func: RValue<'gcc>, args: &[RValue<'gcc>], then: Block<'gcc>, catch: Block<'gcc>, _funclet: Option<&Funclet>) -> RValue<'gcc> { - // TODO(bjorn3): Properly implement unwinding. let call_site = self.call(typ, func, args, None); let condition = self.context.new_rvalue_from_int(self.bool_type, 1); self.llbb().end_with_conditional(None, condition, then, catch); @@ -1160,23 +1189,56 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { aggregate_value } - fn set_personality_fn(&mut self, _personality: RValue<'gcc>) { - // TODO(antoyo) + fn set_personality_fn(&mut self, personality: RValue<'gcc>) { + let personality = self.rvalue_as_function(personality); // FIXME: why calling + //rvalue_as_function doesn't work? + //let personality = unsafe { std::mem::transmute(personality) }; + #[cfg(feature="master")] + self.current_func().set_personality_function(personality); + // FIXME: rustc manages to generate the symbol DW.ref.rust_eh_personality multiple times + // for the same asm file, which causes an assembler error. } - fn cleanup_landing_pad(&mut self, _ty: Type<'gcc>, _pers_fn: RValue<'gcc>) -> RValue<'gcc> { - let field1 = self.context.new_field(None, self.u8_type.make_pointer(), "landing_pad_field_1"); - let field2 = self.context.new_field(None, self.i32_type, "landing_pad_field_1"); + fn cleanup_landing_pad(&mut self, _ty: Type<'gcc>, pers_fn: RValue<'gcc>) -> RValue<'gcc> { + self.set_personality_fn(pers_fn); + + // FIXME: we're probably not creating a real cleanup pad here. + // FIXME: FIXME: FIXME: It seems to be the actual problem: + // libunwind finds a catch, so returns _URC_HANDLER_FOUND instead of _URC_CONTINUE_UNWIND. + // TODO: can we generate a goto from the finally to the cleanup landing pad? + // TODO: TODO: TODO: add this block to a cleanup_blocks variable and generate a try/finally instead if + // the catch block for it is a cleanup block. + // + // TODO: look at TRY_CATCH_IS_CLEANUP, CLEANUP_POINT_EXPR, WITH_CLEANUP_EXPR, CLEANUP_EH_ONLY. + let eh_pointer_builtin = self.cx.context.get_target_builtin_function("__builtin_eh_pointer"); + let zero = self.cx.context.new_rvalue_zero(self.int_type); + let ptr = self.cx.context.new_call(None, eh_pointer_builtin, &[zero]); + + let field1_type = self.u8_type.make_pointer(); + let field1 = self.context.new_field(None, field1_type, "landing_pad_field_1"); + let field2 = self.context.new_field(None, self.i32_type, "landing_pad_field_2"); let struct_type = self.context.new_struct_type(None, "landing_pad", &[field1, field2]); - self.current_func().new_local(None, struct_type.as_type(), "landing_pad") - .to_rvalue() - // TODO(antoyo): Properly implement unwinding. - // the above is just to make the compilation work as it seems - // rustc_codegen_ssa now calls the unwinding builder methods even on panic=abort. + let value = self.current_func().new_local(None, struct_type.as_type(), "landing_pad"); + let ptr = self.cx.context.new_cast(None, ptr, field1_type); + self.block.add_assignment(None, value.access_field(None, field1), ptr); + self.block.add_assignment(None, value.access_field(None, field2), zero); // TODO: set the proper value here (the type of exception?). + + // Resume. + let param = self.context.new_parameter(None, ptr.get_type(), "exn"); + // TODO: should we call __builtin_unwind_resume instead? + // FIXME: should probably not called resume because it could be executed (I believe) in + // normal (no exception) cases + let unwind_resume = self.context.new_function(None, FunctionType::Extern, self.type_void(), &[param], "_Unwind_Resume", false); + self.block.add_eval(None, self.context.new_call(None, unwind_resume, &[ptr])); + + value.to_rvalue() } - fn resume(&mut self, _exn: RValue<'gcc>) { - // TODO(bjorn3): Properly implement unwinding. + fn resume(&mut self, exn: RValue<'gcc>) { + let param = self.context.new_parameter(None, exn.get_type(), "exn"); + // TODO: should we call __builtin_unwind_resume instead? + let unwind_resume = self.context.new_function(None, FunctionType::Extern, self.type_void(), &[param], "_Unwind_Resume", false); + self.llbb().add_eval(None, self.context.new_call(None, unwind_resume, &[exn])); self.unreachable(); } diff --git a/src/callee.rs b/src/callee.rs index be7d48b2279a..fea5df9b9b0d 100644 --- a/src/callee.rs +++ b/src/callee.rs @@ -1,6 +1,6 @@ #[cfg(feature="master")] use gccjit::{FnAttribute, Visibility}; -use gccjit::{FunctionType, RValue}; +use gccjit::{FunctionType, RValue, Function}; use rustc_codegen_ssa::traits::BaseTypeMethods; use rustc_middle::ty::{self, Instance, TypeVisitable}; use rustc_middle::ty::layout::{FnAbiOf, HasTyCtxt}; @@ -16,22 +16,31 @@ use crate::context::CodegenCx; /// /// - `cx`: the crate context /// - `instance`: the instance to be instantiated -pub fn get_fn<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, instance: Instance<'tcx>) -> RValue<'gcc> { +pub fn get_fn<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, instance: Instance<'tcx>, dont_cache: bool) -> Function<'gcc> { let tcx = cx.tcx(); assert!(!instance.substs.needs_infer()); assert!(!instance.substs.has_escaping_bound_vars()); + let sym = tcx.symbol_name(instance).name; + if let Some(&func) = cx.function_instances.borrow().get(&instance) { + if sym == "rust_eh_personality" { + println!("Cached"); + } return func; } - let sym = tcx.symbol_name(instance).name; + if sym == "rust_eh_personality" { + println!("Not cached"); + } let fn_abi = cx.fn_abi_of_instance(instance, ty::List::empty()); let func = if let Some(func) = cx.get_declared_value(&sym) { + unreachable!(); + /* // Create a fn pointer with the new signature. let ptrty = fn_abi.ptr_to_gcc_type(cx); @@ -64,11 +73,14 @@ pub fn get_fn<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, instance: Instance<'tcx>) } else { func - } + }*/ } else { cx.linkage.set(FunctionType::Extern); - let func = cx.declare_fn(&sym, &fn_abi); + /*if sym == "rust_eh_personality" { + panic!(); + }*/ + let func = cx.declare_fn(&sym, &fn_abi, dont_cache); attributes::from_fn_attrs(cx, func, instance); @@ -163,11 +175,15 @@ pub fn get_fn<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, instance: Instance<'tcx>) } } - // FIXME(antoyo): this is a wrong cast. That requires changing the compiler API. - unsafe { std::mem::transmute(func) } + func }; - cx.function_instances.borrow_mut().insert(instance, func); + //if !dont_cache { + if sym == "rust_eh_personality" { + println!("Caching here"); + } + cx.function_instances.borrow_mut().insert(instance, func); + //} func } diff --git a/src/context.rs b/src/context.rs index 5f34ddd92bac..04371048380f 100644 --- a/src/context.rs +++ b/src/context.rs @@ -1,9 +1,10 @@ use std::cell::{Cell, RefCell}; -use gccjit::{Block, CType, Context, Function, FunctionPtrType, FunctionType, LValue, RValue, Type}; +use gccjit::{Block, CType, Context, Function, FunctionPtrType, FunctionType, LValue, RValue, Type, FnAttribute}; use rustc_codegen_ssa::base::wants_msvc_seh; use rustc_codegen_ssa::traits::{ BackendTypes, + BaseTypeMethods, MiscMethods, }; use rustc_data_structures::base_n; @@ -11,7 +12,7 @@ use rustc_data_structures::fx::{FxHashMap, FxHashSet}; use rustc_middle::span_bug; use rustc_middle::mir::mono::CodegenUnit; use rustc_middle::ty::{self, Instance, ParamEnv, PolyExistentialTraitRef, Ty, TyCtxt}; -use rustc_middle::ty::layout::{FnAbiError, FnAbiOfHelpers, FnAbiRequest, HasParamEnv, HasTyCtxt, LayoutError, TyAndLayout, LayoutOfHelpers}; +use rustc_middle::ty::layout::{FnAbiError, FnAbiOf, FnAbiOfHelpers, FnAbiRequest, HasParamEnv, HasTyCtxt, LayoutError, TyAndLayout, LayoutOfHelpers}; use rustc_session::Session; use rustc_span::Span; use rustc_target::abi::{call::FnAbi, HasDataLayout, PointeeInfo, Size, TargetDataLayout, VariantIdx}; @@ -82,7 +83,7 @@ pub struct CodegenCx<'gcc, 'tcx> { /// Cache instances of monomorphic and polymorphic items pub instances: RefCell, LValue<'gcc>>>, /// Cache function instances of monomorphic and polymorphic items - pub function_instances: RefCell, RValue<'gcc>>>, + pub function_instances: RefCell, Function<'gcc>>>, /// Cache generated vtables pub vtables: RefCell, Option>), RValue<'gcc>>>, @@ -109,6 +110,7 @@ pub struct CodegenCx<'gcc, 'tcx> { local_gen_sym_counter: Cell, eh_personality: Cell>>, + pub rust_try_fn: Cell, Function<'gcc>)>>, pub pointee_infos: RefCell, Size), Option>>, @@ -245,6 +247,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { struct_types: Default::default(), local_gen_sym_counter: Cell::new(0), eh_personality: Cell::new(None), + rust_try_fn: Cell::new(None), pointee_infos: Default::default(), structs_as_pointer: Default::default(), } @@ -252,8 +255,9 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { pub fn rvalue_as_function(&self, value: RValue<'gcc>) -> Function<'gcc> { let function: Function<'gcc> = unsafe { std::mem::transmute(value) }; - debug_assert!(self.functions.borrow().values().find(|value| **value == function).is_some(), - "{:?} ({:?}) is not a function", value, value.get_type()); + // FIXME: seems like self.functions get overwritten for rust_eh_personality. + /*debug_assert!(self.functions.borrow().values().find(|value| **value == function).is_some(), + "{:?} is not a function", function);*/ function } @@ -325,9 +329,9 @@ impl<'gcc, 'tcx> MiscMethods<'tcx> for CodegenCx<'gcc, 'tcx> { } fn get_fn(&self, instance: Instance<'tcx>) -> RValue<'gcc> { - let func = get_fn(self, instance); - *self.current_func.borrow_mut() = Some(self.rvalue_as_function(func)); - func + let func = get_fn(self, instance, false); + *self.current_func.borrow_mut() = Some(func); + unsafe { std::mem::transmute(func) } } fn get_fn_addr(&self, instance: Instance<'tcx>) -> RValue<'gcc> { @@ -338,8 +342,7 @@ impl<'gcc, 'tcx> MiscMethods<'tcx> for CodegenCx<'gcc, 'tcx> { self.intrinsics.borrow()[func_name].clone() } else { - let func = get_fn(self, instance); - self.rvalue_as_function(func) + get_fn(self, instance, false) }; let ptr = func.get_address(None); @@ -377,31 +380,68 @@ impl<'gcc, 'tcx> MiscMethods<'tcx> for CodegenCx<'gcc, 'tcx> { return llpersonality; } let tcx = self.tcx; - let llfn = match tcx.lang_items().eh_personality() { - Some(def_id) if !wants_msvc_seh(self.sess()) => self.get_fn_addr( - ty::Instance::resolve( - tcx, - ty::ParamEnv::reveal_all(), - def_id, - tcx.intern_substs(&[]), - ) - .unwrap().unwrap(), - ), - _ => { - let _name = if wants_msvc_seh(self.sess()) { - "__CxxFrameHandler3" - } else { - "rust_eh_personality" - }; - //let func = self.declare_func(name, self.type_i32(), &[], true); - // FIXME(antoyo): this hack should not be needed. That will probably be removed when - // unwinding support is added. - self.context.new_rvalue_from_int(self.int_type, 0) - } - }; + let func = + match tcx.lang_items().eh_personality() { + Some(def_id) if !wants_msvc_seh(self.sess()) => { + // FIXME: this create an instance into self.functions and prevent the creating + // of the function defined in std. + let instance = + ty::Instance::resolve( + tcx, + ty::ParamEnv::reveal_all(), + def_id, + tcx.intern_substs(&[]), + ) + .unwrap().unwrap(); + + let symbol_name = tcx.symbol_name(instance).name; + let fn_abi = self.fn_abi_of_instance(instance, ty::List::empty()); + self.linkage.set(FunctionType::Extern); + let func = self.declare_fn(symbol_name, &fn_abi, false); + //func.add_attribute(FnAttribute::Weak); + + /*let block = func.new_block("eh_personality_block"); + // NOTE: it seems this function is overwritten by the standard library, so just + // return a dummy value in this version. + let zero = self.context.new_rvalue_zero(self.type_u32()); + block.end_with_return(None, zero);*/ + + //*self.current_func.borrow_mut() = Some(func); + let func: RValue<'gcc> = unsafe { std::mem::transmute(func) }; + func + /*self.get_fn( + ty::Instance::resolve( + tcx, + ty::ParamEnv::reveal_all(), + def_id, + tcx.intern_substs(&[]), + ) + .unwrap().unwrap(), + )*/ + }, + _ => { + let name = if wants_msvc_seh(self.sess()) { + "__CxxFrameHandler3" + } else { + "rust_eh_personality" + }; + let func = self.declare_func(name, self.type_i32(), &[], true); + //*self.current_func.borrow_mut() = Some(func); + // NOTE: this function is created multiple times and is overwritten by the + // standard library, so mark it as weak. + //func.add_attribute(FnAttribute::Weak); + //self.functions.borrow_mut().insert(name.to_string(), func); + /*let block = func.new_block("eh_personality_block"); + // NOTE: it seems this function is overwritten by the standard library, so just + // return a dummy value in this version. + let zero = self.context.new_rvalue_zero(self.type_i32()); + block.end_with_return(None, zero);*/ + unsafe { std::mem::transmute(func) } + } + }; // TODO(antoyo): apply target cpu attributes. - self.eh_personality.set(Some(llfn)); - llfn + self.eh_personality.set(Some(func)); + func } fn sess(&self) -> &Session { diff --git a/src/declare.rs b/src/declare.rs index 5f6360a7da53..fdde82e8df77 100644 --- a/src/declare.rs +++ b/src/declare.rs @@ -38,12 +38,10 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { global } - /*pub fn declare_func(&self, name: &str, return_type: Type<'gcc>, params: &[Type<'gcc>], variadic: bool) -> RValue<'gcc> { - self.linkage.set(FunctionType::Exported); - let func = declare_raw_fn(self, name, () /*llvm::CCallConv*/, return_type, params, variadic); - // FIXME(antoyo): this is a wrong cast. That requires changing the compiler API. - unsafe { std::mem::transmute(func) } - }*/ + pub fn declare_func(&self, name: &str, return_type: Type<'gcc>, params: &[Type<'gcc>], variadic: bool) -> Function<'gcc> { + self.linkage.set(FunctionType::Extern); + declare_raw_fn(self, name, () /*llvm::CCallConv*/, return_type, params, variadic, true) + } pub fn declare_global(&self, name: &str, ty: Type<'gcc>, global_kind: GlobalKind, is_tls: bool, link_section: Option) -> LValue<'gcc> { let global = self.context.new_global(None, global_kind, ty, name); @@ -71,7 +69,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { let return_type = self.type_i32(); let variadic = false; self.linkage.set(FunctionType::Exported); - let func = declare_raw_fn(self, name, () /*llvm::CCallConv*/, return_type, &[self.type_i32(), const_string], variadic); + let func = declare_raw_fn(self, name, () /*llvm::CCallConv*/, return_type, &[self.type_i32(), const_string], variadic, false); // NOTE: it is needed to set the current_func here as well, because get_fn() is not called // for the main function. *self.current_func.borrow_mut() = Some(func); @@ -79,9 +77,19 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { unsafe { std::mem::transmute(func) } } - pub fn declare_fn(&self, name: &str, fn_abi: &FnAbi<'tcx, Ty<'tcx>>) -> Function<'gcc> { + pub fn declare_fn(&self, name: &str, fn_abi: &FnAbi<'tcx, Ty<'tcx>>, dont_cache: bool) -> Function<'gcc> { let (return_type, params, variadic, on_stack_param_indices) = fn_abi.gcc_type(self); - let func = declare_raw_fn(self, name, () /*fn_abi.llvm_cconv()*/, return_type, ¶ms, variadic); + /*static mut COUNTER: i32 = 0; + if name.contains("personality") { + println!("{}: {}", name, skip_cache); + unsafe { + COUNTER += 1; + if COUNTER == 6 { + panic!("{}", name); + } + } + }*/ + let func = declare_raw_fn(self, name, () /*fn_abi.llvm_cconv()*/, return_type, ¶ms, variadic, dont_cache); self.on_stack_function_params.borrow_mut().insert(func, on_stack_param_indices); func } @@ -100,7 +108,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { /// /// If there’s a value with the same name already declared, the function will /// update the declaration and return existing Value instead. -fn declare_raw_fn<'gcc>(cx: &CodegenCx<'gcc, '_>, name: &str, _callconv: () /*llvm::CallConv*/, return_type: Type<'gcc>, param_types: &[Type<'gcc>], variadic: bool) -> Function<'gcc> { +fn declare_raw_fn<'gcc>(cx: &CodegenCx<'gcc, '_>, name: &str, _callconv: () /*llvm::CallConv*/, return_type: Type<'gcc>, param_types: &[Type<'gcc>], variadic: bool, dont_cache: bool) -> Function<'gcc> { if name.starts_with("llvm.") { let intrinsic = llvm::intrinsic(name, cx); cx.intrinsics.borrow_mut().insert(name.to_string(), intrinsic); @@ -115,7 +123,9 @@ fn declare_raw_fn<'gcc>(cx: &CodegenCx<'gcc, '_>, name: &str, _callconv: () /*ll .map(|(index, param)| cx.context.new_parameter(None, *param, &format!("param{}", index))) // TODO(antoyo): set name. .collect(); let func = cx.context.new_function(None, cx.linkage.get(), return_type, ¶ms, mangle_name(name), variadic); - cx.functions.borrow_mut().insert(name.to_string(), func); + //if !dont_cache { + cx.functions.borrow_mut().insert(name.to_string(), func); + //} func }; diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index e3461b97973e..511256e45a32 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -1,22 +1,24 @@ pub mod llvm; mod simd; +use std::iter; + use gccjit::{ComparisonOp, Function, RValue, ToRValue, Type, UnaryOp, FunctionType}; use rustc_codegen_ssa::MemFlags; use rustc_codegen_ssa::base::wants_msvc_seh; use rustc_codegen_ssa::common::{IntPredicate, span_invalid_monomorphization_error}; use rustc_codegen_ssa::mir::operand::{OperandRef, OperandValue}; use rustc_codegen_ssa::mir::place::PlaceRef; -use rustc_codegen_ssa::traits::{ArgAbiMethods, BaseTypeMethods, BuilderMethods, ConstMethods, IntrinsicCallMethods}; +use rustc_codegen_ssa::traits::{ArgAbiMethods, BaseTypeMethods, BuilderMethods, ConstMethods, DerivedTypeMethods, IntrinsicCallMethods, MiscMethods}; use rustc_middle::bug; use rustc_middle::ty::{self, Instance, Ty}; -use rustc_middle::ty::layout::LayoutOf; +use rustc_middle::ty::layout::{FnAbiOf, HasTyCtxt, LayoutOf}; use rustc_span::{Span, Symbol, symbol::kw, sym}; use rustc_target::abi::HasDataLayout; use rustc_target::abi::call::{ArgAbi, FnAbi, PassMode}; -use rustc_target::spec::PanicStrategy; +use rustc_target::spec::{abi::Abi, PanicStrategy}; -use crate::abi::GccType; +use crate::abi::{FnAbiGccExt, GccType}; use crate::builder::Builder; use crate::common::{SignType, TypeReflection}; use crate::context::CodegenCx; @@ -1115,9 +1117,9 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { } } -fn try_intrinsic<'gcc, 'tcx>(bx: &mut Builder<'_, 'gcc, 'tcx>, try_func: RValue<'gcc>, data: RValue<'gcc>, _catch_func: RValue<'gcc>, dest: RValue<'gcc>) { +fn try_intrinsic<'a, 'b, 'gcc, 'tcx>(bx: &'b mut Builder<'a, 'gcc, 'tcx>, try_func: RValue<'gcc>, data: RValue<'gcc>, catch_func: RValue<'gcc>, dest: RValue<'gcc>) { // NOTE: the `|| true` here is to use the panic=abort strategy with panic=unwind too - if bx.sess().panic_strategy() == PanicStrategy::Abort || true { + if bx.sess().panic_strategy() == PanicStrategy::Abort { // TODO(bjorn3): Properly implement unwinding and remove the `|| true` once this is done. bx.call(bx.type_void(), try_func, &[data], None); // Return 0 unconditionally from the intrinsic call; @@ -1129,6 +1131,143 @@ fn try_intrinsic<'gcc, 'tcx>(bx: &mut Builder<'_, 'gcc, 'tcx>, try_func: RValue< unimplemented!(); } else { - unimplemented!(); + codegen_gnu_try(bx, try_func, data, catch_func, dest); } } + +// Definition of the standard `try` function for Rust using the GNU-like model +// of exceptions (e.g., the normal semantics of LLVM's `landingpad` and `invoke` +// instructions). +// +// This codegen is a little surprising because we always call a shim +// function instead of inlining the call to `invoke` manually here. This is done +// because in LLVM we're only allowed to have one personality per function +// definition. The call to the `try` intrinsic is being inlined into the +// function calling it, and that function may already have other personality +// functions in play. By calling a shim we're guaranteed that our shim will have +// the right personality function. +fn codegen_gnu_try<'gcc>(bx: &mut Builder<'_, 'gcc, '_>, try_func: RValue<'gcc>, data: RValue<'gcc>, catch_func: RValue<'gcc>, dest: RValue<'gcc>) { + //use std::ops::Deref; + //let cx: &CodegenCx<'gcc, '_> = bx.deref(); + let cx: &CodegenCx<'gcc, '_> = bx.cx; + let (llty, func) = get_rust_try_fn(cx, &mut |mut bx| { + // Codegens the shims described above: + // + // bx: + // invoke %try_func(%data) normal %normal unwind %catch + // + // normal: + // ret 0 + // + // catch: + // (%ptr, _) = landingpad + // call %catch_func(%data, %ptr) + // ret 1 + let then = bx.append_sibling_block("then"); + let catch = bx.append_sibling_block("catch"); + + let func = bx.current_func(); + let try_func = func.get_param(0).to_rvalue(); + let data = func.get_param(1).to_rvalue(); + let catch_func = func.get_param(2).to_rvalue(); + let try_func_ty = bx.type_func(&[bx.type_i8p()], bx.type_void()); + + let current_block = bx.block.clone(); + + bx.switch_to_block(then); + bx.ret(bx.const_i32(0)); + + // Type indicator for the exception being thrown. + // + // The first value in this tuple is a pointer to the exception object + // being thrown. The second value is a "selector" indicating which of + // the landing pad clauses the exception's type had been matched to. + // rust_try ignores the selector. + bx.switch_to_block(catch); + /*let lpad_ty = bx.type_struct(&[bx.type_i8p(), bx.type_i32()], false); + let vals = bx.landing_pad(lpad_ty, bx.eh_personality(), 1); + let tydesc = bx.const_null(bx.type_i8p()); + bx.add_clause(vals, tydesc); + let ptr = bx.extract_value(vals, 0);*/ + + let eh_pointer_builtin = bx.cx.context.get_target_builtin_function("__builtin_eh_pointer"); + let zero = bx.cx.context.new_rvalue_zero(bx.int_type); + let ptr = bx.cx.context.new_call(None, eh_pointer_builtin, &[zero]); + let catch_ty = bx.type_func(&[bx.type_i8p(), bx.type_i8p()], bx.type_void()); + bx.call(catch_ty, catch_func, &[data, ptr], None); + bx.ret(bx.const_i32(1)); + + // NOTE: the blocks must be filled before adding the try/catch, otherwise gcc will not + // generate a try/catch. + // FIXME: add a check in the libgccjit API to prevent this. + bx.switch_to_block(current_block); + bx.invoke(try_func_ty, try_func, &[data], then, catch, None); + }); + + let func = unsafe { std::mem::transmute(func) }; + + // Note that no invoke is used here because by definition this function + // can't panic (that's what it's catching). + let ret = bx.call(llty, func, &[try_func, data, catch_func], None); + let i32_align = bx.tcx().data_layout.i32_align.abi; + bx.store(ret, dest, i32_align); +} + + +// Helper function used to get a handle to the `__rust_try` function used to +// catch exceptions. +// +// This function is only generated once and is then cached. +fn get_rust_try_fn<'a, 'gcc, 'tcx>(cx: &'a CodegenCx<'gcc, 'tcx>, codegen: &mut dyn FnMut(Builder<'a, 'gcc, 'tcx>)) -> (Type<'gcc>, Function<'gcc>) { + if let Some(llfn) = cx.rust_try_fn.get() { + return llfn; + } + + // Define the type up front for the signature of the rust_try function. + let tcx = cx.tcx; + let i8p = tcx.mk_mut_ptr(tcx.types.i8); + // `unsafe fn(*mut i8) -> ()` + let try_fn_ty = tcx.mk_fn_ptr(ty::Binder::dummy(tcx.mk_fn_sig( + iter::once(i8p), + tcx.mk_unit(), + false, + rustc_hir::Unsafety::Unsafe, + Abi::Rust, + ))); + // `unsafe fn(*mut i8, *mut i8) -> ()` + let catch_fn_ty = tcx.mk_fn_ptr(ty::Binder::dummy(tcx.mk_fn_sig( + [i8p, i8p].iter().cloned(), + tcx.mk_unit(), + false, + rustc_hir::Unsafety::Unsafe, + Abi::Rust, + ))); + // `unsafe fn(unsafe fn(*mut i8) -> (), *mut i8, unsafe fn(*mut i8, *mut i8) -> ()) -> i32` + let rust_fn_sig = ty::Binder::dummy(cx.tcx.mk_fn_sig( + [try_fn_ty, i8p, catch_fn_ty].into_iter(), + &tcx.types.i32, + false, + rustc_hir::Unsafety::Unsafe, + Abi::Rust, + )); + let rust_try = gen_fn(cx, "__rust_try", rust_fn_sig, codegen); + cx.rust_try_fn.set(Some(rust_try)); + rust_try +} + +// Helper function to give a Block to a closure to codegen a shim function. +// This is currently primarily used for the `try` intrinsic functions above. +fn gen_fn<'a, 'gcc, 'tcx>(cx: &'a CodegenCx<'gcc, 'tcx>, name: &str, rust_fn_sig: ty::PolyFnSig<'tcx>, codegen: &mut dyn FnMut(Builder<'a, 'gcc, 'tcx>)) -> (Type<'gcc>, Function<'gcc>) { + let fn_abi = cx.fn_abi_of_fn_ptr(rust_fn_sig, ty::List::empty()); + let (typ, _, _, _) = fn_abi.gcc_type(cx); + // FIXME(eddyb) find a nicer way to do this. + cx.linkage.set(FunctionType::Internal); + let func = cx.declare_fn(name, fn_abi, false); + let func_val = unsafe { std::mem::transmute(func) }; + cx.set_frame_pointer_type(func_val); + cx.apply_target_cpu_attr(func_val); + let block = Builder::append_block(cx, func_val, "entry-block"); + let bx = Builder::build(cx, block); + codegen(bx); + (typ, func) +} diff --git a/src/mono_item.rs b/src/mono_item.rs index ce439d339b6b..09ffd8dc7983 100644 --- a/src/mono_item.rs +++ b/src/mono_item.rs @@ -35,7 +35,10 @@ impl<'gcc, 'tcx> PreDefineMethods<'tcx> for CodegenCx<'gcc, 'tcx> { let fn_abi = self.fn_abi_of_instance(instance, ty::List::empty()); self.linkage.set(base::linkage_to_gcc(linkage)); - let decl = self.declare_fn(symbol_name, &fn_abi); + if symbol_name == "rust_eh_personality" { + println!("********************* Generating real rust_eh_personality: {:?}", base::linkage_to_gcc(linkage)); + } + let decl = self.declare_fn(symbol_name, &fn_abi, false); //let attrs = self.tcx.codegen_fn_attrs(instance.def_id()); attributes::from_fn_attrs(self, decl, instance); @@ -59,5 +62,11 @@ impl<'gcc, 'tcx> PreDefineMethods<'tcx> for CodegenCx<'gcc, 'tcx> { // TODO(antoyo): call set_link_section() to allow initializing argc/argv. // TODO(antoyo): set unique comdat. // TODO(antoyo): use inline attribute from there in linkage.set() above. + + self.functions.borrow_mut().insert(symbol_name.to_string(), decl); + if symbol_name == "rust_eh_personality" { + println!("Caching here 2"); + } + self.function_instances.borrow_mut().insert(instance, unsafe { std::mem::transmute(decl) }); } } From b0cf0e8c0653aab2c89de7b5e1ef34a24bf8ea80 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 20 Nov 2022 10:36:15 -0500 Subject: [PATCH 209/356] WIP --- src/builder.rs | 20 ++++++++++++++++---- src/callee.rs | 10 ---------- src/context.rs | 3 +++ src/mono_item.rs | 6 ------ 4 files changed, 19 insertions(+), 20 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index 68b664a3ba26..082b7be8c4e3 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -467,7 +467,15 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { try_block.end_with_jump(None, then); - self.block.add_try_catch(None, try_block, catch); + if self.cleanup_blocks.borrow().contains(&catch) { + self.block.add_try_finally(None, try_block, catch); + } + else { + // FIXME: FIXME: FIXME: Seems like bad (_URC_NO_REASON) return code, perhaps because the cleanup pad was created properly. + // FIXME: Wrong personality function: __gcc_personality_v0 + println!("Try/catch in {:?}", self.current_func()); + self.block.add_try_catch(None, try_block, catch); + } self.block.end_with_jump(None, then); @@ -1202,12 +1210,15 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { fn cleanup_landing_pad(&mut self, _ty: Type<'gcc>, pers_fn: RValue<'gcc>) -> RValue<'gcc> { self.set_personality_fn(pers_fn); + self.cleanup_blocks.borrow_mut().insert(self.block); + // FIXME: we're probably not creating a real cleanup pad here. - // FIXME: FIXME: FIXME: It seems to be the actual problem: + // FIXME: It seems to be the actual problem: // libunwind finds a catch, so returns _URC_HANDLER_FOUND instead of _URC_CONTINUE_UNWIND. // TODO: can we generate a goto from the finally to the cleanup landing pad? - // TODO: TODO: TODO: add this block to a cleanup_blocks variable and generate a try/finally instead if + // TODO: add this block to a cleanup_blocks variable and generate a try/finally instead if // the catch block for it is a cleanup block. + // => NO, a cleanup is only called during unwinding. // // TODO: look at TRY_CATCH_IS_CLEANUP, CLEANUP_POINT_EXPR, WITH_CLEANUP_EXPR, CLEANUP_EH_ONLY. let eh_pointer_builtin = self.cx.context.get_target_builtin_function("__builtin_eh_pointer"); @@ -1223,13 +1234,14 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { self.block.add_assignment(None, value.access_field(None, field1), ptr); self.block.add_assignment(None, value.access_field(None, field2), zero); // TODO: set the proper value here (the type of exception?). + /* // Resume. let param = self.context.new_parameter(None, ptr.get_type(), "exn"); // TODO: should we call __builtin_unwind_resume instead? // FIXME: should probably not called resume because it could be executed (I believe) in // normal (no exception) cases let unwind_resume = self.context.new_function(None, FunctionType::Extern, self.type_void(), &[param], "_Unwind_Resume", false); - self.block.add_eval(None, self.context.new_call(None, unwind_resume, &[ptr])); + self.block.add_eval(None, self.context.new_call(None, unwind_resume, &[ptr]));*/ value.to_rvalue() } diff --git a/src/callee.rs b/src/callee.rs index fea5df9b9b0d..496b8578bc3d 100644 --- a/src/callee.rs +++ b/src/callee.rs @@ -25,16 +25,9 @@ pub fn get_fn<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, instance: Instance<'tcx>, let sym = tcx.symbol_name(instance).name; if let Some(&func) = cx.function_instances.borrow().get(&instance) { - if sym == "rust_eh_personality" { - println!("Cached"); - } return func; } - if sym == "rust_eh_personality" { - println!("Not cached"); - } - let fn_abi = cx.fn_abi_of_instance(instance, ty::List::empty()); let func = @@ -179,9 +172,6 @@ pub fn get_fn<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, instance: Instance<'tcx>, }; //if !dont_cache { - if sym == "rust_eh_personality" { - println!("Caching here"); - } cx.function_instances.borrow_mut().insert(instance, func); //} diff --git a/src/context.rs b/src/context.rs index 04371048380f..62e30679efa5 100644 --- a/src/context.rs +++ b/src/context.rs @@ -120,6 +120,8 @@ pub struct CodegenCx<'gcc, 'tcx> { /// they can be dereferenced later. /// FIXME(antoyo): fix the rustc API to avoid having this hack. pub structs_as_pointer: RefCell>>, + + pub cleanup_blocks: RefCell>>, } impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { @@ -250,6 +252,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { rust_try_fn: Cell::new(None), pointee_infos: Default::default(), structs_as_pointer: Default::default(), + cleanup_blocks: Default::default(), } } diff --git a/src/mono_item.rs b/src/mono_item.rs index 09ffd8dc7983..3b7f9a0b6bc2 100644 --- a/src/mono_item.rs +++ b/src/mono_item.rs @@ -35,9 +35,6 @@ impl<'gcc, 'tcx> PreDefineMethods<'tcx> for CodegenCx<'gcc, 'tcx> { let fn_abi = self.fn_abi_of_instance(instance, ty::List::empty()); self.linkage.set(base::linkage_to_gcc(linkage)); - if symbol_name == "rust_eh_personality" { - println!("********************* Generating real rust_eh_personality: {:?}", base::linkage_to_gcc(linkage)); - } let decl = self.declare_fn(symbol_name, &fn_abi, false); //let attrs = self.tcx.codegen_fn_attrs(instance.def_id()); @@ -64,9 +61,6 @@ impl<'gcc, 'tcx> PreDefineMethods<'tcx> for CodegenCx<'gcc, 'tcx> { // TODO(antoyo): use inline attribute from there in linkage.set() above. self.functions.borrow_mut().insert(symbol_name.to_string(), decl); - if symbol_name == "rust_eh_personality" { - println!("Caching here 2"); - } self.function_instances.borrow_mut().insert(instance, unsafe { std::mem::transmute(decl) }); } } From 71d7e561bdc2e58cef7fedcec1970dafc852bb61 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Tue, 3 Jan 2023 08:56:00 -0500 Subject: [PATCH 210/356] Comment --- Readme.md | 10 ++++++++++ src/builder.rs | 8 ++++++++ 2 files changed, 18 insertions(+) diff --git a/Readme.md b/Readme.md index a74750228ba0..e9c719d84722 100644 --- a/Readme.md +++ b/Readme.md @@ -172,6 +172,16 @@ debug_gimple_stmt(gimple_struct) To get the `rustc` command to run in `gdb`, add the `--verbose` flag to `cargo build`. +To have the correct file paths in `gdb` instead of `/usr/src/debug/gcc/libstdc++-v3/libsupc++/eh_personality.cc`, TODO + +Maybe by calling the following at the beginning of gdb: + +``` +set substitute-path /usr/src/debug/gcc /home/bouanto/Ordinateur/Programmation/Projets/gcc-repo/gcc +``` + +TODO: but that's not what I remember I was doing. + ### How to use a custom-build rustc * Build the stage2 compiler (`rustup toolchain link debug-current build/x86_64-unknown-linux-gnu/stage2`). diff --git a/src/builder.rs b/src/builder.rs index 082b7be8c4e3..fd674ed0b871 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1210,6 +1210,14 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { fn cleanup_landing_pad(&mut self, _ty: Type<'gcc>, pers_fn: RValue<'gcc>) -> RValue<'gcc> { self.set_personality_fn(pers_fn); + /* + * Matching GCC exception handling with LLVM: + * + * GCC LLVM + * CATCH_EXPR landing pad catch clause + * TRY_FINALLY_EXPR cleanup + */ + self.cleanup_blocks.borrow_mut().insert(self.block); // FIXME: we're probably not creating a real cleanup pad here. From 7c1d21c3b91e33d5185228e98ec0eb01ed3f1cd5 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Tue, 3 Jan 2023 15:08:07 -0500 Subject: [PATCH 211/356] Don't automatically run asm_tests in test.sh --- test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test.sh b/test.sh index 9cfb8eb0d078..12a14190e497 100755 --- a/test.sh +++ b/test.sh @@ -400,7 +400,7 @@ function all() { mini_tests build_sysroot std_tests - asm_tests + #asm_tests test_libcore extended_sysroot_tests test_rustc From a4b74e3adf214d985c541eb7d005bb77e59338f5 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Fri, 6 Jan 2023 10:42:38 -0500 Subject: [PATCH 212/356] Fix unwinding --- src/builder.rs | 23 +++-------------------- src/intrinsic/mod.rs | 12 +++--------- 2 files changed, 6 insertions(+), 29 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index fd674ed0b871..af77fa418c86 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -472,7 +472,6 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } else { // FIXME: FIXME: FIXME: Seems like bad (_URC_NO_REASON) return code, perhaps because the cleanup pad was created properly. - // FIXME: Wrong personality function: __gcc_personality_v0 println!("Try/catch in {:?}", self.current_func()); self.block.add_try_catch(None, try_block, catch); } @@ -1220,15 +1219,6 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { self.cleanup_blocks.borrow_mut().insert(self.block); - // FIXME: we're probably not creating a real cleanup pad here. - // FIXME: It seems to be the actual problem: - // libunwind finds a catch, so returns _URC_HANDLER_FOUND instead of _URC_CONTINUE_UNWIND. - // TODO: can we generate a goto from the finally to the cleanup landing pad? - // TODO: add this block to a cleanup_blocks variable and generate a try/finally instead if - // the catch block for it is a cleanup block. - // => NO, a cleanup is only called during unwinding. - // - // TODO: look at TRY_CATCH_IS_CLEANUP, CLEANUP_POINT_EXPR, WITH_CLEANUP_EXPR, CLEANUP_EH_ONLY. let eh_pointer_builtin = self.cx.context.get_target_builtin_function("__builtin_eh_pointer"); let zero = self.cx.context.new_rvalue_zero(self.int_type); let ptr = self.cx.context.new_call(None, eh_pointer_builtin, &[zero]); @@ -1242,21 +1232,14 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { self.block.add_assignment(None, value.access_field(None, field1), ptr); self.block.add_assignment(None, value.access_field(None, field2), zero); // TODO: set the proper value here (the type of exception?). - /* - // Resume. - let param = self.context.new_parameter(None, ptr.get_type(), "exn"); - // TODO: should we call __builtin_unwind_resume instead? - // FIXME: should probably not called resume because it could be executed (I believe) in - // normal (no exception) cases - let unwind_resume = self.context.new_function(None, FunctionType::Extern, self.type_void(), &[param], "_Unwind_Resume", false); - self.block.add_eval(None, self.context.new_call(None, unwind_resume, &[ptr]));*/ - value.to_rvalue() } fn resume(&mut self, exn: RValue<'gcc>) { + // TODO: check if this is normal that we need to dereference the value. + let exn = exn.dereference(None).to_rvalue(); let param = self.context.new_parameter(None, exn.get_type(), "exn"); - // TODO: should we call __builtin_unwind_resume instead? + // TODO(antoyo): should we call __builtin_unwind_resume instead? This might actually be the same. let unwind_resume = self.context.new_function(None, FunctionType::Extern, self.type_void(), &[param], "_Unwind_Resume", false); self.llbb().add_eval(None, self.context.new_call(None, unwind_resume, &[exn])); self.unreachable(); diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index 511256e45a32..ce7874a3de47 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -1179,16 +1179,10 @@ fn codegen_gnu_try<'gcc>(bx: &mut Builder<'_, 'gcc, '_>, try_func: RValue<'gcc>, // Type indicator for the exception being thrown. // - // The first value in this tuple is a pointer to the exception object - // being thrown. The second value is a "selector" indicating which of - // the landing pad clauses the exception's type had been matched to. - // rust_try ignores the selector. + // The value is a pointer to the exception object + // being thrown. bx.switch_to_block(catch); - /*let lpad_ty = bx.type_struct(&[bx.type_i8p(), bx.type_i32()], false); - let vals = bx.landing_pad(lpad_ty, bx.eh_personality(), 1); - let tydesc = bx.const_null(bx.type_i8p()); - bx.add_clause(vals, tydesc); - let ptr = bx.extract_value(vals, 0);*/ + bx.set_personality_fn(bx.eh_personality()); let eh_pointer_builtin = bx.cx.context.get_target_builtin_function("__builtin_eh_pointer"); let zero = bx.cx.context.new_rvalue_zero(bx.int_type); From 70659f7591b9ecc4a92df9d45c1d18e750a5339b Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 8 Jan 2023 11:42:00 -0500 Subject: [PATCH 213/356] Cleanup --- Readme.md | 2 +- example/alloc_example.rs | 12 ++++++++- src/asm.rs | 4 +-- src/base.rs | 9 +------ src/builder.rs | 20 +++------------ src/callee.rs | 19 ++++++-------- src/context.rs | 54 ++++++++++------------------------------ src/declare.rs | 24 +++++------------- src/intrinsic/mod.rs | 6 ++--- src/mono_item.rs | 2 +- test.sh | 9 ++++--- 11 files changed, 53 insertions(+), 108 deletions(-) diff --git a/Readme.md b/Readme.md index e9c719d84722..3201afbd7820 100644 --- a/Readme.md +++ b/Readme.md @@ -177,7 +177,7 @@ To have the correct file paths in `gdb` instead of `/usr/src/debug/gcc/libstdc++ Maybe by calling the following at the beginning of gdb: ``` -set substitute-path /usr/src/debug/gcc /home/bouanto/Ordinateur/Programmation/Projets/gcc-repo/gcc +set substitute-path /usr/src/debug/gcc /path/to/gcc-repo/gcc ``` TODO: but that's not what I remember I was doing. diff --git a/example/alloc_example.rs b/example/alloc_example.rs index c327b93f1bbd..c80348ca5497 100644 --- a/example/alloc_example.rs +++ b/example/alloc_example.rs @@ -1,4 +1,4 @@ -#![feature(start, box_syntax, core_intrinsics, alloc_error_handler)] +#![feature(start, box_syntax, core_intrinsics, alloc_error_handler, lang_items)] #![no_std] extern crate alloc; @@ -26,6 +26,16 @@ fn alloc_error_handler(_: alloc::alloc::Layout) -> ! { core::intrinsics::abort(); } +#[lang = "eh_personality"] +fn eh_personality() -> ! { + loop {} +} + +#[no_mangle] +unsafe extern "C" fn _Unwind_Resume() { + core::intrinsics::unreachable(); +} + #[start] fn main(_argc: isize, _argv: *const *const u8) -> isize { let world: Box<&str> = box "Hello World!\0"; diff --git a/src/asm.rs b/src/asm.rs index b937f7e69ace..19cd44f28193 100644 --- a/src/asm.rs +++ b/src/asm.rs @@ -352,7 +352,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { inputs.push(AsmInOperand { constraint: "X".into(), rust_idx, - val: get_fn(self.cx, instance, false).get_address(None), + val: get_fn(self.cx, instance).get_address(None), }); } @@ -738,7 +738,7 @@ impl<'gcc, 'tcx> AsmMethods<'tcx> for CodegenCx<'gcc, 'tcx> { } GlobalAsmOperandRef::SymFn { instance } => { - let function = get_fn(self, instance, false); + let function = get_fn(self, instance); self.add_used_function(function); // TODO(@Amanieu): Additional mangling is needed on // some targets to add a leading underscore (Mach-O) diff --git a/src/base.rs b/src/base.rs index 0e98166a7cc8..ea933c25b2f3 100644 --- a/src/base.rs +++ b/src/base.rs @@ -91,12 +91,6 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ context.add_command_line_option("-fexceptions"); context.add_driver_option("-fexceptions"); - /*context.add_command_line_option("-fasynchronous-unwind-tables"); - context.add_driver_option("-fasynchronous-unwind-tables"); - - context.add_command_line_option("-funwind-tables"); - context.add_driver_option("-funwind-tables");*/ - // TODO(antoyo): only set on x86 platforms. context.add_command_line_option("-masm=intel"); // TODO(antoyo): only add the following cli argument if the feature is supported. @@ -156,8 +150,7 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ context.set_keep_intermediates(true); } - // TODO(bjorn3): Remove once unwinding is properly implemented - // TODO: remove. + // NOTE: The codegen generates unrechable blocks. context.set_allow_unreachable_blocks(true); { diff --git a/src/builder.rs b/src/builder.rs index af77fa418c86..080a306e70eb 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -457,7 +457,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { let current_block = self.block.clone(); self.block = try_block; - let call = self.call(typ, func, args, None); // TODO: use funclet here? + let call = self.call(typ, func, args, None); // TODO(antoyo): use funclet here? self.block = current_block; let return_value = self.current_func() @@ -471,8 +471,6 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { self.block.add_try_finally(None, try_block, catch); } else { - // FIXME: FIXME: FIXME: Seems like bad (_URC_NO_REASON) return code, perhaps because the cleanup pad was created properly. - println!("Try/catch in {:?}", self.current_func()); self.block.add_try_catch(None, try_block, catch); } @@ -1197,26 +1195,16 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } fn set_personality_fn(&mut self, personality: RValue<'gcc>) { - let personality = self.rvalue_as_function(personality); // FIXME: why calling - //rvalue_as_function doesn't work? - //let personality = unsafe { std::mem::transmute(personality) }; + let personality = self.rvalue_as_function(personality); #[cfg(feature="master")] self.current_func().set_personality_function(personality); - // FIXME: rustc manages to generate the symbol DW.ref.rust_eh_personality multiple times - // for the same asm file, which causes an assembler error. } fn cleanup_landing_pad(&mut self, _ty: Type<'gcc>, pers_fn: RValue<'gcc>) -> RValue<'gcc> { self.set_personality_fn(pers_fn); - /* - * Matching GCC exception handling with LLVM: - * - * GCC LLVM - * CATCH_EXPR landing pad catch clause - * TRY_FINALLY_EXPR cleanup - */ - + // NOTE: insert the current block in a variable so that a later call to invoke knows to + // generate a try/finally instead of a try/catch for this block. self.cleanup_blocks.borrow_mut().insert(self.block); let eh_pointer_builtin = self.cx.context.get_target_builtin_function("__builtin_eh_pointer"); diff --git a/src/callee.rs b/src/callee.rs index 496b8578bc3d..70cdece7f0af 100644 --- a/src/callee.rs +++ b/src/callee.rs @@ -1,11 +1,9 @@ #[cfg(feature="master")] use gccjit::{FnAttribute, Visibility}; -use gccjit::{FunctionType, RValue, Function}; -use rustc_codegen_ssa::traits::BaseTypeMethods; +use gccjit::{FunctionType, Function}; use rustc_middle::ty::{self, Instance, TypeVisitable}; use rustc_middle::ty::layout::{FnAbiOf, HasTyCtxt}; -use crate::abi::FnAbiGccExt; use crate::attributes; use crate::context::CodegenCx; @@ -16,7 +14,7 @@ use crate::context::CodegenCx; /// /// - `cx`: the crate context /// - `instance`: the instance to be instantiated -pub fn get_fn<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, instance: Instance<'tcx>, dont_cache: bool) -> Function<'gcc> { +pub fn get_fn<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, instance: Instance<'tcx>) -> Function<'gcc> { let tcx = cx.tcx(); assert!(!instance.substs.needs_infer()); @@ -31,7 +29,9 @@ pub fn get_fn<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, instance: Instance<'tcx>, let fn_abi = cx.fn_abi_of_instance(instance, ty::List::empty()); let func = - if let Some(func) = cx.get_declared_value(&sym) { + if let Some(_func) = cx.get_declared_value(&sym) { + // FIXME: we never reach this because get_declared_value only returns global variables + // and here we try to get a function. unreachable!(); /* // Create a fn pointer with the new signature. @@ -70,10 +70,7 @@ pub fn get_fn<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, instance: Instance<'tcx>, } else { cx.linkage.set(FunctionType::Extern); - /*if sym == "rust_eh_personality" { - panic!(); - }*/ - let func = cx.declare_fn(&sym, &fn_abi, dont_cache); + let func = cx.declare_fn(&sym, &fn_abi); attributes::from_fn_attrs(cx, func, instance); @@ -171,9 +168,7 @@ pub fn get_fn<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, instance: Instance<'tcx>, func }; - //if !dont_cache { - cx.function_instances.borrow_mut().insert(instance, func); - //} + cx.function_instances.borrow_mut().insert(instance, func); func } diff --git a/src/context.rs b/src/context.rs index 62e30679efa5..a66e13b6008a 100644 --- a/src/context.rs +++ b/src/context.rs @@ -1,6 +1,6 @@ use std::cell::{Cell, RefCell}; -use gccjit::{Block, CType, Context, Function, FunctionPtrType, FunctionType, LValue, RValue, Type, FnAttribute}; +use gccjit::{Block, CType, Context, Function, FunctionPtrType, FunctionType, LValue, RValue, Type}; use rustc_codegen_ssa::base::wants_msvc_seh; use rustc_codegen_ssa::traits::{ BackendTypes, @@ -259,8 +259,8 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { pub fn rvalue_as_function(&self, value: RValue<'gcc>) -> Function<'gcc> { let function: Function<'gcc> = unsafe { std::mem::transmute(value) }; // FIXME: seems like self.functions get overwritten for rust_eh_personality. - /*debug_assert!(self.functions.borrow().values().find(|value| **value == function).is_some(), - "{:?} is not a function", function);*/ + debug_assert!(self.functions.borrow().values().find(|value| **value == function).is_some(), + "{:?} is not a function", function); function } @@ -332,7 +332,7 @@ impl<'gcc, 'tcx> MiscMethods<'tcx> for CodegenCx<'gcc, 'tcx> { } fn get_fn(&self, instance: Instance<'tcx>) -> RValue<'gcc> { - let func = get_fn(self, instance, false); + let func = get_fn(self, instance); *self.current_func.borrow_mut() = Some(func); unsafe { std::mem::transmute(func) } } @@ -345,7 +345,7 @@ impl<'gcc, 'tcx> MiscMethods<'tcx> for CodegenCx<'gcc, 'tcx> { self.intrinsics.borrow()[func_name].clone() } else { - get_fn(self, instance, false) + get_fn(self, instance) }; let ptr = func.get_address(None); @@ -386,8 +386,6 @@ impl<'gcc, 'tcx> MiscMethods<'tcx> for CodegenCx<'gcc, 'tcx> { let func = match tcx.lang_items().eh_personality() { Some(def_id) if !wants_msvc_seh(self.sess()) => { - // FIXME: this create an instance into self.functions and prevent the creating - // of the function defined in std. let instance = ty::Instance::resolve( tcx, @@ -400,45 +398,19 @@ impl<'gcc, 'tcx> MiscMethods<'tcx> for CodegenCx<'gcc, 'tcx> { let symbol_name = tcx.symbol_name(instance).name; let fn_abi = self.fn_abi_of_instance(instance, ty::List::empty()); self.linkage.set(FunctionType::Extern); - let func = self.declare_fn(symbol_name, &fn_abi, false); - //func.add_attribute(FnAttribute::Weak); - - /*let block = func.new_block("eh_personality_block"); - // NOTE: it seems this function is overwritten by the standard library, so just - // return a dummy value in this version. - let zero = self.context.new_rvalue_zero(self.type_u32()); - block.end_with_return(None, zero);*/ - - //*self.current_func.borrow_mut() = Some(func); + let func = self.declare_fn(symbol_name, &fn_abi); let func: RValue<'gcc> = unsafe { std::mem::transmute(func) }; func - /*self.get_fn( - ty::Instance::resolve( - tcx, - ty::ParamEnv::reveal_all(), - def_id, - tcx.intern_substs(&[]), - ) - .unwrap().unwrap(), - )*/ }, _ => { - let name = if wants_msvc_seh(self.sess()) { - "__CxxFrameHandler3" - } else { - "rust_eh_personality" - }; + let name = + if wants_msvc_seh(self.sess()) { + "__CxxFrameHandler3" + } + else { + "rust_eh_personality" + }; let func = self.declare_func(name, self.type_i32(), &[], true); - //*self.current_func.borrow_mut() = Some(func); - // NOTE: this function is created multiple times and is overwritten by the - // standard library, so mark it as weak. - //func.add_attribute(FnAttribute::Weak); - //self.functions.borrow_mut().insert(name.to_string(), func); - /*let block = func.new_block("eh_personality_block"); - // NOTE: it seems this function is overwritten by the standard library, so just - // return a dummy value in this version. - let zero = self.context.new_rvalue_zero(self.type_i32()); - block.end_with_return(None, zero);*/ unsafe { std::mem::transmute(func) } } }; diff --git a/src/declare.rs b/src/declare.rs index fdde82e8df77..b4b7d1b011ea 100644 --- a/src/declare.rs +++ b/src/declare.rs @@ -40,7 +40,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { pub fn declare_func(&self, name: &str, return_type: Type<'gcc>, params: &[Type<'gcc>], variadic: bool) -> Function<'gcc> { self.linkage.set(FunctionType::Extern); - declare_raw_fn(self, name, () /*llvm::CCallConv*/, return_type, params, variadic, true) + declare_raw_fn(self, name, () /*llvm::CCallConv*/, return_type, params, variadic) } pub fn declare_global(&self, name: &str, ty: Type<'gcc>, global_kind: GlobalKind, is_tls: bool, link_section: Option) -> LValue<'gcc> { @@ -69,7 +69,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { let return_type = self.type_i32(); let variadic = false; self.linkage.set(FunctionType::Exported); - let func = declare_raw_fn(self, name, () /*llvm::CCallConv*/, return_type, &[self.type_i32(), const_string], variadic, false); + let func = declare_raw_fn(self, name, () /*llvm::CCallConv*/, return_type, &[self.type_i32(), const_string], variadic); // NOTE: it is needed to set the current_func here as well, because get_fn() is not called // for the main function. *self.current_func.borrow_mut() = Some(func); @@ -77,19 +77,9 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { unsafe { std::mem::transmute(func) } } - pub fn declare_fn(&self, name: &str, fn_abi: &FnAbi<'tcx, Ty<'tcx>>, dont_cache: bool) -> Function<'gcc> { + pub fn declare_fn(&self, name: &str, fn_abi: &FnAbi<'tcx, Ty<'tcx>>) -> Function<'gcc> { let (return_type, params, variadic, on_stack_param_indices) = fn_abi.gcc_type(self); - /*static mut COUNTER: i32 = 0; - if name.contains("personality") { - println!("{}: {}", name, skip_cache); - unsafe { - COUNTER += 1; - if COUNTER == 6 { - panic!("{}", name); - } - } - }*/ - let func = declare_raw_fn(self, name, () /*fn_abi.llvm_cconv()*/, return_type, ¶ms, variadic, dont_cache); + let func = declare_raw_fn(self, name, () /*fn_abi.llvm_cconv()*/, return_type, ¶ms, variadic); self.on_stack_function_params.borrow_mut().insert(func, on_stack_param_indices); func } @@ -108,7 +98,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { /// /// If there’s a value with the same name already declared, the function will /// update the declaration and return existing Value instead. -fn declare_raw_fn<'gcc>(cx: &CodegenCx<'gcc, '_>, name: &str, _callconv: () /*llvm::CallConv*/, return_type: Type<'gcc>, param_types: &[Type<'gcc>], variadic: bool, dont_cache: bool) -> Function<'gcc> { +fn declare_raw_fn<'gcc>(cx: &CodegenCx<'gcc, '_>, name: &str, _callconv: () /*llvm::CallConv*/, return_type: Type<'gcc>, param_types: &[Type<'gcc>], variadic: bool) -> Function<'gcc> { if name.starts_with("llvm.") { let intrinsic = llvm::intrinsic(name, cx); cx.intrinsics.borrow_mut().insert(name.to_string(), intrinsic); @@ -123,9 +113,7 @@ fn declare_raw_fn<'gcc>(cx: &CodegenCx<'gcc, '_>, name: &str, _callconv: () /*ll .map(|(index, param)| cx.context.new_parameter(None, *param, &format!("param{}", index))) // TODO(antoyo): set name. .collect(); let func = cx.context.new_function(None, cx.linkage.get(), return_type, ¶ms, mangle_name(name), variadic); - //if !dont_cache { - cx.functions.borrow_mut().insert(name.to_string(), func); - //} + cx.functions.borrow_mut().insert(name.to_string(), func); func }; diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index ce7874a3de47..fa78325ec9d1 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -1118,9 +1118,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { } fn try_intrinsic<'a, 'b, 'gcc, 'tcx>(bx: &'b mut Builder<'a, 'gcc, 'tcx>, try_func: RValue<'gcc>, data: RValue<'gcc>, catch_func: RValue<'gcc>, dest: RValue<'gcc>) { - // NOTE: the `|| true` here is to use the panic=abort strategy with panic=unwind too if bx.sess().panic_strategy() == PanicStrategy::Abort { - // TODO(bjorn3): Properly implement unwinding and remove the `|| true` once this is done. bx.call(bx.type_void(), try_func, &[data], None); // Return 0 unconditionally from the intrinsic call; // we can never unwind. @@ -1238,7 +1236,7 @@ fn get_rust_try_fn<'a, 'gcc, 'tcx>(cx: &'a CodegenCx<'gcc, 'tcx>, codegen: &mut ))); // `unsafe fn(unsafe fn(*mut i8) -> (), *mut i8, unsafe fn(*mut i8, *mut i8) -> ()) -> i32` let rust_fn_sig = ty::Binder::dummy(cx.tcx.mk_fn_sig( - [try_fn_ty, i8p, catch_fn_ty].into_iter(), + [try_fn_ty, i8p, catch_fn_ty].iter(), &tcx.types.i32, false, rustc_hir::Unsafety::Unsafe, @@ -1256,7 +1254,7 @@ fn gen_fn<'a, 'gcc, 'tcx>(cx: &'a CodegenCx<'gcc, 'tcx>, name: &str, rust_fn_sig let (typ, _, _, _) = fn_abi.gcc_type(cx); // FIXME(eddyb) find a nicer way to do this. cx.linkage.set(FunctionType::Internal); - let func = cx.declare_fn(name, fn_abi, false); + let func = cx.declare_fn(name, fn_abi); let func_val = unsafe { std::mem::transmute(func) }; cx.set_frame_pointer_type(func_val); cx.apply_target_cpu_attr(func_val); diff --git a/src/mono_item.rs b/src/mono_item.rs index 3b7f9a0b6bc2..0491fffc8abf 100644 --- a/src/mono_item.rs +++ b/src/mono_item.rs @@ -35,7 +35,7 @@ impl<'gcc, 'tcx> PreDefineMethods<'tcx> for CodegenCx<'gcc, 'tcx> { let fn_abi = self.fn_abi_of_instance(instance, ty::List::empty()); self.linkage.set(base::linkage_to_gcc(linkage)); - let decl = self.declare_fn(symbol_name, &fn_abi, false); + let decl = self.declare_fn(symbol_name, &fn_abi); //let attrs = self.tcx.codegen_fn_attrs(instance.def_id()); attributes::from_fn_attrs(self, decl, instance); diff --git a/test.sh b/test.sh index 9cfb8eb0d078..5604fd4ff94b 100755 --- a/test.sh +++ b/test.sh @@ -191,11 +191,11 @@ function std_tests() { $RUN_WRAPPER ./target/out/std_example --target $TARGET_TRIPLE echo "[AOT] subslice-patterns-const-eval" - $RUSTC example/subslice-patterns-const-eval.rs --crate-type bin -Cpanic=abort --target $TARGET_TRIPLE + $RUSTC example/subslice-patterns-const-eval.rs --crate-type bin --target $TARGET_TRIPLE $RUN_WRAPPER ./target/out/subslice-patterns-const-eval echo "[AOT] track-caller-attribute" - $RUSTC example/track-caller-attribute.rs --crate-type bin -Cpanic=abort --target $TARGET_TRIPLE + $RUSTC example/track-caller-attribute.rs --crate-type bin --target $TARGET_TRIPLE $RUN_WRAPPER ./target/out/track-caller-attribute echo "[BUILD] mod_bench" @@ -340,6 +340,7 @@ function test_rustc() { rm -r src/test/ui/{abi*,extern/,panic-runtime/,panics/,unsized-locals/,proc-macro/,threads-sendsync/,thinlto/,borrowck/,chalkify/bugs/,test*,*lto*.rs,consts/const-float-bits-reject-conv.rs,consts/issue-miri-1910.rs} || true rm src/test/ui/mir/mir_heavy_promoted.rs # this tests is oom-killed in the CI. + # TODO: re-enable panics tests. for test in $(rg --files-with-matches "catch_unwind|should_panic|thread|lto" src/test/ui); do rm $test done @@ -348,7 +349,7 @@ function test_rustc() { git checkout src/test/ui/type-alias-impl-trait/auxiliary/cross_crate_ice2.rs git checkout src/test/ui/macros/rfc-2011-nicer-assert-messages/auxiliary/common.rs - RUSTC_ARGS="-Zpanic-abort-tests -Csymbol-mangling-version=v0 -Zcodegen-backend="$(pwd)"/../target/"$CHANNEL"/librustc_codegen_gcc."$dylib_ext" --sysroot "$(pwd)"/../build_sysroot/sysroot -Cpanic=abort" + RUSTC_ARGS="-Csymbol-mangling-version=v0 -Zcodegen-backend="$(pwd)"/../target/"$CHANNEL"/librustc_codegen_gcc."$dylib_ext" --sysroot "$(pwd)"/../build_sysroot/sysroot" if [ $# -eq 0 ]; then # No argument supplied to the function. Doing nothing. @@ -400,7 +401,7 @@ function all() { mini_tests build_sysroot std_tests - asm_tests + #asm_tests test_libcore extended_sysroot_tests test_rustc From af8db759be6e92e470a6af810f22b2ebc0cfc87f Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Mon, 9 Jan 2023 17:04:59 -0500 Subject: [PATCH 214/356] Support libgccjit12 --- .github/workflows/ci.yml | 10 +++++----- config.sh | 2 +- src/builder.rs | 39 +++++++++++++++++++++++++++------------ src/intrinsic/mod.rs | 27 +++++++++++++++++++++------ test.sh | 9 ++++----- 5 files changed, 58 insertions(+), 29 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 2fd27654dc41..1c99e5e2bc28 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -19,9 +19,9 @@ jobs: fail-fast: false matrix: libgccjit_version: - - { gcc: "libgccjit.so", extra: "", artifacts_branch: "master" } - - { gcc: "libgccjit_without_int128.so", extra: "", artifacts_branch: "master-without-128bit-integers" } - - { gcc: "libgccjit12.so", extra: "--no-default-features", artifacts_branch: "gcc12" } + - { gcc: "libgccjit.so", extra: "", env_extra: "", artifacts_branch: "master" } + - { gcc: "libgccjit_without_int128.so", extra: "", env_extra: "", artifacts_branch: "master-without-128bit-integers" } + - { gcc: "libgccjit12.so", extra: "--no-default-features", env_extra: "TEST_FLAGS='-Cpanic=abort -Zpanic-abort-tests'", artifacts_branch: "gcc12" } commands: [ "--mini-tests", "--std-tests", @@ -120,7 +120,7 @@ jobs: - name: Build run: | ./prepare_build.sh - ./build.sh ${{ matrix.libgccjit_version.extra }} + ${{ matrix.libgccjit_version.env_extra }} ./build.sh ${{ matrix.libgccjit_version.extra }} cargo test ${{ matrix.libgccjit_version.extra }} ./clean_all.sh @@ -143,7 +143,7 @@ jobs: - name: Run tests run: | - ./test.sh --release --clean --build-sysroot ${{ matrix.commands }} ${{ matrix.libgccjit_version.extra }} + ${{ matrix.libgccjit_version.env_extra }} ./test.sh --release --clean --build-sysroot ${{ matrix.commands }} ${{ matrix.libgccjit_version.extra }} duplicates: runs-on: ubuntu-latest diff --git a/config.sh b/config.sh index 6bad0586c5ba..166e83901c4f 100644 --- a/config.sh +++ b/config.sh @@ -38,7 +38,7 @@ if [[ "$HOST_TRIPLE" != "$TARGET_TRIPLE" ]]; then fi fi -export RUSTFLAGS="$CG_RUSTFLAGS $linker -Csymbol-mangling-version=v0 -Cdebuginfo=2 -Clto=off -Zcodegen-backend=$(pwd)/target/${CHANNEL:-debug}/librustc_codegen_gcc.$dylib_ext --sysroot $(pwd)/build_sysroot/sysroot" +export RUSTFLAGS="$CG_RUSTFLAGS $linker -Csymbol-mangling-version=v0 -Cdebuginfo=2 -Clto=off -Zcodegen-backend=$(pwd)/target/${CHANNEL:-debug}/librustc_codegen_gcc.$dylib_ext --sysroot $(pwd)/build_sysroot/sysroot $TEST_FLAGS" # FIXME(antoyo): remove once the atomic shim is gone if [[ `uname` == 'Darwin' ]]; then diff --git a/src/builder.rs b/src/builder.rs index 080a306e70eb..0150f5ba8c14 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -13,7 +13,7 @@ use gccjit::{ RValue, ToRValue, Type, - UnaryOp, FunctionType, + UnaryOp, }; use rustc_codegen_ssa::MemFlags; use rustc_codegen_ssa::common::{AtomicOrdering, AtomicRmwBinOp, IntPredicate, RealPredicate, SynchronizationScope}; @@ -476,11 +476,6 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { self.block.end_with_jump(None, then); - // NOTE: since jumps were added in a place rustc does not expect, the current blocks in the - // state need to be updated. - // FIXME: not sure it's actually needed. - self.switch_to_block(then); - return_value.to_rvalue() } @@ -1194,12 +1189,15 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { aggregate_value } - fn set_personality_fn(&mut self, personality: RValue<'gcc>) { - let personality = self.rvalue_as_function(personality); + fn set_personality_fn(&mut self, _personality: RValue<'gcc>) { #[cfg(feature="master")] - self.current_func().set_personality_function(personality); + { + let personality = self.rvalue_as_function(_personality); + self.current_func().set_personality_function(personality); + } } + #[cfg(feature="master")] fn cleanup_landing_pad(&mut self, _ty: Type<'gcc>, pers_fn: RValue<'gcc>) -> RValue<'gcc> { self.set_personality_fn(pers_fn); @@ -1223,16 +1221,33 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { value.to_rvalue() } + #[cfg(not(feature="master"))] + fn cleanup_landing_pad(&mut self, _ty: Type<'gcc>, _pers_fn: RValue<'gcc>) -> RValue<'gcc> { + let field1 = self.context.new_field(None, self.u8_type.make_pointer(), "landing_pad_field_1"); + let field2 = self.context.new_field(None, self.i32_type, "landing_pad_field_1"); + let struct_type = self.context.new_struct_type(None, "landing_pad", &[field1, field2]); + self.current_func().new_local(None, struct_type.as_type(), "landing_pad") + .to_rvalue() + } + + #[cfg(feature="master")] fn resume(&mut self, exn: RValue<'gcc>) { // TODO: check if this is normal that we need to dereference the value. + // NOTE: the type is wrong, so in order to get a pointer for parameter, cast it to a + // pointer of pointer that is later dereferenced. + let exn_type = exn.get_type().make_pointer(); + let exn = self.context.new_cast(None, exn, exn_type); let exn = exn.dereference(None).to_rvalue(); - let param = self.context.new_parameter(None, exn.get_type(), "exn"); - // TODO(antoyo): should we call __builtin_unwind_resume instead? This might actually be the same. - let unwind_resume = self.context.new_function(None, FunctionType::Extern, self.type_void(), &[param], "_Unwind_Resume", false); + let unwind_resume = self.context.get_target_builtin_function("__builtin_unwind_resume"); self.llbb().add_eval(None, self.context.new_call(None, unwind_resume, &[exn])); self.unreachable(); } + #[cfg(not(feature="master"))] + fn resume(&mut self, _exn: RValue<'gcc>) { + self.unreachable(); + } + fn cleanup_pad(&mut self, _parent: Option>, _args: &[RValue<'gcc>]) -> Funclet { unimplemented!(); } diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index fa78325ec9d1..46471096e910 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -1,6 +1,7 @@ pub mod llvm; mod simd; +#[cfg(feature="master")] use std::iter; use gccjit::{ComparisonOp, Function, RValue, ToRValue, Type, UnaryOp, FunctionType}; @@ -9,16 +10,24 @@ use rustc_codegen_ssa::base::wants_msvc_seh; use rustc_codegen_ssa::common::{IntPredicate, span_invalid_monomorphization_error}; use rustc_codegen_ssa::mir::operand::{OperandRef, OperandValue}; use rustc_codegen_ssa::mir::place::PlaceRef; -use rustc_codegen_ssa::traits::{ArgAbiMethods, BaseTypeMethods, BuilderMethods, ConstMethods, DerivedTypeMethods, IntrinsicCallMethods, MiscMethods}; +use rustc_codegen_ssa::traits::{ArgAbiMethods, BaseTypeMethods, BuilderMethods, ConstMethods, IntrinsicCallMethods}; +#[cfg(feature="master")] +use rustc_codegen_ssa::traits::{DerivedTypeMethods, MiscMethods}; use rustc_middle::bug; use rustc_middle::ty::{self, Instance, Ty}; -use rustc_middle::ty::layout::{FnAbiOf, HasTyCtxt, LayoutOf}; +use rustc_middle::ty::layout::LayoutOf; +#[cfg(feature="master")] +use rustc_middle::ty::layout::{FnAbiOf, HasTyCtxt}; use rustc_span::{Span, Symbol, symbol::kw, sym}; use rustc_target::abi::HasDataLayout; use rustc_target::abi::call::{ArgAbi, FnAbi, PassMode}; -use rustc_target::spec::{abi::Abi, PanicStrategy}; +use rustc_target::spec::PanicStrategy; +#[cfg(feature="master")] +use rustc_target::spec::abi::Abi; -use crate::abi::{FnAbiGccExt, GccType}; +use crate::abi::GccType; +#[cfg(feature="master")] +use crate::abi::FnAbiGccExt; use crate::builder::Builder; use crate::common::{SignType, TypeReflection}; use crate::context::CodegenCx; @@ -1117,7 +1126,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { } } -fn try_intrinsic<'a, 'b, 'gcc, 'tcx>(bx: &'b mut Builder<'a, 'gcc, 'tcx>, try_func: RValue<'gcc>, data: RValue<'gcc>, catch_func: RValue<'gcc>, dest: RValue<'gcc>) { +fn try_intrinsic<'a, 'b, 'gcc, 'tcx>(bx: &'b mut Builder<'a, 'gcc, 'tcx>, try_func: RValue<'gcc>, data: RValue<'gcc>, _catch_func: RValue<'gcc>, dest: RValue<'gcc>) { if bx.sess().panic_strategy() == PanicStrategy::Abort { bx.call(bx.type_void(), try_func, &[data], None); // Return 0 unconditionally from the intrinsic call; @@ -1129,7 +1138,10 @@ fn try_intrinsic<'a, 'b, 'gcc, 'tcx>(bx: &'b mut Builder<'a, 'gcc, 'tcx>, try_fu unimplemented!(); } else { - codegen_gnu_try(bx, try_func, data, catch_func, dest); + #[cfg(feature="master")] + codegen_gnu_try(bx, try_func, data, _catch_func, dest); + #[cfg(not(feature="master"))] + unimplemented!(); } } @@ -1144,6 +1156,7 @@ fn try_intrinsic<'a, 'b, 'gcc, 'tcx>(bx: &'b mut Builder<'a, 'gcc, 'tcx>, try_fu // function calling it, and that function may already have other personality // functions in play. By calling a shim we're guaranteed that our shim will have // the right personality function. +#[cfg(feature="master")] fn codegen_gnu_try<'gcc>(bx: &mut Builder<'_, 'gcc, '_>, try_func: RValue<'gcc>, data: RValue<'gcc>, catch_func: RValue<'gcc>, dest: RValue<'gcc>) { //use std::ops::Deref; //let cx: &CodegenCx<'gcc, '_> = bx.deref(); @@ -1210,6 +1223,7 @@ fn codegen_gnu_try<'gcc>(bx: &mut Builder<'_, 'gcc, '_>, try_func: RValue<'gcc>, // catch exceptions. // // This function is only generated once and is then cached. +#[cfg(feature="master")] fn get_rust_try_fn<'a, 'gcc, 'tcx>(cx: &'a CodegenCx<'gcc, 'tcx>, codegen: &mut dyn FnMut(Builder<'a, 'gcc, 'tcx>)) -> (Type<'gcc>, Function<'gcc>) { if let Some(llfn) = cx.rust_try_fn.get() { return llfn; @@ -1249,6 +1263,7 @@ fn get_rust_try_fn<'a, 'gcc, 'tcx>(cx: &'a CodegenCx<'gcc, 'tcx>, codegen: &mut // Helper function to give a Block to a closure to codegen a shim function. // This is currently primarily used for the `try` intrinsic functions above. +#[cfg(feature="master")] fn gen_fn<'a, 'gcc, 'tcx>(cx: &'a CodegenCx<'gcc, 'tcx>, name: &str, rust_fn_sig: ty::PolyFnSig<'tcx>, codegen: &mut dyn FnMut(Builder<'a, 'gcc, 'tcx>)) -> (Type<'gcc>, Function<'gcc>) { let fn_abi = cx.fn_abi_of_fn_ptr(rust_fn_sig, ty::List::empty()); let (typ, _, _, _) = fn_abi.gcc_type(cx); diff --git a/test.sh b/test.sh index 5604fd4ff94b..25f5a3a419ef 100755 --- a/test.sh +++ b/test.sh @@ -191,11 +191,11 @@ function std_tests() { $RUN_WRAPPER ./target/out/std_example --target $TARGET_TRIPLE echo "[AOT] subslice-patterns-const-eval" - $RUSTC example/subslice-patterns-const-eval.rs --crate-type bin --target $TARGET_TRIPLE + $RUSTC example/subslice-patterns-const-eval.rs --crate-type bin $TEST_FLAGS --target $TARGET_TRIPLE $RUN_WRAPPER ./target/out/subslice-patterns-const-eval echo "[AOT] track-caller-attribute" - $RUSTC example/track-caller-attribute.rs --crate-type bin --target $TARGET_TRIPLE + $RUSTC example/track-caller-attribute.rs --crate-type bin $TEST_FLAGS --target $TARGET_TRIPLE $RUN_WRAPPER ./target/out/track-caller-attribute echo "[BUILD] mod_bench" @@ -338,10 +338,9 @@ function test_rustc() { git checkout -- src/test/ui/issues/auxiliary/issue-3136-a.rs # contains //~ERROR, but shouldn't be removed - rm -r src/test/ui/{abi*,extern/,panic-runtime/,panics/,unsized-locals/,proc-macro/,threads-sendsync/,thinlto/,borrowck/,chalkify/bugs/,test*,*lto*.rs,consts/const-float-bits-reject-conv.rs,consts/issue-miri-1910.rs} || true + rm -r src/test/ui/{abi*,extern/,unsized-locals/,proc-macro/,threads-sendsync/,thinlto/,borrowck/,chalkify/bugs/,test*,*lto*.rs,consts/const-float-bits-reject-conv.rs,consts/issue-miri-1910.rs} || true rm src/test/ui/mir/mir_heavy_promoted.rs # this tests is oom-killed in the CI. - # TODO: re-enable panics tests. - for test in $(rg --files-with-matches "catch_unwind|should_panic|thread|lto" src/test/ui); do + for test in $(rg --files-with-matches "thread|lto" src/test/ui); do rm $test done git checkout src/test/ui/lto/auxiliary/dylib.rs From 2bf7fb402b88b0345847db65c0857f2d81ea54db Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Mon, 9 Jan 2023 17:12:08 -0500 Subject: [PATCH 215/356] Use gccjit from repo --- Cargo.lock | 2 ++ Cargo.toml | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index e52e742ec6ce..e20980caee16 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -41,6 +41,7 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" +source = "git+https://github.com/antoyo/gccjit.rs#1e6ecc67fe73ac995e511516eacf4fe3aec8974e" dependencies = [ "gccjit_sys", ] @@ -48,6 +49,7 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" +source = "git+https://github.com/antoyo/gccjit.rs#1e6ecc67fe73ac995e511516eacf4fe3aec8974e" dependencies = [ "libc 0.1.12", ] diff --git a/Cargo.toml b/Cargo.toml index 26a0e92923d5..3ac354ea4942 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -22,10 +22,10 @@ default = ["master"] master = ["gccjit/master"] [dependencies] -#gccjit = { git = "https://github.com/antoyo/gccjit.rs" } +gccjit = { git = "https://github.com/antoyo/gccjit.rs" } # Local copy. -gccjit = { path = "../gccjit.rs" } +#gccjit = { path = "../gccjit.rs" } smallvec = { version = "1.6.1", features = ["union", "may_dangle"] } target-lexicon = "0.10.0" From f1f136bb661725dbf283280a793410b7abe2ad73 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Mon, 9 Jan 2023 17:27:28 -0500 Subject: [PATCH 216/356] Fix tests --- tests/lang_tests_common.rs | 1 - tests/run/int.rs | 16 +++------------- 2 files changed, 3 insertions(+), 14 deletions(-) diff --git a/tests/lang_tests_common.rs b/tests/lang_tests_common.rs index 8e378177e245..53d3266776d0 100644 --- a/tests/lang_tests_common.rs +++ b/tests/lang_tests_common.rs @@ -46,7 +46,6 @@ pub fn main_inner(profile: Profile) { &format!("-Zcodegen-backend={}/target/debug/librustc_codegen_gcc.so", current_dir), "--sysroot", &format!("{}/build_sysroot/sysroot/", current_dir), "-Zno-parallel-llvm", - "-C", "panic=abort", "-C", "link-arg=-lc", "-o", exe.to_str().expect("to_str"), path.to_str().expect("to_str"), diff --git a/tests/run/int.rs b/tests/run/int.rs index 2b90e4ae8d82..5693b6a215a6 100644 --- a/tests/run/int.rs +++ b/tests/run/int.rs @@ -3,22 +3,14 @@ // Run-time: // status: 0 -#![feature(bench_black_box, const_black_box, core_intrinsics, start)] - -#![no_std] - -#[panic_handler] -fn panic_handler(_: &core::panic::PanicInfo) -> ! { - core::intrinsics::abort(); -} +#![feature(bench_black_box, const_black_box)] /* * Code */ -#[start] -fn main(_argc: isize, _argv: *const *const u8) -> isize { - use core::hint::black_box; +fn main() { + use std::hint::black_box; macro_rules! check { ($ty:ty, $expr:expr) => { @@ -335,6 +327,4 @@ fn main(_argc: isize, _argv: *const *const u8) -> isize { const VAL5: T = 73236519889708027473620326106273939584_i128; check_ops128!(); } - - 0 } From 4b628e5334fdfab981dc29862d3a806482b493df Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Mon, 9 Jan 2023 17:42:35 -0500 Subject: [PATCH 217/356] Fix tests --- .github/workflows/ci.yml | 2 +- tests/lang_tests_common.rs | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 1c99e5e2bc28..927eb3077616 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -121,7 +121,7 @@ jobs: run: | ./prepare_build.sh ${{ matrix.libgccjit_version.env_extra }} ./build.sh ${{ matrix.libgccjit_version.extra }} - cargo test ${{ matrix.libgccjit_version.extra }} + ${{ matrix.libgccjit_version.env_extra }} cargo test ${{ matrix.libgccjit_version.extra }} ./clean_all.sh - name: Prepare dependencies diff --git a/tests/lang_tests_common.rs b/tests/lang_tests_common.rs index 53d3266776d0..06de26f7efc9 100644 --- a/tests/lang_tests_common.rs +++ b/tests/lang_tests_common.rs @@ -50,6 +50,11 @@ pub fn main_inner(profile: Profile) { "-o", exe.to_str().expect("to_str"), path.to_str().expect("to_str"), ]); + if let Some(flags) = option_env!("TEST_FLAGS") { + for flag in flags.split_whitespace() { + compiler.arg(&flag); + } + } match profile { Profile::Debug => {} Profile::Release => { From e87b01447f05fdee6846a21520d5f7b059d39604 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Mon, 9 Jan 2023 18:08:50 -0500 Subject: [PATCH 218/356] Add missing failing tests --- failing-ui-tests.txt | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index 6182353599b2..1ba38498a75b 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -41,3 +41,18 @@ src/test/ui/sse2.rs src/test/ui/statics/issue-91050-1.rs src/test/ui/statics/issue-91050-2.rs src/test/ui/target-feature/missing-plusminus.rs +src/test/ui/asm/x86_64/may_unwind.rs +src/test/ui/backtrace.rs +src/test/ui/catch-unwind-bang.rs +src/test/ui/cfg/cfg-panic-abort.rs +src/test/ui/drop/dynamic-drop-async.rs +src/test/ui/drop/repeat-drop.rs +src/test/ui/fmt/format-args-capture.rs +src/test/ui/generator/panic-drops-resume.rs +src/test/ui/generator/panic-drops.rs +src/test/ui/generator/panic-safe.rs +src/test/ui/intrinsics/panic-uninitialized-zeroed.rs#mir +src/test/ui/intrinsics/panic-uninitialized-zeroed.rs#strict +src/test/ui/intrinsics/panic-uninitialized-zeroed.rs#thir +src/test/ui/issues/issue-14875.rs +src/test/ui/issues/issue-29948.rs From 5f8cdd2d3646da3a36e5794abbbe440f460034dc Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Mon, 9 Jan 2023 18:27:16 -0500 Subject: [PATCH 219/356] Fix tests --- failing-ui-tests.txt | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index 1ba38498a75b..13351fd0e7eb 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -51,8 +51,6 @@ src/test/ui/fmt/format-args-capture.rs src/test/ui/generator/panic-drops-resume.rs src/test/ui/generator/panic-drops.rs src/test/ui/generator/panic-safe.rs -src/test/ui/intrinsics/panic-uninitialized-zeroed.rs#mir -src/test/ui/intrinsics/panic-uninitialized-zeroed.rs#strict -src/test/ui/intrinsics/panic-uninitialized-zeroed.rs#thir +src/test/ui/intrinsics/panic-uninitialized-zeroed.rs src/test/ui/issues/issue-14875.rs src/test/ui/issues/issue-29948.rs From ea75295180aeb8265bf5c5317206abc4c21ea33f Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Mon, 9 Jan 2023 19:30:28 -0500 Subject: [PATCH 220/356] Fix tests --- failing-ui-tests.txt | 13 +++++++++++++ test.sh | 2 +- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index 13351fd0e7eb..2629144f1674 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -54,3 +54,16 @@ src/test/ui/generator/panic-safe.rs src/test/ui/intrinsics/panic-uninitialized-zeroed.rs src/test/ui/issues/issue-14875.rs src/test/ui/issues/issue-29948.rs +src/test/ui/issues/issue-43853.rs +src/test/ui/iterators/iter-sum-overflow-debug.rs +src/test/ui/iterators/iter-sum-overflow-overflow-checks.rs +src/test/ui/mir/mir_calls_to_shims.rs +src/test/ui/mir/mir_drop_order.rs +src/test/ui/mir/mir_let_chains_drop_order.rs +src/test/ui/oom_unwind.rs +src/test/ui/panic-runtime/abort-link-to-unwinding-crates.rs +src/test/ui/panic-runtime/abort.rs +src/test/ui/panic-runtime/link-to-abort.rs +src/test/ui/rfc-2091-track-caller/std-panic-locations.rs +src/test/ui/rfcs/rfc1857-drop-order.rs +src/test/ui/unwind-no-uwtable.rs diff --git a/test.sh b/test.sh index 25f5a3a419ef..4c490f04ae9d 100755 --- a/test.sh +++ b/test.sh @@ -348,7 +348,7 @@ function test_rustc() { git checkout src/test/ui/type-alias-impl-trait/auxiliary/cross_crate_ice2.rs git checkout src/test/ui/macros/rfc-2011-nicer-assert-messages/auxiliary/common.rs - RUSTC_ARGS="-Csymbol-mangling-version=v0 -Zcodegen-backend="$(pwd)"/../target/"$CHANNEL"/librustc_codegen_gcc."$dylib_ext" --sysroot "$(pwd)"/../build_sysroot/sysroot" + RUSTC_ARGS="$TEST_FLAGS -Csymbol-mangling-version=v0 -Zcodegen-backend="$(pwd)"/../target/"$CHANNEL"/librustc_codegen_gcc."$dylib_ext" --sysroot "$(pwd)"/../build_sysroot/sysroot" if [ $# -eq 0 ]; then # No argument supplied to the function. Doing nothing. From 246ba9b39394054751f29e92128706aa73775719 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Mon, 9 Jan 2023 22:19:10 -0500 Subject: [PATCH 221/356] Add missing libgccjit 12 failing tests --- failing-ui-tests12.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/failing-ui-tests12.txt b/failing-ui-tests12.txt index 32feb2c886b2..e52248b1d0b7 100644 --- a/failing-ui-tests12.txt +++ b/failing-ui-tests12.txt @@ -22,3 +22,12 @@ src/test/ui/simd/intrinsic/inlining-issue67557.rs src/test/ui/simd/monomorphize-shuffle-index.rs src/test/ui/simd/shuffle.rs src/test/ui/simd/simd-bitmask.rs +src/test/ui/binding/fn-arg-incomplete-pattern-drop-order.rs +src/test/ui/drop/dynamic-drop.rs +src/test/ui/generator/resume-after-return.rs +src/test/ui/iterators/iter-step-overflow-debug.rs +src/test/ui/macros/rfc-2011-nicer-assert-messages/all-expr-kinds.rs +src/test/ui/numbers-arithmetic/next-power-of-two-overflow-debug.rs +src/test/ui/panic-while-printing.rs +src/test/ui/privacy/reachable-unnameable-items.rs +src/test/ui/rfc-1937-termination-trait/termination-trait-in-test.rs From 8e77fbf0cce0fbbc780819ad81459bba2e0ba0c0 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Tue, 10 Jan 2023 18:38:50 -0500 Subject: [PATCH 222/356] Fix LLVM builtin mapping --- src/intrinsic/llvm.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 4552ab95e537..ee0ea6e993f9 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -705,9 +705,9 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.aesni.aesenclast.512" => "__builtin_ia32_vaesenclast_v64qi", "llvm.x86.aesni.aesdec.512" => "__builtin_ia32_vaesdec_v64qi", "llvm.x86.aesni.aesdeclast.512" => "__builtin_ia32_vaesdeclast_v64qi", - "llvm.x86.avx512bf16.cvtne2ps2bf16.128" => "__builtin_ia32_cvtne2ps2bf16_v8hi", - "llvm.x86.avx512bf16.cvtne2ps2bf16.256" => "__builtin_ia32_cvtne2ps2bf16_v16hi", - "llvm.x86.avx512bf16.cvtne2ps2bf16.512" => "__builtin_ia32_cvtne2ps2bf16_v32hi", + "llvm.x86.avx512bf16.cvtne2ps2bf16.128" => "__builtin_ia32_cvtne2ps2bf16_v8bf", + "llvm.x86.avx512bf16.cvtne2ps2bf16.256" => "__builtin_ia32_cvtne2ps2bf16_v16bf", + "llvm.x86.avx512bf16.cvtne2ps2bf16.512" => "__builtin_ia32_cvtne2ps2bf16_v32bf", "llvm.x86.avx512bf16.cvtneps2bf16.256" => "__builtin_ia32_cvtneps2bf16_v8sf", "llvm.x86.avx512bf16.cvtneps2bf16.512" => "__builtin_ia32_cvtneps2bf16_v16sf", "llvm.x86.avx512bf16.dpbf16ps.128" => "__builtin_ia32_dpbf16ps_v4sf", From 7fa06f6b882bd0ee9366f31ccf4ae948a16494f9 Mon Sep 17 00:00:00 2001 From: bjorn3 <17426603+bjorn3@users.noreply.github.com> Date: Tue, 13 Dec 2022 17:26:17 +0100 Subject: [PATCH 223/356] Avoid a hir access inside get_static --- src/consts.rs | 133 ++++++++++++++++++++------------------------------ 1 file changed, 53 insertions(+), 80 deletions(-) diff --git a/src/consts.rs b/src/consts.rs index 9307d280f61c..d70c9076897b 100644 --- a/src/consts.rs +++ b/src/consts.rs @@ -2,9 +2,7 @@ use gccjit::FnAttribute; use gccjit::{Function, GlobalKind, LValue, RValue, ToRValue, Type}; use rustc_codegen_ssa::traits::{BaseTypeMethods, ConstMethods, DerivedTypeMethods, StaticMethods}; -use rustc_hir as hir; -use rustc_hir::Node; -use rustc_middle::{bug, span_bug}; +use rustc_middle::span_bug; use rustc_middle::middle::codegen_fn_attrs::{CodegenFnAttrFlags, CodegenFnAttrs}; use rustc_middle::mir::mono::MonoItem; use rustc_middle::ty::{self, Instance, Ty}; @@ -217,84 +215,59 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { let ty = instance.ty(self.tcx, ty::ParamEnv::reveal_all()); let sym = self.tcx.symbol_name(instance).name; - let global = - if let Some(def_id) = def_id.as_local() { - let id = self.tcx.hir().local_def_id_to_hir_id(def_id); - let llty = self.layout_of(ty).gcc_type(self); - // FIXME: refactor this to work without accessing the HIR - let global = match self.tcx.hir().get(id) { - Node::Item(&hir::Item { span, kind: hir::ItemKind::Static(..), .. }) => { - if let Some(global) = self.get_declared_value(&sym) { - if self.val_ty(global) != self.type_ptr_to(llty) { - span_bug!(span, "Conflicting types for static"); - } - } - - let is_tls = fn_attrs.flags.contains(CodegenFnAttrFlags::THREAD_LOCAL); - let global = self.declare_global( - &sym, - llty, - GlobalKind::Exported, - is_tls, - fn_attrs.link_section, - ); - - if !self.tcx.is_reachable_non_generic(def_id) { - // TODO(antoyo): set visibility. - } - - global - } - - Node::ForeignItem(&hir::ForeignItem { - span, - kind: hir::ForeignItemKind::Static(..), - .. - }) => { - let fn_attrs = self.tcx.codegen_fn_attrs(def_id); - check_and_apply_linkage(&self, &fn_attrs, ty, sym, span) - } - - item => bug!("get_static: expected static, found {:?}", item), - }; - - global - } - else { - // FIXME(nagisa): perhaps the map of externs could be offloaded to llvm somehow? - //debug!("get_static: sym={} item_attr={:?}", sym, self.tcx.item_attrs(def_id)); - - let attrs = self.tcx.codegen_fn_attrs(def_id); - let span = self.tcx.def_span(def_id); - let global = check_and_apply_linkage(&self, &attrs, ty, sym, span); - - let needs_dll_storage_attr = false; // TODO(antoyo) - - // If this assertion triggers, there's something wrong with commandline - // argument validation. - debug_assert!( - !(self.tcx.sess.opts.cg.linker_plugin_lto.enabled() - && self.tcx.sess.target.options.is_like_msvc - && self.tcx.sess.opts.cg.prefer_dynamic) - ); - - if needs_dll_storage_attr { - // This item is external but not foreign, i.e., it originates from an external Rust - // crate. Since we don't know whether this crate will be linked dynamically or - // statically in the final application, we always mark such symbols as 'dllimport'. - // If final linkage happens to be static, we rely on compiler-emitted __imp_ stubs - // to make things work. - // - // However, in some scenarios we defer emission of statics to downstream - // crates, so there are cases where a static with an upstream DefId - // is actually present in the current crate. We can find out via the - // is_codegened_item query. - if !self.tcx.is_codegened_item(def_id) { - unimplemented!(); - } + let global = if def_id.is_local() && !self.tcx.is_foreign_item(def_id) { + let llty = self.layout_of(ty).gcc_type(self); + if let Some(global) = self.get_declared_value(sym) { + if self.val_ty(global) != self.type_ptr_to(llty) { + span_bug!(self.tcx.def_span(def_id), "Conflicting types for static"); } - global - }; + } + + let is_tls = fn_attrs.flags.contains(CodegenFnAttrFlags::THREAD_LOCAL); + let global = self.declare_global( + &sym, + llty, + GlobalKind::Exported, + is_tls, + fn_attrs.link_section, + ); + + if !self.tcx.is_reachable_non_generic(def_id) { + // TODO(antoyo): set visibility. + } + + global + } else { + check_and_apply_linkage(&self, &fn_attrs, ty, sym, self.tcx.def_span(def_id)) + }; + + if !def_id.is_local() { + let needs_dll_storage_attr = false; // TODO(antoyo) + + // If this assertion triggers, there's something wrong with commandline + // argument validation. + debug_assert!( + !(self.tcx.sess.opts.cg.linker_plugin_lto.enabled() + && self.tcx.sess.target.options.is_like_msvc + && self.tcx.sess.opts.cg.prefer_dynamic) + ); + + if needs_dll_storage_attr { + // This item is external but not foreign, i.e., it originates from an external Rust + // crate. Since we don't know whether this crate will be linked dynamically or + // statically in the final application, we always mark such symbols as 'dllimport'. + // If final linkage happens to be static, we rely on compiler-emitted __imp_ stubs + // to make things work. + // + // However, in some scenarios we defer emission of statics to downstream + // crates, so there are cases where a static with an upstream DefId + // is actually present in the current crate. We can find out via the + // is_codegened_item query. + if !self.tcx.is_codegened_item(def_id) { + unimplemented!(); + } + } + } // TODO(antoyo): set dll storage class. From f5ced68a6688016e06464cf6dc942e5bf8f4620b Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 22 Jan 2023 20:16:46 -0500 Subject: [PATCH 224/356] Adjust failing tests --- failing-ui-tests.txt | 17 ----------------- failing-ui-tests12.txt | 7 +++++++ 2 files changed, 7 insertions(+), 17 deletions(-) diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index 2629144f1674..f3784e65ce90 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -9,22 +9,14 @@ src/test/ui/allocator/xcrate-use.rs src/test/ui/allocator/xcrate-use2.rs src/test/ui/asm/may_unwind.rs src/test/ui/asm/x86_64/multiple-clobber-abi.rs -src/test/ui/async-await/async-fn-size-moved-locals.rs -src/test/ui/async-await/async-fn-size-uninit-locals.rs -src/test/ui/cfg/cfg-panic.rs src/test/ui/debuginfo/debuginfo-emit-llvm-ir-and-split-debuginfo.rs src/test/ui/functions-closures/parallel-codegen-closures.rs -src/test/ui/generator/size-moved-locals.rs -src/test/ui/issues/issue-40883.rs -src/test/ui/issues/issue-47364.rs src/test/ui/linkage-attr/linkage1.rs src/test/ui/lto/dylib-works.rs -src/test/ui/macros/rfc-2011-nicer-assert-messages/all-not-available-cases.rs src/test/ui/macros/rfc-2011-nicer-assert-messages/assert-without-captures-does-not-create-unnecessary-code.rs src/test/ui/numbers-arithmetic/saturating-float-casts.rs src/test/ui/polymorphization/promoted-function.rs src/test/ui/process/nofile-limit.rs -src/test/ui/runtime/rt-explody-panic-payloads.rs src/test/ui/sepcomp/sepcomp-cci.rs src/test/ui/sepcomp/sepcomp-extern.rs src/test/ui/sepcomp/sepcomp-fns-backwards.rs @@ -32,14 +24,8 @@ src/test/ui/sepcomp/sepcomp-fns.rs src/test/ui/sepcomp/sepcomp-statics.rs src/test/ui/simd/intrinsic/generic-arithmetic-pass.rs src/test/ui/simd/intrinsic/generic-gather-pass.rs -src/test/ui/simd/issue-17170.rs -src/test/ui/simd/issue-39720.rs -src/test/ui/simd/issue-85915-simd-ptrs.rs -src/test/ui/simd/issue-89193.rs src/test/ui/simd/type-generic-monomorphisation-extern-nonnull-ptr.rs src/test/ui/sse2.rs -src/test/ui/statics/issue-91050-1.rs -src/test/ui/statics/issue-91050-2.rs src/test/ui/target-feature/missing-plusminus.rs src/test/ui/asm/x86_64/may_unwind.rs src/test/ui/backtrace.rs @@ -52,9 +38,6 @@ src/test/ui/generator/panic-drops-resume.rs src/test/ui/generator/panic-drops.rs src/test/ui/generator/panic-safe.rs src/test/ui/intrinsics/panic-uninitialized-zeroed.rs -src/test/ui/issues/issue-14875.rs -src/test/ui/issues/issue-29948.rs -src/test/ui/issues/issue-43853.rs src/test/ui/iterators/iter-sum-overflow-debug.rs src/test/ui/iterators/iter-sum-overflow-overflow-checks.rs src/test/ui/mir/mir_calls_to_shims.rs diff --git a/failing-ui-tests12.txt b/failing-ui-tests12.txt index e52248b1d0b7..64c8bcdf5c2c 100644 --- a/failing-ui-tests12.txt +++ b/failing-ui-tests12.txt @@ -31,3 +31,10 @@ src/test/ui/numbers-arithmetic/next-power-of-two-overflow-debug.rs src/test/ui/panic-while-printing.rs src/test/ui/privacy/reachable-unnameable-items.rs src/test/ui/rfc-1937-termination-trait/termination-trait-in-test.rs +src/test/ui/async-await/async-fn-size-moved-locals.rs +src/test/ui/async-await/async-fn-size-uninit-locals.rs +src/test/ui/cfg/cfg-panic.rs +src/test/ui/generator/size-moved-locals.rs +src/test/ui/macros/rfc-2011-nicer-assert-messages/all-not-available-cases.rs +src/test/ui/runtime/rt-explody-panic-payloads.rs +src/test/ui/simd/issue-17170.rs From fa6ae3c8bbf8ae2351e548c09fb39745207e1e43 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 22 Jan 2023 20:22:09 -0500 Subject: [PATCH 225/356] Cleanup --- Readme.md | 4 ++-- failing-ui-tests.txt | 15 +++++++++++++-- failing-ui-tests12.txt | 1 - src/builder.rs | 7 +++---- src/callee.rs | 2 +- src/context.rs | 2 +- src/intrinsic/mod.rs | 4 +--- 7 files changed, 21 insertions(+), 14 deletions(-) diff --git a/Readme.md b/Readme.md index 3201afbd7820..b473f79a526b 100644 --- a/Readme.md +++ b/Readme.md @@ -172,7 +172,7 @@ debug_gimple_stmt(gimple_struct) To get the `rustc` command to run in `gdb`, add the `--verbose` flag to `cargo build`. -To have the correct file paths in `gdb` instead of `/usr/src/debug/gcc/libstdc++-v3/libsupc++/eh_personality.cc`, TODO +To have the correct file paths in `gdb` instead of `/usr/src/debug/gcc/libstdc++-v3/libsupc++/eh_personality.cc`: Maybe by calling the following at the beginning of gdb: @@ -180,7 +180,7 @@ Maybe by calling the following at the beginning of gdb: set substitute-path /usr/src/debug/gcc /path/to/gcc-repo/gcc ``` -TODO: but that's not what I remember I was doing. +TODO(antoyo): but that's not what I remember I was doing. ### How to use a custom-build rustc diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index f3784e65ce90..a51a7f1428e3 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -13,7 +13,6 @@ src/test/ui/debuginfo/debuginfo-emit-llvm-ir-and-split-debuginfo.rs src/test/ui/functions-closures/parallel-codegen-closures.rs src/test/ui/linkage-attr/linkage1.rs src/test/ui/lto/dylib-works.rs -src/test/ui/macros/rfc-2011-nicer-assert-messages/assert-without-captures-does-not-create-unnecessary-code.rs src/test/ui/numbers-arithmetic/saturating-float-casts.rs src/test/ui/polymorphization/promoted-function.rs src/test/ui/process/nofile-limit.rs @@ -47,6 +46,18 @@ src/test/ui/oom_unwind.rs src/test/ui/panic-runtime/abort-link-to-unwinding-crates.rs src/test/ui/panic-runtime/abort.rs src/test/ui/panic-runtime/link-to-abort.rs +src/test/ui/unwind-no-uwtable.rs +src/test/ui/issues/issue-14875.rs +src/test/ui/issues/issue-29948.rs +src/test/ui/issues/issue-40883.rs +src/test/ui/issues/issue-43853.rs +src/test/ui/issues/issue-47364.rs +src/test/ui/simd/issue-17170.rs +src/test/ui/simd/issue-39720.rs +src/test/ui/simd/issue-85915-simd-ptrs.rs +src/test/ui/simd/issue-89193.rs +src/test/ui/statics/issue-91050-1.rs +src/test/ui/statics/issue-91050-2.rs +src/test/ui/macros/rfc-2011-nicer-assert-messages/assert-without-captures-does-not-create-unnecessary-code.rs src/test/ui/rfc-2091-track-caller/std-panic-locations.rs src/test/ui/rfcs/rfc1857-drop-order.rs -src/test/ui/unwind-no-uwtable.rs diff --git a/failing-ui-tests12.txt b/failing-ui-tests12.txt index 64c8bcdf5c2c..22441efeee9f 100644 --- a/failing-ui-tests12.txt +++ b/failing-ui-tests12.txt @@ -37,4 +37,3 @@ src/test/ui/cfg/cfg-panic.rs src/test/ui/generator/size-moved-locals.rs src/test/ui/macros/rfc-2011-nicer-assert-messages/all-not-available-cases.rs src/test/ui/runtime/rt-explody-panic-payloads.rs -src/test/ui/simd/issue-17170.rs diff --git a/src/builder.rs b/src/builder.rs index 0150f5ba8c14..6ac1daeca5d9 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -375,8 +375,7 @@ impl<'tcx> FnAbiOfHelpers<'tcx> for Builder<'_, '_, 'tcx> { impl<'a, 'gcc, 'tcx> Deref for Builder<'a, 'gcc, 'tcx> { type Target = CodegenCx<'gcc, 'tcx>; - fn deref<'b>(&'b self) -> &'a Self::Target - { + fn deref<'b>(&'b self) -> &'a Self::Target { self.cx } } @@ -1216,7 +1215,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { let value = self.current_func().new_local(None, struct_type.as_type(), "landing_pad"); let ptr = self.cx.context.new_cast(None, ptr, field1_type); self.block.add_assignment(None, value.access_field(None, field1), ptr); - self.block.add_assignment(None, value.access_field(None, field2), zero); // TODO: set the proper value here (the type of exception?). + self.block.add_assignment(None, value.access_field(None, field2), zero); // TODO(antoyo): set the proper value here (the type of exception?). value.to_rvalue() } @@ -1232,7 +1231,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { #[cfg(feature="master")] fn resume(&mut self, exn: RValue<'gcc>) { - // TODO: check if this is normal that we need to dereference the value. + // TODO(antoyo): check if this is normal that we need to dereference the value. // NOTE: the type is wrong, so in order to get a pointer for parameter, cast it to a // pointer of pointer that is later dereferenced. let exn_type = exn.get_type().make_pointer(); diff --git a/src/callee.rs b/src/callee.rs index 70cdece7f0af..bc68340e7a07 100644 --- a/src/callee.rs +++ b/src/callee.rs @@ -30,7 +30,7 @@ pub fn get_fn<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, instance: Instance<'tcx>) let func = if let Some(_func) = cx.get_declared_value(&sym) { - // FIXME: we never reach this because get_declared_value only returns global variables + // FIXME(antoyo): we never reach this because get_declared_value only returns global variables // and here we try to get a function. unreachable!(); /* diff --git a/src/context.rs b/src/context.rs index a66e13b6008a..07222c534401 100644 --- a/src/context.rs +++ b/src/context.rs @@ -258,7 +258,6 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { pub fn rvalue_as_function(&self, value: RValue<'gcc>) -> Function<'gcc> { let function: Function<'gcc> = unsafe { std::mem::transmute(value) }; - // FIXME: seems like self.functions get overwritten for rust_eh_personality. debug_assert!(self.functions.borrow().values().find(|value| **value == function).is_some(), "{:?} is not a function", function); function @@ -334,6 +333,7 @@ impl<'gcc, 'tcx> MiscMethods<'tcx> for CodegenCx<'gcc, 'tcx> { fn get_fn(&self, instance: Instance<'tcx>) -> RValue<'gcc> { let func = get_fn(self, instance); *self.current_func.borrow_mut() = Some(func); + // FIXME(antoyo): this is a wrong cast. That requires changing the compiler API. unsafe { std::mem::transmute(func) } } diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index 46471096e910..6ca171801159 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -1158,8 +1158,6 @@ fn try_intrinsic<'a, 'b, 'gcc, 'tcx>(bx: &'b mut Builder<'a, 'gcc, 'tcx>, try_fu // the right personality function. #[cfg(feature="master")] fn codegen_gnu_try<'gcc>(bx: &mut Builder<'_, 'gcc, '_>, try_func: RValue<'gcc>, data: RValue<'gcc>, catch_func: RValue<'gcc>, dest: RValue<'gcc>) { - //use std::ops::Deref; - //let cx: &CodegenCx<'gcc, '_> = bx.deref(); let cx: &CodegenCx<'gcc, '_> = bx.cx; let (llty, func) = get_rust_try_fn(cx, &mut |mut bx| { // Codegens the shims described above: @@ -1204,7 +1202,7 @@ fn codegen_gnu_try<'gcc>(bx: &mut Builder<'_, 'gcc, '_>, try_func: RValue<'gcc>, // NOTE: the blocks must be filled before adding the try/catch, otherwise gcc will not // generate a try/catch. - // FIXME: add a check in the libgccjit API to prevent this. + // FIXME(antoyo): add a check in the libgccjit API to prevent this. bx.switch_to_block(current_block); bx.invoke(try_func_ty, try_func, &[data], then, catch, None); }); From 41f5e701e69a164acae301574938c30e2fd605a5 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 22 Jan 2023 21:22:49 -0500 Subject: [PATCH 226/356] Fix signed integer overflow --- .github/workflows/release.yml | 3 ++- src/base.rs | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml index 2e81442298c6..c60c96d2023e 100644 --- a/.github/workflows/release.yml +++ b/.github/workflows/release.yml @@ -104,7 +104,8 @@ jobs: - name: Run tests run: | - ./test.sh --release --clean --release-sysroot --build-sysroot --mini-tests --std-tests # --test-libcore # FIXME(antoyo): libcore tests fail. + ./test.sh --release --clean --release-sysroot --build-sysroot --mini-tests --std-tests --test-libcore + # TODO(antoyo): also run the rustc's test suite. - name: Run stdarch tests run: | diff --git a/src/base.rs b/src/base.rs index ea933c25b2f3..6102016b4345 100644 --- a/src/base.rs +++ b/src/base.rs @@ -124,6 +124,8 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ context.add_command_line_option("-fno-semantic-interposition"); // NOTE: Rust relies on LLVM not doing TBAA (https://github.com/rust-lang/unsafe-code-guidelines/issues/292). context.add_command_line_option("-fno-strict-aliasing"); + // NOTE: Rust relies on LLVM doing wrapping on overflow. + context.add_command_line_option("-fwrapv"); if tcx.sess.opts.unstable_opts.function_sections.unwrap_or(tcx.sess.target.function_sections) { context.add_command_line_option("-ffunction-sections"); From 2dc7dbc01219ac2d8a7543af7fa5ff7026786569 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Thu, 26 Jan 2023 17:31:49 -0500 Subject: [PATCH 227/356] Run rustc's testsuite in release mode --- .github/workflows/release.yml | 12 ++-- .github/workflows/stdarch.yml | 116 ++++++++++++++++++++++++++++++++++ 2 files changed, 121 insertions(+), 7 deletions(-) create mode 100644 .github/workflows/stdarch.yml diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml index c60c96d2023e..c4e99469bc20 100644 --- a/.github/workflows/release.yml +++ b/.github/workflows/release.yml @@ -20,6 +20,10 @@ jobs: matrix: libgccjit_version: - { gcc: "libgccjit.so", artifacts_branch: "master" } + commands: [ + "--test-successful-rustc --nb-parts 2 --current-part 0", + "--test-successful-rustc --nb-parts 2 --current-part 1", + ] steps: - uses: actions/checkout@v3 @@ -104,10 +108,4 @@ jobs: - name: Run tests run: | - ./test.sh --release --clean --release-sysroot --build-sysroot --mini-tests --std-tests --test-libcore - # TODO(antoyo): also run the rustc's test suite. - - - name: Run stdarch tests - run: | - cd build_sysroot/sysroot_src/library/stdarch/ - CHANNEL=release TARGET=x86_64-unknown-linux-gnu ../../../../cargo.sh test + ./test.sh --release --clean --release-sysroot --build-sysroot ${{ matrix.commands }} diff --git a/.github/workflows/stdarch.yml b/.github/workflows/stdarch.yml new file mode 100644 index 000000000000..42fb35e738ff --- /dev/null +++ b/.github/workflows/stdarch.yml @@ -0,0 +1,116 @@ +name: stdarch tests with sysroot compiled in release mode + +on: + - push + - pull_request + +permissions: + contents: read + +env: + # Enable backtraces for easier debugging + RUST_BACKTRACE: 1 + +jobs: + build: + runs-on: ubuntu-latest + + strategy: + fail-fast: false + matrix: + libgccjit_version: + - { gcc: "libgccjit.so", artifacts_branch: "master" } + commands: [ + "--test-successful-rustc --nb-parts 2 --current-part 0", + "--test-successful-rustc --nb-parts 2 --current-part 1", + ] + + steps: + - uses: actions/checkout@v3 + + - uses: actions/checkout@v3 + with: + repository: llvm/llvm-project + path: llvm + + - name: Install packages + run: sudo apt-get install ninja-build ripgrep + + - name: Download artifact + uses: dawidd6/action-download-artifact@v2 + with: + workflow: main.yml + name: ${{ matrix.libgccjit_version.gcc }} + path: gcc-build + repo: antoyo/gcc + branch: ${{ matrix.libgccjit_version.artifacts_branch }} + event: push + search_artifacts: true # Because, instead, the action only check the last job ran and that won't work since we want multiple artifacts. + + - name: Setup path to libgccjit + run: | + echo $(readlink -f gcc-build) > gcc_path + # NOTE: the filename is still libgccjit.so even when the artifact name is different. + ln gcc-build/libgccjit.so gcc-build/libgccjit.so.0 + + - name: Set env + run: | + echo "LIBRARY_PATH=$(cat gcc_path)" >> $GITHUB_ENV + echo "LD_LIBRARY_PATH=$(cat gcc_path)" >> $GITHUB_ENV + echo "workspace="$GITHUB_WORKSPACE >> $GITHUB_ENV + + - name: Set RUST_COMPILER_RT_ROOT + run: echo "RUST_COMPILER_RT_ROOT="${{ env.workspace }}/llvm/compiler-rt >> $GITHUB_ENV + + - name: Cache cargo installed crates + uses: actions/cache@v3 + with: + path: ~/.cargo/bin + key: cargo-installed-crates2-ubuntu-latest + + - name: Cache cargo registry + uses: actions/cache@v3 + with: + path: ~/.cargo/registry + key: ${{ runner.os }}-cargo-registry2-${{ hashFiles('**/Cargo.lock') }} + + - name: Cache cargo index + uses: actions/cache@v3 + with: + path: ~/.cargo/git + key: ${{ runner.os }}-cargo-index-${{ hashFiles('**/Cargo.lock') }} + + - name: Cache cargo target dir + uses: actions/cache@v3 + with: + path: target + key: ${{ runner.os }}-cargo-build-target-${{ hashFiles('rust-toolchain') }} + + - name: Build + run: | + ./prepare_build.sh + ./build.sh --release --release-sysroot + cargo test + ./clean_all.sh + + - name: Prepare dependencies + run: | + git config --global user.email "user@example.com" + git config --global user.name "User" + ./prepare.sh + + # Compile is a separate step, as the actions-rs/cargo action supports error annotations + - name: Compile + uses: actions-rs/cargo@v1.0.3 + with: + command: build + args: --release + + - name: Run tests + run: | + ./test.sh --release --clean --release-sysroot --build-sysroot --mini-tests --std-tests --test-libcore + + - name: Run stdarch tests + run: | + cd build_sysroot/sysroot_src/library/stdarch/ + CHANNEL=release TARGET=x86_64-unknown-linux-gnu ../../../../cargo.sh test From 0898eab220ab0447a578ebaa3b5f08eabf480201 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 25 Feb 2023 17:24:16 -0500 Subject: [PATCH 228/356] Implement simd_gather --- Cargo.lock | 4 +- src/builder.rs | 2 +- src/intrinsic/simd.rs | 151 ++++++++++++++++++++++++++++++++++++++++++ src/type_of.rs | 8 +++ 4 files changed, 162 insertions(+), 3 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index e20980caee16..fba8c3db42e4 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -41,7 +41,7 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" -source = "git+https://github.com/antoyo/gccjit.rs#1e6ecc67fe73ac995e511516eacf4fe3aec8974e" +source = "git+https://github.com/antoyo/gccjit.rs#1bd270d0d130fe31807cfbe509ca095c082e5848" dependencies = [ "gccjit_sys", ] @@ -49,7 +49,7 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" -source = "git+https://github.com/antoyo/gccjit.rs#1e6ecc67fe73ac995e511516eacf4fe3aec8974e" +source = "git+https://github.com/antoyo/gccjit.rs#1bd270d0d130fe31807cfbe509ca095c082e5848" dependencies = [ "libc 0.1.12", ] diff --git a/src/builder.rs b/src/builder.rs index 6ac1daeca5d9..2d7860536c25 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1419,7 +1419,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { #[cfg(feature="master")] pub fn shuffle_vector(&mut self, v1: RValue<'gcc>, v2: RValue<'gcc>, mask: RValue<'gcc>) -> RValue<'gcc> { - let struct_type = mask.get_type().is_struct().expect("mask of struct type"); + let struct_type = mask.get_type().is_struct().expect("mask should be of struct type"); // TODO(antoyo): use a recursive unqualified() here. let vector_type = v1.get_type().unqualified().dyncast_vector().expect("vector type"); diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index a4f35c061f0a..c7dc6860c8a6 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -14,6 +14,7 @@ use rustc_span::{Span, Symbol, sym}; use rustc_target::abi::Align; use crate::builder::Builder; +use crate::context::CodegenCx; pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, name: Symbol, callee_ty: Ty<'tcx>, args: &[OperandRef<'tcx, RValue<'gcc>>], ret_ty: Ty<'tcx>, llret_ty: Type<'gcc>, span: Span) -> Result, ()> { // macros for error handling: @@ -507,6 +508,156 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, return simd_simple_float_intrinsic(name, in_elem, in_ty, in_len, bx, span, args); } + fn vector_ty<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, elem_ty: Ty<'tcx>, vec_len: u64) -> Type<'gcc> { + // FIXME: use cx.layout_of(ty).llvm_type() ? + let elem_ty = match *elem_ty.kind() { + ty::Int(v) => cx.type_int_from_ty(v), + ty::Uint(v) => cx.type_uint_from_ty(v), + ty::Float(v) => cx.type_float_from_ty(v), + _ => unreachable!(), + }; + cx.type_vector(elem_ty, vec_len) + } + + if name == sym::simd_gather { + // simd_gather(values: , pointers: , + // mask: ) -> + // * N: number of elements in the input vectors + // * T: type of the element to load + // * M: any integer width is supported, will be truncated to i1 + + // All types must be simd vector types + require_simd!(in_ty, "first"); + require_simd!(arg_tys[1], "second"); + require_simd!(arg_tys[2], "third"); + require_simd!(ret_ty, "return"); + + // Of the same length: + let (out_len, _) = arg_tys[1].simd_size_and_type(bx.tcx()); + let (out_len2, _) = arg_tys[2].simd_size_and_type(bx.tcx()); + require!( + in_len == out_len, + "expected {} argument with length {} (same as input type `{}`), \ + found `{}` with length {}", + "second", + in_len, + in_ty, + arg_tys[1], + out_len + ); + require!( + in_len == out_len2, + "expected {} argument with length {} (same as input type `{}`), \ + found `{}` with length {}", + "third", + in_len, + in_ty, + arg_tys[2], + out_len2 + ); + + // The return type must match the first argument type + require!(ret_ty == in_ty, "expected return type `{}`, found `{}`", in_ty, ret_ty); + + // This counts how many pointers + fn ptr_count(t: Ty<'_>) -> usize { + match t.kind() { + ty::RawPtr(p) => 1 + ptr_count(p.ty), + _ => 0, + } + } + + // Non-ptr type + fn non_ptr(t: Ty<'_>) -> Ty<'_> { + match t.kind() { + ty::RawPtr(p) => non_ptr(p.ty), + _ => t, + } + } + + // The second argument must be a simd vector with an element type that's a pointer + // to the element type of the first argument + let (_, element_ty0) = arg_tys[0].simd_size_and_type(bx.tcx()); + let (_, element_ty1) = arg_tys[1].simd_size_and_type(bx.tcx()); + let (pointer_count, underlying_ty) = match element_ty1.kind() { + ty::RawPtr(p) if p.ty == in_elem => (ptr_count(element_ty1), non_ptr(element_ty1)), + _ => { + require!( + false, + "expected element type `{}` of second argument `{}` \ + to be a pointer to the element type `{}` of the first \ + argument `{}`, found `{}` != `*_ {}`", + element_ty1, + arg_tys[1], + in_elem, + in_ty, + element_ty1, + in_elem + ); + unreachable!(); + } + }; + assert!(pointer_count > 0); + assert_eq!(pointer_count - 1, ptr_count(element_ty0)); + assert_eq!(underlying_ty, non_ptr(element_ty0)); + + // The element type of the third argument must be a signed integer type of any width: + let (_, element_ty2) = arg_tys[2].simd_size_and_type(bx.tcx()); + match element_ty2.kind() { + ty::Int(_) => (), + _ => { + require!( + false, + "expected element type `{}` of third argument `{}` \ + to be a signed integer type", + element_ty2, + arg_tys[2] + ); + } + } + + let vector_type = + if pointer_count > 1 { + bx.context.new_vector_type(bx.usize_type, in_len) + } + else { + vector_ty(bx, underlying_ty, in_len) + }; + let elem_type = vector_type.dyncast_vector().expect("vector type").get_element_type(); + + let mut values = vec![]; + let pointers = args[1].immediate(); + for i in 0..in_len { + let index = bx.context.new_rvalue_from_long(bx.i32_type, i as i64); + let int = bx.context.new_vector_access(None, pointers, index).to_rvalue(); + + let ptr_type = elem_type.make_pointer(); + + let ptr = bx.context.new_bitcast(None, int, ptr_type); + let value = ptr.dereference(None).to_rvalue(); + values.push(value); + } + + let vector = bx.context.new_rvalue_from_vector(None, vector_type, &values); + let default = args[0].immediate(); + let mask = args[2].immediate(); + + let mut mask_types = vec![]; + let mut mask_values = vec![]; + for i in 0..in_len { + let index = bx.context.new_rvalue_from_long(bx.i32_type, i as i64); + mask_types.push(bx.context.new_field(None, bx.i32_type, "m")); // TODO: choose an integer based on the size of the vector element type. + let mask_value = bx.context.new_vector_access(None, mask, index).to_rvalue(); + let masked = bx.context.new_rvalue_from_int(bx.i32_type, in_len as i32) & mask_value; + let value = index + masked; + mask_values.push(value); + } + let mask_type = bx.context.new_struct_type(None, "mask_type", &mask_types); + let mask = bx.context.new_struct_constructor(None, mask_type.as_type(), None, &mask_values); + + return Ok(bx.shuffle_vector(default, vector, mask)); + } + arith_binary! { simd_add: Uint, Int => add, Float => fadd; simd_sub: Uint, Int => sub, Float => fsub; diff --git a/src/type_of.rs b/src/type_of.rs index 29d394dbba4a..09c79b69ce3c 100644 --- a/src/type_of.rs +++ b/src/type_of.rs @@ -55,6 +55,14 @@ fn uncached_gcc_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, layout: TyAndLayout Abi::Scalar(_) => bug!("handled elsewhere"), Abi::Vector { ref element, count } => { let element = layout.scalar_gcc_type_at(cx, element, Size::ZERO); + let element = + // NOTE: gcc doesn't allow pointer types in vectors. + if element.get_pointee().is_some() { + cx.usize_type + } + else { + element + }; return cx.context.new_vector_type(element, count); }, Abi::ScalarPair(..) => { From df72765646b7d90a8f3e37090d3cb24597896750 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 25 Feb 2023 19:37:51 -0500 Subject: [PATCH 229/356] Implement simd_scatter --- src/intrinsic/simd.rs | 176 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 151 insertions(+), 25 deletions(-) diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index c7dc6860c8a6..5ab1f9e4300e 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -519,6 +519,50 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, cx.type_vector(elem_ty, vec_len) } + fn gather<'a, 'gcc, 'tcx>(default: RValue<'gcc>, pointers: RValue<'gcc>, mask: RValue<'gcc>, pointer_count: usize, bx: &mut Builder<'a, 'gcc, 'tcx>, in_len: u64, underlying_ty: Ty<'tcx>, invert: bool) -> RValue<'gcc> { + let vector_type = + if pointer_count > 1 { + bx.context.new_vector_type(bx.usize_type, in_len) + } + else { + vector_ty(bx, underlying_ty, in_len) + }; + let elem_type = vector_type.dyncast_vector().expect("vector type").get_element_type(); + + let mut values = vec![]; + for i in 0..in_len { + let index = bx.context.new_rvalue_from_long(bx.i32_type, i as i64); + let int = bx.context.new_vector_access(None, pointers, index).to_rvalue(); + + let ptr_type = elem_type.make_pointer(); + let ptr = bx.context.new_bitcast(None, int, ptr_type); + let value = ptr.dereference(None).to_rvalue(); + values.push(value); + } + + let vector = bx.context.new_rvalue_from_vector(None, vector_type, &values); + + let mut mask_types = vec![]; + let mut mask_values = vec![]; + for i in 0..in_len { + let index = bx.context.new_rvalue_from_long(bx.i32_type, i as i64); + mask_types.push(bx.context.new_field(None, bx.i32_type, "m")); // TODO: choose an integer based on the size of the vector element type. + let mask_value = bx.context.new_vector_access(None, mask, index).to_rvalue(); + let masked = bx.context.new_rvalue_from_int(bx.i32_type, in_len as i32) & mask_value; + let value = index + masked; + mask_values.push(value); + } + let mask_type = bx.context.new_struct_type(None, "mask_type", &mask_types); + let mask = bx.context.new_struct_constructor(None, mask_type.as_type(), None, &mask_values); + + if invert { + bx.shuffle_vector(vector, default, mask) + } + else { + bx.shuffle_vector(default, vector, mask) + } + } + if name == sym::simd_gather { // simd_gather(values: , pointers: , // mask: ) -> @@ -616,6 +660,108 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, } } + return Ok(gather(args[0].immediate(), args[1].immediate(), args[2].immediate(), pointer_count, bx, in_len, underlying_ty, false)); + } + + if name == sym::simd_scatter { + // simd_scatter(values: , pointers: , + // mask: ) -> () + // * N: number of elements in the input vectors + // * T: type of the element to load + // * M: any integer width is supported, will be truncated to i1 + + // All types must be simd vector types + require_simd!(in_ty, "first"); + require_simd!(arg_tys[1], "second"); + require_simd!(arg_tys[2], "third"); + + // Of the same length: + let (element_len1, _) = arg_tys[1].simd_size_and_type(bx.tcx()); + let (element_len2, _) = arg_tys[2].simd_size_and_type(bx.tcx()); + require!( + in_len == element_len1, + "expected {} argument with length {} (same as input type `{}`), \ + found `{}` with length {}", + "second", + in_len, + in_ty, + arg_tys[1], + element_len1 + ); + require!( + in_len == element_len2, + "expected {} argument with length {} (same as input type `{}`), \ + found `{}` with length {}", + "third", + in_len, + in_ty, + arg_tys[2], + element_len2 + ); + + // This counts how many pointers + fn ptr_count(t: Ty<'_>) -> usize { + match t.kind() { + ty::RawPtr(p) => 1 + ptr_count(p.ty), + _ => 0, + } + } + + // Non-ptr type + fn non_ptr(t: Ty<'_>) -> Ty<'_> { + match t.kind() { + ty::RawPtr(p) => non_ptr(p.ty), + _ => t, + } + } + + // The second argument must be a simd vector with an element type that's a pointer + // to the element type of the first argument + let (_, element_ty0) = arg_tys[0].simd_size_and_type(bx.tcx()); + let (_, element_ty1) = arg_tys[1].simd_size_and_type(bx.tcx()); + let (_, element_ty2) = arg_tys[2].simd_size_and_type(bx.tcx()); + let (pointer_count, underlying_ty) = match element_ty1.kind() { + ty::RawPtr(p) if p.ty == in_elem && p.mutbl == hir::Mutability::Mut => { + (ptr_count(element_ty1), non_ptr(element_ty1)) + } + _ => { + require!( + false, + "expected element type `{}` of second argument `{}` \ + to be a pointer to the element type `{}` of the first \ + argument `{}`, found `{}` != `*mut {}`", + element_ty1, + arg_tys[1], + in_elem, + in_ty, + element_ty1, + in_elem + ); + unreachable!(); + } + }; + assert!(pointer_count > 0); + assert_eq!(pointer_count - 1, ptr_count(element_ty0)); + assert_eq!(underlying_ty, non_ptr(element_ty0)); + + // The element type of the third argument must be a signed integer type of any width: + match element_ty2.kind() { + ty::Int(_) => (), + _ => { + require!( + false, + "expected element type `{}` of third argument `{}` \ + be a signed integer type", + element_ty2, + arg_tys[2] + ); + } + } + + let result = gather(args[0].immediate(), args[1].immediate(), args[2].immediate(), pointer_count, bx, in_len, underlying_ty, true); + + let pointers = args[1].immediate(); + let vector_type = if pointer_count > 1 { bx.context.new_vector_type(bx.usize_type, in_len) @@ -625,37 +771,17 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, }; let elem_type = vector_type.dyncast_vector().expect("vector type").get_element_type(); - let mut values = vec![]; - let pointers = args[1].immediate(); for i in 0..in_len { - let index = bx.context.new_rvalue_from_long(bx.i32_type, i as i64); + let index = bx.context.new_rvalue_from_int(bx.int_type, i as i32); + let value = bx.context.new_vector_access(None, result, index); + let int = bx.context.new_vector_access(None, pointers, index).to_rvalue(); - let ptr_type = elem_type.make_pointer(); - let ptr = bx.context.new_bitcast(None, int, ptr_type); - let value = ptr.dereference(None).to_rvalue(); - values.push(value); + bx.llbb().add_assignment(None, ptr.dereference(None), value); } - let vector = bx.context.new_rvalue_from_vector(None, vector_type, &values); - let default = args[0].immediate(); - let mask = args[2].immediate(); - - let mut mask_types = vec![]; - let mut mask_values = vec![]; - for i in 0..in_len { - let index = bx.context.new_rvalue_from_long(bx.i32_type, i as i64); - mask_types.push(bx.context.new_field(None, bx.i32_type, "m")); // TODO: choose an integer based on the size of the vector element type. - let mask_value = bx.context.new_vector_access(None, mask, index).to_rvalue(); - let masked = bx.context.new_rvalue_from_int(bx.i32_type, in_len as i32) & mask_value; - let value = index + masked; - mask_values.push(value); - } - let mask_type = bx.context.new_struct_type(None, "mask_type", &mask_types); - let mask = bx.context.new_struct_constructor(None, mask_type.as_type(), None, &mask_values); - - return Ok(bx.shuffle_vector(default, vector, mask)); + return Ok(bx.context.new_rvalue_zero(bx.i32_type)); } arith_binary! { From 830a821b9b8fadd4ee1c779f1776ab38e18f09a2 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 25 Feb 2023 19:54:34 -0500 Subject: [PATCH 230/356] Update failures --- failing-ui-tests.txt | 3 --- 1 file changed, 3 deletions(-) diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index a51a7f1428e3..f43116544ed2 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -22,8 +22,6 @@ src/test/ui/sepcomp/sepcomp-fns-backwards.rs src/test/ui/sepcomp/sepcomp-fns.rs src/test/ui/sepcomp/sepcomp-statics.rs src/test/ui/simd/intrinsic/generic-arithmetic-pass.rs -src/test/ui/simd/intrinsic/generic-gather-pass.rs -src/test/ui/simd/type-generic-monomorphisation-extern-nonnull-ptr.rs src/test/ui/sse2.rs src/test/ui/target-feature/missing-plusminus.rs src/test/ui/asm/x86_64/may_unwind.rs @@ -54,7 +52,6 @@ src/test/ui/issues/issue-43853.rs src/test/ui/issues/issue-47364.rs src/test/ui/simd/issue-17170.rs src/test/ui/simd/issue-39720.rs -src/test/ui/simd/issue-85915-simd-ptrs.rs src/test/ui/simd/issue-89193.rs src/test/ui/statics/issue-91050-1.rs src/test/ui/statics/issue-91050-2.rs From 3e61492dc5196ea5806cacd56a87db3484e2495b Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 25 Feb 2023 20:37:20 -0500 Subject: [PATCH 231/356] Add feature gate --- src/intrinsic/simd.rs | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index 5ab1f9e4300e..0635ad2e0c7b 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -14,6 +14,7 @@ use rustc_span::{Span, Symbol, sym}; use rustc_target::abi::Align; use crate::builder::Builder; +#[cfg(feature="master")] use crate::context::CodegenCx; pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, name: Symbol, callee_ty: Ty<'tcx>, args: &[OperandRef<'tcx, RValue<'gcc>>], ret_ty: Ty<'tcx>, llret_ty: Type<'gcc>, span: Span) -> Result, ()> { @@ -508,6 +509,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, return simd_simple_float_intrinsic(name, in_elem, in_ty, in_len, bx, span, args); } + #[cfg(feature="master")] fn vector_ty<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, elem_ty: Ty<'tcx>, vec_len: u64) -> Type<'gcc> { // FIXME: use cx.layout_of(ty).llvm_type() ? let elem_ty = match *elem_ty.kind() { @@ -519,6 +521,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, cx.type_vector(elem_ty, vec_len) } + #[cfg(feature="master")] fn gather<'a, 'gcc, 'tcx>(default: RValue<'gcc>, pointers: RValue<'gcc>, mask: RValue<'gcc>, pointer_count: usize, bx: &mut Builder<'a, 'gcc, 'tcx>, in_len: u64, underlying_ty: Ty<'tcx>, invert: bool) -> RValue<'gcc> { let vector_type = if pointer_count > 1 { @@ -563,6 +566,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, } } + #[cfg(feature="master")] if name == sym::simd_gather { // simd_gather(values: , pointers: , // mask: ) -> @@ -663,6 +667,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, return Ok(gather(args[0].immediate(), args[1].immediate(), args[2].immediate(), pointer_count, bx, in_len, underlying_ty, false)); } + #[cfg(feature="master")] if name == sym::simd_scatter { // simd_scatter(values: , pointers: , // mask: ) -> () From edee0973b24382d641c5b1c5ab43ee16e8d4ec36 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 25 Feb 2023 21:03:58 -0500 Subject: [PATCH 232/356] Update failures for libgccjit12 --- failing-ui-tests12.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/failing-ui-tests12.txt b/failing-ui-tests12.txt index 22441efeee9f..2a9f39e88ccb 100644 --- a/failing-ui-tests12.txt +++ b/failing-ui-tests12.txt @@ -37,3 +37,5 @@ src/test/ui/cfg/cfg-panic.rs src/test/ui/generator/size-moved-locals.rs src/test/ui/macros/rfc-2011-nicer-assert-messages/all-not-available-cases.rs src/test/ui/runtime/rt-explody-panic-payloads.rs +src/test/ui/simd/intrinsic/generic-gather-pass.rs +src/test/ui/simd/issue-85915-simd-ptrs.rs From 16b377efbd612c276a6800dbcecbb0fe9ad9a204 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 25 Feb 2023 21:48:44 -0500 Subject: [PATCH 233/356] Remove comment --- src/intrinsic/simd.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index 0635ad2e0c7b..233d0b7f739d 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -549,7 +549,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let mut mask_values = vec![]; for i in 0..in_len { let index = bx.context.new_rvalue_from_long(bx.i32_type, i as i64); - mask_types.push(bx.context.new_field(None, bx.i32_type, "m")); // TODO: choose an integer based on the size of the vector element type. + mask_types.push(bx.context.new_field(None, bx.i32_type, "m")); let mask_value = bx.context.new_vector_access(None, mask, index).to_rvalue(); let masked = bx.context.new_rvalue_from_int(bx.i32_type, in_len as i32) & mask_value; let value = index + masked; From 1fcf4373062d4648bfe0fb66ecff619544f36ae8 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Tue, 28 Feb 2023 17:39:01 -0500 Subject: [PATCH 234/356] Add instructions for a working git-subtree --- Readme.md | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Readme.md b/Readme.md index b473f79a526b..44b3c14fb9a7 100644 --- a/Readme.md +++ b/Readme.md @@ -187,6 +187,17 @@ TODO(antoyo): but that's not what I remember I was doing. * Build the stage2 compiler (`rustup toolchain link debug-current build/x86_64-unknown-linux-gnu/stage2`). * Clean and rebuild the codegen with `debug-current` in the file `rust-toolchain`. +### How to install a forked git-subtree + +Using git-subtree with `rustc` requires a patched git to make it work. +The PR that is needed is [here](https://github.com/gitgitgadget/git/pull/493). +Compile it and copy those files to `/usr/local/bin`: + +``` +git-commit-tree git-ls-tree git-merge-tree git-read-tree git-write-tree +git-diff-tree git-merge-subtree git-mktree git-worktree +``` + ### How to use [mem-trace](https://github.com/antoyo/mem-trace) `rustc` needs to be built without `jemalloc` so that `mem-trace` can overload `malloc` since `jemalloc` is linked statically, so a `LD_PRELOAD`-ed library won't a chance to intercept the calls to `malloc`. From 32a2e378f4cc509718cba147b0d6588528cdd6e5 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Tue, 28 Feb 2023 18:25:09 -0500 Subject: [PATCH 235/356] Fix instructions for installing git-subtree --- Readme.md | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/Readme.md b/Readme.md index 44b3c14fb9a7..bb7419438925 100644 --- a/Readme.md +++ b/Readme.md @@ -191,11 +191,17 @@ TODO(antoyo): but that's not what I remember I was doing. Using git-subtree with `rustc` requires a patched git to make it work. The PR that is needed is [here](https://github.com/gitgitgadget/git/pull/493). -Compile it and copy those files to `/usr/local/bin`: +Use the following instructions to install it: ``` -git-commit-tree git-ls-tree git-merge-tree git-read-tree git-write-tree -git-diff-tree git-merge-subtree git-mktree git-worktree +git clone git@github.com:tqc/git.git +cd git +git checkout tqc/subtree +make +make install +cd contrib/subtree +make +cp git-subtree ~/bin ``` ### How to use [mem-trace](https://github.com/antoyo/mem-trace) From d01d0d1f76a9ff51681d079916073ad33ba190d4 Mon Sep 17 00:00:00 2001 From: Nicholas Nethercote Date: Thu, 25 Aug 2022 17:52:37 +1000 Subject: [PATCH 236/356] Box `CastTarget` within `PassMode`. Because `PassMode::Cast` is by far the largest variant, but is relatively rare. This requires making `PassMode` not impl `Copy`, and `Clone` is no longer necessary. This causes lots of sigil adjusting, but nothing very notable. --- src/abi.rs | 4 ++-- src/intrinsic/mod.rs | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/abi.rs b/src/abi.rs index 0ed3e1fbe93f..9b55db6a5476 100644 --- a/src/abi.rs +++ b/src/abi.rs @@ -133,7 +133,7 @@ impl<'gcc, 'tcx> FnAbiGccExt<'gcc, 'tcx> for FnAbi<'tcx, Ty<'tcx>> { match self.ret.mode { PassMode::Ignore => cx.type_void(), PassMode::Direct(_) | PassMode::Pair(..) => self.ret.layout.immediate_gcc_type(cx), - PassMode::Cast(cast) => cast.gcc_type(cx), + PassMode::Cast(ref cast) => cast.gcc_type(cx), PassMode::Indirect { .. } => { argument_tys.push(cx.type_ptr_to(self.ret.memory_ty(cx))); cx.type_void() @@ -157,7 +157,7 @@ impl<'gcc, 'tcx> FnAbiGccExt<'gcc, 'tcx> for FnAbi<'tcx, Ty<'tcx>> { PassMode::Indirect { extra_attrs: Some(_), .. } => { unimplemented!(); } - PassMode::Cast(cast) => cast.gcc_type(cx), + PassMode::Cast(ref cast) => cast.gcc_type(cx), PassMode::Indirect { extra_attrs: None, on_stack: true, .. } => { on_stack_param_indices.insert(argument_tys.len()); arg.memory_ty(cx) diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index 6ca171801159..90c49c627019 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -141,7 +141,7 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { sym::volatile_load | sym::unaligned_volatile_load => { let tp_ty = substs.type_at(0); let mut ptr = args[0].immediate(); - if let PassMode::Cast(ty) = fn_abi.ret.mode { + if let PassMode::Cast(ty) = &fn_abi.ret.mode { ptr = self.pointercast(ptr, self.type_ptr_to(ty.gcc_type(self))); } let load = self.volatile_load(ptr.get_type(), ptr); @@ -331,7 +331,7 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { }; if !fn_abi.ret.is_ignore() { - if let PassMode::Cast(ty) = fn_abi.ret.mode { + if let PassMode::Cast(ty) = &fn_abi.ret.mode { let ptr_llty = self.type_ptr_to(ty.gcc_type(self)); let ptr = self.pointercast(result.llval, ptr_llty); self.store(llval, ptr, result.align); @@ -427,7 +427,7 @@ impl<'gcc, 'tcx> ArgAbiExt<'gcc, 'tcx> for ArgAbi<'tcx, Ty<'tcx>> { else if self.is_unsized_indirect() { bug!("unsized `ArgAbi` must be handled through `store_fn_arg`"); } - else if let PassMode::Cast(cast) = self.mode { + else if let PassMode::Cast(ref cast) = self.mode { // FIXME(eddyb): Figure out when the simpler Store is safe, clang // uses it for i16 -> {i8, i8}, but not for i24 -> {i8, i8, i8}. let can_store_through_cast_ptr = false; From a283dedd44f5e426f01d24a447fbf4cb7d5dc41a Mon Sep 17 00:00:00 2001 From: Nicholas Nethercote Date: Thu, 25 Aug 2022 19:08:04 +1000 Subject: [PATCH 237/356] Change `FnAbi::args` to a boxed slice. --- src/abi.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/abi.rs b/src/abi.rs index 9b55db6a5476..7f313583c82c 100644 --- a/src/abi.rs +++ b/src/abi.rs @@ -140,7 +140,7 @@ impl<'gcc, 'tcx> FnAbiGccExt<'gcc, 'tcx> for FnAbi<'tcx, Ty<'tcx>> { } }; - for arg in &self.args { + for arg in self.args.iter() { // add padding if let Some(ty) = arg.pad { argument_tys.push(ty.gcc_type(cx)); From 3c2d43265c1691647a9e2adc57c7239a4366a624 Mon Sep 17 00:00:00 2001 From: Nicholas Nethercote Date: Fri, 26 Aug 2022 10:37:51 +1000 Subject: [PATCH 238/356] Simplify arg capacity calculations. Currently they try to be very precise. But they are wrong, i.e. they don't match what's happening in the loop below. This code isn't hot enough for it to matter that much. --- src/abi.rs | 22 +++------------------- 1 file changed, 3 insertions(+), 19 deletions(-) diff --git a/src/abi.rs b/src/abi.rs index 7f313583c82c..87b730d29cdf 100644 --- a/src/abi.rs +++ b/src/abi.rs @@ -107,26 +107,10 @@ pub trait FnAbiGccExt<'gcc, 'tcx> { impl<'gcc, 'tcx> FnAbiGccExt<'gcc, 'tcx> for FnAbi<'tcx, Ty<'tcx>> { fn gcc_type(&self, cx: &CodegenCx<'gcc, 'tcx>) -> (Type<'gcc>, Vec>, bool, FxHashSet) { let mut on_stack_param_indices = FxHashSet::default(); - let args_capacity: usize = self.args.iter().map(|arg| - if arg.pad.is_some() { - 1 - } - else { - 0 - } + - if let PassMode::Pair(_, _) = arg.mode { - 2 - } else { - 1 - } - ).sum(); + + // This capacity calculation is approximate. let mut argument_tys = Vec::with_capacity( - if let PassMode::Indirect { .. } = self.ret.mode { - 1 - } - else { - 0 - } + args_capacity, + self.args.len() + if let PassMode::Indirect { .. } = self.ret.mode { 1 } else { 0 } ); let return_ty = From 8ebade29d6f45e51b8f72d410a04edd2a25d5bf8 Mon Sep 17 00:00:00 2001 From: Nicholas Nethercote Date: Thu, 25 Aug 2022 19:18:01 +1000 Subject: [PATCH 239/356] Turn `ArgAbi::pad` into a `bool`. Because it's only ever set to `None` or `Some(Reg::i32())`. --- src/abi.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/abi.rs b/src/abi.rs index 87b730d29cdf..3186b363e359 100644 --- a/src/abi.rs +++ b/src/abi.rs @@ -126,8 +126,8 @@ impl<'gcc, 'tcx> FnAbiGccExt<'gcc, 'tcx> for FnAbi<'tcx, Ty<'tcx>> { for arg in self.args.iter() { // add padding - if let Some(ty) = arg.pad { - argument_tys.push(ty.gcc_type(cx)); + if arg.pad_i32 { + argument_tys.push(Reg::i32().gcc_type(cx)); } let arg_ty = match arg.mode { From b3f294215637c763b8a689705a01b6fd4428e371 Mon Sep 17 00:00:00 2001 From: Nicholas Nethercote Date: Thu, 25 Aug 2022 22:19:38 +1000 Subject: [PATCH 240/356] Move `ArgAbi::pad_i32` into `PassMode::Cast`. Because it's only needed for that variant. This shrinks the types and clarifies the logic. --- src/abi.rs | 15 ++++++++------- src/intrinsic/mod.rs | 8 ++++---- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/src/abi.rs b/src/abi.rs index 3186b363e359..848c34211ff6 100644 --- a/src/abi.rs +++ b/src/abi.rs @@ -117,7 +117,7 @@ impl<'gcc, 'tcx> FnAbiGccExt<'gcc, 'tcx> for FnAbi<'tcx, Ty<'tcx>> { match self.ret.mode { PassMode::Ignore => cx.type_void(), PassMode::Direct(_) | PassMode::Pair(..) => self.ret.layout.immediate_gcc_type(cx), - PassMode::Cast(ref cast) => cast.gcc_type(cx), + PassMode::Cast(ref cast, _) => cast.gcc_type(cx), PassMode::Indirect { .. } => { argument_tys.push(cx.type_ptr_to(self.ret.memory_ty(cx))); cx.type_void() @@ -125,11 +125,6 @@ impl<'gcc, 'tcx> FnAbiGccExt<'gcc, 'tcx> for FnAbi<'tcx, Ty<'tcx>> { }; for arg in self.args.iter() { - // add padding - if arg.pad_i32 { - argument_tys.push(Reg::i32().gcc_type(cx)); - } - let arg_ty = match arg.mode { PassMode::Ignore => continue, PassMode::Direct(_) => arg.layout.immediate_gcc_type(cx), @@ -141,7 +136,13 @@ impl<'gcc, 'tcx> FnAbiGccExt<'gcc, 'tcx> for FnAbi<'tcx, Ty<'tcx>> { PassMode::Indirect { extra_attrs: Some(_), .. } => { unimplemented!(); } - PassMode::Cast(ref cast) => cast.gcc_type(cx), + PassMode::Cast(ref cast, pad_i32) => { + // add padding + if pad_i32 { + argument_tys.push(Reg::i32().gcc_type(cx)); + } + cast.gcc_type(cx) + } PassMode::Indirect { extra_attrs: None, on_stack: true, .. } => { on_stack_param_indices.insert(argument_tys.len()); arg.memory_ty(cx) diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index 90c49c627019..41361e17cb5f 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -141,7 +141,7 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { sym::volatile_load | sym::unaligned_volatile_load => { let tp_ty = substs.type_at(0); let mut ptr = args[0].immediate(); - if let PassMode::Cast(ty) = &fn_abi.ret.mode { + if let PassMode::Cast(ty, _) = &fn_abi.ret.mode { ptr = self.pointercast(ptr, self.type_ptr_to(ty.gcc_type(self))); } let load = self.volatile_load(ptr.get_type(), ptr); @@ -331,7 +331,7 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { }; if !fn_abi.ret.is_ignore() { - if let PassMode::Cast(ty) = &fn_abi.ret.mode { + if let PassMode::Cast(ty, _) = &fn_abi.ret.mode { let ptr_llty = self.type_ptr_to(ty.gcc_type(self)); let ptr = self.pointercast(result.llval, ptr_llty); self.store(llval, ptr, result.align); @@ -427,7 +427,7 @@ impl<'gcc, 'tcx> ArgAbiExt<'gcc, 'tcx> for ArgAbi<'tcx, Ty<'tcx>> { else if self.is_unsized_indirect() { bug!("unsized `ArgAbi` must be handled through `store_fn_arg`"); } - else if let PassMode::Cast(ref cast) = self.mode { + else if let PassMode::Cast(ref cast, _) = self.mode { // FIXME(eddyb): Figure out when the simpler Store is safe, clang // uses it for i16 -> {i8, i8}, but not for i24 -> {i8, i8, i8}. let can_store_through_cast_ptr = false; @@ -492,7 +492,7 @@ impl<'gcc, 'tcx> ArgAbiExt<'gcc, 'tcx> for ArgAbi<'tcx, Ty<'tcx>> { PassMode::Indirect { extra_attrs: Some(_), .. } => { OperandValue::Ref(next(), Some(next()), self.layout.align.abi).store(bx, dst); }, - PassMode::Direct(_) | PassMode::Indirect { extra_attrs: None, .. } | PassMode::Cast(_) => { + PassMode::Direct(_) | PassMode::Indirect { extra_attrs: None, .. } | PassMode::Cast(..) => { let next_arg = next(); self.store(bx, next_arg, dst); }, From a7f6e7ebaf697f03d22374303aaaa09d9ed70237 Mon Sep 17 00:00:00 2001 From: Maybe Waffle Date: Wed, 11 May 2022 22:01:53 +0400 Subject: [PATCH 241/356] Implement `ptr_mask` intrinsic in cg gcc --- src/intrinsic/mod.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index 41361e17cb5f..ff7332478f3c 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -320,6 +320,8 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { return; } + sym::ptr_mask => self.and(args[0].immediate(), args[1].immediate()), + _ if name_str.starts_with("simd_") => { match generic_simd_intrinsic(self, name, callee_ty, args, ret_ty, llret_ty, span) { Ok(llval) => llval, From 5eedd541a962a36e86d3302856211248317f635c Mon Sep 17 00:00:00 2001 From: Maybe Waffle Date: Fri, 13 May 2022 17:08:44 +0400 Subject: [PATCH 242/356] Fix `ptr_mask` impl in cg gcc --- src/intrinsic/mod.rs | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index ff7332478f3c..205f795ec58c 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -320,8 +320,18 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { return; } - sym::ptr_mask => self.and(args[0].immediate(), args[1].immediate()), + sym::ptr_mask => { + let usize_type = self.context.new_type::(); + let void_ptr_type = self.context.new_type::<*const ()>(); + let ptr = args[0].immediate(); + let mask = args[1].immediate(); + + let addr = self.bitcast(ptr, usize_type); + let masked = self.and(addr, mask); + self.bitcast(masked, void_ptr_type) + }, + _ if name_str.starts_with("simd_") => { match generic_simd_intrinsic(self, name, callee_ty, args, ret_ty, llret_ty, span) { Ok(llval) => llval, From 80b1c8dab5eb64826692051c963ff9c57baced76 Mon Sep 17 00:00:00 2001 From: Ralf Jung Date: Sat, 27 Aug 2022 14:11:19 -0400 Subject: [PATCH 243/356] =?UTF-8?q?interpret:=20rename=20relocation=20?= =?UTF-8?q?=E2=86=92=20provenance?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/consts.rs | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/consts.rs b/src/consts.rs index d70c9076897b..b91fbfd6d94f 100644 --- a/src/consts.rs +++ b/src/consts.rs @@ -127,7 +127,7 @@ impl<'gcc, 'tcx> StaticMethods for CodegenCx<'gcc, 'tcx> { // // We could remove this hack whenever we decide to drop macOS 10.10 support. if self.tcx.sess.target.options.is_like_osx { - // The `inspect` method is okay here because we checked relocations, and + // The `inspect` method is okay here because we checked for provenance, and // because we are doing this access to inspect the final interpreter state // (not as part of the interpreter execution). // @@ -278,17 +278,17 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { pub fn const_alloc_to_gcc<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, alloc: ConstAllocation<'tcx>) -> RValue<'gcc> { let alloc = alloc.inner(); - let mut llvals = Vec::with_capacity(alloc.relocations().len() + 1); + let mut llvals = Vec::with_capacity(alloc.provenance().len() + 1); let dl = cx.data_layout(); let pointer_size = dl.pointer_size.bytes() as usize; let mut next_offset = 0; - for &(offset, alloc_id) in alloc.relocations().iter() { + for &(offset, alloc_id) in alloc.provenance().iter() { let offset = offset.bytes(); assert_eq!(offset as usize as u64, offset); let offset = offset as usize; if offset > next_offset { - // This `inspect` is okay since we have checked that it is not within a relocation, it + // This `inspect` is okay since we have checked that it is not within a pointer with provenance, it // is within the bounds of the allocation, and it doesn't affect interpreter execution // (we inspect the result after interpreter execution). Any undef byte is replaced with // some arbitrary byte value. @@ -301,7 +301,7 @@ pub fn const_alloc_to_gcc<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, alloc: ConstAl read_target_uint( dl.endian, // This `inspect` is okay since it is within the bounds of the allocation, it doesn't // affect interpreter execution (we inspect the result after interpreter execution), - // and we properly interpret the relocation as a relocation pointer offset. + // and we properly interpret the provenance as a relocation pointer offset. alloc.inspect_with_uninit_and_ptr_outside_interpreter(offset..(offset + pointer_size)), ) .expect("const_alloc_to_llvm: could not read relocation pointer") @@ -318,7 +318,7 @@ pub fn const_alloc_to_gcc<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, alloc: ConstAl } if alloc.len() >= next_offset { let range = next_offset..alloc.len(); - // This `inspect` is okay since we have check that it is after all relocations, it is + // This `inspect` is okay since we have check that it is after all provenance, it is // within the bounds of the allocation, and it doesn't affect interpreter execution (we // inspect the result after interpreter execution). Any undef byte is replaced with some // arbitrary byte value. From 91cf28428e7db791e248ef44e7dc55cd20429158 Mon Sep 17 00:00:00 2001 From: Josh Stone Date: Tue, 16 Aug 2022 15:46:17 -0700 Subject: [PATCH 244/356] Move the cast_float_to_int fallback code to GCC Now that we require at least LLVM 13, that codegen backend is always using its intrinsic `fptosi.sat` and `fptoui.sat` conversions, so it doesn't need the manual implementation. However, the GCC backend still needs it, so we can move all of that code down there. --- src/builder.rs | 174 +++++++++++++++++++++++++++++++++++++++++++++++-- src/lib.rs | 1 + 2 files changed, 170 insertions(+), 5 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index 2d7860536c25..a560539d6e1e 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -15,8 +15,11 @@ use gccjit::{ Type, UnaryOp, }; +use rustc_apfloat::{ieee, Float, Round, Status}; use rustc_codegen_ssa::MemFlags; -use rustc_codegen_ssa::common::{AtomicOrdering, AtomicRmwBinOp, IntPredicate, RealPredicate, SynchronizationScope}; +use rustc_codegen_ssa::common::{ + AtomicOrdering, AtomicRmwBinOp, IntPredicate, RealPredicate, SynchronizationScope, TypeKind, +}; use rustc_codegen_ssa::mir::operand::{OperandRef, OperandValue}; use rustc_codegen_ssa::mir::place::PlaceRef; use rustc_codegen_ssa::traits::{ @@ -31,6 +34,7 @@ use rustc_codegen_ssa::traits::{ StaticBuilderMethods, }; use rustc_data_structures::fx::FxHashSet; +use rustc_middle::bug; use rustc_middle::ty::{ParamEnv, Ty, TyCtxt}; use rustc_middle::ty::layout::{FnAbiError, FnAbiOfHelpers, FnAbiRequest, HasParamEnv, HasTyCtxt, LayoutError, LayoutOfHelpers, TyAndLayout}; use rustc_span::Span; @@ -1403,12 +1407,12 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { val } - fn fptoui_sat(&mut self, _val: RValue<'gcc>, _dest_ty: Type<'gcc>) -> Option> { - None + fn fptoui_sat(&mut self, val: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { + self.fptoint_sat(false, val, dest_ty) } - fn fptosi_sat(&mut self, _val: RValue<'gcc>, _dest_ty: Type<'gcc>) -> Option> { - None + fn fptosi_sat(&mut self, val: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { + self.fptoint_sat(true, val, dest_ty) } fn instrprof_increment(&mut self, _fn_name: RValue<'gcc>, _hash: RValue<'gcc>, _num_counters: RValue<'gcc>, _index: RValue<'gcc>) { @@ -1417,6 +1421,166 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { + fn fptoint_sat(&mut self, signed: bool, val: RValue<'gcc>, dest_ty: Type<'gcc>) -> RValue<'gcc> { + let src_ty = self.cx.val_ty(val); + let (float_ty, int_ty) = if self.cx.type_kind(src_ty) == TypeKind::Vector { + assert_eq!(self.cx.vector_length(src_ty), self.cx.vector_length(dest_ty)); + (self.cx.element_type(src_ty), self.cx.element_type(dest_ty)) + } else { + (src_ty, dest_ty) + }; + + // FIXME(jistone): the following was originally the fallback SSA implementation, before LLVM 13 + // added native `fptosi.sat` and `fptoui.sat` conversions, but it was used by GCC as well. + // Now that LLVM always relies on its own, the code has been moved to GCC, but the comments are + // still LLVM-specific. This should be updated, and use better GCC specifics if possible. + + let int_width = self.cx.int_width(int_ty); + let float_width = self.cx.float_width(float_ty); + // LLVM's fpto[su]i returns undef when the input val is infinite, NaN, or does not fit into the + // destination integer type after rounding towards zero. This `undef` value can cause UB in + // safe code (see issue #10184), so we implement a saturating conversion on top of it: + // Semantically, the mathematical value of the input is rounded towards zero to the next + // mathematical integer, and then the result is clamped into the range of the destination + // integer type. Positive and negative infinity are mapped to the maximum and minimum value of + // the destination integer type. NaN is mapped to 0. + // + // Define f_min and f_max as the largest and smallest (finite) floats that are exactly equal to + // a value representable in int_ty. + // They are exactly equal to int_ty::{MIN,MAX} if float_ty has enough significand bits. + // Otherwise, int_ty::MAX must be rounded towards zero, as it is one less than a power of two. + // int_ty::MIN, however, is either zero or a negative power of two and is thus exactly + // representable. Note that this only works if float_ty's exponent range is sufficiently large. + // f16 or 256 bit integers would break this property. Right now the smallest float type is f32 + // with exponents ranging up to 127, which is barely enough for i128::MIN = -2^127. + // On the other hand, f_max works even if int_ty::MAX is greater than float_ty::MAX. Because + // we're rounding towards zero, we just get float_ty::MAX (which is always an integer). + // This already happens today with u128::MAX = 2^128 - 1 > f32::MAX. + let int_max = |signed: bool, int_width: u64| -> u128 { + let shift_amount = 128 - int_width; + if signed { i128::MAX as u128 >> shift_amount } else { u128::MAX >> shift_amount } + }; + let int_min = |signed: bool, int_width: u64| -> i128 { + if signed { i128::MIN >> (128 - int_width) } else { 0 } + }; + + let compute_clamp_bounds_single = |signed: bool, int_width: u64| -> (u128, u128) { + let rounded_min = + ieee::Single::from_i128_r(int_min(signed, int_width), Round::TowardZero); + assert_eq!(rounded_min.status, Status::OK); + let rounded_max = + ieee::Single::from_u128_r(int_max(signed, int_width), Round::TowardZero); + assert!(rounded_max.value.is_finite()); + (rounded_min.value.to_bits(), rounded_max.value.to_bits()) + }; + let compute_clamp_bounds_double = |signed: bool, int_width: u64| -> (u128, u128) { + let rounded_min = + ieee::Double::from_i128_r(int_min(signed, int_width), Round::TowardZero); + assert_eq!(rounded_min.status, Status::OK); + let rounded_max = + ieee::Double::from_u128_r(int_max(signed, int_width), Round::TowardZero); + assert!(rounded_max.value.is_finite()); + (rounded_min.value.to_bits(), rounded_max.value.to_bits()) + }; + // To implement saturation, we perform the following steps: + // + // 1. Cast val to an integer with fpto[su]i. This may result in undef. + // 2. Compare val to f_min and f_max, and use the comparison results to select: + // a) int_ty::MIN if val < f_min or val is NaN + // b) int_ty::MAX if val > f_max + // c) the result of fpto[su]i otherwise + // 3. If val is NaN, return 0.0, otherwise return the result of step 2. + // + // This avoids resulting undef because values in range [f_min, f_max] by definition fit into the + // destination type. It creates an undef temporary, but *producing* undef is not UB. Our use of + // undef does not introduce any non-determinism either. + // More importantly, the above procedure correctly implements saturating conversion. + // Proof (sketch): + // If val is NaN, 0 is returned by definition. + // Otherwise, val is finite or infinite and thus can be compared with f_min and f_max. + // This yields three cases to consider: + // (1) if val in [f_min, f_max], the result of fpto[su]i is returned, which agrees with + // saturating conversion for inputs in that range. + // (2) if val > f_max, then val is larger than int_ty::MAX. This holds even if f_max is rounded + // (i.e., if f_max < int_ty::MAX) because in those cases, nextUp(f_max) is already larger + // than int_ty::MAX. Because val is larger than int_ty::MAX, the return value of int_ty::MAX + // is correct. + // (3) if val < f_min, then val is smaller than int_ty::MIN. As shown earlier, f_min exactly equals + // int_ty::MIN and therefore the return value of int_ty::MIN is correct. + // QED. + + let float_bits_to_llval = |bx: &mut Self, bits| { + let bits_llval = match float_width { + 32 => bx.cx().const_u32(bits as u32), + 64 => bx.cx().const_u64(bits as u64), + n => bug!("unsupported float width {}", n), + }; + bx.bitcast(bits_llval, float_ty) + }; + let (f_min, f_max) = match float_width { + 32 => compute_clamp_bounds_single(signed, int_width), + 64 => compute_clamp_bounds_double(signed, int_width), + n => bug!("unsupported float width {}", n), + }; + let f_min = float_bits_to_llval(self, f_min); + let f_max = float_bits_to_llval(self, f_max); + let int_max = self.cx.const_uint_big(int_ty, int_max(signed, int_width)); + let int_min = self.cx.const_uint_big(int_ty, int_min(signed, int_width) as u128); + let zero = self.cx.const_uint(int_ty, 0); + + // If we're working with vectors, constants must be "splatted": the constant is duplicated + // into each lane of the vector. The algorithm stays the same, we are just using the + // same constant across all lanes. + let maybe_splat = |bx: &mut Self, val| { + if bx.cx().type_kind(dest_ty) == TypeKind::Vector { + bx.vector_splat(bx.vector_length(dest_ty), val) + } else { + val + } + }; + let f_min = maybe_splat(self, f_min); + let f_max = maybe_splat(self, f_max); + let int_max = maybe_splat(self, int_max); + let int_min = maybe_splat(self, int_min); + let zero = maybe_splat(self, zero); + + // Step 1 ... + let fptosui_result = if signed { self.fptosi(val, dest_ty) } else { self.fptoui(val, dest_ty) }; + let less_or_nan = self.fcmp(RealPredicate::RealULT, val, f_min); + let greater = self.fcmp(RealPredicate::RealOGT, val, f_max); + + // Step 2: We use two comparisons and two selects, with %s1 being the + // result: + // %less_or_nan = fcmp ult %val, %f_min + // %greater = fcmp olt %val, %f_max + // %s0 = select %less_or_nan, int_ty::MIN, %fptosi_result + // %s1 = select %greater, int_ty::MAX, %s0 + // Note that %less_or_nan uses an *unordered* comparison. This + // comparison is true if the operands are not comparable (i.e., if val is + // NaN). The unordered comparison ensures that s1 becomes int_ty::MIN if + // val is NaN. + // + // Performance note: Unordered comparison can be lowered to a "flipped" + // comparison and a negation, and the negation can be merged into the + // select. Therefore, it not necessarily any more expensive than an + // ordered ("normal") comparison. Whether these optimizations will be + // performed is ultimately up to the backend, but at least x86 does + // perform them. + let s0 = self.select(less_or_nan, int_min, fptosui_result); + let s1 = self.select(greater, int_max, s0); + + // Step 3: NaN replacement. + // For unsigned types, the above step already yielded int_ty::MIN == 0 if val is NaN. + // Therefore we only need to execute this step for signed integer types. + if signed { + // LLVM has no isNaN predicate, so we use (val == val) instead + let cmp = self.fcmp(RealPredicate::RealOEQ, val, val); + self.select(cmp, s1, zero) + } else { + s1 + } + } + #[cfg(feature="master")] pub fn shuffle_vector(&mut self, v1: RValue<'gcc>, v2: RValue<'gcc>, mask: RValue<'gcc>) -> RValue<'gcc> { let struct_type = mask.get_type().is_struct().expect("mask should be of struct type"); diff --git a/src/lib.rs b/src/lib.rs index e52ee4818f3e..36aa071fd0f8 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -19,6 +19,7 @@ #![warn(rust_2018_idioms)] #![warn(unused_lifetimes)] +extern crate rustc_apfloat; extern crate rustc_ast; extern crate rustc_attr; extern crate rustc_codegen_ssa; From a50c15275f951d09f6f75c1503443424b5d71869 Mon Sep 17 00:00:00 2001 From: Oli Scherer Date: Tue, 6 Sep 2022 14:09:49 +0000 Subject: [PATCH 245/356] Remove dead broken code from const zst handling in backends --- src/common.rs | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/common.rs b/src/common.rs index 1d44dc486683..102d1e5a824d 100644 --- a/src/common.rs +++ b/src/common.rs @@ -158,10 +158,6 @@ impl<'gcc, 'tcx> ConstMethods<'tcx> for CodegenCx<'gcc, 'tcx> { None } - fn zst_to_backend(&self, _ty: Type<'gcc>) -> RValue<'gcc> { - self.const_undef(self.type_ix(0)) - } - fn scalar_to_backend(&self, cv: Scalar, layout: abi::Scalar, ty: Type<'gcc>) -> RValue<'gcc> { let bitsize = if layout.is_bool() { 1 } else { layout.size(self).bits() }; match cv { From a900ba9163e7631ab2292c33aeac8e669f65d458 Mon Sep 17 00:00:00 2001 From: Urgau Date: Sat, 24 Sep 2022 12:34:56 +0200 Subject: [PATCH 246/356] Stabilize bench_black_box --- tests/run/int.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/run/int.rs b/tests/run/int.rs index 5693b6a215a6..bfe73c38435a 100644 --- a/tests/run/int.rs +++ b/tests/run/int.rs @@ -3,7 +3,7 @@ // Run-time: // status: 0 -#![feature(bench_black_box, const_black_box)] +#![feature(const_black_box)] /* * Code From c503d978dc78281dd0f93f1bbb55d378a6a97736 Mon Sep 17 00:00:00 2001 From: Ellis Hoag Date: Fri, 26 Aug 2022 19:32:04 -0700 Subject: [PATCH 247/356] Add RanlibFailure --- src/archive.rs | 4 +++- src/errors.rs | 7 +++++++ src/lib.rs | 2 ++ 3 files changed, 12 insertions(+), 1 deletion(-) create mode 100644 src/errors.rs diff --git a/src/archive.rs b/src/archive.rs index f863abdcc97e..14a69c194e4e 100644 --- a/src/archive.rs +++ b/src/archive.rs @@ -1,6 +1,8 @@ use std::fs::File; use std::path::{Path, PathBuf}; +use crate::errors::RanlibFailure; + use rustc_codegen_ssa::back::archive::{ArchiveBuilder, ArchiveBuilderBuilder}; use rustc_session::Session; @@ -181,7 +183,7 @@ impl<'a> ArchiveBuilder<'a> for ArArchiveBuilder<'a> { std::process::Command::new("ranlib").arg(output).status().expect("Couldn't run ranlib"); if !status.success() { - self.config.sess.fatal(&format!("Ranlib exited with code {:?}", status.code())); + self.config.sess.emit_fatal(RanlibFailure { exit_code: status.code() }); } any_members diff --git a/src/errors.rs b/src/errors.rs new file mode 100644 index 000000000000..1a0e38fc0bb2 --- /dev/null +++ b/src/errors.rs @@ -0,0 +1,7 @@ +use rustc_macros::SessionDiagnostic; + +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::ranlib_failure)] +pub(crate) struct RanlibFailure { + pub exit_code: Option +} diff --git a/src/lib.rs b/src/lib.rs index 36aa071fd0f8..45e85034cc1c 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -26,6 +26,7 @@ extern crate rustc_codegen_ssa; extern crate rustc_data_structures; extern crate rustc_errors; extern crate rustc_hir; +extern crate rustc_macros; extern crate rustc_metadata; extern crate rustc_middle; extern crate rustc_session; @@ -52,6 +53,7 @@ mod context; mod coverageinfo; mod debuginfo; mod declare; +mod errors; mod int; mod intrinsic; mod mono_item; From 5a9ec83a177e01fc45bd2439148dd3d470424480 Mon Sep 17 00:00:00 2001 From: Ellis Hoag Date: Fri, 26 Aug 2022 20:23:50 -0700 Subject: [PATCH 248/356] Add LinkageConstOrMutType --- src/consts.rs | 6 ++---- src/errors.rs | 8 ++++++++ 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/src/consts.rs b/src/consts.rs index b91fbfd6d94f..be50850d82fc 100644 --- a/src/consts.rs +++ b/src/consts.rs @@ -14,6 +14,7 @@ use rustc_target::abi::{self, Align, HasDataLayout, Primitive, Size, WrappingRan use crate::base; use crate::context::CodegenCx; +use crate::errors::LinkageConstOrMutType; use crate::type_of::LayoutGccExt; impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { @@ -350,10 +351,7 @@ fn check_and_apply_linkage<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, attrs: &Codeg cx.layout_of(mt.ty).gcc_type(cx) } else { - cx.sess().span_fatal( - span, - "must have type `*const T` or `*mut T` due to `#[linkage]` attribute", - ) + cx.sess().emit_fatal(LinkageConstOrMutType { span: span }) }; // Declare a symbol `foo` with the desired linkage. let global1 = cx.declare_global_with_linkage(&sym, llty2, base::global_linkage_to_gcc(linkage)); diff --git a/src/errors.rs b/src/errors.rs index 1a0e38fc0bb2..456a60c6f90b 100644 --- a/src/errors.rs +++ b/src/errors.rs @@ -1,7 +1,15 @@ use rustc_macros::SessionDiagnostic; +use rustc_span::Span; #[derive(SessionDiagnostic)] #[diag(codegen_gcc::ranlib_failure)] pub(crate) struct RanlibFailure { pub exit_code: Option } + +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::linkage_const_or_mut_type)] +pub(crate) struct LinkageConstOrMutType { + #[primary_span] + pub span: Span +} From 2592befa7c5a10f179270621b002b49581fe6824 Mon Sep 17 00:00:00 2001 From: Ellis Hoag Date: Fri, 26 Aug 2022 20:44:44 -0700 Subject: [PATCH 249/356] Add UnwindingInlineAsm --- src/asm.rs | 3 ++- src/errors.rs | 7 +++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/asm.rs b/src/asm.rs index 19cd44f28193..b8ca1c3fd612 100644 --- a/src/asm.rs +++ b/src/asm.rs @@ -12,6 +12,7 @@ use std::borrow::Cow; use crate::builder::Builder; use crate::context::CodegenCx; +use crate::errors::UnwindingInlineAsm; use crate::type_of::LayoutGccExt; use crate::callee::get_fn; @@ -109,7 +110,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { fn codegen_inline_asm(&mut self, template: &[InlineAsmTemplatePiece], rust_operands: &[InlineAsmOperandRef<'tcx, Self>], options: InlineAsmOptions, span: &[Span], _instance: Instance<'_>, _dest_catch_funclet: Option<(Self::BasicBlock, Self::BasicBlock, Option<&Self::Funclet>)>) { if options.contains(InlineAsmOptions::MAY_UNWIND) { self.sess() - .struct_span_err(span[0], "GCC backend does not support unwinding from inline asm") + .create_err(UnwindingInlineAsm { span: span[0] }) .emit(); return; } diff --git a/src/errors.rs b/src/errors.rs index 456a60c6f90b..e0c7dca8e324 100644 --- a/src/errors.rs +++ b/src/errors.rs @@ -13,3 +13,10 @@ pub(crate) struct LinkageConstOrMutType { #[primary_span] pub span: Span } + +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::unwinding_inline_asm)] +pub(crate) struct UnwindingInlineAsm { + #[primary_span] + pub span: Span +} From 4a861c140a79bea5ef63b45a6f60141e6b0e0bfa Mon Sep 17 00:00:00 2001 From: Ellis Hoag Date: Fri, 26 Aug 2022 20:50:37 -0700 Subject: [PATCH 250/356] Add LTONotSupported --- src/errors.rs | 4 ++++ src/lib.rs | 3 ++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/errors.rs b/src/errors.rs index e0c7dca8e324..1b2953952ef7 100644 --- a/src/errors.rs +++ b/src/errors.rs @@ -14,6 +14,10 @@ pub(crate) struct LinkageConstOrMutType { pub span: Span } +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::lto_not_supported)] +pub(crate) struct LTONotSupported {} + #[derive(SessionDiagnostic)] #[diag(codegen_gcc::unwinding_inline_asm)] pub(crate) struct UnwindingInlineAsm { diff --git a/src/lib.rs b/src/lib.rs index 45e85034cc1c..0c0f5255fb8a 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -63,6 +63,7 @@ mod type_of; use std::any::Any; use std::sync::{Arc, Mutex}; +use crate::errors::LTONotSupported; use gccjit::{Context, OptimizationLevel, CType}; use rustc_ast::expand::allocator::AllocatorKind; use rustc_codegen_ssa::{CodegenResults, CompiledModule, ModuleCodegen}; @@ -101,7 +102,7 @@ pub struct GccCodegenBackend { impl CodegenBackend for GccCodegenBackend { fn init(&self, sess: &Session) { if sess.lto() != Lto::No { - sess.warn("LTO is not supported. You may get a linker error."); + sess.emit_warning(LTONotSupported {}); } let temp_dir = TempDir::new().expect("cannot create temporary directory"); From 1b5dd4bf5ebf987ad4d70975e466bf4d6b1f395c Mon Sep 17 00:00:00 2001 From: Ellis Hoag Date: Sat, 27 Aug 2022 15:19:16 -0700 Subject: [PATCH 251/356] Add LayoutSizeOverflow --- src/context.rs | 5 +++-- src/errors.rs | 8 ++++++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/context.rs b/src/context.rs index 07222c534401..f1f808caafe6 100644 --- a/src/context.rs +++ b/src/context.rs @@ -19,6 +19,7 @@ use rustc_target::abi::{call::FnAbi, HasDataLayout, PointeeInfo, Size, TargetDat use rustc_target::spec::{HasTargetSpec, Target, TlsModel}; use crate::callee::get_fn; +use crate::errors::LayoutSizeOverflow; #[derive(Clone)] pub struct FuncSig<'gcc> { @@ -492,7 +493,7 @@ impl<'gcc, 'tcx> LayoutOfHelpers<'tcx> for CodegenCx<'gcc, 'tcx> { #[inline] fn handle_layout_err(&self, err: LayoutError<'tcx>, span: Span, ty: Ty<'tcx>) -> ! { if let LayoutError::SizeOverflow(_) = err { - self.sess().span_fatal(span, &err.to_string()) + self.sess().emit_fatal(LayoutSizeOverflow { span, error: err.to_string() }) } else { span_bug!(span, "failed to get layout for `{}`: {}", ty, err) } @@ -510,7 +511,7 @@ impl<'gcc, 'tcx> FnAbiOfHelpers<'tcx> for CodegenCx<'gcc, 'tcx> { fn_abi_request: FnAbiRequest<'tcx>, ) -> ! { if let FnAbiError::Layout(LayoutError::SizeOverflow(_)) = err { - self.sess().span_fatal(span, &err.to_string()) + self.sess().emit_fatal(LayoutSizeOverflow { span, error: err.to_string() }) } else { match fn_abi_request { FnAbiRequest::OfFnPtr { sig, extra_args } => { diff --git a/src/errors.rs b/src/errors.rs index 1b2953952ef7..490a209ead05 100644 --- a/src/errors.rs +++ b/src/errors.rs @@ -7,6 +7,14 @@ pub(crate) struct RanlibFailure { pub exit_code: Option } +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::layout_size_overflow)] +pub(crate) struct LayoutSizeOverflow { + #[primary_span] + pub span: Span, + pub error: String, +} + #[derive(SessionDiagnostic)] #[diag(codegen_gcc::linkage_const_or_mut_type)] pub(crate) struct LinkageConstOrMutType { From b4a051e3b342d62a52f1d204dafac5bea31f5360 Mon Sep 17 00:00:00 2001 From: Ellis Hoag Date: Sat, 27 Aug 2022 15:21:46 -0700 Subject: [PATCH 252/356] Lint against untranslatable diagnostics in rustc_codegen_gcc --- src/lib.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/lib.rs b/src/lib.rs index 0c0f5255fb8a..b660029a4af9 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -18,6 +18,8 @@ #![recursion_limit="256"] #![warn(rust_2018_idioms)] #![warn(unused_lifetimes)] +#![deny(rustc::untranslatable_diagnostic)] +#![deny(rustc::diagnostic_outside_of_impl)] extern crate rustc_apfloat; extern crate rustc_ast; From c4149da9fd52d93aecbdcb1aae5b2c830f3c0ab6 Mon Sep 17 00:00:00 2001 From: Ellis Hoag Date: Mon, 29 Aug 2022 20:22:03 -0700 Subject: [PATCH 253/356] remove IntoDiagnosticArg impl for Option --- src/archive.rs | 2 +- src/errors.rs | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/archive.rs b/src/archive.rs index 14a69c194e4e..77fbb2c500e8 100644 --- a/src/archive.rs +++ b/src/archive.rs @@ -183,7 +183,7 @@ impl<'a> ArchiveBuilder<'a> for ArArchiveBuilder<'a> { std::process::Command::new("ranlib").arg(output).status().expect("Couldn't run ranlib"); if !status.success() { - self.config.sess.emit_fatal(RanlibFailure { exit_code: status.code() }); + self.config.sess.emit_fatal(RanlibFailure { exit_code: format!("{:?}", status.code()) }); } any_members diff --git a/src/errors.rs b/src/errors.rs index 490a209ead05..01de75976a32 100644 --- a/src/errors.rs +++ b/src/errors.rs @@ -4,7 +4,7 @@ use rustc_span::Span; #[derive(SessionDiagnostic)] #[diag(codegen_gcc::ranlib_failure)] pub(crate) struct RanlibFailure { - pub exit_code: Option + pub exit_code: String, } #[derive(SessionDiagnostic)] From 4718beead66e1d234ff40d1621b84a2f3537fa91 Mon Sep 17 00:00:00 2001 From: Ellis Hoag Date: Wed, 31 Aug 2022 22:02:35 -0700 Subject: [PATCH 254/356] Add wrapper type for ExitCode for use in RanlibFailure --- src/archive.rs | 2 +- src/errors.rs | 24 +++++++++++++++++++++++- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/src/archive.rs b/src/archive.rs index 77fbb2c500e8..ac0342f6b80a 100644 --- a/src/archive.rs +++ b/src/archive.rs @@ -183,7 +183,7 @@ impl<'a> ArchiveBuilder<'a> for ArArchiveBuilder<'a> { std::process::Command::new("ranlib").arg(output).status().expect("Couldn't run ranlib"); if !status.success() { - self.config.sess.emit_fatal(RanlibFailure { exit_code: format!("{:?}", status.code()) }); + self.config.sess.emit_fatal(RanlibFailure::new(status.code())); } any_members diff --git a/src/errors.rs b/src/errors.rs index 01de75976a32..b5fc789c2791 100644 --- a/src/errors.rs +++ b/src/errors.rs @@ -1,10 +1,32 @@ +use rustc_errors::{DiagnosticArgValue, IntoDiagnosticArg}; use rustc_macros::SessionDiagnostic; use rustc_span::Span; +use std::borrow::Cow; + +struct ExitCode { + pub exit_code: Option, +} + +impl IntoDiagnosticArg for ExitCode { + fn into_diagnostic_arg(self) -> DiagnosticArgValue<'static> { + match self.exit_code { + Some(t) => t.into_diagnostic_arg(), + None => DiagnosticArgValue::Str(Cow::Borrowed("None")), + } + } +} #[derive(SessionDiagnostic)] #[diag(codegen_gcc::ranlib_failure)] pub(crate) struct RanlibFailure { - pub exit_code: String, + exit_code: ExitCode, +} + +impl RanlibFailure { + pub fn new(exit_code: Option) -> Self { + let exit_code = ExitCode{ exit_code }; + RanlibFailure { exit_code } + } } #[derive(SessionDiagnostic)] From f21041d7c3eb68ecbb3b06b4878071e30d387f9d Mon Sep 17 00:00:00 2001 From: Ellis Hoag Date: Wed, 31 Aug 2022 22:03:05 -0700 Subject: [PATCH 255/356] lint type --- src/errors.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/errors.rs b/src/errors.rs index b5fc789c2791..938c0a74af38 100644 --- a/src/errors.rs +++ b/src/errors.rs @@ -46,7 +46,7 @@ pub(crate) struct LinkageConstOrMutType { #[derive(SessionDiagnostic)] #[diag(codegen_gcc::lto_not_supported)] -pub(crate) struct LTONotSupported {} +pub(crate) struct LTONotSupported; #[derive(SessionDiagnostic)] #[diag(codegen_gcc::unwinding_inline_asm)] From ef3aaa1f210b2e72c16a9a880ae3d1fd6061fc9f Mon Sep 17 00:00:00 2001 From: Ellis Hoag Date: Sun, 11 Sep 2022 16:43:18 -0700 Subject: [PATCH 256/356] Add monomorphization errors --- src/errors.rs | 198 +++++++++++++++++++++++++++++++++++++++- src/intrinsic/mod.rs | 13 +-- src/intrinsic/simd.rs | 207 +++++++++++++++--------------------------- 3 files changed, 271 insertions(+), 147 deletions(-) diff --git a/src/errors.rs b/src/errors.rs index 938c0a74af38..a70ebf62da3e 100644 --- a/src/errors.rs +++ b/src/errors.rs @@ -1,6 +1,7 @@ use rustc_errors::{DiagnosticArgValue, IntoDiagnosticArg}; use rustc_macros::SessionDiagnostic; -use rustc_span::Span; +use rustc_middle::ty::Ty; +use rustc_span::{Span, Symbol}; use std::borrow::Cow; struct ExitCode { @@ -29,6 +30,201 @@ impl RanlibFailure { } } +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::invalid_monomorphization_basic_integer, code = "E0511")] +pub(crate) struct InvalidMonomorphizationBasicInteger<'a> { + #[primary_span] + pub span: Span, + pub name: Symbol, + pub ty: Ty<'a>, +} + +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::invalid_monomorphization_invalid_float_vector, code = "E0511")] +pub(crate) struct InvalidMonomorphizationInvalidFloatVector<'a> { + #[primary_span] + pub span: Span, + pub name: Symbol, + pub elem_ty: &'a str, + pub vec_ty: Ty<'a>, +} + +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::invalid_monomorphization_not_float, code = "E0511")] +pub(crate) struct InvalidMonomorphizationNotFloat<'a> { + #[primary_span] + pub span: Span, + pub name: Symbol, + pub ty: Ty<'a>, +} + +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::invalid_monomorphization_unrecognized, code = "E0511")] +pub(crate) struct InvalidMonomorphizationUnrecognized { + #[primary_span] + pub span: Span, + pub name: Symbol, +} + +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::invalid_monomorphization_expected_signed_unsigned, code = "E0511")] +pub(crate) struct InvalidMonomorphizationExpectedSignedUnsigned<'a> { + #[primary_span] + pub span: Span, + pub name: Symbol, + pub elem_ty: Ty<'a>, + pub vec_ty: Ty<'a>, +} + +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::invalid_monomorphization_unsupported_element, code = "E0511")] +pub(crate) struct InvalidMonomorphizationUnsupportedElement<'a> { + #[primary_span] + pub span: Span, + pub name: Symbol, + pub in_ty: Ty<'a>, + pub elem_ty: Ty<'a>, + pub ret_ty: Ty<'a>, +} + +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::invalid_monomorphization_invalid_bitmask, code = "E0511")] +pub(crate) struct InvalidMonomorphizationInvalidBitmask<'a> { + #[primary_span] + pub span: Span, + pub name: Symbol, + pub ty: Ty<'a>, + pub expected_int_bits: u64, + pub expected_bytes: u64, +} + +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::invalid_monomorphization_simd_shuffle, code = "E0511")] +pub(crate) struct InvalidMonomorphizationSimdShuffle<'a> { + #[primary_span] + pub span: Span, + pub name: Symbol, + pub ty: Ty<'a>, +} + +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::invalid_monomorphization_expected_simd, code = "E0511")] +pub(crate) struct InvalidMonomorphizationExpectedSimd<'a> { + #[primary_span] + pub span: Span, + pub name: Symbol, + pub position: &'a str, + pub found_ty: Ty<'a>, +} + +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::invalid_monomorphization_mask_type, code = "E0511")] +pub(crate) struct InvalidMonomorphizationMaskType<'a> { + #[primary_span] + pub span: Span, + pub name: Symbol, + pub ty: Ty<'a>, +} + +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::invalid_monomorphization_return_length, code = "E0511")] +pub(crate) struct InvalidMonomorphizationReturnLength<'a> { + #[primary_span] + pub span: Span, + pub name: Symbol, + pub in_len: u64, + pub ret_ty: Ty<'a>, + pub out_len: u64, +} + +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::invalid_monomorphization_return_length_input_type, code = "E0511")] +pub(crate) struct InvalidMonomorphizationReturnLengthInputType<'a> { + #[primary_span] + pub span: Span, + pub name: Symbol, + pub in_len: u64, + pub in_ty: Ty<'a>, + pub ret_ty: Ty<'a>, + pub out_len: u64, +} + +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::invalid_monomorphization_return_element, code = "E0511")] +pub(crate) struct InvalidMonomorphizationReturnElement<'a> { + #[primary_span] + pub span: Span, + pub name: Symbol, + pub in_elem: Ty<'a>, + pub in_ty: Ty<'a>, + pub ret_ty: Ty<'a>, + pub out_ty: Ty<'a>, +} + +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::invalid_monomorphization_return_type, code = "E0511")] +pub(crate) struct InvalidMonomorphizationReturnType<'a> { + #[primary_span] + pub span: Span, + pub name: Symbol, + pub in_elem: Ty<'a>, + pub in_ty: Ty<'a>, + pub ret_ty: Ty<'a>, +} + +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::invalid_monomorphization_inserted_type, code = "E0511")] +pub(crate) struct InvalidMonomorphizationInsertedType<'a> { + #[primary_span] + pub span: Span, + pub name: Symbol, + pub in_elem: Ty<'a>, + pub in_ty: Ty<'a>, + pub out_ty: Ty<'a>, +} + +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::invalid_monomorphization_return_integer_type, code = "E0511")] +pub(crate) struct InvalidMonomorphizationReturnIntegerType<'a> { + #[primary_span] + pub span: Span, + pub name: Symbol, + pub ret_ty: Ty<'a>, + pub out_ty: Ty<'a>, +} + +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::invalid_monomorphization_mismatched_lengths, code = "E0511")] +pub(crate) struct InvalidMonomorphizationMismatchedLengths { + #[primary_span] + pub span: Span, + pub name: Symbol, + pub m_len: u64, + pub v_len: u64, +} + +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::invalid_monomorphization_unsupported_cast, code = "E0511")] +pub(crate) struct InvalidMonomorphizationUnsupportedCast<'a> { + #[primary_span] + pub span: Span, + pub name: Symbol, + pub in_ty: Ty<'a>, + pub in_elem: Ty<'a>, + pub ret_ty: Ty<'a>, + pub out_elem: Ty<'a>, +} + +#[derive(SessionDiagnostic)] +#[diag(codegen_gcc::invalid_monomorphization_unsupported_operation, code = "E0511")] +pub(crate) struct InvalidMonomorphizationUnsupportedOperation<'a> { + #[primary_span] + pub span: Span, + pub name: Symbol, + pub in_ty: Ty<'a>, + pub in_elem: Ty<'a>, +} + #[derive(SessionDiagnostic)] #[diag(codegen_gcc::layout_size_overflow)] pub(crate) struct LayoutSizeOverflow { diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index 205f795ec58c..bdeede2ab5e6 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -7,7 +7,7 @@ use std::iter; use gccjit::{ComparisonOp, Function, RValue, ToRValue, Type, UnaryOp, FunctionType}; use rustc_codegen_ssa::MemFlags; use rustc_codegen_ssa::base::wants_msvc_seh; -use rustc_codegen_ssa::common::{IntPredicate, span_invalid_monomorphization_error}; +use rustc_codegen_ssa::common::IntPredicate; use rustc_codegen_ssa::mir::operand::{OperandRef, OperandValue}; use rustc_codegen_ssa::mir::place::PlaceRef; use rustc_codegen_ssa::traits::{ArgAbiMethods, BaseTypeMethods, BuilderMethods, ConstMethods, IntrinsicCallMethods}; @@ -31,6 +31,7 @@ use crate::abi::FnAbiGccExt; use crate::builder::Builder; use crate::common::{SignType, TypeReflection}; use crate::context::CodegenCx; +use crate::errors::InvalidMonomorphizationBasicInteger; use crate::type_of::LayoutGccExt; use crate::intrinsic::simd::generic_simd_intrinsic; @@ -253,15 +254,7 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { _ => bug!(), }, None => { - span_invalid_monomorphization_error( - tcx.sess, - span, - &format!( - "invalid monomorphization of `{}` intrinsic: \ - expected basic integer type, found `{}`", - name, ty - ), - ); + tcx.sess.emit_err(InvalidMonomorphizationBasicInteger { span, name, ty }); return; } } diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index 233d0b7f739d..f95db2271b33 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -2,7 +2,7 @@ use gccjit::{ToRValue, ComparisonOp, UnaryOp}; use gccjit::{BinaryOp, RValue, Type}; use rustc_codegen_ssa::base::compare_simd_types; -use rustc_codegen_ssa::common::{IntPredicate, TypeKind, span_invalid_monomorphization_error}; +use rustc_codegen_ssa::common::{IntPredicate, TypeKind}; use rustc_codegen_ssa::mir::operand::OperandRef; use rustc_codegen_ssa::mir::place::PlaceRef; use rustc_codegen_ssa::traits::{BaseTypeMethods, BuilderMethods}; @@ -16,42 +16,46 @@ use rustc_target::abi::Align; use crate::builder::Builder; #[cfg(feature="master")] use crate::context::CodegenCx; +use crate::errors::{ + InvalidMonomorphizationInvalidFloatVector, + InvalidMonomorphizationNotFloat, + InvalidMonomorphizationUnrecognized, + InvalidMonomorphizationExpectedSignedUnsigned, + InvalidMonomorphizationUnsupportedElement, + InvalidMonomorphizationInvalidBitmask, + InvalidMonomorphizationSimdShuffle, + InvalidMonomorphizationExpectedSimd, + InvalidMonomorphizationMaskType, + InvalidMonomorphizationReturnLength, + InvalidMonomorphizationReturnLengthInputType, + InvalidMonomorphizationReturnElement, + InvalidMonomorphizationReturnType, + InvalidMonomorphizationInsertedType, + InvalidMonomorphizationReturnIntegerType, + InvalidMonomorphizationMismatchedLengths, + InvalidMonomorphizationUnsupportedOperation +}; pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, name: Symbol, callee_ty: Ty<'tcx>, args: &[OperandRef<'tcx, RValue<'gcc>>], ret_ty: Ty<'tcx>, llret_ty: Type<'gcc>, span: Span) -> Result, ()> { // macros for error handling: - #[allow(unused_macro_rules)] - macro_rules! emit_error { - ($msg: tt) => { - emit_error!($msg, ) - }; - ($msg: tt, $($fmt: tt)*) => { - span_invalid_monomorphization_error( - bx.sess(), span, - &format!(concat!("invalid monomorphization of `{}` intrinsic: ", $msg), - name, $($fmt)*)); - } - } - macro_rules! return_error { - ($($fmt: tt)*) => { + ($err:expr) => { { - emit_error!($($fmt)*); + bx.sess().emit_err($err); return Err(()); } } } - macro_rules! require { - ($cond: expr, $($fmt: tt)*) => { + ($cond:expr, $err:expr) => { if !$cond { - return_error!($($fmt)*); + return_error!($err); } - }; + } } - macro_rules! require_simd { ($ty: expr, $position: expr) => { - require!($ty.is_simd(), "expected SIMD {} type, found non-SIMD `{}`", $position, $ty) + require!($ty.is_simd(), InvalidMonomorphizationExpectedSimd { span, name, position: $position, found_ty: $ty }) }; } @@ -83,10 +87,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, bx.load(int_ty, ptr, Align::ONE) } _ => return_error!( - "invalid bitmask `{}`, expected `u{}` or `[u8; {}]`", - mask_ty, - expected_int_bits, - expected_bytes + InvalidMonomorphizationInvalidBitmask { span, name, ty: mask_ty, expected_int_bits, expected_bytes } ), }; @@ -133,18 +134,11 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let (out_len, out_ty) = ret_ty.simd_size_and_type(bx.tcx()); require!( in_len == out_len, - "expected return type with length {} (same as input type `{}`), \ - found `{}` with length {}", - in_len, - in_ty, - ret_ty, - out_len + InvalidMonomorphizationReturnLengthInputType { span, name, in_len, in_ty, ret_ty, out_len } ); require!( bx.type_kind(bx.element_type(llret_ty)) == TypeKind::Integer, - "expected return type with integer elements, found `{}` with non-integer `{}`", - ret_ty, - out_ty + InvalidMonomorphizationReturnIntegerType {span, name, ret_ty, out_ty} ); return Ok(compare_simd_types( @@ -169,8 +163,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, }) } _ => return_error!( - "simd_shuffle index must be an array of `u32`, got `{}`", - args[2].layout.ty + InvalidMonomorphizationSimdShuffle { span, name, ty: args[2].layout.ty } ), } } @@ -185,19 +178,11 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let (out_len, out_ty) = ret_ty.simd_size_and_type(bx.tcx()); require!( out_len == n, - "expected return type of length {}, found `{}` with length {}", - n, - ret_ty, - out_len + InvalidMonomorphizationReturnLength { span, name, in_len: n, ret_ty, out_len } ); require!( in_elem == out_ty, - "expected return element type `{}` (element of input `{}`), \ - found `{}` with element type `{}`", - in_elem, - in_ty, - ret_ty, - out_ty + InvalidMonomorphizationReturnElement { span, name, in_elem, in_ty, ret_ty, out_ty } ); let vector = args[2].immediate(); @@ -213,10 +198,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, if name == sym::simd_insert { require!( in_elem == arg_tys[2], - "expected inserted type `{}` (element of input `{}`), found `{}`", - in_elem, - in_ty, - arg_tys[2] + InvalidMonomorphizationInsertedType { span, name, in_elem, in_ty, out_ty: arg_tys[2] } ); let vector = args[0].immediate(); let index = args[1].immediate(); @@ -233,10 +215,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, if name == sym::simd_extract { require!( ret_ty == in_elem, - "expected return type `{}` (element of input `{}`), found `{}`", - in_elem, - in_ty, - ret_ty + InvalidMonomorphizationReturnType { span, name, in_elem, in_ty, ret_ty } ); let vector = args[0].immediate(); return Ok(bx.context.new_vector_access(None, vector, args[1].immediate()).to_rvalue()); @@ -249,13 +228,11 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let (v_len, _) = arg_tys[1].simd_size_and_type(bx.tcx()); require!( m_len == v_len, - "mismatched lengths: mask length `{}` != other vector length `{}`", - m_len, - v_len + InvalidMonomorphizationMismatchedLengths { span, name, m_len, v_len } ); match m_elem_ty.kind() { ty::Int(_) => {} - _ => return_error!("mask element type is `{}`, expected `i_`", m_elem_ty), + _ => return_error!(InvalidMonomorphizationMaskType { span, name, ty: m_elem_ty }), } return Ok(bx.vector_select(args[0].immediate(), args[1].immediate(), args[2].immediate())); } @@ -266,12 +243,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let (out_len, out_elem) = ret_ty.simd_size_and_type(bx.tcx()); require!( in_len == out_len, - "expected return type with length {} (same as input type `{}`), \ - found `{}` with length {}", - in_len, - in_ty, - ret_ty, - out_len + InvalidMonomorphizationReturnLengthInputType { span, name, in_len, in_ty, ret_ty, out_len } ); // casting cares about nominal type, not just structural type if in_elem == out_elem { @@ -322,10 +294,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, })* _ => {}, } - require!(false, - "unsupported operation on `{}` with element `{}`", - in_ty, - in_elem) + return_error!(InvalidMonomorphizationUnsupportedOperation { span, name, in_ty, in_elem }) })* } } @@ -403,23 +372,14 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, span: Span, args: &[OperandRef<'tcx, RValue<'gcc>>], ) -> Result, ()> { - macro_rules! emit_error { - ($msg: tt, $($fmt: tt)*) => { - span_invalid_monomorphization_error( - bx.sess(), span, - &format!(concat!("invalid monomorphization of `{}` intrinsic: ", $msg), - name, $($fmt)*)); - } - } macro_rules! return_error { - ($($fmt: tt)*) => { + ($err:expr) => { { - emit_error!($($fmt)*); + bx.sess().emit_err($err); return Err(()); } } } - let (elem_ty_str, elem_ty) = if let ty::Float(f) = in_elem.kind() { let elem_ty = bx.cx.type_float_from_ty(*f); @@ -427,16 +387,13 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, 32 => ("f", elem_ty), 64 => ("", elem_ty), _ => { - return_error!( - "unsupported element type `{}` of floating-point vector `{}`", - f.name_str(), - in_ty - ); + // Can we pass elem_ty directly? + return_error!(InvalidMonomorphizationInvalidFloatVector { span, name, elem_ty: f.name_str(), vec_ty: in_ty }); } } } else { - return_error!("`{}` is not a floating-point type", in_ty); + return_error!(InvalidMonomorphizationNotFloat { span, name, ty: in_ty }); }; let vec_ty = bx.cx.type_vector(elem_ty, in_len); @@ -459,7 +416,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, sym::simd_fsqrt => "sqrt", sym::simd_round => "round", sym::simd_trunc => "trunc", - _ => return_error!("unrecognized intrinsic `{}`", name), + _ => return_error!(InvalidMonomorphizationUnrecognized { span, name }) }; let builtin_name = format!("{}{}", intr_name, elem_ty_str); let funcs = bx.cx.functions.borrow(); @@ -813,10 +770,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, })* _ => {}, } - require!(false, - "unsupported operation on `{}` with element `{}`", - in_ty, - in_elem) + return_error!(InvalidMonomorphizationUnsupportedOperation { span, name, in_ty, in_elem }) })* } } @@ -836,13 +790,25 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, ty::Int(i) => (true, i.bit_width().unwrap_or(ptr_bits) / 8, bx.cx.type_int_from_ty(i)), ty::Uint(i) => (false, i.bit_width().unwrap_or(ptr_bits) / 8, bx.cx.type_uint_from_ty(i)), _ => { - return_error!( - "expected element type `{}` of vector type `{}` \ - to be a signed or unsigned integer type", - arg_tys[0].simd_size_and_type(bx.tcx()).1, - arg_tys[0] - ); - } + return_error!(InvalidMonomorphizationExpectedSignedUnsigned { + span, + name, + elem_ty: arg_tys[0].simd_size_and_type(bx.tcx()).1, + vec_ty: arg_tys[0], + }); + } + }; + let builtin_name = + match (signed, is_add, in_len, elem_width) { + (true, true, 32, 8) => "__builtin_ia32_paddsb256", // TODO(antoyo): cast arguments to unsigned. + (false, true, 32, 8) => "__builtin_ia32_paddusb256", + (true, true, 16, 16) => "__builtin_ia32_paddsw256", + (false, true, 16, 16) => "__builtin_ia32_paddusw256", + (true, false, 16, 16) => "__builtin_ia32_psubsw256", + (false, false, 16, 16) => "__builtin_ia32_psubusw256", + (true, false, 32, 8) => "__builtin_ia32_psubsb256", + (false, false, 32, 8) => "__builtin_ia32_psubusb256", + _ => unimplemented!("signed: {}, is_add: {}, in_len: {}, elem_width: {}", signed, is_add, in_len, elem_width), }; let result = @@ -924,10 +890,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, if name == sym::$name { require!( ret_ty == in_elem, - "expected return type `{}` (element of input `{}`), found `{}`", - in_elem, - in_ty, - ret_ty + InvalidMonomorphizationReturnType { span, name, in_elem, in_ty, ret_ty } ); return match in_elem.kind() { ty::Int(_) | ty::Uint(_) => { @@ -951,13 +914,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, Ok(bx.vector_reduce_op(args[0].immediate(), $vec_op)) } } - _ => return_error!( - "unsupported {} from `{}` with element `{}` to `{}`", - sym::$name, - in_ty, - in_elem, - ret_ty - ), + _ => return_error!(InvalidMonomorphizationUnsupportedElement { span, name, in_ty, elem_ty: in_elem, ret_ty }), }; } }; @@ -998,21 +955,12 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, if name == sym::$name { require!( ret_ty == in_elem, - "expected return type `{}` (element of input `{}`), found `{}`", - in_elem, - in_ty, - ret_ty + InvalidMonomorphizationReturnType { span, name, in_elem, in_ty, ret_ty } ); return match in_elem.kind() { ty::Int(_) | ty::Uint(_) => Ok(bx.$int_red(args[0].immediate())), ty::Float(_) => Ok(bx.$float_red(args[0].immediate())), - _ => return_error!( - "unsupported {} from `{}` with element `{}` to `{}`", - sym::$name, - in_ty, - in_elem, - ret_ty - ), + _ => return_error!(InvalidMonomorphizationUnsupportedElement { span, name, in_ty, elem_ty: in_elem, ret_ty }), }; } }; @@ -1030,22 +978,13 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let input = if !$boolean { require!( ret_ty == in_elem, - "expected return type `{}` (element of input `{}`), found `{}`", - in_elem, - in_ty, - ret_ty + InvalidMonomorphizationReturnType { span, name, in_elem, in_ty, ret_ty } ); args[0].immediate() } else { match in_elem.kind() { ty::Int(_) | ty::Uint(_) => {} - _ => return_error!( - "unsupported {} from `{}` with element `{}` to `{}`", - sym::$name, - in_ty, - in_elem, - ret_ty - ), + _ => return_error!(InvalidMonomorphizationUnsupportedElement { span, name, in_ty, elem_ty: in_elem, ret_ty }), } args[0].immediate() @@ -1056,11 +995,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, Ok(if !$boolean { r } else { bx.icmp(IntPredicate::IntNE, r, bx.context.new_rvalue_zero(r.get_type())) }) } _ => return_error!( - "unsupported {} from `{}` with element `{}` to `{}`", - sym::$name, - in_ty, - in_elem, - ret_ty + InvalidMonomorphizationUnsupportedElement { span, name, in_ty, elem_ty: in_elem, ret_ty } ), }; } From 2e46dc2cffaca41a17498a4392068dc51aa0349f Mon Sep 17 00:00:00 2001 From: Ellis Hoag Date: Sun, 11 Sep 2022 17:34:51 -0700 Subject: [PATCH 257/356] impl SessionDiagnostic for LayoutError and Spanned --- src/context.rs | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/src/context.rs b/src/context.rs index f1f808caafe6..5341d0f75a66 100644 --- a/src/context.rs +++ b/src/context.rs @@ -14,7 +14,7 @@ use rustc_middle::mir::mono::CodegenUnit; use rustc_middle::ty::{self, Instance, ParamEnv, PolyExistentialTraitRef, Ty, TyCtxt}; use rustc_middle::ty::layout::{FnAbiError, FnAbiOf, FnAbiOfHelpers, FnAbiRequest, HasParamEnv, HasTyCtxt, LayoutError, TyAndLayout, LayoutOfHelpers}; use rustc_session::Session; -use rustc_span::Span; +use rustc_span::{Span, source_map::respan}; use rustc_target::abi::{call::FnAbi, HasDataLayout, PointeeInfo, Size, TargetDataLayout, VariantIdx}; use rustc_target::spec::{HasTargetSpec, Target, TlsModel}; @@ -493,6 +493,23 @@ impl<'gcc, 'tcx> LayoutOfHelpers<'tcx> for CodegenCx<'gcc, 'tcx> { #[inline] fn handle_layout_err(&self, err: LayoutError<'tcx>, span: Span, ty: Ty<'tcx>) -> ! { if let LayoutError::SizeOverflow(_) = err { + let _ = respan(span, err); + // error: lifetime may not live long enough + // --> src/context.rs:483:13 + // | + // 475 | impl<'gcc, 'tcx> LayoutOfHelpers<'tcx> for CodegenCx<'gcc, 'tcx> { + // | ---- ---- lifetime `'tcx` defined here + // | | + // | lifetime `'gcc` defined here + // ... + // 483 | self.sess().emit_fatal(respan(span, err)) + // | ^^^^^^^^^^^ argument requires that `'gcc` must outlive `'tcx` + // | + // = help: consider adding the following bound: `'gcc: 'tcx` + // = note: requirement occurs because of the type `CodegenCx<'_, '_>`, which makes the generic argument `'_` invariant + // = note: the struct `CodegenCx<'gcc, 'tcx>` is invariant over the parameter `'gcc` + // = help: see for more information about variance + // self.sess().emit_fatal(respan(span, err)) self.sess().emit_fatal(LayoutSizeOverflow { span, error: err.to_string() }) } else { span_bug!(span, "failed to get layout for `{}`: {}", ty, err) From 9bbb49150ace414bf0b10476de83fb5c2c4b6630 Mon Sep 17 00:00:00 2001 From: Ellis Hoag Date: Sat, 24 Sep 2022 11:05:37 -0700 Subject: [PATCH 258/356] rebase and update trait names --- src/errors.rs | 50 +++++++++++++++++++++++++------------------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/src/errors.rs b/src/errors.rs index a70ebf62da3e..a1c95e7a7f45 100644 --- a/src/errors.rs +++ b/src/errors.rs @@ -1,5 +1,5 @@ use rustc_errors::{DiagnosticArgValue, IntoDiagnosticArg}; -use rustc_macros::SessionDiagnostic; +use rustc_macros::Diagnostic; use rustc_middle::ty::Ty; use rustc_span::{Span, Symbol}; use std::borrow::Cow; @@ -17,7 +17,7 @@ impl IntoDiagnosticArg for ExitCode { } } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::ranlib_failure)] pub(crate) struct RanlibFailure { exit_code: ExitCode, @@ -30,7 +30,7 @@ impl RanlibFailure { } } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::invalid_monomorphization_basic_integer, code = "E0511")] pub(crate) struct InvalidMonomorphizationBasicInteger<'a> { #[primary_span] @@ -39,7 +39,7 @@ pub(crate) struct InvalidMonomorphizationBasicInteger<'a> { pub ty: Ty<'a>, } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::invalid_monomorphization_invalid_float_vector, code = "E0511")] pub(crate) struct InvalidMonomorphizationInvalidFloatVector<'a> { #[primary_span] @@ -49,7 +49,7 @@ pub(crate) struct InvalidMonomorphizationInvalidFloatVector<'a> { pub vec_ty: Ty<'a>, } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::invalid_monomorphization_not_float, code = "E0511")] pub(crate) struct InvalidMonomorphizationNotFloat<'a> { #[primary_span] @@ -58,7 +58,7 @@ pub(crate) struct InvalidMonomorphizationNotFloat<'a> { pub ty: Ty<'a>, } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::invalid_monomorphization_unrecognized, code = "E0511")] pub(crate) struct InvalidMonomorphizationUnrecognized { #[primary_span] @@ -66,7 +66,7 @@ pub(crate) struct InvalidMonomorphizationUnrecognized { pub name: Symbol, } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::invalid_monomorphization_expected_signed_unsigned, code = "E0511")] pub(crate) struct InvalidMonomorphizationExpectedSignedUnsigned<'a> { #[primary_span] @@ -76,7 +76,7 @@ pub(crate) struct InvalidMonomorphizationExpectedSignedUnsigned<'a> { pub vec_ty: Ty<'a>, } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::invalid_monomorphization_unsupported_element, code = "E0511")] pub(crate) struct InvalidMonomorphizationUnsupportedElement<'a> { #[primary_span] @@ -87,7 +87,7 @@ pub(crate) struct InvalidMonomorphizationUnsupportedElement<'a> { pub ret_ty: Ty<'a>, } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::invalid_monomorphization_invalid_bitmask, code = "E0511")] pub(crate) struct InvalidMonomorphizationInvalidBitmask<'a> { #[primary_span] @@ -98,7 +98,7 @@ pub(crate) struct InvalidMonomorphizationInvalidBitmask<'a> { pub expected_bytes: u64, } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::invalid_monomorphization_simd_shuffle, code = "E0511")] pub(crate) struct InvalidMonomorphizationSimdShuffle<'a> { #[primary_span] @@ -107,7 +107,7 @@ pub(crate) struct InvalidMonomorphizationSimdShuffle<'a> { pub ty: Ty<'a>, } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::invalid_monomorphization_expected_simd, code = "E0511")] pub(crate) struct InvalidMonomorphizationExpectedSimd<'a> { #[primary_span] @@ -117,7 +117,7 @@ pub(crate) struct InvalidMonomorphizationExpectedSimd<'a> { pub found_ty: Ty<'a>, } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::invalid_monomorphization_mask_type, code = "E0511")] pub(crate) struct InvalidMonomorphizationMaskType<'a> { #[primary_span] @@ -126,7 +126,7 @@ pub(crate) struct InvalidMonomorphizationMaskType<'a> { pub ty: Ty<'a>, } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::invalid_monomorphization_return_length, code = "E0511")] pub(crate) struct InvalidMonomorphizationReturnLength<'a> { #[primary_span] @@ -137,7 +137,7 @@ pub(crate) struct InvalidMonomorphizationReturnLength<'a> { pub out_len: u64, } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::invalid_monomorphization_return_length_input_type, code = "E0511")] pub(crate) struct InvalidMonomorphizationReturnLengthInputType<'a> { #[primary_span] @@ -149,7 +149,7 @@ pub(crate) struct InvalidMonomorphizationReturnLengthInputType<'a> { pub out_len: u64, } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::invalid_monomorphization_return_element, code = "E0511")] pub(crate) struct InvalidMonomorphizationReturnElement<'a> { #[primary_span] @@ -161,7 +161,7 @@ pub(crate) struct InvalidMonomorphizationReturnElement<'a> { pub out_ty: Ty<'a>, } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::invalid_monomorphization_return_type, code = "E0511")] pub(crate) struct InvalidMonomorphizationReturnType<'a> { #[primary_span] @@ -172,7 +172,7 @@ pub(crate) struct InvalidMonomorphizationReturnType<'a> { pub ret_ty: Ty<'a>, } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::invalid_monomorphization_inserted_type, code = "E0511")] pub(crate) struct InvalidMonomorphizationInsertedType<'a> { #[primary_span] @@ -183,7 +183,7 @@ pub(crate) struct InvalidMonomorphizationInsertedType<'a> { pub out_ty: Ty<'a>, } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::invalid_monomorphization_return_integer_type, code = "E0511")] pub(crate) struct InvalidMonomorphizationReturnIntegerType<'a> { #[primary_span] @@ -193,7 +193,7 @@ pub(crate) struct InvalidMonomorphizationReturnIntegerType<'a> { pub out_ty: Ty<'a>, } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::invalid_monomorphization_mismatched_lengths, code = "E0511")] pub(crate) struct InvalidMonomorphizationMismatchedLengths { #[primary_span] @@ -203,7 +203,7 @@ pub(crate) struct InvalidMonomorphizationMismatchedLengths { pub v_len: u64, } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::invalid_monomorphization_unsupported_cast, code = "E0511")] pub(crate) struct InvalidMonomorphizationUnsupportedCast<'a> { #[primary_span] @@ -215,7 +215,7 @@ pub(crate) struct InvalidMonomorphizationUnsupportedCast<'a> { pub out_elem: Ty<'a>, } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::invalid_monomorphization_unsupported_operation, code = "E0511")] pub(crate) struct InvalidMonomorphizationUnsupportedOperation<'a> { #[primary_span] @@ -225,7 +225,7 @@ pub(crate) struct InvalidMonomorphizationUnsupportedOperation<'a> { pub in_elem: Ty<'a>, } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::layout_size_overflow)] pub(crate) struct LayoutSizeOverflow { #[primary_span] @@ -233,18 +233,18 @@ pub(crate) struct LayoutSizeOverflow { pub error: String, } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::linkage_const_or_mut_type)] pub(crate) struct LinkageConstOrMutType { #[primary_span] pub span: Span } -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::lto_not_supported)] pub(crate) struct LTONotSupported; -#[derive(SessionDiagnostic)] +#[derive(Diagnostic)] #[diag(codegen_gcc::unwinding_inline_asm)] pub(crate) struct UnwindingInlineAsm { #[primary_span] From 925b11ece042a545f848eabc3d990d461a890978 Mon Sep 17 00:00:00 2001 From: Ellis Hoag Date: Sat, 24 Sep 2022 11:36:16 -0700 Subject: [PATCH 259/356] fix lifetime error --- src/context.rs | 24 +++--------------------- src/errors.rs | 8 -------- 2 files changed, 3 insertions(+), 29 deletions(-) diff --git a/src/context.rs b/src/context.rs index 5341d0f75a66..ec3c3a972503 100644 --- a/src/context.rs +++ b/src/context.rs @@ -19,7 +19,6 @@ use rustc_target::abi::{call::FnAbi, HasDataLayout, PointeeInfo, Size, TargetDat use rustc_target::spec::{HasTargetSpec, Target, TlsModel}; use crate::callee::get_fn; -use crate::errors::LayoutSizeOverflow; #[derive(Clone)] pub struct FuncSig<'gcc> { @@ -299,7 +298,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { self.is_native_int_type(typ) || self.is_non_native_int_type(typ) || typ.is_compatible_with(self.bool_type) } - pub fn sess(&self) -> &Session { + pub fn sess(&self) -> &'tcx Session { &self.tcx.sess } @@ -493,24 +492,7 @@ impl<'gcc, 'tcx> LayoutOfHelpers<'tcx> for CodegenCx<'gcc, 'tcx> { #[inline] fn handle_layout_err(&self, err: LayoutError<'tcx>, span: Span, ty: Ty<'tcx>) -> ! { if let LayoutError::SizeOverflow(_) = err { - let _ = respan(span, err); - // error: lifetime may not live long enough - // --> src/context.rs:483:13 - // | - // 475 | impl<'gcc, 'tcx> LayoutOfHelpers<'tcx> for CodegenCx<'gcc, 'tcx> { - // | ---- ---- lifetime `'tcx` defined here - // | | - // | lifetime `'gcc` defined here - // ... - // 483 | self.sess().emit_fatal(respan(span, err)) - // | ^^^^^^^^^^^ argument requires that `'gcc` must outlive `'tcx` - // | - // = help: consider adding the following bound: `'gcc: 'tcx` - // = note: requirement occurs because of the type `CodegenCx<'_, '_>`, which makes the generic argument `'_` invariant - // = note: the struct `CodegenCx<'gcc, 'tcx>` is invariant over the parameter `'gcc` - // = help: see for more information about variance - // self.sess().emit_fatal(respan(span, err)) - self.sess().emit_fatal(LayoutSizeOverflow { span, error: err.to_string() }) + self.sess().emit_fatal(respan(span, err)) } else { span_bug!(span, "failed to get layout for `{}`: {}", ty, err) } @@ -528,7 +510,7 @@ impl<'gcc, 'tcx> FnAbiOfHelpers<'tcx> for CodegenCx<'gcc, 'tcx> { fn_abi_request: FnAbiRequest<'tcx>, ) -> ! { if let FnAbiError::Layout(LayoutError::SizeOverflow(_)) = err { - self.sess().emit_fatal(LayoutSizeOverflow { span, error: err.to_string() }) + self.sess().emit_fatal(respan(span, err)) } else { match fn_abi_request { FnAbiRequest::OfFnPtr { sig, extra_args } => { diff --git a/src/errors.rs b/src/errors.rs index a1c95e7a7f45..eb8528104fac 100644 --- a/src/errors.rs +++ b/src/errors.rs @@ -225,14 +225,6 @@ pub(crate) struct InvalidMonomorphizationUnsupportedOperation<'a> { pub in_elem: Ty<'a>, } -#[derive(Diagnostic)] -#[diag(codegen_gcc::layout_size_overflow)] -pub(crate) struct LayoutSizeOverflow { - #[primary_span] - pub span: Span, - pub error: String, -} - #[derive(Diagnostic)] #[diag(codegen_gcc::linkage_const_or_mut_type)] pub(crate) struct LinkageConstOrMutType { From 70aeb9e2b316829398940194d949a1130842e9cc Mon Sep 17 00:00:00 2001 From: Ellis Hoag Date: Sat, 24 Sep 2022 15:03:14 -0700 Subject: [PATCH 260/356] remove comment --- src/intrinsic/simd.rs | 1 - 1 file changed, 1 deletion(-) diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index f95db2271b33..ff75543ecd1e 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -387,7 +387,6 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, 32 => ("f", elem_ty), 64 => ("", elem_ty), _ => { - // Can we pass elem_ty directly? return_error!(InvalidMonomorphizationInvalidFloatVector { span, name, elem_ty: f.name_str(), vec_ty: in_ty }); } } From 9c67dcfe423cb08873a3c9cde1190ed9a607381a Mon Sep 17 00:00:00 2001 From: Ellis Hoag Date: Mon, 26 Sep 2022 19:57:40 -0700 Subject: [PATCH 261/356] lint and remove unused diagnostic --- src/errors.rs | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/errors.rs b/src/errors.rs index eb8528104fac..83f4af16612e 100644 --- a/src/errors.rs +++ b/src/errors.rs @@ -4,13 +4,12 @@ use rustc_middle::ty::Ty; use rustc_span::{Span, Symbol}; use std::borrow::Cow; -struct ExitCode { - pub exit_code: Option, -} +struct ExitCode(Option); impl IntoDiagnosticArg for ExitCode { fn into_diagnostic_arg(self) -> DiagnosticArgValue<'static> { - match self.exit_code { + let ExitCode(exit_code) = self; + match exit_code { Some(t) => t.into_diagnostic_arg(), None => DiagnosticArgValue::Str(Cow::Borrowed("None")), } @@ -25,8 +24,7 @@ pub(crate) struct RanlibFailure { impl RanlibFailure { pub fn new(exit_code: Option) -> Self { - let exit_code = ExitCode{ exit_code }; - RanlibFailure { exit_code } + RanlibFailure { exit_code: ExitCode(exit_code) } } } From 5c30c25f07d1144ff1945e4ef1ee56aefd53bc9d Mon Sep 17 00:00:00 2001 From: Ellis Hoag Date: Wed, 28 Sep 2022 19:02:38 -0700 Subject: [PATCH 262/356] print when ranlib failed without an exit code --- src/errors.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/errors.rs b/src/errors.rs index 83f4af16612e..d7816e395c8e 100644 --- a/src/errors.rs +++ b/src/errors.rs @@ -11,7 +11,7 @@ impl IntoDiagnosticArg for ExitCode { let ExitCode(exit_code) = self; match exit_code { Some(t) => t.into_diagnostic_arg(), - None => DiagnosticArgValue::Str(Cow::Borrowed("None")), + None => DiagnosticArgValue::Str(Cow::Borrowed("")), } } } From 5943166b299ba66d26fa343b06d72b567e82ce1b Mon Sep 17 00:00:00 2001 From: bjorn3 <17426603+bjorn3@users.noreply.github.com> Date: Sat, 1 Oct 2022 16:34:45 +0000 Subject: [PATCH 263/356] Remove unused Context assoc type from WriteBackendMethods --- src/lib.rs | 1 - 1 file changed, 1 deletion(-) diff --git a/src/lib.rs b/src/lib.rs index b660029a4af9..3b631e7e18d4 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -212,7 +212,6 @@ impl WriteBackendMethods for GccCodegenBackend { type Module = GccContext; type TargetMachine = (); type ModuleBuffer = ModuleBuffer; - type Context = (); type ThinData = (); type ThinBuffer = ThinBuffer; From 5d5c5f92fbdfb6a513a679f397041f0a92e84e0f Mon Sep 17 00:00:00 2001 From: bjorn3 <17426603+bjorn3@users.noreply.github.com> Date: Sat, 1 Oct 2022 16:45:07 +0000 Subject: [PATCH 264/356] Remove several unused methods from MiscMethods --- src/context.rs | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/src/context.rs b/src/context.rs index ec3c3a972503..a4c63c0be1f9 100644 --- a/src/context.rs +++ b/src/context.rs @@ -431,10 +431,6 @@ impl<'gcc, 'tcx> MiscMethods<'tcx> for CodegenCx<'gcc, 'tcx> { self.codegen_unit } - fn used_statics(&self) -> &RefCell>> { - unimplemented!(); - } - fn set_frame_pointer_type(&self, _llfn: RValue<'gcc>) { // TODO(antoyo) } @@ -443,10 +439,6 @@ impl<'gcc, 'tcx> MiscMethods<'tcx> for CodegenCx<'gcc, 'tcx> { // TODO(antoyo) } - fn create_used_variable(&self) { - unimplemented!(); - } - fn declare_c_main(&self, fn_type: Self::Type) -> Option { if self.get_declared_value("main").is_none() { Some(self.declare_cfn("main", fn_type)) @@ -458,14 +450,6 @@ impl<'gcc, 'tcx> MiscMethods<'tcx> for CodegenCx<'gcc, 'tcx> { None } } - - fn compiler_used_statics(&self) -> &RefCell>> { - unimplemented!() - } - - fn create_compiler_used_variable(&self) { - unimplemented!() - } } impl<'gcc, 'tcx> HasTyCtxt<'tcx> for CodegenCx<'gcc, 'tcx> { From 15b0747049300aca6e90c38b4a25f10cc2f89d29 Mon Sep 17 00:00:00 2001 From: bjorn3 <17426603+bjorn3@users.noreply.github.com> Date: Sat, 1 Oct 2022 16:45:33 +0000 Subject: [PATCH 265/356] Remove unused target_cpu and tune_cpu methods from ExtraBackendMethods --- src/lib.rs | 9 --------- 1 file changed, 9 deletions(-) diff --git a/src/lib.rs b/src/lib.rs index 3b631e7e18d4..0d5272eb0074 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -173,15 +173,6 @@ impl ExtraBackendMethods for GccCodegenBackend { Ok(()) }) } - - fn target_cpu<'b>(&self, _sess: &'b Session) -> &'b str { - unimplemented!(); - } - - fn tune_cpu<'b>(&self, _sess: &'b Session) -> Option<&'b str> { - None - // TODO(antoyo) - } } pub struct ModuleBuffer; From d9933199cd1f85a51c6b9bb732c543419c188161 Mon Sep 17 00:00:00 2001 From: bjorn3 <17426603+bjorn3@users.noreply.github.com> Date: Sat, 1 Oct 2022 17:01:31 +0000 Subject: [PATCH 266/356] Merge apply_attrs_callsite into call and invoke Some codegen backends are not able to apply callsite attrs after the fact. --- src/abi.rs | 4 ---- src/asm.rs | 2 +- src/builder.rs | 24 +++++++++++++++++++----- src/intrinsic/mod.rs | 6 +++--- 4 files changed, 23 insertions(+), 13 deletions(-) diff --git a/src/abi.rs b/src/abi.rs index 848c34211ff6..6fb1cbfad8cd 100644 --- a/src/abi.rs +++ b/src/abi.rs @@ -11,10 +11,6 @@ use crate::intrinsic::ArgAbiExt; use crate::type_of::LayoutGccExt; impl<'a, 'gcc, 'tcx> AbiBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { - fn apply_attrs_callsite(&mut self, _fn_abi: &FnAbi<'tcx, Ty<'tcx>>, _callsite: Self::Value) { - // TODO(antoyo) - } - fn get_param(&mut self, index: usize) -> Self::Value { let func = self.current_func(); let param = func.get_param(index as i32); diff --git a/src/asm.rs b/src/asm.rs index b8ca1c3fd612..41e9d61a10e5 100644 --- a/src/asm.rs +++ b/src/asm.rs @@ -501,7 +501,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { if options.contains(InlineAsmOptions::NORETURN) { let builtin_unreachable = self.context.get_builtin_function("__builtin_unreachable"); let builtin_unreachable: RValue<'gcc> = unsafe { std::mem::transmute(builtin_unreachable) }; - self.call(self.type_void(), builtin_unreachable, &[], None); + self.call(self.type_void(), None, builtin_unreachable, &[], None); } // Write results to outputs. diff --git a/src/builder.rs b/src/builder.rs index a560539d6e1e..9cf2d6519015 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -455,7 +455,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } #[cfg(feature="master")] - fn invoke(&mut self, typ: Type<'gcc>, func: RValue<'gcc>, args: &[RValue<'gcc>], then: Block<'gcc>, catch: Block<'gcc>, _funclet: Option<&Funclet>) -> RValue<'gcc> { + fn invoke(&mut self, typ: Type<'gcc>, fn_abi: Option<&FnAbi<'tcx, Ty<'tcx>>>, func: RValue<'gcc>, args: &[RValue<'gcc>], then: Block<'gcc>, catch: Block<'gcc>, _funclet: Option<&Funclet>) -> RValue<'gcc> { let try_block = self.current_func().new_block("try"); let current_block = self.block.clone(); @@ -483,10 +483,13 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } #[cfg(not(feature="master"))] - fn invoke(&mut self, typ: Type<'gcc>, func: RValue<'gcc>, args: &[RValue<'gcc>], then: Block<'gcc>, catch: Block<'gcc>, _funclet: Option<&Funclet>) -> RValue<'gcc> { - let call_site = self.call(typ, func, args, None); + fn invoke(&mut self, typ: Type<'gcc>, fn_abi: Option<&FnAbi<'tcx, Ty<'tcx>>>, func: RValue<'gcc>, args: &[RValue<'gcc>], then: Block<'gcc>, catch: Block<'gcc>, _funclet: Option<&Funclet>) -> RValue<'gcc> { + let call_site = self.call(typ, None, func, args, None); let condition = self.context.new_rvalue_from_int(self.bool_type, 1); self.llbb().end_with_conditional(None, condition, then, catch); + if let Some(_fn_abi) = fn_abi { + // TODO(bjorn3): Apply function attributes + } call_site } @@ -1359,16 +1362,27 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { // TODO(antoyo) } - fn call(&mut self, _typ: Type<'gcc>, func: RValue<'gcc>, args: &[RValue<'gcc>], funclet: Option<&Funclet>) -> RValue<'gcc> { + fn call( + &mut self, + _typ: Type<'gcc>, + fn_abi: Option<&FnAbi<'tcx, Ty<'tcx>>>, + func: RValue<'gcc>, + args: &[RValue<'gcc>], + funclet: Option<&Funclet>, + ) -> RValue<'gcc> { // FIXME(antoyo): remove when having a proper API. let gcc_func = unsafe { std::mem::transmute(func) }; - if self.functions.borrow().values().find(|value| **value == gcc_func).is_some() { + let call = if self.functions.borrow().values().find(|value| **value == gcc_func).is_some() { self.function_call(func, args, funclet) } else { // If it's a not function that was defined, it's a function pointer. self.function_ptr_call(func, args, funclet) + }; + if let Some(_fn_abi) = fn_abi { + // TODO(bjorn3): Apply function attributes } + call } fn zext(&mut self, value: RValue<'gcc>, dest_typ: Type<'gcc>) -> RValue<'gcc> { diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index bdeede2ab5e6..b58381871a9c 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -111,7 +111,7 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { _ if simple.is_some() => { // FIXME(antoyo): remove this cast when the API supports function. let func = unsafe { std::mem::transmute(simple.expect("simple")) }; - self.call(self.type_void(), func, &args.iter().map(|arg| arg.immediate()).collect::>(), None) + self.call(self.type_void(), None, func, &args.iter().map(|arg| arg.immediate()).collect::>(), None) }, sym::likely => { self.expect(args[0].immediate(), true) @@ -352,7 +352,7 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { fn abort(&mut self) { let func = self.context.get_builtin_function("abort"); let func: RValue<'gcc> = unsafe { std::mem::transmute(func) }; - self.call(self.type_void(), func, &[], None); + self.call(self.type_void(), None, func, &[], None); } fn assume(&mut self, value: Self::Value) { @@ -1133,7 +1133,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { fn try_intrinsic<'a, 'b, 'gcc, 'tcx>(bx: &'b mut Builder<'a, 'gcc, 'tcx>, try_func: RValue<'gcc>, data: RValue<'gcc>, _catch_func: RValue<'gcc>, dest: RValue<'gcc>) { if bx.sess().panic_strategy() == PanicStrategy::Abort { - bx.call(bx.type_void(), try_func, &[data], None); + bx.call(bx.type_void(), None, try_func, &[data], None); // Return 0 unconditionally from the intrinsic call; // we can never unwind. let ret_align = bx.tcx.data_layout.i32_align.abi; From b909493151dbe517c9c897eb81de3346e0d451f9 Mon Sep 17 00:00:00 2001 From: bjorn3 <17426603+bjorn3@users.noreply.github.com> Date: Sat, 1 Oct 2022 17:34:21 +0000 Subject: [PATCH 267/356] Remove dynamic_alloca from BuilderMethods --- src/builder.rs | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index 9cf2d6519015..e3d4462cb2b5 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -714,10 +714,6 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { self.current_func().new_local(None, aligned_type, &format!("stack_var_{}", self.stack_var_count.get())).get_address(None) } - fn dynamic_alloca(&mut self, _ty: Type<'gcc>, _align: Align) -> RValue<'gcc> { - unimplemented!(); - } - fn array_alloca(&mut self, _ty: Type<'gcc>, _len: RValue<'gcc>, _align: Align) -> RValue<'gcc> { unimplemented!(); } From 4310bbdfa6bdd2fa5ebbd9cd32c850ee12bcd0a2 Mon Sep 17 00:00:00 2001 From: bjorn3 <17426603+bjorn3@users.noreply.github.com> Date: Sat, 1 Oct 2022 18:22:46 +0000 Subject: [PATCH 268/356] Remove type argument of array_alloca and rename to byte_array_alloca --- src/builder.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/builder.rs b/src/builder.rs index e3d4462cb2b5..c43895ee5650 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -714,7 +714,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { self.current_func().new_local(None, aligned_type, &format!("stack_var_{}", self.stack_var_count.get())).get_address(None) } - fn array_alloca(&mut self, _ty: Type<'gcc>, _len: RValue<'gcc>, _align: Align) -> RValue<'gcc> { + fn byte_array_alloca(&mut self, _len: RValue<'gcc>, _align: Align) -> RValue<'gcc> { unimplemented!(); } From affe23bc3bf80ab00e3b32fea628846455028f48 Mon Sep 17 00:00:00 2001 From: Amanieu d'Antras Date: Mon, 17 Oct 2022 22:38:37 +0100 Subject: [PATCH 269/356] Stabilize asm_sym --- tests/run/asm.rs | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/tests/run/asm.rs b/tests/run/asm.rs index 46abbb553bf2..38c1eac7adf6 100644 --- a/tests/run/asm.rs +++ b/tests/run/asm.rs @@ -3,11 +3,12 @@ // Run-time: // status: 0 -#![feature(asm_const, asm_sym)] +#![feature(asm_const)] use std::arch::{asm, global_asm}; -global_asm!(" +global_asm!( + " .global add_asm add_asm: mov rax, rdi @@ -132,7 +133,9 @@ fn main() { assert_eq!(x, 43); // check sym fn - extern "C" fn foo() -> u64 { 42 } + extern "C" fn foo() -> u64 { + 42 + } let x: u64; unsafe { asm!("call {}", sym foo, lateout("rax") x); From dbe3df3d84450403802f036bbb7bb17bf7841937 Mon Sep 17 00:00:00 2001 From: Nilstrieb <48135649+Nilstrieb@users.noreply.github.com> Date: Sat, 22 Oct 2022 11:07:54 +0200 Subject: [PATCH 270/356] Migrate all diagnostics --- src/errors.rs | 46 +++++++++++++++++++++++----------------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/src/errors.rs b/src/errors.rs index d7816e395c8e..15ad90f9043c 100644 --- a/src/errors.rs +++ b/src/errors.rs @@ -17,7 +17,7 @@ impl IntoDiagnosticArg for ExitCode { } #[derive(Diagnostic)] -#[diag(codegen_gcc::ranlib_failure)] +#[diag(codegen_gcc_ranlib_failure)] pub(crate) struct RanlibFailure { exit_code: ExitCode, } @@ -29,7 +29,7 @@ impl RanlibFailure { } #[derive(Diagnostic)] -#[diag(codegen_gcc::invalid_monomorphization_basic_integer, code = "E0511")] +#[diag(codegen_gcc_invalid_monomorphization_basic_integer, code = "E0511")] pub(crate) struct InvalidMonomorphizationBasicInteger<'a> { #[primary_span] pub span: Span, @@ -38,7 +38,7 @@ pub(crate) struct InvalidMonomorphizationBasicInteger<'a> { } #[derive(Diagnostic)] -#[diag(codegen_gcc::invalid_monomorphization_invalid_float_vector, code = "E0511")] +#[diag(codegen_gcc_invalid_monomorphization_invalid_float_vector, code = "E0511")] pub(crate) struct InvalidMonomorphizationInvalidFloatVector<'a> { #[primary_span] pub span: Span, @@ -48,7 +48,7 @@ pub(crate) struct InvalidMonomorphizationInvalidFloatVector<'a> { } #[derive(Diagnostic)] -#[diag(codegen_gcc::invalid_monomorphization_not_float, code = "E0511")] +#[diag(codegen_gcc_invalid_monomorphization_not_float, code = "E0511")] pub(crate) struct InvalidMonomorphizationNotFloat<'a> { #[primary_span] pub span: Span, @@ -57,7 +57,7 @@ pub(crate) struct InvalidMonomorphizationNotFloat<'a> { } #[derive(Diagnostic)] -#[diag(codegen_gcc::invalid_monomorphization_unrecognized, code = "E0511")] +#[diag(codegen_gcc_invalid_monomorphization_unrecognized, code = "E0511")] pub(crate) struct InvalidMonomorphizationUnrecognized { #[primary_span] pub span: Span, @@ -65,7 +65,7 @@ pub(crate) struct InvalidMonomorphizationUnrecognized { } #[derive(Diagnostic)] -#[diag(codegen_gcc::invalid_monomorphization_expected_signed_unsigned, code = "E0511")] +#[diag(codegen_gcc_invalid_monomorphization_expected_signed_unsigned, code = "E0511")] pub(crate) struct InvalidMonomorphizationExpectedSignedUnsigned<'a> { #[primary_span] pub span: Span, @@ -75,7 +75,7 @@ pub(crate) struct InvalidMonomorphizationExpectedSignedUnsigned<'a> { } #[derive(Diagnostic)] -#[diag(codegen_gcc::invalid_monomorphization_unsupported_element, code = "E0511")] +#[diag(codegen_gcc_invalid_monomorphization_unsupported_element, code = "E0511")] pub(crate) struct InvalidMonomorphizationUnsupportedElement<'a> { #[primary_span] pub span: Span, @@ -86,7 +86,7 @@ pub(crate) struct InvalidMonomorphizationUnsupportedElement<'a> { } #[derive(Diagnostic)] -#[diag(codegen_gcc::invalid_monomorphization_invalid_bitmask, code = "E0511")] +#[diag(codegen_gcc_invalid_monomorphization_invalid_bitmask, code = "E0511")] pub(crate) struct InvalidMonomorphizationInvalidBitmask<'a> { #[primary_span] pub span: Span, @@ -97,7 +97,7 @@ pub(crate) struct InvalidMonomorphizationInvalidBitmask<'a> { } #[derive(Diagnostic)] -#[diag(codegen_gcc::invalid_monomorphization_simd_shuffle, code = "E0511")] +#[diag(codegen_gcc_invalid_monomorphization_simd_shuffle, code = "E0511")] pub(crate) struct InvalidMonomorphizationSimdShuffle<'a> { #[primary_span] pub span: Span, @@ -106,7 +106,7 @@ pub(crate) struct InvalidMonomorphizationSimdShuffle<'a> { } #[derive(Diagnostic)] -#[diag(codegen_gcc::invalid_monomorphization_expected_simd, code = "E0511")] +#[diag(codegen_gcc_invalid_monomorphization_expected_simd, code = "E0511")] pub(crate) struct InvalidMonomorphizationExpectedSimd<'a> { #[primary_span] pub span: Span, @@ -116,7 +116,7 @@ pub(crate) struct InvalidMonomorphizationExpectedSimd<'a> { } #[derive(Diagnostic)] -#[diag(codegen_gcc::invalid_monomorphization_mask_type, code = "E0511")] +#[diag(codegen_gcc_invalid_monomorphization_mask_type, code = "E0511")] pub(crate) struct InvalidMonomorphizationMaskType<'a> { #[primary_span] pub span: Span, @@ -125,7 +125,7 @@ pub(crate) struct InvalidMonomorphizationMaskType<'a> { } #[derive(Diagnostic)] -#[diag(codegen_gcc::invalid_monomorphization_return_length, code = "E0511")] +#[diag(codegen_gcc_invalid_monomorphization_return_length, code = "E0511")] pub(crate) struct InvalidMonomorphizationReturnLength<'a> { #[primary_span] pub span: Span, @@ -136,7 +136,7 @@ pub(crate) struct InvalidMonomorphizationReturnLength<'a> { } #[derive(Diagnostic)] -#[diag(codegen_gcc::invalid_monomorphization_return_length_input_type, code = "E0511")] +#[diag(codegen_gcc_invalid_monomorphization_return_length_input_type, code = "E0511")] pub(crate) struct InvalidMonomorphizationReturnLengthInputType<'a> { #[primary_span] pub span: Span, @@ -148,7 +148,7 @@ pub(crate) struct InvalidMonomorphizationReturnLengthInputType<'a> { } #[derive(Diagnostic)] -#[diag(codegen_gcc::invalid_monomorphization_return_element, code = "E0511")] +#[diag(codegen_gcc_invalid_monomorphization_return_element, code = "E0511")] pub(crate) struct InvalidMonomorphizationReturnElement<'a> { #[primary_span] pub span: Span, @@ -160,7 +160,7 @@ pub(crate) struct InvalidMonomorphizationReturnElement<'a> { } #[derive(Diagnostic)] -#[diag(codegen_gcc::invalid_monomorphization_return_type, code = "E0511")] +#[diag(codegen_gcc_invalid_monomorphization_return_type, code = "E0511")] pub(crate) struct InvalidMonomorphizationReturnType<'a> { #[primary_span] pub span: Span, @@ -171,7 +171,7 @@ pub(crate) struct InvalidMonomorphizationReturnType<'a> { } #[derive(Diagnostic)] -#[diag(codegen_gcc::invalid_monomorphization_inserted_type, code = "E0511")] +#[diag(codegen_gcc_invalid_monomorphization_inserted_type, code = "E0511")] pub(crate) struct InvalidMonomorphizationInsertedType<'a> { #[primary_span] pub span: Span, @@ -182,7 +182,7 @@ pub(crate) struct InvalidMonomorphizationInsertedType<'a> { } #[derive(Diagnostic)] -#[diag(codegen_gcc::invalid_monomorphization_return_integer_type, code = "E0511")] +#[diag(codegen_gcc_invalid_monomorphization_return_integer_type, code = "E0511")] pub(crate) struct InvalidMonomorphizationReturnIntegerType<'a> { #[primary_span] pub span: Span, @@ -192,7 +192,7 @@ pub(crate) struct InvalidMonomorphizationReturnIntegerType<'a> { } #[derive(Diagnostic)] -#[diag(codegen_gcc::invalid_monomorphization_mismatched_lengths, code = "E0511")] +#[diag(codegen_gcc_invalid_monomorphization_mismatched_lengths, code = "E0511")] pub(crate) struct InvalidMonomorphizationMismatchedLengths { #[primary_span] pub span: Span, @@ -202,7 +202,7 @@ pub(crate) struct InvalidMonomorphizationMismatchedLengths { } #[derive(Diagnostic)] -#[diag(codegen_gcc::invalid_monomorphization_unsupported_cast, code = "E0511")] +#[diag(codegen_gcc_invalid_monomorphization_unsupported_cast, code = "E0511")] pub(crate) struct InvalidMonomorphizationUnsupportedCast<'a> { #[primary_span] pub span: Span, @@ -214,7 +214,7 @@ pub(crate) struct InvalidMonomorphizationUnsupportedCast<'a> { } #[derive(Diagnostic)] -#[diag(codegen_gcc::invalid_monomorphization_unsupported_operation, code = "E0511")] +#[diag(codegen_gcc_invalid_monomorphization_unsupported_operation, code = "E0511")] pub(crate) struct InvalidMonomorphizationUnsupportedOperation<'a> { #[primary_span] pub span: Span, @@ -224,18 +224,18 @@ pub(crate) struct InvalidMonomorphizationUnsupportedOperation<'a> { } #[derive(Diagnostic)] -#[diag(codegen_gcc::linkage_const_or_mut_type)] +#[diag(codegen_gcc_linkage_const_or_mut_type)] pub(crate) struct LinkageConstOrMutType { #[primary_span] pub span: Span } #[derive(Diagnostic)] -#[diag(codegen_gcc::lto_not_supported)] +#[diag(codegen_gcc_lto_not_supported)] pub(crate) struct LTONotSupported; #[derive(Diagnostic)] -#[diag(codegen_gcc::unwinding_inline_asm)] +#[diag(codegen_gcc_unwinding_inline_asm)] pub(crate) struct UnwindingInlineAsm { #[primary_span] pub span: Span From 4c0a6e610e5ff15cc1a8c0e4d731083405b5da87 Mon Sep 17 00:00:00 2001 From: Daniel Paoliello Date: Wed, 12 Oct 2022 14:44:01 -0700 Subject: [PATCH 271/356] Support raw-dylib functions being used inside inlined functions --- src/archive.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/src/archive.rs b/src/archive.rs index ac0342f6b80a..f18ae7ea5e9b 100644 --- a/src/archive.rs +++ b/src/archive.rs @@ -47,6 +47,7 @@ impl ArchiveBuilderBuilder for ArArchiveBuilderBuilder { _lib_name: &str, _dll_imports: &[DllImport], _tmpdir: &Path, + _is_direct_dependency: bool, ) -> PathBuf { unimplemented!(); } From dd930a3b5cff68646f1fd4eff7256a9a25302ceb Mon Sep 17 00:00:00 2001 From: Amanieu d'Antras Date: Fri, 14 Oct 2022 02:24:58 +0100 Subject: [PATCH 272/356] Rewrite implementation of `#[alloc_error_handler]` The new implementation doesn't use weak lang items and instead changes `#[alloc_error_handler]` to an attribute macro just like `#[global_allocator]`. The attribute will generate the `__rg_oom` function which is called by the compiler-generated `__rust_alloc_error_handler`. If no `__rg_oom` function is defined in any crate then the compiler shim will call `__rdl_oom` in the alloc crate which will simply panic. This also fixes link errors with `-C link-dead-code` with `default_alloc_error_handler`: `__rg_oom` was previously defined in the alloc crate and would attempt to reference the `oom` lang item, even if it didn't exist. This worked as long as `__rg_oom` was excluded from linking since it was not called. This is a prerequisite for the stabilization of `default_alloc_error_handler` (#102318). --- src/allocator.rs | 11 ++--------- src/lib.rs | 4 ++-- 2 files changed, 4 insertions(+), 11 deletions(-) diff --git a/src/allocator.rs b/src/allocator.rs index 11482c69d594..4bad33ee879e 100644 --- a/src/allocator.rs +++ b/src/allocator.rs @@ -9,7 +9,7 @@ use rustc_span::symbol::sym; use crate::GccContext; -pub(crate) unsafe fn codegen(tcx: TyCtxt<'_>, mods: &mut GccContext, _module_name: &str, kind: AllocatorKind, has_alloc_error_handler: bool) { +pub(crate) unsafe fn codegen(tcx: TyCtxt<'_>, mods: &mut GccContext, _module_name: &str, kind: AllocatorKind, alloc_error_handler_kind: AllocatorKind) { let context = &mods.context; let usize = match tcx.sess.target.pointer_width { @@ -99,14 +99,7 @@ pub(crate) unsafe fn codegen(tcx: TyCtxt<'_>, mods: &mut GccContext, _module_nam func.add_attribute(FnAttribute::Visibility(gccjit::Visibility::Hidden)); } - let kind = - if has_alloc_error_handler { - AllocatorKind::Global - } - else { - AllocatorKind::Default - }; - let callee = kind.fn_name(sym::oom); + let callee = alloc_error_handler_kind.fn_name(sym::oom); let args: Vec<_> = types.iter().enumerate() .map(|(index, typ)| context.new_parameter(None, *typ, &format!("param{}", index))) .collect(); diff --git a/src/lib.rs b/src/lib.rs index 0d5272eb0074..1261eb4aaa4a 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -155,11 +155,11 @@ impl CodegenBackend for GccCodegenBackend { } impl ExtraBackendMethods for GccCodegenBackend { - fn codegen_allocator<'tcx>(&self, tcx: TyCtxt<'tcx>, module_name: &str, kind: AllocatorKind, has_alloc_error_handler: bool) -> Self::Module { + fn codegen_allocator<'tcx>(&self, tcx: TyCtxt<'tcx>, module_name: &str, kind: AllocatorKind, alloc_error_handler_kind: AllocatorKind) -> Self::Module { let mut mods = GccContext { context: Context::default(), }; - unsafe { allocator::codegen(tcx, &mut mods, module_name, kind, has_alloc_error_handler); } + unsafe { allocator::codegen(tcx, &mut mods, module_name, kind, alloc_error_handler_kind); } mods } From a8978641504ba90aaaa41b2acb72578ea7bb328c Mon Sep 17 00:00:00 2001 From: Ayush Singh Date: Sun, 6 Nov 2022 14:01:46 +0530 Subject: [PATCH 273/356] Add type_array to BaseTypeMethods Moved type_array function to rustc_codegen_ssa::BaseTypeMethods trait. This allows using normal alloca function to create arrays as suggested in https://github.com/rust-lang/rust/pull/104022. Signed-off-by: Ayush Singh --- src/type_.rs | 42 +++++++++++++++++++++++------------------- 1 file changed, 23 insertions(+), 19 deletions(-) diff --git a/src/type_.rs b/src/type_.rs index d7eca2a33df7..58d4f2900600 100644 --- a/src/type_.rs +++ b/src/type_.rs @@ -201,6 +201,27 @@ impl<'gcc, 'tcx> BaseTypeMethods<'tcx> for CodegenCx<'gcc, 'tcx> { fn val_ty(&self, value: RValue<'gcc>) -> Type<'gcc> { value.get_type() } + + fn type_array(&self, ty: Type<'gcc>, mut len: u64) -> Type<'gcc> { + if let Some(struct_type) = ty.is_struct() { + if struct_type.get_field_count() == 0 { + // NOTE: since gccjit only supports i32 for the array size and libcore's tests uses a + // size of usize::MAX in test_binary_search, we workaround this by setting the size to + // zero for ZSTs. + // FIXME(antoyo): fix gccjit API. + len = 0; + } + } + + // NOTE: see note above. Some other test uses usize::MAX. + if len == u64::MAX { + len = 0; + } + + let len: i32 = len.try_into().expect("array len"); + + self.context.new_array_type(None, ty, len) + } } impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { @@ -227,25 +248,8 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { self.context.new_opaque_struct_type(None, name) } - pub fn type_array(&self, ty: Type<'gcc>, mut len: u64) -> Type<'gcc> { - if let Some(struct_type) = ty.is_struct() { - if struct_type.get_field_count() == 0 { - // NOTE: since gccjit only supports i32 for the array size and libcore's tests uses a - // size of usize::MAX in test_binary_search, we workaround this by setting the size to - // zero for ZSTs. - // FIXME(antoyo): fix gccjit API. - len = 0; - } - } - - // NOTE: see note above. Some other test uses usize::MAX. - if len == u64::MAX { - len = 0; - } - - let len: i32 = len.try_into().expect("array len"); - - self.context.new_array_type(None, ty, len) + pub fn type_bool(&self) -> Type<'gcc> { + self.context.new_type::() } } From fb747d0e24a38422d7b7f6b9372dd2ecfe6f408f Mon Sep 17 00:00:00 2001 From: Ralf Jung Date: Sun, 13 Nov 2022 12:14:59 +0100 Subject: [PATCH 274/356] add is_sized method on Abi and Layout, and use it --- src/type_.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/type_.rs b/src/type_.rs index 58d4f2900600..55e4d0c6289a 100644 --- a/src/type_.rs +++ b/src/type_.rs @@ -277,7 +277,7 @@ pub fn struct_fields<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, layout: TyAndLayout offset = target_offset + field.size; prev_effective_align = effective_field_align; } - if !layout.is_unsized() && field_count > 0 { + if layout.is_sized() && field_count > 0 { if offset > layout.size { bug!("layout: {:#?} stride: {:?} offset: {:?}", layout, layout.size, offset); } From 5378b465f0fcb3c675950157cfc17c1ebf58295c Mon Sep 17 00:00:00 2001 From: Ralf Jung Date: Sun, 6 Nov 2022 14:15:20 +0100 Subject: [PATCH 275/356] fix cranelift and gcc --- src/consts.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/consts.rs b/src/consts.rs index be50850d82fc..7ffb345df9b6 100644 --- a/src/consts.rs +++ b/src/consts.rs @@ -279,12 +279,12 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { pub fn const_alloc_to_gcc<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, alloc: ConstAllocation<'tcx>) -> RValue<'gcc> { let alloc = alloc.inner(); - let mut llvals = Vec::with_capacity(alloc.provenance().len() + 1); + let mut llvals = Vec::with_capacity(alloc.provenance().ptrs().len() + 1); let dl = cx.data_layout(); let pointer_size = dl.pointer_size.bytes() as usize; let mut next_offset = 0; - for &(offset, alloc_id) in alloc.provenance().iter() { + for &(offset, alloc_id) in alloc.provenance().ptrs().iter() { let offset = offset.bytes(); assert_eq!(offset as usize as u64, offset); let offset = offset as usize; From 4cbf5e6813d7c194aa9d2525a027b86e52e07f2f Mon Sep 17 00:00:00 2001 From: Camille GILLOT Date: Sat, 1 Oct 2022 23:10:36 +0200 Subject: [PATCH 276/356] Introduce composite debuginfo. --- src/debuginfo.rs | 57 +++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 49 insertions(+), 8 deletions(-) diff --git a/src/debuginfo.rs b/src/debuginfo.rs index 266759ed6cfa..a81585d41284 100644 --- a/src/debuginfo.rs +++ b/src/debuginfo.rs @@ -4,8 +4,9 @@ use rustc_codegen_ssa::traits::{DebugInfoBuilderMethods, DebugInfoMethods}; use rustc_middle::mir; use rustc_middle::ty::{Instance, PolyExistentialTraitRef, Ty}; use rustc_span::{SourceFile, Span, Symbol}; -use rustc_target::abi::Size; use rustc_target::abi::call::FnAbi; +use rustc_target::abi::Size; +use std::ops::Range; use crate::builder::Builder; use crate::context::CodegenCx; @@ -13,7 +14,15 @@ use crate::context::CodegenCx; impl<'a, 'gcc, 'tcx> DebugInfoBuilderMethods for Builder<'a, 'gcc, 'tcx> { // FIXME(eddyb) find a common convention for all of the debuginfo-related // names (choose between `dbg`, `debug`, `debuginfo`, `debug_info` etc.). - fn dbg_var_addr(&mut self, _dbg_var: Self::DIVariable, _scope_metadata: Self::DIScope, _variable_alloca: Self::Value, _direct_offset: Size, _indirect_offsets: &[Size]) { + fn dbg_var_addr( + &mut self, + _dbg_var: Self::DIVariable, + _scope_metadata: Self::DIScope, + _variable_alloca: Self::Value, + _direct_offset: Size, + _indirect_offsets: &[Size], + _fragment: Option>, + ) { unimplemented!(); } @@ -31,16 +40,31 @@ impl<'a, 'gcc, 'tcx> DebugInfoBuilderMethods for Builder<'a, 'gcc, 'tcx> { } impl<'gcc, 'tcx> DebugInfoMethods<'tcx> for CodegenCx<'gcc, 'tcx> { - fn create_vtable_debuginfo(&self, _ty: Ty<'tcx>, _trait_ref: Option>, _vtable: Self::Value) { + fn create_vtable_debuginfo( + &self, + _ty: Ty<'tcx>, + _trait_ref: Option>, + _vtable: Self::Value, + ) { // TODO(antoyo) } - fn create_function_debug_context(&self, _instance: Instance<'tcx>, _fn_abi: &FnAbi<'tcx, Ty<'tcx>>, _llfn: RValue<'gcc>, _mir: &mir::Body<'tcx>) -> Option> { + fn create_function_debug_context( + &self, + _instance: Instance<'tcx>, + _fn_abi: &FnAbi<'tcx, Ty<'tcx>>, + _llfn: RValue<'gcc>, + _mir: &mir::Body<'tcx>, + ) -> Option> { // TODO(antoyo) None } - fn extend_scope_to_file(&self, _scope_metadata: Self::DIScope, _file: &SourceFile) -> Self::DIScope { + fn extend_scope_to_file( + &self, + _scope_metadata: Self::DIScope, + _file: &SourceFile, + ) -> Self::DIScope { unimplemented!(); } @@ -48,15 +72,32 @@ impl<'gcc, 'tcx> DebugInfoMethods<'tcx> for CodegenCx<'gcc, 'tcx> { // TODO(antoyo) } - fn create_dbg_var(&self, _variable_name: Symbol, _variable_type: Ty<'tcx>, _scope_metadata: Self::DIScope, _variable_kind: VariableKind, _span: Span) -> Self::DIVariable { + fn create_dbg_var( + &self, + _variable_name: Symbol, + _variable_type: Ty<'tcx>, + _scope_metadata: Self::DIScope, + _variable_kind: VariableKind, + _span: Span, + ) -> Self::DIVariable { unimplemented!(); } - fn dbg_scope_fn(&self, _instance: Instance<'tcx>, _fn_abi: &FnAbi<'tcx, Ty<'tcx>>, _maybe_definition_llfn: Option>) -> Self::DIScope { + fn dbg_scope_fn( + &self, + _instance: Instance<'tcx>, + _fn_abi: &FnAbi<'tcx, Ty<'tcx>>, + _maybe_definition_llfn: Option>, + ) -> Self::DIScope { unimplemented!(); } - fn dbg_loc(&self, _scope: Self::DIScope, _inlined_at: Option, _span: Span) -> Self::DILocation { + fn dbg_loc( + &self, + _scope: Self::DIScope, + _inlined_at: Option, + _span: Span, + ) -> Self::DILocation { unimplemented!(); } } From 5b9b849a1918636f55433e858ee6ce4847dd6ced Mon Sep 17 00:00:00 2001 From: Caleb Zulawski Date: Sat, 29 Oct 2022 23:36:47 -0400 Subject: [PATCH 277/356] Allow actual AVX512-related feature names in the case of some misleading aliases --- src/lib.rs | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/lib.rs b/src/lib.rs index 1261eb4aaa4a..0d99f4e2f335 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -320,10 +320,10 @@ pub fn target_features(sess: &Session, allow_unstable: bool) -> Vec { false } /* - adx, aes, avx, avx2, avx512bf16, avx512bitalg, avx512bw, avx512cd, avx512dq, avx512er, avx512f, avx512gfni, - avx512ifma, avx512pf, avx512vaes, avx512vbmi, avx512vbmi2, avx512vl, avx512vnni, avx512vp2intersect, avx512vpclmulqdq, - avx512vpopcntdq, bmi1, bmi2, cmpxchg16b, ermsb, f16c, fma, fxsr, lzcnt, movbe, pclmulqdq, popcnt, rdrand, rdseed, rtm, - sha, sse, sse2, sse3, sse4.1, sse4.2, sse4a, ssse3, tbm, xsave, xsavec, xsaveopt, xsaves + adx, aes, avx, avx2, avx512bf16, avx512bitalg, avx512bw, avx512cd, avx512dq, avx512er, avx512f, avx512ifma, + avx512pf, avx512vbmi, avx512vbmi2, avx512vl, avx512vnni, avx512vp2intersect, avx512vpopcntdq, + bmi1, bmi2, cmpxchg16b, ermsb, f16c, fma, fxsr, gfni, lzcnt, movbe, pclmulqdq, popcnt, rdrand, rdseed, rtm, + sha, sse, sse2, sse3, sse4.1, sse4.2, sse4a, ssse3, tbm, vaes, vpclmulqdq, xsave, xsavec, xsaveopt, xsaves */ //false }) From bf4e1e49ea80d52ec6662938ce859de17fd831f4 Mon Sep 17 00:00:00 2001 From: Nicholas Nethercote Date: Wed, 9 Nov 2022 11:04:10 +1100 Subject: [PATCH 278/356] Use `&mut Bx` more. For the next commit, `FunctionCx::codegen_*_terminator` need to take a `&mut Bx` instead of consuming a `Bx`. This triggers a cascade of similar changes across multiple functions. The resulting code is more concise and replaces many `&mut bx` expressions with `bx`. --- src/builder.rs | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index c43895ee5650..1603e9bf6282 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -814,11 +814,11 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { OperandRef { val, layout: place.layout } } - fn write_operand_repeatedly(mut self, cg_elem: OperandRef<'tcx, RValue<'gcc>>, count: u64, dest: PlaceRef<'tcx, RValue<'gcc>>) -> Self { + fn write_operand_repeatedly(&mut self, cg_elem: OperandRef<'tcx, RValue<'gcc>>, count: u64, dest: PlaceRef<'tcx, RValue<'gcc>>) { let zero = self.const_usize(0); let count = self.const_usize(count); - let start = dest.project_index(&mut self, zero).llval; - let end = dest.project_index(&mut self, count).llval; + let start = dest.project_index(self, zero).llval; + let end = dest.project_index(self, count).llval; let header_bb = self.append_sibling_block("repeat_loop_header"); let body_bb = self.append_sibling_block("repeat_loop_body"); @@ -837,14 +837,13 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { self.switch_to_block(body_bb); let align = dest.align.restrict_for_offset(dest.layout.field(self.cx(), 0).size); - cg_elem.val.store(&mut self, PlaceRef::new_sized_aligned(current_val, cg_elem.layout, align)); + cg_elem.val.store(self, PlaceRef::new_sized_aligned(current_val, cg_elem.layout, align)); let next = self.inbounds_gep(self.backend_type(cg_elem.layout), current.to_rvalue(), &[self.const_usize(1)]); self.llbb().add_assignment(None, current, next); self.br(header_bb); self.switch_to_block(next_bb); - self } fn range_metadata(&mut self, _load: RValue<'gcc>, _range: WrappingRange) { From 21af0df1e5e7f501af1e4864f2d9b9b3fac76924 Mon Sep 17 00:00:00 2001 From: Ayush Singh Date: Tue, 15 Nov 2022 22:15:55 +0530 Subject: [PATCH 279/356] Use custom entry name in gcc This is a continuation of 9f0a8620bd7d325e6d42417b08daff3e55cb88f6 for gcc. Signed-off-by: Ayush Singh --- src/context.rs | 5 +++-- src/declare.rs | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/context.rs b/src/context.rs index a4c63c0be1f9..29df1d2608a5 100644 --- a/src/context.rs +++ b/src/context.rs @@ -440,8 +440,9 @@ impl<'gcc, 'tcx> MiscMethods<'tcx> for CodegenCx<'gcc, 'tcx> { } fn declare_c_main(&self, fn_type: Self::Type) -> Option { - if self.get_declared_value("main").is_none() { - Some(self.declare_cfn("main", fn_type)) + let entry_name = self.sess().target.entry_name.as_ref(); + if self.get_declared_value(entry_name).is_none() { + Some(self.declare_entry_fn(entry_name, fn_type, ())) } else { // If the symbol already exists, it is an error: for example, the user wrote diff --git a/src/declare.rs b/src/declare.rs index b4b7d1b011ea..4748e7e4be2a 100644 --- a/src/declare.rs +++ b/src/declare.rs @@ -63,13 +63,13 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { global } - pub fn declare_cfn(&self, name: &str, _fn_type: Type<'gcc>) -> RValue<'gcc> { + pub fn declare_entry_fn(&self, name: &str, _fn_type: Type<'gcc>, callconv: () /*llvm::CCallConv*/) -> RValue<'gcc> { // TODO(antoyo): use the fn_type parameter. let const_string = self.context.new_type::().make_pointer().make_pointer(); let return_type = self.type_i32(); let variadic = false; self.linkage.set(FunctionType::Exported); - let func = declare_raw_fn(self, name, () /*llvm::CCallConv*/, return_type, &[self.type_i32(), const_string], variadic); + let func = declare_raw_fn(self, name, callconv, return_type, &[self.type_i32(), const_string], variadic); // NOTE: it is needed to set the current_func here as well, because get_fn() is not called // for the main function. *self.current_func.borrow_mut() = Some(func); From 6f7a01796dfde168c4b2d5163e17aa62e1f89f94 Mon Sep 17 00:00:00 2001 From: Chris Denton Date: Sat, 26 Nov 2022 09:54:54 +0000 Subject: [PATCH 280/356] Remove more redundant `all`s --- example/alloc_system.rs | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/example/alloc_system.rs b/example/alloc_system.rs index 89661918d05a..fd01fcf1fc82 100644 --- a/example/alloc_system.rs +++ b/example/alloc_system.rs @@ -13,17 +13,17 @@ // The minimum alignment guaranteed by the architecture. This value is used to // add fast paths for low alignment values. -#[cfg(all(any(target_arch = "x86", +#[cfg(any(target_arch = "x86", target_arch = "arm", target_arch = "mips", target_arch = "powerpc", - target_arch = "powerpc64")))] + target_arch = "powerpc64"))] const MIN_ALIGN: usize = 8; -#[cfg(all(any(target_arch = "x86_64", +#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "mips64", target_arch = "s390x", - target_arch = "sparc64")))] + target_arch = "sparc64"))] const MIN_ALIGN: usize = 16; pub struct System; From 634a709549db03962700b24619253f9965ea864a Mon Sep 17 00:00:00 2001 From: Maybe Waffle Date: Sun, 27 Nov 2022 11:15:06 +0000 Subject: [PATCH 281/356] Prefer doc comments over `//`-comments in compiler --- src/context.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/context.rs b/src/context.rs index 29df1d2608a5..6391c4e9d836 100644 --- a/src/context.rs +++ b/src/context.rs @@ -88,9 +88,9 @@ pub struct CodegenCx<'gcc, 'tcx> { pub vtables: RefCell, Option>), RValue<'gcc>>>, // TODO(antoyo): improve the SSA API to not require those. - // Mapping from function pointer type to indexes of on stack parameters. + /// Mapping from function pointer type to indexes of on stack parameters. pub on_stack_params: RefCell, FxHashSet>>, - // Mapping from function to indexes of on stack parameters. + /// Mapping from function to indexes of on stack parameters. pub on_stack_function_params: RefCell, FxHashSet>>, /// Cache of emitted const globals (value -> global) From d1eb38f5b5a3ed04f55189641b1d30ecd86b4a01 Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Sat, 28 May 2022 10:43:51 +0000 Subject: [PATCH 282/356] Rewrite LLVM's archive writer in Rust This allows it to be used by other codegen backends --- Cargo.lock | 14 ---- Cargo.toml | 3 - src/archive.rs | 177 ++----------------------------------------------- src/errors.rs | 16 +---- 4 files changed, 8 insertions(+), 202 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index fba8c3db42e4..b2013db3e3b3 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -11,12 +11,6 @@ dependencies = [ "memchr", ] -[[package]] -name = "ar" -version = "0.8.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "450575f58f7bee32816abbff470cbc47797397c2a81e0eaced4b98436daf52e1" - [[package]] name = "bitflags" version = "1.3.2" @@ -212,11 +206,9 @@ dependencies = [ name = "rustc_codegen_gcc" version = "0.1.0" dependencies = [ - "ar", "gccjit", "lang_tester", "smallvec", - "target-lexicon", "tempfile", ] @@ -235,12 +227,6 @@ version = "1.8.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "f2dd574626839106c320a323308629dcb1acfc96e32a8cba364ddc61ac23ee83" -[[package]] -name = "target-lexicon" -version = "0.10.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ab0e7238dcc7b40a7be719a25365910f6807bd864f4cce6b2e6b873658e2b19d" - [[package]] name = "tempfile" version = "3.2.0" diff --git a/Cargo.toml b/Cargo.toml index 3ac354ea4942..81066d9ce1f0 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -28,9 +28,6 @@ gccjit = { git = "https://github.com/antoyo/gccjit.rs" } #gccjit = { path = "../gccjit.rs" } smallvec = { version = "1.6.1", features = ["union", "may_dangle"] } -target-lexicon = "0.10.0" - -ar = "0.8.0" [dev-dependencies] lang_tester = "0.3.9" diff --git a/src/archive.rs b/src/archive.rs index f18ae7ea5e9b..11fa074f5ac7 100644 --- a/src/archive.rs +++ b/src/archive.rs @@ -1,44 +1,17 @@ -use std::fs::File; use std::path::{Path, PathBuf}; -use crate::errors::RanlibFailure; - -use rustc_codegen_ssa::back::archive::{ArchiveBuilder, ArchiveBuilderBuilder}; +use rustc_codegen_ssa::back::archive::{ + get_native_object_symbols, ArArchiveBuilder, ArchiveBuilder, ArchiveBuilderBuilder, +}; use rustc_session::Session; use rustc_session::cstore::DllImport; -struct ArchiveConfig<'a> { - sess: &'a Session, - use_native_ar: bool, - use_gnu_style_archive: bool, -} - -#[derive(Debug)] -enum ArchiveEntry { - FromArchive { - archive_index: usize, - entry_index: usize, - }, - File(PathBuf), -} - -pub struct ArArchiveBuilderBuilder; +pub(crate) struct ArArchiveBuilderBuilder; impl ArchiveBuilderBuilder for ArArchiveBuilderBuilder { fn new_archive_builder<'a>(&self, sess: &'a Session) -> Box + 'a> { - let config = ArchiveConfig { - sess, - use_native_ar: false, - // FIXME test for linux and System V derivatives instead - use_gnu_style_archive: sess.target.options.archive_format == "gnu", - }; - - Box::new(ArArchiveBuilder { - config, - src_archives: vec![], - entries: vec![], - }) + Box::new(ArArchiveBuilder::new(sess, get_native_object_symbols)) } fn create_dll_import_lib( @@ -49,144 +22,6 @@ impl ArchiveBuilderBuilder for ArArchiveBuilderBuilder { _tmpdir: &Path, _is_direct_dependency: bool, ) -> PathBuf { - unimplemented!(); - } -} - -pub struct ArArchiveBuilder<'a> { - config: ArchiveConfig<'a>, - src_archives: Vec<(PathBuf, ar::Archive)>, - // Don't use `HashMap` here, as the order is important. `rust.metadata.bin` must always be at - // the end of an archive for linkers to not get confused. - entries: Vec<(String, ArchiveEntry)>, -} - -impl<'a> ArchiveBuilder<'a> for ArArchiveBuilder<'a> { - fn add_file(&mut self, file: &Path) { - self.entries.push(( - file.file_name().unwrap().to_str().unwrap().to_string(), - ArchiveEntry::File(file.to_owned()), - )); - } - - fn add_archive( - &mut self, - archive_path: &Path, - mut skip: Box bool + 'static>, - ) -> std::io::Result<()> { - let mut archive = ar::Archive::new(std::fs::File::open(&archive_path)?); - let archive_index = self.src_archives.len(); - - let mut i = 0; - while let Some(entry) = archive.next_entry() { - let entry = entry?; - let file_name = String::from_utf8(entry.header().identifier().to_vec()) - .map_err(|err| std::io::Error::new(std::io::ErrorKind::InvalidData, err))?; - if !skip(&file_name) { - self.entries - .push((file_name, ArchiveEntry::FromArchive { archive_index, entry_index: i })); - } - i += 1; - } - - self.src_archives.push((archive_path.to_owned(), archive)); - Ok(()) - } - - fn build(mut self: Box, output: &Path) -> bool { - use std::process::Command; - - fn add_file_using_ar(archive: &Path, file: &Path) { - Command::new("ar") - .arg("r") // add or replace file - .arg("-c") // silence created file message - .arg(archive) - .arg(&file) - .status() - .unwrap(); - } - - enum BuilderKind<'a> { - Bsd(ar::Builder), - Gnu(ar::GnuBuilder), - NativeAr(&'a Path), - } - - let mut builder = if self.config.use_native_ar { - BuilderKind::NativeAr(output) - } else if self.config.use_gnu_style_archive { - BuilderKind::Gnu(ar::GnuBuilder::new( - File::create(output).unwrap(), - self.entries - .iter() - .map(|(name, _)| name.as_bytes().to_vec()) - .collect(), - )) - } else { - BuilderKind::Bsd(ar::Builder::new(File::create(output).unwrap())) - }; - - let any_members = !self.entries.is_empty(); - - // Add all files - for (entry_name, entry) in self.entries.into_iter() { - match entry { - ArchiveEntry::FromArchive { - archive_index, - entry_index, - } => { - let (ref src_archive_path, ref mut src_archive) = - self.src_archives[archive_index]; - let entry = src_archive.jump_to_entry(entry_index).unwrap(); - let header = entry.header().clone(); - - match builder { - BuilderKind::Bsd(ref mut builder) => { - builder.append(&header, entry).unwrap() - } - BuilderKind::Gnu(ref mut builder) => { - builder.append(&header, entry).unwrap() - } - BuilderKind::NativeAr(archive_file) => { - Command::new("ar") - .arg("x") - .arg(src_archive_path) - .arg(&entry_name) - .status() - .unwrap(); - add_file_using_ar(archive_file, Path::new(&entry_name)); - std::fs::remove_file(entry_name).unwrap(); - } - } - } - ArchiveEntry::File(file) => - match builder { - BuilderKind::Bsd(ref mut builder) => { - builder - .append_file(entry_name.as_bytes(), &mut File::open(file).expect("file for bsd builder")) - .unwrap() - }, - BuilderKind::Gnu(ref mut builder) => { - builder - .append_file(entry_name.as_bytes(), &mut File::open(&file).expect(&format!("file {:?} for gnu builder", file))) - .unwrap() - }, - BuilderKind::NativeAr(archive_file) => add_file_using_ar(archive_file, &file), - }, - } - } - - // Finalize archive - std::mem::drop(builder); - - // Run ranlib to be able to link the archive - let status = - std::process::Command::new("ranlib").arg(output).status().expect("Couldn't run ranlib"); - - if !status.success() { - self.config.sess.emit_fatal(RanlibFailure::new(status.code())); - } - - any_members + unimplemented!("creating dll imports is not yet supported"); } } diff --git a/src/errors.rs b/src/errors.rs index 15ad90f9043c..89fed7be1315 100644 --- a/src/errors.rs +++ b/src/errors.rs @@ -16,18 +16,6 @@ impl IntoDiagnosticArg for ExitCode { } } -#[derive(Diagnostic)] -#[diag(codegen_gcc_ranlib_failure)] -pub(crate) struct RanlibFailure { - exit_code: ExitCode, -} - -impl RanlibFailure { - pub fn new(exit_code: Option) -> Self { - RanlibFailure { exit_code: ExitCode(exit_code) } - } -} - #[derive(Diagnostic)] #[diag(codegen_gcc_invalid_monomorphization_basic_integer, code = "E0511")] pub(crate) struct InvalidMonomorphizationBasicInteger<'a> { @@ -227,7 +215,7 @@ pub(crate) struct InvalidMonomorphizationUnsupportedOperation<'a> { #[diag(codegen_gcc_linkage_const_or_mut_type)] pub(crate) struct LinkageConstOrMutType { #[primary_span] - pub span: Span + pub span: Span, } #[derive(Diagnostic)] @@ -238,5 +226,5 @@ pub(crate) struct LTONotSupported; #[diag(codegen_gcc_unwinding_inline_asm)] pub(crate) struct UnwindingInlineAsm { #[primary_span] - pub span: Span + pub span: Span, } From 43f868b1c3efa4fcf2526e9600c0f047c19a3eb7 Mon Sep 17 00:00:00 2001 From: Peter Collingbourne Date: Wed, 23 Nov 2022 18:13:30 -0800 Subject: [PATCH 283/356] Move linkage type check to HIR analysis and fix semantics issues. This ensures that the error is printed even for unused variables, as well as unifying the handling between the LLVM and GCC backends. This also fixes unusual behavior around exported Rust-defined variables with linkage attributes. With the previous behavior, it appears to be impossible to define such a variable such that it can actually be imported and used by another crate. This is because on the importing side, the variable is required to be a pointer, but on the exporting side, the type checker rejects static variables of pointer type because they do not implement `Sync`. Even if it were possible to import such a type, it appears that code generation on the importing side would add an unexpected additional level of pointer indirection, which would break type safety. This highlighted that the semantics of linkage on Rust-defined variables is different to linkage on foreign items. As such, we now model the difference with two different codegen attributes: linkage for Rust-defined variables, and import_linkage for foreign items. This change gives semantics to the test src/test/ui/linkage-attr/auxiliary/def_illtyped_external.rs which was previously expected to fail to compile. Therefore, convert it into a test that is expected to successfully compile. The update to the GCC backend is speculative and untested. --- src/consts.rs | 25 ++++++------------------- src/errors.rs | 7 ------- 2 files changed, 6 insertions(+), 26 deletions(-) diff --git a/src/consts.rs b/src/consts.rs index 7ffb345df9b6..eeb2b8f0d296 100644 --- a/src/consts.rs +++ b/src/consts.rs @@ -8,13 +8,11 @@ use rustc_middle::mir::mono::MonoItem; use rustc_middle::ty::{self, Instance, Ty}; use rustc_middle::ty::layout::LayoutOf; use rustc_middle::mir::interpret::{self, ConstAllocation, ErrorHandled, Scalar as InterpScalar, read_target_uint}; -use rustc_span::Span; use rustc_span::def_id::DefId; use rustc_target::abi::{self, Align, HasDataLayout, Primitive, Size, WrappingRange}; use crate::base; use crate::context::CodegenCx; -use crate::errors::LinkageConstOrMutType; use crate::type_of::LayoutGccExt; impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { @@ -216,7 +214,8 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { let ty = instance.ty(self.tcx, ty::ParamEnv::reveal_all()); let sym = self.tcx.symbol_name(instance).name; - let global = if def_id.is_local() && !self.tcx.is_foreign_item(def_id) { + let global = + if def_id.is_local() && !self.tcx.is_foreign_item(def_id) { let llty = self.layout_of(ty).gcc_type(self); if let Some(global) = self.get_declared_value(sym) { if self.val_ty(global) != self.type_ptr_to(llty) { @@ -239,7 +238,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { global } else { - check_and_apply_linkage(&self, &fn_attrs, ty, sym, self.tcx.def_span(def_id)) + check_and_apply_linkage(&self, &fn_attrs, ty, sym) }; if !def_id.is_local() { @@ -337,24 +336,12 @@ pub fn codegen_static_initializer<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, def_id Ok((const_alloc_to_gcc(cx, alloc), alloc)) } -fn check_and_apply_linkage<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, attrs: &CodegenFnAttrs, ty: Ty<'tcx>, sym: &str, span: Span) -> LValue<'gcc> { +fn check_and_apply_linkage<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, attrs: &CodegenFnAttrs, ty: Ty<'tcx>, sym: &str) -> LValue<'gcc> { let is_tls = attrs.flags.contains(CodegenFnAttrFlags::THREAD_LOCAL); let llty = cx.layout_of(ty).gcc_type(cx); - if let Some(linkage) = attrs.linkage { - // If this is a static with a linkage specified, then we need to handle - // it a little specially. The typesystem prevents things like &T and - // extern "C" fn() from being non-null, so we can't just declare a - // static and call it a day. Some linkages (like weak) will make it such - // that the static actually has a null value. - let llty2 = - if let ty::RawPtr(ref mt) = ty.kind() { - cx.layout_of(mt.ty).gcc_type(cx) - } - else { - cx.sess().emit_fatal(LinkageConstOrMutType { span: span }) - }; + if let Some(linkage) = attrs.import_linkage { // Declare a symbol `foo` with the desired linkage. - let global1 = cx.declare_global_with_linkage(&sym, llty2, base::global_linkage_to_gcc(linkage)); + let global1 = cx.declare_global_with_linkage(&sym, cx.type_i8(), base::global_linkage_to_gcc(linkage)); // Declare an internal global `extern_with_linkage_foo` which // is initialized with the address of `foo`. If `foo` is diff --git a/src/errors.rs b/src/errors.rs index 89fed7be1315..d0ba7e247911 100644 --- a/src/errors.rs +++ b/src/errors.rs @@ -211,13 +211,6 @@ pub(crate) struct InvalidMonomorphizationUnsupportedOperation<'a> { pub in_elem: Ty<'a>, } -#[derive(Diagnostic)] -#[diag(codegen_gcc_linkage_const_or_mut_type)] -pub(crate) struct LinkageConstOrMutType { - #[primary_span] - pub span: Span, -} - #[derive(Diagnostic)] #[diag(codegen_gcc_lto_not_supported)] pub(crate) struct LTONotSupported; From 7c2db89ce4951014a7fbec62ae81bda9abcf3657 Mon Sep 17 00:00:00 2001 From: Ramon de C Valle Date: Mon, 21 Nov 2022 21:29:00 -0800 Subject: [PATCH 284/356] Add LLVM KCFI support to the Rust compiler This commit adds LLVM Kernel Control Flow Integrity (KCFI) support to the Rust compiler. It initially provides forward-edge control flow protection for operating systems kernels for Rust-compiled code only by aggregating function pointers in groups identified by their return and parameter types. (See llvm/llvm-project@cff5bef.) Forward-edge control flow protection for C or C++ and Rust -compiled code "mixed binaries" (i.e., for when C or C++ and Rust -compiled code share the same virtual address space) will be provided in later work as part of this project by identifying C char and integer type uses at the time types are encoded (see Type metadata in the design document in the tracking issue #89653). LLVM KCFI can be enabled with -Zsanitizer=kcfi. Co-authored-by: bjorn3 <17426603+bjorn3@users.noreply.github.com> --- src/type_.rs | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/type_.rs b/src/type_.rs index 55e4d0c6289a..eacd76c6ea0e 100644 --- a/src/type_.rs +++ b/src/type_.rs @@ -300,4 +300,8 @@ impl<'gcc, 'tcx> TypeMembershipMethods<'tcx> for CodegenCx<'gcc, 'tcx> { // Unsupported. self.context.new_rvalue_from_int(self.int_type, 0) } + + fn set_kcfi_type_metadata(&self, _function: RValue<'gcc>, _kcfi_typeid: u32) { + // Unsupported. + } } From c2e83dce57c41363095cac253c5255070afcd667 Mon Sep 17 00:00:00 2001 From: bjorn3 <17426603+bjorn3@users.noreply.github.com> Date: Sat, 3 Dec 2022 18:27:18 +0000 Subject: [PATCH 285/356] Destruct landing_pad return value before passing it to cg_ssa --- src/builder.rs | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index 1603e9bf6282..70a93cb06d13 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1199,7 +1199,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } #[cfg(feature="master")] - fn cleanup_landing_pad(&mut self, _ty: Type<'gcc>, pers_fn: RValue<'gcc>) -> RValue<'gcc> { + fn cleanup_landing_pad(&mut self, pers_fn: RValue<'gcc>) -> (RValue<'gcc>, RValue<'gcc>) { self.set_personality_fn(pers_fn); // NOTE: insert the current block in a variable so that a later call to invoke knows to @@ -1223,21 +1223,19 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } #[cfg(not(feature="master"))] - fn cleanup_landing_pad(&mut self, _ty: Type<'gcc>, _pers_fn: RValue<'gcc>) -> RValue<'gcc> { + fn cleanup_landing_pad(&mut self, _pers_fn: RValue<'gcc>) -> (RValue<'gcc>, RValue<'gcc>) { let field1 = self.context.new_field(None, self.u8_type.make_pointer(), "landing_pad_field_1"); let field2 = self.context.new_field(None, self.i32_type, "landing_pad_field_1"); - let struct_type = self.context.new_struct_type(None, "landing_pad", &[field1, field2]); - self.current_func().new_local(None, struct_type.as_type(), "landing_pad") - .to_rvalue() + (field1, field2) } #[cfg(feature="master")] - fn resume(&mut self, exn: RValue<'gcc>) { + fn resume(&mut self, exn0: RValue<'gcc>, _exn1: RValue<'gcc>) { // TODO(antoyo): check if this is normal that we need to dereference the value. // NOTE: the type is wrong, so in order to get a pointer for parameter, cast it to a // pointer of pointer that is later dereferenced. - let exn_type = exn.get_type().make_pointer(); - let exn = self.context.new_cast(None, exn, exn_type); + let exn_type = exn0.get_type().make_pointer(); + let exn = self.context.new_cast(None, exn0, exn_type); let exn = exn.dereference(None).to_rvalue(); let unwind_resume = self.context.get_target_builtin_function("__builtin_unwind_resume"); self.llbb().add_eval(None, self.context.new_call(None, unwind_resume, &[exn])); @@ -1245,7 +1243,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } #[cfg(not(feature="master"))] - fn resume(&mut self, _exn: RValue<'gcc>) { + fn resume(&mut self, _exn0: RValue<'gcc>, _exn1: RValue<'gcc>) { self.unreachable(); } From 888137d7d27405ce0d41ae134088f814a2ec92a2 Mon Sep 17 00:00:00 2001 From: Jeremy Stucki Date: Tue, 20 Dec 2022 22:10:40 +0100 Subject: [PATCH 286/356] rustc: Remove needless lifetimes --- src/base.rs | 2 +- src/common.rs | 2 +- src/lib.rs | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/base.rs b/src/base.rs index 6102016b4345..dcd560b3dcd9 100644 --- a/src/base.rs +++ b/src/base.rs @@ -63,7 +63,7 @@ pub fn linkage_to_gcc(linkage: Linkage) -> FunctionType { } } -pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_128bit_integers: bool) -> (ModuleCodegen, u64) { +pub fn compile_codegen_unit(tcx: TyCtxt<'_>, cgu_name: Symbol, supports_128bit_integers: bool) -> (ModuleCodegen, u64) { let prof_timer = tcx.prof.generic_activity("codegen_module"); let start_time = Instant::now(); diff --git a/src/common.rs b/src/common.rs index 102d1e5a824d..ef857cbe5719 100644 --- a/src/common.rs +++ b/src/common.rs @@ -44,7 +44,7 @@ pub fn bytes_in_context<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, bytes: &[u8]) -> context.new_array_constructor(None, typ, &elements) } -pub fn type_is_pointer<'gcc>(typ: Type<'gcc>) -> bool { +pub fn type_is_pointer(typ: Type) -> bool { typ.get_pointee().is_some() } diff --git a/src/lib.rs b/src/lib.rs index 0d99f4e2f335..16db781a894a 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -163,7 +163,7 @@ impl ExtraBackendMethods for GccCodegenBackend { mods } - fn compile_codegen_unit<'tcx>(&self, tcx: TyCtxt<'tcx>, cgu_name: Symbol) -> (ModuleCodegen, u64) { + fn compile_codegen_unit(&self, tcx: TyCtxt<'_>, cgu_name: Symbol) -> (ModuleCodegen, u64) { base::compile_codegen_unit(tcx, cgu_name, *self.supports_128bit_integers.lock().expect("lock")) } From 3a1d3241b4f998d136afe188072dc36f006d026c Mon Sep 17 00:00:00 2001 From: Jeremy Stucki Date: Tue, 20 Dec 2022 22:34:42 +0100 Subject: [PATCH 287/356] Add missing anonymous lifetime --- src/common.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/common.rs b/src/common.rs index ef857cbe5719..0c7d9697d399 100644 --- a/src/common.rs +++ b/src/common.rs @@ -44,7 +44,7 @@ pub fn bytes_in_context<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, bytes: &[u8]) -> context.new_array_constructor(None, typ, &elements) } -pub fn type_is_pointer(typ: Type) -> bool { +pub fn type_is_pointer(typ: Type<'_>) -> bool { typ.get_pointee().is_some() } From fa874b03e43aa4f3e136e1920e6016060418bb9b Mon Sep 17 00:00:00 2001 From: Michael Goulet Date: Sat, 10 Dec 2022 20:31:01 +0000 Subject: [PATCH 288/356] Simplify some iterator combinators --- src/builder.rs | 2 +- src/context.rs | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index 70a93cb06d13..f30362871528 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1365,7 +1365,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { ) -> RValue<'gcc> { // FIXME(antoyo): remove when having a proper API. let gcc_func = unsafe { std::mem::transmute(func) }; - let call = if self.functions.borrow().values().find(|value| **value == gcc_func).is_some() { + let call = if self.functions.borrow().values().any(|value| *value == gcc_func) { self.function_call(func, args, funclet) } else { diff --git a/src/context.rs b/src/context.rs index 6391c4e9d836..9bd3710ac8ad 100644 --- a/src/context.rs +++ b/src/context.rs @@ -258,8 +258,8 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { pub fn rvalue_as_function(&self, value: RValue<'gcc>) -> Function<'gcc> { let function: Function<'gcc> = unsafe { std::mem::transmute(value) }; - debug_assert!(self.functions.borrow().values().find(|value| **value == function).is_some(), - "{:?} is not a function", function); + debug_assert!(self.functions.borrow().values().any(|value| *value == function), + "{:?} ({:?}) is not a function", value, value.get_type()); function } From 5dcda26aa6640ecf3d0d77d08ee37983b4ca1f4a Mon Sep 17 00:00:00 2001 From: Albert Larsan <74931857+albertlarsan68@users.noreply.github.com> Date: Thu, 5 Jan 2023 09:45:44 +0100 Subject: [PATCH 289/356] Change `src/test` to `tests` in source files, fix tidy and tests --- test.sh | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/test.sh b/test.sh index 4c490f04ae9d..97d5a8b006df 100755 --- a/test.sh +++ b/test.sh @@ -228,7 +228,7 @@ llvm-filecheck = "`which FileCheck-10 || which FileCheck-11 || which FileCheck-1 EOF rustc -V | cut -d' ' -f3 | tr -d '(' - git checkout $(rustc -V | cut -d' ' -f3 | tr -d '(') src/test + git checkout $(rustc -V | cut -d' ' -f3 | tr -d '(') tests } function asm_tests() { @@ -236,7 +236,7 @@ function asm_tests() { echo "[TEST] rustc test suite" RUSTC_ARGS="-Zpanic-abort-tests -Csymbol-mangling-version=v0 -Zcodegen-backend="$(pwd)"/../target/"$CHANNEL"/librustc_codegen_gcc."$dylib_ext" --sysroot "$(pwd)"/../build_sysroot/sysroot -Cpanic=abort" - COMPILETEST_FORCE_STAGE0=1 ./x.py test --run always --stage 0 src/test/assembly/asm --rustc-args "$RUSTC_ARGS" + COMPILETEST_FORCE_STAGE0=1 ./x.py test --run always --stage 0 tests/assembly/asm --rustc-args "$RUSTC_ARGS" } # FIXME(antoyo): linker gives multiple definitions error on Linux @@ -332,21 +332,21 @@ function test_rustc() { setup_rustc - for test in $(rg -i --files-with-matches "//(\[\w+\])?~|// error-pattern:|// build-fail|// run-fail|-Cllvm-args" src/test/ui); do + for test in $(rg -i --files-with-matches "//(\[\w+\])?~|// error-pattern:|// build-fail|// run-fail|-Cllvm-args" tests/ui); do rm $test done - git checkout -- src/test/ui/issues/auxiliary/issue-3136-a.rs # contains //~ERROR, but shouldn't be removed + git checkout -- tests/ui/issues/auxiliary/issue-3136-a.rs # contains //~ERROR, but shouldn't be removed - rm -r src/test/ui/{abi*,extern/,unsized-locals/,proc-macro/,threads-sendsync/,thinlto/,borrowck/,chalkify/bugs/,test*,*lto*.rs,consts/const-float-bits-reject-conv.rs,consts/issue-miri-1910.rs} || true - rm src/test/ui/mir/mir_heavy_promoted.rs # this tests is oom-killed in the CI. - for test in $(rg --files-with-matches "thread|lto" src/test/ui); do + rm -r tests/ui/{abi*,extern/,unsized-locals/,proc-macro/,threads-sendsync/,thinlto/,borrowck/,chalkify/bugs/,test*,*lto*.rs,consts/const-float-bits-reject-conv.rs,consts/issue-miri-1910.rs} || true + rm tests/ui/mir/mir_heavy_promoted.rs # this tests is oom-killed in the CI. + for test in $(rg --files-with-matches "thread|lto" tests/ui); do rm $test done - git checkout src/test/ui/lto/auxiliary/dylib.rs - git checkout src/test/ui/type-alias-impl-trait/auxiliary/cross_crate_ice.rs - git checkout src/test/ui/type-alias-impl-trait/auxiliary/cross_crate_ice2.rs - git checkout src/test/ui/macros/rfc-2011-nicer-assert-messages/auxiliary/common.rs + git checkout tests/ui/lto/auxiliary/dylib.rs + git checkout tests/ui/type-alias-impl-trait/auxiliary/cross_crate_ice.rs + git checkout tests/ui/type-alias-impl-trait/auxiliary/cross_crate_ice2.rs + git checkout tests/ui/macros/rfc-2011-nicer-assert-messages/auxiliary/common.rs RUSTC_ARGS="$TEST_FLAGS -Csymbol-mangling-version=v0 -Zcodegen-backend="$(pwd)"/../target/"$CHANNEL"/librustc_codegen_gcc."$dylib_ext" --sysroot "$(pwd)"/../build_sysroot/sysroot" @@ -358,14 +358,14 @@ function test_rustc() { xargs -a ../failing-ui-tests.txt -d'\n' rm else # Removing all tests. - find src/test/ui -type f -name '*.rs' -not -path '*/auxiliary/*' -delete + find tests/ui -type f -name '*.rs' -not -path '*/auxiliary/*' -delete # Putting back only the failing ones. xargs -a ../failing-ui-tests.txt -d'\n' git checkout -- fi if [ $nb_parts -gt 0 ]; then echo "Splitting ui_test into $nb_parts parts (and running part $current_part)" - find src/test/ui -type f -name '*.rs' -not -path "*/auxiliary/*" > ui_tests + find tests/ui -type f -name '*.rs' -not -path "*/auxiliary/*" > ui_tests # To ensure it'll be always the same sub files, we sort the content. sort ui_tests -o ui_tests count=$((`wc -l < ui_tests` / $nb_parts)) @@ -374,13 +374,13 @@ function test_rustc() { count=$((count + 1)) split -d -l $count -a 1 ui_tests ui_tests.split # Removing all tests. - find src/test/ui -type f -name '*.rs' -not -path "*/auxiliary/*" -delete + find tests/ui -type f -name '*.rs' -not -path "*/auxiliary/*" -delete # Putting back only the ones we want to test. xargs -a "ui_tests.split$current_part" -d'\n' git checkout -- fi echo "[TEST] rustc test suite" - COMPILETEST_FORCE_STAGE0=1 ./x.py test --run always --stage 0 src/test/ui/ --rustc-args "$RUSTC_ARGS" + COMPILETEST_FORCE_STAGE0=1 ./x.py test --run always --stage 0 tests/ui/ --rustc-args "$RUSTC_ARGS" } function test_failing_rustc() { From 7bf06701693934ded0774f0c17f45943cdbe44f3 Mon Sep 17 00:00:00 2001 From: Erik Desjardins Date: Sun, 22 Jan 2023 23:03:58 -0500 Subject: [PATCH 290/356] abi: add `AddressSpace` field to `Primitive::Pointer` ...and remove it from `PointeeInfo`, which isn't meant for this. There are still various places (marked with FIXMEs) that assume all pointers have the same size and alignment. Fixing this requires parsing non-default address spaces in the data layout string, which will be done in a followup. --- src/builder.rs | 2 +- src/common.rs | 2 +- src/consts.rs | 16 ++++++++++++---- src/type_of.rs | 4 ++-- 4 files changed, 16 insertions(+), 8 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index f30362871528..05b3bacfbf91 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -768,7 +768,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { bx.range_metadata(load, vr); } } - abi::Pointer if vr.start < vr.end && !vr.contains(0) => { + abi::Pointer(_) if vr.start < vr.end && !vr.contains(0) => { bx.nonnull_metadata(load); } _ => {} diff --git a/src/common.rs b/src/common.rs index 0c7d9697d399..54325e1277b0 100644 --- a/src/common.rs +++ b/src/common.rs @@ -221,7 +221,7 @@ impl<'gcc, 'tcx> ConstMethods<'tcx> for CodegenCx<'gcc, 'tcx> { let base_addr = self.const_bitcast(base_addr, self.usize_type); let offset = self.context.new_rvalue_from_long(self.usize_type, offset.bytes() as i64); let ptr = self.const_bitcast(base_addr + offset, ptr_type); - if layout.primitive() != Pointer { + if !matches!(layout.primitive(), Pointer(_)) { self.const_bitcast(ptr.dereference(None).to_rvalue(), ty) } else { diff --git a/src/consts.rs b/src/consts.rs index eeb2b8f0d296..52e5ea777870 100644 --- a/src/consts.rs +++ b/src/consts.rs @@ -7,9 +7,9 @@ use rustc_middle::middle::codegen_fn_attrs::{CodegenFnAttrFlags, CodegenFnAttrs} use rustc_middle::mir::mono::MonoItem; use rustc_middle::ty::{self, Instance, Ty}; use rustc_middle::ty::layout::LayoutOf; -use rustc_middle::mir::interpret::{self, ConstAllocation, ErrorHandled, Scalar as InterpScalar, read_target_uint}; +use rustc_middle::mir::interpret::{self, ConstAllocation, ErrorHandled, GlobalAlloc, Scalar as InterpScalar, read_target_uint}; use rustc_span::def_id::DefId; -use rustc_target::abi::{self, Align, HasDataLayout, Primitive, Size, WrappingRange}; +use rustc_target::abi::{self, AddressSpace, Align, HasDataLayout, Primitive, Size, WrappingRange}; use crate::base; use crate::context::CodegenCx; @@ -306,13 +306,21 @@ pub fn const_alloc_to_gcc<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, alloc: ConstAl ) .expect("const_alloc_to_llvm: could not read relocation pointer") as u64; + + let address_space = match cx.tcx.global_alloc(alloc_id) { + GlobalAlloc::Function(..) => cx.data_layout().instruction_address_space, + GlobalAlloc::Static(..) | GlobalAlloc::Memory(..) | GlobalAlloc::VTable(..) => { + AddressSpace::DATA + } + }; + llvals.push(cx.scalar_to_backend( InterpScalar::from_pointer( interpret::Pointer::new(alloc_id, Size::from_bytes(ptr_offset)), &cx.tcx, ), - abi::Scalar::Initialized { value: Primitive::Pointer, valid_range: WrappingRange::full(dl.pointer_size) }, - cx.type_i8p(), + abi::Scalar::Initialized { value: Primitive::Pointer(address_space), valid_range: WrappingRange::full(dl.pointer_size) }, + cx.type_i8p_ext(address_space), )); next_offset = offset + pointer_size; } diff --git a/src/type_of.rs b/src/type_of.rs index 09c79b69ce3c..b01bd114656c 100644 --- a/src/type_of.rs +++ b/src/type_of.rs @@ -253,7 +253,7 @@ impl<'tcx> LayoutGccExt<'tcx> for TyAndLayout<'tcx> { Int(i, false) => cx.type_from_unsigned_integer(i), F32 => cx.type_f32(), F64 => cx.type_f64(), - Pointer => { + Pointer(address_space) => { // If we know the alignment, pick something better than i8. let pointee = if let Some(pointee) = self.pointee_info_at(cx, offset) { @@ -262,7 +262,7 @@ impl<'tcx> LayoutGccExt<'tcx> for TyAndLayout<'tcx> { else { cx.type_i8() }; - cx.type_ptr_to(pointee) + cx.type_ptr_to_ext(pointee, address_space) } } } From bedaeda5084ab94fde088de0dba80e3bdc2363ef Mon Sep 17 00:00:00 2001 From: Erik Desjardins Date: Wed, 25 Jan 2023 01:46:19 -0500 Subject: [PATCH 291/356] create and use GlobalAlloc::address_space --- src/consts.rs | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/src/consts.rs b/src/consts.rs index 52e5ea777870..b651b60924f7 100644 --- a/src/consts.rs +++ b/src/consts.rs @@ -7,9 +7,9 @@ use rustc_middle::middle::codegen_fn_attrs::{CodegenFnAttrFlags, CodegenFnAttrs} use rustc_middle::mir::mono::MonoItem; use rustc_middle::ty::{self, Instance, Ty}; use rustc_middle::ty::layout::LayoutOf; -use rustc_middle::mir::interpret::{self, ConstAllocation, ErrorHandled, GlobalAlloc, Scalar as InterpScalar, read_target_uint}; +use rustc_middle::mir::interpret::{self, ConstAllocation, ErrorHandled, Scalar as InterpScalar, read_target_uint}; use rustc_span::def_id::DefId; -use rustc_target::abi::{self, AddressSpace, Align, HasDataLayout, Primitive, Size, WrappingRange}; +use rustc_target::abi::{self, Align, HasDataLayout, Primitive, Size, WrappingRange}; use crate::base; use crate::context::CodegenCx; @@ -307,12 +307,7 @@ pub fn const_alloc_to_gcc<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, alloc: ConstAl .expect("const_alloc_to_llvm: could not read relocation pointer") as u64; - let address_space = match cx.tcx.global_alloc(alloc_id) { - GlobalAlloc::Function(..) => cx.data_layout().instruction_address_space, - GlobalAlloc::Static(..) | GlobalAlloc::Memory(..) | GlobalAlloc::VTable(..) => { - AddressSpace::DATA - } - }; + let address_space = cx.tcx.global_alloc(alloc_id).address_space(cx); llvals.push(cx.scalar_to_backend( InterpScalar::from_pointer( From 1640ccac4da37ae2095d6e9bec68ff90aa71aecf Mon Sep 17 00:00:00 2001 From: David Wood Date: Fri, 19 Aug 2022 14:48:15 +0100 Subject: [PATCH 292/356] session: diagnostic migration lint on more fns Apply the diagnostic migration lint to more functions on `Session`. Signed-off-by: David Wood --- src/lib.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/src/lib.rs b/src/lib.rs index 16db781a894a..48c16cba240c 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -202,6 +202,7 @@ unsafe impl Sync for GccContext {} impl WriteBackendMethods for GccCodegenBackend { type Module = GccContext; type TargetMachine = (); + type TargetMachineError = (); type ModuleBuffer = ModuleBuffer; type ThinData = (); type ThinBuffer = ThinBuffer; From ae429e8cab135902df69135d8b4b4aca555f4ace Mon Sep 17 00:00:00 2001 From: Oli Scherer Date: Tue, 14 Feb 2023 08:51:19 +0000 Subject: [PATCH 293/356] s/eval_usize/eval_target_usize/ for clarity --- src/intrinsic/simd.rs | 189 +++++++++++++++++++++++++----------------- 1 file changed, 111 insertions(+), 78 deletions(-) diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index ff75543ecd1e..b8c479970091 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -1,6 +1,7 @@ #[cfg_attr(not(feature="master"), allow(unused_imports))] use gccjit::{ToRValue, ComparisonOp, UnaryOp}; use gccjit::{BinaryOp, RValue, Type}; + use rustc_codegen_ssa::base::compare_simd_types; use rustc_codegen_ssa::common::{IntPredicate, TypeKind}; use rustc_codegen_ssa::mir::operand::OperandRef; @@ -10,52 +11,58 @@ use rustc_hir as hir; use rustc_middle::span_bug; use rustc_middle::ty::layout::HasTyCtxt; use rustc_middle::ty::{self, Ty}; -use rustc_span::{Span, Symbol, sym}; +use rustc_span::{sym, Span, Symbol}; use rustc_target::abi::Align; use crate::builder::Builder; #[cfg(feature="master")] use crate::context::CodegenCx; use crate::errors::{ - InvalidMonomorphizationInvalidFloatVector, - InvalidMonomorphizationNotFloat, - InvalidMonomorphizationUnrecognized, - InvalidMonomorphizationExpectedSignedUnsigned, - InvalidMonomorphizationUnsupportedElement, - InvalidMonomorphizationInvalidBitmask, - InvalidMonomorphizationSimdShuffle, - InvalidMonomorphizationExpectedSimd, - InvalidMonomorphizationMaskType, - InvalidMonomorphizationReturnLength, - InvalidMonomorphizationReturnLengthInputType, - InvalidMonomorphizationReturnElement, - InvalidMonomorphizationReturnType, - InvalidMonomorphizationInsertedType, - InvalidMonomorphizationReturnIntegerType, - InvalidMonomorphizationMismatchedLengths, - InvalidMonomorphizationUnsupportedOperation + InvalidMonomorphizationExpectedSignedUnsigned, InvalidMonomorphizationExpectedSimd, + InvalidMonomorphizationInsertedType, InvalidMonomorphizationInvalidBitmask, + InvalidMonomorphizationInvalidFloatVector, InvalidMonomorphizationMaskType, + InvalidMonomorphizationMismatchedLengths, InvalidMonomorphizationNotFloat, + InvalidMonomorphizationReturnElement, InvalidMonomorphizationReturnIntegerType, + InvalidMonomorphizationReturnLength, InvalidMonomorphizationReturnLengthInputType, + InvalidMonomorphizationReturnType, InvalidMonomorphizationSimdShuffle, + InvalidMonomorphizationUnrecognized, InvalidMonomorphizationUnsupportedElement, + InvalidMonomorphizationUnsupportedOperation, }; -pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, name: Symbol, callee_ty: Ty<'tcx>, args: &[OperandRef<'tcx, RValue<'gcc>>], ret_ty: Ty<'tcx>, llret_ty: Type<'gcc>, span: Span) -> Result, ()> { +pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>( + bx: &mut Builder<'a, 'gcc, 'tcx>, + name: Symbol, + callee_ty: Ty<'tcx>, + args: &[OperandRef<'tcx, RValue<'gcc>>], + ret_ty: Ty<'tcx>, + llret_ty: Type<'gcc>, + span: Span, +) -> Result, ()> { // macros for error handling: macro_rules! return_error { - ($err:expr) => { - { - bx.sess().emit_err($err); - return Err(()); - } - } + ($err:expr) => {{ + bx.sess().emit_err($err); + return Err(()); + }}; } macro_rules! require { ($cond:expr, $err:expr) => { if !$cond { return_error!($err); } - } + }; } macro_rules! require_simd { ($ty: expr, $position: expr) => { - require!($ty.is_simd(), InvalidMonomorphizationExpectedSimd { span, name, position: $position, found_ty: $ty }) + require!( + $ty.is_simd(), + InvalidMonomorphizationExpectedSimd { + span, + name, + position: $position, + found_ty: $ty + } + ) }; } @@ -77,7 +84,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, ty::Uint(i) if i.bit_width() == Some(expected_int_bits) => args[0].immediate(), ty::Array(elem, len) if matches!(elem.kind(), ty::Uint(ty::UintTy::U8)) - && len.try_eval_usize(bx.tcx, ty::ParamEnv::reveal_all()) + && len.try_eval_target_usize(bx.tcx, ty::ParamEnv::reveal_all()) == Some(expected_bytes) => { let place = PlaceRef::alloca(bx, args[0].layout); @@ -86,9 +93,13 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let ptr = bx.pointercast(place.llval, bx.cx.type_ptr_to(int_ty)); bx.load(int_ty, ptr, Align::ONE) } - _ => return_error!( - InvalidMonomorphizationInvalidBitmask { span, name, ty: mask_ty, expected_int_bits, expected_bytes } - ), + _ => return_error!(InvalidMonomorphizationInvalidBitmask { + span, + name, + ty: mask_ty, + expected_int_bits, + expected_bytes + }), }; let arg1 = args[1].immediate(); @@ -134,11 +145,18 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let (out_len, out_ty) = ret_ty.simd_size_and_type(bx.tcx()); require!( in_len == out_len, - InvalidMonomorphizationReturnLengthInputType { span, name, in_len, in_ty, ret_ty, out_len } + InvalidMonomorphizationReturnLengthInputType { + span, + name, + in_len, + in_ty, + ret_ty, + out_len + } ); require!( bx.type_kind(bx.element_type(llret_ty)) == TypeKind::Integer, - InvalidMonomorphizationReturnIntegerType {span, name, ret_ty, out_ty} + InvalidMonomorphizationReturnIntegerType { span, name, ret_ty, out_ty } ); return Ok(compare_simd_types( @@ -152,26 +170,26 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, } if let Some(stripped) = name.as_str().strip_prefix("simd_shuffle") { - let n: u64 = - if stripped.is_empty() { - // Make sure this is actually an array, since typeck only checks the length-suffixed - // version of this intrinsic. - match args[2].layout.ty.kind() { - ty::Array(ty, len) if matches!(ty.kind(), ty::Uint(ty::UintTy::U32)) => { - len.try_eval_usize(bx.cx.tcx, ty::ParamEnv::reveal_all()).unwrap_or_else(|| { - span_bug!(span, "could not evaluate shuffle index array length") - }) - } - _ => return_error!( - InvalidMonomorphizationSimdShuffle { span, name, ty: args[2].layout.ty } - ), + let n: u64 = if stripped.is_empty() { + // Make sure this is actually an array, since typeck only checks the length-suffixed + // version of this intrinsic. + match args[2].layout.ty.kind() { + ty::Array(ty, len) if matches!(ty.kind(), ty::Uint(ty::UintTy::U32)) => { + len.try_eval_target_usize(bx.cx.tcx, ty::ParamEnv::reveal_all()).unwrap_or_else( + || span_bug!(span, "could not evaluate shuffle index array length"), + ) } + _ => return_error!(InvalidMonomorphizationSimdShuffle { + span, + name, + ty: args[2].layout.ty + }), } - else { - stripped.parse().unwrap_or_else(|_| { - span_bug!(span, "bad `simd_shuffle` instruction only caught in codegen?") - }) - }; + } else { + stripped.parse().unwrap_or_else(|_| { + span_bug!(span, "bad `simd_shuffle` instruction only caught in codegen?") + }) + }; require_simd!(ret_ty, "return"); @@ -187,14 +205,10 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let vector = args[2].immediate(); - return Ok(bx.shuffle_vector( - args[0].immediate(), - args[1].immediate(), - vector, - )); + return Ok(bx.shuffle_vector(args[0].immediate(), args[1].immediate(), vector)); } - #[cfg(feature="master")] + #[cfg(feature = "master")] if name == sym::simd_insert { require!( in_elem == arg_tys[2], @@ -211,7 +225,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, return Ok(variable.to_rvalue()); } - #[cfg(feature="master")] + #[cfg(feature = "master")] if name == sym::simd_extract { require!( ret_ty == in_elem, @@ -243,7 +257,14 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let (out_len, out_elem) = ret_ty.simd_size_and_type(bx.tcx()); require!( in_len == out_len, - InvalidMonomorphizationReturnLengthInputType { span, name, in_len, in_ty, ret_ty, out_len } + InvalidMonomorphizationReturnLengthInputType { + span, + name, + in_len, + in_ty, + ret_ty, + out_len + } ); // casting cares about nominal type, not just structural type if in_elem == out_elem { @@ -373,12 +394,10 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, args: &[OperandRef<'tcx, RValue<'gcc>>], ) -> Result, ()> { macro_rules! return_error { - ($err:expr) => { - { - bx.sess().emit_err($err); - return Err(()); - } - } + ($err:expr) => {{ + bx.sess().emit_err($err); + return Err(()); + }}; } let (elem_ty_str, elem_ty) = if let ty::Float(f) = in_elem.kind() { @@ -391,9 +410,9 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, } } } - else { - return_error!(InvalidMonomorphizationNotFloat { span, name, ty: in_ty }); - }; + } else { + return_error!(InvalidMonomorphizationNotFloat { span, name, ty: in_ty }); + }; let vec_ty = bx.cx.type_vector(elem_ty, in_len); @@ -778,7 +797,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, simd_neg: Int => neg, Float => fneg; } - #[cfg(feature="master")] + #[cfg(feature = "master")] if name == sym::simd_saturating_add || name == sym::simd_saturating_sub { let lhs = args[0].immediate(); let rhs = args[1].immediate(); @@ -898,8 +917,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, // if overflow occurs, the result is the // mathematical result modulo 2^n: Ok(bx.$op(args[1].immediate(), r)) - } - else { + } else { Ok(bx.vector_reduce_op(args[0].immediate(), $vec_op)) } } @@ -908,12 +926,17 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, // ordered arithmetic reductions take an accumulator let acc = args[1].immediate(); Ok(bx.$float_reduce(acc, args[0].immediate())) - } - else { + } else { Ok(bx.vector_reduce_op(args[0].immediate(), $vec_op)) } } - _ => return_error!(InvalidMonomorphizationUnsupportedElement { span, name, in_ty, elem_ty: in_elem, ret_ty }), + _ => return_error!(InvalidMonomorphizationUnsupportedElement { + span, + name, + in_ty, + elem_ty: in_elem, + ret_ty + }), }; } }; @@ -983,7 +1006,13 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, } else { match in_elem.kind() { ty::Int(_) | ty::Uint(_) => {} - _ => return_error!(InvalidMonomorphizationUnsupportedElement { span, name, in_ty, elem_ty: in_elem, ret_ty }), + _ => return_error!(InvalidMonomorphizationUnsupportedElement { + span, + name, + in_ty, + elem_ty: in_elem, + ret_ty + }), } args[0].immediate() @@ -993,9 +1022,13 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, let r = bx.vector_reduce_op(input, $op); Ok(if !$boolean { r } else { bx.icmp(IntPredicate::IntNE, r, bx.context.new_rvalue_zero(r.get_type())) }) } - _ => return_error!( - InvalidMonomorphizationUnsupportedElement { span, name, in_ty, elem_ty: in_elem, ret_ty } - ), + _ => return_error!(InvalidMonomorphizationUnsupportedElement { + span, + name, + in_ty, + elem_ty: in_elem, + ret_ty + }), }; } }; From 564ab10b9c6799063934ef7e6d82b8388f349047 Mon Sep 17 00:00:00 2001 From: David Wood Date: Thu, 13 Oct 2022 10:13:02 +0100 Subject: [PATCH 294/356] errors: generate typed identifiers in each crate Instead of loading the Fluent resources for every crate in `rustc_error_messages`, each crate generates typed identifiers for its own diagnostics and creates a static which are pulled together in the `rustc_driver` crate and provided to the diagnostic emitter. Signed-off-by: David Wood --- locales/en-US.ftl | 62 +++++++++++++++++++++++++++++++++++++++++++++++ src/lib.rs | 5 +++- 2 files changed, 66 insertions(+), 1 deletion(-) create mode 100644 locales/en-US.ftl diff --git a/locales/en-US.ftl b/locales/en-US.ftl new file mode 100644 index 000000000000..6101b28ab0cd --- /dev/null +++ b/locales/en-US.ftl @@ -0,0 +1,62 @@ +codegen_gcc_unwinding_inline_asm = + GCC backend does not support unwinding from inline asm + +codegen_gcc_lto_not_supported = + LTO is not supported. You may get a linker error. + +codegen_gcc_invalid_monomorphization_basic_integer = + invalid monomorphization of `{$name}` intrinsic: expected basic integer type, found `{$ty}` + +codegen_gcc_invalid_monomorphization_invalid_float_vector = + invalid monomorphization of `{$name}` intrinsic: unsupported element type `{$elem_ty}` of floating-point vector `{$vec_ty}` + +codegen_gcc_invalid_monomorphization_not_float = + invalid monomorphization of `{$name}` intrinsic: `{$ty}` is not a floating-point type + +codegen_gcc_invalid_monomorphization_unrecognized = + invalid monomorphization of `{$name}` intrinsic: unrecognized intrinsic `{$name}` + +codegen_gcc_invalid_monomorphization_expected_signed_unsigned = + invalid monomorphization of `{$name}` intrinsic: expected element type `{$elem_ty}` of vector type `{$vec_ty}` to be a signed or unsigned integer type + +codegen_gcc_invalid_monomorphization_unsupported_element = + invalid monomorphization of `{$name}` intrinsic: unsupported {$name} from `{$in_ty}` with element `{$elem_ty}` to `{$ret_ty}` + +codegen_gcc_invalid_monomorphization_invalid_bitmask = + invalid monomorphization of `{$name}` intrinsic: invalid bitmask `{$ty}`, expected `u{$expected_int_bits}` or `[u8; {$expected_bytes}]` + +codegen_gcc_invalid_monomorphization_simd_shuffle = + invalid monomorphization of `{$name}` intrinsic: simd_shuffle index must be an array of `u32`, got `{$ty}` + +codegen_gcc_invalid_monomorphization_expected_simd = + invalid monomorphization of `{$name}` intrinsic: expected SIMD {$expected_ty} type, found non-SIMD `{$found_ty}` + +codegen_gcc_invalid_monomorphization_mask_type = + invalid monomorphization of `{$name}` intrinsic: mask element type is `{$ty}`, expected `i_` + +codegen_gcc_invalid_monomorphization_return_length = + invalid monomorphization of `{$name}` intrinsic: expected return type of length {$in_len}, found `{$ret_ty}` with length {$out_len} + +codegen_gcc_invalid_monomorphization_return_length_input_type = + invalid monomorphization of `{$name}` intrinsic: expected return type with length {$in_len} (same as input type `{$in_ty}`), found `{$ret_ty}` with length {$out_len} + +codegen_gcc_invalid_monomorphization_return_element = + invalid monomorphization of `{$name}` intrinsic: expected return element type `{$in_elem}` (element of input `{$in_ty}`), found `{$ret_ty}` with element type `{$out_ty}` + +codegen_gcc_invalid_monomorphization_return_type = + invalid monomorphization of `{$name}` intrinsic: expected return type `{$in_elem}` (element of input `{$in_ty}`), found `{$ret_ty}` + +codegen_gcc_invalid_monomorphization_inserted_type = + invalid monomorphization of `{$name}` intrinsic: expected inserted type `{$in_elem}` (element of input `{$in_ty}`), found `{$out_ty}` + +codegen_gcc_invalid_monomorphization_return_integer_type = + invalid monomorphization of `{$name}` intrinsic: expected return type with integer elements, found `{$ret_ty}` with non-integer `{$out_ty}` + +codegen_gcc_invalid_monomorphization_mismatched_lengths = + invalid monomorphization of `{$name}` intrinsic: mismatched lengths: mask length `{$m_len}` != other vector length `{$v_len}` + +codegen_gcc_invalid_monomorphization_unsupported_cast = + invalid monomorphization of `{$name}` intrinsic: unsupported cast from `{$in_ty}` with element `{$in_elem}` to `{$ret_ty}` with element `{$out_elem}` + +codegen_gcc_invalid_monomorphization_unsupported_operation = + invalid monomorphization of `{$name}` intrinsic: unsupported operation on `{$in_ty}` with element `{$in_elem}` diff --git a/src/lib.rs b/src/lib.rs index 48c16cba240c..c32c837d83a8 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -75,7 +75,8 @@ use rustc_codegen_ssa::back::lto::{LtoModuleCodegen, SerializedModule, ThinModul use rustc_codegen_ssa::target_features::supported_target_features; use rustc_codegen_ssa::traits::{CodegenBackend, ExtraBackendMethods, ModuleBufferMethods, ThinBufferMethods, WriteBackendMethods}; use rustc_data_structures::fx::FxHashMap; -use rustc_errors::{ErrorGuaranteed, Handler}; +use rustc_errors::{DiagnosticMessage, ErrorGuaranteed, Handler, SubdiagnosticMessage}; +use rustc_macros::fluent_messages; use rustc_metadata::EncodedMetadata; use rustc_middle::dep_graph::{WorkProduct, WorkProductId}; use rustc_middle::ty::TyCtxt; @@ -86,6 +87,8 @@ use rustc_span::Symbol; use rustc_span::fatal_error::FatalError; use tempfile::TempDir; +fluent_messages! { "../locales/en-US.ftl" } + pub struct PrintOnPanic String>(pub F); impl String> Drop for PrintOnPanic { From 7696f981ea8a19d4e1e261bef6ade31d4d902f38 Mon Sep 17 00:00:00 2001 From: David Wood Date: Mon, 17 Oct 2022 14:11:26 +0100 Subject: [PATCH 295/356] various: translation resources from cg backend Extend `CodegenBackend` trait with a function returning the translation resources from the codegen backend, which can be added to the complete list of resources provided to the emitter. Signed-off-by: David Wood --- src/lib.rs | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/lib.rs b/src/lib.rs index c32c837d83a8..1b7feb5f8a18 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -105,6 +105,10 @@ pub struct GccCodegenBackend { } impl CodegenBackend for GccCodegenBackend { + fn locale_resource(&self) -> &'static str { + crate::DEFAULT_LOCALE_RESOURCE + } + fn init(&self, sess: &Session) { if sess.lto() != Lto::No { sess.emit_warning(LTONotSupported {}); From 802e9026d93557e2d4ee03c7ab80aac4a665ead1 Mon Sep 17 00:00:00 2001 From: Alan Egerton Date: Wed, 22 Feb 2023 02:18:40 +0000 Subject: [PATCH 296/356] Remove type-traversal trait aliases --- src/callee.rs | 2 +- src/mono_item.rs | 2 +- src/type_of.rs | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/callee.rs b/src/callee.rs index bc68340e7a07..ba1e86562089 100644 --- a/src/callee.rs +++ b/src/callee.rs @@ -1,7 +1,7 @@ #[cfg(feature="master")] use gccjit::{FnAttribute, Visibility}; use gccjit::{FunctionType, Function}; -use rustc_middle::ty::{self, Instance, TypeVisitable}; +use rustc_middle::ty::{self, Instance, TypeVisitableExt}; use rustc_middle::ty::layout::{FnAbiOf, HasTyCtxt}; use crate::attributes; diff --git a/src/mono_item.rs b/src/mono_item.rs index 0491fffc8abf..c1f6340866ca 100644 --- a/src/mono_item.rs +++ b/src/mono_item.rs @@ -4,7 +4,7 @@ use rustc_codegen_ssa::traits::PreDefineMethods; use rustc_hir::def_id::{DefId, LOCAL_CRATE}; use rustc_middle::middle::codegen_fn_attrs::CodegenFnAttrFlags; use rustc_middle::mir::mono::{Linkage, Visibility}; -use rustc_middle::ty::{self, Instance, TypeVisitable}; +use rustc_middle::ty::{self, Instance, TypeVisitableExt}; use rustc_middle::ty::layout::{FnAbiOf, LayoutOf}; use crate::attributes; diff --git a/src/type_of.rs b/src/type_of.rs index b01bd114656c..1a4fae666f22 100644 --- a/src/type_of.rs +++ b/src/type_of.rs @@ -3,7 +3,7 @@ use std::fmt::Write; use gccjit::{Struct, Type}; use crate::rustc_codegen_ssa::traits::{BaseTypeMethods, DerivedTypeMethods, LayoutTypeMethods}; use rustc_middle::bug; -use rustc_middle::ty::{self, Ty, TypeVisitable}; +use rustc_middle::ty::{self, Ty, TypeVisitableExt}; use rustc_middle::ty::layout::{FnAbiOf, LayoutOf, TyAndLayout}; use rustc_middle::ty::print::with_no_trimmed_paths; use rustc_target::abi::{self, Abi, F32, F64, FieldsShape, Int, Integer, Pointer, PointeeInfo, Size, TyAbiInterface, Variants}; From 78f3a7ed1ffc2787205bf64fc70cfa15640fba1e Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Tue, 28 Feb 2023 18:57:08 -0500 Subject: [PATCH 297/356] Update toolchain --- rust-toolchain | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rust-toolchain b/rust-toolchain index 775d9906bf41..a6d506185dc6 100644 --- a/rust-toolchain +++ b/rust-toolchain @@ -1,3 +1,3 @@ [toolchain] -channel = "nightly-2022-08-26" +channel = "nightly-2023-02-28" components = ["rust-src", "rustc-dev", "llvm-tools-preview"] From e74f6ff54fc6c0d266387a3f04730abd43d69901 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Tue, 28 Feb 2023 22:35:10 -0500 Subject: [PATCH 298/356] Fix rebase --- src/builder.rs | 25 +++---- src/context.rs | 2 +- src/intrinsic/mod.rs | 10 +-- src/intrinsic/simd.rs | 154 ++++++++++++++++++++++-------------------- src/type_.rs | 4 -- 5 files changed, 96 insertions(+), 99 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index 05b3bacfbf91..913f5734ff0d 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -455,12 +455,12 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } #[cfg(feature="master")] - fn invoke(&mut self, typ: Type<'gcc>, fn_abi: Option<&FnAbi<'tcx, Ty<'tcx>>>, func: RValue<'gcc>, args: &[RValue<'gcc>], then: Block<'gcc>, catch: Block<'gcc>, _funclet: Option<&Funclet>) -> RValue<'gcc> { + fn invoke(&mut self, typ: Type<'gcc>, _fn_abi: Option<&FnAbi<'tcx, Ty<'tcx>>>, func: RValue<'gcc>, args: &[RValue<'gcc>], then: Block<'gcc>, catch: Block<'gcc>, _funclet: Option<&Funclet>) -> RValue<'gcc> { let try_block = self.current_func().new_block("try"); let current_block = self.block.clone(); self.block = try_block; - let call = self.call(typ, func, args, None); // TODO(antoyo): use funclet here? + let call = self.call(typ, None, func, args, None); // TODO(antoyo): use funclet here? self.block = current_block; let return_value = self.current_func() @@ -1210,23 +1210,20 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { let zero = self.cx.context.new_rvalue_zero(self.int_type); let ptr = self.cx.context.new_call(None, eh_pointer_builtin, &[zero]); - let field1_type = self.u8_type.make_pointer(); - let field1 = self.context.new_field(None, field1_type, "landing_pad_field_1"); - let field2 = self.context.new_field(None, self.i32_type, "landing_pad_field_2"); - let struct_type = self.context.new_struct_type(None, "landing_pad", &[field1, field2]); - let value = self.current_func().new_local(None, struct_type.as_type(), "landing_pad"); - let ptr = self.cx.context.new_cast(None, ptr, field1_type); - self.block.add_assignment(None, value.access_field(None, field1), ptr); - self.block.add_assignment(None, value.access_field(None, field2), zero); // TODO(antoyo): set the proper value here (the type of exception?). + let value1_type = self.u8_type.make_pointer(); + let ptr = self.cx.context.new_cast(None, ptr, value1_type); + let value1 = ptr; + let value2 = zero; // TODO(antoyo): set the proper value here (the type of exception?). - value.to_rvalue() + (value1, value2) } #[cfg(not(feature="master"))] fn cleanup_landing_pad(&mut self, _pers_fn: RValue<'gcc>) -> (RValue<'gcc>, RValue<'gcc>) { - let field1 = self.context.new_field(None, self.u8_type.make_pointer(), "landing_pad_field_1"); - let field2 = self.context.new_field(None, self.i32_type, "landing_pad_field_1"); - (field1, field2) + let value1 = self.current_func().new_local(None, self.u8_type.make_pointer(), "landing_pad0") + .to_rvalue(); + let value2 = self.current_func().new_local(None, self.i32_type, "landing_pad1").to_rvalue(); + (value1, value2) } #[cfg(feature="master")] diff --git a/src/context.rs b/src/context.rs index 9bd3710ac8ad..661681bdb50f 100644 --- a/src/context.rs +++ b/src/context.rs @@ -391,7 +391,7 @@ impl<'gcc, 'tcx> MiscMethods<'tcx> for CodegenCx<'gcc, 'tcx> { tcx, ty::ParamEnv::reveal_all(), def_id, - tcx.intern_substs(&[]), + ty::List::empty(), ) .unwrap().unwrap(); diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index b58381871a9c..2590e0e3af44 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -1202,21 +1202,21 @@ fn codegen_gnu_try<'gcc>(bx: &mut Builder<'_, 'gcc, '_>, try_func: RValue<'gcc>, let zero = bx.cx.context.new_rvalue_zero(bx.int_type); let ptr = bx.cx.context.new_call(None, eh_pointer_builtin, &[zero]); let catch_ty = bx.type_func(&[bx.type_i8p(), bx.type_i8p()], bx.type_void()); - bx.call(catch_ty, catch_func, &[data, ptr], None); + bx.call(catch_ty, None, catch_func, &[data, ptr], None); bx.ret(bx.const_i32(1)); // NOTE: the blocks must be filled before adding the try/catch, otherwise gcc will not // generate a try/catch. // FIXME(antoyo): add a check in the libgccjit API to prevent this. bx.switch_to_block(current_block); - bx.invoke(try_func_ty, try_func, &[data], then, catch, None); + bx.invoke(try_func_ty, None, try_func, &[data], then, catch, None); }); let func = unsafe { std::mem::transmute(func) }; // Note that no invoke is used here because by definition this function // can't panic (that's what it's catching). - let ret = bx.call(llty, func, &[try_func, data, catch_func], None); + let ret = bx.call(llty, None, func, &[try_func, data, catch_func], None); let i32_align = bx.tcx().data_layout.i32_align.abi; bx.store(ret, dest, i32_align); } @@ -1253,8 +1253,8 @@ fn get_rust_try_fn<'a, 'gcc, 'tcx>(cx: &'a CodegenCx<'gcc, 'tcx>, codegen: &mut ))); // `unsafe fn(unsafe fn(*mut i8) -> (), *mut i8, unsafe fn(*mut i8, *mut i8) -> ()) -> i32` let rust_fn_sig = ty::Binder::dummy(cx.tcx.mk_fn_sig( - [try_fn_ty, i8p, catch_fn_ty].iter(), - &tcx.types.i32, + [try_fn_ty, i8p, catch_fn_ty], + tcx.types.i32, false, rustc_hir::Unsafety::Unsafe, Abi::Rust, diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index b8c479970091..fca59d50974f 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -4,6 +4,7 @@ use gccjit::{BinaryOp, RValue, Type}; use rustc_codegen_ssa::base::compare_simd_types; use rustc_codegen_ssa::common::{IntPredicate, TypeKind}; +use rustc_codegen_ssa::errors::{ExpectedPointerMutability, InvalidMonomorphization}; use rustc_codegen_ssa::mir::operand::OperandRef; use rustc_codegen_ssa::mir::place::PlaceRef; use rustc_codegen_ssa::traits::{BaseTypeMethods, BuilderMethods}; @@ -295,11 +296,14 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>( (Style::Unsupported, Style::Unsupported) => { require!( false, - "unsupported cast from `{}` with element `{}` to `{}` with element `{}`", - in_ty, - in_elem, - ret_ty, - out_elem + InvalidMonomorphization::UnsupportedCast { + span, + name, + in_ty, + in_elem, + ret_ty, + out_elem + } ); }, _ => return Ok(bx.context.convert_vector(None, args[0].immediate(), llret_ty)), @@ -362,7 +366,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>( } ty::Array(elem, len) if matches!(elem.kind(), ty::Uint(ty::UintTy::U8)) - && len.try_eval_usize(bx.tcx, ty::ParamEnv::reveal_all()) + && len.try_eval_target_usize(bx.tcx, ty::ParamEnv::reveal_all()) == Some(expected_bytes) => { // Zero-extend iN to the array length: @@ -375,12 +379,13 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>( let ptr = bx.pointercast(ptr, bx.cx.type_ptr_to(array_ty)); return Ok(bx.load(array_ty, ptr, Align::ONE)); } - _ => return_error!( - "cannot return `{}`, expected `u{}` or `[u8; {}]`", + _ => return_error!(InvalidMonomorphization::CannotReturn { + span, + name, ret_ty, expected_int_bits, expected_bytes - ), + }), } } @@ -410,9 +415,9 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>( } } } - } else { - return_error!(InvalidMonomorphizationNotFloat { span, name, ty: in_ty }); - }; + else { + return_error!(InvalidMonomorphizationNotFloat { span, name, ty: in_ty }); + }; let vec_ty = bx.cx.type_vector(elem_ty, in_len); @@ -560,27 +565,32 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>( let (out_len2, _) = arg_tys[2].simd_size_and_type(bx.tcx()); require!( in_len == out_len, - "expected {} argument with length {} (same as input type `{}`), \ - found `{}` with length {}", - "second", - in_len, - in_ty, - arg_tys[1], - out_len + InvalidMonomorphization::SecondArgumentLength { + span, + name, + in_len, + in_ty, + arg_ty: arg_tys[1], + out_len + } ); require!( in_len == out_len2, - "expected {} argument with length {} (same as input type `{}`), \ - found `{}` with length {}", - "third", - in_len, - in_ty, - arg_tys[2], - out_len2 + InvalidMonomorphization::ThirdArgumentLength { + span, + name, + in_len, + in_ty, + arg_ty: arg_tys[2], + out_len: out_len2 + } ); // The return type must match the first argument type - require!(ret_ty == in_ty, "expected return type `{}`, found `{}`", in_ty, ret_ty); + require!( + ret_ty == in_ty, + InvalidMonomorphization::ExpectedReturnType { span, name, in_ty, ret_ty } + ); // This counts how many pointers fn ptr_count(t: Ty<'_>) -> usize { @@ -607,15 +617,15 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>( _ => { require!( false, - "expected element type `{}` of second argument `{}` \ - to be a pointer to the element type `{}` of the first \ - argument `{}`, found `{}` != `*_ {}`", - element_ty1, - arg_tys[1], + InvalidMonomorphization::ExpectedElementType { + span, + name, + expected_element: element_ty1, + second_arg: arg_tys[1], in_elem, in_ty, - element_ty1, - in_elem + mutability: ExpectedPointerMutability::Not, + } ); unreachable!(); } @@ -631,10 +641,12 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>( _ => { require!( false, - "expected element type `{}` of third argument `{}` \ - to be a signed integer type", - element_ty2, - arg_tys[2] + InvalidMonomorphization::ThirdArgElementType { + span, + name, + expected_element: element_ty2, + third_arg: arg_tys[2] + } ); } } @@ -660,23 +672,25 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>( let (element_len2, _) = arg_tys[2].simd_size_and_type(bx.tcx()); require!( in_len == element_len1, - "expected {} argument with length {} (same as input type `{}`), \ - found `{}` with length {}", - "second", - in_len, - in_ty, - arg_tys[1], - element_len1 + InvalidMonomorphization::SecondArgumentLength { + span, + name, + in_len, + in_ty, + arg_ty: arg_tys[1], + out_len: element_len1 + } ); require!( in_len == element_len2, - "expected {} argument with length {} (same as input type `{}`), \ - found `{}` with length {}", - "third", - in_len, - in_ty, - arg_tys[2], - element_len2 + InvalidMonomorphization::ThirdArgumentLength { + span, + name, + in_len, + in_ty, + arg_ty: arg_tys[2], + out_len: element_len2 + } ); // This counts how many pointers @@ -707,15 +721,15 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>( _ => { require!( false, - "expected element type `{}` of second argument `{}` \ - to be a pointer to the element type `{}` of the first \ - argument `{}`, found `{}` != `*mut {}`", - element_ty1, - arg_tys[1], + InvalidMonomorphization::ExpectedElementType { + span, + name, + expected_element: element_ty1, + second_arg: arg_tys[1], in_elem, in_ty, - element_ty1, - in_elem + mutability: ExpectedPointerMutability::Mut, + } ); unreachable!(); } @@ -730,10 +744,12 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>( _ => { require!( false, - "expected element type `{}` of third argument `{}` \ - be a signed integer type", - element_ty2, - arg_tys[2] + InvalidMonomorphization::ThirdArgElementType { + span, + name, + expected_element: element_ty2, + third_arg: arg_tys[2] + } ); } } @@ -816,18 +832,6 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>( }); } }; - let builtin_name = - match (signed, is_add, in_len, elem_width) { - (true, true, 32, 8) => "__builtin_ia32_paddsb256", // TODO(antoyo): cast arguments to unsigned. - (false, true, 32, 8) => "__builtin_ia32_paddusb256", - (true, true, 16, 16) => "__builtin_ia32_paddsw256", - (false, true, 16, 16) => "__builtin_ia32_paddusw256", - (true, false, 16, 16) => "__builtin_ia32_psubsw256", - (false, false, 16, 16) => "__builtin_ia32_psubusw256", - (true, false, 32, 8) => "__builtin_ia32_psubsb256", - (false, false, 32, 8) => "__builtin_ia32_psubusb256", - _ => unimplemented!("signed: {}, is_add: {}, in_len: {}, elem_width: {}", signed, is_add, in_len, elem_width), - }; let result = match (signed, is_add) { diff --git a/src/type_.rs b/src/type_.rs index eacd76c6ea0e..929499666173 100644 --- a/src/type_.rs +++ b/src/type_.rs @@ -247,10 +247,6 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { pub fn type_named_struct(&self, name: &str) -> Struct<'gcc> { self.context.new_opaque_struct_type(None, name) } - - pub fn type_bool(&self) -> Type<'gcc> { - self.context.new_type::() - } } pub fn struct_fields<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, layout: TyAndLayout<'tcx>) -> (Vec>, bool) { From d8b5a3eaa927c0b8730d3fb3e4cd0731bbe48813 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Tue, 28 Feb 2023 22:39:50 -0500 Subject: [PATCH 299/356] Fix to examples --- example/mini_core.rs | 17 +++++++++++++---- example/mini_core_hello_world.rs | 1 + src/common.rs | 4 ++-- 3 files changed, 16 insertions(+), 6 deletions(-) diff --git a/example/mini_core.rs b/example/mini_core.rs index b23ecda35d3e..637b8dc53fef 100644 --- a/example/mini_core.rs +++ b/example/mini_core.rs @@ -17,6 +17,9 @@ pub trait Sized {} #[lang = "destruct"] pub trait Destruct {} +#[lang = "tuple_trait"] +pub trait Tuple {} + #[lang = "unsize"] pub trait Unsize {} @@ -396,7 +399,7 @@ pub struct PhantomData; #[lang = "fn_once"] #[rustc_paren_sugar] -pub trait FnOnce { +pub trait FnOnce { #[lang = "fn_once_output"] type Output; @@ -405,7 +408,7 @@ pub trait FnOnce { #[lang = "fn_mut"] #[rustc_paren_sugar] -pub trait FnMut: FnOnce { +pub trait FnMut: FnOnce { extern "rust-call" fn call_mut(&mut self, args: Args) -> Self::Output; } @@ -418,8 +421,8 @@ pub fn panic(_msg: &'static str) -> ! { } } -#[lang = "panic_no_unwind"] -fn panic_no_unwind() -> ! { +#[lang = "panic_cannot_unwind"] +fn panic_cannot_unwind() -> ! { unsafe { libc::puts("Panicking\n\0" as *const str as *const u8); intrinsics::abort(); @@ -531,16 +534,22 @@ pub mod intrinsics { use crate::Sized; extern "rust-intrinsic" { + #[rustc_safe_intrinsic] pub fn abort() -> !; + #[rustc_safe_intrinsic] pub fn size_of() -> usize; pub fn size_of_val(val: *const T) -> usize; + #[rustc_safe_intrinsic] pub fn min_align_of() -> usize; pub fn min_align_of_val(val: *const T) -> usize; pub fn copy(src: *const T, dst: *mut T, count: usize); pub fn transmute(e: T) -> U; pub fn ctlz_nonzero(x: T) -> T; + #[rustc_safe_intrinsic] pub fn needs_drop() -> bool; + #[rustc_safe_intrinsic] pub fn bitreverse(x: T) -> T; + #[rustc_safe_intrinsic] pub fn bswap(x: T) -> T; pub fn write_bytes(dst: *mut T, val: u8, count: usize); pub fn unreachable() -> !; diff --git a/example/mini_core_hello_world.rs b/example/mini_core_hello_world.rs index 7b10425e800f..993a31e68eab 100644 --- a/example/mini_core_hello_world.rs +++ b/example/mini_core_hello_world.rs @@ -85,6 +85,7 @@ fn start( main: fn() -> T, argc: isize, argv: *const *const u8, + _sigpipe: u8, ) -> isize { if argc == 3 { unsafe { puts(*argv); } diff --git a/src/common.rs b/src/common.rs index 54325e1277b0..12c0b3923234 100644 --- a/src/common.rs +++ b/src/common.rs @@ -115,8 +115,8 @@ impl<'gcc, 'tcx> ConstMethods<'tcx> for CodegenCx<'gcc, 'tcx> { self.const_uint(self.usize_type, i) } - fn const_u8(&self, _i: u8) -> RValue<'gcc> { - unimplemented!(); + fn const_u8(&self, i: u8) -> RValue<'gcc> { + self.const_uint(self.type_u8(), i as u64) } fn const_real(&self, typ: Type<'gcc>, val: f64) -> RValue<'gcc> { From b4f83c6ed817bc42b1ea2e2c582488cfe5f6f1da Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Thu, 2 Mar 2023 17:15:57 -0500 Subject: [PATCH 300/356] Fix error --- ...0024-core-Disable-portable-simd-test.patch | 32 ------------------- src/common.rs | 2 +- src/consts.rs | 9 +++--- 3 files changed, 6 insertions(+), 37 deletions(-) delete mode 100644 patches/0024-core-Disable-portable-simd-test.patch diff --git a/patches/0024-core-Disable-portable-simd-test.patch b/patches/0024-core-Disable-portable-simd-test.patch deleted file mode 100644 index 7ea0eebe6a12..000000000000 --- a/patches/0024-core-Disable-portable-simd-test.patch +++ /dev/null @@ -1,32 +0,0 @@ -From f845df4056f5ba16b9f5bd703460c4ac40ea03b9 Mon Sep 17 00:00:00 2001 -From: Antoni Boucher -Date: Fri, 26 Aug 2022 20:38:58 -0400 -Subject: [PATCH] Edit - ---- - library/core/tests/lib.rs | 2 -- - 1 file changed, 2 deletions(-) - -diff --git a/library/core/tests/lib.rs b/library/core/tests/lib.rs -index 59510d3..179bf26 100644 ---- a/library/core/tests/lib.rs -+++ b/library/core/tests/lib.rs -@@ -77,7 +77,6 @@ - #![feature(unwrap_infallible)] - #![feature(result_into_ok_or_err)] - #![feature(pointer_byte_offsets)] --#![feature(portable_simd)] - #![feature(ptr_metadata)] - #![feature(once_cell)] - #![feature(option_result_contains)] -@@ -135,7 +134,6 @@ mod pin; - mod pin_macro; - mod ptr; - mod result; --mod simd; - mod slice; - mod str; - mod str_lossy; --- -2.26.2.7.g19db9cfb68.dirty - diff --git a/src/common.rs b/src/common.rs index 12c0b3923234..617c7e8640a9 100644 --- a/src/common.rs +++ b/src/common.rs @@ -241,7 +241,7 @@ impl<'gcc, 'tcx> ConstMethods<'tcx> for CodegenCx<'gcc, 'tcx> { let value = if layout.size == Size::ZERO { let value = self.const_usize(alloc.inner().align.bytes()); - self.context.new_cast(None, value, ty) + self.const_bitcast(value, ty) } else { let init = const_alloc_to_gcc(self, alloc); diff --git a/src/consts.rs b/src/consts.rs index b651b60924f7..86a7f78de270 100644 --- a/src/consts.rs +++ b/src/consts.rs @@ -341,7 +341,7 @@ pub fn codegen_static_initializer<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, def_id fn check_and_apply_linkage<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, attrs: &CodegenFnAttrs, ty: Ty<'tcx>, sym: &str) -> LValue<'gcc> { let is_tls = attrs.flags.contains(CodegenFnAttrFlags::THREAD_LOCAL); - let llty = cx.layout_of(ty).gcc_type(cx); + let gcc_type = cx.layout_of(ty).gcc_type(cx); if let Some(linkage) = attrs.import_linkage { // Declare a symbol `foo` with the desired linkage. let global1 = cx.declare_global_with_linkage(&sym, cx.type_i8(), base::global_linkage_to_gcc(linkage)); @@ -354,9 +354,10 @@ fn check_and_apply_linkage<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, attrs: &Codeg // zero. let mut real_name = "_rust_extern_with_linkage_".to_string(); real_name.push_str(&sym); - let global2 = cx.define_global(&real_name, llty, is_tls, attrs.link_section); + let global2 = cx.define_global(&real_name, gcc_type, is_tls, attrs.link_section); // TODO(antoyo): set linkage. - global2.global_set_initializer_rvalue(global1.get_address(None)); + let value = cx.const_ptrcast(global1.get_address(None), gcc_type); + global2.global_set_initializer_rvalue(value); // TODO(antoyo): use global_set_initializer() when it will work. global2 } @@ -370,6 +371,6 @@ fn check_and_apply_linkage<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, attrs: &Codeg // don't do this then linker errors can be generated where the linker // complains that one object files has a thread local version of the // symbol and another one doesn't. - cx.declare_global(&sym, llty, GlobalKind::Imported, is_tls, attrs.link_section) + cx.declare_global(&sym, gcc_type, GlobalKind::Imported, is_tls, attrs.link_section) } } From 74506d3bb1b03ddad2637ceeb3e72b40bd803e26 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Thu, 2 Mar 2023 23:30:11 +0100 Subject: [PATCH 301/356] Regen intrinsics --- src/intrinsic/archs.rs | 74 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 72 insertions(+), 2 deletions(-) diff --git a/src/intrinsic/archs.rs b/src/intrinsic/archs.rs index 3879fcb1d982..8a4559355ea6 100644 --- a/src/intrinsic/archs.rs +++ b/src/intrinsic/archs.rs @@ -34,6 +34,7 @@ match name { "llvm.aarch64.dmb" => "__builtin_arm_dmb", "llvm.aarch64.dsb" => "__builtin_arm_dsb", "llvm.aarch64.isb" => "__builtin_arm_isb", + "llvm.aarch64.prefetch" => "__builtin_arm_prefetch", "llvm.aarch64.sve.aesd" => "__builtin_sve_svaesd_u8", "llvm.aarch64.sve.aese" => "__builtin_sve_svaese_u8", "llvm.aarch64.sve.aesimc" => "__builtin_sve_svaesimc_u8", @@ -90,7 +91,6 @@ match name { "llvm.amdgcn.fdot2.bf16.bf16" => "__builtin_amdgcn_fdot2_bf16_bf16", "llvm.amdgcn.fdot2.f16.f16" => "__builtin_amdgcn_fdot2_f16_f16", "llvm.amdgcn.fdot2.f32.bf16" => "__builtin_amdgcn_fdot2_f32_bf16", - "llvm.amdgcn.fmed3" => "__builtin_amdgcn_fmed3", "llvm.amdgcn.fmul.legacy" => "__builtin_amdgcn_fmul_legacy", "llvm.amdgcn.groupstaticsize" => "__builtin_amdgcn_groupstaticsize", "llvm.amdgcn.iglp.opt" => "__builtin_amdgcn_iglp_opt", @@ -151,6 +151,7 @@ match name { "llvm.amdgcn.msad.u8" => "__builtin_amdgcn_msad_u8", "llvm.amdgcn.perm" => "__builtin_amdgcn_perm", "llvm.amdgcn.permlane16" => "__builtin_amdgcn_permlane16", + "llvm.amdgcn.permlane64" => "__builtin_amdgcn_permlane64", "llvm.amdgcn.permlanex16" => "__builtin_amdgcn_permlanex16", "llvm.amdgcn.qsad.pk.u16.u8" => "__builtin_amdgcn_qsad_pk_u16_u8", "llvm.amdgcn.queue.ptr" => "__builtin_amdgcn_queue_ptr", @@ -175,6 +176,7 @@ match name { "llvm.amdgcn.s.setprio" => "__builtin_amdgcn_s_setprio", "llvm.amdgcn.s.setreg" => "__builtin_amdgcn_s_setreg", "llvm.amdgcn.s.sleep" => "__builtin_amdgcn_s_sleep", + "llvm.amdgcn.s.wait.event.export.ready" => "__builtin_amdgcn_s_wait_event_export_ready", "llvm.amdgcn.s.waitcnt" => "__builtin_amdgcn_s_waitcnt", "llvm.amdgcn.sad.hi.u8" => "__builtin_amdgcn_sad_hi_u8", "llvm.amdgcn.sad.u16" => "__builtin_amdgcn_sad_u16", @@ -663,7 +665,7 @@ match name { "llvm.hexagon.F2.sfmpy" => "__builtin_HEXAGON_F2_sfmpy", "llvm.hexagon.F2.sfsub" => "__builtin_HEXAGON_F2_sfsub", "llvm.hexagon.L2.loadw.locked" => "__builtin_HEXAGON_L2_loadw_locked", - "llvm.hexagon.L4.loadd.locked" => "__builtin_HEXAGON_L4_loadd_locked", + "llvm.hexagon.L4.loadd.locked" => "__builtin__HEXAGON_L4_loadd_locked", "llvm.hexagon.M2.acci" => "__builtin_HEXAGON_M2_acci", "llvm.hexagon.M2.accii" => "__builtin_HEXAGON_M2_accii", "llvm.hexagon.M2.cmaci.s0" => "__builtin_HEXAGON_M2_cmaci_s0", @@ -1319,6 +1321,8 @@ match name { "llvm.hexagon.V6.vadd.qf32.mix.128B" => "__builtin_HEXAGON_V6_vadd_qf32_mix_128B", "llvm.hexagon.V6.vadd.sf" => "__builtin_HEXAGON_V6_vadd_sf", "llvm.hexagon.V6.vadd.sf.128B" => "__builtin_HEXAGON_V6_vadd_sf_128B", + "llvm.hexagon.V6.vadd.sf.bf" => "__builtin_HEXAGON_V6_vadd_sf_bf", + "llvm.hexagon.V6.vadd.sf.bf.128B" => "__builtin_HEXAGON_V6_vadd_sf_bf_128B", "llvm.hexagon.V6.vadd.sf.hf" => "__builtin_HEXAGON_V6_vadd_sf_hf", "llvm.hexagon.V6.vadd.sf.hf.128B" => "__builtin_HEXAGON_V6_vadd_sf_hf_128B", "llvm.hexagon.V6.vadd.sf.sf" => "__builtin_HEXAGON_V6_vadd_sf_sf", @@ -1509,14 +1513,24 @@ match name { "llvm.hexagon.V6.vcl0w.128B" => "__builtin_HEXAGON_V6_vcl0w_128B", "llvm.hexagon.V6.vcombine" => "__builtin_HEXAGON_V6_vcombine", "llvm.hexagon.V6.vcombine.128B" => "__builtin_HEXAGON_V6_vcombine_128B", + "llvm.hexagon.V6.vconv.h.hf" => "__builtin_HEXAGON_V6_vconv_h_hf", + "llvm.hexagon.V6.vconv.h.hf.128B" => "__builtin_HEXAGON_V6_vconv_h_hf_128B", + "llvm.hexagon.V6.vconv.hf.h" => "__builtin_HEXAGON_V6_vconv_hf_h", + "llvm.hexagon.V6.vconv.hf.h.128B" => "__builtin_HEXAGON_V6_vconv_hf_h_128B", "llvm.hexagon.V6.vconv.hf.qf16" => "__builtin_HEXAGON_V6_vconv_hf_qf16", "llvm.hexagon.V6.vconv.hf.qf16.128B" => "__builtin_HEXAGON_V6_vconv_hf_qf16_128B", "llvm.hexagon.V6.vconv.hf.qf32" => "__builtin_HEXAGON_V6_vconv_hf_qf32", "llvm.hexagon.V6.vconv.hf.qf32.128B" => "__builtin_HEXAGON_V6_vconv_hf_qf32_128B", "llvm.hexagon.V6.vconv.sf.qf32" => "__builtin_HEXAGON_V6_vconv_sf_qf32", "llvm.hexagon.V6.vconv.sf.qf32.128B" => "__builtin_HEXAGON_V6_vconv_sf_qf32_128B", + "llvm.hexagon.V6.vconv.sf.w" => "__builtin_HEXAGON_V6_vconv_sf_w", + "llvm.hexagon.V6.vconv.sf.w.128B" => "__builtin_HEXAGON_V6_vconv_sf_w_128B", + "llvm.hexagon.V6.vconv.w.sf" => "__builtin_HEXAGON_V6_vconv_w_sf", + "llvm.hexagon.V6.vconv.w.sf.128B" => "__builtin_HEXAGON_V6_vconv_w_sf_128B", "llvm.hexagon.V6.vcvt.b.hf" => "__builtin_HEXAGON_V6_vcvt_b_hf", "llvm.hexagon.V6.vcvt.b.hf.128B" => "__builtin_HEXAGON_V6_vcvt_b_hf_128B", + "llvm.hexagon.V6.vcvt.bf.sf" => "__builtin_HEXAGON_V6_vcvt_bf_sf", + "llvm.hexagon.V6.vcvt.bf.sf.128B" => "__builtin_HEXAGON_V6_vcvt_bf_sf_128B", "llvm.hexagon.V6.vcvt.h.hf" => "__builtin_HEXAGON_V6_vcvt_h_hf", "llvm.hexagon.V6.vcvt.h.hf.128B" => "__builtin_HEXAGON_V6_vcvt_h_hf_128B", "llvm.hexagon.V6.vcvt.hf.b" => "__builtin_HEXAGON_V6_vcvt_hf_b", @@ -1649,6 +1663,14 @@ match name { "llvm.hexagon.V6.vgtb.or.128B" => "__builtin_HEXAGON_V6_vgtb_or_128B", "llvm.hexagon.V6.vgtb.xor" => "__builtin_HEXAGON_V6_vgtb_xor", "llvm.hexagon.V6.vgtb.xor.128B" => "__builtin_HEXAGON_V6_vgtb_xor_128B", + "llvm.hexagon.V6.vgtbf" => "__builtin_HEXAGON_V6_vgtbf", + "llvm.hexagon.V6.vgtbf.128B" => "__builtin_HEXAGON_V6_vgtbf_128B", + "llvm.hexagon.V6.vgtbf.and" => "__builtin_HEXAGON_V6_vgtbf_and", + "llvm.hexagon.V6.vgtbf.and.128B" => "__builtin_HEXAGON_V6_vgtbf_and_128B", + "llvm.hexagon.V6.vgtbf.or" => "__builtin_HEXAGON_V6_vgtbf_or", + "llvm.hexagon.V6.vgtbf.or.128B" => "__builtin_HEXAGON_V6_vgtbf_or_128B", + "llvm.hexagon.V6.vgtbf.xor" => "__builtin_HEXAGON_V6_vgtbf_xor", + "llvm.hexagon.V6.vgtbf.xor.128B" => "__builtin_HEXAGON_V6_vgtbf_xor_128B", "llvm.hexagon.V6.vgth" => "__builtin_HEXAGON_V6_vgth", "llvm.hexagon.V6.vgth.128B" => "__builtin_HEXAGON_V6_vgth_128B", "llvm.hexagon.V6.vgth.and" => "__builtin_HEXAGON_V6_vgth_and", @@ -1751,6 +1773,8 @@ match name { "llvm.hexagon.V6.vlutvwh.oracci.128B" => "__builtin_HEXAGON_V6_vlutvwh_oracci_128B", "llvm.hexagon.V6.vlutvwhi" => "__builtin_HEXAGON_V6_vlutvwhi", "llvm.hexagon.V6.vlutvwhi.128B" => "__builtin_HEXAGON_V6_vlutvwhi_128B", + "llvm.hexagon.V6.vmax.bf" => "__builtin_HEXAGON_V6_vmax_bf", + "llvm.hexagon.V6.vmax.bf.128B" => "__builtin_HEXAGON_V6_vmax_bf_128B", "llvm.hexagon.V6.vmax.hf" => "__builtin_HEXAGON_V6_vmax_hf", "llvm.hexagon.V6.vmax.hf.128B" => "__builtin_HEXAGON_V6_vmax_hf_128B", "llvm.hexagon.V6.vmax.sf" => "__builtin_HEXAGON_V6_vmax_sf", @@ -1765,6 +1789,8 @@ match name { "llvm.hexagon.V6.vmaxuh.128B" => "__builtin_HEXAGON_V6_vmaxuh_128B", "llvm.hexagon.V6.vmaxw" => "__builtin_HEXAGON_V6_vmaxw", "llvm.hexagon.V6.vmaxw.128B" => "__builtin_HEXAGON_V6_vmaxw_128B", + "llvm.hexagon.V6.vmin.bf" => "__builtin_HEXAGON_V6_vmin_bf", + "llvm.hexagon.V6.vmin.bf.128B" => "__builtin_HEXAGON_V6_vmin_bf_128B", "llvm.hexagon.V6.vmin.hf" => "__builtin_HEXAGON_V6_vmin_hf", "llvm.hexagon.V6.vmin.hf.128B" => "__builtin_HEXAGON_V6_vmin_hf_128B", "llvm.hexagon.V6.vmin.sf" => "__builtin_HEXAGON_V6_vmin_sf", @@ -1825,6 +1851,10 @@ match name { "llvm.hexagon.V6.vmpy.qf32.qf16.128B" => "__builtin_HEXAGON_V6_vmpy_qf32_qf16_128B", "llvm.hexagon.V6.vmpy.qf32.sf" => "__builtin_HEXAGON_V6_vmpy_qf32_sf", "llvm.hexagon.V6.vmpy.qf32.sf.128B" => "__builtin_HEXAGON_V6_vmpy_qf32_sf_128B", + "llvm.hexagon.V6.vmpy.sf.bf" => "__builtin_HEXAGON_V6_vmpy_sf_bf", + "llvm.hexagon.V6.vmpy.sf.bf.128B" => "__builtin_HEXAGON_V6_vmpy_sf_bf_128B", + "llvm.hexagon.V6.vmpy.sf.bf.acc" => "__builtin_HEXAGON_V6_vmpy_sf_bf_acc", + "llvm.hexagon.V6.vmpy.sf.bf.acc.128B" => "__builtin_HEXAGON_V6_vmpy_sf_bf_acc_128B", "llvm.hexagon.V6.vmpy.sf.hf" => "__builtin_HEXAGON_V6_vmpy_sf_hf", "llvm.hexagon.V6.vmpy.sf.hf.128B" => "__builtin_HEXAGON_V6_vmpy_sf_hf_128B", "llvm.hexagon.V6.vmpy.sf.hf.acc" => "__builtin_HEXAGON_V6_vmpy_sf_hf_acc", @@ -2091,6 +2121,8 @@ match name { "llvm.hexagon.V6.vsub.qf32.mix.128B" => "__builtin_HEXAGON_V6_vsub_qf32_mix_128B", "llvm.hexagon.V6.vsub.sf" => "__builtin_HEXAGON_V6_vsub_sf", "llvm.hexagon.V6.vsub.sf.128B" => "__builtin_HEXAGON_V6_vsub_sf_128B", + "llvm.hexagon.V6.vsub.sf.bf" => "__builtin_HEXAGON_V6_vsub_sf_bf", + "llvm.hexagon.V6.vsub.sf.bf.128B" => "__builtin_HEXAGON_V6_vsub_sf_bf_128B", "llvm.hexagon.V6.vsub.sf.hf" => "__builtin_HEXAGON_V6_vsub_sf_hf", "llvm.hexagon.V6.vsub.sf.hf.128B" => "__builtin_HEXAGON_V6_vsub_sf_hf_128B", "llvm.hexagon.V6.vsub.sf.sf" => "__builtin_HEXAGON_V6_vsub_sf_sf", @@ -5674,6 +5706,10 @@ match name { "llvm.x86.3dnowa.pfnacc" => "__builtin_ia32_pfnacc", "llvm.x86.3dnowa.pfpnacc" => "__builtin_ia32_pfpnacc", "llvm.x86.3dnowa.pi2fw" => "__builtin_ia32_pi2fw", + "llvm.x86.aadd32" => "__builtin_ia32_aadd32", + "llvm.x86.aadd64" => "__builtin_ia32_aadd64", + "llvm.x86.aand32" => "__builtin_ia32_aand32", + "llvm.x86.aand64" => "__builtin_ia32_aand64", "llvm.x86.addcarry.u32" => "__builtin_ia32_addcarry_u32", "llvm.x86.addcarry.u64" => "__builtin_ia32_addcarry_u64", "llvm.x86.addcarryx.u32" => "__builtin_ia32_addcarryx_u32", @@ -5692,6 +5728,8 @@ match name { "llvm.x86.aesni.aesenclast.512" => "__builtin_ia32_aesenclast512", "llvm.x86.aesni.aesimc" => "__builtin_ia32_aesimc128", "llvm.x86.aesni.aeskeygenassist" => "__builtin_ia32_aeskeygenassist128", + "llvm.x86.aor32" => "__builtin_ia32_aor32", + "llvm.x86.aor64" => "__builtin_ia32_aor64", "llvm.x86.avx.addsub.pd.256" => "__builtin_ia32_addsubpd256", "llvm.x86.avx.addsub.ps.256" => "__builtin_ia32_addsubps256", "llvm.x86.avx.blend.pd.256" => "__builtin_ia32_blendpd256", @@ -5904,6 +5942,18 @@ match name { "llvm.x86.avx2.vbroadcast.ss.ps.256" => "__builtin_ia32_vbroadcastss_ps256", "llvm.x86.avx2.vextracti128" => "__builtin_ia32_extract128i256", "llvm.x86.avx2.vinserti128" => "__builtin_ia32_insert128i256", + "llvm.x86.avx2.vpdpbssd.128" => "__builtin_ia32_vpdpbssd128", + "llvm.x86.avx2.vpdpbssd.256" => "__builtin_ia32_vpdpbssd256", + "llvm.x86.avx2.vpdpbssds.128" => "__builtin_ia32_vpdpbssds128", + "llvm.x86.avx2.vpdpbssds.256" => "__builtin_ia32_vpdpbssds256", + "llvm.x86.avx2.vpdpbsud.128" => "__builtin_ia32_vpdpbsud128", + "llvm.x86.avx2.vpdpbsud.256" => "__builtin_ia32_vpdpbsud256", + "llvm.x86.avx2.vpdpbsuds.128" => "__builtin_ia32_vpdpbsuds128", + "llvm.x86.avx2.vpdpbsuds.256" => "__builtin_ia32_vpdpbsuds256", + "llvm.x86.avx2.vpdpbuud.128" => "__builtin_ia32_vpdpbuud128", + "llvm.x86.avx2.vpdpbuud.256" => "__builtin_ia32_vpdpbuud256", + "llvm.x86.avx2.vpdpbuuds.128" => "__builtin_ia32_vpdpbuuds128", + "llvm.x86.avx2.vpdpbuuds.256" => "__builtin_ia32_vpdpbuuds256", "llvm.x86.avx2.vperm2i128" => "__builtin_ia32_permti256", "llvm.x86.avx512.add.pd.512" => "__builtin_ia32_addpd512", "llvm.x86.avx512.add.ps.512" => "__builtin_ia32_addps512", @@ -7406,6 +7456,8 @@ match name { "llvm.x86.avx512fp16.vcvtusi642sh" => "__builtin_ia32_vcvtusi642sh", "llvm.x86.avx512fp16.vfmaddsub.ph.128" => "__builtin_ia32_vfmaddsubph", "llvm.x86.avx512fp16.vfmaddsub.ph.256" => "__builtin_ia32_vfmaddsubph256", + "llvm.x86.axor32" => "__builtin_ia32_axor32", + "llvm.x86.axor64" => "__builtin_ia32_axor64", "llvm.x86.bmi.bextr.32" => "__builtin_ia32_bextr_u32", "llvm.x86.bmi.bextr.64" => "__builtin_ia32_bextr_u64", "llvm.x86.bmi.bzhi.32" => "__builtin_ia32_bzhi_si", @@ -7420,6 +7472,8 @@ match name { "llvm.x86.clui" => "__builtin_ia32_clui", "llvm.x86.clwb" => "__builtin_ia32_clwb", "llvm.x86.clzero" => "__builtin_ia32_clzero", + "llvm.x86.cmpccxadd32" => "__builtin_ia32_cmpccxadd32", + "llvm.x86.cmpccxadd64" => "__builtin_ia32_cmpccxadd64", "llvm.x86.directstore32" => "__builtin_ia32_directstore_u32", "llvm.x86.directstore64" => "__builtin_ia32_directstore_u64", "llvm.x86.enqcmd" => "__builtin_ia32_enqcmd", @@ -7851,6 +7905,8 @@ match name { "llvm.x86.tdpbusd.internal" => "__builtin_ia32_tdpbusd_internal", "llvm.x86.tdpbuud" => "__builtin_ia32_tdpbuud", "llvm.x86.tdpbuud.internal" => "__builtin_ia32_tdpbuud_internal", + "llvm.x86.tdpfp16ps" => "__builtin_ia32_tdpfp16ps", + "llvm.x86.tdpfp16ps.internal" => "__builtin_ia32_tdpfp16ps_internal", "llvm.x86.testui" => "__builtin_ia32_testui", "llvm.x86.tileloadd64" => "__builtin_ia32_tileloadd64", "llvm.x86.tileloadd64.internal" => "__builtin_ia32_tileloadd64_internal", @@ -7864,6 +7920,20 @@ match name { "llvm.x86.tpause" => "__builtin_ia32_tpause", "llvm.x86.umonitor" => "__builtin_ia32_umonitor", "llvm.x86.umwait" => "__builtin_ia32_umwait", + "llvm.x86.vbcstnebf162ps128" => "__builtin_ia32_vbcstnebf162ps128", + "llvm.x86.vbcstnebf162ps256" => "__builtin_ia32_vbcstnebf162ps256", + "llvm.x86.vbcstnesh2ps128" => "__builtin_ia32_vbcstnesh2ps128", + "llvm.x86.vbcstnesh2ps256" => "__builtin_ia32_vbcstnesh2ps256", + "llvm.x86.vcvtneebf162ps128" => "__builtin_ia32_vcvtneebf162ps128", + "llvm.x86.vcvtneebf162ps256" => "__builtin_ia32_vcvtneebf162ps256", + "llvm.x86.vcvtneeph2ps128" => "__builtin_ia32_vcvtneeph2ps128", + "llvm.x86.vcvtneeph2ps256" => "__builtin_ia32_vcvtneeph2ps256", + "llvm.x86.vcvtneobf162ps128" => "__builtin_ia32_vcvtneobf162ps128", + "llvm.x86.vcvtneobf162ps256" => "__builtin_ia32_vcvtneobf162ps256", + "llvm.x86.vcvtneoph2ps128" => "__builtin_ia32_vcvtneoph2ps128", + "llvm.x86.vcvtneoph2ps256" => "__builtin_ia32_vcvtneoph2ps256", + "llvm.x86.vcvtneps2bf16128" => "__builtin_ia32_vcvtneps2bf16128", + "llvm.x86.vcvtneps2bf16256" => "__builtin_ia32_vcvtneps2bf16256", "llvm.x86.vcvtph2ps.128" => "__builtin_ia32_vcvtph2ps", "llvm.x86.vcvtph2ps.256" => "__builtin_ia32_vcvtph2ps256", "llvm.x86.vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph", From a2f499f05f431d1aaeea605c396e55adb238d799 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 4 Mar 2023 14:26:00 -0500 Subject: [PATCH 302/356] Fix tests --- Cargo.lock | 4 +- locales/en-US.ftl | 3 ++ ...022-core-Disable-not-compiling-tests.patch | 47 ++++++------------- rust-toolchain | 2 +- src/builder.rs | 6 +-- src/common.rs | 2 +- src/consts.rs | 18 ++++++- src/errors.rs | 6 +++ src/type_.rs | 16 ++----- src/type_of.rs | 8 +++- test.sh | 3 ++ 11 files changed, 59 insertions(+), 56 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index b2013db3e3b3..ac0fc0eeb7e9 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -35,7 +35,7 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" -source = "git+https://github.com/antoyo/gccjit.rs#1bd270d0d130fe31807cfbe509ca095c082e5848" +source = "git+https://github.com/antoyo/gccjit.rs#eefb8c662d61477f34b7c32d26bcda5f1ef08432" dependencies = [ "gccjit_sys", ] @@ -43,7 +43,7 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" -source = "git+https://github.com/antoyo/gccjit.rs#1bd270d0d130fe31807cfbe509ca095c082e5848" +source = "git+https://github.com/antoyo/gccjit.rs#eefb8c662d61477f34b7c32d26bcda5f1ef08432" dependencies = [ "libc 0.1.12", ] diff --git a/locales/en-US.ftl b/locales/en-US.ftl index 6101b28ab0cd..2181d49eeef6 100644 --- a/locales/en-US.ftl +++ b/locales/en-US.ftl @@ -60,3 +60,6 @@ codegen_gcc_invalid_monomorphization_unsupported_cast = codegen_gcc_invalid_monomorphization_unsupported_operation = invalid monomorphization of `{$name}` intrinsic: unsupported operation on `{$in_ty}` with element `{$in_elem}` + +codegen_gcc_invalid_minimum_alignment = + invalid minimum global alignment: {$err} diff --git a/patches/0022-core-Disable-not-compiling-tests.patch b/patches/0022-core-Disable-not-compiling-tests.patch index 301b3f9bde4d..4db56fa3bd2c 100644 --- a/patches/0022-core-Disable-not-compiling-tests.patch +++ b/patches/0022-core-Disable-not-compiling-tests.patch @@ -18,7 +18,7 @@ new file mode 100644 index 0000000..46fd999 --- /dev/null +++ b/library/core/tests/Cargo.toml -@@ -0,0 +1,8 @@ +@@ -0,0 +1,12 @@ +[package] +name = "core" +version = "0.0.0" @@ -27,37 +27,18 @@ index 0000000..46fd999 +[lib] +name = "coretests" +path = "lib.rs" -diff --git a/library/core/tests/num/flt2dec/mod.rs b/library/core/tests/num/flt2dec/mod.rs -index a35897e..f0bf645 100644 ---- a/library/core/tests/num/flt2dec/mod.rs -+++ b/library/core/tests/num/flt2dec/mod.rs -@@ -13,7 +13,6 @@ mod strategy { - mod dragon; - mod grisu; - } --mod random; - - pub fn decode_finite(v: T) -> Decoded { - match decode(v).1 { -diff --git a/library/core/tests/slice.rs b/library/core/tests/slice.rs -index 6609bc3..241b497 100644 ---- a/library/core/tests/slice.rs -+++ b/library/core/tests/slice.rs -@@ -1209,6 +1209,7 @@ fn brute_force_rotate_test_1() { - } - } - -+/* - #[test] - #[cfg(not(target_arch = "wasm32"))] - fn sort_unstable() { -@@ -1394,6 +1395,7 @@ fn partition_at_index() { - v.select_nth_unstable(0); - assert!(v == [0xDEADBEEF]); - } -+*/ - - #[test] - #[should_panic(expected = "index 0 greater than length of slice")] ++ ++[dependencies] ++rand = { version = "0.8.5", default-features = false } ++rand_xorshift = { version = "0.3.0", default-features = false } +diff --git a/library/core/tests/lib.rs b/library/core/tests/lib.rs +index 42a26ae..5ac1042 100644 +--- a/library/core/tests/lib.rs ++++ b/library/core/tests/lib.rs +@@ -1,3 +1,4 @@ ++#![cfg(test)] + #![feature(alloc_layout_extra)] + #![feature(array_chunks)] + #![feature(array_methods)] -- 2.21.0 (Apple Git-122) diff --git a/rust-toolchain b/rust-toolchain index a6d506185dc6..933ecd45baad 100644 --- a/rust-toolchain +++ b/rust-toolchain @@ -1,3 +1,3 @@ [toolchain] -channel = "nightly-2023-02-28" +channel = "nightly-2023-03-02" components = ["rust-src", "rustc-dev", "llvm-tools-preview"] diff --git a/src/builder.rs b/src/builder.rs index 913f5734ff0d..8f0208f6848e 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1228,12 +1228,8 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { #[cfg(feature="master")] fn resume(&mut self, exn0: RValue<'gcc>, _exn1: RValue<'gcc>) { - // TODO(antoyo): check if this is normal that we need to dereference the value. - // NOTE: the type is wrong, so in order to get a pointer for parameter, cast it to a - // pointer of pointer that is later dereferenced. - let exn_type = exn0.get_type().make_pointer(); + let exn_type = exn0.get_type(); let exn = self.context.new_cast(None, exn0, exn_type); - let exn = exn.dereference(None).to_rvalue(); let unwind_resume = self.context.get_target_builtin_function("__builtin_unwind_resume"); self.llbb().add_eval(None, self.context.new_call(None, unwind_resume, &[exn])); self.unreachable(); diff --git a/src/common.rs b/src/common.rs index 617c7e8640a9..76fc7bd222e1 100644 --- a/src/common.rs +++ b/src/common.rs @@ -36,7 +36,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { pub fn bytes_in_context<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, bytes: &[u8]) -> RValue<'gcc> { let context = &cx.context; let byte_type = context.new_type::(); - let typ = context.new_array_type(None, byte_type, bytes.len() as i32); + let typ = context.new_array_type(None, byte_type, bytes.len() as u64); let elements: Vec<_> = bytes.iter() .map(|&byte| context.new_rvalue_from_int(byte_type, byte as i32)) diff --git a/src/consts.rs b/src/consts.rs index 86a7f78de270..792ab8f890d8 100644 --- a/src/consts.rs +++ b/src/consts.rs @@ -13,6 +13,7 @@ use rustc_target::abi::{self, Align, HasDataLayout, Primitive, Size, WrappingRan use crate::base; use crate::context::CodegenCx; +use crate::errors::InvalidMinimumAlignment; use crate::type_of::LayoutGccExt; impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { @@ -30,6 +31,21 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { } } +fn set_global_alignment<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, gv: LValue<'gcc>, mut align: Align) { + // The target may require greater alignment for globals than the type does. + // Note: GCC and Clang also allow `__attribute__((aligned))` on variables, + // which can force it to be smaller. Rust doesn't support this yet. + if let Some(min) = cx.sess().target.min_global_align { + match Align::from_bits(min) { + Ok(min) => align = align.max(min), + Err(err) => { + cx.sess().emit_err(InvalidMinimumAlignment { err }); + } + } + } + gv.set_alignment(align.bytes() as i32); +} + impl<'gcc, 'tcx> StaticMethods for CodegenCx<'gcc, 'tcx> { fn static_addr_of(&self, cv: RValue<'gcc>, align: Align, kind: Option<&str>) -> RValue<'gcc> { // TODO(antoyo): implement a proper rvalue comparison in libgccjit instead of doing the @@ -81,7 +97,7 @@ impl<'gcc, 'tcx> StaticMethods for CodegenCx<'gcc, 'tcx> { let ty = instance.ty(self.tcx, ty::ParamEnv::reveal_all()); let gcc_type = self.layout_of(ty).gcc_type(self); - // TODO(antoyo): set alignment. + set_global_alignment(self, global, self.align_of(ty)); let value = self.bitcast_if_needed(value, gcc_type); global.global_set_initializer_rvalue(value); diff --git a/src/errors.rs b/src/errors.rs index d0ba7e247911..5ea39606c086 100644 --- a/src/errors.rs +++ b/src/errors.rs @@ -221,3 +221,9 @@ pub(crate) struct UnwindingInlineAsm { #[primary_span] pub span: Span, } + +#[derive(Diagnostic)] +#[diag(codegen_gcc_invalid_minimum_alignment)] +pub(crate) struct InvalidMinimumAlignment { + pub err: String, +} diff --git a/src/type_.rs b/src/type_.rs index 929499666173..daa661f35c4c 100644 --- a/src/type_.rs +++ b/src/type_.rs @@ -1,5 +1,3 @@ -use std::convert::TryInto; - use gccjit::{RValue, Struct, Type}; use rustc_codegen_ssa::traits::{BaseTypeMethods, DerivedTypeMethods, TypeMembershipMethods}; use rustc_codegen_ssa::common::TypeKind; @@ -202,8 +200,9 @@ impl<'gcc, 'tcx> BaseTypeMethods<'tcx> for CodegenCx<'gcc, 'tcx> { value.get_type() } - fn type_array(&self, ty: Type<'gcc>, mut len: u64) -> Type<'gcc> { - if let Some(struct_type) = ty.is_struct() { + fn type_array(&self, ty: Type<'gcc>, len: u64) -> Type<'gcc> { + // TODO: remove this as well? + /*if let Some(struct_type) = ty.is_struct() { if struct_type.get_field_count() == 0 { // NOTE: since gccjit only supports i32 for the array size and libcore's tests uses a // size of usize::MAX in test_binary_search, we workaround this by setting the size to @@ -211,14 +210,7 @@ impl<'gcc, 'tcx> BaseTypeMethods<'tcx> for CodegenCx<'gcc, 'tcx> { // FIXME(antoyo): fix gccjit API. len = 0; } - } - - // NOTE: see note above. Some other test uses usize::MAX. - if len == u64::MAX { - len = 0; - } - - let len: i32 = len.try_into().expect("array len"); + }*/ self.context.new_array_type(None, ty, len) } diff --git a/src/type_of.rs b/src/type_of.rs index 1a4fae666f22..5df8c1a209db 100644 --- a/src/type_of.rs +++ b/src/type_of.rs @@ -6,7 +6,7 @@ use rustc_middle::bug; use rustc_middle::ty::{self, Ty, TypeVisitableExt}; use rustc_middle::ty::layout::{FnAbiOf, LayoutOf, TyAndLayout}; use rustc_middle::ty::print::with_no_trimmed_paths; -use rustc_target::abi::{self, Abi, F32, F64, FieldsShape, Int, Integer, Pointer, PointeeInfo, Size, TyAbiInterface, Variants}; +use rustc_target::abi::{self, Abi, Align, F32, F64, FieldsShape, Int, Integer, Pointer, PointeeInfo, Size, TyAbiInterface, Variants}; use rustc_target::abi::call::{CastTarget, FnAbi, Reg}; use crate::abi::{FnAbiGccExt, GccType}; @@ -50,6 +50,12 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { } } +impl<'a, 'tcx> CodegenCx<'a, 'tcx> { + pub fn align_of(&self, ty: Ty<'tcx>) -> Align { + self.layout_of(ty).align.abi + } +} + fn uncached_gcc_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, layout: TyAndLayout<'tcx>, defer: &mut Option<(Struct<'gcc>, TyAndLayout<'tcx>)>) -> Type<'gcc> { match layout.abi { Abi::Scalar(_) => bug!("handled elsewhere"), diff --git a/test.sh b/test.sh index 97d5a8b006df..6139892aefca 100755 --- a/test.sh +++ b/test.sh @@ -225,6 +225,9 @@ rustc = "$HOME/.rustup/toolchains/$rust_toolchain-$TARGET_TRIPLE/bin/rustc" [target.x86_64-unknown-linux-gnu] llvm-filecheck = "`which FileCheck-10 || which FileCheck-11 || which FileCheck-12 || which FileCheck-13 || which FileCheck-14`" + +[llvm] +download-ci-llvm = false EOF rustc -V | cut -d' ' -f3 | tr -d '(' From 901e413a3f34379f0f7eab1c7178b303e1f499fb Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 4 Mar 2023 14:42:34 -0500 Subject: [PATCH 303/356] Fix tests --- tests/run/abort1.rs | 1 + tests/run/abort2.rs | 1 + tests/run/array.rs | 1 + tests/run/assign.rs | 1 + tests/run/closure.rs | 8 ++++++-- tests/run/condition.rs | 1 + tests/run/fun_ptr.rs | 1 + tests/run/int_overflow.rs | 1 + tests/run/mut_ref.rs | 1 + tests/run/operations.rs | 1 + tests/run/ptr_cast.rs | 1 + tests/run/slice.rs | 1 + tests/run/static.rs | 1 + 13 files changed, 18 insertions(+), 2 deletions(-) diff --git a/tests/run/abort1.rs b/tests/run/abort1.rs index 291af5993aa2..25041d93e748 100644 --- a/tests/run/abort1.rs +++ b/tests/run/abort1.rs @@ -33,6 +33,7 @@ mod intrinsics { use super::Sized; extern "rust-intrinsic" { + #[rustc_safe_intrinsic] pub fn abort() -> !; } } diff --git a/tests/run/abort2.rs b/tests/run/abort2.rs index 3c87c567892b..e7443c8dbe5b 100644 --- a/tests/run/abort2.rs +++ b/tests/run/abort2.rs @@ -33,6 +33,7 @@ mod intrinsics { use super::Sized; extern "rust-intrinsic" { + #[rustc_safe_intrinsic] pub fn abort() -> !; } } diff --git a/tests/run/array.rs b/tests/run/array.rs index c53d98340f04..49b28d98f2fe 100644 --- a/tests/run/array.rs +++ b/tests/run/array.rs @@ -105,6 +105,7 @@ fn panic_bounds_check(index: usize, len: usize) -> ! { mod intrinsics { extern "rust-intrinsic" { + #[rustc_safe_intrinsic] pub fn abort() -> !; } } diff --git a/tests/run/assign.rs b/tests/run/assign.rs index b95a7b714153..427c1a250339 100644 --- a/tests/run/assign.rs +++ b/tests/run/assign.rs @@ -57,6 +57,7 @@ mod libc { mod intrinsics { extern "rust-intrinsic" { + #[rustc_safe_intrinsic] pub fn abort() -> !; } } diff --git a/tests/run/closure.rs b/tests/run/closure.rs index 4d01d879dc1d..8daa681abf7d 100644 --- a/tests/run/closure.rs +++ b/tests/run/closure.rs @@ -97,10 +97,14 @@ fn panic_bounds_check(index: usize, len: usize) -> ! { mod intrinsics { extern "rust-intrinsic" { + #[rustc_safe_intrinsic] pub fn abort() -> !; } } +#[lang = "tuple_trait"] +pub trait Tuple {} + #[lang = "unsize"] pub trait Unsize {} @@ -114,7 +118,7 @@ impl, U: ?Sized> CoerceUnsized<*mut U> for *mut T {} #[lang = "fn_once"] #[rustc_paren_sugar] -pub trait FnOnce { +pub trait FnOnce { #[lang = "fn_once_output"] type Output; @@ -123,7 +127,7 @@ pub trait FnOnce { #[lang = "fn_mut"] #[rustc_paren_sugar] -pub trait FnMut: FnOnce { +pub trait FnMut: FnOnce { extern "rust-call" fn call_mut(&mut self, args: Args) -> Self::Output; } diff --git a/tests/run/condition.rs b/tests/run/condition.rs index 38b3084cb6c7..b7a13081deae 100644 --- a/tests/run/condition.rs +++ b/tests/run/condition.rs @@ -108,6 +108,7 @@ fn panic_bounds_check(index: usize, len: usize) -> ! { mod intrinsics { extern "rust-intrinsic" { + #[rustc_safe_intrinsic] pub fn abort() -> !; } } diff --git a/tests/run/fun_ptr.rs b/tests/run/fun_ptr.rs index 995fc5ca5d23..8a196f774c82 100644 --- a/tests/run/fun_ptr.rs +++ b/tests/run/fun_ptr.rs @@ -102,6 +102,7 @@ fn panic_bounds_check(index: usize, len: usize) -> ! { mod intrinsics { extern "rust-intrinsic" { + #[rustc_safe_intrinsic] pub fn abort() -> !; } } diff --git a/tests/run/int_overflow.rs b/tests/run/int_overflow.rs index 4ca623625395..c3fcb3c0a2a0 100644 --- a/tests/run/int_overflow.rs +++ b/tests/run/int_overflow.rs @@ -55,6 +55,7 @@ mod libc { mod intrinsics { extern "rust-intrinsic" { + #[rustc_safe_intrinsic] pub fn abort() -> !; } } diff --git a/tests/run/mut_ref.rs b/tests/run/mut_ref.rs index 814bb1a612e4..2a2ea8b8bf0a 100644 --- a/tests/run/mut_ref.rs +++ b/tests/run/mut_ref.rs @@ -59,6 +59,7 @@ mod libc { mod intrinsics { extern "rust-intrinsic" { + #[rustc_safe_intrinsic] pub fn abort() -> !; } } diff --git a/tests/run/operations.rs b/tests/run/operations.rs index affe12067ffe..67b9f241dbbb 100644 --- a/tests/run/operations.rs +++ b/tests/run/operations.rs @@ -65,6 +65,7 @@ mod libc { mod intrinsics { extern "rust-intrinsic" { + #[rustc_safe_intrinsic] pub fn abort() -> !; } } diff --git a/tests/run/ptr_cast.rs b/tests/run/ptr_cast.rs index 08481739a7f9..da8a8295d564 100644 --- a/tests/run/ptr_cast.rs +++ b/tests/run/ptr_cast.rs @@ -102,6 +102,7 @@ fn panic_bounds_check(index: usize, len: usize) -> ! { mod intrinsics { extern "rust-intrinsic" { + #[rustc_safe_intrinsic] pub fn abort() -> !; } } diff --git a/tests/run/slice.rs b/tests/run/slice.rs index ad9258ed0bde..96f1c4792e58 100644 --- a/tests/run/slice.rs +++ b/tests/run/slice.rs @@ -102,6 +102,7 @@ mod intrinsics { use super::Sized; extern "rust-intrinsic" { + #[rustc_safe_intrinsic] pub fn abort() -> !; } } diff --git a/tests/run/static.rs b/tests/run/static.rs index 294add968449..19201f1df266 100644 --- a/tests/run/static.rs +++ b/tests/run/static.rs @@ -45,6 +45,7 @@ mod intrinsics { use super::Sized; extern "rust-intrinsic" { + #[rustc_safe_intrinsic] pub fn abort() -> !; } } From 6958188e101068fc825428c00ebe236db099d3d7 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 4 Mar 2023 15:02:49 -0500 Subject: [PATCH 304/356] Temporarily disable rust repo cache --- .github/workflows/ci.yml | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 927eb3077616..d2b7724a2215 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -108,14 +108,14 @@ jobs: path: target key: ${{ runner.os }}-cargo-build-target-${{ hashFiles('rust-toolchain') }} - - name: Cache rust repository - # We only clone the rust repository for rustc tests - if: ${{ contains(matrix.commands, 'rustc') }} - uses: actions/cache@v3 - id: cache-rust-repository - with: - path: rust - key: ${{ runner.os }}-packages-${{ hashFiles('rust/.git/HEAD') }} + #- name: Cache rust repository + ## We only clone the rust repository for rustc tests + #if: ${{ contains(matrix.commands, 'rustc') }} + #uses: actions/cache@v3 + #id: cache-rust-repository + #with: + #path: rust + #key: ${{ runner.os }}-packages-${{ hashFiles('rust/.git/HEAD') }} - name: Build run: | From 08c75aee1b216bd1a4c07e1776fbced45a5e0ba0 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 4 Mar 2023 15:03:05 -0500 Subject: [PATCH 305/356] Fix error in libgccjit12 code path --- src/builder.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/builder.rs b/src/builder.rs index 8f0208f6848e..a3c8142bea2d 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -1108,7 +1108,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { let vector_type = vec.get_type().unqualified().dyncast_vector().expect("Called extract_element on a non-vector type"); let element_type = vector_type.get_element_type(); let vec_num_units = vector_type.get_num_units(); - let array_type = self.context.new_array_type(None, element_type, vec_num_units as i32); + let array_type = self.context.new_array_type(None, element_type, vec_num_units as u64); let array = self.context.new_bitcast(None, vec, array_type).to_rvalue(); self.context.new_array_access(None, array, idx).to_rvalue() } From 5c35dc067dd09327f129906a41fb524b6e8acead Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 4 Mar 2023 15:04:55 -0500 Subject: [PATCH 306/356] Fix warnings --- src/intrinsic/simd.rs | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index fca59d50974f..b59c3a64f572 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -1,10 +1,13 @@ -#[cfg_attr(not(feature="master"), allow(unused_imports))] -use gccjit::{ToRValue, ComparisonOp, UnaryOp}; +#[cfg(feature="master")] +use gccjit::{ComparisonOp, UnaryOp}; +use gccjit::ToRValue; use gccjit::{BinaryOp, RValue, Type}; use rustc_codegen_ssa::base::compare_simd_types; use rustc_codegen_ssa::common::{IntPredicate, TypeKind}; -use rustc_codegen_ssa::errors::{ExpectedPointerMutability, InvalidMonomorphization}; +#[cfg(feature="master")] +use rustc_codegen_ssa::errors::ExpectedPointerMutability; +use rustc_codegen_ssa::errors::InvalidMonomorphization; use rustc_codegen_ssa::mir::operand::OperandRef; use rustc_codegen_ssa::mir::place::PlaceRef; use rustc_codegen_ssa::traits::{BaseTypeMethods, BuilderMethods}; @@ -18,9 +21,11 @@ use rustc_target::abi::Align; use crate::builder::Builder; #[cfg(feature="master")] use crate::context::CodegenCx; +#[cfg(feature="master")] +use crate::errors::{InvalidMonomorphizationExpectedSignedUnsigned, InvalidMonomorphizationInsertedType}; use crate::errors::{ - InvalidMonomorphizationExpectedSignedUnsigned, InvalidMonomorphizationExpectedSimd, - InvalidMonomorphizationInsertedType, InvalidMonomorphizationInvalidBitmask, + InvalidMonomorphizationExpectedSimd, + InvalidMonomorphizationInvalidBitmask, InvalidMonomorphizationInvalidFloatVector, InvalidMonomorphizationMaskType, InvalidMonomorphizationMismatchedLengths, InvalidMonomorphizationNotFloat, InvalidMonomorphizationReturnElement, InvalidMonomorphizationReturnIntegerType, From 9d5bc7c929c82e34300850537aa2840097f78d47 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 4 Mar 2023 15:25:34 -0500 Subject: [PATCH 307/356] Fix tests --- failing-ui-tests.txt | 132 ++++++++++++++++++++++------------------- failing-ui-tests12.txt | 82 ++++++++++++------------- src/intrinsic/llvm.rs | 2 +- 3 files changed, 114 insertions(+), 102 deletions(-) diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index f43116544ed2..b82e6e157e58 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -1,60 +1,72 @@ -src/test/ui/alloc-error/default-alloc-error-hook.rs -src/test/ui/allocator/custom-in-block.rs -src/test/ui/allocator/custom-in-submodule.rs -src/test/ui/allocator/custom.rs -src/test/ui/allocator/hygiene.rs -src/test/ui/allocator/no_std-alloc-error-handler-custom.rs -src/test/ui/allocator/no_std-alloc-error-handler-default.rs -src/test/ui/allocator/xcrate-use.rs -src/test/ui/allocator/xcrate-use2.rs -src/test/ui/asm/may_unwind.rs -src/test/ui/asm/x86_64/multiple-clobber-abi.rs -src/test/ui/debuginfo/debuginfo-emit-llvm-ir-and-split-debuginfo.rs -src/test/ui/functions-closures/parallel-codegen-closures.rs -src/test/ui/linkage-attr/linkage1.rs -src/test/ui/lto/dylib-works.rs -src/test/ui/numbers-arithmetic/saturating-float-casts.rs -src/test/ui/polymorphization/promoted-function.rs -src/test/ui/process/nofile-limit.rs -src/test/ui/sepcomp/sepcomp-cci.rs -src/test/ui/sepcomp/sepcomp-extern.rs -src/test/ui/sepcomp/sepcomp-fns-backwards.rs -src/test/ui/sepcomp/sepcomp-fns.rs -src/test/ui/sepcomp/sepcomp-statics.rs -src/test/ui/simd/intrinsic/generic-arithmetic-pass.rs -src/test/ui/sse2.rs -src/test/ui/target-feature/missing-plusminus.rs -src/test/ui/asm/x86_64/may_unwind.rs -src/test/ui/backtrace.rs -src/test/ui/catch-unwind-bang.rs -src/test/ui/cfg/cfg-panic-abort.rs -src/test/ui/drop/dynamic-drop-async.rs -src/test/ui/drop/repeat-drop.rs -src/test/ui/fmt/format-args-capture.rs -src/test/ui/generator/panic-drops-resume.rs -src/test/ui/generator/panic-drops.rs -src/test/ui/generator/panic-safe.rs -src/test/ui/intrinsics/panic-uninitialized-zeroed.rs -src/test/ui/iterators/iter-sum-overflow-debug.rs -src/test/ui/iterators/iter-sum-overflow-overflow-checks.rs -src/test/ui/mir/mir_calls_to_shims.rs -src/test/ui/mir/mir_drop_order.rs -src/test/ui/mir/mir_let_chains_drop_order.rs -src/test/ui/oom_unwind.rs -src/test/ui/panic-runtime/abort-link-to-unwinding-crates.rs -src/test/ui/panic-runtime/abort.rs -src/test/ui/panic-runtime/link-to-abort.rs -src/test/ui/unwind-no-uwtable.rs -src/test/ui/issues/issue-14875.rs -src/test/ui/issues/issue-29948.rs -src/test/ui/issues/issue-40883.rs -src/test/ui/issues/issue-43853.rs -src/test/ui/issues/issue-47364.rs -src/test/ui/simd/issue-17170.rs -src/test/ui/simd/issue-39720.rs -src/test/ui/simd/issue-89193.rs -src/test/ui/statics/issue-91050-1.rs -src/test/ui/statics/issue-91050-2.rs -src/test/ui/macros/rfc-2011-nicer-assert-messages/assert-without-captures-does-not-create-unnecessary-code.rs -src/test/ui/rfc-2091-track-caller/std-panic-locations.rs -src/test/ui/rfcs/rfc1857-drop-order.rs +tests/ui/alloc-error/default-alloc-error-hook.rs +tests/ui/allocator/custom-in-block.rs +tests/ui/allocator/custom-in-submodule.rs +tests/ui/allocator/custom.rs +tests/ui/allocator/hygiene.rs +tests/ui/allocator/no_std-alloc-error-handler-custom.rs +tests/ui/allocator/no_std-alloc-error-handler-default.rs +tests/ui/allocator/xcrate-use.rs +tests/ui/allocator/xcrate-use2.rs +tests/ui/asm/may_unwind.rs +tests/ui/asm/x86_64/multiple-clobber-abi.rs +tests/ui/debuginfo/debuginfo-emit-llvm-ir-and-split-debuginfo.rs +tests/ui/functions-closures/parallel-codegen-closures.rs +tests/ui/linkage-attr/linkage1.rs +tests/ui/lto/dylib-works.rs +tests/ui/numbers-arithmetic/saturating-float-casts.rs +tests/ui/polymorphization/promoted-function.rs +tests/ui/process/nofile-limit.rs +tests/ui/sepcomp/sepcomp-cci.rs +tests/ui/sepcomp/sepcomp-extern.rs +tests/ui/sepcomp/sepcomp-fns-backwards.rs +tests/ui/sepcomp/sepcomp-fns.rs +tests/ui/sepcomp/sepcomp-statics.rs +tests/ui/simd/intrinsic/generic-arithmetic-pass.rs +tests/ui/sse2.rs +tests/ui/target-feature/missing-plusminus.rs +tests/ui/asm/x86_64/may_unwind.rs +tests/ui/backtrace.rs +tests/ui/catch-unwind-bang.rs +tests/ui/cfg/cfg-panic-abort.rs +tests/ui/drop/dynamic-drop-async.rs +tests/ui/drop/repeat-drop.rs +tests/ui/fmt/format-args-capture.rs +tests/ui/generator/panic-drops-resume.rs +tests/ui/generator/panic-drops.rs +tests/ui/generator/panic-safe.rs +tests/ui/intrinsics/panic-uninitialized-zeroed.rs +tests/ui/iterators/iter-sum-overflow-debug.rs +tests/ui/iterators/iter-sum-overflow-overflow-checks.rs +tests/ui/mir/mir_calls_to_shims.rs +tests/ui/mir/mir_drop_order.rs +tests/ui/mir/mir_let_chains_drop_order.rs +tests/ui/oom_unwind.rs +tests/ui/panic-runtime/abort-link-to-unwinding-crates.rs +tests/ui/panic-runtime/abort.rs +tests/ui/panic-runtime/link-to-abort.rs +tests/ui/unwind-no-uwtable.rs +tests/ui/issues/issue-14875.rs +tests/ui/issues/issue-29948.rs +tests/ui/issues/issue-40883.rs +tests/ui/issues/issue-43853.rs +tests/ui/issues/issue-47364.rs +tests/ui/simd/issue-17170.rs +tests/ui/simd/issue-39720.rs +tests/ui/simd/issue-89193.rs +tests/ui/statics/issue-91050-1.rs +tests/ui/statics/issue-91050-2.rs +tests/ui/macros/rfc-2011-nicer-assert-messages/assert-without-captures-does-not-create-unnecessary-code.rs +tests/ui/rfc-2091-track-caller/std-panic-locations.rs +tests/ui/rfcs/rfc1857-drop-order.rs +tests/ui/parser/unclosed-delimiter-in-dep.rs +tests/ui/runtime/rt-explody-panic-payloads.rs +tests/ui/simd/intrinsic/ptr-cast.rs +tests/ui/binding/fn-arg-incomplete-pattern-drop-order.rs +tests/ui/codegen/issue-55976.rs +tests/ui/consts/missing_span_in_backtrace.rs +tests/ui/drop/dynamic-drop.rs +tests/ui/dyn-star/box.rs +tests/ui/dyn-star/const.rs +tests/ui/dyn-star/drop.rs +tests/ui/dyn-star/make-dyn-star.rs +tests/ui/dyn-star/method.rs diff --git a/failing-ui-tests12.txt b/failing-ui-tests12.txt index 2a9f39e88ccb..bda0f633bc72 100644 --- a/failing-ui-tests12.txt +++ b/failing-ui-tests12.txt @@ -1,41 +1,41 @@ -src/test/ui/asm/x86_64/issue-96797.rs -src/test/ui/intrinsics/const-eval-select-x86_64.rs -src/test/ui/packed/packed-struct-drop-aligned.rs -src/test/ui/packed/packed-struct-generic-layout.rs -src/test/ui/packed/packed-struct-layout.rs -src/test/ui/packed/packed-struct-optimized-enum.rs -src/test/ui/packed/packed-struct-size.rs -src/test/ui/packed/packed-struct-vec.rs -src/test/ui/packed/packed-tuple-struct-layout.rs -src/test/ui/simd/array-type.rs -src/test/ui/simd/intrinsic/float-minmax-pass.rs -src/test/ui/simd/intrinsic/generic-arithmetic-saturating-pass.rs -src/test/ui/simd/intrinsic/generic-as.rs -src/test/ui/simd/intrinsic/generic-cast-pass.rs -src/test/ui/simd/intrinsic/generic-cast-pointer-width.rs -src/test/ui/simd/intrinsic/generic-comparison-pass.rs -src/test/ui/simd/intrinsic/generic-elements-pass.rs -src/test/ui/simd/intrinsic/generic-reduction-pass.rs -src/test/ui/simd/intrinsic/generic-select-pass.rs -src/test/ui/simd/intrinsic/inlining-issue67557-ice.rs -src/test/ui/simd/intrinsic/inlining-issue67557.rs -src/test/ui/simd/monomorphize-shuffle-index.rs -src/test/ui/simd/shuffle.rs -src/test/ui/simd/simd-bitmask.rs -src/test/ui/binding/fn-arg-incomplete-pattern-drop-order.rs -src/test/ui/drop/dynamic-drop.rs -src/test/ui/generator/resume-after-return.rs -src/test/ui/iterators/iter-step-overflow-debug.rs -src/test/ui/macros/rfc-2011-nicer-assert-messages/all-expr-kinds.rs -src/test/ui/numbers-arithmetic/next-power-of-two-overflow-debug.rs -src/test/ui/panic-while-printing.rs -src/test/ui/privacy/reachable-unnameable-items.rs -src/test/ui/rfc-1937-termination-trait/termination-trait-in-test.rs -src/test/ui/async-await/async-fn-size-moved-locals.rs -src/test/ui/async-await/async-fn-size-uninit-locals.rs -src/test/ui/cfg/cfg-panic.rs -src/test/ui/generator/size-moved-locals.rs -src/test/ui/macros/rfc-2011-nicer-assert-messages/all-not-available-cases.rs -src/test/ui/runtime/rt-explody-panic-payloads.rs -src/test/ui/simd/intrinsic/generic-gather-pass.rs -src/test/ui/simd/issue-85915-simd-ptrs.rs +tests/ui/asm/x86_64/issue-96797.rs +tests/ui/intrinsics/const-eval-select-x86_64.rs +tests/ui/packed/packed-struct-drop-aligned.rs +tests/ui/packed/packed-struct-generic-layout.rs +tests/ui/packed/packed-struct-layout.rs +tests/ui/packed/packed-struct-optimized-enum.rs +tests/ui/packed/packed-struct-size.rs +tests/ui/packed/packed-struct-vec.rs +tests/ui/packed/packed-tuple-struct-layout.rs +tests/ui/simd/array-type.rs +tests/ui/simd/intrinsic/float-minmax-pass.rs +tests/ui/simd/intrinsic/generic-arithmetic-saturating-pass.rs +tests/ui/simd/intrinsic/generic-as.rs +tests/ui/simd/intrinsic/generic-cast-pass.rs +tests/ui/simd/intrinsic/generic-cast-pointer-width.rs +tests/ui/simd/intrinsic/generic-comparison-pass.rs +tests/ui/simd/intrinsic/generic-elements-pass.rs +tests/ui/simd/intrinsic/generic-reduction-pass.rs +tests/ui/simd/intrinsic/generic-select-pass.rs +tests/ui/simd/intrinsic/inlining-issue67557-ice.rs +tests/ui/simd/intrinsic/inlining-issue67557.rs +tests/ui/simd/monomorphize-shuffle-index.rs +tests/ui/simd/shuffle.rs +tests/ui/simd/simd-bitmask.rs +tests/ui/binding/fn-arg-incomplete-pattern-drop-order.rs +tests/ui/drop/dynamic-drop.rs +tests/ui/generator/resume-after-return.rs +tests/ui/iterators/iter-step-overflow-debug.rs +tests/ui/macros/rfc-2011-nicer-assert-messages/all-expr-kinds.rs +tests/ui/numbers-arithmetic/next-power-of-two-overflow-debug.rs +tests/ui/panic-while-printing.rs +tests/ui/privacy/reachable-unnameable-items.rs +tests/ui/rfc-1937-termination-trait/termination-trait-in-test.rs +tests/ui/async-await/async-fn-size-moved-locals.rs +tests/ui/async-await/async-fn-size-uninit-locals.rs +tests/ui/cfg/cfg-panic.rs +tests/ui/generator/size-moved-locals.rs +tests/ui/macros/rfc-2011-nicer-assert-messages/all-not-available-cases.rs +tests/ui/runtime/rt-explody-panic-payloads.rs +tests/ui/simd/intrinsic/generic-gather-pass.rs +tests/ui/simd/issue-85915-simd-ptrs.rs diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index ee0ea6e993f9..0edec566be30 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -407,7 +407,7 @@ pub fn ignore_arg_cast(func_name: &str, index: usize, args_len: usize) -> bool { #[cfg(not(feature="master"))] pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function<'gcc> { match name { - "llvm.x86.xgetbv" => { + "llvm.x86.xgetbv" | "llvm.x86.sse2.pause" => { let gcc_name = "__builtin_trap"; let func = cx.context.get_builtin_function(gcc_name); cx.functions.borrow_mut().insert(gcc_name.to_string(), func); From 42a89bd87599106a6d3fca34fe64b43b377a4e80 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 4 Mar 2023 15:41:30 -0500 Subject: [PATCH 308/356] Fix tests --- failing-ui-tests12.txt | 3 --- 1 file changed, 3 deletions(-) diff --git a/failing-ui-tests12.txt b/failing-ui-tests12.txt index bda0f633bc72..d3a27aa945ca 100644 --- a/failing-ui-tests12.txt +++ b/failing-ui-tests12.txt @@ -22,8 +22,6 @@ tests/ui/simd/intrinsic/inlining-issue67557.rs tests/ui/simd/monomorphize-shuffle-index.rs tests/ui/simd/shuffle.rs tests/ui/simd/simd-bitmask.rs -tests/ui/binding/fn-arg-incomplete-pattern-drop-order.rs -tests/ui/drop/dynamic-drop.rs tests/ui/generator/resume-after-return.rs tests/ui/iterators/iter-step-overflow-debug.rs tests/ui/macros/rfc-2011-nicer-assert-messages/all-expr-kinds.rs @@ -36,6 +34,5 @@ tests/ui/async-await/async-fn-size-uninit-locals.rs tests/ui/cfg/cfg-panic.rs tests/ui/generator/size-moved-locals.rs tests/ui/macros/rfc-2011-nicer-assert-messages/all-not-available-cases.rs -tests/ui/runtime/rt-explody-panic-payloads.rs tests/ui/simd/intrinsic/generic-gather-pass.rs tests/ui/simd/issue-85915-simd-ptrs.rs From f83ede03f5632c4f41103d95f0495f023b6dc28a Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 4 Mar 2023 18:52:25 -0500 Subject: [PATCH 309/356] Fix tests --- failing-ui-tests.txt | 21 +-------------------- failing-ui-tests12.txt | 2 ++ 2 files changed, 3 insertions(+), 20 deletions(-) diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index b82e6e157e58..bd7b718f9d2d 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -1,4 +1,3 @@ -tests/ui/alloc-error/default-alloc-error-hook.rs tests/ui/allocator/custom-in-block.rs tests/ui/allocator/custom-in-submodule.rs tests/ui/allocator/custom.rs @@ -33,7 +32,6 @@ tests/ui/drop/repeat-drop.rs tests/ui/fmt/format-args-capture.rs tests/ui/generator/panic-drops-resume.rs tests/ui/generator/panic-drops.rs -tests/ui/generator/panic-safe.rs tests/ui/intrinsics/panic-uninitialized-zeroed.rs tests/ui/iterators/iter-sum-overflow-debug.rs tests/ui/iterators/iter-sum-overflow-overflow-checks.rs @@ -45,28 +43,11 @@ tests/ui/panic-runtime/abort-link-to-unwinding-crates.rs tests/ui/panic-runtime/abort.rs tests/ui/panic-runtime/link-to-abort.rs tests/ui/unwind-no-uwtable.rs -tests/ui/issues/issue-14875.rs -tests/ui/issues/issue-29948.rs -tests/ui/issues/issue-40883.rs -tests/ui/issues/issue-43853.rs -tests/ui/issues/issue-47364.rs -tests/ui/simd/issue-17170.rs -tests/ui/simd/issue-39720.rs -tests/ui/simd/issue-89193.rs -tests/ui/statics/issue-91050-1.rs -tests/ui/statics/issue-91050-2.rs -tests/ui/macros/rfc-2011-nicer-assert-messages/assert-without-captures-does-not-create-unnecessary-code.rs -tests/ui/rfc-2091-track-caller/std-panic-locations.rs -tests/ui/rfcs/rfc1857-drop-order.rs tests/ui/parser/unclosed-delimiter-in-dep.rs tests/ui/runtime/rt-explody-panic-payloads.rs tests/ui/simd/intrinsic/ptr-cast.rs tests/ui/binding/fn-arg-incomplete-pattern-drop-order.rs -tests/ui/codegen/issue-55976.rs tests/ui/consts/missing_span_in_backtrace.rs tests/ui/drop/dynamic-drop.rs tests/ui/dyn-star/box.rs -tests/ui/dyn-star/const.rs -tests/ui/dyn-star/drop.rs -tests/ui/dyn-star/make-dyn-star.rs -tests/ui/dyn-star/method.rs +tests/ui/panic-while-printing.rs diff --git a/failing-ui-tests12.txt b/failing-ui-tests12.txt index d3a27aa945ca..4e3a64e9eb74 100644 --- a/failing-ui-tests12.txt +++ b/failing-ui-tests12.txt @@ -36,3 +36,5 @@ tests/ui/generator/size-moved-locals.rs tests/ui/macros/rfc-2011-nicer-assert-messages/all-not-available-cases.rs tests/ui/simd/intrinsic/generic-gather-pass.rs tests/ui/simd/issue-85915-simd-ptrs.rs +tests/ui/issues/issue-68010-large-zst-consts.rs +tests/ui/rust-2018/proc-macro-crate-in-paths.rs From 3180da55292c1fb8448eecea6bf3106d05f1f9df Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 4 Mar 2023 19:18:31 -0500 Subject: [PATCH 310/356] Fix tests --- failing-ui-tests.txt | 16 +++++++++++++++- failing-ui-tests12.txt | 2 +- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index bd7b718f9d2d..286aff33eab6 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -50,4 +50,18 @@ tests/ui/binding/fn-arg-incomplete-pattern-drop-order.rs tests/ui/consts/missing_span_in_backtrace.rs tests/ui/drop/dynamic-drop.rs tests/ui/dyn-star/box.rs -tests/ui/panic-while-printing.rs +tests/ui/issues/issue-40883.rs +tests/ui/issues/issue-43853.rs +tests/ui/issues/issue-47364.rs +tests/ui/macros/rfc-2011-nicer-assert-messages/assert-without-captures-does-not-create-unnecessary-code.rs +tests/ui/rfc-2091-track-caller/std-panic-locations.rs +tests/ui/rfcs/rfc1857-drop-order.rs +tests/ui/simd/issue-17170.rs +tests/ui/simd/issue-39720.rs +tests/ui/simd/issue-89193.rs +tests/ui/statics/issue-91050-1.rs +tests/ui/statics/issue-91050-2.rs +tests/ui/alloc-error/default-alloc-error-hook.rs +tests/ui/generator/panic-safe.rs +tests/ui/issues/issue-14875.rs +tests/ui/issues/issue-29948.rs diff --git a/failing-ui-tests12.txt b/failing-ui-tests12.txt index 4e3a64e9eb74..e4bdcb36b5ef 100644 --- a/failing-ui-tests12.txt +++ b/failing-ui-tests12.txt @@ -26,7 +26,6 @@ tests/ui/generator/resume-after-return.rs tests/ui/iterators/iter-step-overflow-debug.rs tests/ui/macros/rfc-2011-nicer-assert-messages/all-expr-kinds.rs tests/ui/numbers-arithmetic/next-power-of-two-overflow-debug.rs -tests/ui/panic-while-printing.rs tests/ui/privacy/reachable-unnameable-items.rs tests/ui/rfc-1937-termination-trait/termination-trait-in-test.rs tests/ui/async-await/async-fn-size-moved-locals.rs @@ -38,3 +37,4 @@ tests/ui/simd/intrinsic/generic-gather-pass.rs tests/ui/simd/issue-85915-simd-ptrs.rs tests/ui/issues/issue-68010-large-zst-consts.rs tests/ui/rust-2018/proc-macro-crate-in-paths.rs +tests/ui/panic-while-printing.rs From 4b878ccab4cc9e68119a30bc2227522e301c674c Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 4 Mar 2023 19:49:03 -0500 Subject: [PATCH 311/356] Fix tests --- failing-ui-tests.txt | 1 + failing-ui-tests12.txt | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index 286aff33eab6..8539e27ea6a5 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -65,3 +65,4 @@ tests/ui/alloc-error/default-alloc-error-hook.rs tests/ui/generator/panic-safe.rs tests/ui/issues/issue-14875.rs tests/ui/issues/issue-29948.rs +tests/ui/panic-while-printing.rs diff --git a/failing-ui-tests12.txt b/failing-ui-tests12.txt index e4bdcb36b5ef..8c27bd8b8ca8 100644 --- a/failing-ui-tests12.txt +++ b/failing-ui-tests12.txt @@ -37,4 +37,3 @@ tests/ui/simd/intrinsic/generic-gather-pass.rs tests/ui/simd/issue-85915-simd-ptrs.rs tests/ui/issues/issue-68010-large-zst-consts.rs tests/ui/rust-2018/proc-macro-crate-in-paths.rs -tests/ui/panic-while-printing.rs From 77a9effd3dde6eabcda086ccd36dd1bfb5fb88ab Mon Sep 17 00:00:00 2001 From: Arpan Kapoor Date: Fri, 24 Mar 2023 13:06:20 +0530 Subject: [PATCH 312/356] Optimize bitreverse codegen --- example/mini_core_hello_world.rs | 5 + src/intrinsic/mod.rs | 161 +++++++------------------------ 2 files changed, 41 insertions(+), 125 deletions(-) diff --git a/example/mini_core_hello_world.rs b/example/mini_core_hello_world.rs index 993a31e68eab..4dff341e67d0 100644 --- a/example/mini_core_hello_world.rs +++ b/example/mini_core_hello_world.rs @@ -168,6 +168,11 @@ fn main() { world as Box; assert_eq!(intrinsics::bitreverse(0b10101000u8), 0b00010101u8); + assert_eq!(intrinsics::bitreverse(0xddccu16), 0x33bbu16); + assert_eq!(intrinsics::bitreverse(0xffee_ddccu32), 0x33bb77ffu32); + assert_eq!(intrinsics::bitreverse(0x1234_5678_ffee_ddccu64), 0x33bb77ff1e6a2c48u64); + // != cannot be applied to type u128? + // assert_eq!(intrinsics::bitreverse(0x1234_5678_ffee_ddcc_1234_5678_ffee_ddccu128), 0x33bb77ff1e6a2c4833bb77ff1e6a2c48u128); assert_eq!(intrinsics::bswap(0xabu8), 0xabu8); assert_eq!(intrinsics::bswap(0xddccu16), 0xccddu16); diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index 2590e0e3af44..6f856e481bca 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -549,141 +549,52 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let context = &self.cx.context; let result = match width { - 8 => { + 8 | 16 | 32 | 64 => { + let mask = ((1u128 << width) - 1) as u64; + let (m0, m1, m2) = if width > 16 { + ( + context.new_rvalue_from_long(typ, (0x5555555555555555u64 & mask) as i64), + context.new_rvalue_from_long(typ, (0x3333333333333333u64 & mask) as i64), + context.new_rvalue_from_long(typ, (0x0f0f0f0f0f0f0f0fu64 & mask) as i64), + ) + } else { + ( + context.new_rvalue_from_int(typ, (0x5555u64 & mask) as i32), + context.new_rvalue_from_int(typ, (0x3333u64 & mask) as i32), + context.new_rvalue_from_int(typ, (0x0f0fu64 & mask) as i32), + ) + }; + let one = context.new_rvalue_from_int(typ, 1); + let two = context.new_rvalue_from_int(typ, 2); + let four = context.new_rvalue_from_int(typ, 4); + // First step. - let left = self.and(value, context.new_rvalue_from_int(typ, 0xF0)); - let left = self.lshr(left, context.new_rvalue_from_int(typ, 4)); - let right = self.and(value, context.new_rvalue_from_int(typ, 0x0F)); - let right = self.shl(right, context.new_rvalue_from_int(typ, 4)); + let left = self.lshr(value, one); + let left = self.and(left, m0); + let right = self.and(value, m0); + let right = self.shl(right, one); let step1 = self.or(left, right); // Second step. - let left = self.and(step1, context.new_rvalue_from_int(typ, 0xCC)); - let left = self.lshr(left, context.new_rvalue_from_int(typ, 2)); - let right = self.and(step1, context.new_rvalue_from_int(typ, 0x33)); - let right = self.shl(right, context.new_rvalue_from_int(typ, 2)); + let left = self.lshr(step1, two); + let left = self.and(left, m1); + let right = self.and(step1, m1); + let right = self.shl(right, two); let step2 = self.or(left, right); // Third step. - let left = self.and(step2, context.new_rvalue_from_int(typ, 0xAA)); - let left = self.lshr(left, context.new_rvalue_from_int(typ, 1)); - let right = self.and(step2, context.new_rvalue_from_int(typ, 0x55)); - let right = self.shl(right, context.new_rvalue_from_int(typ, 1)); - let step3 = self.or(left, right); - - step3 - }, - 16 => { - // First step. - let left = self.and(value, context.new_rvalue_from_int(typ, 0x5555)); - let left = self.shl(left, context.new_rvalue_from_int(typ, 1)); - let right = self.and(value, context.new_rvalue_from_int(typ, 0xAAAA)); - let right = self.lshr(right, context.new_rvalue_from_int(typ, 1)); - let step1 = self.or(left, right); - - // Second step. - let left = self.and(step1, context.new_rvalue_from_int(typ, 0x3333)); - let left = self.shl(left, context.new_rvalue_from_int(typ, 2)); - let right = self.and(step1, context.new_rvalue_from_int(typ, 0xCCCC)); - let right = self.lshr(right, context.new_rvalue_from_int(typ, 2)); - let step2 = self.or(left, right); - - // Third step. - let left = self.and(step2, context.new_rvalue_from_int(typ, 0x0F0F)); - let left = self.shl(left, context.new_rvalue_from_int(typ, 4)); - let right = self.and(step2, context.new_rvalue_from_int(typ, 0xF0F0)); - let right = self.lshr(right, context.new_rvalue_from_int(typ, 4)); + let left = self.lshr(step2, four); + let left = self.and(left, m2); + let right = self.and(step2, m2); + let right = self.shl(right, four); let step3 = self.or(left, right); // Fourth step. - let left = self.and(step3, context.new_rvalue_from_int(typ, 0x00FF)); - let left = self.shl(left, context.new_rvalue_from_int(typ, 8)); - let right = self.and(step3, context.new_rvalue_from_int(typ, 0xFF00)); - let right = self.lshr(right, context.new_rvalue_from_int(typ, 8)); - let step4 = self.or(left, right); - - step4 - }, - 32 => { - // TODO(antoyo): Refactor with other implementations. - // First step. - let left = self.and(value, context.new_rvalue_from_long(typ, 0x55555555)); - let left = self.shl(left, context.new_rvalue_from_long(typ, 1)); - let right = self.and(value, context.new_rvalue_from_long(typ, 0xAAAAAAAA)); - let right = self.lshr(right, context.new_rvalue_from_long(typ, 1)); - let step1 = self.or(left, right); - - // Second step. - let left = self.and(step1, context.new_rvalue_from_long(typ, 0x33333333)); - let left = self.shl(left, context.new_rvalue_from_long(typ, 2)); - let right = self.and(step1, context.new_rvalue_from_long(typ, 0xCCCCCCCC)); - let right = self.lshr(right, context.new_rvalue_from_long(typ, 2)); - let step2 = self.or(left, right); - - // Third step. - let left = self.and(step2, context.new_rvalue_from_long(typ, 0x0F0F0F0F)); - let left = self.shl(left, context.new_rvalue_from_long(typ, 4)); - let right = self.and(step2, context.new_rvalue_from_long(typ, 0xF0F0F0F0)); - let right = self.lshr(right, context.new_rvalue_from_long(typ, 4)); - let step3 = self.or(left, right); - - // Fourth step. - let left = self.and(step3, context.new_rvalue_from_long(typ, 0x00FF00FF)); - let left = self.shl(left, context.new_rvalue_from_long(typ, 8)); - let right = self.and(step3, context.new_rvalue_from_long(typ, 0xFF00FF00)); - let right = self.lshr(right, context.new_rvalue_from_long(typ, 8)); - let step4 = self.or(left, right); - - // Fifth step. - let left = self.and(step4, context.new_rvalue_from_long(typ, 0x0000FFFF)); - let left = self.shl(left, context.new_rvalue_from_long(typ, 16)); - let right = self.and(step4, context.new_rvalue_from_long(typ, 0xFFFF0000)); - let right = self.lshr(right, context.new_rvalue_from_long(typ, 16)); - let step5 = self.or(left, right); - - step5 - }, - 64 => { - // First step. - let left = self.shl(value, context.new_rvalue_from_long(typ, 32)); - let right = self.lshr(value, context.new_rvalue_from_long(typ, 32)); - let step1 = self.or(left, right); - - // Second step. - let left = self.and(step1, context.new_rvalue_from_long(typ, 0x0001FFFF0001FFFF)); - let left = self.shl(left, context.new_rvalue_from_long(typ, 15)); - let right = self.and(step1, context.new_rvalue_from_long(typ, 0xFFFE0000FFFE0000u64 as i64)); // TODO(antoyo): transmute the number instead? - let right = self.lshr(right, context.new_rvalue_from_long(typ, 17)); - let step2 = self.or(left, right); - - // Third step. - let left = self.lshr(step2, context.new_rvalue_from_long(typ, 10)); - let left = self.xor(step2, left); - let temp = self.and(left, context.new_rvalue_from_long(typ, 0x003F801F003F801F)); - - let left = self.shl(temp, context.new_rvalue_from_long(typ, 10)); - let left = self.or(temp, left); - let step3 = self.xor(left, step2); - - // Fourth step. - let left = self.lshr(step3, context.new_rvalue_from_long(typ, 4)); - let left = self.xor(step3, left); - let temp = self.and(left, context.new_rvalue_from_long(typ, 0x0E0384210E038421)); - - let left = self.shl(temp, context.new_rvalue_from_long(typ, 4)); - let left = self.or(temp, left); - let step4 = self.xor(left, step3); - - // Fifth step. - let left = self.lshr(step4, context.new_rvalue_from_long(typ, 2)); - let left = self.xor(step4, left); - let temp = self.and(left, context.new_rvalue_from_long(typ, 0x2248884222488842)); - - let left = self.shl(temp, context.new_rvalue_from_long(typ, 2)); - let left = self.or(temp, left); - let step5 = self.xor(left, step4); - - step5 + if width == 8 { + step3 + } else { + self.gcc_bswap(step3, width) + } }, 128 => { // TODO(antoyo): find a more efficient implementation? From 6e1a79c6a4630d1cd0bd143919ffac3c598f0e3d Mon Sep 17 00:00:00 2001 From: Arpan Kapoor Date: Sun, 26 Mar 2023 13:19:57 +0530 Subject: [PATCH 313/356] Add u128 PartialEq impl in mini_core.rs --- example/mini_core.rs | 11 +++++++++++ example/mini_core_hello_world.rs | 3 +-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/example/mini_core.rs b/example/mini_core.rs index 637b8dc53fef..018bbaf025da 100644 --- a/example/mini_core.rs +++ b/example/mini_core.rs @@ -59,6 +59,7 @@ unsafe impl Copy for u8 {} unsafe impl Copy for u16 {} unsafe impl Copy for u32 {} unsafe impl Copy for u64 {} +unsafe impl Copy for u128 {} unsafe impl Copy for usize {} unsafe impl Copy for i8 {} unsafe impl Copy for i16 {} @@ -79,6 +80,7 @@ unsafe impl Sync for u8 {} unsafe impl Sync for u16 {} unsafe impl Sync for u32 {} unsafe impl Sync for u64 {} +unsafe impl Sync for u128 {} unsafe impl Sync for usize {} unsafe impl Sync for i8 {} unsafe impl Sync for i16 {} @@ -294,6 +296,15 @@ impl PartialEq for u64 { } } +impl PartialEq for u128 { + fn eq(&self, other: &u128) -> bool { + (*self) == (*other) + } + fn ne(&self, other: &u128) -> bool { + (*self) != (*other) + } +} + impl PartialEq for usize { fn eq(&self, other: &usize) -> bool { (*self) == (*other) diff --git a/example/mini_core_hello_world.rs b/example/mini_core_hello_world.rs index 4dff341e67d0..ad244814208f 100644 --- a/example/mini_core_hello_world.rs +++ b/example/mini_core_hello_world.rs @@ -171,8 +171,7 @@ fn main() { assert_eq!(intrinsics::bitreverse(0xddccu16), 0x33bbu16); assert_eq!(intrinsics::bitreverse(0xffee_ddccu32), 0x33bb77ffu32); assert_eq!(intrinsics::bitreverse(0x1234_5678_ffee_ddccu64), 0x33bb77ff1e6a2c48u64); - // != cannot be applied to type u128? - // assert_eq!(intrinsics::bitreverse(0x1234_5678_ffee_ddcc_1234_5678_ffee_ddccu128), 0x33bb77ff1e6a2c4833bb77ff1e6a2c48u128); + assert_eq!(intrinsics::bitreverse(0x1234_5678_ffee_ddcc_1234_5678_ffee_ddccu128), 0x33bb77ff1e6a2c4833bb77ff1e6a2c48u128); assert_eq!(intrinsics::bswap(0xabu8), 0xabu8); assert_eq!(intrinsics::bswap(0xddccu16), 0xccddu16); From 68b8500235fe2641afa6a36f1786a9d5d5105065 Mon Sep 17 00:00:00 2001 From: Arpan Kapoor Date: Mon, 27 Mar 2023 20:33:05 +0530 Subject: [PATCH 314/356] move u128 test to std_example --- example/mini_core.rs | 11 ----------- example/mini_core_hello_world.rs | 1 - example/std_example.rs | 1 + 3 files changed, 1 insertion(+), 12 deletions(-) diff --git a/example/mini_core.rs b/example/mini_core.rs index 018bbaf025da..637b8dc53fef 100644 --- a/example/mini_core.rs +++ b/example/mini_core.rs @@ -59,7 +59,6 @@ unsafe impl Copy for u8 {} unsafe impl Copy for u16 {} unsafe impl Copy for u32 {} unsafe impl Copy for u64 {} -unsafe impl Copy for u128 {} unsafe impl Copy for usize {} unsafe impl Copy for i8 {} unsafe impl Copy for i16 {} @@ -80,7 +79,6 @@ unsafe impl Sync for u8 {} unsafe impl Sync for u16 {} unsafe impl Sync for u32 {} unsafe impl Sync for u64 {} -unsafe impl Sync for u128 {} unsafe impl Sync for usize {} unsafe impl Sync for i8 {} unsafe impl Sync for i16 {} @@ -296,15 +294,6 @@ impl PartialEq for u64 { } } -impl PartialEq for u128 { - fn eq(&self, other: &u128) -> bool { - (*self) == (*other) - } - fn ne(&self, other: &u128) -> bool { - (*self) != (*other) - } -} - impl PartialEq for usize { fn eq(&self, other: &usize) -> bool { (*self) == (*other) diff --git a/example/mini_core_hello_world.rs b/example/mini_core_hello_world.rs index ad244814208f..1c8ca6b9d7c8 100644 --- a/example/mini_core_hello_world.rs +++ b/example/mini_core_hello_world.rs @@ -171,7 +171,6 @@ fn main() { assert_eq!(intrinsics::bitreverse(0xddccu16), 0x33bbu16); assert_eq!(intrinsics::bitreverse(0xffee_ddccu32), 0x33bb77ffu32); assert_eq!(intrinsics::bitreverse(0x1234_5678_ffee_ddccu64), 0x33bb77ff1e6a2c48u64); - assert_eq!(intrinsics::bitreverse(0x1234_5678_ffee_ddcc_1234_5678_ffee_ddccu128), 0x33bb77ff1e6a2c4833bb77ff1e6a2c48u128); assert_eq!(intrinsics::bswap(0xabu8), 0xabu8); assert_eq!(intrinsics::bswap(0xddccu16), 0xccddu16); diff --git a/example/std_example.rs b/example/std_example.rs index 5c171c49fd19..18f2ddcde126 100644 --- a/example/std_example.rs +++ b/example/std_example.rs @@ -58,6 +58,7 @@ fn main() { assert_eq!(0b0000000000000000000000000010000010000000000000000000000000000000_0000000000100000000000000000000000001000000000000100000000000000u128.leading_zeros(), 26); assert_eq!(0b0000000000000000000000000010000000000000000000000000000000000000_0000000000000000000000000000000000001000000000000000000010000000u128.trailing_zeros(), 7); + assert_eq!(0x1234_5678_ffee_ddcc_1234_5678_ffee_ddccu128.reverse_bits(), 0x33bb77ff1e6a2c4833bb77ff1e6a2c48u128); let _d = 0i128.checked_div(2i128); let _d = 0u128.checked_div(2u128); From 7e2e5054a6dd0a4d40b6e28309919287ff48efbd Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Wed, 5 Apr 2023 16:30:21 +0200 Subject: [PATCH 315/356] Update gccjit dependency version --- Cargo.lock | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index ac0fc0eeb7e9..6e94c03a1540 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -35,7 +35,7 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" -source = "git+https://github.com/antoyo/gccjit.rs#eefb8c662d61477f34b7c32d26bcda5f1ef08432" +source = "git+https://github.com/antoyo/gccjit.rs#98a29ddd64f662beb5d11810434fbeaad4a1856c" dependencies = [ "gccjit_sys", ] @@ -43,9 +43,9 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" -source = "git+https://github.com/antoyo/gccjit.rs#eefb8c662d61477f34b7c32d26bcda5f1ef08432" +source = "git+https://github.com/antoyo/gccjit.rs#98a29ddd64f662beb5d11810434fbeaad4a1856c" dependencies = [ - "libc 0.1.12", + "libc", ] [[package]] @@ -64,7 +64,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "7fcd999463524c52659517fe2cea98493cfe485d10565e7b0fb07dbba7ad2753" dependencies = [ "cfg-if", - "libc 0.2.112", + "libc", "wasi", ] @@ -74,7 +74,7 @@ version = "0.1.19" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "62b467343b94ba476dcb2500d242dadbb39557df889310ac77c5d99100aaac33" dependencies = [ - "libc 0.2.112", + "libc", ] [[package]] @@ -85,7 +85,7 @@ checksum = "96bd995a092cac79868250589869b5a5d656b02a02bd74c8ebdc566dc7203090" dependencies = [ "fm", "getopts", - "libc 0.2.112", + "libc", "num_cpus", "termcolor", "threadpool", @@ -93,12 +93,6 @@ dependencies = [ "walkdir", ] -[[package]] -name = "libc" -version = "0.1.12" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e32a70cf75e5846d53a673923498228bbec6a8624708a9ea5645f075d6276122" - [[package]] name = "libc" version = "0.2.112" @@ -118,7 +112,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "05499f3756671c15885fee9034446956fff3f243d6077b91e5767df161f766b3" dependencies = [ "hermit-abi", - "libc 0.2.112", + "libc", ] [[package]] @@ -133,7 +127,7 @@ version = "0.8.4" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "2e7573632e6454cf6b99d7aac4ccca54be06da05aca2ef7423d22d27d4d4bcd8" dependencies = [ - "libc 0.2.112", + "libc", "rand_chacha", "rand_core", "rand_hc", @@ -234,7 +228,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "dac1c663cfc93810f88aed9b8941d48cabf856a1b111c29a40439018d870eb22" dependencies = [ "cfg-if", - "libc 0.2.112", + "libc", "rand", "redox_syscall", "remove_dir_all", @@ -271,7 +265,7 @@ version = "0.2.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "9f200f5b12eb75f8c1ed65abd4b2db8a6e1b138a20de009dacee265a2498f3f6" dependencies = [ - "libc 0.2.112", + "libc", ] [[package]] From b769ad26b08f65e9d741d8b720b9bfb8038a2808 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Wed, 5 Apr 2023 16:20:20 +0200 Subject: [PATCH 316/356] Add `llvm` folder to .gitignore file --- .gitignore | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index 12ed56675639..c5ed7de200c2 100644 --- a/.gitignore +++ b/.gitignore @@ -23,3 +23,5 @@ benchmarks tools/llvm-project tools/llvmint tools/llvmint-2 +# The `llvm` folder is generated by the `tools/generate_intrinsics.py` script to update intrinsics. +llvm From 98482ad1e4b690f349509460f2e05333a05822b1 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Wed, 5 Apr 2023 16:17:45 +0200 Subject: [PATCH 317/356] Regen intrinsics --- src/intrinsic/archs.rs | 50 ++++-------------------------------------- 1 file changed, 4 insertions(+), 46 deletions(-) diff --git a/src/intrinsic/archs.rs b/src/intrinsic/archs.rs index 8a4559355ea6..8cd8d1bfb429 100644 --- a/src/intrinsic/archs.rs +++ b/src/intrinsic/archs.rs @@ -3020,8 +3020,6 @@ match name { "llvm.nvvm.div.rz.ftz.f" => "__nvvm_div_rz_ftz_f", "llvm.nvvm.ex2.approx.d" => "__nvvm_ex2_approx_d", "llvm.nvvm.ex2.approx.f" => "__nvvm_ex2_approx_f", - "llvm.nvvm.ex2.approx.f16" => "__nvvm_ex2_approx_f16", - "llvm.nvvm.ex2.approx.f16x2" => "__nvvm_ex2_approx_f16x2", "llvm.nvvm.ex2.approx.ftz.f" => "__nvvm_ex2_approx_ftz_f", "llvm.nvvm.f2bf16.rn" => "__nvvm_f2bf16_rn", "llvm.nvvm.f2bf16.rn.relu" => "__nvvm_f2bf16_rn_relu", @@ -3083,21 +3081,9 @@ match name { "llvm.nvvm.fma.rn.bf16x2" => "__nvvm_fma_rn_bf16x2", "llvm.nvvm.fma.rn.d" => "__nvvm_fma_rn_d", "llvm.nvvm.fma.rn.f" => "__nvvm_fma_rn_f", - "llvm.nvvm.fma.rn.f16" => "__nvvm_fma_rn_f16", - "llvm.nvvm.fma.rn.f16x2" => "__nvvm_fma_rn_f16x2", "llvm.nvvm.fma.rn.ftz.f" => "__nvvm_fma_rn_ftz_f", - "llvm.nvvm.fma.rn.ftz.f16" => "__nvvm_fma_rn_ftz_f16", - "llvm.nvvm.fma.rn.ftz.f16x2" => "__nvvm_fma_rn_ftz_f16x2", - "llvm.nvvm.fma.rn.ftz.relu.f16" => "__nvvm_fma_rn_ftz_relu_f16", - "llvm.nvvm.fma.rn.ftz.relu.f16x2" => "__nvvm_fma_rn_ftz_relu_f16x2", - "llvm.nvvm.fma.rn.ftz.sat.f16" => "__nvvm_fma_rn_ftz_sat_f16", - "llvm.nvvm.fma.rn.ftz.sat.f16x2" => "__nvvm_fma_rn_ftz_sat_f16x2", "llvm.nvvm.fma.rn.relu.bf16" => "__nvvm_fma_rn_relu_bf16", "llvm.nvvm.fma.rn.relu.bf16x2" => "__nvvm_fma_rn_relu_bf16x2", - "llvm.nvvm.fma.rn.relu.f16" => "__nvvm_fma_rn_relu_f16", - "llvm.nvvm.fma.rn.relu.f16x2" => "__nvvm_fma_rn_relu_f16x2", - "llvm.nvvm.fma.rn.sat.f16" => "__nvvm_fma_rn_sat_f16", - "llvm.nvvm.fma.rn.sat.f16x2" => "__nvvm_fma_rn_sat_f16x2", "llvm.nvvm.fma.rp.d" => "__nvvm_fma_rp_d", "llvm.nvvm.fma.rp.f" => "__nvvm_fma_rp_f", "llvm.nvvm.fma.rp.ftz.f" => "__nvvm_fma_rp_ftz_f", @@ -3108,68 +3094,36 @@ match name { "llvm.nvvm.fmax.bf16x2" => "__nvvm_fmax_bf16x2", "llvm.nvvm.fmax.d" => "__nvvm_fmax_d", "llvm.nvvm.fmax.f" => "__nvvm_fmax_f", - "llvm.nvvm.fmax.f16" => "__nvvm_fmax_f16", - "llvm.nvvm.fmax.f16x2" => "__nvvm_fmax_f16x2", "llvm.nvvm.fmax.ftz.f" => "__nvvm_fmax_ftz_f", - "llvm.nvvm.fmax.ftz.f16" => "__nvvm_fmax_ftz_f16", - "llvm.nvvm.fmax.ftz.f16x2" => "__nvvm_fmax_ftz_f16x2", "llvm.nvvm.fmax.ftz.nan.f" => "__nvvm_fmax_ftz_nan_f", - "llvm.nvvm.fmax.ftz.nan.f16" => "__nvvm_fmax_ftz_nan_f16", - "llvm.nvvm.fmax.ftz.nan.f16x2" => "__nvvm_fmax_ftz_nan_f16x2", "llvm.nvvm.fmax.ftz.nan.xorsign.abs.f" => "__nvvm_fmax_ftz_nan_xorsign_abs_f", - "llvm.nvvm.fmax.ftz.nan.xorsign.abs.f16" => "__nvvm_fmax_ftz_nan_xorsign_abs_f16", - "llvm.nvvm.fmax.ftz.nan.xorsign.abs.f16x2" => "__nvvm_fmax_ftz_nan_xorsign_abs_f16x2", "llvm.nvvm.fmax.ftz.xorsign.abs.f" => "__nvvm_fmax_ftz_xorsign_abs_f", - "llvm.nvvm.fmax.ftz.xorsign.abs.f16" => "__nvvm_fmax_ftz_xorsign_abs_f16", - "llvm.nvvm.fmax.ftz.xorsign.abs.f16x2" => "__nvvm_fmax_ftz_xorsign_abs_f16x2", "llvm.nvvm.fmax.nan.bf16" => "__nvvm_fmax_nan_bf16", "llvm.nvvm.fmax.nan.bf16x2" => "__nvvm_fmax_nan_bf16x2", "llvm.nvvm.fmax.nan.f" => "__nvvm_fmax_nan_f", - "llvm.nvvm.fmax.nan.f16" => "__nvvm_fmax_nan_f16", - "llvm.nvvm.fmax.nan.f16x2" => "__nvvm_fmax_nan_f16x2", "llvm.nvvm.fmax.nan.xorsign.abs.bf16" => "__nvvm_fmax_nan_xorsign_abs_bf16", "llvm.nvvm.fmax.nan.xorsign.abs.bf16x2" => "__nvvm_fmax_nan_xorsign_abs_bf16x2", "llvm.nvvm.fmax.nan.xorsign.abs.f" => "__nvvm_fmax_nan_xorsign_abs_f", - "llvm.nvvm.fmax.nan.xorsign.abs.f16" => "__nvvm_fmax_nan_xorsign_abs_f16", - "llvm.nvvm.fmax.nan.xorsign.abs.f16x2" => "__nvvm_fmax_nan_xorsign_abs_f16x2", "llvm.nvvm.fmax.xorsign.abs.bf16" => "__nvvm_fmax_xorsign_abs_bf16", "llvm.nvvm.fmax.xorsign.abs.bf16x2" => "__nvvm_fmax_xorsign_abs_bf16x2", "llvm.nvvm.fmax.xorsign.abs.f" => "__nvvm_fmax_xorsign_abs_f", - "llvm.nvvm.fmax.xorsign.abs.f16" => "__nvvm_fmax_xorsign_abs_f16", - "llvm.nvvm.fmax.xorsign.abs.f16x2" => "__nvvm_fmax_xorsign_abs_f16x2", "llvm.nvvm.fmin.bf16" => "__nvvm_fmin_bf16", "llvm.nvvm.fmin.bf16x2" => "__nvvm_fmin_bf16x2", "llvm.nvvm.fmin.d" => "__nvvm_fmin_d", "llvm.nvvm.fmin.f" => "__nvvm_fmin_f", - "llvm.nvvm.fmin.f16" => "__nvvm_fmin_f16", - "llvm.nvvm.fmin.f16x2" => "__nvvm_fmin_f16x2", "llvm.nvvm.fmin.ftz.f" => "__nvvm_fmin_ftz_f", - "llvm.nvvm.fmin.ftz.f16" => "__nvvm_fmin_ftz_f16", - "llvm.nvvm.fmin.ftz.f16x2" => "__nvvm_fmin_ftz_f16x2", "llvm.nvvm.fmin.ftz.nan.f" => "__nvvm_fmin_ftz_nan_f", - "llvm.nvvm.fmin.ftz.nan.f16" => "__nvvm_fmin_ftz_nan_f16", - "llvm.nvvm.fmin.ftz.nan.f16x2" => "__nvvm_fmin_ftz_nan_f16x2", "llvm.nvvm.fmin.ftz.nan.xorsign.abs.f" => "__nvvm_fmin_ftz_nan_xorsign_abs_f", - "llvm.nvvm.fmin.ftz.nan.xorsign.abs.f16" => "__nvvm_fmin_ftz_nan_xorsign_abs_f16", - "llvm.nvvm.fmin.ftz.nan.xorsign.abs.f16x2" => "__nvvm_fmin_ftz_nan_xorsign_abs_f16x2", "llvm.nvvm.fmin.ftz.xorsign.abs.f" => "__nvvm_fmin_ftz_xorsign_abs_f", - "llvm.nvvm.fmin.ftz.xorsign.abs.f16" => "__nvvm_fmin_ftz_xorsign_abs_f16", - "llvm.nvvm.fmin.ftz.xorsign.abs.f16x2" => "__nvvm_fmin_ftz_xorsign_abs_f16x2", "llvm.nvvm.fmin.nan.bf16" => "__nvvm_fmin_nan_bf16", "llvm.nvvm.fmin.nan.bf16x2" => "__nvvm_fmin_nan_bf16x2", "llvm.nvvm.fmin.nan.f" => "__nvvm_fmin_nan_f", - "llvm.nvvm.fmin.nan.f16" => "__nvvm_fmin_nan_f16", - "llvm.nvvm.fmin.nan.f16x2" => "__nvvm_fmin_nan_f16x2", "llvm.nvvm.fmin.nan.xorsign.abs.bf16" => "__nvvm_fmin_nan_xorsign_abs_bf16", "llvm.nvvm.fmin.nan.xorsign.abs.bf16x2" => "__nvvm_fmin_nan_xorsign_abs_bf16x2", "llvm.nvvm.fmin.nan.xorsign.abs.f" => "__nvvm_fmin_nan_xorsign_abs_f", - "llvm.nvvm.fmin.nan.xorsign.abs.f16" => "__nvvm_fmin_nan_xorsign_abs_f16", - "llvm.nvvm.fmin.nan.xorsign.abs.f16x2" => "__nvvm_fmin_nan_xorsign_abs_f16x2", "llvm.nvvm.fmin.xorsign.abs.bf16" => "__nvvm_fmin_xorsign_abs_bf16", "llvm.nvvm.fmin.xorsign.abs.bf16x2" => "__nvvm_fmin_xorsign_abs_bf16x2", "llvm.nvvm.fmin.xorsign.abs.f" => "__nvvm_fmin_xorsign_abs_f", - "llvm.nvvm.fmin.xorsign.abs.f16" => "__nvvm_fmin_xorsign_abs_f16", - "llvm.nvvm.fmin.xorsign.abs.f16x2" => "__nvvm_fmin_xorsign_abs_f16x2", "llvm.nvvm.fns" => "__nvvm_fns", "llvm.nvvm.h2f" => "__nvvm_h2f", "llvm.nvvm.i2d.rm" => "__nvvm_i2d_rm", @@ -7895,6 +7849,10 @@ match name { "llvm.x86.subborrow.u64" => "__builtin_ia32_subborrow_u64", "llvm.x86.tbm.bextri.u32" => "__builtin_ia32_bextri_u32", "llvm.x86.tbm.bextri.u64" => "__builtin_ia32_bextri_u64", + "llvm.x86.tcmmimfp16ps" => "__builtin_ia32_tcmmimfp16ps", + "llvm.x86.tcmmimfp16ps.internal" => "__builtin_ia32_tcmmimfp16ps_internal", + "llvm.x86.tcmmrlfp16ps" => "__builtin_ia32_tcmmrlfp16ps", + "llvm.x86.tcmmrlfp16ps.internal" => "__builtin_ia32_tcmmrlfp16ps_internal", "llvm.x86.tdpbf16ps" => "__builtin_ia32_tdpbf16ps", "llvm.x86.tdpbf16ps.internal" => "__builtin_ia32_tdpbf16ps_internal", "llvm.x86.tdpbssd" => "__builtin_ia32_tdpbssd", From 65a20d3f711e8cb6ea418fb7948a9c4a054d5bc8 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Wed, 5 Apr 2023 22:22:42 -0400 Subject: [PATCH 318/356] Fix vpshrd llvm instrinsics --- src/intrinsic/llvm.rs | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 0edec566be30..f28348380d7b 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -313,6 +313,13 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc let new_args = args.to_vec(); args = vec![new_args[1], new_args[0], new_args[2], new_args[3], new_args[4]].into(); }, + "__builtin_ia32_vpshrdv_v8di" | "__builtin_ia32_vpshrdv_v4di" | "__builtin_ia32_vpshrdv_v2di" | + "__builtin_ia32_vpshrdv_v16si" | "__builtin_ia32_vpshrdv_v8si" | "__builtin_ia32_vpshrdv_v4si" | + "__builtin_ia32_vpshrdv_v32hi" | "__builtin_ia32_vpshrdv_v16hi" | "__builtin_ia32_vpshrdv_v8hi" => { + // The first two arguments are reversed, compared to LLVM. + let new_args = args.to_vec(); + args = vec![new_args[1], new_args[0], new_args[2]].into(); + }, _ => (), } } From a6d7ab5b00e1b74bf77cab783c23c805f144b43f Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 8 Apr 2023 12:39:58 -0400 Subject: [PATCH 319/356] Run emulated stdarch tests in the CI --- .github/workflows/stdarch.yml | 32 +++++++++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/.github/workflows/stdarch.yml b/.github/workflows/stdarch.yml index 42fb35e738ff..556c64448332 100644 --- a/.github/workflows/stdarch.yml +++ b/.github/workflows/stdarch.yml @@ -20,9 +20,9 @@ jobs: matrix: libgccjit_version: - { gcc: "libgccjit.so", artifacts_branch: "master" } - commands: [ - "--test-successful-rustc --nb-parts 2 --current-part 0", - "--test-successful-rustc --nb-parts 2 --current-part 1", + cargo_runner: [ + "sde -future -rtm_mode full --", + "", ] steps: @@ -36,6 +36,20 @@ jobs: - name: Install packages run: sudo apt-get install ninja-build ripgrep + - name: Install Intel Software Development Emulator + if: ${{ matrix.cargo_runner }} + run: | + mkdir intel-sde + cd intel-sde + dir=sde-external-9.14.0-2022-10-25-lin + file=$dir.tar.xz + wget https://downloadmirror.intel.com/751535/$file + tar xvf $file + sudo mkdir /usr/share/intel-sde + sudo cp -r $dir/* /usr/share/intel-sde + sudo ln -s /usr/share/intel-sde/sde /usr/bin/sde + sudo ln -s /usr/share/intel-sde/sde64 /usr/bin/sde64 + - name: Download artifact uses: dawidd6/action-download-artifact@v2 with: @@ -91,6 +105,10 @@ jobs: ./prepare_build.sh ./build.sh --release --release-sysroot cargo test + + - name: Clean + if: ${{ !matrix.cargo_runner }} + run: | ./clean_all.sh - name: Prepare dependencies @@ -107,10 +125,18 @@ jobs: args: --release - name: Run tests + if: ${{ !matrix.cargo_runner }} run: | ./test.sh --release --clean --release-sysroot --build-sysroot --mini-tests --std-tests --test-libcore - name: Run stdarch tests + if: ${{ !matrix.cargo_runner }} run: | cd build_sysroot/sysroot_src/library/stdarch/ CHANNEL=release TARGET=x86_64-unknown-linux-gnu ../../../../cargo.sh test + + - name: Run stdarch tests + if: ${{ matrix.cargo_runner }} + run: | + cd build_sysroot/sysroot_src/library/stdarch/ + STDARCH_TEST_EVERYTHING=1 CHANNEL=release CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER="${{ matrix.cargo_runner }}" TARGET=x86_64-unknown-linux-gnu ../../../../cargo.sh test -- --skip rtm --skip tbm --skip sse4a From b93041af0a3100feb8785a6ff17b242c21d1a6f8 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 16 Apr 2023 14:12:42 -0400 Subject: [PATCH 320/356] Add support for inline attribute --- Cargo.lock | 4 ++-- Cargo.toml | 2 +- src/attributes.rs | 39 +++++++++++++++++++++++++++++++++++++++ src/lib.rs | 2 ++ 4 files changed, 44 insertions(+), 3 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 6e94c03a1540..3c5357eec105 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -35,7 +35,7 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" -source = "git+https://github.com/antoyo/gccjit.rs#98a29ddd64f662beb5d11810434fbeaad4a1856c" +source = "git+https://github.com/antoyo/gccjit.rs#d6e52626cfc6f487094a5d5ac66302baf3439984" dependencies = [ "gccjit_sys", ] @@ -43,7 +43,7 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" -source = "git+https://github.com/antoyo/gccjit.rs#98a29ddd64f662beb5d11810434fbeaad4a1856c" +source = "git+https://github.com/antoyo/gccjit.rs#d6e52626cfc6f487094a5d5ac66302baf3439984" dependencies = [ "libc", ] diff --git a/Cargo.toml b/Cargo.toml index 81066d9ce1f0..7285e3eaf519 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -25,7 +25,7 @@ master = ["gccjit/master"] gccjit = { git = "https://github.com/antoyo/gccjit.rs" } # Local copy. -#gccjit = { path = "../gccjit.rs" } +# gccjit = { path = "../gccjit.rs" } smallvec = { version = "1.6.1", features = ["union", "may_dangle"] } diff --git a/src/attributes.rs b/src/attributes.rs index 243a1a36dd09..23c1f886e09e 100644 --- a/src/attributes.rs +++ b/src/attributes.rs @@ -2,9 +2,13 @@ use gccjit::FnAttribute; use gccjit::Function; use rustc_attr::InstructionSetAttr; +#[cfg(feature="master")] +use rustc_attr::InlineAttr; use rustc_codegen_ssa::target_features::tied_target_features; use rustc_data_structures::fx::FxHashMap; use rustc_middle::ty; +#[cfg(feature="master")] +use rustc_middle::middle::codegen_fn_attrs::CodegenFnAttrFlags; use rustc_session::Session; use rustc_span::symbol::sym; use smallvec::{smallvec, SmallVec}; @@ -67,6 +71,24 @@ fn to_gcc_features<'a>(sess: &Session, s: &'a str) -> SmallVec<[&'a str; 2]> { } } +/// Get GCC attribute for the provided inline heuristic. +#[cfg(feature="master")] +#[inline] +fn inline_attr<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, inline: InlineAttr) -> Option> { + match inline { + InlineAttr::Hint => Some(FnAttribute::Inline), + InlineAttr::Always => Some(FnAttribute::AlwaysInline), + InlineAttr::Never => { + if cx.sess().target.arch != "amdgpu" { + Some(FnAttribute::NoInline) + } else { + None + } + } + InlineAttr::None => None, + } +} + /// Composite function which sets GCC attributes for function depending on its AST (`#[attribute]`) /// attributes. pub fn from_fn_attrs<'gcc, 'tcx>( @@ -77,6 +99,23 @@ pub fn from_fn_attrs<'gcc, 'tcx>( ) { let codegen_fn_attrs = cx.tcx.codegen_fn_attrs(instance.def_id()); + #[cfg(feature="master")] + { + let inline = + if codegen_fn_attrs.flags.contains(CodegenFnAttrFlags::NAKED) { + InlineAttr::Never + } + else if codegen_fn_attrs.inline == InlineAttr::None && instance.def.requires_inline(cx.tcx) { + InlineAttr::Hint + } + else { + codegen_fn_attrs.inline + }; + if let Some(attr) = inline_attr(cx, inline) { + func.add_attribute(attr); + } + } + let function_features = codegen_fn_attrs.target_features.iter().map(|features| features.as_str()).collect::>(); diff --git a/src/lib.rs b/src/lib.rs index 1b7feb5f8a18..3b26e248fc26 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -110,6 +110,8 @@ impl CodegenBackend for GccCodegenBackend { } fn init(&self, sess: &Session) { + #[cfg(feature="master")] + gccjit::set_global_personality_function_name(b"rust_eh_personality\0"); if sess.lto() != Lto::No { sess.emit_warning(LTONotSupported {}); } From a512e98028bf830e1ebc0fa018d210801c86793c Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Thu, 25 May 2023 09:17:59 -0400 Subject: [PATCH 321/356] Set visibility of global --- src/consts.rs | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/consts.rs b/src/consts.rs index 792ab8f890d8..56513c29ce09 100644 --- a/src/consts.rs +++ b/src/consts.rs @@ -1,5 +1,5 @@ #[cfg(feature = "master")] -use gccjit::FnAttribute; +use gccjit::{FnAttribute, VarAttribute, Visibility}; use gccjit::{Function, GlobalKind, LValue, RValue, ToRValue, Type}; use rustc_codegen_ssa::traits::{BaseTypeMethods, ConstMethods, DerivedTypeMethods, StaticMethods}; use rustc_middle::span_bug; @@ -249,7 +249,8 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { ); if !self.tcx.is_reachable_non_generic(def_id) { - // TODO(antoyo): set visibility. + #[cfg(feature = "master")] + global.add_attribute(VarAttribute::Visibility(Visibility::Hidden)); } global From 2c6b9792955336ad25feb64cf040fd9be5dccb7c Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Fri, 2 Jun 2023 16:22:50 +0200 Subject: [PATCH 322/356] Regen intrinsics with latest LLVM version --- src/intrinsic/archs.rs | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/intrinsic/archs.rs b/src/intrinsic/archs.rs index 8cd8d1bfb429..3fc1dfdb4475 100644 --- a/src/intrinsic/archs.rs +++ b/src/intrinsic/archs.rs @@ -2967,10 +2967,6 @@ match name { "llvm.nvvm.clz.ll" => "__nvvm_clz_ll", "llvm.nvvm.cos.approx.f" => "__nvvm_cos_approx_f", "llvm.nvvm.cos.approx.ftz.f" => "__nvvm_cos_approx_ftz_f", - "llvm.nvvm.cp.async.ca.shared.global.16" => "__nvvm_cp_async_ca_shared_global_16", - "llvm.nvvm.cp.async.ca.shared.global.4" => "__nvvm_cp_async_ca_shared_global_4", - "llvm.nvvm.cp.async.ca.shared.global.8" => "__nvvm_cp_async_ca_shared_global_8", - "llvm.nvvm.cp.async.cg.shared.global.16" => "__nvvm_cp_async_cg_shared_global_16", "llvm.nvvm.cp.async.commit.group" => "__nvvm_cp_async_commit_group", "llvm.nvvm.cp.async.mbarrier.arrive" => "__nvvm_cp_async_mbarrier_arrive", "llvm.nvvm.cp.async.mbarrier.arrive.noinc" => "__nvvm_cp_async_mbarrier_arrive_noinc", From 8c2b14f7088c31c442f1ebc5c0ad7d5e22011963 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 11 Jun 2023 11:41:06 -0400 Subject: [PATCH 323/356] Update to nightly-2023-06-11 --- rust-toolchain | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rust-toolchain b/rust-toolchain index 933ecd45baad..90f9a621077a 100644 --- a/rust-toolchain +++ b/rust-toolchain @@ -1,3 +1,3 @@ [toolchain] -channel = "nightly-2023-03-02" +channel = "nightly-2023-06-11" components = ["rust-src", "rustc-dev", "llvm-tools-preview"] From c8376e4c78cfdc4d55b6c818fc888a6d62dc08fe Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 3 Jun 2023 09:04:12 -0400 Subject: [PATCH 324/356] Add usage of git subtree to readme --- Readme.md | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Readme.md b/Readme.md index bb7419438925..593cd3f9bbf4 100644 --- a/Readme.md +++ b/Readme.md @@ -193,7 +193,7 @@ Using git-subtree with `rustc` requires a patched git to make it work. The PR that is needed is [here](https://github.com/gitgitgadget/git/pull/493). Use the following instructions to install it: -``` +```bash git clone git@github.com:tqc/git.git cd git git checkout tqc/subtree @@ -204,6 +204,12 @@ make cp git-subtree ~/bin ``` +Then, do a sync with this command: + +```bash +PATH="$HOME/bin:$PATH" ~/bin/git-subtree push -P compiler/rustc_codegen_gcc/ ../rustc_codegen_gcc/ sync_branch_name +``` + ### How to use [mem-trace](https://github.com/antoyo/mem-trace) `rustc` needs to be built without `jemalloc` so that `mem-trace` can overload `malloc` since `jemalloc` is linked statically, so a `LD_PRELOAD`-ed library won't a chance to intercept the calls to `malloc`. From 94e5c2701228b6fc8d765136967ddc6d51dff6a9 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 3 Jun 2023 09:34:56 -0400 Subject: [PATCH 325/356] Update libgccjit and mini_core --- Cargo.lock | 4 ++-- example/mini_core.rs | 16 +++++++++++++++- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 0f2e152f8ce5..1c8754bf675e 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -35,7 +35,7 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" -source = "git+https://github.com/antoyo/gccjit.rs#fe242b7eb26980e6c78859d51c8d4cc1e43381a3" +source = "git+https://github.com/antoyo/gccjit.rs#d6e52626cfc6f487094a5d5ac66302baf3439984" dependencies = [ "gccjit_sys", ] @@ -43,7 +43,7 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" -source = "git+https://github.com/antoyo/gccjit.rs#fe242b7eb26980e6c78859d51c8d4cc1e43381a3" +source = "git+https://github.com/antoyo/gccjit.rs#d6e52626cfc6f487094a5d5ac66302baf3439984" dependencies = [ "libc", ] diff --git a/example/mini_core.rs b/example/mini_core.rs index 637b8dc53fef..f0347db00cc2 100644 --- a/example/mini_core.rs +++ b/example/mini_core.rs @@ -451,6 +451,9 @@ pub unsafe fn drop_in_place(to_drop: *mut T) { drop_in_place(to_drop); } +#[lang = "unpin"] +pub auto trait Unpin {} + #[lang = "deref"] pub trait Deref { type Target: ?Sized; @@ -486,7 +489,18 @@ impl DispatchFromDyn> for Unique where T: Uns #[lang = "owned_box"] pub struct Box(Unique, A); -impl, U: ?Sized, A: Allocator> CoerceUnsized> for Box {} +impl, U: ?Sized> CoerceUnsized> for Box {} + +impl Box { + pub fn new(val: T) -> Box { + unsafe { + let size = intrinsics::size_of::(); + let ptr = libc::malloc(size); + intrinsics::copy(&val as *const T as *const u8, ptr, size); + Box(Unique { pointer: NonNull(ptr as *const T), _marker: PhantomData }, Global) + } + } +} impl Drop for Box { fn drop(&mut self) { From 4115e09c13a975b42d506e2db6119d7c3ff1876e Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 4 Jun 2023 13:14:55 -0400 Subject: [PATCH 326/356] Fix for opaque pointers --- Cargo.toml | 2 +- src/builder.rs | 40 ++++++++++++++++++++++++++-------------- src/type_of.rs | 6 +++--- 3 files changed, 30 insertions(+), 18 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index 7285e3eaf519..81066d9ce1f0 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -25,7 +25,7 @@ master = ["gccjit/master"] gccjit = { git = "https://github.com/antoyo/gccjit.rs" } # Local copy. -# gccjit = { path = "../gccjit.rs" } +#gccjit = { path = "../gccjit.rs" } smallvec = { version = "1.6.1", features = ["union", "may_dangle"] } diff --git a/src/builder.rs b/src/builder.rs index f9ea0f004564..d578a0df51d6 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -280,8 +280,17 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { } } - fn function_ptr_call(&mut self, func_ptr: RValue<'gcc>, args: &[RValue<'gcc>], _funclet: Option<&Funclet>) -> RValue<'gcc> { - let gcc_func = func_ptr.get_type().dyncast_function_ptr_type().expect("function ptr"); + fn function_ptr_call(&mut self, typ: Type<'gcc>, mut func_ptr: RValue<'gcc>, args: &[RValue<'gcc>], _funclet: Option<&Funclet>) -> RValue<'gcc> { + let gcc_func = + match func_ptr.get_type().dyncast_function_ptr_type() { + Some(func) => func, + None => { + // NOTE: due to opaque pointers now being used, we need to cast here. + let new_func_type = typ.dyncast_function_ptr_type().expect("function ptr"); + func_ptr = self.context.new_cast(None, func_ptr, typ); + new_func_type + }, + }; let func_name = format!("{:?}", func_ptr); let previous_arg_count = args.len(); let orig_args = args; @@ -424,16 +433,17 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { self.llbb().end_with_void_return(None) } - fn ret(&mut self, value: RValue<'gcc>) { - let value = - if self.structs_as_pointer.borrow().contains(&value) { - // NOTE: hack to workaround a limitation of the rustc API: see comment on - // CodegenCx.structs_as_pointer - value.dereference(None).to_rvalue() - } - else { - value - }; + fn ret(&mut self, mut value: RValue<'gcc>) { + if self.structs_as_pointer.borrow().contains(&value) { + // NOTE: hack to workaround a limitation of the rustc API: see comment on + // CodegenCx.structs_as_pointer + value = value.dereference(None).to_rvalue(); + } + let expected_return_type = self.current_func().get_return_type(); + if !expected_return_type.is_compatible_with(value.get_type()) { + // NOTE: due to opaque pointers now being used, we need to cast here. + value = self.context.new_cast(None, value, expected_return_type); + } self.llbb().end_with_return(None, value); } @@ -938,6 +948,8 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { element.get_address(None) } else if let Some(struct_type) = value_type.is_struct() { + // NOTE: due to opaque pointers now being used, we need to bitcast here. + let ptr = self.bitcast_if_needed(ptr, value_type.make_pointer()); ptr.dereference_field(None, struct_type.get_field(idx as i32)).get_address(None) } else { @@ -1356,7 +1368,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { fn call( &mut self, - _typ: Type<'gcc>, + typ: Type<'gcc>, _fn_attrs: Option<&CodegenFnAttrs>, fn_abi: Option<&FnAbi<'tcx, Ty<'tcx>>>, func: RValue<'gcc>, @@ -1370,7 +1382,7 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { } else { // If it's a not function that was defined, it's a function pointer. - self.function_ptr_call(func, args, funclet) + self.function_ptr_call(typ, func, args, funclet) }; if let Some(_fn_abi) = fn_abi { // TODO(bjorn3): Apply function attributes diff --git a/src/type_of.rs b/src/type_of.rs index 30a3fe67b854..74f016cf90ae 100644 --- a/src/type_of.rs +++ b/src/type_of.rs @@ -383,8 +383,8 @@ impl<'gcc, 'tcx> LayoutTypeMethods<'tcx> for CodegenCx<'gcc, 'tcx> { unimplemented!(); } - fn fn_decl_backend_type(&self, _fn_abi: &FnAbi<'tcx, Ty<'tcx>>) -> Type<'gcc> { - // FIXME(antoyo): return correct type. - self.type_void() + fn fn_decl_backend_type(&self, fn_abi: &FnAbi<'tcx, Ty<'tcx>>) -> Type<'gcc> { + let (return_type, param_types, variadic, _) = fn_abi.gcc_type(self); + self.context.new_function_pointer_type(None, return_type, ¶m_types, variadic) } } From e74bc5113dac9f00b2eabcd1963d05e0f1a84ec2 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 4 Jun 2023 18:21:44 -0400 Subject: [PATCH 327/356] Attempt to fix the tests --- build_sysroot/prepare_sysroot_src.sh | 8 ++++---- src/intrinsic/simd.rs | 9 +++++++-- src/lib.rs | 2 ++ test.sh | 15 ++++++++++++--- 4 files changed, 25 insertions(+), 9 deletions(-) diff --git a/build_sysroot/prepare_sysroot_src.sh b/build_sysroot/prepare_sysroot_src.sh index 56768bbf1d01..71b3876bac2c 100755 --- a/build_sysroot/prepare_sysroot_src.sh +++ b/build_sysroot/prepare_sysroot_src.sh @@ -29,10 +29,10 @@ git config user.name || git config user.name "None" git commit -m "Initial commit" -q for file in $(ls ../../patches/ | grep -v patcha); do -echo "[GIT] apply" $file -git apply ../../patches/$file -git add -A -git commit --no-gpg-sign -m "Patch $file" + echo "[GIT] apply" $file + git apply ../../patches/$file + git add -A + git commit --no-gpg-sign -m "Patch $file" done popd diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index b59c3a64f572..36b9c9b63641 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -165,10 +165,15 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>( InvalidMonomorphizationReturnIntegerType { span, name, ret_ty, out_ty } ); + let arg1 = args[0].immediate(); + // NOTE: we get different vector types for the same vector type and libgccjit doesn't + // compare them as equal, so bitcast. + // FIXME(antoyo): allow comparing vector types as equal in libgccjit. + let arg2 = bx.context.new_bitcast(None, args[1].immediate(), arg1.get_type()); return Ok(compare_simd_types( bx, - args[0].immediate(), - args[1].immediate(), + arg1, + arg2, in_elem, llret_ty, cmp_op, diff --git a/src/lib.rs b/src/lib.rs index 204741ca3c1b..3bf92c063022 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -1,3 +1,5 @@ +// FIXME: simple programs now segfault with a sysroot compile in release mode. + /* * TODO(antoyo): implement equality in libgccjit based on https://zpz.github.io/blog/overloading-equality-operator-in-cpp-class-hierarchy/ (for type equality?) * TODO(antoyo): support #[inline] attributes. diff --git a/test.sh b/test.sh index 6139892aefca..c62c49cef994 100755 --- a/test.sh +++ b/test.sh @@ -214,12 +214,14 @@ function setup_rustc() { rm config.toml || true cat > config.toml < Date: Thu, 8 Jun 2023 20:51:29 -0400 Subject: [PATCH 328/356] Add missing cast to fix another issue caused by opaque pointers --- src/builder.rs | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/builder.rs b/src/builder.rs index d578a0df51d6..f2775421ccd0 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -919,7 +919,9 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { self.context.new_bitcast(None, result, ptr_type) } - fn inbounds_gep(&mut self, _typ: Type<'gcc>, ptr: RValue<'gcc>, indices: &[RValue<'gcc>]) -> RValue<'gcc> { + fn inbounds_gep(&mut self, typ: Type<'gcc>, ptr: RValue<'gcc>, indices: &[RValue<'gcc>]) -> RValue<'gcc> { + // NOTE: due to opaque pointers now being used, we need to cast here. + let ptr = self.context.new_cast(None, ptr, typ.make_pointer()); // NOTE: array indexing is always considered in bounds in GCC (TODO(antoyo): to be verified). let mut indices = indices.into_iter(); let index = indices.next().expect("first index in inbounds_gep"); From 984b9c52ccc0d493d2215167ecb03d76e9cb30ec Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Fri, 9 Jun 2023 10:00:50 -0400 Subject: [PATCH 329/356] Improve sync instructions --- Readme.md | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Readme.md b/Readme.md index 593cd3f9bbf4..a93637d9038d 100644 --- a/Readme.md +++ b/Readme.md @@ -208,8 +208,17 @@ Then, do a sync with this command: ```bash PATH="$HOME/bin:$PATH" ~/bin/git-subtree push -P compiler/rustc_codegen_gcc/ ../rustc_codegen_gcc/ sync_branch_name +cd ../rustc_codegen_gcc +git checkout master +git pull +git checkout sync_branch_name +git merge master ``` +TODO: write a script that does the above. + +https://rust-lang.zulipchat.com/#narrow/stream/301329-t-devtools/topic/subtree.20madness/near/258877725 + ### How to use [mem-trace](https://github.com/antoyo/mem-trace) `rustc` needs to be built without `jemalloc` so that `mem-trace` can overload `malloc` since `jemalloc` is linked statically, so a `LD_PRELOAD`-ed library won't a chance to intercept the calls to `malloc`. From e9708ebcefe398d5d8669e80260a4c73415ddc1d Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 10 Jun 2023 14:08:33 -0400 Subject: [PATCH 330/356] Add note --- test.sh | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/test.sh b/test.sh index c62c49cef994..7c8fe55da14e 100755 --- a/test.sh +++ b/test.sh @@ -356,11 +356,12 @@ function test_rustc() { # We need to overwrite the sysroot in the tests, now. # TODO(antoyo): find a faster way to do this. # FIXME: this makes the stderr different since it changes the line numbers. - for file in $(find tests/ui -type f -name '*.rs'); do - sed -ie "1i // compile-flags: --sysroot "$(pwd)"/../build_sysroot/sysroot\n" $file - done + #for file in $(find tests/ui -type f -name '*.rs'); do + #sed -ie "1i // compile-flags: --sysroot "$(pwd)"/../build_sysroot/sysroot\n" $file + #done - RUSTC_ARGS="$TEST_FLAGS -Csymbol-mangling-version=v0 -Zcodegen-backend="$(pwd)"/../target/"$CHANNEL"/librustc_codegen_gcc."$dylib_ext"" + # TODO: copy the sysroot at the correct location to not have to use the --sysroot flag. + RUSTC_ARGS="$TEST_FLAGS -Csymbol-mangling-version=v0 -Zcodegen-backend="$(pwd)"/../target/"$CHANNEL"/librustc_codegen_gcc."$dylib_ext" --sysroot "$(pwd)"/../build_sysroot/sysroot" if [ $# -eq 0 ]; then # No argument supplied to the function. Doing nothing. From a0edbfb2d3f163f899156a2f2050b227463ba659 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 11 Jun 2023 11:35:35 -0400 Subject: [PATCH 331/356] Test to fix UI tests --- test.sh | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/test.sh b/test.sh index 7c8fe55da14e..5c5c26699b09 100755 --- a/test.sh +++ b/test.sh @@ -213,6 +213,13 @@ function setup_rustc() { rm config.toml || true + # TODO: copy in build_sysroot/build_sysroot.sh instead to avoid having to rebuild stage0 libraries everytime? + my_toolchain_dir=$HOME/.rustup/toolchains/my_toolchain + rm -rf $my_toolchain_dir + cp -r $HOME/.rustup/toolchains/$rust_toolchain-$TARGET_TRIPLE $my_toolchain_dir + rm -rf $my_toolchain_dir/lib/rustlib/x86_64-unknown-linux-gnu/ + cp -r ../build_sysroot/sysroot/* $my_toolchain_dir + cat > config.toml < ../trace + COMPILETEST_FORCE_STAGE0=1 ./x.py test --run always --stage 0 tests/ui/zero-sized/zero-sized-linkedlist-push.rs --rustc-args "$RUSTC_ARGS" } function test_failing_rustc() { From 90527b81c9c767adfef2c895fb8b776eb3ac3212 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 11 Jun 2023 16:04:00 -0400 Subject: [PATCH 332/356] Some fixes and cleanups --- rust-toolchain | 2 +- src/lib.rs | 2 +- test.sh | 17 ++++------------- 3 files changed, 6 insertions(+), 15 deletions(-) diff --git a/rust-toolchain b/rust-toolchain index 90f9a621077a..2614fa081a86 100644 --- a/rust-toolchain +++ b/rust-toolchain @@ -1,3 +1,3 @@ [toolchain] -channel = "nightly-2023-06-11" +channel = "nightly-2023-06-10" components = ["rust-src", "rustc-dev", "llvm-tools-preview"] diff --git a/src/lib.rs b/src/lib.rs index 3bf92c063022..7a89a449b692 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -79,7 +79,7 @@ use rustc_codegen_ssa::target_features::supported_target_features; use rustc_codegen_ssa::traits::{CodegenBackend, ExtraBackendMethods, ModuleBufferMethods, ThinBufferMethods, WriteBackendMethods}; use rustc_data_structures::fx::FxIndexMap; use rustc_errors::{DiagnosticMessage, ErrorGuaranteed, Handler, SubdiagnosticMessage}; -use rustc_macros::fluent_messages; +use rustc_fluent_macro::fluent_messages; use rustc_metadata::EncodedMetadata; use rustc_middle::dep_graph::{WorkProduct, WorkProductId}; use rustc_middle::query::Providers; diff --git a/test.sh b/test.sh index 5c5c26699b09..7c68e00771d6 100755 --- a/test.sh +++ b/test.sh @@ -213,7 +213,8 @@ function setup_rustc() { rm config.toml || true - # TODO: copy in build_sysroot/build_sysroot.sh instead to avoid having to rebuild stage0 libraries everytime? + # TODO: move these lines to build_sysroot/build_sysroot.sh instead to avoid having to rebuild stage0 libraries everytime? + # Since we can't override the sysroot anymore, we create a new toolchain and manually overwrite the sysroot directory. my_toolchain_dir=$HOME/.rustup/toolchains/my_toolchain rm -rf $my_toolchain_dir cp -r $HOME/.rustup/toolchains/$rust_toolchain-$TARGET_TRIPLE $my_toolchain_dir @@ -362,16 +363,7 @@ function test_rustc() { git checkout tests/ui/type-alias-impl-trait/auxiliary/cross_crate_ice2.rs git checkout tests/ui/macros/rfc-2011-nicer-assert-messages/auxiliary/common.rs - # We need to overwrite the sysroot in the tests, now. - # TODO(antoyo): find a faster way to do this. - # FIXME: this makes the stderr different since it changes the line numbers. - #for file in $(find tests/ui -type f -name '*.rs'); do - #sed -ie "1i // compile-flags: --sysroot "$(pwd)"/../build_sysroot/sysroot\n" $file - #done - - # TODO: copy the sysroot at the correct location to not have to use the --sysroot flag. - #RUSTC_ARGS="$TEST_FLAGS -Csymbol-mangling-version=v0 -Zcodegen-backend="$(pwd)"/../target/"$CHANNEL"/librustc_codegen_gcc."$dylib_ext"" - RUSTC_ARGS="$TEST_FLAGS -Csymbol-mangling-version=v0 -Zcodegen-backend="$(pwd)"/../target/"$CHANNEL"/librustc_codegen_gcc."$dylib_ext" --sysroot $HOME/.rustup/toolchains/$rust_toolchain-$TARGET_TRIPLE/bin/rustc" + RUSTC_ARGS="$TEST_FLAGS -Csymbol-mangling-version=v0 -Zcodegen-backend="$(pwd)"/../target/"$CHANNEL"/librustc_codegen_gcc."$dylib_ext"" if [ $# -eq 0 ]; then @@ -404,8 +396,7 @@ function test_rustc() { fi echo "[TEST] rustc test suite" - #COMPILETEST_FORCE_STAGE0=1 strace -f ./x.py test --run always --stage 0 tests/ui/ --rustc-args "$RUSTC_ARGS" &> ../trace - COMPILETEST_FORCE_STAGE0=1 ./x.py test --run always --stage 0 tests/ui/zero-sized/zero-sized-linkedlist-push.rs --rustc-args "$RUSTC_ARGS" + COMPILETEST_FORCE_STAGE0=1 ./x.py test --run always --stage 0 tests/ui --rustc-args "$RUSTC_ARGS" } function test_failing_rustc() { From 3371fce044f1f4aafe258d21f3e03774d30a1cab Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 11 Jun 2023 18:21:00 -0400 Subject: [PATCH 333/356] Fix tests --- failing-ui-tests.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index 8539e27ea6a5..1b0e30c920a5 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -54,8 +54,8 @@ tests/ui/issues/issue-40883.rs tests/ui/issues/issue-43853.rs tests/ui/issues/issue-47364.rs tests/ui/macros/rfc-2011-nicer-assert-messages/assert-without-captures-does-not-create-unnecessary-code.rs -tests/ui/rfc-2091-track-caller/std-panic-locations.rs -tests/ui/rfcs/rfc1857-drop-order.rs +tests/ui/rfcs/rfc-2091-track-caller/std-panic-locations.rs +tests/ui/rfcs/rfc-1857-stabilize-drop-order/drop-order.rs tests/ui/simd/issue-17170.rs tests/ui/simd/issue-39720.rs tests/ui/simd/issue-89193.rs From ef037e6d30b21363c48c47045b325a780fdde6d3 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 11 Jun 2023 19:27:39 -0400 Subject: [PATCH 334/356] Fix tests --- build_sysroot/Cargo.toml | 1 + failing-ui-tests.txt | 2 ++ src/declare.rs | 2 +- test.sh | 2 ++ 4 files changed, 6 insertions(+), 1 deletion(-) diff --git a/build_sysroot/Cargo.toml b/build_sysroot/Cargo.toml index cfadf47cc3f8..a84f86a82189 100644 --- a/build_sysroot/Cargo.toml +++ b/build_sysroot/Cargo.toml @@ -9,6 +9,7 @@ compiler_builtins = "0.1" alloc = { path = "./sysroot_src/library/alloc" } std = { path = "./sysroot_src/library/std", features = ["panic_unwind", "backtrace"] } test = { path = "./sysroot_src/library/test" } +proc_macro = { path = "./sysroot_src/library/proc_macro" } [patch.crates-io] rustc-std-workspace-core = { path = "./sysroot_src/library/rustc-std-workspace-core" } diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index 1b0e30c920a5..801464daae9a 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -66,3 +66,5 @@ tests/ui/generator/panic-safe.rs tests/ui/issues/issue-14875.rs tests/ui/issues/issue-29948.rs tests/ui/panic-while-printing.rs +tests/ui/enum-discriminant/get_discr.rs +tests/ui/panics/nested_panic_caught.rs diff --git a/src/declare.rs b/src/declare.rs index 4748e7e4be2a..493626c3cf5d 100644 --- a/src/declare.rs +++ b/src/declare.rs @@ -132,7 +132,7 @@ fn declare_raw_fn<'gcc>(cx: &CodegenCx<'gcc, '_>, name: &str, _callconv: () /*ll pub fn mangle_name(name: &str) -> String { name.replace(|char: char| { if !char.is_alphanumeric() && char != '_' { - debug_assert!("$.".contains(char), "Unsupported char in function name: {}", char); + debug_assert!("$.*".contains(char), "Unsupported char in function name {}: {}", name, char); true } else { diff --git a/test.sh b/test.sh index 7c68e00771d6..72753e1d4666 100755 --- a/test.sh +++ b/test.sh @@ -350,6 +350,8 @@ function test_rustc() { for test in $(rg -i --files-with-matches "//(\[\w+\])?~|// error-pattern:|// build-fail|// run-fail|-Cllvm-args" tests/ui); do rm $test done + rm tests/ui/consts/const_cmp_type_id.rs + rm tests/ui/consts/issue-73976-monomorphic.rs git checkout -- tests/ui/issues/auxiliary/issue-3136-a.rs # contains //~ERROR, but shouldn't be removed From 8bba64673c4fa7b19524efa563ae6233e0bda217 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 11 Jun 2023 20:01:24 -0400 Subject: [PATCH 335/356] Cleanup --- build_sysroot/build_sysroot.sh | 8 ++++++++ src/lib.rs | 2 -- test.sh | 8 -------- 3 files changed, 8 insertions(+), 10 deletions(-) diff --git a/build_sysroot/build_sysroot.sh b/build_sysroot/build_sysroot.sh index 9d692d599f6b..dc80e4fff806 100755 --- a/build_sysroot/build_sysroot.sh +++ b/build_sysroot/build_sysroot.sh @@ -28,3 +28,11 @@ fi # Copy files to sysroot mkdir -p sysroot/lib/rustlib/$TARGET_TRIPLE/lib/ cp -r target/$TARGET_TRIPLE/$sysroot_channel/deps/* sysroot/lib/rustlib/$TARGET_TRIPLE/lib/ + +# Since we can't override the sysroot for the UI tests anymore, we create a new toolchain and manually overwrite the sysroot directory. +my_toolchain_dir=$HOME/.rustup/toolchains/my_toolchain +rm -rf $my_toolchain_dir +rust_toolchain=$(cat ../rust-toolchain | grep channel | sed 's/channel = "\(.*\)"/\1/') +cp -r $HOME/.rustup/toolchains/$rust_toolchain-$TARGET_TRIPLE $my_toolchain_dir +rm -rf $my_toolchain_dir/lib/rustlib/$TARGET_TRIPLE/ +cp -r ../build_sysroot/sysroot/* $my_toolchain_dir diff --git a/src/lib.rs b/src/lib.rs index 7a89a449b692..2a6b642782df 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -1,5 +1,3 @@ -// FIXME: simple programs now segfault with a sysroot compile in release mode. - /* * TODO(antoyo): implement equality in libgccjit based on https://zpz.github.io/blog/overloading-equality-operator-in-cpp-class-hierarchy/ (for type equality?) * TODO(antoyo): support #[inline] attributes. diff --git a/test.sh b/test.sh index 72753e1d4666..a6e87fca1623 100755 --- a/test.sh +++ b/test.sh @@ -213,13 +213,7 @@ function setup_rustc() { rm config.toml || true - # TODO: move these lines to build_sysroot/build_sysroot.sh instead to avoid having to rebuild stage0 libraries everytime? - # Since we can't override the sysroot anymore, we create a new toolchain and manually overwrite the sysroot directory. my_toolchain_dir=$HOME/.rustup/toolchains/my_toolchain - rm -rf $my_toolchain_dir - cp -r $HOME/.rustup/toolchains/$rust_toolchain-$TARGET_TRIPLE $my_toolchain_dir - rm -rf $my_toolchain_dir/lib/rustlib/x86_64-unknown-linux-gnu/ - cp -r ../build_sysroot/sysroot/* $my_toolchain_dir cat > config.toml < Date: Mon, 12 Jun 2023 20:51:29 -0400 Subject: [PATCH 336/356] Tests for the CI --- build_sysroot/build_sysroot.sh | 2 +- test.sh | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/build_sysroot/build_sysroot.sh b/build_sysroot/build_sysroot.sh index dc80e4fff806..063219aabd27 100755 --- a/build_sysroot/build_sysroot.sh +++ b/build_sysroot/build_sysroot.sh @@ -30,7 +30,7 @@ mkdir -p sysroot/lib/rustlib/$TARGET_TRIPLE/lib/ cp -r target/$TARGET_TRIPLE/$sysroot_channel/deps/* sysroot/lib/rustlib/$TARGET_TRIPLE/lib/ # Since we can't override the sysroot for the UI tests anymore, we create a new toolchain and manually overwrite the sysroot directory. -my_toolchain_dir=$HOME/.rustup/toolchains/my_toolchain +my_toolchain_dir=$HOME/.rustup/toolchains/codegen_gcc_ui_tests rm -rf $my_toolchain_dir rust_toolchain=$(cat ../rust-toolchain | grep channel | sed 's/channel = "\(.*\)"/\1/') cp -r $HOME/.rustup/toolchains/$rust_toolchain-$TARGET_TRIPLE $my_toolchain_dir diff --git a/test.sh b/test.sh index a6e87fca1623..6213ed49183c 100755 --- a/test.sh +++ b/test.sh @@ -213,7 +213,7 @@ function setup_rustc() { rm config.toml || true - my_toolchain_dir=$HOME/.rustup/toolchains/my_toolchain + my_toolchain_dir=$HOME/.rustup/toolchains/codegen_gcc_ui_tests cat > config.toml < Date: Thu, 15 Jun 2023 20:45:20 -0400 Subject: [PATCH 337/356] Working, but requires a patched rustc --- build_sysroot/build_sysroot.sh | 4 ++-- test.sh | 15 +++++++++------ 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/build_sysroot/build_sysroot.sh b/build_sysroot/build_sysroot.sh index 063219aabd27..6aea9b94b48e 100755 --- a/build_sysroot/build_sysroot.sh +++ b/build_sysroot/build_sysroot.sh @@ -30,9 +30,9 @@ mkdir -p sysroot/lib/rustlib/$TARGET_TRIPLE/lib/ cp -r target/$TARGET_TRIPLE/$sysroot_channel/deps/* sysroot/lib/rustlib/$TARGET_TRIPLE/lib/ # Since we can't override the sysroot for the UI tests anymore, we create a new toolchain and manually overwrite the sysroot directory. -my_toolchain_dir=$HOME/.rustup/toolchains/codegen_gcc_ui_tests -rm -rf $my_toolchain_dir rust_toolchain=$(cat ../rust-toolchain | grep channel | sed 's/channel = "\(.*\)"/\1/') +my_toolchain_dir=$HOME/.rustup/toolchains/codegen_gcc_ui_tests-$rust_toolchain-$TARGET_TRIPLE +rm -rf $my_toolchain_dir cp -r $HOME/.rustup/toolchains/$rust_toolchain-$TARGET_TRIPLE $my_toolchain_dir rm -rf $my_toolchain_dir/lib/rustlib/$TARGET_TRIPLE/ cp -r ../build_sysroot/sysroot/* $my_toolchain_dir diff --git a/test.sh b/test.sh index 6213ed49183c..2e485b927393 100755 --- a/test.sh +++ b/test.sh @@ -209,11 +209,12 @@ function setup_rustc() { cd rust git fetch git checkout $(rustc -V | cut -d' ' -f3 | tr -d '(') + git am ../0001-Allow-overwriting-the-sysroot-compile-flag-via-rustc.patch export RUSTFLAGS= rm config.toml || true - my_toolchain_dir=$HOME/.rustup/toolchains/codegen_gcc_ui_tests + my_toolchain_dir=$HOME/.rustup/toolchains/codegen_gcc_ui_tests-$rust_toolchain-$TARGET_TRIPLE cat > config.toml < Date: Thu, 15 Jun 2023 20:51:29 -0400 Subject: [PATCH 338/356] Handle alignment of the load instruction --- src/builder.rs | 19 ++++++++++++++----- src/intrinsic/simd.rs | 9 ++++++--- 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index f2775421ccd0..bb23524d8af4 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -729,17 +729,25 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { unimplemented!(); } - fn load(&mut self, pointee_ty: Type<'gcc>, ptr: RValue<'gcc>, _align: Align) -> RValue<'gcc> { + fn load(&mut self, pointee_ty: Type<'gcc>, ptr: RValue<'gcc>, align: Align) -> RValue<'gcc> { let block = self.llbb(); let function = block.get_function(); // NOTE: instead of returning the dereference here, we have to assign it to a variable in // the current basic block. Otherwise, it could be used in another basic block, causing a // dereference after a drop, for instance. - // TODO(antoyo): handle align of the load instruction. - let ptr = self.context.new_cast(None, ptr, pointee_ty.make_pointer()); + // FIXME(antoyo): this check that we don't call get_aligned() a second time on a type. + // Ideally, we shouldn't need to do this check. + let aligned_type = + if pointee_ty == self.cx.u128_type || pointee_ty == self.cx.i128_type { + pointee_ty + } + else { + pointee_ty.get_aligned(align.bytes()) + }; + let ptr = self.context.new_cast(None, ptr, aligned_type.make_pointer()); let deref = ptr.dereference(None).to_rvalue(); unsafe { RETURN_VALUE_COUNT += 1 }; - let loaded_value = function.new_local(None, pointee_ty, &format!("loadedValue{}", unsafe { RETURN_VALUE_COUNT })); + let loaded_value = function.new_local(None, aligned_type, &format!("loadedValue{}", unsafe { RETURN_VALUE_COUNT })); block.add_assignment(None, loaded_value, deref); loaded_value.to_rvalue() } @@ -1857,7 +1865,8 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { #[cfg(feature="master")] let (cond, element_type) = { - let then_val_vector_type = then_val.get_type().dyncast_vector().expect("vector type"); + // TODO(antoyo): dyncast_vector should not require a call to unqualified. + let then_val_vector_type = then_val.get_type().unqualified().dyncast_vector().expect("vector type"); let then_val_element_type = then_val_vector_type.get_element_type(); let then_val_element_size = then_val_element_type.get_size(); diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index 36b9c9b63641..9115cf971196 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -346,7 +346,8 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>( // endian and MSB-first for big endian. let vector = args[0].immediate(); - let vector_type = vector.get_type().dyncast_vector().expect("vector type"); + // TODO(antoyo): dyncast_vector should not require a call to unqualified. + let vector_type = vector.get_type().unqualified().dyncast_vector().expect("vector type"); let elem_type = vector_type.get_element_type(); let expected_int_bits = in_len.max(8); @@ -853,7 +854,8 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>( (true, true) => { // Algorithm from: https://codereview.stackexchange.com/questions/115869/saturated-signed-addition // TODO(antoyo): improve using conditional operators if possible. - let arg_type = lhs.get_type(); + // TODO(antoyo): dyncast_vector should not require a call to unqualified. + let arg_type = lhs.get_type().unqualified(); // TODO(antoyo): convert lhs and rhs to unsigned. let sum = lhs + rhs; let vector_type = arg_type.dyncast_vector().expect("vector type"); @@ -883,7 +885,8 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>( res & cmp }, (true, false) => { - let arg_type = lhs.get_type(); + // TODO(antoyo): dyncast_vector should not require a call to unqualified. + let arg_type = lhs.get_type().unqualified(); // TODO(antoyo): this uses the same algorithm from saturating add, but add the // negative of the right operand. Find a proper subtraction algorithm. let rhs = bx.context.new_unary_op(None, UnaryOp::Minus, arg_type, rhs); From 8560b07ebfe177049a3790f4452196250b1cfb06 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Thu, 15 Jun 2023 20:52:45 -0400 Subject: [PATCH 339/356] TO REVERT: temporarily add a patch for rustc --- ...g-the-sysroot-compile-flag-via-rustc.patch | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 0001-Allow-overwriting-the-sysroot-compile-flag-via-rustc.patch diff --git a/0001-Allow-overwriting-the-sysroot-compile-flag-via-rustc.patch b/0001-Allow-overwriting-the-sysroot-compile-flag-via-rustc.patch new file mode 100644 index 000000000000..f7860bd9105b --- /dev/null +++ b/0001-Allow-overwriting-the-sysroot-compile-flag-via-rustc.patch @@ -0,0 +1,27 @@ +From 8d5e85607d3d52f920990334ae1cfa9798ad9259 Mon Sep 17 00:00:00 2001 +From: Antoni Boucher +Date: Thu, 8 Jun 2023 17:27:34 -0400 +Subject: [PATCH] Allow overwriting the sysroot compile flag via --rustc-args + +--- + src/tools/compiletest/src/runtest.rs | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/src/tools/compiletest/src/runtest.rs b/src/tools/compiletest/src/runtest.rs +index 6582b534488..d16a7d66154 100644 +--- a/src/tools/compiletest/src/runtest.rs ++++ b/src/tools/compiletest/src/runtest.rs +@@ -1951,7 +1951,9 @@ fn make_compile_args( + rustc.arg("-Ztranslate-remapped-path-to-local-path=no"); + + // Optionally prevent default --sysroot if specified in test compile-flags. +- if !self.props.compile_flags.iter().any(|flag| flag.starts_with("--sysroot")) { ++ if !self.props.compile_flags.iter().any(|flag| flag.starts_with("--sysroot")) ++ && !self.config.host_rustcflags.iter().any(|flag| flag == "--sysroot") ++ { + // In stage 0, make sure we use `stage0-sysroot` instead of the bootstrap sysroot. + rustc.arg("--sysroot").arg(&self.config.sysroot_base); + } +-- +2.41.0 + From 3d7ec5923d2e4373a354e7aec879e09e48f21517 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sat, 17 Jun 2023 13:19:41 -0400 Subject: [PATCH 340/356] Fix for check_ptr_call for variadic functions --- build_sysroot/build_sysroot.sh | 13 +++++++------ src/builder.rs | 9 ++++++++- 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/build_sysroot/build_sysroot.sh b/build_sysroot/build_sysroot.sh index 6aea9b94b48e..7f2c8d6121d6 100755 --- a/build_sysroot/build_sysroot.sh +++ b/build_sysroot/build_sysroot.sh @@ -30,9 +30,10 @@ mkdir -p sysroot/lib/rustlib/$TARGET_TRIPLE/lib/ cp -r target/$TARGET_TRIPLE/$sysroot_channel/deps/* sysroot/lib/rustlib/$TARGET_TRIPLE/lib/ # Since we can't override the sysroot for the UI tests anymore, we create a new toolchain and manually overwrite the sysroot directory. -rust_toolchain=$(cat ../rust-toolchain | grep channel | sed 's/channel = "\(.*\)"/\1/') -my_toolchain_dir=$HOME/.rustup/toolchains/codegen_gcc_ui_tests-$rust_toolchain-$TARGET_TRIPLE -rm -rf $my_toolchain_dir -cp -r $HOME/.rustup/toolchains/$rust_toolchain-$TARGET_TRIPLE $my_toolchain_dir -rm -rf $my_toolchain_dir/lib/rustlib/$TARGET_TRIPLE/ -cp -r ../build_sysroot/sysroot/* $my_toolchain_dir +# TODO: to remove. +#rust_toolchain=$(cat ../rust-toolchain | grep channel | sed 's/channel = "\(.*\)"/\1/') +#my_toolchain_dir=$HOME/.rustup/toolchains/codegen_gcc_ui_tests-$rust_toolchain-$TARGET_TRIPLE +#rm -rf $my_toolchain_dir +#cp -r $HOME/.rustup/toolchains/$rust_toolchain-$TARGET_TRIPLE $my_toolchain_dir +#rm -rf $my_toolchain_dir/lib/rustlib/$TARGET_TRIPLE/ +#cp -r ../build_sysroot/sysroot/* $my_toolchain_dir diff --git a/src/builder.rs b/src/builder.rs index bb23524d8af4..43d0aafbd50b 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -181,6 +181,8 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { }) .collect(); + debug_assert_eq!(casted_args.len(), args.len()); + Cow::Owned(casted_args) } @@ -207,7 +209,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let func_name = format!("{:?}", func_ptr); - let casted_args: Vec<_> = param_types + let mut casted_args: Vec<_> = param_types .into_iter() .zip(args.iter()) .enumerate() @@ -237,6 +239,11 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { }) .collect(); + // NOTE: to take into account variadic functions. + for i in casted_args.len()..args.len() { + casted_args.push(args[i]); + } + Cow::Owned(casted_args) } From 607cbfda14ab8a4292d34afdffdf817f81fe95ab Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Sun, 18 Jun 2023 19:40:12 -0400 Subject: [PATCH 341/356] Cleanup and update to rustc 2023-06-19 --- ...g-the-sysroot-compile-flag-via-rustc.patch | 27 ---------- build_sysroot/build_sysroot.sh | 9 ---- example/mini_core.rs | 10 ++-- patches/0023-core-Ignore-failing-tests.patch | 49 ------------------- rust-toolchain | 2 +- src/common.rs | 4 ++ test.sh | 7 --- 7 files changed, 9 insertions(+), 99 deletions(-) delete mode 100644 0001-Allow-overwriting-the-sysroot-compile-flag-via-rustc.patch delete mode 100644 patches/0023-core-Ignore-failing-tests.patch diff --git a/0001-Allow-overwriting-the-sysroot-compile-flag-via-rustc.patch b/0001-Allow-overwriting-the-sysroot-compile-flag-via-rustc.patch deleted file mode 100644 index f7860bd9105b..000000000000 --- a/0001-Allow-overwriting-the-sysroot-compile-flag-via-rustc.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 8d5e85607d3d52f920990334ae1cfa9798ad9259 Mon Sep 17 00:00:00 2001 -From: Antoni Boucher -Date: Thu, 8 Jun 2023 17:27:34 -0400 -Subject: [PATCH] Allow overwriting the sysroot compile flag via --rustc-args - ---- - src/tools/compiletest/src/runtest.rs | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/src/tools/compiletest/src/runtest.rs b/src/tools/compiletest/src/runtest.rs -index 6582b534488..d16a7d66154 100644 ---- a/src/tools/compiletest/src/runtest.rs -+++ b/src/tools/compiletest/src/runtest.rs -@@ -1951,7 +1951,9 @@ fn make_compile_args( - rustc.arg("-Ztranslate-remapped-path-to-local-path=no"); - - // Optionally prevent default --sysroot if specified in test compile-flags. -- if !self.props.compile_flags.iter().any(|flag| flag.starts_with("--sysroot")) { -+ if !self.props.compile_flags.iter().any(|flag| flag.starts_with("--sysroot")) -+ && !self.config.host_rustcflags.iter().any(|flag| flag == "--sysroot") -+ { - // In stage 0, make sure we use `stage0-sysroot` instead of the bootstrap sysroot. - rustc.arg("--sysroot").arg(&self.config.sysroot_base); - } --- -2.41.0 - diff --git a/build_sysroot/build_sysroot.sh b/build_sysroot/build_sysroot.sh index 7f2c8d6121d6..9d692d599f6b 100755 --- a/build_sysroot/build_sysroot.sh +++ b/build_sysroot/build_sysroot.sh @@ -28,12 +28,3 @@ fi # Copy files to sysroot mkdir -p sysroot/lib/rustlib/$TARGET_TRIPLE/lib/ cp -r target/$TARGET_TRIPLE/$sysroot_channel/deps/* sysroot/lib/rustlib/$TARGET_TRIPLE/lib/ - -# Since we can't override the sysroot for the UI tests anymore, we create a new toolchain and manually overwrite the sysroot directory. -# TODO: to remove. -#rust_toolchain=$(cat ../rust-toolchain | grep channel | sed 's/channel = "\(.*\)"/\1/') -#my_toolchain_dir=$HOME/.rustup/toolchains/codegen_gcc_ui_tests-$rust_toolchain-$TARGET_TRIPLE -#rm -rf $my_toolchain_dir -#cp -r $HOME/.rustup/toolchains/$rust_toolchain-$TARGET_TRIPLE $my_toolchain_dir -#rm -rf $my_toolchain_dir/lib/rustlib/$TARGET_TRIPLE/ -#cp -r ../build_sysroot/sysroot/* $my_toolchain_dir diff --git a/example/mini_core.rs b/example/mini_core.rs index 835419efc3a0..0cd7e6047c20 100644 --- a/example/mini_core.rs +++ b/example/mini_core.rs @@ -504,7 +504,10 @@ impl Box { impl Drop for Box { fn drop(&mut self) { - // drop is currently performed by compiler. + // inner value is dropped by compiler. + unsafe { + libc::free(self.0.pointer.0 as *mut u8); + } } } @@ -521,11 +524,6 @@ unsafe fn allocate(size: usize, _align: usize) -> *mut u8 { libc::malloc(size) } -#[lang = "box_free"] -unsafe fn box_free(ptr: Unique, _alloc: ()) { - libc::free(ptr.pointer.0 as *mut u8); -} - #[lang = "drop"] pub trait Drop { fn drop(&mut self); diff --git a/patches/0023-core-Ignore-failing-tests.patch b/patches/0023-core-Ignore-failing-tests.patch deleted file mode 100644 index ee5ba449fb8e..000000000000 --- a/patches/0023-core-Ignore-failing-tests.patch +++ /dev/null @@ -1,49 +0,0 @@ -From dd82e95c9de212524e14fc60155de1ae40156dfc Mon Sep 17 00:00:00 2001 -From: bjorn3 -Date: Sun, 24 Nov 2019 15:34:06 +0100 -Subject: [PATCH] [core] Ignore failing tests - ---- - library/core/tests/iter.rs | 4 ++++ - library/core/tests/num/bignum.rs | 10 ++++++++++ - library/core/tests/num/mod.rs | 5 +++-- - library/core/tests/time.rs | 1 + - 4 files changed, 18 insertions(+), 2 deletions(-) - -diff --git a/library/core/tests/array.rs b/library/core/tests/array.rs -index 4bc44e9..8e3c7a4 100644 ---- a/library/core/tests/array.rs -+++ b/library/core/tests/array.rs -@@ -242,6 +242,7 @@ fn iterator_drops() { - assert_eq!(i.get(), 5); - } - -+/* - // This test does not work on targets without panic=unwind support. - // To work around this problem, test is marked is should_panic, so it will - // be automagically skipped on unsuitable targets, such as -@@ -283,6 +284,7 @@ fn array_default_impl_avoids_leaks_on_panic() { - assert_eq!(COUNTER.load(Relaxed), 0); - panic!("test succeeded") - } -+*/ - - #[test] - fn empty_array_is_always_default() { -@@ -304,6 +304,7 @@ fn array_map() { - assert_eq!(b, [1, 2, 3]); - } - -+/* - // See note on above test for why `should_panic` is used. - #[test] - #[should_panic(expected = "test succeeded")] -@@ -332,6 +333,7 @@ fn array_map_drop_safety() { - assert_eq!(DROPPED.load(Ordering::SeqCst), num_to_create); - panic!("test succeeded") - } -+*/ - - #[test] - fn cell_allows_array_cycle() { --- 2.21.0 (Apple Git-122) diff --git a/rust-toolchain b/rust-toolchain index 2614fa081a86..ebb04d0069cf 100644 --- a/rust-toolchain +++ b/rust-toolchain @@ -1,3 +1,3 @@ [toolchain] -channel = "nightly-2023-06-10" +channel = "nightly-2023-06-19" components = ["rust-src", "rustc-dev", "llvm-tools-preview"] diff --git a/src/common.rs b/src/common.rs index 7fa986e2737e..b62f4676f70b 100644 --- a/src/common.rs +++ b/src/common.rs @@ -108,6 +108,10 @@ impl<'gcc, 'tcx> ConstMethods<'tcx> for CodegenCx<'gcc, 'tcx> { self.const_uint(self.type_u64(), i) } + fn const_u128(&self, i: u128) -> RValue<'gcc> { + self.const_uint_big(self.type_u128(), i) + } + fn const_usize(&self, i: u64) -> RValue<'gcc> { let bit_size = self.data_layout().pointer_size.bits(); if bit_size < 64 { diff --git a/test.sh b/test.sh index 2e485b927393..d12fe718a968 100755 --- a/test.sh +++ b/test.sh @@ -209,13 +209,10 @@ function setup_rustc() { cd rust git fetch git checkout $(rustc -V | cut -d' ' -f3 | tr -d '(') - git am ../0001-Allow-overwriting-the-sysroot-compile-flag-via-rustc.patch export RUSTFLAGS= rm config.toml || true - my_toolchain_dir=$HOME/.rustup/toolchains/codegen_gcc_ui_tests-$rust_toolchain-$TARGET_TRIPLE - cat > config.toml < Date: Sun, 18 Jun 2023 19:42:20 -0400 Subject: [PATCH 342/356] Fix indent --- src/asm.rs | 69 +++++++++++++++++++++++++++--------------------------- test.sh | 3 +-- 2 files changed, 35 insertions(+), 37 deletions(-) diff --git a/src/asm.rs b/src/asm.rs index be7ae603ca61..4c3b7f5036cc 100644 --- a/src/asm.rs +++ b/src/asm.rs @@ -502,49 +502,48 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { let builtin_unreachable = self.context.get_builtin_function("__builtin_unreachable"); let builtin_unreachable: RValue<'gcc> = unsafe { std::mem::transmute(builtin_unreachable) }; self.call(self.type_void(), None, None, builtin_unreachable, &[], None); - } + } - // Write results to outputs. - // - // We need to do this because: - // 1. Turning `PlaceRef` into `RValue` is error-prone and has nasty edge cases - // (especially with current `rustc_backend_ssa` API). - // 2. Not every output operand has an `out_place`, and it's required by `add_output_operand`. - // - // Instead, we generate a temporary output variable for each output operand, and then this loop, - // generates `out_place = tmp_var;` assignments if out_place exists. - for op in &outputs { - if let Some(place) = op.out_place { - OperandValue::Immediate(op.tmp_var.to_rvalue()).store(self, place); + // Write results to outputs. + // + // We need to do this because: + // 1. Turning `PlaceRef` into `RValue` is error-prone and has nasty edge cases + // (especially with current `rustc_backend_ssa` API). + // 2. Not every output operand has an `out_place`, and it's required by `add_output_operand`. + // + // Instead, we generate a temporary output variable for each output operand, and then this loop, + // generates `out_place = tmp_var;` assignments if out_place exists. + for op in &outputs { + if let Some(place) = op.out_place { + OperandValue::Immediate(op.tmp_var.to_rvalue()).store(self, place); + } } } - -} } fn estimate_template_length(template: &[InlineAsmTemplatePiece], constants_len: usize, att_dialect: bool) -> usize { -let len: usize = template.iter().map(|piece| { - match *piece { - InlineAsmTemplatePiece::String(ref string) => { - string.len() - } - InlineAsmTemplatePiece::Placeholder { .. } => { - // '%' + 1 char modifier + 1 char index - 3 + let len: usize = template.iter().map(|piece| { + match *piece { + InlineAsmTemplatePiece::String(ref string) => { + string.len() + } + InlineAsmTemplatePiece::Placeholder { .. } => { + // '%' + 1 char modifier + 1 char index + 3 + } } + }) + .sum(); + + // increase it by 5% to account for possible '%' signs that'll be duplicated + // I pulled the number out of blue, but should be fair enough + // as the upper bound + let mut res = (len as f32 * 1.05) as usize + constants_len; + + if att_dialect { + res += INTEL_SYNTAX_INS.len() + ATT_SYNTAX_INS.len(); } -}) -.sum(); - -// increase it by 5% to account for possible '%' signs that'll be duplicated -// I pulled the number out of blue, but should be fair enough -// as the upper bound -let mut res = (len as f32 * 1.05) as usize + constants_len; - -if att_dialect { - res += INTEL_SYNTAX_INS.len() + ATT_SYNTAX_INS.len(); -} -res + res } /// Converts a register class to a GCC constraint code. diff --git a/test.sh b/test.sh index d12fe718a968..592997b8ab9d 100755 --- a/test.sh +++ b/test.sh @@ -357,7 +357,6 @@ function test_rustc() { RUSTC_ARGS="$TEST_FLAGS -Csymbol-mangling-version=v0 -Zcodegen-backend="$(pwd)"/../target/"$CHANNEL"/librustc_codegen_gcc."$dylib_ext" --sysroot "$(pwd)"/../build_sysroot/sysroot" - if [ $# -eq 0 ]; then # No argument supplied to the function. Doing nothing. echo "No argument provided. Keeping all UI tests" @@ -388,7 +387,7 @@ function test_rustc() { fi echo "[TEST] rustc test suite" - COMPILETEST_FORCE_STAGE0=1 ./x.py test --run always --stage 0 tests/ui --rustc-args "$RUSTC_ARGS" + COMPILETEST_FORCE_STAGE0=1 ./x.py test --run always --stage 0 tests/ui/ --rustc-args "$RUSTC_ARGS" } function test_failing_rustc() { From afc6489394abd238fcfbe2c39ca35c4ce3e84234 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Fri, 30 Jun 2023 17:11:09 +0200 Subject: [PATCH 343/356] Add support for cold attribute --- src/attributes.rs | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/attributes.rs b/src/attributes.rs index eb0cce19b85c..fbafc981f664 100644 --- a/src/attributes.rs +++ b/src/attributes.rs @@ -114,6 +114,10 @@ pub fn from_fn_attrs<'gcc, 'tcx>( if let Some(attr) = inline_attr(cx, inline) { func.add_attribute(attr); } + + if codegen_fn_attrs.flags.contains(CodegenFnAttrFlags::COLD) { + func.add_attribute(FnAttribute::Cold); + } } let function_features = From 5920bad104dd842a8b036a7f32c0ae5cf7737496 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Mon, 3 Jul 2023 16:56:34 +0200 Subject: [PATCH 344/356] Update dependencies --- Cargo.lock | 272 +++++++++++++++++++++++++++++++++-------------------- 1 file changed, 172 insertions(+), 100 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 3c5357eec105..92cb25b7d0be 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -4,25 +4,67 @@ version = 3 [[package]] name = "aho-corasick" -version = "0.7.18" +version = "1.0.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1e37cfd5e7657ada45f742d6e99ca5788580b5c529dc78faf11ece6dc702656f" +checksum = "43f6cb1bf222025340178f382c426f13757b2960e89779dfcb319c32542a5a41" dependencies = [ "memchr", ] +[[package]] +name = "autocfg" +version = "1.1.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d468802bab17cbc0cc575e9b053f41e72aa36bfa6b7f55e3529ffa43161b97fa" + [[package]] name = "bitflags" version = "1.3.2" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a" +[[package]] +name = "cc" +version = "1.0.79" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "50d30906286121d95be3d479533b458f87493b30a4b5f79a607db8f5d11aa91f" + [[package]] name = "cfg-if" version = "1.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd" +[[package]] +name = "errno" +version = "0.3.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "4bcfec3a70f97c962c307b2d2c56e358cf1d00b558d74262b5f929ee8cc7e73a" +dependencies = [ + "errno-dragonfly", + "libc", + "windows-sys", +] + +[[package]] +name = "errno-dragonfly" +version = "0.1.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "aa68f1b12764fab894d2755d2518754e71b4fd80ecfb822714a1206c2aab39bf" +dependencies = [ + "cc", + "libc", +] + +[[package]] +name = "fastrand" +version = "1.9.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e51093e27b0797c359783294ca4f0a911c270184cb10f85783b118614a1501be" +dependencies = [ + "instant", +] + [[package]] name = "fm" version = "0.1.4" @@ -35,7 +77,7 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" -source = "git+https://github.com/antoyo/gccjit.rs#d6e52626cfc6f487094a5d5ac66302baf3439984" +source = "git+https://github.com/antoyo/gccjit.rs#2f6b60543d0f72003a2d19430d446dae27b06753" dependencies = [ "gccjit_sys", ] @@ -43,7 +85,7 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" -source = "git+https://github.com/antoyo/gccjit.rs#d6e52626cfc6f487094a5d5ac66302baf3439984" +source = "git+https://github.com/antoyo/gccjit.rs#2f6b60543d0f72003a2d19430d446dae27b06753" dependencies = [ "libc", ] @@ -58,23 +100,29 @@ dependencies = [ ] [[package]] -name = "getrandom" -version = "0.2.3" +name = "hermit-abi" +version = "0.3.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7fcd999463524c52659517fe2cea98493cfe485d10565e7b0fb07dbba7ad2753" +checksum = "fed44880c466736ef9a5c5b5facefb5ed0785676d0c02d612db14e54f0d84286" + +[[package]] +name = "instant" +version = "0.1.12" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7a5bbe824c507c5da5956355e86a746d82e0e1464f65d862cc5e71da70e94b2c" dependencies = [ "cfg-if", - "libc", - "wasi", ] [[package]] -name = "hermit-abi" -version = "0.1.19" +name = "io-lifetimes" +version = "1.0.11" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "62b467343b94ba476dcb2500d242dadbb39557df889310ac77c5d99100aaac33" +checksum = "eae7b9aee968036d54dce06cebaefd919e4472e753296daccd6d344e3e2df0c2" dependencies = [ + "hermit-abi", "libc", + "windows-sys", ] [[package]] @@ -95,86 +143,46 @@ dependencies = [ [[package]] name = "libc" -version = "0.2.112" +version = "0.2.147" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1b03d17f364a3a042d5e5d46b053bbbf82c92c9430c592dd4c064dc6ee997125" +checksum = "b4668fb0ea861c1df094127ac5f1da3409a82116a4ba74fca2e58ef927159bb3" + +[[package]] +name = "linux-raw-sys" +version = "0.3.8" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ef53942eb7bf7ff43a617b3e2c1c4a5ecf5944a7c1bc12d7ee39bbb15e5c1519" [[package]] name = "memchr" -version = "2.4.1" +version = "2.5.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "308cc39be01b73d0d18f82a0e7b2a3df85245f84af96fdddc5d202d27e47b86a" +checksum = "2dffe52ecf27772e601905b7522cb4ef790d2cc203488bbd0e2fe85fcb74566d" [[package]] name = "num_cpus" -version = "1.13.0" +version = "1.16.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "05499f3756671c15885fee9034446956fff3f243d6077b91e5767df161f766b3" +checksum = "4161fcb6d602d4d2081af7c3a45852d875a03dd337a6bfdd6e06407b61342a43" dependencies = [ "hermit-abi", "libc", ] -[[package]] -name = "ppv-lite86" -version = "0.2.15" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ed0cfbc8191465bed66e1718596ee0b0b35d5ee1f41c5df2189d0fe8bde535ba" - -[[package]] -name = "rand" -version = "0.8.4" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2e7573632e6454cf6b99d7aac4ccca54be06da05aca2ef7423d22d27d4d4bcd8" -dependencies = [ - "libc", - "rand_chacha", - "rand_core", - "rand_hc", -] - -[[package]] -name = "rand_chacha" -version = "0.3.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e6c10a63a0fa32252be49d21e7709d4d4baf8d231c2dbce1eaa8141b9b127d88" -dependencies = [ - "ppv-lite86", - "rand_core", -] - -[[package]] -name = "rand_core" -version = "0.6.3" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d34f1408f55294453790c48b2f1ebbb1c5b4b7563eb1f418bcfcfdbb06ebb4e7" -dependencies = [ - "getrandom", -] - -[[package]] -name = "rand_hc" -version = "0.3.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d51e9f596de227fda2ea6c84607f5558e196eeaf43c986b724ba4fb8fdf497e7" -dependencies = [ - "rand_core", -] - [[package]] name = "redox_syscall" -version = "0.2.10" +version = "0.3.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "8383f39639269cde97d255a32bdb68c047337295414940c68bdd30c2e13203ff" +checksum = "567664f262709473930a4bf9e51bf2ebf3348f2e748ccc50dea20646858f8f29" dependencies = [ "bitflags", ] [[package]] name = "regex" -version = "1.5.4" +version = "1.8.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d07a8629359eb56f1e2fb1652bb04212c072a87ba68546a04065d525673ac461" +checksum = "d0ab3ca65655bb1e41f2a8c8cd662eb4fb035e67c3f78da1d61dffe89d07300f" dependencies = [ "aho-corasick", "memchr", @@ -183,18 +191,9 @@ dependencies = [ [[package]] name = "regex-syntax" -version = "0.6.25" +version = "0.7.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f497285884f3fcff424ffc933e56d7cbca511def0c9831a7f9b5f6153e3cc89b" - -[[package]] -name = "remove_dir_all" -version = "0.5.3" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3acd125665422973a33ac9d3dd2df85edad0f4ae9b00dafb1a05e43a9f5ef8e7" -dependencies = [ - "winapi", -] +checksum = "436b050e76ed2903236f032a59761c1eb99e1b0aead2c257922771dab1fc8c78" [[package]] name = "rustc_codegen_gcc" @@ -206,6 +205,20 @@ dependencies = [ "tempfile", ] +[[package]] +name = "rustix" +version = "0.37.22" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8818fa822adcc98b18fedbb3632a6a33213c070556b5aa7c4c8cc21cff565c4c" +dependencies = [ + "bitflags", + "errno", + "io-lifetimes", + "libc", + "linux-raw-sys", + "windows-sys", +] + [[package]] name = "same-file" version = "1.0.6" @@ -217,29 +230,29 @@ dependencies = [ [[package]] name = "smallvec" -version = "1.8.0" +version = "1.10.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f2dd574626839106c320a323308629dcb1acfc96e32a8cba364ddc61ac23ee83" +checksum = "a507befe795404456341dfab10cef66ead4c041f62b8b11bbb92bffe5d0953e0" [[package]] name = "tempfile" -version = "3.2.0" +version = "3.6.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "dac1c663cfc93810f88aed9b8941d48cabf856a1b111c29a40439018d870eb22" +checksum = "31c0432476357e58790aaa47a8efb0c5138f137343f3b5f23bd36a27e3b0a6d6" dependencies = [ + "autocfg", "cfg-if", - "libc", - "rand", + "fastrand", "redox_syscall", - "remove_dir_all", - "winapi", + "rustix", + "windows-sys", ] [[package]] name = "termcolor" -version = "1.1.2" +version = "1.2.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2dfed899f0eb03f32ee8c6a0aabdb8a7949659e3466561fc0adf54e26d88c5f4" +checksum = "be55cf8942feac5c765c2c993422806843c9a9a45d4d5c407ad6dd2ea95eb9b6" dependencies = [ "winapi-util", ] @@ -255,9 +268,9 @@ dependencies = [ [[package]] name = "unicode-width" -version = "0.1.9" +version = "0.1.10" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3ed742d4ea2bd1176e236172c8429aaf54486e7ac098db29ffe6529e0ce50973" +checksum = "c0edd1e5b14653f783770bce4a4dabb4a5108a5370a5f5d8cfe8710c361f6c8b" [[package]] name = "wait-timeout" @@ -270,21 +283,14 @@ dependencies = [ [[package]] name = "walkdir" -version = "2.3.2" +version = "2.3.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "808cf2735cd4b6866113f648b791c6adc5714537bc222d9347bb203386ffda56" +checksum = "36df944cda56c7d8d8b7496af378e6b16de9284591917d307c9b4d313c44e698" dependencies = [ "same-file", - "winapi", "winapi-util", ] -[[package]] -name = "wasi" -version = "0.10.2+wasi-snapshot-preview1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "fd6fbd9a79829dd1ad0cc20627bf1ed606756a7f77edff7b66b7064f9cb327c6" - [[package]] name = "winapi" version = "0.3.9" @@ -315,3 +321,69 @@ name = "winapi-x86_64-pc-windows-gnu" version = "0.4.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "712e227841d057c1ee1cd2fb22fa7e5a5461ae8e48fa2ca79ec42cfc1931183f" + +[[package]] +name = "windows-sys" +version = "0.48.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "677d2418bec65e3338edb076e806bc1ec15693c5d0104683f2efe857f61056a9" +dependencies = [ + "windows-targets", +] + +[[package]] +name = "windows-targets" +version = "0.48.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "05d4b17490f70499f20b9e791dcf6a299785ce8af4d709018206dc5b4953e95f" +dependencies = [ + "windows_aarch64_gnullvm", + "windows_aarch64_msvc", + "windows_i686_gnu", + "windows_i686_msvc", + "windows_x86_64_gnu", + "windows_x86_64_gnullvm", + "windows_x86_64_msvc", +] + +[[package]] +name = "windows_aarch64_gnullvm" +version = "0.48.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "91ae572e1b79dba883e0d315474df7305d12f569b400fcf90581b06062f7e1bc" + +[[package]] +name = "windows_aarch64_msvc" +version = "0.48.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b2ef27e0d7bdfcfc7b868b317c1d32c641a6fe4629c171b8928c7b08d98d7cf3" + +[[package]] +name = "windows_i686_gnu" +version = "0.48.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "622a1962a7db830d6fd0a69683c80a18fda201879f0f447f065a3b7467daa241" + +[[package]] +name = "windows_i686_msvc" +version = "0.48.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "4542c6e364ce21bf45d69fdd2a8e455fa38d316158cfd43b3ac1c5b1b19f8e00" + +[[package]] +name = "windows_x86_64_gnu" +version = "0.48.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ca2b8a661f7628cbd23440e50b05d705db3686f894fc9580820623656af974b1" + +[[package]] +name = "windows_x86_64_gnullvm" +version = "0.48.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7896dbc1f41e08872e9d5e8f8baa8fdd2677f29468c4e156210174edc7f7b953" + +[[package]] +name = "windows_x86_64_msvc" +version = "0.48.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1a515f5799fe4961cb532f983ce2b23082366b898e52ffbce459c86f67c8378a" From 91e04000eab437a791d0b7e1fe19c2a2b2234281 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Tue, 4 Jul 2023 21:04:15 -0400 Subject: [PATCH 345/356] Add support for detecting CPU features --- Cargo.lock | 4 ++-- Readme.md | 4 +--- failing-ui-tests.txt | 1 - src/base.rs | 51 ++++++++++++++++++++++++++------------------ src/lib.rs | 42 +++++++++++++++--------------------- 5 files changed, 50 insertions(+), 52 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 92cb25b7d0be..2800dc6ccd14 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -77,7 +77,7 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" -source = "git+https://github.com/antoyo/gccjit.rs#2f6b60543d0f72003a2d19430d446dae27b06753" +source = "git+https://github.com/antoyo/gccjit.rs#79c8bb49ff09b7f40a04055203a5f3894a266210" dependencies = [ "gccjit_sys", ] @@ -85,7 +85,7 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" -source = "git+https://github.com/antoyo/gccjit.rs#2f6b60543d0f72003a2d19430d446dae27b06753" +source = "git+https://github.com/antoyo/gccjit.rs#79c8bb49ff09b7f40a04055203a5f3894a266210" dependencies = [ "libc", ] diff --git a/Readme.md b/Readme.md index a93637d9038d..c58662b9ce5d 100644 --- a/Readme.md +++ b/Readme.md @@ -14,9 +14,7 @@ A secondary goal is to check if using the gcc backend will provide any run-time ## Building **This requires a patched libgccjit in order to work. -The patches in [this repository](https://github.com/antoyo/libgccjit-patches) need to be applied. -(Those patches should work when applied on master, but in case it doesn't work, they are known to work when applied on 079c23cfe079f203d5df83fea8e92a60c7d7e878.) -You can also use my [fork of gcc](https://github.com/antoyo/gcc) which already includes these patches.** +You need to use my [fork of gcc](https://github.com/antoyo/gcc) which already includes these patches.** To build it (most of these instructions come from [here](https://gcc.gnu.org/onlinedocs/jit/internals/index.html), so don't hesitate to take a look there if you encounter an issue): diff --git a/failing-ui-tests.txt b/failing-ui-tests.txt index 801464daae9a..69f57036b01e 100644 --- a/failing-ui-tests.txt +++ b/failing-ui-tests.txt @@ -21,7 +21,6 @@ tests/ui/sepcomp/sepcomp-fns-backwards.rs tests/ui/sepcomp/sepcomp-fns.rs tests/ui/sepcomp/sepcomp-statics.rs tests/ui/simd/intrinsic/generic-arithmetic-pass.rs -tests/ui/sse2.rs tests/ui/target-feature/missing-plusminus.rs tests/ui/asm/x86_64/may_unwind.rs tests/ui/backtrace.rs diff --git a/src/base.rs b/src/base.rs index dcd560b3dcd9..82669aa99cf1 100644 --- a/src/base.rs +++ b/src/base.rs @@ -1,10 +1,12 @@ +use std::collections::HashSet; use std::env; +use std::sync::Arc; use std::time::Instant; use gccjit::{ Context, FunctionType, - GlobalKind, + GlobalKind, TargetInfo, }; use rustc_middle::dep_graph; use rustc_middle::ty::TyCtxt; @@ -63,7 +65,7 @@ pub fn linkage_to_gcc(linkage: Linkage) -> FunctionType { } } -pub fn compile_codegen_unit(tcx: TyCtxt<'_>, cgu_name: Symbol, supports_128bit_integers: bool) -> (ModuleCodegen, u64) { +pub fn compile_codegen_unit(tcx: TyCtxt<'_>, cgu_name: Symbol, target_info: Arc) -> (ModuleCodegen, u64) { let prof_timer = tcx.prof.generic_activity("codegen_module"); let start_time = Instant::now(); @@ -71,7 +73,7 @@ pub fn compile_codegen_unit(tcx: TyCtxt<'_>, cgu_name: Symbol, supports_128bit_i let (module, _) = tcx.dep_graph.with_task( dep_node, tcx, - (cgu_name, supports_128bit_integers), + (cgu_name, target_info), module_codegen, Some(dep_graph::hash_result), ); @@ -82,7 +84,7 @@ pub fn compile_codegen_unit(tcx: TyCtxt<'_>, cgu_name: Symbol, supports_128bit_i // the time we needed for codegenning it. let cost = time_to_codegen.as_secs() * 1_000_000_000 + time_to_codegen.subsec_nanos() as u64; - fn module_codegen(tcx: TyCtxt<'_>, (cgu_name, supports_128bit_integers): (Symbol, bool)) -> ModuleCodegen { + fn module_codegen(tcx: TyCtxt<'_>, (cgu_name, target_info): (Symbol, Arc)) -> ModuleCodegen { let cgu = tcx.codegen_unit(cgu_name); // Instantiate monomorphizations without filling out definitions yet... //let llvm_module = ModuleLlvm::new(tcx, &cgu_name.as_str()); @@ -91,29 +93,36 @@ pub fn compile_codegen_unit(tcx: TyCtxt<'_>, cgu_name: Symbol, supports_128bit_i context.add_command_line_option("-fexceptions"); context.add_driver_option("-fexceptions"); + let disabled_features: HashSet<_> = tcx.sess.opts.cg.target_feature.split(',') + .filter(|feature| feature.starts_with('-')) + .map(|string| &string[1..]) + .collect(); + + let add_cpu_feature_flag = |feature: &str| { + // FIXME(antoyo): some tests cause a segfault in GCC when not enabling all these + // features. + if (true || target_info.cpu_supports(feature)) && !disabled_features.contains(feature) { + context.add_command_line_option(&format!("-m{}", feature)); + } + }; + // TODO(antoyo): only set on x86 platforms. context.add_command_line_option("-masm=intel"); - // TODO(antoyo): only add the following cli argument if the feature is supported. - context.add_command_line_option("-msse2"); - context.add_command_line_option("-mavx2"); - // FIXME(antoyo): the following causes an illegal instruction on vmovdqu64 in std_example on my CPU. - // Only add if the CPU supports it. - context.add_command_line_option("-msha"); + + let features = ["sse2", "avx", "avx2", "sha", "fma", "gfni", "f16c", "aes", "bmi2", "rtm", + "vaes", "vpclmulqdq", "xsavec", + ]; + + for feature in &features { + add_cpu_feature_flag(feature); + } + + // TODO(antoyo): only add the following cli arguments if the feature is supported. context.add_command_line_option("-mpclmul"); - context.add_command_line_option("-mfma"); context.add_command_line_option("-mfma4"); context.add_command_line_option("-m64"); context.add_command_line_option("-mbmi"); - context.add_command_line_option("-mgfni"); //context.add_command_line_option("-mavxvnni"); // The CI doesn't support this option. - context.add_command_line_option("-mf16c"); - context.add_command_line_option("-maes"); - context.add_command_line_option("-mxsavec"); - context.add_command_line_option("-mbmi2"); - context.add_command_line_option("-mrtm"); - context.add_command_line_option("-mvaes"); - context.add_command_line_option("-mvpclmulqdq"); - context.add_command_line_option("-mavx"); for arg in &tcx.sess.opts.cg.llvm_args { context.add_command_line_option(arg); @@ -156,7 +165,7 @@ pub fn compile_codegen_unit(tcx: TyCtxt<'_>, cgu_name: Symbol, supports_128bit_i context.set_allow_unreachable_blocks(true); { - let cx = CodegenCx::new(&context, cgu, tcx, supports_128bit_integers); + let cx = CodegenCx::new(&context, cgu, tcx, target_info.supports_128bit_int()); let mono_items = cgu.items_in_deterministic_order(tcx); for &(mono_item, (linkage, visibility)) in &mono_items { diff --git a/src/lib.rs b/src/lib.rs index 2a6b642782df..4e9c2f91be5e 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -35,7 +35,6 @@ extern crate rustc_middle; extern crate rustc_session; extern crate rustc_span; extern crate rustc_target; -extern crate tempfile; // This prevents duplicating functions and statics that are already part of the host rustc process. #[allow(unused_extern_crates)] @@ -64,10 +63,10 @@ mod type_; mod type_of; use std::any::Any; -use std::sync::{Arc, Mutex}; +use std::sync::Arc; use crate::errors::LTONotSupported; -use gccjit::{Context, OptimizationLevel, CType}; +use gccjit::{Context, OptimizationLevel, TargetInfo}; use rustc_ast::expand::allocator::AllocatorKind; use rustc_codegen_ssa::{CodegenResults, CompiledModule, ModuleCodegen}; use rustc_codegen_ssa::base::codegen_crate; @@ -86,7 +85,6 @@ use rustc_session::config::{Lto, OptLevel, OutputFilenames}; use rustc_session::Session; use rustc_span::Symbol; use rustc_span::fatal_error::FatalError; -use tempfile::TempDir; fluent_messages! { "../messages.ftl" } @@ -102,7 +100,7 @@ impl String> Drop for PrintOnPanic { #[derive(Clone)] pub struct GccCodegenBackend { - supports_128bit_integers: Arc>, + target_info: Arc, } impl CodegenBackend for GccCodegenBackend { @@ -116,15 +114,6 @@ impl CodegenBackend for GccCodegenBackend { if sess.lto() != Lto::No { sess.emit_warning(LTONotSupported {}); } - - let temp_dir = TempDir::new().expect("cannot create temporary directory"); - let temp_file = temp_dir.into_path().join("result.asm"); - let check_context = Context::default(); - check_context.set_print_errors_to_stderr(false); - let _int128_ty = check_context.new_c_type(CType::UInt128t); - // NOTE: we cannot just call compile() as this would require other files than libgccjit.so. - check_context.compile_to_file(gccjit::OutputKind::Assembler, temp_file.to_str().expect("path to str")); - *self.supports_128bit_integers.lock().expect("lock") = check_context.get_last_error() == Ok(None); } fn provide(&self, providers: &mut Providers) { @@ -160,7 +149,7 @@ impl CodegenBackend for GccCodegenBackend { } fn target_features(&self, sess: &Session, allow_unstable: bool) -> Vec { - target_features(sess, allow_unstable) + target_features(sess, allow_unstable, &self.target_info) } } @@ -174,7 +163,7 @@ impl ExtraBackendMethods for GccCodegenBackend { } fn compile_codegen_unit(&self, tcx: TyCtxt<'_>, cgu_name: Symbol) -> (ModuleCodegen, u64) { - base::compile_codegen_unit(tcx, cgu_name, *self.supports_128bit_integers.lock().expect("lock")) + base::compile_codegen_unit(tcx, cgu_name, Arc::clone(&self.target_info)) } fn target_machine_factory(&self, _sess: &Session, _opt_level: OptLevel, _features: &[String]) -> TargetMachineFactoryFn { @@ -273,8 +262,17 @@ impl WriteBackendMethods for GccCodegenBackend { /// This is the entrypoint for a hot plugged rustc_codegen_gccjit #[no_mangle] pub fn __rustc_codegen_backend() -> Box { + // Get the native arch and check whether the target supports 128-bit integers. + let context = Context::default(); + let arch = context.get_target_info().arch().unwrap(); + + // Get the second TargetInfo with the correct CPU features by setting the arch. + let context = Context::default(); + context.add_driver_option(&format!("-march={}", arch.to_str().unwrap())); + let target_info = Arc::new(context.get_target_info()); + Box::new(GccCodegenBackend { - supports_128bit_integers: Arc::new(Mutex::new(false)), + target_info, }) } @@ -308,7 +306,7 @@ pub fn target_cpu(sess: &Session) -> &str { } } -pub fn target_features(sess: &Session, allow_unstable: bool) -> Vec { +pub fn target_features(sess: &Session, allow_unstable: bool, target_info: &Arc) -> Vec { supported_target_features(sess) .iter() .filter_map( @@ -317,14 +315,9 @@ pub fn target_features(sess: &Session, allow_unstable: bool) -> Vec { }, ) .filter(|_feature| { - // TODO(antoyo): implement a way to get enabled feature in libgccjit. - // Probably using the equivalent of __builtin_cpu_supports. - // TODO(antoyo): maybe use whatever outputs the following command: - // gcc -march=native -Q --help=target #[cfg(feature="master")] { - // NOTE: the CPU in the CI doesn't support sse4a, so disable it to make the stdarch tests pass in the CI. - (_feature.contains("sse") || _feature.contains("avx")) && !_feature.contains("avx512") && !_feature.contains("sse4a") + target_info.cpu_supports(_feature) } #[cfg(not(feature="master"))] { @@ -336,7 +329,6 @@ pub fn target_features(sess: &Session, allow_unstable: bool) -> Vec { bmi1, bmi2, cmpxchg16b, ermsb, f16c, fma, fxsr, gfni, lzcnt, movbe, pclmulqdq, popcnt, rdrand, rdseed, rtm, sha, sse, sse2, sse3, sse4.1, sse4.2, sse4a, ssse3, tbm, vaes, vpclmulqdq, xsave, xsavec, xsaveopt, xsaves */ - //false }) .map(|feature| Symbol::intern(feature)) .collect() From e1092eb4d123f568f2f51c8ff4da54d7be89dc0c Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Thu, 6 Jul 2023 17:44:15 -0400 Subject: [PATCH 346/356] Add license explanations --- Readme.md | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Readme.md b/Readme.md index c58662b9ce5d..e05f8dae1c6f 100644 --- a/Readme.md +++ b/Readme.md @@ -105,6 +105,12 @@ $ rustc +$(cat $cg_gccjit_dir/rust-toolchain) -Cpanic=abort -Zcodegen-backend=$c
Display the time it took to perform codegen for a crate
+## Licensing + +While this crate is licensed under a dual Apache/MIT license, it links to `libgccjit` which is under the GPLv3+ and thus, the resulting toolchain (rustc + GCC codegen) will need to be released under the GPL license. + +However, programs compiled with `rustc_codegen_gcc` do not need to be released under a GPL license. + ## Debugging Sometimes, libgccjit will crash and output an error like this: From 97a0d35a8c21b8aeed474a5fa856e89c1feeb5fb Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Thu, 6 Jul 2023 16:54:50 +0200 Subject: [PATCH 347/356] Add support for "returns_twice" function attribute --- src/attributes.rs | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/attributes.rs b/src/attributes.rs index fbafc981f664..0fda9e7ae50b 100644 --- a/src/attributes.rs +++ b/src/attributes.rs @@ -118,6 +118,9 @@ pub fn from_fn_attrs<'gcc, 'tcx>( if codegen_fn_attrs.flags.contains(CodegenFnAttrFlags::COLD) { func.add_attribute(FnAttribute::Cold); } + if codegen_fn_attrs.flags.contains(CodegenFnAttrFlags::FFI_RETURNS_TWICE) { + func.add_attribute(FnAttribute::ReturnsTwice); + } } let function_features = From a6d1aa28101ca14c07aaf367b41cc4a13aaad82e Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Wed, 12 Jul 2023 16:46:16 +0200 Subject: [PATCH 348/356] Update gccjit dependency --- Cargo.lock | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 2800dc6ccd14..3062b191f35a 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -77,7 +77,7 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" -source = "git+https://github.com/antoyo/gccjit.rs#79c8bb49ff09b7f40a04055203a5f3894a266210" +source = "git+https://github.com/antoyo/gccjit.rs#78ed1a380eb276e7443645a41b0e87222f291e82" dependencies = [ "gccjit_sys", ] @@ -85,7 +85,7 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" -source = "git+https://github.com/antoyo/gccjit.rs#79c8bb49ff09b7f40a04055203a5f3894a266210" +source = "git+https://github.com/antoyo/gccjit.rs#78ed1a380eb276e7443645a41b0e87222f291e82" dependencies = [ "libc", ] From c04a631ea651c76504f281994984f75971353735 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Thu, 13 Jul 2023 21:43:12 +0200 Subject: [PATCH 349/356] Add support for "pure" function attribute --- src/attributes.rs | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/attributes.rs b/src/attributes.rs index 0fda9e7ae50b..6195de912d27 100644 --- a/src/attributes.rs +++ b/src/attributes.rs @@ -121,6 +121,9 @@ pub fn from_fn_attrs<'gcc, 'tcx>( if codegen_fn_attrs.flags.contains(CodegenFnAttrFlags::FFI_RETURNS_TWICE) { func.add_attribute(FnAttribute::ReturnsTwice); } + if codegen_fn_attrs.flags.contains(CodegenFnAttrFlags::FFI_PURE) { + func.add_attribute(FnAttribute::Pure); + } } let function_features = From 7ba60ecb538249a7ba23d3a4bcc96e468de03a50 Mon Sep 17 00:00:00 2001 From: bjorn3 <17426603+bjorn3@users.noreply.github.com> Date: Sat, 15 Jul 2023 12:37:47 +0000 Subject: [PATCH 350/356] Extract a create_wrapper_function for use in allocator shim writing This deduplicates some logic and makes it easier to follow what wrappers are produced. In the future it may allow moving the code to determine which wrappers to create to cg_ssa. --- src/allocator.rs | 135 ++++++++++++++++++++++------------------------- 1 file changed, 63 insertions(+), 72 deletions(-) diff --git a/src/allocator.rs b/src/allocator.rs index 13f88192bbc9..38309fa01539 100644 --- a/src/allocator.rs +++ b/src/allocator.rs @@ -1,6 +1,6 @@ #[cfg(feature="master")] use gccjit::FnAttribute; -use gccjit::{FunctionType, GlobalKind, ToRValue}; +use gccjit::{Context, FunctionType, GlobalKind, ToRValue, Type}; use rustc_ast::expand::allocator::{ alloc_error_handler_name, default_fn_name, global_fn_name, AllocatorKind, AllocatorTy, ALLOCATOR_METHODS, NO_ALLOC_SHIM_IS_UNSTABLE, @@ -22,7 +22,6 @@ pub(crate) unsafe fn codegen(tcx: TyCtxt<'_>, mods: &mut GccContext, _module_nam }; let i8 = context.new_type::(); let i8p = i8.make_pointer(); - let void = context.new_type::<()>(); if kind == AllocatorKind::Default { for method in ALLOCATOR_METHODS { @@ -47,80 +46,22 @@ pub(crate) unsafe fn codegen(tcx: TyCtxt<'_>, mods: &mut GccContext, _module_nam panic!("invalid allocator output") } }; - let name = global_fn_name(method.name); + let from_name = global_fn_name(method.name); + let to_name = default_fn_name(method.name); - let args: Vec<_> = types.iter().enumerate() - .map(|(index, typ)| context.new_parameter(None, *typ, &format!("param{}", index))) - .collect(); - let func = context.new_function(None, FunctionType::Exported, output.unwrap_or(void), &args, name, false); - - if tcx.sess.target.options.default_hidden_visibility { - #[cfg(feature="master")] - func.add_attribute(FnAttribute::Visibility(gccjit::Visibility::Hidden)); - } - if tcx.sess.must_emit_unwind_tables() { - // TODO(antoyo): emit unwind tables. - } - - let callee = default_fn_name(method.name); - let args: Vec<_> = types.iter().enumerate() - .map(|(index, typ)| context.new_parameter(None, *typ, &format!("param{}", index))) - .collect(); - let callee = context.new_function(None, FunctionType::Extern, output.unwrap_or(void), &args, callee, false); - #[cfg(feature="master")] - callee.add_attribute(FnAttribute::Visibility(gccjit::Visibility::Hidden)); - - let block = func.new_block("entry"); - - let args = args - .iter() - .enumerate() - .map(|(i, _)| func.get_param(i as i32).to_rvalue()) - .collect::>(); - let ret = context.new_call(None, callee, &args); - //llvm::LLVMSetTailCall(ret, True); - if output.is_some() { - block.end_with_return(None, ret); - } - else { - block.end_with_void_return(None); - } - - // TODO(@Commeownist): Check if we need to emit some extra debugging info in certain circumstances - // as described in https://github.com/rust-lang/rust/commit/77a96ed5646f7c3ee8897693decc4626fe380643 + create_wrapper_function(tcx, context, &from_name, &to_name, &types, output); } } - let types = [usize, usize]; - let name = "__rust_alloc_error_handler".to_string(); - let args: Vec<_> = types.iter().enumerate() - .map(|(index, typ)| context.new_parameter(None, *typ, &format!("param{}", index))) - .collect(); - let func = context.new_function(None, FunctionType::Exported, void, &args, name, false); - - if tcx.sess.target.default_hidden_visibility { - #[cfg(feature="master")] - func.add_attribute(FnAttribute::Visibility(gccjit::Visibility::Hidden)); - } - - let callee = alloc_error_handler_name(alloc_error_handler_kind); - let args: Vec<_> = types.iter().enumerate() - .map(|(index, typ)| context.new_parameter(None, *typ, &format!("param{}", index))) - .collect(); - let callee = context.new_function(None, FunctionType::Extern, void, &args, callee, false); - #[cfg(feature="master")] - callee.add_attribute(FnAttribute::Visibility(gccjit::Visibility::Hidden)); - - let block = func.new_block("entry"); - - let args = args - .iter() - .enumerate() - .map(|(i, _)| func.get_param(i as i32).to_rvalue()) - .collect::>(); - let _ret = context.new_call(None, callee, &args); - //llvm::LLVMSetTailCall(ret, True); - block.end_with_void_return(None); + // FIXME(bjorn3): Add noreturn attribute + create_wrapper_function( + tcx, + context, + "__rust_alloc_error_handler", + &alloc_error_handler_name(alloc_error_handler_kind), + &[usize, usize], + None, + ); let name = OomStrategy::SYMBOL.to_string(); let global = context.new_global(None, GlobalKind::Exported, i8, name); @@ -133,3 +74,53 @@ pub(crate) unsafe fn codegen(tcx: TyCtxt<'_>, mods: &mut GccContext, _module_nam let value = context.new_rvalue_from_int(i8, 0); global.global_set_initializer_rvalue(value); } + +fn create_wrapper_function( + tcx: TyCtxt<'_>, + context: &Context<'_>, + from_name: &str, + to_name: &str, + types: &[Type<'_>], + output: Option>, +) { + let void = context.new_type::<()>(); + + let args: Vec<_> = types.iter().enumerate() + .map(|(index, typ)| context.new_parameter(None, *typ, &format!("param{}", index))) + .collect(); + let func = context.new_function(None, FunctionType::Exported, output.unwrap_or(void), &args, from_name, false); + + if tcx.sess.target.options.default_hidden_visibility { + #[cfg(feature="master")] + func.add_attribute(FnAttribute::Visibility(gccjit::Visibility::Hidden)); + } + if tcx.sess.must_emit_unwind_tables() { + // TODO(antoyo): emit unwind tables. + } + + let args: Vec<_> = types.iter().enumerate() + .map(|(index, typ)| context.new_parameter(None, *typ, &format!("param{}", index))) + .collect(); + let callee = context.new_function(None, FunctionType::Extern, output.unwrap_or(void), &args, to_name, false); + #[cfg(feature="master")] + callee.add_attribute(FnAttribute::Visibility(gccjit::Visibility::Hidden)); + + let block = func.new_block("entry"); + + let args = args + .iter() + .enumerate() + .map(|(i, _)| func.get_param(i as i32).to_rvalue()) + .collect::>(); + let ret = context.new_call(None, callee, &args); + //llvm::LLVMSetTailCall(ret, True); + if output.is_some() { + block.end_with_return(None, ret); + } + else { + block.end_with_void_return(None); + } + + // TODO(@Commeownist): Check if we need to emit some extra debugging info in certain circumstances + // as described in https://github.com/rust-lang/rust/commit/77a96ed5646f7c3ee8897693decc4626fe380643 +} From 34922fc3ce1bd25fa2701c419a455d4dd4fe960e Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Mon, 17 Jul 2023 23:22:45 +0200 Subject: [PATCH 351/356] Update gccjit-rs version --- Cargo.lock | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 3062b191f35a..488b51c9366b 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -77,7 +77,7 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" -source = "git+https://github.com/antoyo/gccjit.rs#78ed1a380eb276e7443645a41b0e87222f291e82" +source = "git+https://github.com/antoyo/gccjit.rs#de70a3bdc1908098ae4b10efc530bd695971a67c" dependencies = [ "gccjit_sys", ] @@ -85,7 +85,7 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" -source = "git+https://github.com/antoyo/gccjit.rs#78ed1a380eb276e7443645a41b0e87222f291e82" +source = "git+https://github.com/antoyo/gccjit.rs#de70a3bdc1908098ae4b10efc530bd695971a67c" dependencies = [ "libc", ] From 918332bea228e103fd2e81dc719a53e4c3122bac Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Fri, 21 Jul 2023 11:23:41 +0200 Subject: [PATCH 352/356] Add support for "ffi_const" function attribute --- src/attributes.rs | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/attributes.rs b/src/attributes.rs index 6195de912d27..35682db9c785 100644 --- a/src/attributes.rs +++ b/src/attributes.rs @@ -124,6 +124,9 @@ pub fn from_fn_attrs<'gcc, 'tcx>( if codegen_fn_attrs.flags.contains(CodegenFnAttrFlags::FFI_PURE) { func.add_attribute(FnAttribute::Pure); } + if codegen_fn_attrs.flags.contains(CodegenFnAttrFlags::FFI_CONST) { + func.add_attribute(FnAttribute::Const); + } } let function_features = From 136548d3fe9d2c8ac993d7d1b0d2e20256f02750 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Sat, 22 Jul 2023 14:44:20 +0200 Subject: [PATCH 353/356] Update gccjit dependency --- Cargo.lock | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 488b51c9366b..60df0e60988b 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -77,7 +77,7 @@ dependencies = [ [[package]] name = "gccjit" version = "1.0.0" -source = "git+https://github.com/antoyo/gccjit.rs#de70a3bdc1908098ae4b10efc530bd695971a67c" +source = "git+https://github.com/antoyo/gccjit.rs#61d8d55c894bd462ee66c096cc31157a44a9f869" dependencies = [ "gccjit_sys", ] @@ -85,7 +85,7 @@ dependencies = [ [[package]] name = "gccjit_sys" version = "0.0.1" -source = "git+https://github.com/antoyo/gccjit.rs#de70a3bdc1908098ae4b10efc530bd695971a67c" +source = "git+https://github.com/antoyo/gccjit.rs#61d8d55c894bd462ee66c096cc31157a44a9f869" dependencies = [ "libc", ] From cd57c6ea1c13db57a6ebd4423ddbf2ca8e28e765 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Fri, 21 Jul 2023 15:14:15 +0200 Subject: [PATCH 354/356] Add instructions on how to generate GIMPLE format --- Readme.md | 5 ++++ doc/gimple.md | 80 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 85 insertions(+) create mode 100644 doc/gimple.md diff --git a/Readme.md b/Readme.md index e05f8dae1c6f..b9a78b0277b7 100644 --- a/Readme.md +++ b/Readme.md @@ -227,6 +227,11 @@ https://rust-lang.zulipchat.com/#narrow/stream/301329-t-devtools/topic/subtree.2 `rustc` needs to be built without `jemalloc` so that `mem-trace` can overload `malloc` since `jemalloc` is linked statically, so a `LD_PRELOAD`-ed library won't a chance to intercept the calls to `malloc`. +### How to generate GIMPLE + +If you need to check what gccjit is generating (GIMPLE), then take a look at how to +generate it in [gimple.md](./doc/gimple.md). + ### How to build a cross-compiling libgccjit #### Building libgccjit diff --git a/doc/gimple.md b/doc/gimple.md new file mode 100644 index 000000000000..589cf3db7a68 --- /dev/null +++ b/doc/gimple.md @@ -0,0 +1,80 @@ +# GIMPLE + +You can see the full documentation about what GIMPLE is [here](https://gcc.gnu.org/onlinedocs/gccint/GIMPLE.html). In this document we will explain how to generate it. + +First, we'll copy the content from `gcc/gcc/testsuite/jit.dg/test-const-attribute.c` into a +file named `local.c` and remove the content we're not interested into: + +```diff +- /* { dg-do compile { target x86_64-*-* } } */ +... +- /* We don't want set_options() in harness.h to set -O3 to see that the const +- attribute affects the optimizations. */ +- #define TEST_ESCHEWS_SET_OPTIONS +- static void set_options (gcc_jit_context *ctxt, const char *argv0) +- { +- // Set "-O3". +- gcc_jit_context_set_int_option(ctxt, GCC_JIT_INT_OPTION_OPTIMIZATION_LEVEL, 3); +- } +- +- #define TEST_COMPILING_TO_FILE +- #define OUTPUT_KIND GCC_JIT_OUTPUT_KIND_ASSEMBLER +- #define OUTPUT_FILENAME "output-of-test-const-attribute.c.s" +- #include "harness.h" +... +- /* { dg-final { jit-verify-output-file-was-created "" } } */ +- /* Check that the loop was optimized away */ +- /* { dg-final { jit-verify-assembler-output-not "jne" } } */ +``` + +Then we'll add a `main` function which will call the `create_code` function but +also add the calls we need to generate the GIMPLE: + +```C +int main() { + gcc_jit_context *ctxt = gcc_jit_context_acquire(); + create_code(ctxt, NULL); + gcc_jit_context_compile_to_file(ctxt, GCC_JIT_OUTPUT_KIND_DYNAMIC_LIBRARY, "tmp"); + return 0; +} +``` + +Then we can compile it by using: + +```console +gcc const.c -I `pwd`/gcc/gcc/jit/ -L `pwd`/gcc-build/gcc -lgccjit -o out +``` + +And finally when you run it: + +```console +LD_LIBRARY_PATH=`pwd`/gcc-build/gcc ./out +``` + +It should display: + +```c +__attribute__((const)) +int xxx () +{ + int D.3394; + int sum; + int x; + + : + x = 45; + sum = 0; + goto loop_cond; + loop_cond: + x = x >> 1; + if (x != 0) goto after_loop; else goto loop_body; + loop_body: + _1 = foo (x); + _2 = _1 * 2; + x = x + _2; + goto loop_cond; + after_loop: + D.3394 = sum; + return D.3394; +} +``` From 14964ed2f6c8f19a444afe886d0c2ac68a831e45 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Mon, 24 Jul 2023 13:49:35 -0400 Subject: [PATCH 355/356] Update the IRC link to the link of the Matrix channel --- Readme.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Readme.md b/Readme.md index b9a78b0277b7..fbe1a407733c 100644 --- a/Readme.md +++ b/Readme.md @@ -1,6 +1,6 @@ # WIP libgccjit codegen backend for rust -[![Chat on IRC](https://img.shields.io/badge/irc.libera.chat-%23rustc__codegen__gcc-blue.svg)](https://web.libera.chat/#rustc_codegen_gcc) +[![Chat on IRC](https://img.shields.io/badge/matrix.org-%23rustc__codegen__gcc-blue.svg)](https://matrix.to/#/#rustc_codegen_gcc:matrix.org) This is a GCC codegen for rustc, which means it can be loaded by the existing rustc frontend, but benefits from GCC: more architectures are supported and GCC's optimizations are used. From 52716d237cf00dab0d51b253bc080810570f47ef Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Thu, 27 Jul 2023 19:21:00 -0400 Subject: [PATCH 356/356] Add back link to IRC --- Readme.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Readme.md b/Readme.md index fbe1a407733c..55daad6dcd01 100644 --- a/Readme.md +++ b/Readme.md @@ -1,6 +1,7 @@ # WIP libgccjit codegen backend for rust -[![Chat on IRC](https://img.shields.io/badge/matrix.org-%23rustc__codegen__gcc-blue.svg)](https://matrix.to/#/#rustc_codegen_gcc:matrix.org) +[![Chat on IRC](https://img.shields.io/badge/irc.libera.chat-%23rustc__codegen__gcc-blue.svg)](https://web.libera.chat/#rustc_codegen_gcc) +[![Chat on Matrix](https://img.shields.io/badge/matrix.org-%23rustc__codegen__gcc-blue.svg)](https://matrix.to/#/#rustc_codegen_gcc:matrix.org) This is a GCC codegen for rustc, which means it can be loaded by the existing rustc frontend, but benefits from GCC: more architectures are supported and GCC's optimizations are used.