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Remove unsupported *vfp functions (#678)

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Remove all *vfp functions and related tests since LLVM no longer emits them.

Link: https://github.com/rust-lang/compiler-builtins/pull/626

[ Reword commit message - Trevor ]
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Sbstn Bcht 2024-09-04 04:55:44 +02:00 • committed by GitHub
parent 6a78d7c2b6
commit 69406c118a
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13 changed files with 37 additions and 191 deletions
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71
library/compiler-builtins/README.md
View file

@ -103,9 +103,7 @@ rely on CI.
- [x] aarch64/chkstk.S
- [x] adddf3.c
- [x] addsf3.c
- [x] arm/adddf3vfp.S
- [x] arm/addsf3.S
- [x] arm/addsf3vfp.S
- [x] arm/aeabi_dcmp.S
- [x] arm/aeabi_fcmp.S
- [x] arm/aeabi_idivmod.S
@ -116,45 +114,13 @@ rely on CI.
- [x] arm/aeabi_uidivmod.S
- [x] arm/aeabi_uldivmod.S
- [ ] arm/chkstk.S
- [x] arm/divdf3vfp.S
- [ ] arm/divmodsi4.S (generic version is done)
- [x] arm/divsf3vfp.S
- [ ] arm/divsi3.S (generic version is done)
- [x] arm/eqdf2vfp.S
- [x] arm/eqsf2vfp.S
- [x] arm/extendsfdf2vfp.S
- [ ] arm/fixdfsivfp.S
- [ ] arm/fixsfsivfp.S
- [ ] arm/fixunsdfsivfp.S
- [ ] arm/fixunssfsivfp.S
- [ ] arm/floatsidfvfp.S
- [ ] arm/floatsisfvfp.S
- [ ] arm/floatunssidfvfp.S
- [ ] arm/floatunssisfvfp.S
- [x] arm/gedf2vfp.S
- [x] arm/gesf2vfp.S
- [x] arm/gtdf2vfp.S
- [x] arm/gtsf2vfp.S
- [x] arm/ledf2vfp.S
- [x] arm/lesf2vfp.S
- [x] arm/ltdf2vfp.S
- [x] arm/ltsf2vfp.S
- [ ] arm/modsi3.S (generic version is done)
- [x] arm/muldf3vfp.S
- [x] arm/mulsf3vfp.S
- [x] arm/nedf2vfp.S
- [ ] arm/negdf2vfp.S
- [ ] arm/negsf2vfp.S
- [x] arm/nesf2vfp.S
- [x] arm/softfloat-alias.list
- [x] arm/subdf3vfp.S
- [x] arm/subsf3vfp.S
- [x] arm/truncdfsf2vfp.S
- [ ] arm/udivmodsi4.S (generic version is done)
- [ ] arm/udivsi3.S (generic version is done)
- [ ] arm/umodsi3.S (generic version is done)
- [ ] arm/unorddf2vfp.S
- [ ] arm/unordsf2vfp.S
- [x] ashldi3.c
- [x] ashrdi3.c
- [ ] avr/divmodhi4.S
@ -501,6 +467,43 @@ Floating-point implementations of builtins that are only called from soft-float
- ~~x86_64/floatdidf.c~~
- ~~x86_64/floatdisf.c~~
Unsupported in any current target: used on old versions of 32-bit iOS with ARMv5.
- ~~arm/adddf3vfp.S~~
- ~~arm/addsf3vfp.S~~
- ~~arm/divdf3vfp.S~~
- ~~arm/divsf3vfp.S~~
- ~~arm/eqdf2vfp.S~~
- ~~arm/eqsf2vfp.S~~
- ~~arm/extendsfdf2vfp.S~~
- ~~arm/fixdfsivfp.S~~
- ~~arm/fixsfsivfp.S~~
- ~~arm/fixunsdfsivfp.S~~
- ~~arm/fixunssfsivfp.S~~
- ~~arm/floatsidfvfp.S~~
- ~~arm/floatsisfvfp.S~~
- ~~arm/floatunssidfvfp.S~~
- ~~arm/floatunssisfvfp.S~~
- ~~arm/gedf2vfp.S~~
- ~~arm/gesf2vfp.S~~
- ~~arm/gtdf2vfp.S~~
- ~~arm/gtsf2vfp.S~~
- ~~arm/ledf2vfp.S~~
- ~~arm/lesf2vfp.S~~
- ~~arm/ltdf2vfp.S~~
- ~~arm/ltsf2vfp.S~~
- ~~arm/muldf3vfp.S~~
- ~~arm/mulsf3vfp.S~~
- ~~arm/nedf2vfp.S~~
- ~~arm/negdf2vfp.S~~
- ~~arm/negsf2vfp.S~~
- ~~arm/nesf2vfp.S~~
- ~~arm/subdf3vfp.S~~
- ~~arm/subsf3vfp.S~~
- ~~arm/truncdfsf2vfp.S~~
- ~~arm/unorddf2vfp.S~~
- ~~arm/unordsf2vfp.S~~
## License
The compiler-builtins crate is dual licensed under both the University of

10
library/compiler-builtins/src/float/add.rs
View file

@ -208,14 +208,4 @@ intrinsics! {
pub extern "C" fn __addtf3(a: f128, b: f128) -> f128 {
add(a, b)
}
#[cfg(target_arch = "arm")]
pub extern "C" fn __addsf3vfp(a: f32, b: f32) -> f32 {
a + b
}
#[cfg(target_arch = "arm")]
pub extern "C" fn __adddf3vfp(a: f64, b: f64) -> f64 {
a + b
}
}

51
library/compiler-builtins/src/float/cmp.rs
View file

@ -258,55 +258,4 @@ intrinsics! {
pub extern "aapcs" fn __aeabi_dcmpgt(a: f64, b: f64) -> i32 {
(__gtdf2(a, b) > 0) as i32
}
// On hard-float targets LLVM will use native instructions
// for all VFP intrinsics below
pub extern "C" fn __gesf2vfp(a: f32, b: f32) -> i32 {
(a >= b) as i32
}
pub extern "C" fn __gedf2vfp(a: f64, b: f64) -> i32 {
(a >= b) as i32
}
pub extern "C" fn __gtsf2vfp(a: f32, b: f32) -> i32 {
(a > b) as i32
}
pub extern "C" fn __gtdf2vfp(a: f64, b: f64) -> i32 {
(a > b) as i32
}
pub extern "C" fn __ltsf2vfp(a: f32, b: f32) -> i32 {
(a < b) as i32
}
pub extern "C" fn __ltdf2vfp(a: f64, b: f64) -> i32 {
(a < b) as i32
}
pub extern "C" fn __lesf2vfp(a: f32, b: f32) -> i32 {
(a <= b) as i32
}
pub extern "C" fn __ledf2vfp(a: f64, b: f64) -> i32 {
(a <= b) as i32
}
pub extern "C" fn __nesf2vfp(a: f32, b: f32) -> i32 {
(a != b) as i32
}
pub extern "C" fn __nedf2vfp(a: f64, b: f64) -> i32 {
(a != b) as i32
}
pub extern "C" fn __eqsf2vfp(a: f32, b: f32) -> i32 {
(a == b) as i32
}
pub extern "C" fn __eqdf2vfp(a: f64, b: f64) -> i32 {
(a == b) as i32
}
}

10
library/compiler-builtins/src/float/div.rs
View file

@ -926,14 +926,4 @@ intrinsics! {
pub extern "C" fn __divdf3(a: f64, b: f64) -> f64 {
div64(a, b)
}
#[cfg(target_arch = "arm")]
pub extern "C" fn __divsf3vfp(a: f32, b: f32) -> f32 {
a / b
}
#[cfg(target_arch = "arm")]
pub extern "C" fn __divdf3vfp(a: f64, b: f64) -> f64 {
a / b
}
}

5
library/compiler-builtins/src/float/extend.rs
View file

@ -76,11 +76,6 @@ intrinsics! {
pub extern "C" fn __extendsfdf2(a: f32) -> f64 {
extend(a)
}
#[cfg(target_arch = "arm")]
pub extern "C" fn __extendsfdf2vfp(a: f32) -> f64 {
a as f64 // LLVM generate 'fcvtds'
}
}
intrinsics! {

10
library/compiler-builtins/src/float/mul.rs
View file

@ -199,14 +199,4 @@ intrinsics! {
pub extern "C" fn __multf3(a: f128, b: f128) -> f128 {
mul(a, b)
}
#[cfg(target_arch = "arm")]
pub extern "C" fn __mulsf3vfp(a: f32, b: f32) -> f32 {
a * b
}
#[cfg(target_arch = "arm")]
pub extern "C" fn __muldf3vfp(a: f64, b: f64) -> f64 {
a * b
}
}

10
library/compiler-builtins/src/float/sub.rs
View file

@ -23,14 +23,4 @@ intrinsics! {
__addtf3(a, f128::from_repr(b.repr() ^ f128::SIGN_MASK))
}
#[cfg(target_arch = "arm")]
pub extern "C" fn __subsf3vfp(a: f32, b: f32) -> f32 {
a - b
}
#[cfg(target_arch = "arm")]
pub extern "C" fn __subdf3vfp(a: f64, b: f64) -> f64 {
a - b
}
}

5
library/compiler-builtins/src/float/trunc.rs
View file

@ -124,11 +124,6 @@ intrinsics! {
pub extern "C" fn __truncdfsf2(a: f64) -> f32 {
trunc(a)
}
#[cfg(target_arch = "arm")]
pub extern "C" fn __truncdfsf2vfp(a: f64) -> f32 {
a as f32
}
}
intrinsics! {

10
library/compiler-builtins/testcrate/tests/addsub.rs
View file

@ -139,13 +139,3 @@ mod float_addsub_f128_ppc {
f128, __addkf3, __subkf3, Quad, not(feature = "no-sys-f128");
}
}
#[cfg(target_arch = "arm")]
mod float_addsub_arm {
use super::*;
float_sum! {
f32, __addsf3vfp, __subsf3vfp, Single, all();
f64, __adddf3vfp, __subdf3vfp, Double, all();
}
}

14
library/compiler-builtins/testcrate/tests/cmp.rs
View file

@ -156,7 +156,6 @@ mod float_comparisons_arm {
fn cmp_f32() {
use compiler_builtins::float::cmp::{
__aeabi_fcmpeq, __aeabi_fcmpge, __aeabi_fcmpgt, __aeabi_fcmple, __aeabi_fcmplt,
__eqsf2vfp, __gesf2vfp, __gtsf2vfp, __lesf2vfp, __ltsf2vfp, __nesf2vfp,
};
fuzz_float_2(N, |x: f32, y: f32| {
@ -166,12 +165,6 @@ mod float_comparisons_arm {
0, x == y, __aeabi_fcmpeq;
0, x >= y, __aeabi_fcmpge;
0, x > y, __aeabi_fcmpgt;
0, x < y, __ltsf2vfp;
0, x <= y, __lesf2vfp;
0, x == y, __eqsf2vfp;
0, x >= y, __gesf2vfp;
0, x > y, __gtsf2vfp;
1, x != y, __nesf2vfp;
);
});
}
@ -180,7 +173,6 @@ mod float_comparisons_arm {
fn cmp_f64() {
use compiler_builtins::float::cmp::{
__aeabi_dcmpeq, __aeabi_dcmpge, __aeabi_dcmpgt, __aeabi_dcmple, __aeabi_dcmplt,
__eqdf2vfp, __gedf2vfp, __gtdf2vfp, __ledf2vfp, __ltdf2vfp, __nedf2vfp,
};
fuzz_float_2(N, |x: f64, y: f64| {
@ -190,12 +182,6 @@ mod float_comparisons_arm {
0, x == y, __aeabi_dcmpeq;
0, x >= y, __aeabi_dcmpge;
0, x > y, __aeabi_dcmpgt;
0, x < y, __ltdf2vfp;
0, x <= y, __ledf2vfp;
0, x == y, __eqdf2vfp;
0, x >= y, __gedf2vfp;
0, x > y, __gtdf2vfp;
1, x != y, __nedf2vfp;
);
});
}

12
library/compiler-builtins/testcrate/tests/conv.rs
View file

@ -258,12 +258,6 @@ mod extend {
f32 => f64, Single => Double, __extendsfdf2, all();
}
#[cfg(target_arch = "arm")]
f_to_f! {
extend,
f32 => f64, Single => Double, __extendsfdf2vfp, all();
}
#[cfg(all(f16_enabled, f128_enabled))]
#[cfg(not(any(target_arch = "powerpc", target_arch = "powerpc64")))]
f_to_f! {
@ -293,12 +287,6 @@ mod trunc {
f64 => f32, Double => Single, __truncdfsf2, all();
}
#[cfg(target_arch = "arm")]
f_to_f! {
trunc,
f64 => f32, Double => Single, __truncdfsf2vfp, all();
}
#[cfg(all(f16_enabled, f128_enabled))]
#[cfg(not(any(target_arch = "powerpc", target_arch = "powerpc64")))]
f_to_f! {

10
library/compiler-builtins/testcrate/tests/div_rem.rs
View file

@ -156,13 +156,3 @@ mod float_div {
f64, __divdf3, Double, all();
}
}
#[cfg(target_arch = "arm")]
mod float_div_arm {
use super::*;
float! {
f32, __divsf3vfp, Single, all();
f64, __divdf3vfp, Double, all();
}
}

10
library/compiler-builtins/testcrate/tests/mul.rs
View file

@ -153,13 +153,3 @@ mod float_mul_f128_ppc {
f128, __mulkf3, Quad, not(feature = "no-sys-f128");
}
}
#[cfg(target_arch = "arm")]
mod float_mul_arm {
use super::*;
float_mul! {
f32, __mulsf3vfp, Single, all();
f64, __muldf3vfp, Double, all();
}
}