Add tracking issue for AArch64 prefetch intrinsic

This commit is contained in:
Amanieu d'Antras 2023-10-26 12:26:23 +01:00
parent a70d90d17a
commit 6bde701fe3
2 changed files with 8 additions and 0 deletions

View file

@ -22,6 +22,7 @@ mod crc;
pub use self::crc::*;
mod prefetch;
#[unstable(feature = "stdarch_aarch64_prefetch", issue = "117217")]
pub use self::prefetch::*;
#[stable(feature = "neon_intrinsics", since = "1.59.0")]

View file

@ -7,21 +7,27 @@ extern "unadjusted" {
}
/// See [`prefetch`](fn._prefetch.html).
#[unstable(feature = "stdarch_aarch64_prefetch", issue = "117217")]
pub const _PREFETCH_READ: i32 = 0;
/// See [`prefetch`](fn._prefetch.html).
#[unstable(feature = "stdarch_aarch64_prefetch", issue = "117217")]
pub const _PREFETCH_WRITE: i32 = 1;
/// See [`prefetch`](fn._prefetch.html).
#[unstable(feature = "stdarch_aarch64_prefetch", issue = "117217")]
pub const _PREFETCH_LOCALITY0: i32 = 0;
/// See [`prefetch`](fn._prefetch.html).
#[unstable(feature = "stdarch_aarch64_prefetch", issue = "117217")]
pub const _PREFETCH_LOCALITY1: i32 = 1;
/// See [`prefetch`](fn._prefetch.html).
#[unstable(feature = "stdarch_aarch64_prefetch", issue = "117217")]
pub const _PREFETCH_LOCALITY2: i32 = 2;
/// See [`prefetch`](fn._prefetch.html).
#[unstable(feature = "stdarch_aarch64_prefetch", issue = "117217")]
pub const _PREFETCH_LOCALITY3: i32 = 3;
/// Fetch the cache line that contains address `p` using the given `RW` and `LOCALITY`.
@ -64,6 +70,7 @@ pub const _PREFETCH_LOCALITY3: i32 = 3;
#[cfg_attr(test, assert_instr("prfm pstl2keep", RW = _PREFETCH_WRITE, LOCALITY = _PREFETCH_LOCALITY2))]
#[cfg_attr(test, assert_instr("prfm pstl1keep", RW = _PREFETCH_WRITE, LOCALITY = _PREFETCH_LOCALITY3))]
#[rustc_legacy_const_generics(1, 2)]
#[unstable(feature = "stdarch_aarch64_prefetch", issue = "117217")]
// FIXME: Replace this with the standard ACLE __pld/__pldx/__pli/__plix intrinsics
pub unsafe fn _prefetch<const RW: i32, const LOCALITY: i32>(p: *const i8) {
// We use the `llvm.prefetch` intrinsic with `cache type` = 1 (data cache).