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Re-enable all conditionally-disabled x86 assert_instr tests

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sayantn 2025-04-14 11:27:22 +05:30 • committed by Amanieu d'Antras
parent c10b7f8a26
commit 6cc17153d9
12 changed files with 101 additions and 341 deletions
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30
library/stdarch/crates/core_arch/src/x86/avx.rs
View file

@ -970,10 +970,7 @@ pub fn _mm256_cvttps_epi32(a: __m256) -> __m256i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_extractf128_ps)
#[inline]
#[target_feature(enable = "avx")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vextractf128, IMM1 = 1)
)]
#[cfg_attr(test, assert_instr(vextractf128, IMM1 = 1))]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm256_extractf128_ps<const IMM1: i32>(a: __m256) -> __m128 {
@ -993,10 +990,7 @@ pub fn _mm256_extractf128_ps<const IMM1: i32>(a: __m256) -> __m128 {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_extractf128_pd)
#[inline]
#[target_feature(enable = "avx")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vextractf128, IMM1 = 1)
)]
#[cfg_attr(test, assert_instr(vextractf128, IMM1 = 1))]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm256_extractf128_pd<const IMM1: i32>(a: __m256d) -> __m128d {
@ -1009,10 +1003,7 @@ pub fn _mm256_extractf128_pd<const IMM1: i32>(a: __m256d) -> __m128d {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_extractf128_si256)
#[inline]
#[target_feature(enable = "avx")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vextractf128, IMM1 = 1)
)]
#[cfg_attr(test, assert_instr(vextractf128, IMM1 = 1))]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm256_extractf128_si256<const IMM1: i32>(a: __m256i) -> __m128i {
@ -1328,10 +1319,7 @@ pub unsafe fn _mm256_broadcast_pd(a: &__m128d) -> __m256d {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_insertf128_ps)
#[inline]
#[target_feature(enable = "avx")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vinsertf128, IMM1 = 1)
)]
#[cfg_attr(test, assert_instr(vinsertf128, IMM1 = 1))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm256_insertf128_ps<const IMM1: i32>(a: __m256, b: __m128) -> __m256 {
@ -1352,10 +1340,7 @@ pub fn _mm256_insertf128_ps<const IMM1: i32>(a: __m256, b: __m128) -> __m256 {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_insertf128_pd)
#[inline]
#[target_feature(enable = "avx")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vinsertf128, IMM1 = 1)
)]
#[cfg_attr(test, assert_instr(vinsertf128, IMM1 = 1))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm256_insertf128_pd<const IMM1: i32>(a: __m256d, b: __m128d) -> __m256d {
@ -1375,10 +1360,7 @@ pub fn _mm256_insertf128_pd<const IMM1: i32>(a: __m256d, b: __m128d) -> __m256d
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_insertf128_si256)
#[inline]
#[target_feature(enable = "avx")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vinsertf128, IMM1 = 1)
)]
#[cfg_attr(test, assert_instr(vinsertf128, IMM1 = 1))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm256_insertf128_si256<const IMM1: i32>(a: __m256i, b: __m128i) -> __m256i {

10
library/stdarch/crates/core_arch/src/x86/avx2.rs
View file

@ -957,10 +957,7 @@ pub fn _mm256_cvtepu8_epi64(a: __m128i) -> __m256i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_extracti128_si256)
#[inline]
#[target_feature(enable = "avx2")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vextractf128, IMM1 = 1)
)]
#[cfg_attr(test, assert_instr(vextractf128, IMM1 = 1))]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm256_extracti128_si256<const IMM1: i32>(a: __m256i) -> __m128i {
@ -1781,10 +1778,7 @@ pub unsafe fn _mm256_mask_i64gather_pd<const SCALE: i32>(
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_inserti128_si256)
#[inline]
#[target_feature(enable = "avx2")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vinsertf128, IMM1 = 1)
)]
#[cfg_attr(test, assert_instr(vinsertf128, IMM1 = 1))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm256_inserti128_si256<const IMM1: i32>(a: __m256i, b: __m128i) -> __m256i {

104
library/stdarch/crates/core_arch/src/x86/avx512f.rs
View file

@ -24813,10 +24813,7 @@ pub fn _mm256_maskz_shuffle_f64x2<const MASK: i32>(k: __mmask8, a: __m256d, b: _
#[inline]
#[target_feature(enable = "avx512f")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vextractf32x4, IMM8 = 3)
)]
#[cfg_attr(test, assert_instr(vextractf32x4, IMM8 = 3))]
#[rustc_legacy_const_generics(1)]
pub fn _mm512_extractf32x4_ps<const IMM8: i32>(a: __m512) -> __m128 {
unsafe {
@ -24836,10 +24833,7 @@ pub fn _mm512_extractf32x4_ps<const IMM8: i32>(a: __m512) -> __m128 {
#[inline]
#[target_feature(enable = "avx512f")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vextractf32x4, IMM8 = 3)
)]
#[cfg_attr(test, assert_instr(vextractf32x4, IMM8 = 3))]
#[rustc_legacy_const_generics(3)]
pub fn _mm512_mask_extractf32x4_ps<const IMM8: i32>(src: __m128, k: __mmask8, a: __m512) -> __m128 {
unsafe {
@ -24855,10 +24849,7 @@ pub fn _mm512_mask_extractf32x4_ps<const IMM8: i32>(src: __m128, k: __mmask8, a:
#[inline]
#[target_feature(enable = "avx512f")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vextractf32x4, IMM8 = 3)
)]
#[cfg_attr(test, assert_instr(vextractf32x4, IMM8 = 3))]
#[rustc_legacy_const_generics(2)]
pub fn _mm512_maskz_extractf32x4_ps<const IMM8: i32>(k: __mmask8, a: __m512) -> __m128 {
unsafe {
@ -24875,7 +24866,7 @@ pub fn _mm512_maskz_extractf32x4_ps<const IMM8: i32>(k: __mmask8, a: __m512) ->
#[target_feature(enable = "avx512f,avx512vl")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
test,
assert_instr(vextract, IMM8 = 1) //should be vextractf32x4
)]
#[rustc_legacy_const_generics(1)]
@ -24895,10 +24886,7 @@ pub fn _mm256_extractf32x4_ps<const IMM8: i32>(a: __m256) -> __m128 {
#[inline]
#[target_feature(enable = "avx512f,avx512vl")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vextractf32x4, IMM8 = 1)
)]
#[cfg_attr(test, assert_instr(vextractf32x4, IMM8 = 1))]
#[rustc_legacy_const_generics(3)]
pub fn _mm256_mask_extractf32x4_ps<const IMM8: i32>(src: __m128, k: __mmask8, a: __m256) -> __m128 {
unsafe {
@ -24914,10 +24902,7 @@ pub fn _mm256_mask_extractf32x4_ps<const IMM8: i32>(src: __m128, k: __mmask8, a:
#[inline]
#[target_feature(enable = "avx512f,avx512vl")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vextractf32x4, IMM8 = 1)
)]
#[cfg_attr(test, assert_instr(vextractf32x4, IMM8 = 1))]
#[rustc_legacy_const_generics(2)]
pub fn _mm256_maskz_extractf32x4_ps<const IMM8: i32>(k: __mmask8, a: __m256) -> __m128 {
unsafe {
@ -24934,7 +24919,7 @@ pub fn _mm256_maskz_extractf32x4_ps<const IMM8: i32>(k: __mmask8, a: __m256) ->
#[target_feature(enable = "avx512f")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
test,
assert_instr(vextractf64x4, IMM1 = 1) //should be vextracti64x4
)]
#[rustc_legacy_const_generics(1)]
@ -24954,10 +24939,7 @@ pub fn _mm512_extracti64x4_epi64<const IMM1: i32>(a: __m512i) -> __m256i {
#[inline]
#[target_feature(enable = "avx512f")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vextracti64x4, IMM1 = 1)
)]
#[cfg_attr(test, assert_instr(vextracti64x4, IMM1 = 1))]
#[rustc_legacy_const_generics(3)]
pub fn _mm512_mask_extracti64x4_epi64<const IMM1: i32>(
src: __m256i,
@ -24977,10 +24959,7 @@ pub fn _mm512_mask_extracti64x4_epi64<const IMM1: i32>(
#[inline]
#[target_feature(enable = "avx512f")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vextracti64x4, IMM1 = 1)
)]
#[cfg_attr(test, assert_instr(vextracti64x4, IMM1 = 1))]
#[rustc_legacy_const_generics(2)]
pub fn _mm512_maskz_extracti64x4_epi64<const IMM1: i32>(k: __mmask8, a: __m512i) -> __m256i {
unsafe {
@ -24996,10 +24975,7 @@ pub fn _mm512_maskz_extracti64x4_epi64<const IMM1: i32>(k: __mmask8, a: __m512i)
#[inline]
#[target_feature(enable = "avx512f")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vextractf64x4, IMM8 = 1)
)]
#[cfg_attr(test, assert_instr(vextractf64x4, IMM8 = 1))]
#[rustc_legacy_const_generics(1)]
pub fn _mm512_extractf64x4_pd<const IMM8: i32>(a: __m512d) -> __m256d {
unsafe {
@ -25017,10 +24993,7 @@ pub fn _mm512_extractf64x4_pd<const IMM8: i32>(a: __m512d) -> __m256d {
#[inline]
#[target_feature(enable = "avx512f")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vextractf64x4, IMM8 = 1)
)]
#[cfg_attr(test, assert_instr(vextractf64x4, IMM8 = 1))]
#[rustc_legacy_const_generics(3)]
pub fn _mm512_mask_extractf64x4_pd<const IMM8: i32>(
src: __m256d,
@ -25040,10 +25013,7 @@ pub fn _mm512_mask_extractf64x4_pd<const IMM8: i32>(
#[inline]
#[target_feature(enable = "avx512f")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vextractf64x4, IMM8 = 1)
)]
#[cfg_attr(test, assert_instr(vextractf64x4, IMM8 = 1))]
#[rustc_legacy_const_generics(2)]
pub fn _mm512_maskz_extractf64x4_pd<const IMM8: i32>(k: __mmask8, a: __m512d) -> __m256d {
unsafe {
@ -25060,7 +25030,7 @@ pub fn _mm512_maskz_extractf64x4_pd<const IMM8: i32>(k: __mmask8, a: __m512d) ->
#[target_feature(enable = "avx512f")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
test,
assert_instr(vextractf32x4, IMM2 = 3) //should be vextracti32x4
)]
#[rustc_legacy_const_generics(1)]
@ -25085,10 +25055,7 @@ pub fn _mm512_extracti32x4_epi32<const IMM2: i32>(a: __m512i) -> __m128i {
#[inline]
#[target_feature(enable = "avx512f")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vextracti32x4, IMM2 = 3)
)]
#[cfg_attr(test, assert_instr(vextracti32x4, IMM2 = 3))]
#[rustc_legacy_const_generics(3)]
pub fn _mm512_mask_extracti32x4_epi32<const IMM2: i32>(
src: __m128i,
@ -25108,10 +25075,7 @@ pub fn _mm512_mask_extracti32x4_epi32<const IMM2: i32>(
#[inline]
#[target_feature(enable = "avx512f")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vextracti32x4, IMM2 = 3)
)]
#[cfg_attr(test, assert_instr(vextracti32x4, IMM2 = 3))]
#[rustc_legacy_const_generics(2)]
pub fn _mm512_maskz_extracti32x4_epi32<const IMM2: i32>(k: __mmask8, a: __m512i) -> __m128i {
unsafe {
@ -25128,7 +25092,7 @@ pub fn _mm512_maskz_extracti32x4_epi32<const IMM2: i32>(k: __mmask8, a: __m512i)
#[target_feature(enable = "avx512f,avx512vl")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
test,
assert_instr(vextract, IMM1 = 1) //should be vextracti32x4
)]
#[rustc_legacy_const_generics(1)]
@ -25151,10 +25115,7 @@ pub fn _mm256_extracti32x4_epi32<const IMM1: i32>(a: __m256i) -> __m128i {
#[inline]
#[target_feature(enable = "avx512f,avx512vl")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vextracti32x4, IMM1 = 1)
)]
#[cfg_attr(test, assert_instr(vextracti32x4, IMM1 = 1))]
#[rustc_legacy_const_generics(3)]
pub fn _mm256_mask_extracti32x4_epi32<const IMM1: i32>(
src: __m128i,
@ -25174,10 +25135,7 @@ pub fn _mm256_mask_extracti32x4_epi32<const IMM1: i32>(
#[inline]
#[target_feature(enable = "avx512f,avx512vl")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vextracti32x4, IMM1 = 1)
)]
#[cfg_attr(test, assert_instr(vextracti32x4, IMM1 = 1))]
#[rustc_legacy_const_generics(2)]
pub fn _mm256_maskz_extracti32x4_epi32<const IMM1: i32>(k: __mmask8, a: __m256i) -> __m128i {
unsafe {
@ -25572,7 +25530,7 @@ pub fn _mm512_maskz_inserti32x4<const IMM8: i32>(k: __mmask16, a: __m512i, b: __
#[target_feature(enable = "avx512f,avx512vl")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
test,
assert_instr(vinsert, IMM8 = 1) //should be vinserti32x4
)]
#[rustc_legacy_const_generics(2)]
@ -25595,10 +25553,7 @@ pub fn _mm256_inserti32x4<const IMM8: i32>(a: __m256i, b: __m128i) -> __m256i {
#[inline]
#[target_feature(enable = "avx512f,avx512vl")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vinserti32x4, IMM8 = 1)
)]
#[cfg_attr(test, assert_instr(vinserti32x4, IMM8 = 1))]
#[rustc_legacy_const_generics(4)]
pub fn _mm256_mask_inserti32x4<const IMM8: i32>(
src: __m256i,
@ -25619,10 +25574,7 @@ pub fn _mm256_mask_inserti32x4<const IMM8: i32>(
#[inline]
#[target_feature(enable = "avx512f,avx512vl")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vinserti32x4, IMM8 = 1)
)]
#[cfg_attr(test, assert_instr(vinserti32x4, IMM8 = 1))]
#[rustc_legacy_const_generics(3)]
pub fn _mm256_maskz_inserti32x4<const IMM8: i32>(k: __mmask8, a: __m256i, b: __m128i) -> __m256i {
unsafe {
@ -25773,7 +25725,7 @@ pub fn _mm512_maskz_insertf32x4<const IMM8: i32>(k: __mmask16, a: __m512, b: __m
#[target_feature(enable = "avx512f,avx512vl")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
test,
assert_instr(vinsert, IMM8 = 1) //should be vinsertf32x4
)]
#[rustc_legacy_const_generics(2)]
@ -25794,10 +25746,7 @@ pub fn _mm256_insertf32x4<const IMM8: i32>(a: __m256, b: __m128) -> __m256 {
#[inline]
#[target_feature(enable = "avx512f,avx512vl")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vinsertf32x4, IMM8 = 1)
)]
#[cfg_attr(test, assert_instr(vinsertf32x4, IMM8 = 1))]
#[rustc_legacy_const_generics(4)]
pub fn _mm256_mask_insertf32x4<const IMM8: i32>(
src: __m256,
@ -25818,10 +25767,7 @@ pub fn _mm256_mask_insertf32x4<const IMM8: i32>(
#[inline]
#[target_feature(enable = "avx512f,avx512vl")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, not(target_env = "msvc")),
assert_instr(vinsertf32x4, IMM8 = 1)
)]
#[cfg_attr(test, assert_instr(vinsertf32x4, IMM8 = 1))]
#[rustc_legacy_const_generics(3)]
pub fn _mm256_maskz_insertf32x4<const IMM8: i32>(k: __mmask8, a: __m256, b: __m128) -> __m256 {
unsafe {
@ -26958,7 +26904,7 @@ pub fn _mm512_castsi512_pd(a: __m512i) -> __m512d {
#[inline]
#[target_feature(enable = "avx512f")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovd))]
#[cfg_attr(test, assert_instr(vmovd))]
pub fn _mm512_cvtsi512_si32(a: __m512i) -> i32 {
unsafe { simd_extract!(a.as_i32x16(), 0) }
}

20
library/stdarch/crates/core_arch/src/x86/avx512ifma.rs
View file

@ -108,10 +108,7 @@ pub fn _mm512_maskz_madd52lo_epu64(k: __mmask8, a: __m512i, b: __m512i, c: __m51
#[inline]
#[target_feature(enable = "avxifma")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpmadd52huq)
)]
#[cfg_attr(test, assert_instr(vpmadd52huq))]
pub fn _mm256_madd52hi_avx_epu64(a: __m256i, b: __m256i, c: __m256i) -> __m256i {
unsafe { vpmadd52huq_256(a, b, c) }
}
@ -173,10 +170,7 @@ pub fn _mm256_maskz_madd52hi_epu64(k: __mmask8, a: __m256i, b: __m256i, c: __m25
#[inline]
#[target_feature(enable = "avxifma")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpmadd52luq)
)]
#[cfg_attr(test, assert_instr(vpmadd52luq))]
pub fn _mm256_madd52lo_avx_epu64(a: __m256i, b: __m256i, c: __m256i) -> __m256i {
unsafe { vpmadd52luq_256(a, b, c) }
}
@ -238,10 +232,7 @@ pub fn _mm256_maskz_madd52lo_epu64(k: __mmask8, a: __m256i, b: __m256i, c: __m25
#[inline]
#[target_feature(enable = "avxifma")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpmadd52huq)
)]
#[cfg_attr(test, assert_instr(vpmadd52huq))]
pub fn _mm_madd52hi_avx_epu64(a: __m128i, b: __m128i, c: __m128i) -> __m128i {
unsafe { vpmadd52huq_128(a, b, c) }
}
@ -303,10 +294,7 @@ pub fn _mm_maskz_madd52hi_epu64(k: __mmask8, a: __m128i, b: __m128i, c: __m128i)
#[inline]
#[target_feature(enable = "avxifma")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpmadd52luq)
)]
#[cfg_attr(test, assert_instr(vpmadd52luq))]
pub fn _mm_madd52lo_avx_epu64(a: __m128i, b: __m128i, c: __m128i) -> __m128i {
unsafe { vpmadd52luq_128(a, b, c) }
}

160
library/stdarch/crates/core_arch/src/x86/avx512vnni.rs
View file

@ -49,10 +49,7 @@ pub fn _mm512_maskz_dpwssd_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m5
#[inline]
#[target_feature(enable = "avxvnni")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpwssd)
)]
#[cfg_attr(test, assert_instr(vpdpwssd))]
pub fn _mm256_dpwssd_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
unsafe { transmute(vpdpwssd256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
}
@ -102,10 +99,7 @@ pub fn _mm256_maskz_dpwssd_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m25
#[inline]
#[target_feature(enable = "avxvnni")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpwssd)
)]
#[cfg_attr(test, assert_instr(vpdpwssd))]
pub fn _mm_dpwssd_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
unsafe { transmute(vpdpwssd128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
}
@ -194,10 +188,7 @@ pub fn _mm512_maskz_dpwssds_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m
#[inline]
#[target_feature(enable = "avxvnni")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpwssds)
)]
#[cfg_attr(test, assert_instr(vpdpwssds))]
pub fn _mm256_dpwssds_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
unsafe { transmute(vpdpwssds256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
}
@ -247,10 +238,7 @@ pub fn _mm256_maskz_dpwssds_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m2
#[inline]
#[target_feature(enable = "avxvnni")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpwssds)
)]
#[cfg_attr(test, assert_instr(vpdpwssds))]
pub fn _mm_dpwssds_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
unsafe { transmute(vpdpwssds128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
}
@ -339,10 +327,7 @@ pub fn _mm512_maskz_dpbusd_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m5
#[inline]
#[target_feature(enable = "avxvnni")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpbusd)
)]
#[cfg_attr(test, assert_instr(vpdpbusd))]
pub fn _mm256_dpbusd_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
unsafe { transmute(vpdpbusd256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
}
@ -392,10 +377,7 @@ pub fn _mm256_maskz_dpbusd_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m25
#[inline]
#[target_feature(enable = "avxvnni")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpbusd)
)]
#[cfg_attr(test, assert_instr(vpdpbusd))]
pub fn _mm_dpbusd_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
unsafe { transmute(vpdpbusd128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
}
@ -484,10 +466,7 @@ pub fn _mm512_maskz_dpbusds_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m
#[inline]
#[target_feature(enable = "avxvnni")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpbusds)
)]
#[cfg_attr(test, assert_instr(vpdpbusds))]
pub fn _mm256_dpbusds_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
unsafe { transmute(vpdpbusds256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
}
@ -537,10 +516,7 @@ pub fn _mm256_maskz_dpbusds_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m2
#[inline]
#[target_feature(enable = "avxvnni")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpbusds)
)]
#[cfg_attr(test, assert_instr(vpdpbusds))]
pub fn _mm_dpbusds_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
unsafe { transmute(vpdpbusds128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
}
@ -591,10 +567,7 @@ pub fn _mm_maskz_dpbusds_epi32(k: __mmask8, src: __m128i, a: __m128i, b: __m128i
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_dpbssd_epi32&expand=2674)
#[inline]
#[target_feature(enable = "avxvnniint8")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpbssd)
)]
#[cfg_attr(test, assert_instr(vpdpbssd))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm_dpbssd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
unsafe { transmute(vpdpbssd_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
@ -607,10 +580,7 @@ pub fn _mm_dpbssd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_dpbssd_epi32&expand=2675)
#[inline]
#[target_feature(enable = "avxvnniint8")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpbssd)
)]
#[cfg_attr(test, assert_instr(vpdpbssd))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm256_dpbssd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
unsafe { transmute(vpdpbssd_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
@ -623,10 +593,7 @@ pub fn _mm256_dpbssd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_dpbssds_epi32&expand=2676)
#[inline]
#[target_feature(enable = "avxvnniint8")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpbssds)
)]
#[cfg_attr(test, assert_instr(vpdpbssds))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm_dpbssds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
unsafe { transmute(vpdpbssds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
@ -639,10 +606,7 @@ pub fn _mm_dpbssds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_dpbssds_epi32&expand=2677)
#[inline]
#[target_feature(enable = "avxvnniint8")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpbssds)
)]
#[cfg_attr(test, assert_instr(vpdpbssds))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm256_dpbssds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
unsafe { transmute(vpdpbssds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
@ -655,10 +619,7 @@ pub fn _mm256_dpbssds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_dpbsud_epi32&expand=2678)
#[inline]
#[target_feature(enable = "avxvnniint8")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpbsud)
)]
#[cfg_attr(test, assert_instr(vpdpbsud))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm_dpbsud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
unsafe { transmute(vpdpbsud_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
@ -671,10 +632,7 @@ pub fn _mm_dpbsud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_dpbsud_epi32&expand=2679)
#[inline]
#[target_feature(enable = "avxvnniint8")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpbsud)
)]
#[cfg_attr(test, assert_instr(vpdpbsud))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm256_dpbsud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
unsafe { transmute(vpdpbsud_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
@ -687,10 +645,7 @@ pub fn _mm256_dpbsud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_dpbsuds_epi32&expand=2680)
#[inline]
#[target_feature(enable = "avxvnniint8")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpbsuds)
)]
#[cfg_attr(test, assert_instr(vpdpbsuds))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm_dpbsuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
unsafe { transmute(vpdpbsuds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
@ -703,10 +658,7 @@ pub fn _mm_dpbsuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_dpbsuds_epi32&expand=2681)
#[inline]
#[target_feature(enable = "avxvnniint8")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpbsuds)
)]
#[cfg_attr(test, assert_instr(vpdpbsuds))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm256_dpbsuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
unsafe { transmute(vpdpbsuds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
@ -719,10 +671,7 @@ pub fn _mm256_dpbsuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_dpbuud_epi32&expand=2708)
#[inline]
#[target_feature(enable = "avxvnniint8")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpbuud)
)]
#[cfg_attr(test, assert_instr(vpdpbuud))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm_dpbuud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
unsafe { transmute(vpdpbuud_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
@ -735,10 +684,7 @@ pub fn _mm_dpbuud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_dpbuud_epi32&expand=2709)
#[inline]
#[target_feature(enable = "avxvnniint8")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpbuud)
)]
#[cfg_attr(test, assert_instr(vpdpbuud))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm256_dpbuud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
unsafe { transmute(vpdpbuud_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
@ -751,10 +697,7 @@ pub fn _mm256_dpbuud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_dpbuuds_epi32&expand=2710)
#[inline]
#[target_feature(enable = "avxvnniint8")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpbuuds)
)]
#[cfg_attr(test, assert_instr(vpdpbuuds))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm_dpbuuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
unsafe { transmute(vpdpbuuds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
@ -767,10 +710,7 @@ pub fn _mm_dpbuuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_dpbuuds_epi32&expand=2711)
#[inline]
#[target_feature(enable = "avxvnniint8")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpbuuds)
)]
#[cfg_attr(test, assert_instr(vpdpbuuds))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm256_dpbuuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
unsafe { transmute(vpdpbuuds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
@ -783,10 +723,7 @@ pub fn _mm256_dpbuuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_dpwsud_epi32&expand=2738)
#[inline]
#[target_feature(enable = "avxvnniint16")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpwsud)
)]
#[cfg_attr(test, assert_instr(vpdpwsud))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm_dpwsud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
unsafe { transmute(vpdpwsud_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
@ -799,10 +736,7 @@ pub fn _mm_dpwsud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_dpwsud_epi32&expand=2739)
#[inline]
#[target_feature(enable = "avxvnniint16")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpwsud)
)]
#[cfg_attr(test, assert_instr(vpdpwsud))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm256_dpwsud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
unsafe { transmute(vpdpwsud_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
@ -815,10 +749,7 @@ pub fn _mm256_dpwsud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_dpwsuds_epi32&expand=2740)
#[inline]
#[target_feature(enable = "avxvnniint16")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpwsuds)
)]
#[cfg_attr(test, assert_instr(vpdpwsuds))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm_dpwsuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
unsafe { transmute(vpdpwsuds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
@ -831,10 +762,7 @@ pub fn _mm_dpwsuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_dpwsuds_epi32&expand=2741)
#[inline]
#[target_feature(enable = "avxvnniint16")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpwsuds)
)]
#[cfg_attr(test, assert_instr(vpdpwsuds))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm256_dpwsuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
unsafe { transmute(vpdpwsuds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
@ -847,10 +775,7 @@ pub fn _mm256_dpwsuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_dpwusd_epi32&expand=2742)
#[inline]
#[target_feature(enable = "avxvnniint16")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpwusd)
)]
#[cfg_attr(test, assert_instr(vpdpwusd))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm_dpwusd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
unsafe { transmute(vpdpwusd_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
@ -863,10 +788,7 @@ pub fn _mm_dpwusd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_dpwusd_epi32&expand=2743)
#[inline]
#[target_feature(enable = "avxvnniint16")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpwusd)
)]
#[cfg_attr(test, assert_instr(vpdpwusd))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm256_dpwusd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
unsafe { transmute(vpdpwusd_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
@ -879,10 +801,7 @@ pub fn _mm256_dpwusd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_dpwusds_epi32&expand=2744)
#[inline]
#[target_feature(enable = "avxvnniint16")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpwusds)
)]
#[cfg_attr(test, assert_instr(vpdpwusds))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm_dpwusds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
unsafe { transmute(vpdpwusds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
@ -895,10 +814,7 @@ pub fn _mm_dpwusds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_dpwusds_epi32&expand=2745)
#[inline]
#[target_feature(enable = "avxvnniint16")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpwusds)
)]
#[cfg_attr(test, assert_instr(vpdpwusds))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm256_dpwusds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
unsafe { transmute(vpdpwusds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
@ -911,10 +827,7 @@ pub fn _mm256_dpwusds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_dpwuud_epi32&expand=2746)
#[inline]
#[target_feature(enable = "avxvnniint16")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpwuud)
)]
#[cfg_attr(test, assert_instr(vpdpwuud))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm_dpwuud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
unsafe { transmute(vpdpwuud_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
@ -927,10 +840,7 @@ pub fn _mm_dpwuud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_dpwuud_epi32&expand=2747)
#[inline]
#[target_feature(enable = "avxvnniint16")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpwuud)
)]
#[cfg_attr(test, assert_instr(vpdpwuud))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm256_dpwuud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
unsafe { transmute(vpdpwuud_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }
@ -943,10 +853,7 @@ pub fn _mm256_dpwuud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_dpwuuds_epi32&expand=2748)
#[inline]
#[target_feature(enable = "avxvnniint16")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpwuuds)
)]
#[cfg_attr(test, assert_instr(vpdpwuuds))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm_dpwuuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
unsafe { transmute(vpdpwuuds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) }
@ -959,10 +866,7 @@ pub fn _mm_dpwuuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_dpwuuds_epi32&expand=2749)
#[inline]
#[target_feature(enable = "avxvnniint16")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vpdpwuuds)
)]
#[cfg_attr(test, assert_instr(vpdpwuuds))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm256_dpwuuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i {
unsafe { transmute(vpdpwuuds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) }

70
library/stdarch/crates/core_arch/src/x86/avxneconvert.rs
View file

@ -11,10 +11,7 @@ use stdarch_test::assert_instr;
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_bcstnebf16_ps)
#[inline]
#[target_feature(enable = "avxneconvert")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vbcstnebf162ps)
)]
#[cfg_attr(test, assert_instr(vbcstnebf162ps))]
#[unstable(feature = "stdarch_x86_avx512_bf16", issue = "127356")]
pub unsafe fn _mm_bcstnebf16_ps(a: *const bf16) -> __m128 {
bcstnebf162ps_128(a)
@ -27,10 +24,7 @@ pub unsafe fn _mm_bcstnebf16_ps(a: *const bf16) -> __m128 {
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_bcstnebf16_ps)
#[inline]
#[target_feature(enable = "avxneconvert")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vbcstnebf162ps)
)]
#[cfg_attr(test, assert_instr(vbcstnebf162ps))]
#[unstable(feature = "stdarch_x86_avx512_bf16", issue = "127356")]
pub unsafe fn _mm256_bcstnebf16_ps(a: *const bf16) -> __m256 {
bcstnebf162ps_256(a)
@ -43,10 +37,7 @@ pub unsafe fn _mm256_bcstnebf16_ps(a: *const bf16) -> __m256 {
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_bcstnesh_ps)
#[inline]
#[target_feature(enable = "avxneconvert")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vbcstnesh2ps)
)]
#[cfg_attr(test, assert_instr(vbcstnesh2ps))]
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
pub unsafe fn _mm_bcstnesh_ps(a: *const f16) -> __m128 {
bcstnesh2ps_128(a)
@ -59,10 +50,7 @@ pub unsafe fn _mm_bcstnesh_ps(a: *const f16) -> __m128 {
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_bcstnesh_ps)
#[inline]
#[target_feature(enable = "avxneconvert")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vbcstnesh2ps)
)]
#[cfg_attr(test, assert_instr(vbcstnesh2ps))]
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
pub unsafe fn _mm256_bcstnesh_ps(a: *const f16) -> __m256 {
bcstnesh2ps_256(a)
@ -74,10 +62,7 @@ pub unsafe fn _mm256_bcstnesh_ps(a: *const f16) -> __m256 {
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtneebf16_ps)
#[inline]
#[target_feature(enable = "avxneconvert")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vcvtneebf162ps)
)]
#[cfg_attr(test, assert_instr(vcvtneebf162ps))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub unsafe fn _mm_cvtneebf16_ps(a: *const __m128bh) -> __m128 {
transmute(cvtneebf162ps_128(a))
@ -89,10 +74,7 @@ pub unsafe fn _mm_cvtneebf16_ps(a: *const __m128bh) -> __m128 {
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtneebf16_ps)
#[inline]
#[target_feature(enable = "avxneconvert")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vcvtneebf162ps)
)]
#[cfg_attr(test, assert_instr(vcvtneebf162ps))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub unsafe fn _mm256_cvtneebf16_ps(a: *const __m256bh) -> __m256 {
transmute(cvtneebf162ps_256(a))
@ -104,10 +86,7 @@ pub unsafe fn _mm256_cvtneebf16_ps(a: *const __m256bh) -> __m256 {
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtneeph_ps)
#[inline]
#[target_feature(enable = "avxneconvert")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vcvtneeph2ps)
)]
#[cfg_attr(test, assert_instr(vcvtneeph2ps))]
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
pub unsafe fn _mm_cvtneeph_ps(a: *const __m128h) -> __m128 {
transmute(cvtneeph2ps_128(a))
@ -119,10 +98,7 @@ pub unsafe fn _mm_cvtneeph_ps(a: *const __m128h) -> __m128 {
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtneeph_ps)
#[inline]
#[target_feature(enable = "avxneconvert")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vcvtneeph2ps)
)]
#[cfg_attr(test, assert_instr(vcvtneeph2ps))]
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
pub unsafe fn _mm256_cvtneeph_ps(a: *const __m256h) -> __m256 {
transmute(cvtneeph2ps_256(a))
@ -134,10 +110,7 @@ pub unsafe fn _mm256_cvtneeph_ps(a: *const __m256h) -> __m256 {
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtneobf16_ps)
#[inline]
#[target_feature(enable = "avxneconvert")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vcvtneobf162ps)
)]
#[cfg_attr(test, assert_instr(vcvtneobf162ps))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub unsafe fn _mm_cvtneobf16_ps(a: *const __m128bh) -> __m128 {
transmute(cvtneobf162ps_128(a))
@ -149,10 +122,7 @@ pub unsafe fn _mm_cvtneobf16_ps(a: *const __m128bh) -> __m128 {
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtneobf16_ps)
#[inline]
#[target_feature(enable = "avxneconvert")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vcvtneobf162ps)
)]
#[cfg_attr(test, assert_instr(vcvtneobf162ps))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub unsafe fn _mm256_cvtneobf16_ps(a: *const __m256bh) -> __m256 {
transmute(cvtneobf162ps_256(a))
@ -164,10 +134,7 @@ pub unsafe fn _mm256_cvtneobf16_ps(a: *const __m256bh) -> __m256 {
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtneoph_ps)
#[inline]
#[target_feature(enable = "avxneconvert")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vcvtneoph2ps)
)]
#[cfg_attr(test, assert_instr(vcvtneoph2ps))]
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
pub unsafe fn _mm_cvtneoph_ps(a: *const __m128h) -> __m128 {
transmute(cvtneoph2ps_128(a))
@ -179,10 +146,7 @@ pub unsafe fn _mm_cvtneoph_ps(a: *const __m128h) -> __m128 {
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtneoph_ps)
#[inline]
#[target_feature(enable = "avxneconvert")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vcvtneoph2ps)
)]
#[cfg_attr(test, assert_instr(vcvtneoph2ps))]
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
pub unsafe fn _mm256_cvtneoph_ps(a: *const __m256h) -> __m256 {
transmute(cvtneoph2ps_256(a))
@ -194,10 +158,7 @@ pub unsafe fn _mm256_cvtneoph_ps(a: *const __m256h) -> __m256 {
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtneps_avx_pbh)
#[inline]
#[target_feature(enable = "avxneconvert")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vcvtneps2bf16)
)]
#[cfg_attr(test, assert_instr(vcvtneps2bf16))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm_cvtneps_avx_pbh(a: __m128) -> __m128bh {
unsafe {
@ -218,10 +179,7 @@ pub fn _mm_cvtneps_avx_pbh(a: __m128) -> __m128bh {
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtneps_avx_pbh)
#[inline]
#[target_feature(enable = "avxneconvert")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(vcvtneps2bf16)
)]
#[cfg_attr(test, assert_instr(vcvtneps2bf16))]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub fn _mm256_cvtneps_avx_pbh(a: __m256) -> __m128bh {
unsafe {

4
library/stdarch/crates/core_arch/src/x86/sse.rs
View file

@ -1067,7 +1067,7 @@ pub fn _mm_unpacklo_ps(a: __m128, b: __m128) -> __m128 {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_movehl_ps)
#[inline]
#[target_feature(enable = "sse")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(movhlps))]
#[cfg_attr(test, assert_instr(movhlps))]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm_movehl_ps(a: __m128, b: __m128) -> __m128 {
// TODO; figure why this is a different instruction on msvc?
@ -1080,7 +1080,7 @@ pub fn _mm_movehl_ps(a: __m128, b: __m128) -> __m128 {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_movelh_ps)
#[inline]
#[target_feature(enable = "sse")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(movlhps))]
#[cfg_attr(test, assert_instr(movlhps))]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm_movelh_ps(a: __m128, b: __m128) -> __m128 {
unsafe { simd_shuffle!(a, b, [0, 1, 4, 5]) }

15
library/stdarch/crates/core_arch/src/x86/sse2.rs
View file

@ -1385,10 +1385,7 @@ pub unsafe fn _mm_stream_si32(mem_addr: *mut i32, a: i32) {
#[inline]
#[target_feature(enable = "sse2")]
// FIXME movd on msvc, movd on i686
#[cfg_attr(
all(test, not(target_env = "msvc"), target_arch = "x86_64"),
assert_instr(movq)
)]
#[cfg_attr(all(test, target_arch = "x86_64"), assert_instr(movq))]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm_move_epi64(a: __m128i) -> __m128i {
unsafe {
@ -1668,7 +1665,7 @@ pub fn _mm_unpacklo_epi32(a: __m128i, b: __m128i) -> __m128i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_unpacklo_epi64)
#[inline]
#[target_feature(enable = "sse2")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(movlhps))]
#[cfg_attr(test, assert_instr(movlhps))]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm_unpacklo_epi64(a: __m128i, b: __m128i) -> __m128i {
unsafe { transmute::<i64x2, _>(simd_shuffle!(a.as_i64x2(), b.as_i64x2(), [0, 2])) }
@ -2618,7 +2615,7 @@ pub unsafe fn _mm_stream_pd(mem_addr: *mut f64, a: __m128d) {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_store_sd)
#[inline]
#[target_feature(enable = "sse2")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(movlps))]
#[cfg_attr(test, assert_instr(movlps))]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub unsafe fn _mm_store_sd(mem_addr: *mut f64, a: __m128d) {
*mem_addr = simd_extract!(a, 0)
@ -2736,7 +2733,7 @@ pub unsafe fn _mm_storer_pd(mem_addr: *mut f64, a: __m128d) {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_storeh_pd)
#[inline]
#[target_feature(enable = "sse2")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(movhps))]
#[cfg_attr(test, assert_instr(movhps))]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub unsafe fn _mm_storeh_pd(mem_addr: *mut f64, a: __m128d) {
*mem_addr = simd_extract!(a, 1);
@ -2748,7 +2745,7 @@ pub unsafe fn _mm_storeh_pd(mem_addr: *mut f64, a: __m128d) {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_storel_pd)
#[inline]
#[target_feature(enable = "sse2")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(movlps))]
#[cfg_attr(test, assert_instr(movlps))]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub unsafe fn _mm_storel_pd(mem_addr: *mut f64, a: __m128d) {
*mem_addr = simd_extract!(a, 0);
@ -3006,7 +3003,7 @@ pub fn _mm_unpackhi_pd(a: __m128d, b: __m128d) -> __m128d {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_unpacklo_pd)
#[inline]
#[target_feature(enable = "sse2")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(movlhps))]
#[cfg_attr(test, assert_instr(movlhps))]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm_unpacklo_pd(a: __m128d, b: __m128d) -> __m128d {
unsafe { simd_shuffle!(a, b, [0, 2]) }

4
library/stdarch/crates/core_arch/src/x86/sse41.rs
View file

@ -204,7 +204,7 @@ pub fn _mm_blend_ps<const IMM4: i32>(a: __m128, b: __m128) -> __m128 {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_extract_ps)
#[inline]
#[target_feature(enable = "sse4.1")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(extractps, IMM8 = 0))]
#[cfg_attr(test, assert_instr(extractps, IMM8 = 0))]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm_extract_ps<const IMM8: i32>(a: __m128) -> i32 {
@ -233,7 +233,7 @@ pub fn _mm_extract_epi8<const IMM8: i32>(a: __m128i) -> i32 {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_extract_epi32)
#[inline]
#[target_feature(enable = "sse4.1")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(extractps, IMM8 = 1))]
#[cfg_attr(test, assert_instr(extractps, IMM8 = 1))]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm_extract_epi32<const IMM8: i32>(a: __m128i) -> i32 {

15
library/stdarch/crates/core_arch/src/x86_64/amx.rs
View file

@ -191,10 +191,7 @@ pub unsafe fn _tile_dpbuud<const DST: i32, const A: i32, const B: i32>() {
#[inline]
#[rustc_legacy_const_generics(0, 1, 2)]
#[target_feature(enable = "amx-fp16")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(tdpfp16ps, DST = 0, A = 1, B = 2)
)]
#[cfg_attr(test, assert_instr(tdpfp16ps, DST = 0, A = 1, B = 2))]
#[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
pub unsafe fn _tile_dpfp16ps<const DST: i32, const A: i32, const B: i32>() {
static_assert_uimm_bits!(DST, 3);
@ -215,10 +212,7 @@ pub unsafe fn _tile_dpfp16ps<const DST: i32, const A: i32, const B: i32>() {
#[inline]
#[rustc_legacy_const_generics(0, 1, 2)]
#[target_feature(enable = "amx-complex")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(tcmmimfp16ps, DST = 0, A = 1, B = 2)
)]
#[cfg_attr(test, assert_instr(tcmmimfp16ps, DST = 0, A = 1, B = 2))]
#[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
pub unsafe fn _tile_cmmimfp16ps<const DST: i32, const A: i32, const B: i32>() {
static_assert_uimm_bits!(DST, 3);
@ -239,10 +233,7 @@ pub unsafe fn _tile_cmmimfp16ps<const DST: i32, const A: i32, const B: i32>() {
#[inline]
#[rustc_legacy_const_generics(0, 1, 2)]
#[target_feature(enable = "amx-complex")]
#[cfg_attr(
all(test, any(target_os = "linux", target_env = "msvc")),
assert_instr(tcmmrlfp16ps, DST = 0, A = 1, B = 2)
)]
#[cfg_attr(test, assert_instr(tcmmrlfp16ps, DST = 0, A = 1, B = 2))]
#[unstable(feature = "x86_amx_intrinsics", issue = "126622")]
pub unsafe fn _tile_cmmrlfp16ps<const DST: i32, const A: i32, const B: i32>() {
static_assert_uimm_bits!(DST, 3);

8
library/stdarch/crates/core_arch/src/x86_64/sse2.rs
View file

@ -92,7 +92,7 @@ pub unsafe fn _mm_stream_si64(mem_addr: *mut i64, a: i64) {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsi64_si128)
#[inline]
#[target_feature(enable = "sse2")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(movq))]
#[cfg_attr(test, assert_instr(movq))]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm_cvtsi64_si128(a: i64) -> __m128i {
_mm_set_epi64x(0, a)
@ -104,7 +104,7 @@ pub fn _mm_cvtsi64_si128(a: i64) -> __m128i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsi64x_si128)
#[inline]
#[target_feature(enable = "sse2")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(movq))]
#[cfg_attr(test, assert_instr(movq))]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm_cvtsi64x_si128(a: i64) -> __m128i {
_mm_cvtsi64_si128(a)
@ -115,7 +115,7 @@ pub fn _mm_cvtsi64x_si128(a: i64) -> __m128i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsi128_si64)
#[inline]
#[target_feature(enable = "sse2")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(movq))]
#[cfg_attr(test, assert_instr(movq))]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm_cvtsi128_si64(a: __m128i) -> i64 {
unsafe { simd_extract!(a.as_i64x2(), 0) }
@ -126,7 +126,7 @@ pub fn _mm_cvtsi128_si64(a: __m128i) -> i64 {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsi128_si64x)
#[inline]
#[target_feature(enable = "sse2")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(movq))]
#[cfg_attr(test, assert_instr(movq))]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm_cvtsi128_si64x(a: __m128i) -> i64 {
_mm_cvtsi128_si64(a)

2
library/stdarch/crates/core_arch/src/x86_64/sse41.rs
View file

@ -10,7 +10,7 @@ use stdarch_test::assert_instr;
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_extract_epi64)
#[inline]
#[target_feature(enable = "sse4.1")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(pextrq, IMM1 = 1))]
#[cfg_attr(test, assert_instr(pextrq, IMM1 = 1))]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm_extract_epi64<const IMM1: i32>(a: __m128i) -> i64 {