From 746ab07521782afa370dfe89d52f8483e924bb4e Mon Sep 17 00:00:00 2001
From: Alex Crichton <alex@alexcrichton.com>
Date: Sun, 25 Feb 2018 12:37:08 -0600
Subject: [PATCH] Compile examples on CI (#329)

Make sure the top-level `examples` folder is registered with the
`stdsimd` crate!
---
 library/stdarch/crates/stdsimd/Cargo.toml |  8 ++++++++
 library/stdarch/examples/hex.rs           | 17 ++++++++---------
 library/stdarch/examples/nbody.rs         | 15 +++++++++++----
 3 files changed, 27 insertions(+), 13 deletions(-)

diff --git a/library/stdarch/crates/stdsimd/Cargo.toml b/library/stdarch/crates/stdsimd/Cargo.toml
index ac6843a6ba2d..c64dd48f1046 100644
--- a/library/stdarch/crates/stdsimd/Cargo.toml
+++ b/library/stdarch/crates/stdsimd/Cargo.toml
@@ -35,3 +35,11 @@ strict = [ "coresimd/strict" ]
 # Internal-usage only: enables only those intrinsics supported by Intel's
 # Software Development Environment (SDE).
 intel_sde = [ "coresimd/intel_sde" ]
+
+[[example]]
+name = "hex"
+path = "../../examples/hex.rs"
+
+[[example]]
+name = "nbody"
+path = "../../examples/nbody.rs"
diff --git a/library/stdarch/examples/hex.rs b/library/stdarch/examples/hex.rs
index 02be9c71e52f..6a0d4c1135f0 100644
--- a/library/stdarch/examples/hex.rs
+++ b/library/stdarch/examples/hex.rs
@@ -8,16 +8,12 @@
 //!
 //! You can test out this program via:
 //!
-//!     echo test | cargo +nightly run --release --example hex
+//!     echo test | cargo +nightly run --release --example hex -p stdsimd
 //!
 //! and you should see `746573740a` get printed out.
 
-#![feature(cfg_target_feature, target_feature)]
+#![feature(cfg_target_feature, target_feature, stdsimd)]
 #![cfg_attr(test, feature(test))]
-#![cfg_attr(feature = "cargo-clippy",
-            allow(result_unwrap_used, option_unwrap_used, print_stdout,
-                  missing_docs_in_private_items, shadow_reuse,
-                  cast_possible_wrap, cast_sign_loss))]
 
 #[macro_use]
 extern crate stdsimd;
@@ -29,7 +25,10 @@ extern crate quickcheck;
 use std::str;
 use std::io::{self, Read};
 
-use stdsimd::vendor::*;
+#[cfg(target_arch = "x86")]
+use stdsimd::arch::x86::*;
+#[cfg(target_arch = "x86_64")]
+use stdsimd::arch::x86_64::*;
 
 fn main() {
     let mut input = Vec::new();
@@ -175,7 +174,7 @@ fn hex_encode_fallback<'a>(
     unsafe { Ok(str::from_utf8_unchecked(&dst[..src.len() * 2])) }
 }
 
-// Run these with `cargo +nightly test --example hex`
+// Run these with `cargo +nightly test --example hex -p stdsimd`
 #[cfg(test)]
 mod tests {
     use std::iter;
@@ -281,7 +280,7 @@ mod tests {
     }
 }
 
-// Run these with `cargo +nightly bench --example hex`
+// Run these with `cargo +nightly bench --example hex -p stdsimd`
 #[cfg(test)]
 mod benches {
     extern crate rand;
diff --git a/library/stdarch/examples/nbody.rs b/library/stdarch/examples/nbody.rs
index c83933a3259a..a8e192788853 100644
--- a/library/stdarch/examples/nbody.rs
+++ b/library/stdarch/examples/nbody.rs
@@ -4,7 +4,7 @@
 //! html#nbody
 
 #![cfg_attr(feature = "strict", deny(warnings))]
-#![feature(cfg_target_feature)]
+#![feature(cfg_target_feature, stdsimd)]
 #![feature(target_feature)]
 #![cfg_attr(feature = "cargo-clippy",
             allow(similar_names, missing_docs_in_private_items,
@@ -27,7 +27,10 @@ impl Frsqrt for f64x2 {
         #[cfg(all(any(target_arch = "x86", target_arch = "x86_64"),
                   target_feature = "sse"))]
         {
-            use stdsimd::vendor::*;
+            #[cfg(target_arch = "x86")]
+            use stdsimd::arch::x86::*;
+            #[cfg(target_arch = "x86_64")]
+            use stdsimd::arch::x86_64::*;
 
             let t = self.as_f32x2();
 
@@ -45,8 +48,12 @@ impl Frsqrt for f64x2 {
         #[cfg(all(any(target_arch = "arm", target_arch = "aarch64"),
                   target_feature = "neon"))]
         {
-            use self::stdsimd::vendor;
-            unsafe { vendor::vrsqrte_f32(self.as_f32x2()).as_f64x2() }
+            #[cfg(target_arch = "arm")]
+            use stdsimd::arch::arm::*;
+            #[cfg(target_arch = "aarch64")]
+            use stdsimd::arch::aarch64::*;
+
+            unsafe { vrsqrte_f32(self.as_f32x2()).as_f64x2() }
         }
         #[cfg(not(any(all(any(target_arch = "x86",
                               target_arch = "x86_64"),