Add vset neon instructions
This commit is contained in:
SparrowLii
Amanieu d'Antras
parent
2d9b71bca6
commit
7516a80c31
3 changed files with 618 additions and 0 deletions
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@ -7602,6 +7602,26 @@ pub unsafe fn vrsrad_n_u64<const N: i32>(a: u64, b: u64) -> u64 {
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transmute(simd_add(transmute(a), b))
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vset_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> float64x1_t {
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static_assert!(LANE : i32 where LANE == 0);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vsetq_lane_f64<const LANE: i32>(a: f64, b: float64x2_t) -> float64x2_t {
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static_assert_imm1!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Signed Shift left
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#[inline]
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#[target_feature(enable = "neon")]
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@ -15111,6 +15131,24 @@ mod test {
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assert_eq!(r, e);
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}
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#[simd_test(enable = "neon")]
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unsafe fn test_vset_lane_f64() {
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let a: f64 = 1.;
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let b: f64 = 0.;
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let e: f64 = 1.;
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let r: f64 = transmute(vset_lane_f64::<0>(transmute(a), transmute(b)));
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assert_eq!(r, e);
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}
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#[simd_test(enable = "neon")]
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unsafe fn test_vsetq_lane_f64() {
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let a: f64 = 1.;
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let b: f64x2 = f64x2::new(0., 2.);
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let e: f64x2 = f64x2::new(1., 2.);
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let r: f64x2 = transmute(vsetq_lane_f64::<0>(transmute(a), transmute(b)));
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assert_eq!(r, e);
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}
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#[simd_test(enable = "neon")]
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unsafe fn test_vshld_s64() {
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let a: i64 = 1;
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@ -12906,6 +12906,294 @@ pub unsafe fn vrsraq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64
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simd_add(a, vrshrq_n_u64::<N>(b))
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vset_lane_s8<const LANE: i32>(a: i8, b: int8x8_t) -> int8x8_t {
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static_assert_imm3!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vset_lane_s16<const LANE: i32>(a: i16, b: int16x4_t) -> int16x4_t {
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static_assert_imm4!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vset_lane_s32<const LANE: i32>(a: i32, b: int32x2_t) -> int32x2_t {
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static_assert_imm5!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vset_lane_s64<const LANE: i32>(a: i64, b: int64x1_t) -> int64x1_t {
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static_assert_imm6!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vset_lane_u8<const LANE: i32>(a: u8, b: uint8x8_t) -> uint8x8_t {
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static_assert_imm3!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vset_lane_u16<const LANE: i32>(a: u16, b: uint16x4_t) -> uint16x4_t {
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static_assert_imm4!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vset_lane_u32<const LANE: i32>(a: u32, b: uint32x2_t) -> uint32x2_t {
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static_assert_imm5!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vset_lane_u64<const LANE: i32>(a: u64, b: uint64x1_t) -> uint64x1_t {
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static_assert_imm6!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vset_lane_p8<const LANE: i32>(a: p8, b: poly8x8_t) -> poly8x8_t {
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static_assert_imm3!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vset_lane_p16<const LANE: i32>(a: p16, b: poly16x4_t) -> poly16x4_t {
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static_assert_imm4!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon,crypto")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vset_lane_p64<const LANE: i32>(a: p64, b: poly64x1_t) -> poly64x1_t {
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static_assert_imm6!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vsetq_lane_s8<const LANE: i32>(a: i8, b: int8x16_t) -> int8x16_t {
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static_assert_imm3!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vsetq_lane_s16<const LANE: i32>(a: i16, b: int16x8_t) -> int16x8_t {
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static_assert_imm4!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vsetq_lane_s32<const LANE: i32>(a: i32, b: int32x4_t) -> int32x4_t {
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static_assert_imm5!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vsetq_lane_s64<const LANE: i32>(a: i64, b: int64x2_t) -> int64x2_t {
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static_assert_imm6!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vsetq_lane_u8<const LANE: i32>(a: u8, b: uint8x16_t) -> uint8x16_t {
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static_assert_imm3!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vsetq_lane_u16<const LANE: i32>(a: u16, b: uint16x8_t) -> uint16x8_t {
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static_assert_imm4!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vsetq_lane_u32<const LANE: i32>(a: u32, b: uint32x4_t) -> uint32x4_t {
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static_assert_imm5!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vsetq_lane_u64<const LANE: i32>(a: u64, b: uint64x2_t) -> uint64x2_t {
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static_assert_imm6!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vsetq_lane_p8<const LANE: i32>(a: p8, b: poly8x16_t) -> poly8x16_t {
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static_assert_imm3!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vsetq_lane_p16<const LANE: i32>(a: p16, b: poly16x8_t) -> poly16x8_t {
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static_assert_imm4!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon,crypto")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vsetq_lane_p64<const LANE: i32>(a: p64, b: poly64x2_t) -> poly64x2_t {
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static_assert_imm6!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn vset_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> float32x2_t {
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static_assert_imm1!(LANE);
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simd_insert(b, LANE as u32, a)
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}
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/// Insert vector element from another vector element
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
|
||||
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, LANE = 0))]
|
||||
#[rustc_legacy_const_generics(2)]
|
||||
pub unsafe fn vsetq_lane_f32<const LANE: i32>(a: f32, b: float32x4_t) -> float32x4_t {
|
||||
static_assert_imm2!(LANE);
|
||||
simd_insert(b, LANE as u32, a)
|
||||
}
|
||||
|
||||
/// Signed Shift left
|
||||
#[inline]
|
||||
#[target_feature(enable = "neon")]
|
||||
|
|
@ -23316,6 +23604,222 @@ mod test {
|
|||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vset_lane_s8() {
|
||||
let a: i8 = 1;
|
||||
let b: i8x8 = i8x8::new(0, 2, 3, 4, 5, 6, 7, 8);
|
||||
let e: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
|
||||
let r: i8x8 = transmute(vset_lane_s8::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vset_lane_s16() {
|
||||
let a: i16 = 1;
|
||||
let b: i16x4 = i16x4::new(0, 2, 3, 4);
|
||||
let e: i16x4 = i16x4::new(1, 2, 3, 4);
|
||||
let r: i16x4 = transmute(vset_lane_s16::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vset_lane_s32() {
|
||||
let a: i32 = 1;
|
||||
let b: i32x2 = i32x2::new(0, 2);
|
||||
let e: i32x2 = i32x2::new(1, 2);
|
||||
let r: i32x2 = transmute(vset_lane_s32::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vset_lane_s64() {
|
||||
let a: i64 = 1;
|
||||
let b: i64x1 = i64x1::new(0);
|
||||
let e: i64x1 = i64x1::new(1);
|
||||
let r: i64x1 = transmute(vset_lane_s64::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vset_lane_u8() {
|
||||
let a: u8 = 1;
|
||||
let b: u8x8 = u8x8::new(0, 2, 3, 4, 5, 6, 7, 8);
|
||||
let e: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
|
||||
let r: u8x8 = transmute(vset_lane_u8::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vset_lane_u16() {
|
||||
let a: u16 = 1;
|
||||
let b: u16x4 = u16x4::new(0, 2, 3, 4);
|
||||
let e: u16x4 = u16x4::new(1, 2, 3, 4);
|
||||
let r: u16x4 = transmute(vset_lane_u16::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vset_lane_u32() {
|
||||
let a: u32 = 1;
|
||||
let b: u32x2 = u32x2::new(0, 2);
|
||||
let e: u32x2 = u32x2::new(1, 2);
|
||||
let r: u32x2 = transmute(vset_lane_u32::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vset_lane_u64() {
|
||||
let a: u64 = 1;
|
||||
let b: u64x1 = u64x1::new(0);
|
||||
let e: u64x1 = u64x1::new(1);
|
||||
let r: u64x1 = transmute(vset_lane_u64::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vset_lane_p8() {
|
||||
let a: p8 = 1;
|
||||
let b: i8x8 = i8x8::new(0, 2, 3, 4, 5, 6, 7, 8);
|
||||
let e: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
|
||||
let r: i8x8 = transmute(vset_lane_p8::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vset_lane_p16() {
|
||||
let a: p16 = 1;
|
||||
let b: i16x4 = i16x4::new(0, 2, 3, 4);
|
||||
let e: i16x4 = i16x4::new(1, 2, 3, 4);
|
||||
let r: i16x4 = transmute(vset_lane_p16::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vset_lane_p64() {
|
||||
let a: p64 = 1;
|
||||
let b: i64x1 = i64x1::new(0);
|
||||
let e: i64x1 = i64x1::new(1);
|
||||
let r: i64x1 = transmute(vset_lane_p64::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vsetq_lane_s8() {
|
||||
let a: i8 = 1;
|
||||
let b: i8x16 = i8x16::new(0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
|
||||
let e: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
|
||||
let r: i8x16 = transmute(vsetq_lane_s8::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vsetq_lane_s16() {
|
||||
let a: i16 = 1;
|
||||
let b: i16x8 = i16x8::new(0, 2, 3, 4, 5, 6, 7, 8);
|
||||
let e: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
|
||||
let r: i16x8 = transmute(vsetq_lane_s16::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vsetq_lane_s32() {
|
||||
let a: i32 = 1;
|
||||
let b: i32x4 = i32x4::new(0, 2, 3, 4);
|
||||
let e: i32x4 = i32x4::new(1, 2, 3, 4);
|
||||
let r: i32x4 = transmute(vsetq_lane_s32::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vsetq_lane_s64() {
|
||||
let a: i64 = 1;
|
||||
let b: i64x2 = i64x2::new(0, 2);
|
||||
let e: i64x2 = i64x2::new(1, 2);
|
||||
let r: i64x2 = transmute(vsetq_lane_s64::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vsetq_lane_u8() {
|
||||
let a: u8 = 1;
|
||||
let b: u8x16 = u8x16::new(0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
|
||||
let e: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
|
||||
let r: u8x16 = transmute(vsetq_lane_u8::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vsetq_lane_u16() {
|
||||
let a: u16 = 1;
|
||||
let b: u16x8 = u16x8::new(0, 2, 3, 4, 5, 6, 7, 8);
|
||||
let e: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
|
||||
let r: u16x8 = transmute(vsetq_lane_u16::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vsetq_lane_u32() {
|
||||
let a: u32 = 1;
|
||||
let b: u32x4 = u32x4::new(0, 2, 3, 4);
|
||||
let e: u32x4 = u32x4::new(1, 2, 3, 4);
|
||||
let r: u32x4 = transmute(vsetq_lane_u32::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vsetq_lane_u64() {
|
||||
let a: u64 = 1;
|
||||
let b: u64x2 = u64x2::new(0, 2);
|
||||
let e: u64x2 = u64x2::new(1, 2);
|
||||
let r: u64x2 = transmute(vsetq_lane_u64::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vsetq_lane_p8() {
|
||||
let a: p8 = 1;
|
||||
let b: i8x16 = i8x16::new(0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
|
||||
let e: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
|
||||
let r: i8x16 = transmute(vsetq_lane_p8::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vsetq_lane_p16() {
|
||||
let a: p16 = 1;
|
||||
let b: i16x8 = i16x8::new(0, 2, 3, 4, 5, 6, 7, 8);
|
||||
let e: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
|
||||
let r: i16x8 = transmute(vsetq_lane_p16::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vsetq_lane_p64() {
|
||||
let a: p64 = 1;
|
||||
let b: i64x2 = i64x2::new(0, 2);
|
||||
let e: i64x2 = i64x2::new(1, 2);
|
||||
let r: i64x2 = transmute(vsetq_lane_p64::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vset_lane_f32() {
|
||||
let a: f32 = 1.;
|
||||
let b: f32x2 = f32x2::new(0., 2.);
|
||||
let e: f32x2 = f32x2::new(1., 2.);
|
||||
let r: f32x2 = transmute(vset_lane_f32::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vsetq_lane_f32() {
|
||||
let a: f32 = 1.;
|
||||
let b: f32x4 = f32x4::new(0., 2., 3., 4.);
|
||||
let e: f32x4 = f32x4::new(1., 2., 3., 4.);
|
||||
let r: f32x4 = transmute(vsetq_lane_f32::<0>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vshl_s8() {
|
||||
let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
|
||||
|
|
|
|||
|
|
@ -4384,6 +4384,82 @@ validate 2
|
|||
aarch64 = nop
|
||||
generate u64
|
||||
|
||||
/// Insert vector element from another vector element
|
||||
name = vset_lane
|
||||
constn = LANE
|
||||
multi_fn = static_assert_imm-in_bits_exp_len-LANE
|
||||
multi_fn = simd_insert, b, LANE as u32, a
|
||||
a = 1
|
||||
b = 0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
|
||||
n = 0
|
||||
validate 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
|
||||
|
||||
aarch64 = nop
|
||||
arm = nop
|
||||
generate i8:int8x8_t:int8x8_t, i16:int16x4_t:int16x4_t
|
||||
generate i32:int32x2_t:int32x2_t, i64:int64x1_t:int64x1_t
|
||||
generate u8:uint8x8_t:uint8x8_t, u16:uint16x4_t:uint16x4_t
|
||||
generate u32:uint32x2_t:uint32x2_t, u64:uint64x1_t:uint64x1_t
|
||||
generate p8:poly8x8_t:poly8x8_t, p16:poly16x4_t:poly16x4_t
|
||||
|
||||
target = crypto
|
||||
generate p64:poly64x1_t:poly64x1_t
|
||||
|
||||
/// Insert vector element from another vector element
|
||||
name = vsetq_lane
|
||||
no-q
|
||||
constn = LANE
|
||||
multi_fn = static_assert_imm-in_bits_exp_len-LANE
|
||||
multi_fn = simd_insert, b, LANE as u32, a
|
||||
a = 1
|
||||
b = 0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
|
||||
n = 0
|
||||
validate 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
|
||||
|
||||
aarch64 = nop
|
||||
arm = nop
|
||||
generate i8:int8x16_t:int8x16_t, i16:int16x8_t:int16x8_t
|
||||
generate i32:int32x4_t:int32x4_t, i64:int64x2_t:int64x2_t
|
||||
generate u8:uint8x16_t:uint8x16_t, u16:uint16x8_t:uint16x8_t
|
||||
generate u32:uint32x4_t:uint32x4_t, u64:uint64x2_t:uint64x2_t
|
||||
generate p8:poly8x16_t:poly8x16_t, p16:poly16x8_t:poly16x8_t
|
||||
|
||||
target = crypto
|
||||
generate p64:poly64x2_t:poly64x2_t
|
||||
|
||||
/// Insert vector element from another vector element
|
||||
name = vset_lane
|
||||
constn = LANE
|
||||
multi_fn = static_assert_imm-in_exp_len-LANE
|
||||
multi_fn = simd_insert, b, LANE as u32, a
|
||||
a = 1.
|
||||
b = 0., 2., 3., 4.
|
||||
n = 0
|
||||
validate 1., 2., 3., 4.
|
||||
|
||||
aarch64 = nop
|
||||
generate f64:float64x1_t:float64x1_t
|
||||
|
||||
arm = nop
|
||||
generate f32:float32x2_t:float32x2_t
|
||||
|
||||
/// Insert vector element from another vector element
|
||||
name = vsetq_lane
|
||||
no-q
|
||||
constn = LANE
|
||||
multi_fn = static_assert_imm-in_exp_len-LANE
|
||||
multi_fn = simd_insert, b, LANE as u32, a
|
||||
a = 1.
|
||||
b = 0., 2., 3., 4.
|
||||
n = 0
|
||||
validate 1., 2., 3., 4.
|
||||
|
||||
aarch64 = nop
|
||||
generate f64:float64x2_t:float64x2_t
|
||||
|
||||
arm = nop
|
||||
generate f32:float32x4_t:float32x4_t
|
||||
|
||||
/// Signed Shift left
|
||||
name = vshl
|
||||
a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue