Stabilize Ratified RISC-V Target Features
As shortly discussed on Zulip (https://rust-lang.zulipchat.com/#narrow/stream/250483-t-compiler.2Frisc-v/topic/Stabilization.20of.20RISC-V.20Target.20Features/near/394793704), this commit stabilizes the ratified RISC-V instruction bases and extensions. Specifically, this commit stabilizes the: * Atomic Instructions (A) on v2.0 * Compressed Instructions (C) on v2.0 * Integer Multiplication and Division (M) on v2.0 * Bit Manipulations (B) on v1.0 listed as `zba`, `zbc`, `zbs` * Scalar Cryptography (Zk) v1.0.1 listed as `zk`, `zkn`, `zknd`, `zkne`, `zknh`, `zkr`, `zks`, `zksed`, `zksh`, `zkt`, `zbkb`, `zbkc` `zkbx`
This commit is contained in:
Gijs Burghoorn
Amanieu d'Antras
parent
3ac4ba6670
commit
786f28dd8b
1 changed files with 52 additions and 65 deletions
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@ -24,19 +24,39 @@ features! {
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///
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/// The supported ratified RISC-V instruction sets are as follows:
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///
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/// * RV32E: `"rv32e"`
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/// * RV32I: `"rv32i"`
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/// * RV64I: `"rv64i"`
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/// * A: `"a"`
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/// * B: `"b"`
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/// * Zba: `"zba"`
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/// * Zbb: `"zbb"`
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/// * Zbc: `"zbc"`
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/// * Zbs: `"zbs"`
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/// * C: `"c"`
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/// * D: `"d"`
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/// * F: `"f"`
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/// * M: `"m"`
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/// * Q: `"q"`
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/// * V: `"v"`
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/// * Zicntr: `"zicntr"`
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/// * Zicsr: `"zicsr"`
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/// * Zifencei: `"zifencei"`
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/// * Zihintpause: `"zihintpause"`
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/// * RV64I: `"rv64i"`
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/// * M: `"m"`
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/// * A: `"a"`
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/// * Zicsr: `"zicsr"`
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/// * Zicntr: `"zicntr"`
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/// * Zihpm: `"zihpm"`
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/// * F: `"f"`
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/// * D: `"d"`
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/// * Q: `"q"`
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/// * C: `"c"`
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/// * Zk: `"zk"`
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/// * Zbkb: `"zbkb"`
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/// * Zbkc: `"zbkc"`
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/// * Zbkx: `"zbkx"`
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/// * Zkn: `"zkn"`
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/// * Zknd: `"zknd"`
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/// * Zkne: `"zkne"`
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/// * Zknh: `"zknh"`
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/// * Zkr: `"zkr"`
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/// * Zks: `"zks"`
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/// * Zksed: `"zksed"`
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/// * Zksh: `"zksh"`
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/// * Zkt: `"zkt"`
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///
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/// There's also bases and extensions marked as standard instruction set,
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/// but they are in frozen or draft state. These instruction sets are also
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@ -44,6 +64,8 @@ features! {
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///
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/// Frozen RISC-V instruction sets:
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///
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/// * Zfh: `"zfh"`
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/// * Zfhmin: `"zfhmin"`
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/// * Zfinx: `"zfinx"`
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/// * Zdinx: `"zdinx"`
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/// * Zhinx: `"zhinx"`
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@ -52,14 +74,9 @@ features! {
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///
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/// Draft RISC-V instruction sets:
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///
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/// * RV32E: `"rv32e"`
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/// * RV128I: `"rv128i"`
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/// * Zfh: `"zfh"`
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/// * Zfhmin: `"zfhmin"`
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/// * B: `"b"`
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/// * J: `"j"`
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/// * P: `"p"`
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/// * V: `"v"`
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/// * Zam: `"zam"`
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///
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/// Defined by Privileged Specification:
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@ -70,36 +87,8 @@ features! {
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/// * Svinval: `"svinval"`
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/// * Hypervisor: `"h"`
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///
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/// # RISC-V Bit-Manipulation ISA-extensions
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///
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/// This document defined the following extensions:
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///
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/// * Zba: `"zba"`
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/// * Zbb: `"zbb"`
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/// * Zbc: `"zbc"`
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/// * Zbs: `"zbs"`
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///
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/// # RISC-V Cryptography Extensions
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///
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/// These extensions are defined in Volume I, Scalar & Entropy Source
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/// Instructions:
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///
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/// * Zbkb: `"zbkb"`
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/// * Zbkc: `"zbkc"`
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/// * Zbkx: `"zbkx"`
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/// * Zknd: `"zknd"`
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/// * Zkne: `"zkne"`
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/// * Zknh: `"zknh"`
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/// * Zksed: `"zksed"`
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/// * Zksh: `"zksh"`
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/// * Zkr: `"zkr"`
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/// * Zkn: `"zkn"`
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/// * Zks: `"zks"`
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/// * Zk: `"zk"`
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/// * Zkt: `"zkt"`
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///
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/// [ISA manual]: https://github.com/riscv/riscv-isa-manual/
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#[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")]
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#[stable(feature = "riscv_ratified", since = "1.76.0")]
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32i: "rv32i";
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/// RV32I Base Integer Instruction Set
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zifencei: "zifencei";
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@ -108,9 +97,9 @@ features! {
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/// "Zihintpause" Pause Hint
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv64i: "rv64i";
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/// RV64I Base Integer Instruction Set
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] m: "m";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] m: "m";
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/// "M" Standard Extension for Integer Multiplication and Division
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] a: "a";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] a: "a";
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/// "A" Standard Extension for Atomic Instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicsr: "zicsr";
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/// "Zicsr", Control and Status Register (CSR) Instructions
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@ -124,7 +113,7 @@ features! {
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/// "D" Standard Extension for Double-Precision Floating-Point
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] q: "q";
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/// "Q" Standard Extension for Quad-Precision Floating-Point
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] c: "c";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] c: "c";
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/// "C" Standard Extension for Compressed Instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfinx: "zfinx";
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@ -146,8 +135,6 @@ features! {
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/// "Zfh" Standard Extension for 16-Bit Half-Precision Floating-Point
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfhmin: "zfhmin";
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/// "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point Support
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] b: "b";
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/// "B" Standard Extension for Bit Manipulation
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] j: "j";
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/// "J" Standard Extension for Dynamically Translated Languages
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] p: "p";
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@ -168,39 +155,39 @@ features! {
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] h: "h";
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/// Hypervisor Extension
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zba: "zba";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zba: "zba";
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/// "Zba" Standard Extension for Address Generation Instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbb: "zbb";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zbb: "zbb";
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/// "Zbb" Standard Extension for Basic Bit-Manipulation
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbc: "zbc";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zbc: "zbc";
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/// "Zbc" Standard Extension for Carry-less Multiplication
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbs: "zbs";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zbs: "zbs";
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/// "Zbs" Standard Extension for Single-Bit instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbkb: "zbkb";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zbkb: "zbkb";
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/// "Zbkb" Standard Extension for Bitmanip instructions for Cryptography
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbkc: "zbkc";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zbkc: "zbkc";
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/// "Zbkc" Standard Extension for Carry-less multiply instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbkx: "zbkx";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zbkx: "zbkx";
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/// "Zbkx" Standard Extension for Crossbar permutation instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zknd: "zknd";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zknd: "zknd";
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/// "Zknd" Standard Extension for NIST Suite: AES Decryption
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zkne: "zkne";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zkne: "zkne";
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/// "Zkne" Standard Extension for NIST Suite: AES Encryption
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zknh: "zknh";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zknh: "zknh";
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/// "Zknh" Standard Extension for NIST Suite: Hash Function Instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zksed: "zksed";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zksed: "zksed";
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/// "Zksed" Standard Extension for ShangMi Suite: SM4 Block Cipher Instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zksh: "zksh";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zksh: "zksh";
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/// "Zksh" Standard Extension for ShangMi Suite: SM3 Hash Function Instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zkr: "zkr";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zkr: "zkr";
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/// "Zkr" Standard Extension for Entropy Source Extension
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zkn: "zkn";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zkn: "zkn";
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/// "Zkn" Standard Extension for NIST Algorithm Suite
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zks: "zks";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zks: "zks";
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/// "Zks" Standard Extension for ShangMi Algorithm Suite
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zk: "zk";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zk: "zk";
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/// "Zk" Standard Extension for Standard scalar cryptography extension
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zkt: "zkt";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zkt: "zkt";
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/// "Zkt" Standard Extension for Data Independent Execution Latency
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}
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