Update test expectations for aarch64
This commit is contained in:
Nikita Popov
Amanieu d'Antras
parent
1e8274d34d
commit
7f510b818f
2 changed files with 33 additions and 40 deletions
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@ -1357,7 +1357,7 @@ pub unsafe fn vcgeq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s8)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(cmgt))]
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#[cfg_attr(test, assert_instr(cmge))]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vcgez_s8(a: int8x8_t) -> uint8x8_t {
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let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
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@ -1369,7 +1369,7 @@ pub unsafe fn vcgez_s8(a: int8x8_t) -> uint8x8_t {
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s8)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(cmgt))]
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#[cfg_attr(test, assert_instr(cmge))]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vcgezq_s8(a: int8x16_t) -> uint8x16_t {
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let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
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@ -1381,7 +1381,7 @@ pub unsafe fn vcgezq_s8(a: int8x16_t) -> uint8x16_t {
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s16)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(cmgt))]
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#[cfg_attr(test, assert_instr(cmge))]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vcgez_s16(a: int16x4_t) -> uint16x4_t {
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let b: i16x4 = i16x4::new(0, 0, 0, 0);
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@ -1393,7 +1393,7 @@ pub unsafe fn vcgez_s16(a: int16x4_t) -> uint16x4_t {
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s16)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(cmgt))]
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#[cfg_attr(test, assert_instr(cmge))]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vcgezq_s16(a: int16x8_t) -> uint16x8_t {
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let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
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@ -1405,7 +1405,7 @@ pub unsafe fn vcgezq_s16(a: int16x8_t) -> uint16x8_t {
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s32)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(cmgt))]
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#[cfg_attr(test, assert_instr(cmge))]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vcgez_s32(a: int32x2_t) -> uint32x2_t {
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let b: i32x2 = i32x2::new(0, 0);
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@ -1417,7 +1417,7 @@ pub unsafe fn vcgez_s32(a: int32x2_t) -> uint32x2_t {
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s32)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(cmgt))]
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#[cfg_attr(test, assert_instr(cmge))]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vcgezq_s32(a: int32x4_t) -> uint32x4_t {
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let b: i32x4 = i32x4::new(0, 0, 0, 0);
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@ -1429,7 +1429,7 @@ pub unsafe fn vcgezq_s32(a: int32x4_t) -> uint32x4_t {
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s64)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(cmgt))]
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#[cfg_attr(test, assert_instr(cmge))]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vcgez_s64(a: int64x1_t) -> uint64x1_t {
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let b: i64x1 = i64x1::new(0);
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@ -1441,7 +1441,7 @@ pub unsafe fn vcgez_s64(a: int64x1_t) -> uint64x1_t {
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s64)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(cmgt))]
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#[cfg_attr(test, assert_instr(cmge))]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vcgezq_s64(a: int64x2_t) -> uint64x2_t {
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let b: i64x2 = i64x2::new(0, 0);
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@ -1711,7 +1711,7 @@ pub unsafe fn vcgtzd_f64(a: f64) -> u64 {
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s8)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(cmgt))]
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#[cfg_attr(test, assert_instr(cmle))]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vclez_s8(a: int8x8_t) -> uint8x8_t {
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let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
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@ -1723,7 +1723,7 @@ pub unsafe fn vclez_s8(a: int8x8_t) -> uint8x8_t {
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s8)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(cmgt))]
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#[cfg_attr(test, assert_instr(cmle))]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vclezq_s8(a: int8x16_t) -> uint8x16_t {
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let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
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@ -1735,7 +1735,7 @@ pub unsafe fn vclezq_s8(a: int8x16_t) -> uint8x16_t {
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s16)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(cmgt))]
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#[cfg_attr(test, assert_instr(cmle))]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vclez_s16(a: int16x4_t) -> uint16x4_t {
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let b: i16x4 = i16x4::new(0, 0, 0, 0);
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@ -1747,7 +1747,7 @@ pub unsafe fn vclez_s16(a: int16x4_t) -> uint16x4_t {
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s16)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(cmgt))]
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#[cfg_attr(test, assert_instr(cmle))]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vclezq_s16(a: int16x8_t) -> uint16x8_t {
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let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
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@ -1759,7 +1759,7 @@ pub unsafe fn vclezq_s16(a: int16x8_t) -> uint16x8_t {
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s32)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(cmgt))]
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#[cfg_attr(test, assert_instr(cmle))]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vclez_s32(a: int32x2_t) -> uint32x2_t {
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let b: i32x2 = i32x2::new(0, 0);
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@ -1771,7 +1771,7 @@ pub unsafe fn vclez_s32(a: int32x2_t) -> uint32x2_t {
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s32)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(cmgt))]
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#[cfg_attr(test, assert_instr(cmle))]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vclezq_s32(a: int32x4_t) -> uint32x4_t {
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let b: i32x4 = i32x4::new(0, 0, 0, 0);
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@ -1783,7 +1783,7 @@ pub unsafe fn vclezq_s32(a: int32x4_t) -> uint32x4_t {
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s64)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(cmgt))]
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#[cfg_attr(test, assert_instr(cmle))]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vclez_s64(a: int64x1_t) -> uint64x1_t {
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let b: i64x1 = i64x1::new(0);
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@ -1795,7 +1795,7 @@ pub unsafe fn vclez_s64(a: int64x1_t) -> uint64x1_t {
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s64)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(cmgt))]
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#[cfg_attr(test, assert_instr(cmle))]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vclezq_s64(a: int64x2_t) -> uint64x2_t {
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let b: i64x2 = i64x2::new(0, 0);
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@ -9215,7 +9215,7 @@ pub unsafe fn vfma_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t, c:
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f64)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(fmla, LANE = 0))]
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#[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
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#[rustc_legacy_const_generics(3)]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vfma_laneq_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t, c: float64x2_t) -> float64x1_t {
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@ -9254,7 +9254,7 @@ pub unsafe fn vfmaq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t, c
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_lane_f32)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(fmla, LANE = 0))]
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#[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
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#[rustc_legacy_const_generics(3)]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vfmas_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 {
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@ -9273,7 +9273,7 @@ pub unsafe fn vfmas_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) ->
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_laneq_f32)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(fmla, LANE = 0))]
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#[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
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#[rustc_legacy_const_generics(3)]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vfmas_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 {
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@ -9311,7 +9311,7 @@ pub unsafe fn vfmad_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) ->
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_laneq_f64)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(fmla, LANE = 0))]
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#[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
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#[rustc_legacy_const_generics(3)]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vfmad_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
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@ -9441,7 +9441,7 @@ pub unsafe fn vfms_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t, c:
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f64)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(fmls, LANE = 0))]
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#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
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#[rustc_legacy_const_generics(3)]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vfms_laneq_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t, c: float64x2_t) -> float64x1_t {
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@ -9480,7 +9480,7 @@ pub unsafe fn vfmsq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t, c
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_lane_f32)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(fmls, LANE = 0))]
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#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
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#[rustc_legacy_const_generics(3)]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vfmss_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 {
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@ -9492,7 +9492,7 @@ pub unsafe fn vfmss_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) ->
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_laneq_f32)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(fmls, LANE = 0))]
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#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
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#[rustc_legacy_const_generics(3)]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vfmss_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 {
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@ -9516,7 +9516,7 @@ pub unsafe fn vfmsd_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) ->
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_laneq_f64)
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(test, assert_instr(fmls, LANE = 0))]
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#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
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#[rustc_legacy_const_generics(3)]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub unsafe fn vfmsd_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
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@ -732,7 +732,7 @@ a = MIN, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0
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fixed = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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validate FALSE, FALSE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE
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aarch64 = cmgt
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aarch64 = cmge
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generate int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t, int64x1_t:uint64x1_t, int64x2_t:uint64x2_t
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/// Floating-point compare greater than or equal to zero
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@ -808,7 +808,7 @@ a = MIN, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0
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fixed = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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validate TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE
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aarch64 = cmgt
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aarch64 = cmle
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generate int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t, int64x1_t:uint64x1_t, int64x2_t:uint64x2_t
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/// Floating-point compare less than or equal to zero
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@ -4032,9 +4032,9 @@ validate 14., 11., 18., 21.
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aarch64 = fmla
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generate float32x2_t, float32x2_t:float32x2_t:float32x4_t:float32x2_t, float32x4_t:float32x4_t:float32x2_t:float32x4_t, float32x4_t
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aarch64 = fmadd
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generate float64x1_t
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generate float64x1_t, float64x1_t:float64x1_t:float64x2_t:float64x1_t
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aarch64 = fmla
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generate float64x1_t:float64x1_t:float64x2_t:float64x1_t, float64x2_t:float64x2_t:float64x1_t:float64x2_t, float64x2_t
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generate float64x2_t:float64x2_t:float64x1_t:float64x2_t, float64x2_t
|
||||
|
||||
/// Floating-point fused multiply-add to accumulator
|
||||
name = vfma
|
||||
|
|
@ -4049,14 +4049,11 @@ c = 3., 0., 0., 0.
|
|||
n = 0
|
||||
validate 20.
|
||||
|
||||
aarch64 = fmla
|
||||
aarch64 = fmadd
|
||||
link-aarch64 = llvm.fma._EXT_:f32:f32:f32:f32
|
||||
generate f32:f32:float32x2_t:f32, f32:f32:float32x4_t:f32
|
||||
link-aarch64 = llvm.fma._EXT_:f64:f64:f64:f64
|
||||
aarch64 = fmadd
|
||||
generate f64:f64:float64x1_t:f64
|
||||
aarch64 = fmla
|
||||
generate f64:f64:float64x2_t:f64
|
||||
generate f64:f64:float64x1_t:f64, f64:f64:float64x2_t:f64
|
||||
|
||||
/// Floating-point fused multiply-subtract from accumulator
|
||||
name = vfms
|
||||
|
|
@ -4109,9 +4106,9 @@ validate 2., 3., 4., 5.
|
|||
aarch64 = fmls
|
||||
generate float32x2_t, float32x2_t:float32x2_t:float32x4_t:float32x2_t, float32x4_t:float32x4_t:float32x2_t:float32x4_t, float32x4_t
|
||||
aarch64 = fmsub
|
||||
generate float64x1_t
|
||||
generate float64x1_t, float64x1_t:float64x1_t:float64x2_t:float64x1_t
|
||||
aarch64 = fmls
|
||||
generate float64x1_t:float64x1_t:float64x2_t:float64x1_t, float64x2_t:float64x2_t:float64x1_t:float64x2_t, float64x2_t
|
||||
generate float64x2_t:float64x2_t:float64x1_t:float64x2_t, float64x2_t
|
||||
|
||||
/// Floating-point fused multiply-subtract to accumulator
|
||||
name = vfms
|
||||
|
|
@ -4124,12 +4121,8 @@ c = 2., 0., 0., 0.
|
|||
n = 0
|
||||
validate 2.
|
||||
|
||||
aarch64 = fmls
|
||||
generate f32:f32:float32x2_t:f32, f32:f32:float32x4_t:f32
|
||||
aarch64 = fmsub
|
||||
generate f64:f64:float64x1_t:f64
|
||||
aarch64 = fmls
|
||||
generate f64:f64:float64x2_t:f64
|
||||
generate f32:f32:float32x2_t:f32, f32:f32:float32x4_t:f32, f64:f64:float64x1_t:f64, f64:f64:float64x2_t:f64
|
||||
|
||||
/// Divide
|
||||
name = vdiv
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue