Avx512f_avx512vl (#983)
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5 changed files with 2048 additions and 880 deletions
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<summary>["AVX512F"]</summary><p>
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* [x] [`_mm512_abs_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_abs_epi32&expand=5236)
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* [x] [`_mm512_abs_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_abs_epi64&expand=5236)
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* [x] [`_mm512_abs_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_abs_pd&expand=5236)
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* [x] [`_mm512_abs_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_abs_ps&expand=5236)
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* [x] [`_mm512_add_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_add_epi32&expand=5236)
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* [x] [`_mm512_add_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_add_epi64&expand=5236)
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* [x] [`_mm512_add_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_add_pd&expand=5236)
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* [x] [`_mm512_add_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_add_ps&expand=5236)
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* [x] [`_mm512_add_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_add_round_pd&expand=5236)
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* [x] [`_mm512_add_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_add_round_ps&expand=5236)
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* [x] [`_mm512_alignr_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_alignr_epi32&expand=5236)
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* [x] [`_mm512_alignr_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_alignr_epi64&expand=5236)
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* [x] [`_mm512_and_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_and_epi32&expand=5236)
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* [x] [`_mm512_and_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_and_epi64&expand=5236)
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* [x] [`_mm512_and_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_and_si512&expand=5236)
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* [x] [`_mm512_andnot_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_andnot_epi32&expand=5236)
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* [x] [`_mm512_andnot_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_andnot_epi64&expand=5236)
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* [x] [`_mm512_andnot_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_andnot_si512&expand=5236)
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* [x] [`_mm512_broadcast_f32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_broadcast_f32x4&expand=5236)
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* [x] [`_mm512_abs_epi32`]
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* [x] [`_mm512_mask_abs_epi32`]
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* [x] [`_mm512_maskz_abs_epi32`]
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* [x] [`_mm_mask_abs_epi32`]
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* [x] [`_mm_maskz_abs_epi32`]
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* [x] [`_mm256_mask_abs_epi32`]
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* [x] [`_mm256_maskz_abs_epi32`]
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* [x] [`_mm512_abs_epi64`]
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* [x] [`_mm512_mask_abs_epi64`]
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* [x] [`_mm512_maskz_abs_epi64`]
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* [x] [`_mm_abs_epi64`]
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* [x] [`_mm_mask_abs_epi64`]
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* [x] [`_mm_maskz_abs_epi64`]
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* [x] [`_mm256_abs_epi64`]
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* [x] [`_mm256_mask_abs_epi64`]
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* [x] [`_mm256_maskz_abs_epi64`]
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* [x] [`_mm512_abs_pd`]
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* [x] [`_mm512_mask_abs_pd`]
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* [x] [`_mm512_abs_ps`]
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* [x] [`_mm512_mask_abs_ps`]
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* [x] [`_mm512_add_epi32`]
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* [x] [`_mm512_mask_add_epi32`]
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* [x] [`_mm512_maskz_add_epi32`]
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* [x] [`_mm_mask_add_epi32`]
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* [x] [`_mm_maskz_add_epi32`]
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* [x] [`_mm256_mask_add_epi32`]
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* [x] [`_mm256_maskz_add_epi32`]
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* [x] [`_mm512_add_epi64`]
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* [x] [`_mm512_mask_add_epi64`]
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* [x] [`_mm512_maskz_add_epi64`]
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* [x] [`_mm_mask_add_epi64`]
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* [x] [`_mm_maskz_add_epi64`]
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* [x] [`_mm256_mask_add_epi64`]
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* [x] [`_mm256_maskz_add_epi64`]
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* [x] [`_mm512_add_ps`]
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* [x] [`_mm512_mask_add_ps`]
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* [x] [`_mm512_maskz_add_ps`]
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* [x] [`_mm_mask_add_ps`]
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* [x] [`_mm_maskz_add_ps`]
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* [x] [`_mm256_mask_add_ps`]
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* [x] [`_mm256_maskz_add_ps`]
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* [x] [`_mm512_add_pd`]
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* [x] [`_mm512_mask_add_pd`]
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* [x] [`_mm512_maskz_add_pd`]
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* [x] [`_mm_mask_add_pd`]
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* [x] [`_mm_maskz_add_pd`]
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* [x] [`_mm256_mask_add_pd`]
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* [x] [`_mm256_maskz_add_pd`]
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* [x] [`_mm512_add_round_ps`]
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* [x] [`_mm512_mask_add_round_ps`]
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* [x] [`_mm512_maskz_add_round_ps`]
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* [x] [`_mm512_add_round_pd`]
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* [x] [`_mm512_mask_add_round_pd`]
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* [x] [`_mm512_maskz_add_round_pd`]
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* [x] [`_mm512_sub_epi32`]
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* [x] [`_mm512_mask_sub_epi32`]
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* [x] [`_mm512_maskz_sub_epi32`]
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* [x] [`_mm_mask_sub_epi32`]
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* [x] [`_mm_maskz_sub_epi32`]
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* [x] [`_mm256_mask_sub_epi32`]
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* [x] [`_mm256_maskz_sub_epi32`]
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* [x] [`_mm512_sub_epi64`]
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* [x] [`_mm512_mask_sub_epi64`]
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* [x] [`_mm512_maskz_sub_epi64`]
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* [x] [`_mm_mask_sub_epi64`]
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* [x] [`_mm_maskz_sub_epi64`]
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* [x] [`_mm256_mask_sub_epi64`]
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* [x] [`_mm256_maskz_sub_epi64`]
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* [x] [`_mm512_sub_ps`]
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* [x] [`_mm512_mask_sub_ps`]
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* [x] [`_mm512_maskz_sub_ps`]
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* [x] [`_mm_mask_sub_ps`]
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* [x] [`_mm_maskz_sub_ps`]
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* [x] [`_mm256_mask_sub_ps`]
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* [x] [`_mm256_maskz_sub_ps`]
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* [x] [`_mm512_sub_pd`]
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* [x] [`_mm512_mask_sub_pd`]
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* [x] [`_mm512_maskz_sub_pd`]
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* [x] [`_mm_mask_sub_pd`]
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* [x] [`_mm_maskz_sub_pd`]
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* [x] [`_mm256_mask_sub_pd`]
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* [x] [`_mm256_maskz_sub_pd`]
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* [x] [`_mm512_sub_round_ps`]
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* [x] [`_mm512_mask_sub_round_ps`]
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* [x] [`_mm512_maskz_sub_round_ps`]
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* [x] [`_mm512_sub_round_pd`]
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* [x] [`_mm512_mask_sub_round_pd`]
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* [x] [`_mm512_maskz_sub_round_pd`]
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* [x] [`_mm512_mul_epi32`]
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* [x] [`_mm512_mask_mul_epi32`]
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* [x] [`_mm512_maskz_mul_epi32`]
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* [x] [`_mm_mask_mul_epi32`]
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* [x] [`_mm_maskz_mul_epi32`]
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* [x] [`_mm256_mask_mul_epi32`]
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* [x] [`_mm256_maskz_mul_epi32`]
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* [x] [`_mm512_mul_epu32`]
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* [x] [`_mm512_mask_mul_epu32`]
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* [x] [`_mm512_maskz_mul_epu32`]
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* [x] [`_mm_mask_mul_epu32`]
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* [x] [`_mm_maskz_mul_epu32`]
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* [x] [`_mm256_mask_mul_epu32`]
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* [x] [`_mm256_maskz_mul_epu32`]
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* [x] [`_mm512_mul_ps`]
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* [x] [`_mm512_mask_mul_ps`]
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* [x] [`_mm512_maskz_mul_ps`]
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* [x] [`_mm_mask_mul_ps`]
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* [x] [`_mm_maskz_mul_ps`]
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* [x] [`_mm256_mask_mul_ps`]
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* [x] [`_mm256_maskz_mul_ps`]
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* [x] [`_mm512_mul_pd`]
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* [x] [`_mm512_mask_mul_pd`]
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* [x] [`_mm512_maskz_mul_pd`]
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* [x] [`_mm_mask_mul_pd`]
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* [x] [`_mm_maskz_mul_pd`]
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* [x] [`_mm256_mask_mul_pd`]
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* [x] [`_mm256_maskz_mul_pd`]
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* [x] [`_mm512_mul_round_ps`]
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* [x] [`_mm512_mask_mul_round_ps`]
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* [x] [`_mm512_maskz_mul_round_ps`]
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* [x] [`_mm512_mul_round_pd`]
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* [x] [`_mm512_mask_mul_round_pd`]
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* [x] [`_mm512_maskz_mul_round_pd`]
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* [x] [`_mm512_mullo_epi32`]
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* [x] [`_mm512_mask_mullo_epi32`]
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* [x] [`_mm512_maskz_mullo_epi32`]
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* [x] [`_mm_mask_mullo_epi32`]
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* [x] [`_mm_maskz_mullo_epi32`]
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* [x] [`_mm256_mask_mullo_epi32`]
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* [x] [`_mm256_maskz_mullo_epi32`]
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* [x] [`_mm512_mullox_epi64`]
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* [x] [`_mm512_mask_mullox_epi64`]
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* [x] [`_mm512_div_ps`]
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* [x] [`_mm512_mask_div_ps`]
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* [x] [`_mm512_maskz_div_ps`]
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* [x] [`_mm_mask_div_ps`]
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* [x] [`_mm_maskz_div_ps`]
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* [x] [`_mm256_mask_div_ps`]
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* [x] [`_mm256_maskz_div_ps`]
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* [x] [`_mm512_div_pd`]
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* [x] [`_mm512_mask_div_pd`]
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* [x] [`_mm512_maskz_div_pd`]
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* [x] [`_mm_mask_div_pd`]
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* [x] [`_mm_maskz_div_pd`]
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* [x] [`_mm256_mask_div_pd`]
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* [x] [`_mm256_maskz_div_pd`]
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* [x] [`_mm512_div_round_ps`]
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* [x] [`_mm512_mask_div_round_ps`]
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* [x] [`_mm512_maskz_div_round_ps`]
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* [x] [`_mm512_div_round_pd`]
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* [x] [`_mm512_mask_div_round_pd`]
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* [x] [`_mm512_maskz_div_round_pd`]
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* [x] [`_mm512_alignr_epi32`]
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* [x] [`_mm512_alignr_epi64`]
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* [x] [`_mm512_and_epi32`]
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* [x] [`_mm512_and_epi64`]
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* [x] [`_mm512_and_si512`]
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* [x] [`_mm512_andnot_epi32`]
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* [x] [`_mm512_andnot_epi64`]
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* [x] [`_mm512_andnot_si512`]
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* [x] [`_mm512_broadcast_f32x4`]
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* [x] [`_mm512_broadcast_f64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_broadcast_f64x4&expand=5236)
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* [x] [`_mm512_broadcast_i32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_broadcast_i32x4&expand=5236)
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* [x] [`_mm512_broadcast_i64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_broadcast_i64x4&expand=5236)
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* [x] [`_mm512_cvtusepi64_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtusepi64_epi16&expand=5236)
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* [x] [`_mm512_cvtusepi64_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtusepi64_epi32&expand=5236)
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* [x] [`_mm512_cvtusepi64_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtusepi64_epi8&expand=5236)
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* [x] [`_mm512_div_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_div_pd&expand=5236)
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* [x] [`_mm512_div_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_div_ps&expand=5236)
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* [x] [`_mm512_div_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_div_round_pd&expand=5236)
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* [x] [`_mm512_div_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_div_round_ps&expand=5236)
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* [x] [`_mm512_extractf32x4_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_extractf32x4_ps&expand=5236)
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* [x] [`_mm512_extractf64x4_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_extractf64x4_pd&expand=5236)
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* [x] [`_mm512_extracti32x4_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_extracti32x4_epi32&expand=5236)
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* [x] [`_mm512_mask3_fnmsub_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fnmsub_ps&expand=5236)
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* [x] [`_mm512_mask3_fnmsub_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fnmsub_round_pd&expand=5236)
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* [x] [`_mm512_mask3_fnmsub_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fnmsub_round_ps&expand=5236)
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* [x] [`_mm512_mask_abs_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_abs_epi32&expand=5236)
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* [x] [`_mm512_mask_abs_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_abs_epi64&expand=5236)
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* [x] [`_mm512_mask_abs_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_abs_pd&expand=5236)
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* [x] [`_mm512_mask_abs_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_abs_ps&expand=5236)
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* [x] [`_mm512_mask_add_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_add_epi32&expand=5236)
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* [x] [`_mm512_mask_add_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_add_epi64&expand=5236)
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* [x] [`_mm512_mask_add_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_add_pd&expand=5236)
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* [x] [`_mm512_mask_add_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_add_ps&expand=5236)
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* [x] [`_mm512_mask_add_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_add_round_pd&expand=5236)
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* [x] [`_mm512_mask_add_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_add_round_ps&expand=5236)
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* [x] [`_mm512_mask_alignr_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_alignr_epi32&expand=5236)
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* [x] [`_mm512_mask_alignr_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_alignr_epi64&expand=5236)
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* [x] [`_mm512_mask_and_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_and_epi32&expand=5236)
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* [ ] [`_mm512_mask_cvtusepi64_storeu_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi64_storeu_epi16&expand=5236)
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* [ ] [`_mm512_mask_cvtusepi64_storeu_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi64_storeu_epi32&expand=5236)
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* [ ] [`_mm512_mask_cvtusepi64_storeu_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi64_storeu_epi8&expand=5236)
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* [x] [`_mm512_mask_div_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_div_pd&expand=5236)
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* [x] [`_mm512_mask_div_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_div_ps&expand=5236)
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* [x] [`_mm512_mask_div_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_div_round_pd&expand=5236)
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* [x] [`_mm512_mask_div_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_div_round_ps&expand=5236)
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* [x] [`_mm512_mask_expand_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_expand_epi32&expand=5236)
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* [x] [`_mm512_mask_expand_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_expand_epi64&expand=5236)
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* [x] [`_mm512_mask_expand_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_expand_pd&expand=5236)
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@ -548,14 +671,6 @@
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* [x] [`_mm512_mask_movedup_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_movedup_pd&expand=5236)
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* [x] [`_mm512_mask_movehdup_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_movehdup_ps&expand=5236)
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* [x] [`_mm512_mask_moveldup_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_moveldup_ps&expand=5236)
|
||||
* [x] [`_mm512_mask_mul_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mul_epi32&expand=5236)
|
||||
* [x] [`_mm512_mask_mul_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mul_epu32&expand=5236)
|
||||
* [x] [`_mm512_mask_mul_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mul_pd&expand=5236)
|
||||
* [x] [`_mm512_mask_mul_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mul_ps&expand=5236)
|
||||
* [x] [`_mm512_mask_mul_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mul_round_pd&expand=5236)
|
||||
* [x] [`_mm512_mask_mul_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mul_round_ps&expand=5236)
|
||||
* [x] [`_mm512_mask_mullo_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mullo_epi32&expand=5236)
|
||||
* [x] [`_mm512_mask_mullox_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mullox_epi64&expand=5236)
|
||||
* [x] [`_mm512_mask_or_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_or_epi32&expand=5236)
|
||||
* [x] [`_mm512_mask_or_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_or_epi64&expand=5236)
|
||||
* [x] [`_mm512_mask_permute_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_permute_pd&expand=5236)
|
||||
|
|
@ -575,30 +690,30 @@
|
|||
* [x] [`_mm512_mask_permutexvar_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_permutexvar_ps&expand=5236)
|
||||
* [x] [`_mm512_mask_rcp14_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rcp14_pd&expand=5236)
|
||||
* [x] [`_mm512_mask_rcp14_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rcp14_ps&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_add_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_add_epi32&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_add_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_add_epi64&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_add_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_add_pd&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_add_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_add_ps&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_and_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_and_epi32&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_and_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_and_epi64&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_max_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_max_epi32&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_max_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_max_epi64&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_max_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_max_epu32&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_max_epu64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_max_epu64&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_max_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_max_pd&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_max_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_max_ps&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_min_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_min_epi32&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_min_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_min_epi64&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_min_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_min_epu32&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_min_epu64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_min_epu64&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_min_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_min_pd&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_min_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_min_ps&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_mul_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_mul_epi32&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_mul_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_mul_epi64&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_mul_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_mul_pd&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_mul_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_mul_ps&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_or_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_or_epi32&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_or_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_or_epi64&expand=5236)
|
||||
* [x] [`_mm512_mask_reduce_add_epi32`]
|
||||
* [x] [`_mm512_mask_reduce_add_epi64`]
|
||||
* [x] [`_mm512_mask_reduce_add_pd`]
|
||||
* [x] [`_mm512_mask_reduce_add_ps`]
|
||||
* [x] [`_mm512_mask_reduce_and_epi32`]
|
||||
* [x] [`_mm512_mask_reduce_and_epi64`]
|
||||
* [x] [`_mm512_mask_reduce_max_epi32`]
|
||||
* [x] [`_mm512_mask_reduce_max_epi64`]
|
||||
* [x] [`_mm512_mask_reduce_max_epu32`]
|
||||
* [x] [`_mm512_mask_reduce_max_epu64`]
|
||||
* [x] [`_mm512_mask_reduce_max_pd`]
|
||||
* [x] [`_mm512_mask_reduce_max_ps`]
|
||||
* [x] [`_mm512_mask_reduce_min_epi32`]
|
||||
* [x] [`_mm512_mask_reduce_min_epi64`]
|
||||
* [x] [`_mm512_mask_reduce_min_epu32`]
|
||||
* [x] [`_mm512_mask_reduce_min_epu64`]
|
||||
* [x] [`_mm512_mask_reduce_min_pd`]
|
||||
* [x] [`_mm512_mask_reduce_min_ps`]
|
||||
* [x] [`_mm512_mask_reduce_mul_epi32`]
|
||||
* [x] [`_mm512_mask_reduce_mul_epi64`]
|
||||
* [x] [`_mm512_mask_reduce_mul_pd`]
|
||||
* [x] [`_mm512_mask_reduce_mul_ps`]
|
||||
* [x] [`_mm512_mask_reduce_or_epi32`]
|
||||
* [x] [`_mm512_mask_reduce_or_epi64`]
|
||||
* [x] [`_mm512_mask_rol_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rol_epi32&expand=5236)
|
||||
* [x] [`_mm512_mask_rol_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rol_epi64&expand=5236)
|
||||
* [x] [`_mm512_mask_rolv_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rolv_epi32&expand=5236)
|
||||
|
|
@ -656,12 +771,6 @@
|
|||
* [ ] [`_mm512_mask_storeu_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_storeu_epi64&expand=5236)
|
||||
* [ ] [`_mm512_mask_storeu_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_storeu_pd&expand=5236)
|
||||
* [ ] [`_mm512_mask_storeu_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_storeu_ps&expand=5236)
|
||||
* [x] [`_mm512_mask_sub_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sub_epi32&expand=5236)
|
||||
* [x] [`_mm512_mask_sub_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sub_epi64&expand=5236)
|
||||
* [x] [`_mm512_mask_sub_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sub_pd&expand=5236)
|
||||
* [x] [`_mm512_mask_sub_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sub_ps&expand=5236)
|
||||
* [x] [`_mm512_mask_sub_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sub_round_pd&expand=5236)
|
||||
* [x] [`_mm512_mask_sub_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sub_round_ps&expand=5236)
|
||||
* [x] [`_mm512_mask_ternarylogic_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_ternarylogic_epi32&expand=5236)
|
||||
* [x] [`_mm512_mask_ternarylogic_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_ternarylogic_epi64&expand=5236)
|
||||
* [x] [`_mm512_mask_test_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_test_epi32_mask&expand=5236)
|
||||
|
|
@ -678,14 +787,6 @@
|
|||
* [x] [`_mm512_mask_unpacklo_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_unpacklo_ps&expand=5236)
|
||||
* [x] [`_mm512_mask_xor_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_xor_epi32&expand=5236)
|
||||
* [x] [`_mm512_mask_xor_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_xor_epi64&expand=5236)
|
||||
* [x] [`_mm512_maskz_abs_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_abs_epi32&expand=5236)
|
||||
* [x] [`_mm512_maskz_abs_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_abs_epi64&expand=5236)
|
||||
* [x] [`_mm512_maskz_add_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_add_epi32&expand=5236)
|
||||
* [x] [`_mm512_maskz_add_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_add_epi64&expand=5236)
|
||||
* [x] [`_mm512_maskz_add_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_add_pd&expand=5236)
|
||||
* [x] [`_mm512_maskz_add_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_add_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_add_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_add_round_pd&expand=5236)
|
||||
* [x] [`_mm512_maskz_add_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_add_round_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_alignr_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_alignr_epi32&expand=5236)
|
||||
* [x] [`_mm512_maskz_alignr_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_alignr_epi64&expand=5236)
|
||||
* [x] [`_mm512_maskz_and_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_and_epi32&expand=5236)
|
||||
|
|
@ -759,10 +860,6 @@
|
|||
* [x] [`_mm512_maskz_cvtusepi64_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtusepi64_epi16&expand=5236)
|
||||
* [x] [`_mm512_maskz_cvtusepi64_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtusepi64_epi32&expand=5236)
|
||||
* [x] [`_mm512_maskz_cvtusepi64_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtusepi64_epi8&expand=5236)
|
||||
* [x] [`_mm512_maskz_div_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_div_pd&expand=5236)
|
||||
* [x] [`_mm512_maskz_div_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_div_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_div_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_div_round_pd&expand=5236)
|
||||
* [x] [`_mm512_maskz_div_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_div_round_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_expand_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_expand_epi32&expand=5236)
|
||||
* [x] [`_mm512_maskz_expand_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_expand_epi64&expand=5236)
|
||||
* [x] [`_mm512_maskz_expand_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_expand_pd&expand=5236)
|
||||
|
|
@ -846,13 +943,6 @@
|
|||
* [x] [`_mm512_maskz_movedup_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_movedup_pd&expand=5236)
|
||||
* [x] [`_mm512_maskz_movehdup_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_movehdup_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_moveldup_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_moveldup_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_mul_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mul_epi32&expand=5236)
|
||||
* [x] [`_mm512_maskz_mul_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mul_epu32&expand=5236)
|
||||
* [x] [`_mm512_maskz_mul_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mul_pd&expand=5236)
|
||||
* [x] [`_mm512_maskz_mul_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mul_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_mul_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mul_round_pd&expand=5236)
|
||||
* [x] [`_mm512_maskz_mul_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mul_round_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_mullo_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mullo_epi32&expand=5236)
|
||||
* [x] [`_mm512_maskz_or_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_or_epi32&expand=5236)
|
||||
* [x] [`_mm512_maskz_or_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_or_epi64&expand=5236)
|
||||
* [x] [`_mm512_maskz_permute_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_permute_pd&expand=5236)
|
||||
|
|
@ -920,12 +1010,6 @@
|
|||
* [x] [`_mm512_maskz_srli_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_srli_epi64&expand=5236)
|
||||
* [x] [`_mm512_maskz_srlv_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_srlv_epi32&expand=5236)
|
||||
* [x] [`_mm512_maskz_srlv_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_srlv_epi64&expand=5236)
|
||||
* [x] [`_mm512_maskz_sub_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sub_epi32&expand=5236)
|
||||
* [x] [`_mm512_maskz_sub_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sub_epi64&expand=5236)
|
||||
* [x] [`_mm512_maskz_sub_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sub_pd&expand=5236)
|
||||
* [x] [`_mm512_maskz_sub_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sub_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_sub_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sub_round_pd&expand=5236)
|
||||
* [x] [`_mm512_maskz_sub_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sub_round_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_ternarylogic_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_ternarylogic_epi32&expand=5236)
|
||||
* [x] [`_mm512_maskz_ternarylogic_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_ternarylogic_epi64&expand=5236)
|
||||
* [x] [`_mm512_maskz_unpackhi_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_unpackhi_epi32&expand=5236)
|
||||
|
|
@ -957,14 +1041,6 @@
|
|||
* [x] [`_mm512_movedup_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_movedup_pd&expand=5236)
|
||||
* [x] [`_mm512_movehdup_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_movehdup_ps&expand=5236)
|
||||
* [x] [`_mm512_moveldup_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_moveldup_ps&expand=5236)
|
||||
* [x] [`_mm512_mul_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mul_epi32&expand=5236)
|
||||
* [x] [`_mm512_mul_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mul_epu32&expand=5236)
|
||||
* [x] [`_mm512_mul_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mul_pd&expand=5236)
|
||||
* [x] [`_mm512_mul_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mul_ps&expand=5236)
|
||||
* [x] [`_mm512_mul_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mul_round_pd&expand=5236)
|
||||
* [x] [`_mm512_mul_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mul_round_ps&expand=5236)
|
||||
* [x] [`_mm512_mullo_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mullo_epi32&expand=5236)
|
||||
* [x] [`_mm512_mullox_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mullox_epi64&expand=5236)
|
||||
* [x] [`_mm512_or_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_or_epi32&expand=5236)
|
||||
* [x] [`_mm512_or_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_or_epi64&expand=5236)
|
||||
* [x] [`_mm512_or_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_or_si512&expand=5236)
|
||||
|
|
@ -985,30 +1061,30 @@
|
|||
* [x] [`_mm512_permutexvar_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutexvar_ps&expand=5236)
|
||||
* [x] [`_mm512_rcp14_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rcp14_pd&expand=5236)
|
||||
* [x] [`_mm512_rcp14_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rcp14_ps&expand=5236)
|
||||
* [x] [`_mm512_reduce_add_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_add_epi32&expand=5236)
|
||||
* [x] [`_mm512_reduce_add_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_add_epi64&expand=5236)
|
||||
* [x] [`_mm512_reduce_add_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_add_pd&expand=5236)
|
||||
* [x] [`_mm512_reduce_add_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_add_ps&expand=5236)
|
||||
* [x] [`_mm512_reduce_and_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_and_epi32&expand=5236)
|
||||
* [x] [`_mm512_reduce_and_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_and_epi64&expand=5236)
|
||||
* [x] [`_mm512_reduce_max_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_max_epi32&expand=5236)
|
||||
* [x] [`_mm512_reduce_max_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_max_epi64&expand=5236)
|
||||
* [x] [`_mm512_reduce_max_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_max_epu32&expand=5236)
|
||||
* [x] [`_mm512_reduce_max_epu64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_max_epu64&expand=5236)
|
||||
* [x] [`_mm512_reduce_max_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_max_pd&expand=5236)
|
||||
* [x] [`_mm512_reduce_max_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_max_ps&expand=5236)
|
||||
* [x] [`_mm512_reduce_min_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_min_epi32&expand=5236)
|
||||
* [x] [`_mm512_reduce_min_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_min_epi64&expand=5236)
|
||||
* [x] [`_mm512_reduce_min_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_min_epu32&expand=5236)
|
||||
* [x] [`_mm512_reduce_min_epu64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_min_epu64&expand=5236)
|
||||
* [x] [`_mm512_reduce_min_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_min_pd&expand=5236)
|
||||
* [x] [`_mm512_reduce_min_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_min_ps&expand=5236)
|
||||
* [x] [`_mm512_reduce_mul_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_mul_epi32&expand=5236)
|
||||
* [x] [`_mm512_reduce_mul_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_mul_epi64&expand=5236)
|
||||
* [x] [`_mm512_reduce_mul_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_mul_pd&expand=5236)
|
||||
* [x] [`_mm512_reduce_mul_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_mul_ps&expand=5236)
|
||||
* [x] [`_mm512_reduce_or_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_or_epi32&expand=5236)
|
||||
* [x] [`_mm512_reduce_or_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_or_epi64&expand=5236)
|
||||
* [x] [`_mm512_reduce_add_epi32`]
|
||||
* [x] [`_mm512_reduce_add_epi64`]
|
||||
* [x] [`_mm512_reduce_add_pd`]
|
||||
* [x] [`_mm512_reduce_add_ps`]
|
||||
* [x] [`_mm512_reduce_and_epi32`]
|
||||
* [x] [`_mm512_reduce_and_epi64`]
|
||||
* [x] [`_mm512_reduce_max_epi32`]
|
||||
* [x] [`_mm512_reduce_max_epi64`]
|
||||
* [x] [`_mm512_reduce_max_epu32`]
|
||||
* [x] [`_mm512_reduce_max_epu64`]
|
||||
* [x] [`_mm512_reduce_max_pd`]
|
||||
* [x] [`_mm512_reduce_max_ps`]
|
||||
* [x] [`_mm512_reduce_min_epi32`]
|
||||
* [x] [`_mm512_reduce_min_epi64`]
|
||||
* [x] [`_mm512_reduce_min_epu32`]
|
||||
* [x] [`_mm512_reduce_min_epu64`]
|
||||
* [x] [`_mm512_reduce_min_pd`]
|
||||
* [x] [`_mm512_reduce_min_ps`]
|
||||
* [x] [`_mm512_reduce_mul_epi32`]
|
||||
* [x] [`_mm512_reduce_mul_epi64`]
|
||||
* [x] [`_mm512_reduce_mul_pd`]
|
||||
* [x] [`_mm512_reduce_mul_ps`]
|
||||
* [x] [`_mm512_reduce_or_epi32`]
|
||||
* [x] [`_mm512_reduce_or_epi64`]
|
||||
* [x] [`_mm512_rol_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rol_epi32&expand=5236)
|
||||
* [x] [`_mm512_rol_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rol_epi64&expand=5236)
|
||||
* [x] [`_mm512_rolv_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rolv_epi32&expand=5236)
|
||||
|
|
@ -1099,12 +1175,6 @@
|
|||
* [x] [`_mm512_stream_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_stream_pd&expand=5236)
|
||||
* [x] [`_mm512_stream_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_stream_ps&expand=5236)
|
||||
* [x] [`_mm512_stream_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_stream_si512&expand=5236)
|
||||
* [x] [`_mm512_sub_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sub_epi32&expand=5236)
|
||||
* [x] [`_mm512_sub_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sub_epi64&expand=5236)
|
||||
* [x] [`_mm512_sub_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sub_pd&expand=5236)
|
||||
* [x] [`_mm512_sub_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sub_ps&expand=5236)
|
||||
* [x] [`_mm512_sub_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sub_round_pd&expand=5236)
|
||||
* [x] [`_mm512_sub_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sub_round_ps&expand=5236)
|
||||
* [ ] [`_mm512_svml_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_svml_round_pd&expand=5236)
|
||||
* [x] [`_mm512_ternarylogic_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_ternarylogic_epi32&expand=5236)
|
||||
* [x] [`_mm512_ternarylogic_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_ternarylogic_epi64&expand=5236)
|
||||
|
|
|
|||
|
|
@ -245,6 +245,7 @@ simd_ty!(i64x2[i64]: i64, i64 | x0, x1);
|
|||
|
||||
simd_ty!(f32x4[f32]: f32, f32, f32, f32 | x0, x1, x2, x3);
|
||||
simd_ty!(f64x2[f64]: f64, f64 | x0, x1);
|
||||
simd_ty!(f64x4[f64]: f64, f64, f64, f64 | x0, x1, x2, x3);
|
||||
|
||||
simd_m_ty!(
|
||||
m8x16[i8]: i8,
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -495,6 +495,24 @@ impl m256Ext for __m256 {
|
|||
}
|
||||
}
|
||||
|
||||
#[allow(non_camel_case_types)]
|
||||
#[unstable(feature = "stdsimd_internal", issue = "none")]
|
||||
pub(crate) trait m256dExt: Sized {
|
||||
fn as_m256d(self) -> __m256d;
|
||||
|
||||
#[inline]
|
||||
fn as_f64x4(self) -> crate::core_arch::simd::f64x4 {
|
||||
unsafe { transmute(self.as_m256d()) }
|
||||
}
|
||||
}
|
||||
|
||||
impl m256dExt for __m256d {
|
||||
#[inline]
|
||||
fn as_m256d(self) -> Self {
|
||||
self
|
||||
}
|
||||
}
|
||||
|
||||
#[allow(non_camel_case_types)]
|
||||
#[unstable(feature = "stdsimd_internal", issue = "none")]
|
||||
pub(crate) trait m512iExt: Sized {
|
||||
|
|
|
|||
|
|
@ -15,33 +15,60 @@ mod tests {
|
|||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_abs_epi64() {
|
||||
let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
|
||||
let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
|
||||
let r = _mm512_abs_epi64(a);
|
||||
let e = _mm512_setr_epi64(0, 1, 1, i64::MAX, i64::MAX.wrapping_add(1), 100, 100, 32);
|
||||
let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MAX.wrapping_add(1), 100, 100, 32);
|
||||
assert_eq_m512i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_abs_epi64() {
|
||||
let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
|
||||
let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
|
||||
let r = _mm512_mask_abs_epi64(a, 0, a);
|
||||
assert_eq_m512i(r, a);
|
||||
let r = _mm512_mask_abs_epi64(a, 0b00001111, a);
|
||||
let e = _mm512_setr_epi64(0, 1, 1, i64::MAX, i64::MIN, 100, -100, -32);
|
||||
let r = _mm512_mask_abs_epi64(a, 0b11111111, a);
|
||||
let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MIN, 100, 100, 32);
|
||||
assert_eq_m512i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_maskz_abs_epi64() {
|
||||
#[rustfmt::skip]
|
||||
let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
|
||||
let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
|
||||
let r = _mm512_maskz_abs_epi64(0, a);
|
||||
assert_eq_m512i(r, _mm512_setzero_si512());
|
||||
let r = _mm512_maskz_abs_epi64(0b00001111, a);
|
||||
let e = _mm512_setr_epi64(0, 1, 1, i64::MAX, 0, 0, 0, 0);
|
||||
let r = _mm512_maskz_abs_epi64(0b11111111, a);
|
||||
let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MIN, 100, 100, 32);
|
||||
assert_eq_m512i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm256_abs_epi64() {
|
||||
let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
|
||||
let r = _mm256_abs_epi64(a);
|
||||
let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
|
||||
assert_eq_m256i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm256_mask_abs_epi64() {
|
||||
let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
|
||||
let r = _mm256_mask_abs_epi64(a, 0, a);
|
||||
assert_eq_m256i(r, a);
|
||||
let r = _mm256_mask_abs_epi64(a, 0b00001111, a);
|
||||
let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
|
||||
assert_eq_m256i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm256_maskz_abs_epi64() {
|
||||
let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
|
||||
let r = _mm256_maskz_abs_epi64(0, a);
|
||||
assert_eq_m256i(r, _mm256_setzero_si256());
|
||||
let r = _mm256_maskz_abs_epi64(0b00001111, a);
|
||||
let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
|
||||
assert_eq_m256i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_abs_pd() {
|
||||
let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
|
||||
|
|
@ -60,15 +87,6 @@ mod tests {
|
|||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_add_epi64() {
|
||||
let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
|
||||
let b = _mm512_set1_epi64(1);
|
||||
let r = _mm512_add_epi64(a, b);
|
||||
let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, i64::MIN + 1, 101, -99, -31);
|
||||
assert_eq_m512i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_mov_epi64() {
|
||||
let src = _mm512_set1_epi64(1);
|
||||
|
|
@ -107,6 +125,15 @@ mod tests {
|
|||
assert_eq_m512d(r, a);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_add_epi64() {
|
||||
let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
|
||||
let b = _mm512_set1_epi64(1);
|
||||
let r = _mm512_add_epi64(a, b);
|
||||
let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, i64::MIN + 1, 101, -99, -31);
|
||||
assert_eq_m512i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_add_epi64() {
|
||||
let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
|
||||
|
|
@ -120,11 +147,7 @@ mod tests {
|
|||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_maskz_add_epi64() {
|
||||
#[rustfmt::skip]
|
||||
let a = _mm512_setr_epi64(
|
||||
0, 1, -1, i64::MAX,
|
||||
i64::MIN, 100, -100, -32
|
||||
);
|
||||
let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
|
||||
let b = _mm512_set1_epi64(1);
|
||||
let r = _mm512_maskz_add_epi64(0, a, b);
|
||||
assert_eq_m512i(r, _mm512_setzero_si512());
|
||||
|
|
@ -133,6 +156,50 @@ mod tests {
|
|||
assert_eq_m512i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm256_mask_add_epi64() {
|
||||
let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
|
||||
let b = _mm256_set1_epi64x(1);
|
||||
let r = _mm256_mask_add_epi64(a, 0, a, b);
|
||||
assert_eq_m256i(r, a);
|
||||
let r = _mm256_mask_add_epi64(a, 0b00001111, a, b);
|
||||
let e = _mm256_set_epi64x(2, 0, i64::MIN, i64::MIN + 1);
|
||||
assert_eq_m256i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm256_maskz_add_epi64() {
|
||||
let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
|
||||
let b = _mm256_set1_epi64x(1);
|
||||
let r = _mm256_maskz_add_epi64(0, a, b);
|
||||
assert_eq_m256i(r, _mm256_setzero_si256());
|
||||
let r = _mm256_maskz_add_epi64(0b00001111, a, b);
|
||||
let e = _mm256_set_epi64x(2, 0, i64::MIN, i64::MIN + 1);
|
||||
assert_eq_m256i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm_mask_add_epi64() {
|
||||
let a = _mm_set_epi64x(i64::MAX, i64::MIN);
|
||||
let b = _mm_set1_epi64x(1);
|
||||
let r = _mm_mask_add_epi64(a, 0, a, b);
|
||||
assert_eq_m128i(r, a);
|
||||
let r = _mm_mask_add_epi64(a, 0b00000011, a, b);
|
||||
let e = _mm_set_epi64x(i64::MIN, i64::MIN + 1);
|
||||
assert_eq_m128i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm_maskz_add_epi64() {
|
||||
let a = _mm_set_epi64x(i64::MAX, i64::MIN);
|
||||
let b = _mm_set1_epi64x(1);
|
||||
let r = _mm_maskz_add_epi64(0, a, b);
|
||||
assert_eq_m128i(r, _mm_setzero_si128());
|
||||
let r = _mm_maskz_add_epi64(0b00000011, a, b);
|
||||
let e = _mm_set_epi64x(i64::MIN, i64::MIN + 1);
|
||||
assert_eq_m128i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_add_pd() {
|
||||
let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
|
||||
|
|
@ -164,6 +231,50 @@ mod tests {
|
|||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm256_mask_add_pd() {
|
||||
let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
|
||||
let b = _mm256_set1_pd(1.);
|
||||
let r = _mm256_mask_add_pd(a, 0, a, b);
|
||||
assert_eq_m256d(r, a);
|
||||
let r = _mm256_mask_add_pd(a, 0b00001111, a, b);
|
||||
let e = _mm256_set_pd(2., 0., f64::MAX, f64::MIN + 1.);
|
||||
assert_eq_m256d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm256_maskz_add_pd() {
|
||||
let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
|
||||
let b = _mm256_set1_pd(1.);
|
||||
let r = _mm256_maskz_add_pd(0, a, b);
|
||||
assert_eq_m256d(r, _mm256_setzero_pd());
|
||||
let r = _mm256_maskz_add_pd(0b00001111, a, b);
|
||||
let e = _mm256_set_pd(2., 0., f64::MAX, f64::MIN + 1.);
|
||||
assert_eq_m256d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm_mask_add_pd() {
|
||||
let a = _mm_set_pd(f64::MAX, f64::MIN);
|
||||
let b = _mm_set1_pd(1.);
|
||||
let r = _mm_mask_add_pd(a, 0, a, b);
|
||||
assert_eq_m128d(r, a);
|
||||
let r = _mm_mask_add_pd(a, 0b00000011, a, b);
|
||||
let e = _mm_set_pd(f64::MAX, f64::MIN + 1.);
|
||||
assert_eq_m128d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm_maskz_add_pd() {
|
||||
let a = _mm_set_pd(f64::MAX, f64::MIN);
|
||||
let b = _mm_set1_pd(1.);
|
||||
let r = _mm_maskz_add_pd(0, a, b);
|
||||
assert_eq_m128d(r, _mm_setzero_pd());
|
||||
let r = _mm_maskz_add_pd(0b00000011, a, b);
|
||||
let e = _mm_set_pd(f64::MAX, f64::MIN + 1.);
|
||||
assert_eq_m128d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_sub_epi64() {
|
||||
let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
|
||||
|
|
@ -195,6 +306,50 @@ mod tests {
|
|||
assert_eq_m512i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm256_mask_sub_epi64() {
|
||||
let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
|
||||
let b = _mm256_set1_epi64x(1);
|
||||
let r = _mm256_mask_sub_epi64(a, 0, a, b);
|
||||
assert_eq_m256i(r, a);
|
||||
let r = _mm256_mask_sub_epi64(a, 0b00001111, a, b);
|
||||
let e = _mm256_set_epi64x(0, -2, i64::MAX - 1, i64::MAX);
|
||||
assert_eq_m256i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm256_maskz_sub_epi64() {
|
||||
let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
|
||||
let b = _mm256_set1_epi64x(1);
|
||||
let r = _mm256_maskz_sub_epi64(0, a, b);
|
||||
assert_eq_m256i(r, _mm256_setzero_si256());
|
||||
let r = _mm256_maskz_sub_epi64(0b00001111, a, b);
|
||||
let e = _mm256_set_epi64x(0, -2, i64::MAX - 1, i64::MAX);
|
||||
assert_eq_m256i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm_mask_sub_epi64() {
|
||||
let a = _mm_set_epi64x(i64::MAX, i64::MIN);
|
||||
let b = _mm_set1_epi64x(1);
|
||||
let r = _mm_mask_sub_epi64(a, 0, a, b);
|
||||
assert_eq_m128i(r, a);
|
||||
let r = _mm_mask_sub_epi64(a, 0b00000011, a, b);
|
||||
let e = _mm_set_epi64x(i64::MAX - 1, i64::MAX);
|
||||
assert_eq_m128i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm_maskz_sub_epi64() {
|
||||
let a = _mm_set_epi64x(i64::MAX, i64::MIN);
|
||||
let b = _mm_set1_epi64x(1);
|
||||
let r = _mm_maskz_sub_epi64(0, a, b);
|
||||
assert_eq_m128i(r, _mm_setzero_si128());
|
||||
let r = _mm_maskz_sub_epi64(0b00000011, a, b);
|
||||
let e = _mm_set_epi64x(i64::MAX - 1, i64::MAX);
|
||||
assert_eq_m128i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_sub_pd() {
|
||||
let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
|
||||
|
|
@ -226,9 +381,53 @@ mod tests {
|
|||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm256_mask_sub_pd() {
|
||||
let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
|
||||
let b = _mm256_set1_pd(1.);
|
||||
let r = _mm256_mask_sub_pd(a, 0, a, b);
|
||||
assert_eq_m256d(r, a);
|
||||
let r = _mm256_mask_sub_pd(a, 0b00001111, a, b);
|
||||
let e = _mm256_set_pd(0., -2., f64::MAX - 1., f64::MIN);
|
||||
assert_eq_m256d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm256_maskz_sub_pd() {
|
||||
let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
|
||||
let b = _mm256_set1_pd(1.);
|
||||
let r = _mm256_maskz_sub_pd(0, a, b);
|
||||
assert_eq_m256d(r, _mm256_setzero_pd());
|
||||
let r = _mm256_maskz_sub_pd(0b00001111, a, b);
|
||||
let e = _mm256_set_pd(0., -2., f64::MAX - 1., f64::MIN);
|
||||
assert_eq_m256d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm_mask_sub_pd() {
|
||||
let a = _mm_set_pd(f64::MAX, f64::MIN);
|
||||
let b = _mm_set1_pd(1.);
|
||||
let r = _mm_mask_sub_pd(a, 0, a, b);
|
||||
assert_eq_m128d(r, a);
|
||||
let r = _mm_mask_sub_pd(a, 0b00000011, a, b);
|
||||
let e = _mm_set_pd(f64::MAX - 1., f64::MIN);
|
||||
assert_eq_m128d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm_maskz_sub_pd() {
|
||||
let a = _mm_set_pd(f64::MAX, f64::MIN);
|
||||
let b = _mm_set1_pd(1.);
|
||||
let r = _mm_maskz_sub_pd(0, a, b);
|
||||
assert_eq_m128d(r, _mm_setzero_pd());
|
||||
let r = _mm_maskz_sub_pd(0b00000011, a, b);
|
||||
let e = _mm_set_pd(f64::MAX - 1., f64::MIN);
|
||||
assert_eq_m128d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mul_epi32() {
|
||||
let a = _mm512_setr_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
|
||||
let a = _mm512_set1_epi32(1);
|
||||
let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
|
||||
let r = _mm512_mul_epi32(a, b);
|
||||
let e = _mm512_set_epi64(15, 13, 11, 9, 7, 5, 3, 1);
|
||||
|
|
@ -237,27 +436,22 @@ mod tests {
|
|||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_mul_epi32() {
|
||||
let a = _mm512_setr_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
|
||||
let a = _mm512_set1_epi32(1);
|
||||
let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
|
||||
let r = _mm512_mask_mul_epi32(a, 0, a, b);
|
||||
assert_eq_m512i(r, a);
|
||||
let r = _mm512_mask_mul_epi32(a, 0b00001111, a, b);
|
||||
#[rustfmt::skip]
|
||||
let e = _mm512_set_epi64(
|
||||
1 | 1 << 32,
|
||||
1 | 1 << 32,
|
||||
1 | 1 << 32,
|
||||
1 | 1 << 32,
|
||||
7,
|
||||
5,
|
||||
3,
|
||||
1,
|
||||
1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32,
|
||||
7, 5, 3, 1,
|
||||
);
|
||||
assert_eq_m512i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_maskz_mul_epi32() {
|
||||
let a = _mm512_setr_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
|
||||
let a = _mm512_set1_epi32(1);
|
||||
let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
|
||||
let r = _mm512_maskz_mul_epi32(0, a, b);
|
||||
assert_eq_m512i(r, _mm512_setzero_si512());
|
||||
|
|
@ -266,9 +460,53 @@ mod tests {
|
|||
assert_eq_m512i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm256_mask_mul_epi32() {
|
||||
let a = _mm256_set1_epi32(1);
|
||||
let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
|
||||
let r = _mm256_mask_mul_epi32(a, 0, a, b);
|
||||
assert_eq_m256i(r, a);
|
||||
let r = _mm256_mask_mul_epi32(a, 0b00001111, a, b);
|
||||
let e = _mm256_set_epi64x(2, 4, 6, 8);
|
||||
assert_eq_m256i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm256_maskz_mul_epi32() {
|
||||
let a = _mm256_set1_epi32(1);
|
||||
let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
|
||||
let r = _mm256_maskz_mul_epi32(0, a, b);
|
||||
assert_eq_m256i(r, _mm256_setzero_si256());
|
||||
let r = _mm256_maskz_mul_epi32(0b00001111, a, b);
|
||||
let e = _mm256_set_epi64x(2, 4, 6, 8);
|
||||
assert_eq_m256i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm_mask_mul_epi32() {
|
||||
let a = _mm_set1_epi32(1);
|
||||
let b = _mm_set_epi32(1, 2, 3, 4);
|
||||
let r = _mm_mask_mul_epi32(a, 0, a, b);
|
||||
assert_eq_m128i(r, a);
|
||||
let r = _mm_mask_mul_epi32(a, 0b00000011, a, b);
|
||||
let e = _mm_set_epi64x(2, 4);
|
||||
assert_eq_m128i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm_maskz_mul_epi32() {
|
||||
let a = _mm_set1_epi32(1);
|
||||
let b = _mm_set_epi32(1, 2, 3, 4);
|
||||
let r = _mm_maskz_mul_epi32(0, a, b);
|
||||
assert_eq_m128i(r, _mm_setzero_si128());
|
||||
let r = _mm_maskz_mul_epi32(0b00000011, a, b);
|
||||
let e = _mm_set_epi64x(2, 4);
|
||||
assert_eq_m128i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mul_epu32() {
|
||||
let a = _mm512_setr_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
|
||||
let a = _mm512_set1_epi32(1);
|
||||
let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
|
||||
let r = _mm512_mul_epu32(a, b);
|
||||
let e = _mm512_set_epi64(15, 13, 11, 9, 7, 5, 3, 1);
|
||||
|
|
@ -277,27 +515,22 @@ mod tests {
|
|||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_mul_epu32() {
|
||||
let a = _mm512_setr_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
|
||||
let a = _mm512_set1_epi32(1);
|
||||
let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
|
||||
let r = _mm512_mask_mul_epu32(a, 0, a, b);
|
||||
assert_eq_m512i(r, a);
|
||||
let r = _mm512_mask_mul_epu32(a, 0b00001111, a, b);
|
||||
#[rustfmt::skip]
|
||||
let e = _mm512_set_epi64(
|
||||
1 | 1 << 32,
|
||||
1 | 1 << 32,
|
||||
1 | 1 << 32,
|
||||
1 | 1 << 32,
|
||||
7,
|
||||
5,
|
||||
3,
|
||||
1,
|
||||
1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32,
|
||||
7, 5, 3, 1,
|
||||
);
|
||||
assert_eq_m512i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_maskz_mul_epu32() {
|
||||
let a = _mm512_setr_epi32(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
|
||||
let a = _mm512_set1_epi32(1);
|
||||
let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
|
||||
let r = _mm512_maskz_mul_epu32(0, a, b);
|
||||
assert_eq_m512i(r, _mm512_setzero_si512());
|
||||
|
|
@ -306,6 +539,50 @@ mod tests {
|
|||
assert_eq_m512i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm256_mask_mul_epu32() {
|
||||
let a = _mm256_set1_epi32(1);
|
||||
let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
|
||||
let r = _mm256_mask_mul_epu32(a, 0, a, b);
|
||||
assert_eq_m256i(r, a);
|
||||
let r = _mm256_mask_mul_epu32(a, 0b00001111, a, b);
|
||||
let e = _mm256_set_epi64x(2, 4, 6, 8);
|
||||
assert_eq_m256i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm256_maskz_mul_epu32() {
|
||||
let a = _mm256_set1_epi32(1);
|
||||
let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
|
||||
let r = _mm256_maskz_mul_epu32(0, a, b);
|
||||
assert_eq_m256i(r, _mm256_setzero_si256());
|
||||
let r = _mm256_maskz_mul_epu32(0b00001111, a, b);
|
||||
let e = _mm256_set_epi64x(2, 4, 6, 8);
|
||||
assert_eq_m256i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm_mask_mul_epu32() {
|
||||
let a = _mm_set1_epi32(1);
|
||||
let b = _mm_set_epi32(1, 2, 3, 4);
|
||||
let r = _mm_mask_mul_epu32(a, 0, a, b);
|
||||
assert_eq_m128i(r, a);
|
||||
let r = _mm_mask_mul_epu32(a, 0b00000011, a, b);
|
||||
let e = _mm_set_epi64x(2, 4);
|
||||
assert_eq_m128i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm_maskz_mul_epu32() {
|
||||
let a = _mm_set1_epi32(1);
|
||||
let b = _mm_set_epi32(1, 2, 3, 4);
|
||||
let r = _mm_maskz_mul_epu32(0, a, b);
|
||||
assert_eq_m128i(r, _mm_setzero_si128());
|
||||
let r = _mm_maskz_mul_epu32(0b00000011, a, b);
|
||||
let e = _mm_set_epi64x(2, 4);
|
||||
assert_eq_m128i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mullox_epi64() {
|
||||
let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
|
||||
|
|
@ -331,15 +608,10 @@ mod tests {
|
|||
let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
|
||||
let b = _mm512_set1_pd(2.);
|
||||
let r = _mm512_mul_pd(a, b);
|
||||
#[rustfmt::skip]
|
||||
let e = _mm512_setr_pd(
|
||||
0.,
|
||||
2.,
|
||||
f64::INFINITY,
|
||||
f64::NEG_INFINITY,
|
||||
f64::INFINITY,
|
||||
f64::NEG_INFINITY,
|
||||
-200.,
|
||||
-64.,
|
||||
0., 2., f64::INFINITY, f64::NEG_INFINITY,
|
||||
f64::INFINITY, f64::NEG_INFINITY, -200., -64.,
|
||||
);
|
||||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
|
@ -351,15 +623,10 @@ mod tests {
|
|||
let r = _mm512_mask_mul_pd(a, 0, a, b);
|
||||
assert_eq_m512d(r, a);
|
||||
let r = _mm512_mask_mul_pd(a, 0b00001111, a, b);
|
||||
#[rustfmt::skip]
|
||||
let e = _mm512_setr_pd(
|
||||
0.,
|
||||
2.,
|
||||
f64::INFINITY,
|
||||
f64::NEG_INFINITY,
|
||||
f64::MAX,
|
||||
f64::MIN,
|
||||
-100.,
|
||||
-32.,
|
||||
0., 2., f64::INFINITY, f64::NEG_INFINITY,
|
||||
f64::MAX, f64::MIN, -100., -32.,
|
||||
);
|
||||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
|
@ -375,20 +642,59 @@ mod tests {
|
|||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm256_mask_mul_pd() {
|
||||
let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
|
||||
let b = _mm256_set1_pd(2.);
|
||||
let r = _mm256_mask_mul_pd(a, 0, a, b);
|
||||
assert_eq_m256d(r, a);
|
||||
let r = _mm256_mask_mul_pd(a, 0b00001111, a, b);
|
||||
let e = _mm256_set_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY);
|
||||
assert_eq_m256d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm256_maskz_mul_pd() {
|
||||
let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
|
||||
let b = _mm256_set1_pd(2.);
|
||||
let r = _mm256_maskz_mul_pd(0, a, b);
|
||||
assert_eq_m256d(r, _mm256_setzero_pd());
|
||||
let r = _mm256_maskz_mul_pd(0b00001111, a, b);
|
||||
let e = _mm256_set_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY);
|
||||
assert_eq_m256d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm_mask_mul_pd() {
|
||||
let a = _mm_set_pd(f64::MAX, f64::MIN);
|
||||
let b = _mm_set1_pd(2.);
|
||||
let r = _mm_mask_mul_pd(a, 0, a, b);
|
||||
assert_eq_m128d(r, a);
|
||||
let r = _mm_mask_mul_pd(a, 0b00000011, a, b);
|
||||
let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
|
||||
assert_eq_m128d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm_maskz_mul_pd() {
|
||||
let a = _mm_set_pd(f64::MAX, f64::MIN);
|
||||
let b = _mm_set1_pd(2.);
|
||||
let r = _mm_maskz_mul_pd(0, a, b);
|
||||
assert_eq_m128d(r, _mm_setzero_pd());
|
||||
let r = _mm_maskz_mul_pd(0b00000011, a, b);
|
||||
let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
|
||||
assert_eq_m128d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_div_pd() {
|
||||
let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
|
||||
let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
|
||||
let r = _mm512_div_pd(a, b);
|
||||
#[rustfmt::skip]
|
||||
let e = _mm512_setr_pd(
|
||||
0.,
|
||||
0.5,
|
||||
f64::INFINITY,
|
||||
f64::NEG_INFINITY,
|
||||
f64::INFINITY,
|
||||
f64::NEG_INFINITY,
|
||||
-50.,
|
||||
-16.,
|
||||
0., 0.5, f64::INFINITY, f64::NEG_INFINITY,
|
||||
f64::INFINITY, f64::NEG_INFINITY, -50., -16.,
|
||||
);
|
||||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
|
@ -400,15 +706,10 @@ mod tests {
|
|||
let r = _mm512_mask_div_pd(a, 0, a, b);
|
||||
assert_eq_m512d(r, a);
|
||||
let r = _mm512_mask_div_pd(a, 0b00001111, a, b);
|
||||
#[rustfmt::skip]
|
||||
let e = _mm512_setr_pd(
|
||||
0.,
|
||||
0.5,
|
||||
f64::INFINITY,
|
||||
f64::NEG_INFINITY,
|
||||
f64::MAX,
|
||||
f64::MIN,
|
||||
-100.,
|
||||
-32.,
|
||||
0., 0.5, f64::INFINITY, f64::NEG_INFINITY,
|
||||
f64::MAX, f64::MIN, -100., -32.,
|
||||
);
|
||||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
|
@ -424,6 +725,50 @@ mod tests {
|
|||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm256_mask_div_pd() {
|
||||
let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
|
||||
let b = _mm256_set_pd(2., 2., 0., 0.);
|
||||
let r = _mm256_mask_div_pd(a, 0, a, b);
|
||||
assert_eq_m256d(r, a);
|
||||
let r = _mm256_mask_div_pd(a, 0b00001111, a, b);
|
||||
let e = _mm256_set_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY);
|
||||
assert_eq_m256d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm256_maskz_div_pd() {
|
||||
let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
|
||||
let b = _mm256_set_pd(2., 2., 0., 0.);
|
||||
let r = _mm256_maskz_div_pd(0, a, b);
|
||||
assert_eq_m256d(r, _mm256_setzero_pd());
|
||||
let r = _mm256_maskz_div_pd(0b00001111, a, b);
|
||||
let e = _mm256_set_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY);
|
||||
assert_eq_m256d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm_mask_div_pd() {
|
||||
let a = _mm_set_pd(f64::MAX, f64::MIN);
|
||||
let b = _mm_set_pd(0., 0.);
|
||||
let r = _mm_mask_div_pd(a, 0, a, b);
|
||||
assert_eq_m128d(r, a);
|
||||
let r = _mm_mask_div_pd(a, 0b00000011, a, b);
|
||||
let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
|
||||
assert_eq_m128d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f,avx512vl")]
|
||||
unsafe fn test_mm_maskz_div_pd() {
|
||||
let a = _mm_set_pd(f64::MAX, f64::MIN);
|
||||
let b = _mm_set_pd(0., 0.);
|
||||
let r = _mm_maskz_div_pd(0, a, b);
|
||||
assert_eq_m128d(r, _mm_setzero_pd());
|
||||
let r = _mm_maskz_div_pd(0b00000011, a, b);
|
||||
let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
|
||||
assert_eq_m128d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_max_epi64() {
|
||||
let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue