From 7fd998870de3a16393252b1eaf3e79200fd5bacc Mon Sep 17 00:00:00 2001 From: Gijs Burghoorn Date: Tue, 22 Aug 2023 12:23:51 +0200 Subject: [PATCH] Fix: Change to 'rustc_legacy_const_generics' --- .../crates/core_arch/src/riscv32/zk.rs | 125 ++++++----------- .../crates/core_arch/src/riscv64/zk.rs | 52 +++---- .../crates/core_arch/src/riscv_shared/zk.rs | 127 +++++++++--------- 3 files changed, 120 insertions(+), 184 deletions(-) diff --git a/library/stdarch/crates/core_arch/src/riscv32/zk.rs b/library/stdarch/crates/core_arch/src/riscv32/zk.rs index 81bcd0d2dfc3..62a749230bf6 100644 --- a/library/stdarch/crates/core_arch/src/riscv32/zk.rs +++ b/library/stdarch/crates/core_arch/src/riscv32/zk.rs @@ -1,19 +1,28 @@ -#[allow(unused)] use core::arch::asm; -#[allow(unused)] -macro_rules! constify_imm2 { - ($imm2:expr, $expand:ident) => { - #[allow(overflowing_literals)] - match $imm2 & 0b11 { - 0b00 => $expand!(0), - 0b01 => $expand!(1), - 0b10 => $expand!(2), - _ => $expand!(3), - } +macro_rules! static_assert_imm2 { + ($imm:ident) => { + static_assert!( + $imm < 4, + "Immediate value allowed to be a constant from 0 up to including 3" + ) }; } +extern "unadjusted" { + #[link_name = "llvm.riscv.aes32esi"] + fn _aes32esi(rs1: i32, rs2: i32, bs: i32) -> i32; + + #[link_name = "llvm.riscv.aes32esmi"] + fn _aes32esmi(rs1: i32, rs2: i32, bs: i32) -> i32; + + #[link_name = "llvm.riscv.aes32dsi"] + fn _aes32dsi(rs1: i32, rs2: i32, bs: i32) -> i32; + + #[link_name = "llvm.riscv.aes32dsmi"] + fn _aes32dsmi(rs1: i32, rs2: i32, bs: i32) -> i32; +} + /// AES final round encryption instruction for RV32. /// /// This instruction sources a single byte from rs2 according to bs. To this it applies the @@ -29,32 +38,20 @@ macro_rules! constify_imm2 { /// /// # Note /// -/// The `bs` parameter is expected to be a constant value and only the bottom 2 bits of `bs` are +/// The `BS` parameter is expected to be a constant value and only the bottom 2 bits of `bs` are /// used. /// /// # Safety /// /// This function is safe to use if the `zkne` target feature is present. #[target_feature(enable = "zkne")] +#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(aes32esi))] #[inline] -pub unsafe fn aes32esi(rs1: u32, rs2: u32, bs: u8) -> u32 { - macro_rules! aes32esi { - ($imm2:expr) => {{ - let value: u32; - unsafe { - asm!( - concat!("aes32esi {rd},{rs1},{rs2},", $imm2), - rd = lateout(reg) value, - rs1 = in(reg) rs1, - rs2 = in(reg) rs2, - options(pure, nomem, nostack), - ); - } - value - }} - } - constify_imm2!(bs, aes32esi) +pub unsafe fn aes32esi(rs1: u32, rs2: u32) -> u32 { + static_assert_imm2!(BS); + + _aes32esi(rs1 as i32, rs2 as i32, BS as i32) as u32 } /// AES middle round encryption instruction for RV32 with. @@ -79,25 +76,13 @@ pub unsafe fn aes32esi(rs1: u32, rs2: u32, bs: u8) -> u32 { /// /// This function is safe to use if the `zkne` target feature is present. #[target_feature(enable = "zkne")] +#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(aes32esmi))] #[inline] -pub unsafe fn aes32esmi(rs1: u32, rs2: u32, bs: u8) -> u32 { - macro_rules! aes32esmi { - ($imm2:expr) => {{ - let value: u32; - unsafe { - asm!( - concat!("aes32esmi {rd},{rs1},{rs2},", $imm2), - rd = lateout(reg) value, - rs1 = in(reg) rs1, - rs2 = in(reg) rs2, - options(pure, nomem, nostack), - ); - } - value - }} - } - constify_imm2!(bs, aes32esmi) +pub unsafe fn aes32esmi(rs1: u32, rs2: u32) -> u32 { + static_assert_imm2!(BS); + + _aes32esmi(rs1 as i32, rs2 as i32, BS as i32) as u32 } /// AES final round decryption instruction for RV32. @@ -114,32 +99,20 @@ pub unsafe fn aes32esmi(rs1: u32, rs2: u32, bs: u8) -> u32 { /// /// # Note /// -/// The `bs` parameter is expected to be a constant value and only the bottom 2 bits of `bs` are +/// The `BS` parameter is expected to be a constant value and only the bottom 2 bits of `bs` are /// used. /// /// # Safety /// /// This function is safe to use if the `zknd` target feature is present. #[target_feature(enable = "zknd")] +#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(aes32dsi))] #[inline] -pub unsafe fn aes32dsi(rs1: u32, rs2: u32, bs: u8) -> u32 { - macro_rules! aes32dsi { - ($imm2:expr) => {{ - let value: u32; - unsafe { - asm!( - concat!("aes32dsi {rd},{rs1},{rs2},", $imm2), - rd = lateout(reg) value, - rs1 = in(reg) rs1, - rs2 = in(reg) rs2, - options(pure, nomem, nostack), - ); - } - value - }} - } - constify_imm2!(bs, aes32dsi) +pub unsafe fn aes32dsi(rs1: u32, rs2: u32) -> u32 { + static_assert_imm2!(BS); + + _aes32dsi(rs1 as i32, rs2 as i32, BS as i32) as u32 } /// AES middle round decryption instruction for RV32. @@ -157,32 +130,20 @@ pub unsafe fn aes32dsi(rs1: u32, rs2: u32, bs: u8) -> u32 { /// /// # Note /// -/// The `bs` parameter is expected to be a constant value and only the bottom 2 bits of `bs` are +/// The `BS` parameter is expected to be a constant value and only the bottom 2 bits of `bs` are /// used. /// /// # Safety /// /// This function is safe to use if the `zknd` target feature is present. #[target_feature(enable = "zknd")] +#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(aes32dsmi))] #[inline] -pub unsafe fn aes32dsmi(rs1: u32, rs2: u32, bs: u8) -> u32 { - macro_rules! aes32dsmi { - ($imm2:expr) => {{ - let value: u32; - unsafe { - asm!( - concat!("aes32dsmi {rd},{rs1},{rs2},", $imm2), - rd = lateout(reg) value, - rs1 = in(reg) rs1, - rs2 = in(reg) rs2, - options(pure, nomem, nostack), - ); - } - value - }} - } - constify_imm2!(bs, aes32dsmi) +pub unsafe fn aes32dsmi(rs1: u32, rs2: u32) -> u32 { + static_assert_imm2!(BS); + + _aes32dsmi(rs1 as i32, rs2 as i32, BS as i32) as u32 } /// Place upper/lower halves of the source register into odd/even bits of the destination diff --git a/library/stdarch/crates/core_arch/src/riscv64/zk.rs b/library/stdarch/crates/core_arch/src/riscv64/zk.rs index 8f2884668ab8..017fa1c04178 100644 --- a/library/stdarch/crates/core_arch/src/riscv64/zk.rs +++ b/library/stdarch/crates/core_arch/src/riscv64/zk.rs @@ -1,25 +1,19 @@ -#[allow(unused)] use core::arch::asm; -#[allow(unused)] -macro_rules! constify_imm_0_until_10 { - ($imm2:expr, $expand:ident) => { - match $imm2 { - 1 => $expand!(1), - 2 => $expand!(2), - 3 => $expand!(3), - 4 => $expand!(4), - 5 => $expand!(5), - 6 => $expand!(6), - 7 => $expand!(7), - 8 => $expand!(8), - 9 => $expand!(9), - 10 => $expand!(10), - _ => $expand!(0), - } +macro_rules! static_assert_imm_0_until_10 { + ($imm:ident) => { + static_assert!( + $imm <= 10, + "Immediate value allowed to be a constant from 0 up to including 10" + ) }; } +extern "unadjusted" { + #[link_name = "llvm.riscv.aes64ks1i"] + fn _aes64ks1i(rs1: i64, rnum: i32) -> i64; +} + /// AES final round encryption instruction for RV64. /// /// Uses the two 64-bit source registers to represent the entire AES state, and produces half @@ -168,31 +162,19 @@ pub unsafe fn aes64dsm(rs1: u64, rs2: u64) -> u64 { /// /// # Note /// -/// The `rnum` parameter is expected to be a constant value inside the range of `0..=10`, if a -/// value outside the valid range is given it uses `rnum=0`. +/// The `RNUM` parameter is expected to be a constant value inside the range of `0..=10`. /// /// # Safety /// /// This function is safe to use if the `zkne` or `zknd` target feature is present. #[target_feature(enable = "zkne", enable = "zknd")] +#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(aes64ks1i))] #[inline] -pub unsafe fn aes64ks1i(rs1: u64, rnum: u8) -> u64 { - macro_rules! aes64ks1i { - ($imm_0_until_10:expr) => {{ - let value: u64; - unsafe { - asm!( - concat!("aes64ks1i {rd},{rs1},", $imm_0_until_10), - rd = lateout(reg) value, - rs1 = in(reg) rs1, - options(pure, nomem, nostack), - ) - } - value - }} - } - constify_imm_0_until_10!(rnum, aes64ks1i) +pub unsafe fn aes64ks1i(rs1: u64) -> u64 { + static_assert_imm_0_until_10!(RNUM); + + _aes64ks1i(rs1 as i64, RNUM as i32) as u64 } /// This instruction implements part of the KeySchedule operation for the AES Block cipher. diff --git a/library/stdarch/crates/core_arch/src/riscv_shared/zk.rs b/library/stdarch/crates/core_arch/src/riscv_shared/zk.rs index 8402c267567a..2b1644fc0afd 100644 --- a/library/stdarch/crates/core_arch/src/riscv_shared/zk.rs +++ b/library/stdarch/crates/core_arch/src/riscv_shared/zk.rs @@ -1,19 +1,40 @@ -#[allow(unused)] use core::arch::asm; -#[allow(unused)] -macro_rules! constify_imm2 { - ($imm2:expr, $expand:ident) => { - #[allow(overflowing_literals)] - match $imm2 & 0b11 { - 0b00 => $expand!(0), - 0b01 => $expand!(1), - 0b10 => $expand!(2), - _ => $expand!(3), - } +macro_rules! static_assert_imm2 { + ($imm:ident) => { + static_assert!( + $imm < 4, + "Immediate value allowed to be a constant from 0 up to including 3" + ) }; } +extern "unadjusted" { + #[link_name = "llvm.riscv.sm4ed"] + fn _sm4ed(rs1: i32, rs2: i32, bs: i32) -> i32; + + #[link_name = "llvm.riscv.sm4ks"] + fn _sm4ks(rs1: i32, rs2: i32, bs: i32) -> i32; +} + +#[cfg(target_arch = "riscv32")] +extern "unadjusted" { + #[link_name = "llvm.riscv.xperm8.i32"] + fn _xperm8_32(rs1: i32, rs2: i32) -> i32; + + #[link_name = "llvm.riscv.xperm4.i32"] + fn _xperm4_32(rs1: i32, rs2: i32) -> i32; +} + +#[cfg(target_arch = "riscv64")] +extern "unadjusted" { + #[link_name = "llvm.riscv.xperm8.i64"] + fn _xperm8_64(rs1: i64, rs2: i64) -> i64; + + #[link_name = "llvm.riscv.xperm4.i64"] + fn _xperm4_64(rs1: i64, rs2: i64) -> i64; +} + /// Pack the low halves of rs1 and rs2 into rd. /// /// The pack instruction packs the XLEN/2-bit lower halves of rs1 and rs2 into rd, with rs1 in @@ -125,17 +146,15 @@ pub unsafe fn brev8(rs: usize) -> usize { #[cfg_attr(test, assert_instr(xperm8))] #[inline] pub unsafe fn xperm8(rs1: usize, rs2: usize) -> usize { - let value: usize; - unsafe { - asm!( - "xperm8 {rd},{rs1},{rs2}", - rd = lateout(reg) value, - rs1 = in(reg) rs1, - rs2 = in(reg) rs2, - options(pure, nomem, nostack), - ) + #[cfg(target_arch = "riscv32")] + { + _xperm8_32(rs1 as i32, rs2 as i32) as usize + } + + #[cfg(target_arch = "riscv64")] + { + _xperm8_64(rs1 as i64, rs2 as i64) as usize } - value } /// Nibble-wise lookup of indicies into a vector. @@ -158,17 +177,15 @@ pub unsafe fn xperm8(rs1: usize, rs2: usize) -> usize { #[cfg_attr(test, assert_instr(xperm4))] #[inline] pub unsafe fn xperm4(rs1: usize, rs2: usize) -> usize { - let value: usize; - unsafe { - asm!( - "xperm4 {rd},{rs1},{rs2}", - rd = lateout(reg) value, - rs1 = in(reg) rs1, - rs2 = in(reg) rs2, - options(pure, nomem, nostack), - ) + #[cfg(target_arch = "riscv32")] + { + _xperm4_32(rs1 as i32, rs2 as i32) as usize + } + + #[cfg(target_arch = "riscv64")] + { + _xperm4_64(rs1 as i64, rs2 as i64) as usize } - value } /// Implements the Sigma0 transformation function as used in the SHA2-256 hash function \[49\] @@ -328,7 +345,7 @@ pub unsafe fn sha256sum1(rs1: usize) -> usize { /// /// # Note /// -/// The `bs` parameter is expected to be a constant value and only the bottom 2 bits of `bs` are +/// The `BS` parameter is expected to be a constant value and only the bottom 2 bits of `bs` are /// used. /// /// # Safety @@ -381,25 +398,13 @@ pub unsafe fn sha256sum1(rs1: usize) -> usize { /// # } /// ``` #[target_feature(enable = "zksed")] +#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(sm4ed))] #[inline] -pub unsafe fn sm4ed(rs1: usize, rs2: usize, bs: u8) -> usize { - macro_rules! sm4ed { - ($imm2:expr) => {{ - let value: usize; - unsafe { - asm!( - concat!("sm4ed {rd},{rs1},{rs2},", $imm2), - rd = lateout(reg) value, - rs1 = in(reg) rs1, - rs2 = in(reg) rs2, - options(pure, nomem, nostack), - ) - } - value - }} - } - constify_imm2!(bs, sm4ed) +pub unsafe fn sm4ed(rs1: u32, rs2: u32) -> u32 { + static_assert_imm2!(BS); + + _sm4ed(rs1 as i32, rs2 as i32, BS as i32) as u32 } /// Accelerates the Key Schedule operation of the SM4 block cipher \[5, 31\] with `bs=0`. @@ -419,7 +424,7 @@ pub unsafe fn sm4ed(rs1: usize, rs2: usize, bs: u8) -> usize { /// /// # Note /// -/// The `bs` parameter is expected to be a constant value and only the bottom 2 bits of `bs` are +/// The `BS` parameter is expected to be a constant value and only the bottom 2 bits of `bs` are /// used. /// /// # Safety @@ -472,25 +477,13 @@ pub unsafe fn sm4ed(rs1: usize, rs2: usize, bs: u8) -> usize { /// # } /// ``` #[target_feature(enable = "zksed")] +#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(sm4ks))] #[inline] -pub unsafe fn sm4ks(rs1: usize, rs2: usize, bs: u8) -> usize { - macro_rules! sm4ks { - ($imm2:expr) => {{ - let value: usize; - unsafe { - asm!( - concat!("sm4ks {rd},{rs1},{rs2},", $imm2), - rd = lateout(reg) value, - rs1 = in(reg) rs1, - rs2 = in(reg) rs2, - options(pure, nomem, nostack), - ) - } - value - }} - } - constify_imm2!(bs, sm4ks) +pub unsafe fn sm4ks(rs1: u32, rs2: u32) -> u32 { + static_assert_imm2!(BS); + + _sm4ks(rs1 as i32, rs2 as i32, BS as i32) as u32 } /// Implements the P0 transformation function as used in the SM3 hash function [4, 30].