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feat - FEAT_LUT neon instrinsics

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James Barford-Evans 2025-03-03 08:38:16 +00:00 • committed by Amanieu d'Antras
parent 520dfd5210
commit 89c9c8ba9c
5 changed files with 1606 additions and 1 deletions
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397
library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
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@ -12826,6 +12826,403 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t {
ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
ret_val
}
#[doc = "Lookup table read with 2-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s8)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 1))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti2_lane_s8<const LANE: i32>(a: int8x8_t, b: uint8x8_t) -> int8x16_t {
static_assert!(LANE >= 0 && LANE <= 1);
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.vluti2.lane.v16i8.v8i8"
)]
fn _vluti2_lane_s8(a: int8x8_t, b: uint8x8_t, n: i32) -> int8x16_t;
}
_vluti2_lane_s8(a, b, LANE)
}
#[doc = "Lookup table read with 2-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_s8)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 1))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti2q_lane_s8<const LANE: i32>(a: int8x16_t, b: uint8x8_t) -> int8x16_t {
static_assert!(LANE >= 0 && LANE <= 1);
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.vluti2.lane.v16i8.v16i8"
)]
fn _vluti2q_lane_s8(a: int8x16_t, b: uint8x8_t, n: i32) -> int8x16_t;
}
_vluti2q_lane_s8(a, b, LANE)
}
#[doc = "Lookup table read with 2-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s16)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 1))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti2_lane_s16<const LANE: i32>(a: int16x4_t, b: uint8x8_t) -> int16x8_t {
static_assert!(LANE >= 0 && LANE <= 3);
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.vluti2.lane.v8i16.v4i16"
)]
fn _vluti2_lane_s16(a: int16x4_t, b: uint8x8_t, n: i32) -> int16x8_t;
}
_vluti2_lane_s16(a, b, LANE)
}
#[doc = "Lookup table read with 2-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_s16)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 1))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti2q_lane_s16<const LANE: i32>(a: int16x8_t, b: uint8x8_t) -> int16x8_t {
static_assert!(LANE >= 0 && LANE <= 3);
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.vluti2.lane.v8i16.v8i16"
)]
fn _vluti2q_lane_s16(a: int16x8_t, b: uint8x8_t, n: i32) -> int16x8_t;
}
_vluti2q_lane_s16(a, b, LANE)
}
#[doc = "Lookup table read with 2-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u8)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 1))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti2_lane_u8<const LANE: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t {
static_assert!(LANE >= 0 && LANE <= 1);
transmute(vluti2_lane_s8::<LANE>(transmute(a), b))
}
#[doc = "Lookup table read with 2-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u8)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 1))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti2q_lane_u8<const LANE: i32>(a: uint8x16_t, b: uint8x8_t) -> uint8x16_t {
static_assert!(LANE >= 0 && LANE <= 1);
transmute(vluti2q_lane_s8::<LANE>(transmute(a), b))
}
#[doc = "Lookup table read with 2-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u16)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 1))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti2_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint8x8_t) -> uint16x8_t {
static_assert!(LANE >= 0 && LANE <= 3);
transmute(vluti2_lane_s16::<LANE>(transmute(a), b))
}
#[doc = "Lookup table read with 2-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u16)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 1))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti2q_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t {
static_assert!(LANE >= 0 && LANE <= 3);
transmute(vluti2q_lane_s16::<LANE>(transmute(a), b))
}
#[doc = "Lookup table read with 2-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p8)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 1))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti2_lane_p8<const LANE: i32>(a: poly8x8_t, b: uint8x8_t) -> poly8x16_t {
static_assert!(LANE >= 0 && LANE <= 1);
transmute(vluti2_lane_s8::<LANE>(transmute(a), b))
}
#[doc = "Lookup table read with 2-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p8)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 1))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti2q_lane_p8<const LANE: i32>(a: poly8x16_t, b: uint8x8_t) -> poly8x16_t {
static_assert!(LANE >= 0 && LANE <= 1);
transmute(vluti2q_lane_s8::<LANE>(transmute(a), b))
}
#[doc = "Lookup table read with 2-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p16)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 1))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti2_lane_p16<const LANE: i32>(a: poly16x4_t, b: uint8x8_t) -> poly16x8_t {
static_assert!(LANE >= 0 && LANE <= 3);
transmute(vluti2_lane_s16::<LANE>(transmute(a), b))
}
#[doc = "Lookup table read with 2-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p16)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 1))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti2q_lane_p16<const LANE: i32>(a: poly16x8_t, b: uint8x8_t) -> poly16x8_t {
static_assert!(LANE >= 0 && LANE <= 3);
transmute(vluti2q_lane_s16::<LANE>(transmute(a), b))
}
#[doc = "Lookup table read with 4-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_f16_x2)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut,fp16")]
#[cfg_attr(test, assert_instr(nop, LANE = 0))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti4q_lane_f16_x2<const LANE: i32>(a: float16x8x2_t, b: uint8x8_t) -> float16x8_t {
static_assert!(LANE >= 0 && LANE <= 1);
transmute(vluti4q_lane_s16_x2::<LANE>(transmute(a), b))
}
#[doc = "Lookup table read with 4-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_u16_x2)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 0))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti4q_lane_u16_x2<const LANE: i32>(a: uint16x8x2_t, b: uint8x8_t) -> uint16x8_t {
static_assert!(LANE >= 0 && LANE <= 1);
transmute(vluti4q_lane_s16_x2::<LANE>(transmute(a), b))
}
#[doc = "Lookup table read with 4-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_p16_x2)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 0))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti4q_lane_p16_x2<const LANE: i32>(a: poly16x8x2_t, b: uint8x8_t) -> poly16x8_t {
static_assert!(LANE >= 0 && LANE <= 1);
transmute(vluti4q_lane_s16_x2::<LANE>(transmute(a), b))
}
#[doc = "Lookup table read with 4-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_s16_x2)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 0))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti4q_lane_s16_x2<const LANE: i32>(a: int16x8x2_t, b: uint8x8_t) -> int16x8_t {
static_assert!(LANE >= 0 && LANE <= 1);
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.vluti4q.lane.x2.v8i16"
)]
fn _vluti4q_lane_s16_x2(a: int16x8_t, a: int16x8_t, b: uint8x8_t, n: i32) -> int16x8_t;
}
_vluti4q_lane_s16_x2(a.0, a.1, b, LANE)
}
#[doc = "Lookup table read with 4-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_s8)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 0))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti4q_lane_s8<const LANE: i32>(a: int8x16_t, b: uint8x8_t) -> int8x16_t {
static_assert!(LANE == 0);
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.vluti4q.lane.v8i8"
)]
fn _vluti4q_lane_s8(a: int8x16_t, b: uint8x8_t, n: i32) -> int8x16_t;
}
_vluti4q_lane_s8(a, b, LANE)
}
#[doc = "Lookup table read with 4-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_u8)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 0))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti4q_lane_u8<const LANE: i32>(a: uint8x16_t, b: uint8x8_t) -> uint8x16_t {
static_assert!(LANE == 0);
transmute(vluti4q_lane_s8::<LANE>(transmute(a), b))
}
#[doc = "Lookup table read with 4-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_p8)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 0))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti4q_lane_p8<const LANE: i32>(a: poly8x16_t, b: uint8x8_t) -> poly8x16_t {
static_assert!(LANE == 0);
transmute(vluti4q_lane_s8::<LANE>(transmute(a), b))
}
#[doc = "Lookup table read with 4-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_f16_x2)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut,fp16")]
#[cfg_attr(test, assert_instr(nop, LANE = 3))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti4q_laneq_f16_x2<const LANE: i32>(
a: float16x8x2_t,
b: uint8x16_t,
) -> float16x8_t {
static_assert!(LANE >= 0 && LANE <= 3);
transmute(vluti4q_laneq_s16_x2::<LANE>(transmute(a), b))
}
#[doc = "Lookup table read with 4-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_u16_x2)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 3))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti4q_laneq_u16_x2<const LANE: i32>(a: uint16x8x2_t, b: uint8x16_t) -> uint16x8_t {
static_assert!(LANE >= 0 && LANE <= 3);
transmute(vluti4q_laneq_s16_x2::<LANE>(transmute(a), b))
}
#[doc = "Lookup table read with 4-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_p16_x2)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 3))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti4q_laneq_p16_x2<const LANE: i32>(a: poly16x8x2_t, b: uint8x16_t) -> poly16x8_t {
static_assert!(LANE >= 0 && LANE <= 3);
transmute(vluti4q_laneq_s16_x2::<LANE>(transmute(a), b))
}
#[doc = "Lookup table read with 4-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_s16_x2)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 3))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti4q_laneq_s16_x2<const LANE: i32>(a: int16x8x2_t, b: uint8x16_t) -> int16x8_t {
static_assert!(LANE >= 0 && LANE <= 3);
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.vluti4q.laneq.x2.v8i16"
)]
fn _vluti4q_laneq_s16_x2(a: int16x8_t, b: int16x8_t, c: uint8x16_t, n: i32) -> int16x8_t;
}
_vluti4q_laneq_s16_x2(a.0, a.1, b, LANE)
}
#[doc = "Lookup table read with 4-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_s8)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 0))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti4q_laneq_s8<const LANE: i32>(a: int8x16_t, b: uint8x16_t) -> int8x16_t {
static_assert!(LANE >= 0 && LANE <= 1);
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.vluti4q.laneq.v16i8"
)]
fn _vluti4q_laneq_s8(a: int8x16_t, b: uint8x16_t, n: i32) -> int8x16_t;
}
_vluti4q_laneq_s8(a, b, LANE)
}
#[doc = "Lookup table read with 4-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_u8)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 0))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti4q_laneq_u8<const LANE: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
static_assert!(LANE >= 0 && LANE <= 1);
transmute(vluti4q_laneq_s8::<LANE>(transmute(a), b))
}
#[doc = "Lookup table read with 4-bit indices"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_p8)"]
#[doc = "## Safety"]
#[doc = " * Neon instrinsic unsafe"]
#[inline]
#[target_feature(enable = "neon,lut")]
#[cfg_attr(test, assert_instr(nop, LANE = 0))]
#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
#[rustc_legacy_const_generics(2)]
pub unsafe fn vluti4q_laneq_p8<const LANE: i32>(a: poly8x16_t, b: uint8x16_t) -> poly8x16_t {
static_assert!(LANE >= 0 && LANE <= 1);
transmute(vluti4q_laneq_s8::<LANE>(transmute(a), b))
}
#[doc = "Maximum (vector)"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f64)"]
#[inline]

26
library/stdarch/crates/intrinsic-test/missing_aarch64.txt
View file

@ -30,6 +30,32 @@ vrnd32x_f64
vrnd32z_f64
vrnd64x_f64
vrnd64z_f64
vluti2_lane_p16
vluti2_lane_p8
vluti2_lane_s16
vluti2_lane_s8
vluti2_lane_u16
vluti2_lane_u8
vluti2q_lane_p16
vluti2q_lane_p8
vluti2q_lane_s16
vluti2q_lane_s8
vluti2q_lane_u16
vluti2q_lane_u8
vluti4q_lane_f16_x2
vluti4q_lane_p16_x2
vluti4q_lane_p8
vluti4q_lane_s16_x2
vluti4q_lane_s8
vluti4q_lane_u16_x2
vluti4q_lane_u8
vluti4q_laneq_f16_x2
vluti4q_laneq_p16_x2
vluti4q_laneq_p8
vluti4q_laneq_s16_x2
vluti4q_laneq_s8
vluti4q_laneq_u16_x2
vluti4q_laneq_u8
# Broken in Clang
vcvth_s16_f16

2
library/stdarch/crates/intrinsic-test/src/main.rs
View file

@ -240,7 +240,7 @@ fn compile_c(
let arch_flags = if target.contains("v7") {
"-march=armv8.6-a+crypto+crc+dotprod+fp16"
} else {
"-march=armv8.6-a+crypto+sha3+crc+dotprod+fp16+faminmax"
"-march=armv8.6-a+crypto+sha3+crc+dotprod+fp16+faminmax+lut"
};
let intrinsic_name = &intrinsic.name;

272
library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
View file

@ -89,6 +89,10 @@ aarch64-crc-stable: &aarch64-crc-stable
neon-unstable-f16: &neon-unstable-f16
FnCall: [unstable, ['feature = "stdarch_neon_f16"', 'issue = "136306"']]
# #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
neon-unstable-feat-lut: &neon-unstable-feat-lut
FnCall: [unstable, ['feature = "stdarch_neon_feat_lut"', 'issue = "138050"']]
intrinsics:
- name: "vaddd_{type}"
doc: Add
@ -14013,3 +14017,271 @@ intrinsics:
links:
- link: "llvm.aarch64.neon.famin.{neon_type}"
arch: aarch64,arm64ec
- name: "vluti2{neon_type[0].lane_nox}"
doc: "Lookup table read with 2-bit indices"
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [target_feature, ['enable = {type[4]}']]
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 1']]}]]
- *neon-unstable-feat-lut
- FnCall: [rustc_legacy_const_generics, ['2']]
static_defs: ["const LANE: i32"]
safety:
unsafe: [neon]
types:
- [int8x8_t, uint8x8_t, int8x16_t, 'LANE >= 0 && LANE <= 1', '"neon,lut"']
- [int8x16_t, uint8x8_t, int8x16_t, 'LANE >= 0 && LANE <= 1', '"neon,lut"']
- [int16x4_t, uint8x8_t, int16x8_t, 'LANE >= 0 && LANE <= 3', '"neon,lut"']
- [int16x8_t, uint8x8_t, int16x8_t, 'LANE >= 0 && LANE <= 3', '"neon,lut"']
compose:
- FnCall: ['static_assert!', ['{type[3]}']]
- LLVMLink:
name: "vluti2{neon_type[0].lane_nox}"
arguments:
- 'a: {neon_type[0]}'
- 'b: {neon_type[1]}'
- 'n: i32'
links:
- link: "llvm.aarch64.neon.vluti2.lane.{neon_type[2]}.{neon_type[0]}"
arch: aarch64,arm64ec
- FnCall: ['_vluti2{neon_type[0].lane_nox}', [a, b, LANE]]
- name: "vluti2{neon_type[0].lane_nox}"
doc: "Lookup table read with 2-bit indices"
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [target_feature, ['enable = "neon,lut"']]
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 1']]}]]
- *neon-unstable-feat-lut
- FnCall: [rustc_legacy_const_generics, ['2']]
static_defs: ["const LANE: i32"]
safety:
unsafe: [neon]
types:
- [uint8x8_t, uint8x8_t, uint8x16_t, 'LANE >= 0 && LANE <= 1', 'int8x8_t']
- [uint8x16_t, uint8x8_t, uint8x16_t, 'LANE >= 0 && LANE <= 1', 'int8x16_t']
- [poly8x8_t, uint8x8_t, poly8x16_t, 'LANE >= 0 && LANE <= 1', 'int8x8_t']
- [poly8x16_t, uint8x8_t, poly8x16_t, 'LANE >= 0 && LANE <= 1', 'int8x16_t']
- [uint16x4_t, uint8x8_t, uint16x8_t, 'LANE >= 0 && LANE <= 3', 'int16x4_t']
- [uint16x8_t, uint8x8_t, uint16x8_t, 'LANE >= 0 && LANE <= 3', 'int16x8_t']
- [poly16x4_t, uint8x8_t, poly16x8_t, 'LANE >= 0 && LANE <= 3', 'int16x4_t']
- [poly16x8_t, uint8x8_t, poly16x8_t, 'LANE >= 0 && LANE <= 3', 'int16x8_t']
compose:
- FnCall: ['static_assert!', ['{type[3]}']]
- FnCall:
- transmute
- - FnCall:
- 'vluti2{neon_type[4].lane_nox}::<LANE>'
- - FnCall: [transmute, [a]]
- b
- name: "vluti4{neon_type[0].lane_nox}"
doc: "Lookup table read with 4-bit indices"
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [target_feature, ['enable = {type[3]}']]
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]]
- *neon-unstable-feat-lut
- FnCall: [rustc_legacy_const_generics, ['2']]
static_defs: ["const LANE: i32"]
safety:
unsafe: [neon]
types:
- [int8x16_t, uint8x8_t, 'LANE == 0', '"neon,lut"']
compose:
- FnCall: ['static_assert!', ['{type[2]}']]
- LLVMLink:
name: "vluti4{neon_type[0].lane_nox}"
arguments:
- 'a: {neon_type[0]}'
- 'b: {neon_type[1]}'
- 'n: i32'
links:
- link: "llvm.aarch64.neon.vluti4q.lane.{neon_type[1]}"
arch: aarch64,arm64ec
- FnCall: ['_vluti4{neon_type[0].lane_nox}', [a, b, LANE]]
- name: "vluti4{neon_type[0].lane_nox}"
doc: "Lookup table read with 4-bit indices"
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [target_feature, ['enable = "neon,lut"']]
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]]
- *neon-unstable-feat-lut
- FnCall: [rustc_legacy_const_generics, ['2']]
static_defs: ["const LANE: i32"]
safety:
unsafe: [neon]
types:
- [uint8x16_t, uint8x8_t, 'LANE == 0', int8x16_t]
- [poly8x16_t, uint8x8_t, 'LANE == 0', int8x16_t]
compose:
- FnCall: ['static_assert!', ['{type[2]}']]
- FnCall:
- transmute
- - FnCall:
- 'vluti4{neon_type[3].lane_nox}::<LANE>'
- - FnCall: [transmute, [a]]
- b
- name: "vluti4{neon_type[0].laneq_nox}"
doc: "Lookup table read with 4-bit indices"
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [target_feature, ['enable = "neon,lut"']]
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]]
- *neon-unstable-feat-lut
- FnCall: [rustc_legacy_const_generics, ['2']]
static_defs: ["const LANE: i32"]
safety:
unsafe: [neon]
types:
- [int8x16_t, uint8x16_t, 'LANE >= 0 && LANE <= 1']
compose:
- FnCall: ['static_assert!', ['{type[2]}']]
- LLVMLink:
name: "vluti4{neon_type[0].laneq_nox}"
arguments:
- 'a: {neon_type[0]}'
- 'b: {neon_type[1]}'
- 'n: i32'
links:
- link: "llvm.aarch64.neon.vluti4q.laneq.{neon_type[1]}"
arch: aarch64,arm64ec
- FnCall: ['_vluti4{neon_type[0].laneq_nox}', [a, b, LANE]]
- name: "vluti4{neon_type[0].laneq_nox}"
doc: "Lookup table read with 4-bit indices"
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [target_feature, ['enable = "neon,lut"']]
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]]
- *neon-unstable-feat-lut
- FnCall: [rustc_legacy_const_generics, ['2']]
static_defs: ["const LANE: i32"]
safety:
unsafe: [neon]
types:
- [uint8x16_t, uint8x16_t, 'LANE >= 0 && LANE <= 1', int8x16_t]
- [poly8x16_t, uint8x16_t, 'LANE >= 0 && LANE <= 1', int8x16_t]
compose:
- FnCall: ['static_assert!', ['{type[2]}']]
- FnCall:
- transmute
- - FnCall:
- 'vluti4{neon_type[3].laneq_nox}::<LANE>'
- - FnCall: [transmute, [a]]
- b
- name: "vluti4q_lane_{neon_type[0]}_x2"
doc: "Lookup table read with 4-bit indices"
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [target_feature, ['enable = {type[4]}']]
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]]
- *neon-unstable-feat-lut
- FnCall: [rustc_legacy_const_generics, ['2']]
static_defs: ["const LANE: i32"]
safety:
unsafe: [neon]
types:
- [int16x8x2_t, uint8x8_t, int16x8_t, 'LANE >= 0 && LANE <= 1', '"neon,lut"']
compose:
- FnCall: ['static_assert!', ['{type[3]}']]
- LLVMLink:
name: "vluti4q_lane_{neon_type[0]}_x2"
arguments:
- 'a: {neon_type[2]}'
- 'a: {neon_type[2]}'
- 'b: {neon_type[1]}'
- 'n: i32'
links:
- link: "llvm.aarch64.neon.vluti4q.lane.x2.{neon_type[2]}"
arch: aarch64,arm64ec
- FnCall: ['_vluti4q_lane_{neon_type[0]}_x2', ['a.0', 'a.1', b, LANE]]
- name: "vluti4q_lane_{neon_type[0]}_x2"
doc: "Lookup table read with 4-bit indices"
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [target_feature, ['enable = {type[4]}']]
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]]
- *neon-unstable-feat-lut
- FnCall: [rustc_legacy_const_generics, ['2']]
static_defs: ["const LANE: i32"]
safety:
unsafe: [neon]
types:
- [uint16x8x2_t, uint8x8_t, uint16x8_t, 'LANE >= 0 && LANE <= 1', '"neon,lut"', int16x8x2_t]
- [poly16x8x2_t, uint8x8_t, poly16x8_t, 'LANE >= 0 && LANE <= 1', '"neon,lut"', int16x8x2_t]
- [float16x8x2_t, uint8x8_t, float16x8_t, 'LANE >= 0 && LANE <= 1', '"neon,lut,fp16"', int16x8x2_t]
compose:
- FnCall: ['static_assert!', ['{type[3]}']]
- FnCall:
- transmute
- - FnCall:
- 'vluti4q_lane_{neon_type[5]}_x2::<LANE>'
- - FnCall: [transmute, [a]]
- b
- name: "vluti4q_laneq_{neon_type[0]}_x2"
doc: "Lookup table read with 4-bit indices"
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [target_feature, ['enable = {type[4]}']]
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 3']]}]]
- *neon-unstable-feat-lut
- FnCall: [rustc_legacy_const_generics, ['2']]
static_defs: ["const LANE: i32"]
safety:
unsafe: [neon]
types:
- [int16x8x2_t, uint8x16_t, int16x8_t, 'LANE >= 0 && LANE <= 3', '"neon,lut"']
compose:
- FnCall: ['static_assert!', ['{type[3]}']]
- LLVMLink:
name: "vluti4{neon_type[0].lane_nox}"
arguments:
- 'a: {neon_type[2]}'
- 'b: {neon_type[2]}'
- 'c: {neon_type[1]}'
- 'n: i32'
links:
- link: "llvm.aarch64.neon.vluti4q.laneq.x2.{neon_type[2]}"
arch: aarch64,arm64ec
- FnCall: ['_vluti4q_laneq_{neon_type[0]}_x2', ['a.0', 'a.1', b, LANE]]
- name: "vluti4q_laneq_{neon_type[0]}_x2"
doc: "Lookup table read with 4-bit indices"
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [target_feature, ['enable = {type[4]}']]
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 3']]}]]
- *neon-unstable-feat-lut
- FnCall: [rustc_legacy_const_generics, ['2']]
static_defs: ["const LANE: i32"]
safety:
unsafe: [neon]
types:
- [uint16x8x2_t, uint8x16_t, uint16x8_t, 'LANE >= 0 && LANE <= 3', '"neon,lut"', int16x8x2_t]
- [poly16x8x2_t, uint8x16_t, poly16x8_t, 'LANE >= 0 && LANE <= 3', '"neon,lut"', int16x8x2_t]
- [float16x8x2_t, uint8x16_t, float16x8_t, 'LANE >= 0 && LANE <= 3', '"neon,lut,fp16"', int16x8x2_t]
compose:
- FnCall: ['static_assert!', ['{type[3]}']]
- FnCall:
- transmute
- - FnCall:
- 'vluti4q_laneq_{neon_type[5]}_x2::<LANE>'
- - FnCall: [transmute, [a]]
- b

910
library/stdarch/intrinsics_data/arm_intrinsics.json
View file

@ -118843,5 +118843,915 @@
"FAMAX"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti2_lane_u8",
"arguments": [
"uint8x8_t a",
"uint8x8_t b",
"const int lane"
],
"return_type": {
"value": "uint8x16_t"
},
"Arguments_Preparation": {
"a": {
"register": "Vn.16B"
},
"b": {
"register": "Vm"
},
"lane": {
"minimum": 0,
"maximum": 1
},
"r": {
"register": "Vd.16B"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI2"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti2q_lane_u8",
"arguments": [
"uint8x16_t a",
"uint8x8_t b",
"const int lane"
],
"return_type": {
"value": "uint8x16_t"
},
"Arguments_Preparation": {
"a": {
"register": "Vn.16B"
},
"b": {
"register": "Vm"
},
"lane": {
"minimum": 0,
"maximum": 1
},
"r": {
"register": "Vd.16B"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI2"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti2_lane_s8",
"arguments": [
"int8x8_t a",
"uint8x8_t b",
"const int lane"
],
"return_type": {
"value": "int8x16_t"
},
"Arguments_Preparation": {
"a": {
"register": "Vn.16B"
},
"b": {
"register": "Vm"
},
"lane": {
"minimum": 0,
"maximum": 1
},
"r": {
"register": "Vd.16B"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI2"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti2q_lane_s8",
"arguments": [
"int8x16_t a",
"uint8x8_t b",
"const int lane"
],
"return_type": {
"value": "int8x16_t"
},
"Arguments_Preparation": {
"a": {
"register": "Vn.16B"
},
"b": {
"register": "Vm"
},
"lane": {
"minimum": 0,
"maximum": 1
},
"r": {
"register": "Vd.16B"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI2"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti2_lane_p8",
"arguments": [
"poly8x8_t a",
"uint8x8_t b",
"const int lane"
],
"return_type": {
"value": "poly8x16_t"
},
"Arguments_Preparation": {
"a": {
"register": "Vn.16B"
},
"b": {
"register": "Vm"
},
"lane": {
"minimum": 0,
"maximum": 1
},
"r": {
"register": "Vd.16B"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI2"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti2q_lane_p8",
"arguments": [
"poly8x16_t a",
"uint8x8_t b",
"const int lane"
],
"return_type": {
"value": "poly8x16_t"
},
"Arguments_Preparation": {
"a": {
"register": "Vn.16B"
},
"b": {
"register": "Vm"
},
"lane": {
"minimum": 0,
"maximum": 1
},
"r": {
"register": "Vd.16B"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI2"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti2_lane_u16",
"arguments": [
"uint16x4_t a",
"uint8x8_t b",
"const int lane"
],
"return_type": {
"value": "uint16x8_t"
},
"Arguments_Preparation": {
"a": {
"register": "Vn.8H"
},
"b": {
"register": "Vm"
},
"lane": {
"minimum": 0,
"maximum": 3
},
"r": {
"register": "Vd.8H"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI2"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti2q_lane_u16",
"arguments": [
"uint16x8_t a",
"uint8x8_t b",
"const int lane"
],
"return_type": {
"value": "uint16x8_t"
},
"Arguments_Preparation": {
"a": {
"register": "Vn.8H"
},
"b": {
"register": "Vm"
},
"lane": {
"minimum": 0,
"maximum": 3
},
"r": {
"register": "Vd.8H"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI2"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti2_lane_s16",
"arguments": [
"int16x4_t a",
"uint8x8_t b",
"const int lane"
],
"return_type": {
"value": "int16x8_t"
},
"Arguments_Preparation": {
"a": {
"register": "Vn.8H"
},
"b": {
"register": "Vm"
},
"lane": {
"minimum": 0,
"maximum": 3
},
"r": {
"register": "Vd.8H"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI2"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti2q_lane_s16",
"arguments": [
"int16x8_t a",
"uint8x8_t b",
"const int lane"
],
"return_type": {
"value": "int16x8_t"
},
"Arguments_Preparation": {
"a": {
"register": "Vn.8H"
},
"b": {
"register": "Vm"
},
"lane": {
"minimum": 0,
"maximum": 3
},
"r": {
"register": "Vd.8H"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI2"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti2_lane_p16",
"arguments": [
"poly16x4_t a",
"uint8x8_t b",
"const int lane"
],
"return_type": {
"value": "poly16x8_t"
},
"Arguments_Preparation": {
"a": {
"register": "Vn.8H"
},
"b": {
"register": "Vm"
},
"lane": {
"minimum": 0,
"maximum": 3
},
"r": {
"register": "Vd.8H"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI2"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti2q_lane_p16",
"arguments": [
"poly16x8_t a",
"uint8x8_t b",
"const int lane"
],
"return_type": {
"value": "poly16x8_t"
},
"Arguments_Preparation": {
"a": {
"register": "Vn.8H"
},
"b": {
"register": "Vm"
},
"lane": {
"minimum": 0,
"maximum": 3
},
"r": {
"register": "Vd.8H"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI2"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti4q_lane_u8",
"arguments": [
"uint8x16_t vn",
"uint8x8_t vm",
"const int index"
],
"return_type": {
"value": "uint8x16_t"
},
"Arguments_Preparation": {
"vn": {
"register": "Vn.16B"
},
"vm": {
"register": "Vm"
},
"index": {
"minimum": 0,
"maximum": 0
},
"r": {
"register": "Vd.16B"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI4"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti4q_laneq_u8",
"arguments": [
"uint8x16_t vn",
"uint8x16_t vm",
"const int index"
],
"return_type": {
"value": "uint8x16_t"
},
"Arguments_Preparation": {
"vn": {
"register": "Vn.16B"
},
"vm": {
"register": "Vm"
},
"index": {
"minimum": 0,
"maximum": 1
},
"r": {
"register": "Vd.16B"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI4"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti4q_lane_s8",
"arguments": [
"int8x16_t vn",
"uint8x8_t vm",
"const int index"
],
"return_type": {
"value": "int8x16_t"
},
"Arguments_Preparation": {
"vn": {
"register": "Vn.16B"
},
"vm": {
"register": "Vm"
},
"index": {
"minimum": 0,
"maximum": 0
},
"r": {
"register": "Vd.16B"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI4"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti4q_laneq_s8",
"arguments": [
"int8x16_t vn",
"uint8x16_t vm",
"const int index"
],
"return_type": {
"value": "int8x16_t"
},
"Arguments_Preparation": {
"vn": {
"register": "Vn.16B"
},
"vm": {
"register": "Vm"
},
"index": {
"minimum": 0,
"maximum": 1
},
"r": {
"register": "Vd.16B"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI4"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti4q_lane_p8",
"arguments": [
"poly8x16_t vn",
"uint8x8_t vm",
"const int index"
],
"return_type": {
"value": "poly8x16_t"
},
"Arguments_Preparation": {
"vn": {
"register": "Vn.16B"
},
"vm": {
"register": "Vm"
},
"index": {
"minimum": 0,
"maximum": 0
},
"r": {
"register": "Vd.16B"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI4"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti4q_laneq_p8",
"arguments": [
"poly8x16_t vn",
"uint8x16_t vm",
"const int index"
],
"return_type": {
"value": "poly8x16_t"
},
"Arguments_Preparation": {
"vn": {
"register": "Vn.16B"
},
"vm": {
"register": "Vm"
},
"index": {
"minimum": 0,
"maximum": 1
},
"r": {
"register": "Vd.16B"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI4"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti4q_lane_u16_x2",
"arguments": [
"uint16x8x2_t vn",
"uint8x8_t vm",
"const int index"
],
"return_type": {
"value": "uint16x8_t"
},
"Arguments_Preparation": {
"vn": {
"register": "Vn1.8H"
},
"vm": {
"register": "Vm"
},
"index": {
"minimum": 0,
"maximum": 1
},
"r": {
"register": "Vd.8H"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI4"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti4q_laneq_u16_x2",
"arguments": [
"uint16x8x2_t vn",
"uint8x16_t vm",
"const int index"
],
"return_type": {
"value": "uint16x8_t"
},
"Arguments_Preparation": {
"vn": {
"register": "Vn1.8H"
},
"vm": {
"register": "Vm"
},
"index": {
"minimum": 0,
"maximum": 3
},
"r": {
"register": "Vd.8H"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI4"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti4q_lane_s16_x2",
"arguments": [
"int16x8x2_t vn",
"uint8x8_t vm",
"const int index"
],
"return_type": {
"value": "int16x8_t"
},
"Arguments_Preparation": {
"vn": {
"register": "Vn1.8H"
},
"vm": {
"register": "Vm"
},
"index": {
"minimum": 0,
"maximum": 1
},
"r": {
"register": "Vd.8H"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI4"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti4q_laneq_s16_x2",
"arguments": [
"int16x8x2_t vn",
"uint8x16_t vm",
"const int index"
],
"return_type": {
"value": "int16x8_t"
},
"Arguments_Preparation": {
"vn": {
"register": "Vn1.8H"
},
"vm": {
"register": "Vm"
},
"index": {
"minimum": 0,
"maximum": 3
},
"r": {
"register": "Vd.8H"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI4"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti4q_lane_f16_x2",
"arguments": [
"float16x8x2_t vn",
"uint8x8_t vm",
"const int index"
],
"return_type": {
"value": "float16x8_t"
},
"Arguments_Preparation": {
"vn": {
"register": "Vn1.8H"
},
"vm": {
"register": "Vm"
},
"index": {
"minimum": 0,
"maximum": 1
},
"r": {
"register": "Vd.8H"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI4"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti4q_laneq_f16_x2",
"arguments": [
"float16x8x2_t vn",
"uint8x16_t vm",
"const int index"
],
"return_type": {
"value": "float16x8_t"
},
"Arguments_Preparation": {
"vn": {
"register": "Vn1.8H"
},
"vm": {
"register": "Vm"
},
"index": {
"minimum": 0,
"maximum": 3
},
"r": {
"register": "Vd.8H"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI4"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti4q_lane_p16_x2",
"arguments": [
"poly16x8x2_t vn",
"uint8x8_t vm",
"const int index"
],
"return_type": {
"value": "poly16x8_t"
},
"Arguments_Preparation": {
"vn": {
"register": "Vn1.8H"
},
"vm": {
"register": "Vm"
},
"index": {
"minimum": 0,
"maximum": 1
},
"r": {
"register": "Vd.8H"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI4"
]
]
},
{
"SIMD_ISA": "Neon",
"name": "vluti4q_laneq_p16_x2",
"arguments": [
"poly16x8x2_t vn",
"uint8x16_t vm",
"const int index"
],
"return_type": {
"value": "poly16x8_t"
},
"Arguments_Preparation": {
"vn": {
"register": "Vn1.8H"
},
"vm": {
"register": "Vm"
},
"index": {
"minimum": 0,
"maximum": 3
},
"r": {
"register": "Vd.8H"
}
},
"Architectures": [
"A64"
],
"instructions": [
[
"LUTI4"
]
]
}
]