From 8c7111da07f20422a6bd5243b56d302f0f02c3a5 Mon Sep 17 00:00:00 2001 From: Alexis Beingessner Date: Sun, 26 Jul 2015 18:19:50 -0700 Subject: [PATCH] fixup atomics --- src/doc/tarpl/atomics.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/doc/tarpl/atomics.md b/src/doc/tarpl/atomics.md index 8395b22c8d8e..87378da7c523 100644 --- a/src/doc/tarpl/atomics.md +++ b/src/doc/tarpl/atomics.md @@ -85,12 +85,12 @@ x = 1; y *= 2; Ideally this program has 2 possible final states: -* `y = 3`: (thread 2 did the check before thread 1 completed) y = 6`: (thread 2 -* `did the check after thread 1 completed) +* `y = 3`: (thread 2 did the check before thread 1 completed) +* `y = 6`: (thread 2 did the check after thread 1 completed) However there's a third potential state that the hardware enables: -* `y = 2`: (thread 2 saw `x = 2`, but not `y = 3`, and then overwrote `y = 3`) +* `y = 2`: (thread 2 saw `x = 1`, but not `y = 3`, and then overwrote `y = 3`) It's worth noting that different kinds of CPU provide different guarantees. It is common to separate hardware into two categories: strongly-ordered and weakly-