diff --git a/library/stdarch/crates/core_arch/avx512dq.md b/library/stdarch/crates/core_arch/avx512dq.md deleted file mode 100644 index 2d0447621b89..000000000000 --- a/library/stdarch/crates/core_arch/avx512dq.md +++ /dev/null @@ -1,445 +0,0 @@ -["AVX512DQ"]

- -[Intel's List](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#avx512techs=AVX512DQ) - -- And: - * [x] _mm_mask_and_pd - * [x] _mm_maskz_and_pd - * [x] _mm_mask_and_ps - * [x] _mm_maskz_and_ps - * [x] _mm256_mask_and_pd - * [x] _mm256_maskz_and_pd - * [x] _mm256_mask_and_ps - * [x] _mm256_maskz_and_ps - * [x] _mm512_and_pd - * [x] _mm512_mask_and_pd - * [x] _mm512_maskz_and_pd - * [x] _mm512_and_ps - * [x] _mm512_mask_and_ps - * [x] _mm512_maskz_and_ps - - -- AndNot: - * [x] _mm_mask_andnot_pd - * [x] _mm_maskz_andnot_pd - * [x] _mm_mask_andnot_ps - * [x] _mm_maskz_andnot_ps - * [x] _mm256_mask_andnot_pd - * [x] _mm256_maskz_andnot_pd - * [x] _mm256_mask_andnot_ps - * [x] _mm256_maskz_andnot_ps - * [x] _mm512_andnot_pd - * [x] _mm512_mask_andnot_pd - * [x] _mm512_maskz_andnot_pd - * [x] _mm512_andnot_ps - * [x] _mm512_mask_andnot_ps - * [x] _mm512_maskz_andnot_ps - - -- Or: - * [x] _mm_mask_or_pd - * [x] _mm_maskz_or_pd - * [x] _mm_mask_or_ps - * [x] _mm_maskz_or_ps - * [x] _mm256_mask_or_pd - * [x] _mm256_maskz_or_pd - * [x] _mm256_mask_or_ps - * [x] _mm256_maskz_or_ps - * [x] _mm512_or_pd - * [x] _mm512_mask_or_pd - * [x] _mm512_maskz_or_pd - * [x] _mm512_or_ps - * [x] _mm512_mask_or_ps - * [x] _mm512_maskz_or_ps - - -- Xor: - * [x] _mm_mask_xor_pd - * [x] _mm_maskz_xor_pd - * [x] _mm_mask_xor_ps - * [x] _mm_maskz_xor_ps - * [x] _mm256_mask_xor_pd - * [x] _mm256_maskz_xor_pd - * [x] _mm256_mask_xor_ps - * [x] _mm256_maskz_xor_ps - * [x] _mm512_xor_pd - * [x] _mm512_mask_xor_pd - * [x] _mm512_maskz_xor_pd - * [x] _mm512_xor_ps - * [x] _mm512_mask_xor_ps - * [x] _mm512_maskz_xor_ps - - -- Broadcast: - * [x] _mm256_broadcast_f32x2 - * [x] _mm256_mask_broadcast_f32x2 - * [x] _mm256_maskz_broadcast_f32x2 - * [x] _mm512_broadcast_f32x2 - * [x] _mm512_mask_broadcast_f32x2 - * [x] _mm512_maskz_broadcast_f32x2 - * [x] _mm512_broadcast_f32x8 - * [x] _mm512_mask_broadcast_f32x8 - * [x] _mm512_maskz_broadcast_f32x8 - * [x] _mm256_broadcast_f64x2 - * [x] _mm256_mask_broadcast_f64x2 - * [x] _mm256_maskz_broadcast_f64x2 - * [x] _mm512_broadcast_f64x2 - * [x] _mm512_mask_broadcast_f64x2 - * [x] _mm512_maskz_broadcast_f64x2 - * [x] _mm_broadcast_i32x2 - * [x] _mm_mask_broadcast_i32x2 - * [x] _mm_maskz_broadcast_i32x2 - * [x] _mm256_broadcast_i32x2 - * [x] _mm256_mask_broadcast_i32x2 - * [x] _mm256_maskz_broadcast_i32x2 - * [x] _mm512_broadcast_i32x2 - * [x] _mm512_mask_broadcast_i32x2 - * [x] _mm512_maskz_broadcast_i32x2 - * [x] _mm512_broadcast_i32x8 - * [x] _mm512_mask_broadcast_i32x8 - * [x] _mm512_maskz_broadcast_i32x8 - * [x] _mm256_broadcast_i64x2 - * [x] _mm256_mask_broadcast_i64x2 - * [x] _mm256_maskz_broadcast_i64x2 - * [x] _mm512_broadcast_i64x2 - * [x] _mm512_mask_broadcast_i64x2 - * [x] _mm512_maskz_broadcast_i64x2 - - -- Convert: - * [x] _mm512_cvt_roundepi64_pd - * [x] _mm512_mask_cvt_roundepi64_pd - * [x] _mm512_maskz_cvt_roundepi64_pd - * [x] _mm_cvtepi64_pd - * [x] _mm_mask_cvtepi64_pd - * [x] _mm_maskz_cvtepi64_pd - * [x] _mm256_cvtepi64_pd - * [x] _mm256_mask_cvtepi64_pd - * [x] _mm256_maskz_cvtepi64_pd - * [x] _mm512_cvtepi64_pd - * [x] _mm512_mask_cvtepi64_pd - * [x] _mm512_maskz_cvtepi64_pd - * [x] _mm512_cvt_roundepi64_ps - * [x] _mm512_mask_cvt_roundepi64_ps - * [x] _mm512_maskz_cvt_roundepi64_ps - * [x] _mm_cvtepi64_ps - * [x] _mm_mask_cvtepi64_ps - * [x] _mm_maskz_cvtepi64_ps - * [x] _mm256_cvtepi64_ps - * [x] _mm256_mask_cvtepi64_ps - * [x] _mm256_maskz_cvtepi64_ps - * [x] _mm512_cvtepi64_ps - * [x] _mm512_mask_cvtepi64_ps - * [x] _mm512_maskz_cvtepi64_ps - * [x] _mm512_cvt_roundepu64_pd - * [x] _mm512_mask_cvt_roundepu64_pd - * [x] _mm512_maskz_cvt_roundepu64_pd - * [x] _mm_cvtepu64_pd - * [x] _mm_mask_cvtepu64_pd - * [x] _mm_maskz_cvtepu64_pd - * [x] _mm256_cvtepu64_pd - * [x] _mm256_mask_cvtepu64_pd - * [x] _mm256_maskz_cvtepu64_pd - * [x] _mm512_cvtepu64_pd - * [x] _mm512_mask_cvtepu64_pd - * [x] _mm512_maskz_cvtepu64_pd - * [x] _mm512_cvt_roundepu64_ps - * [x] _mm512_mask_cvt_roundepu64_ps - * [x] _mm512_maskz_cvt_roundepu64_ps - * [x] _mm_cvtepu64_ps - * [x] _mm_mask_cvtepu64_ps - * [x] _mm_maskz_cvtepu64_ps - * [x] _mm256_cvtepu64_ps - * [x] _mm256_mask_cvtepu64_ps - * [x] _mm256_maskz_cvtepu64_ps - * [x] _mm512_cvtepu64_ps - * [x] _mm512_mask_cvtepu64_ps - * [x] _mm512_maskz_cvtepu64_ps - * [x] _mm512_cvt_roundpd_epi64 - * [x] _mm512_mask_cvt_roundpd_epi64 - * [x] _mm512_maskz_cvt_roundpd_epi64 - * [x] _mm_cvtpd_epi64 - * [x] _mm_mask_cvtpd_epi64 - * [x] _mm_maskz_cvtpd_epi64 - * [x] _mm256_cvtpd_epi64 - * [x] _mm256_mask_cvtpd_epi64 - * [x] _mm256_maskz_cvtpd_epi64 - * [x] _mm512_cvtpd_epi64 - * [x] _mm512_mask_cvtpd_epi64 - * [x] _mm512_maskz_cvtpd_epi64 - * [x] _mm512_cvt_roundps_epi64 - * [x] _mm512_mask_cvt_roundps_epi64 - * [x] _mm512_maskz_cvt_roundps_epi64 - * [x] _mm_cvtps_epi64 - * [x] _mm_mask_cvtps_epi64 - * [x] _mm_maskz_cvtps_epi64 - * [x] _mm256_cvtps_epi64 - * [x] _mm256_mask_cvtps_epi64 - * [x] _mm256_maskz_cvtps_epi64 - * [x] _mm512_cvtps_epi64 - * [x] _mm512_mask_cvtps_epi64 - * [x] _mm512_maskz_cvtps_epi64 - * [x] _mm512_cvt_roundpd_epu64 - * [x] _mm512_mask_cvt_roundpd_epu64 - * [x] _mm512_maskz_cvt_roundpd_epu64 - * [x] _mm_cvtpd_epu64 - * [x] _mm_mask_cvtpd_epu64 - * [x] _mm_maskz_cvtpd_epu64 - * [x] _mm256_cvtpd_epu64 - * [x] _mm256_mask_cvtpd_epu64 - * [x] _mm256_maskz_cvtpd_epu64 - * [x] _mm512_cvtpd_epu64 - * [x] _mm512_mask_cvtpd_epu64 - * [x] _mm512_maskz_cvtpd_epu64 - * [x] _mm512_cvt_roundps_epu64 - * [x] _mm512_mask_cvt_roundps_epu64 - * [x] _mm512_maskz_cvt_roundps_epu64 - * [x] _mm_cvtps_epu64 - * [x] _mm_mask_cvtps_epu64 - * [x] _mm_maskz_cvtps_epu64 - * [x] _mm256_cvtps_epu64 - * [x] _mm256_mask_cvtps_epu64 - * [x] _mm256_maskz_cvtps_epu64 - * [x] _mm512_cvtps_epu64 - * [x] _mm512_mask_cvtps_epu64 - * [x] _mm512_maskz_cvtps_epu64 - * [x] _mm512_cvtt_roundpd_epi64 - * [x] _mm512_mask_cvtt_roundpd_epi64 - * [x] _mm512_maskz_cvtt_roundpd_epi64 - * [x] _mm_cvttpd_epi64 - * [x] _mm_mask_cvttpd_epi64 - * [x] _mm_maskz_cvttpd_epi64 - * [x] _mm256_cvttpd_epi64 - * [x] _mm256_mask_cvttpd_epi64 - * [x] _mm256_maskz_cvttpd_epi64 - * [x] _mm512_cvttpd_epi64 - * [x] _mm512_mask_cvttpd_epi64 - * [x] _mm512_maskz_cvttpd_epi64 - * [x] _mm512_cvtt_roundps_epi64 - * [x] _mm512_mask_cvtt_roundps_epi64 - * [x] _mm512_maskz_cvtt_roundps_epi64 - * [x] _mm_cvttps_epi64 - * [x] _mm_mask_cvttps_epi64 - * [x] _mm_maskz_cvttps_epi64 - * [x] _mm256_cvttps_epi64 - * [x] _mm256_mask_cvttps_epi64 - * [x] _mm256_maskz_cvttps_epi64 - * [x] _mm512_cvttps_epi64 - * [x] _mm512_mask_cvttps_epi64 - * [x] _mm512_maskz_cvttps_epi64 - * [x] _mm512_cvtt_roundpd_epu64 - * [x] _mm512_mask_cvtt_roundpd_epu64 - * [x] _mm512_maskz_cvtt_roundpd_epu64 - * [x] _mm_cvttpd_epu64 - * [x] _mm_mask_cvttpd_epu64 - * [x] _mm_maskz_cvttpd_epu64 - * [x] _mm256_cvttpd_epu64 - * [x] _mm256_mask_cvttpd_epu64 - * [x] _mm256_maskz_cvttpd_epu64 - * [x] _mm512_cvttpd_epu64 - * [x] _mm512_mask_cvttpd_epu64 - * [x] _mm512_maskz_cvttpd_epu64 - * [x] _mm512_cvtt_roundps_epu64 - * [x] _mm512_mask_cvtt_roundps_epu64 - * [x] _mm512_maskz_cvtt_roundps_epu64 - * [x] _mm_cvttps_epu64 - * [x] _mm_mask_cvttps_epu64 - * [x] _mm_maskz_cvttps_epu64 - * [x] _mm256_cvttps_epu64 - * [x] _mm256_mask_cvttps_epu64 - * [x] _mm256_maskz_cvttps_epu64 - * [x] _mm512_cvttps_epu64 - * [x] _mm512_mask_cvttps_epu64 - * [x] _mm512_maskz_cvttps_epu64 - - -- Element Extract: - * [x] _mm512_extractf32x8_ps - * [x] _mm512_mask_extractf32x8_ps - * [x] _mm512_maskz_extractf32x8_ps - * [x] _mm256_extractf64x2_pd - * [x] _mm256_mask_extractf64x2_pd - * [x] _mm256_maskz_extractf64x2_pd - * [x] _mm512_extractf64x2_pd - * [x] _mm512_mask_extractf64x2_pd - * [x] _mm512_maskz_extractf64x2_pd - * [x] _mm512_extracti32x8_epi32 - * [x] _mm512_mask_extracti32x8_epi32 - * [x] _mm512_maskz_extracti32x8_epi32 - * [x] _mm256_extracti64x2_epi64 - * [x] _mm256_mask_extracti64x2_epi64 - * [x] _mm256_maskz_extracti64x2_epi64 - * [x] _mm512_extracti64x2_epi64 - * [x] _mm512_mask_extracti64x2_epi64 - * [x] _mm512_maskz_extracti64x2_epi64 - - -- Element Insert: - * [x] _mm512_insertf32x8 - * [x] _mm512_mask_insertf32x8 - * [x] _mm512_maskz_insertf32x8 - * [x] _mm256_insertf64x2 - * [x] _mm256_mask_insertf64x2 - * [x] _mm256_maskz_insertf64x2 - * [x] _mm512_insertf64x2 - * [x] _mm512_mask_insertf64x2 - * [x] _mm512_maskz_insertf64x2 - * [x] _mm512_inserti32x8 - * [x] _mm512_mask_inserti32x8 - * [x] _mm512_maskz_inserti32x8 - * [x] _mm256_inserti64x2 - * [x] _mm256_mask_inserti64x2 - * [x] _mm256_maskz_inserti64x2 - * [x] _mm512_inserti64x2 - * [x] _mm512_mask_inserti64x2 - * [x] _mm512_maskz_inserti64x2 - - -- FP-Class: - * [x] _mm_fpclass_pd_mask (Needs `i1` type) - * [x] _mm_mask_fpclass_pd_mask (Needs `i1` type) - * [x] _mm256_fpclass_pd_mask (Needs `i1` type) - * [x] _mm256_mask_fpclass_pd_mask (Needs `i1` type) - * [x] _mm512_fpclass_pd_mask (Needs `i1` type) - * [x] _mm512_mask_fpclass_pd_mask (Needs `i1` type) - * [x] _mm_fpclass_ps_mask (Needs `i1` type) - * [x] _mm_mask_fpclass_ps_mask (Needs `i1` type) - * [x] _mm256_fpclass_ps_mask (Needs `i1` type) - * [x] _mm256_mask_fpclass_ps_mask (Needs `i1` type) - * [x] _mm512_fpclass_ps_mask (Needs `i1` type) - * [x] _mm512_mask_fpclass_ps_mask (Needs `i1` type) - * [x] _mm_fpclass_sd_mask (Needs `i1` type) - * [x] _mm_mask_fpclass_sd_mask (Needs `i1` type) - * [x] _mm_fpclass_ss_mask (Needs `i1` type) - * [x] _mm_mask_fpclass_ss_mask (Needs `i1` type) - - -- Mask Registers: - * [x] _cvtmask8_u32 - * [x] _cvtu32_mask8 - * [x] _kadd_mask16 - * [x] _kadd_mask8 - * [x] _kand_mask8 - * [x] _kandn_mask8 - * [x] _knot_mask8 - * [x] _kor_mask8 - * [x] _kortest_mask8_u8 - * [x] _kortestc_mask8_u8 - * [x] _kortestz_mask8_u8 - * [x] _kshiftli_mask8 - * [x] _kshiftri_mask8 - * [x] _ktest_mask16_u8 - * [x] _ktest_mask8_u8 - * [x] _ktestc_mask16_u8 - * [x] _ktestc_mask8_u8 - * [x] _ktestz_mask16_u8 - * [x] _ktestz_mask8_u8 - * [x] _kxnor_mask8 - * [x] _kxor_mask8 - * [x] _load_mask8 - * [x] _store_mask8 - - -- Mask register for Bit patterns: - * [x] _mm_movepi32_mask - * [x] _mm256_movepi32_mask - * [x] _mm512_movepi32_mask - * [x] _mm_movepi64_mask - * [x] _mm256_movepi64_mask - * [x] _mm512_movepi64_mask - * [x] _mm_movm_epi32 - * [x] _mm256_movm_epi32 - * [x] _mm512_movm_epi32 - * [x] _mm_movm_epi64 - * [x] _mm256_movm_epi64 - * [x] _mm512_movm_epi64 - - -- Multiply Low: - * [x] _mm_mullo_epi64 - * [x] _mm_mask_mullo_epi64 - * [x] _mm_maskz_mullo_epi64 - * [x] _mm256_mullo_epi64 - * [x] _mm256_mask_mullo_epi64 - * [x] _mm256_maskz_mullo_epi64 - * [x] _mm512_mullo_epi64 - * [x] _mm512_mask_mullo_epi64 - * [x] _mm512_maskz_mullo_epi64 - - -- Range: - * [x] _mm512_range_round_pd - * [x] _mm512_mask_range_round_pd - * [x] _mm512_maskz_range_round_pd - * [x] _mm_range_pd - * [x] _mm_mask_range_pd - * [x] _mm_maskz_range_pd - * [x] _mm256_range_pd - * [x] _mm256_mask_range_pd - * [x] _mm256_maskz_range_pd - * [x] _mm512_range_pd - * [x] _mm512_mask_range_pd - * [x] _mm512_maskz_range_pd - * [x] _mm512_range_round_ps - * [x] _mm512_mask_range_round_ps - * [x] _mm512_maskz_range_round_ps - * [x] _mm_range_ps - * [x] _mm_mask_range_ps - * [x] _mm_maskz_range_ps - * [x] _mm256_range_ps - * [x] _mm256_mask_range_ps - * [x] _mm256_maskz_range_ps - * [x] _mm512_range_ps - * [x] _mm512_mask_range_ps - * [x] _mm512_maskz_range_ps - * [x] _mm_range_round_sd - * [x] _mm_mask_range_round_sd - * [x] _mm_maskz_range_round_sd - * [x] _mm_mask_range_sd - * [x] _mm_maskz_range_sd - * [x] _mm_range_round_ss - * [x] _mm_mask_range_round_ss - * [x] _mm_maskz_range_round_ss - * [x] _mm_mask_range_ss - * [x] _mm_maskz_range_ss - - -- Reduce: - * [x] _mm512_reduce_round_pd - * [x] _mm512_mask_reduce_round_pd - * [x] _mm512_maskz_reduce_round_pd - * [x] _mm_reduce_pd - * [x] _mm_mask_reduce_pd - * [x] _mm_maskz_reduce_pd - * [x] _mm256_reduce_pd - * [x] _mm256_mask_reduce_pd - * [x] _mm256_maskz_reduce_pd - * [x] _mm512_reduce_pd - * [x] _mm512_mask_reduce_pd - * [x] _mm512_maskz_reduce_pd - * [x] _mm512_reduce_round_ps - * [x] _mm512_mask_reduce_round_ps - * [x] _mm512_maskz_reduce_round_ps - * [x] _mm_reduce_ps - * [x] _mm_mask_reduce_ps - * [x] _mm_maskz_reduce_ps - * [x] _mm256_reduce_ps - * [x] _mm256_mask_reduce_ps - * [x] _mm256_maskz_reduce_ps - * [x] _mm512_reduce_ps - * [x] _mm512_mask_reduce_ps - * [x] _mm512_maskz_reduce_ps - * [x] _mm_reduce_round_sd - * [x] _mm_mask_reduce_round_sd - * [x] _mm_maskz_reduce_round_sd - * [x] _mm_reduce_sd - * [x] _mm_mask_reduce_sd - * [x] _mm_maskz_reduce_sd - * [x] _mm_reduce_round_ss - * [x] _mm_mask_reduce_round_ss - * [x] _mm_maskz_reduce_round_ss - * [x] _mm_reduce_ss - * [x] _mm_mask_reduce_ss - * [x] _mm_maskz_reduce_ss - -

diff --git a/library/stdarch/crates/core_arch/src/x86/avx512dq.rs b/library/stdarch/crates/core_arch/src/x86/avx512dq.rs index 5bb33563e326..08018bef8688 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512dq.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512dq.rs @@ -4409,7 +4409,7 @@ pub unsafe fn _ktest_mask16_u8(a: __mmask16, b: __mmask16, and_not: *mut u8) -> #[unstable(feature = "stdarch_x86_avx512", issue = "111137")] pub unsafe fn _ktest_mask8_u8(a: __mmask8, b: __mmask8, and_not: *mut u8) -> u8 { *and_not = (_kandn_mask8(a, b) == 0) as u8; - (_kandn_mask8(a, b) == 0) as u8 + (_kand_mask8(a, b) == 0) as u8 } /// Compute the bitwise NOT of 16-bit mask a and then AND with 16-bit mask b, if the result is all @@ -6409,6 +6409,7 @@ pub unsafe fn _mm_maskz_reduce_ss(k: __mmask8, a: __m128, b: __ // FP-Class +// FIXME: Use LLVM intrinsics instead of inline assembly macro_rules! fpclass_asm { ($instr:literal, $mask_type: ty, $reg: ident, $a: expr) => {{ let dst: $mask_type; @@ -7691,7 +7692,7 @@ mod tests { let a = _mm_set_epi32(1, 2, 3, 4); let b = _mm_set_epi32(5, 6, 7, 8); let r = _mm_mask_broadcast_i32x2(b, 0b0110, a); - let e = _mm_set_epi32(5, 4, 3, 6); + let e = _mm_set_epi32(5, 4, 3, 8); assert_eq_m128i(r, e); } @@ -8010,7 +8011,7 @@ mod tests { ); let r = _mm512_mask_insertf32x8::<1>(src, 0b0110100100111100, a, b); let e = _mm512_set_ps( - 25., 18., 19., 28., 29., 30., 31., 32., 33., 34., 11., 12., 13., 14., 39., 40., + 25., 18., 19., 28., 21., 30., 31., 24., 33., 34., 11., 12., 13., 14., 39., 40., ); assert_eq_m512(r, e); } @@ -8104,7 +8105,7 @@ mod tests { ); let r = _mm512_mask_inserti32x8::<1>(src, 0b0110100100111100, a, b); let e = _mm512_set_epi32( - 25, 18, 19, 28, 20, 30, 31, 24, 33, 34, 11, 12, 13, 14, 39, 40, + 25, 18, 19, 28, 21, 30, 31, 24, 33, 34, 11, 12, 13, 14, 39, 40, ); assert_eq_m512i(r, e); } @@ -9477,7 +9478,7 @@ mod tests { let b = _mm512_set_epi64(9, 10, 11, 12, 13, 14, 15, 16); let c = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24); let r = _mm512_mask_mullo_epi64(c, 0b01101001, a, b); - let e = _mm512_set_epi64(17, 20, 33, 12, 65, 14, 15, 128); + let e = _mm512_set_epi64(17, 20, 33, 20, 65, 22, 23, 128); assert_eq_m512i(r, e); } @@ -9538,7 +9539,7 @@ mod tests { let a: __mmask8 = 0b01101001; let b: __mmask8 = 0b10110011; let r = _kandn_mask8(a, b); - let e: __mmask8 = 0b10011010; + let e: __mmask8 = 0b10010010; assert_eq!(r, e); } @@ -10160,7 +10161,7 @@ mod tests { let r = _mm512_mask_reduce_round_pd::<{ 16 | _MM_FROUND_TO_ZERO }, _MM_FROUND_NO_EXC>( src, 0b01101001, a, ); - let e = _mm512_set_pd(3., 0., 0.25, 4., 0.25, 6., 7., 0.); + let e = _mm512_set_pd(3., 0., 0.25, 6., 0.25, 8., 9., 0.); assert_eq_m512d(r, e); } @@ -10212,7 +10213,7 @@ mod tests { let a = _mm256_set_pd(0.25, 0.50, 0.75, 1.0); let src = _mm256_set_pd(3., 4., 5., 6.); let r = _mm256_mask_reduce_pd::<{ 16 | _MM_FROUND_TO_ZERO }>(src, 0b0110, a); - let e = _mm256_set_pd(3., 0., 0.25, 4.); + let e = _mm256_set_pd(3., 0., 0.25, 6.); assert_eq_m256d(r, e); } @@ -10237,7 +10238,7 @@ mod tests { let a = _mm512_set_pd(0.25, 0.50, 0.75, 1.0, 1.25, 1.50, 1.75, 2.0); let src = _mm512_set_pd(3., 4., 5., 6., 7., 8., 9., 10.); let r = _mm512_mask_reduce_pd::<{ 16 | _MM_FROUND_TO_ZERO }>(src, 0b01101001, a); - let e = _mm512_set_pd(3., 0., 0.25, 4., 0.25, 6., 7., 0.); + let e = _mm512_set_pd(3., 0., 0.25, 6., 0.25, 8., 9., 0.); assert_eq_m512d(r, e); } @@ -10277,7 +10278,7 @@ mod tests { a, ); let e = _mm512_set_ps( - 5., 0., 0.25, 6., 0.25, 8., 9., 0., 13., 14., 0.25, 0., 0.25, 0., 19., 20., + 5., 0., 0.25, 8., 0.25, 10., 11., 0., 13., 14., 0.25, 0., 0.25, 0., 19., 20., ); assert_eq_m512(r, e); } @@ -10311,7 +10312,7 @@ mod tests { let a = _mm_set_ps(0.25, 0.50, 0.75, 1.0); let src = _mm_set_ps(2., 3., 4., 5.); let r = _mm_mask_reduce_ps::<{ 16 | _MM_FROUND_TO_ZERO }>(src, 0b0110, a); - let e = _mm_set_ps(2., 0., 0.25, 3.); + let e = _mm_set_ps(2., 0., 0.25, 5.); assert_eq_m128(r, e); } @@ -10336,7 +10337,7 @@ mod tests { let a = _mm256_set_ps(0.25, 0.50, 0.75, 1.0, 1.25, 1.50, 1.75, 2.0); let src = _mm256_set_ps(3., 4., 5., 6., 7., 8., 9., 10.); let r = _mm256_mask_reduce_ps::<{ 16 | _MM_FROUND_TO_ZERO }>(src, 0b01101001, a); - let e = _mm256_set_ps(3., 0., 0.25, 4., 0.25, 6., 7., 0.); + let e = _mm256_set_ps(3., 0., 0.25, 6., 0.25, 8., 9., 0.); assert_eq_m256(r, e); } @@ -10372,7 +10373,7 @@ mod tests { ); let r = _mm512_mask_reduce_ps::<{ 16 | _MM_FROUND_TO_ZERO }>(src, 0b0110100100111100, a); let e = _mm512_set_ps( - 5., 0., 0.25, 6., 0.25, 8., 9., 0., 13., 14., 0.25, 0., 0.25, 0., 19., 20., + 5., 0., 0.25, 8., 0.25, 10., 11., 0., 13., 14., 0.25, 0., 0.25, 0., 19., 20., ); assert_eq_m512(r, e); } @@ -10619,7 +10620,7 @@ mod tests { f32::NAN, 1.0e-38, ); - let r = _mm256_mask_fpclass_ps_mask::<0>(0b10101010, a); + let r = _mm256_mask_fpclass_ps_mask::<0x18>(0b10101010, a); let e = 0b00100000; assert_eq!(r, e); } @@ -10669,7 +10670,7 @@ mod tests { f32::NAN, -1.0e-38, ); - let r = _mm512_mask_fpclass_ps_mask::<0>(0b1010101010101010, a); + let r = _mm512_mask_fpclass_ps_mask::<0x18>(0b1010101010101010, a); let e = 0b0010000000100000; assert_eq!(r, e); }