From 91bed9bd0c245d739a4e713b9a4cd2926eb32d9a Mon Sep 17 00:00:00 2001 From: SparrowLii Date: Mon, 22 Mar 2021 19:33:57 +0800 Subject: [PATCH] correct instruction names --- .../core_arch/src/aarch64/neon/generated.rs | 328 +++++++++--------- library/stdarch/crates/stdarch-gen/neon.spec | 20 +- .../stdarch/crates/stdarch-gen/src/main.rs | 5 +- 3 files changed, 182 insertions(+), 171 deletions(-) diff --git a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs index 35ede4db9c7f..6e4830e671dd 100644 --- a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs +++ b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs @@ -2055,14 +2055,6 @@ pub unsafe fn vtrn1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { simd_shuffle8(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } -/// Transpose vectors -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(trn1))] -pub unsafe fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_shuffle2(a, b, [0, 2]) -} - /// Transpose vectors #[inline] #[target_feature(enable = "neon")] @@ -2071,14 +2063,6 @@ pub unsafe fn vtrn1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { simd_shuffle4(a, b, [0, 4, 2, 6]) } -/// Transpose vectors -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(trn1))] -pub unsafe fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_shuffle2(a, b, [0, 2]) -} - /// Transpose vectors #[inline] #[target_feature(enable = "neon")] @@ -2111,14 +2095,6 @@ pub unsafe fn vtrn1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { simd_shuffle8(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } -/// Transpose vectors -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(trn1))] -pub unsafe fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_shuffle2(a, b, [0, 2]) -} - /// Transpose vectors #[inline] #[target_feature(enable = "neon")] @@ -2127,14 +2103,6 @@ pub unsafe fn vtrn1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { simd_shuffle4(a, b, [0, 4, 2, 6]) } -/// Transpose vectors -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(trn1))] -pub unsafe fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_shuffle2(a, b, [0, 2]) -} - /// Transpose vectors #[inline] #[target_feature(enable = "neon")] @@ -2170,16 +2138,40 @@ pub unsafe fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { /// Transpose vectors #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(trn1))] -pub unsafe fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { +#[cfg_attr(test, assert_instr(zip1))] +pub unsafe fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { simd_shuffle2(a, b, [0, 2]) } /// Transpose vectors #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(trn1))] -pub unsafe fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +#[cfg_attr(test, assert_instr(zip1))] +pub unsafe fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + simd_shuffle2(a, b, [0, 2]) +} + +/// Transpose vectors +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(zip1))] +pub unsafe fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + simd_shuffle2(a, b, [0, 2]) +} + +/// Transpose vectors +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(zip1))] +pub unsafe fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + simd_shuffle2(a, b, [0, 2]) +} + +/// Transpose vectors +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(zip1))] +pub unsafe fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { simd_shuffle2(a, b, [0, 2]) } @@ -2194,7 +2186,15 @@ pub unsafe fn vtrn1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { /// Transpose vectors #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(trn1))] +#[cfg_attr(test, assert_instr(zip1))] +pub unsafe fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + simd_shuffle2(a, b, [0, 2]) +} + +/// Transpose vectors +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(zip1))] pub unsafe fn vtrn1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { simd_shuffle2(a, b, [0, 2]) } @@ -2231,14 +2231,6 @@ pub unsafe fn vtrn2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { simd_shuffle8(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } -/// Transpose vectors -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(trn2))] -pub unsafe fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_shuffle2(a, b, [1, 3]) -} - /// Transpose vectors #[inline] #[target_feature(enable = "neon")] @@ -2247,14 +2239,6 @@ pub unsafe fn vtrn2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { simd_shuffle4(a, b, [1, 5, 3, 7]) } -/// Transpose vectors -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(trn2))] -pub unsafe fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_shuffle2(a, b, [1, 3]) -} - /// Transpose vectors #[inline] #[target_feature(enable = "neon")] @@ -2287,14 +2271,6 @@ pub unsafe fn vtrn2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { simd_shuffle8(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } -/// Transpose vectors -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(trn2))] -pub unsafe fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_shuffle2(a, b, [1, 3]) -} - /// Transpose vectors #[inline] #[target_feature(enable = "neon")] @@ -2303,14 +2279,6 @@ pub unsafe fn vtrn2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { simd_shuffle4(a, b, [1, 5, 3, 7]) } -/// Transpose vectors -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(trn2))] -pub unsafe fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_shuffle2(a, b, [1, 3]) -} - /// Transpose vectors #[inline] #[target_feature(enable = "neon")] @@ -2346,16 +2314,40 @@ pub unsafe fn vtrn2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { /// Transpose vectors #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(trn2))] -pub unsafe fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { +#[cfg_attr(test, assert_instr(zip2))] +pub unsafe fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { simd_shuffle2(a, b, [1, 3]) } /// Transpose vectors #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(trn2))] -pub unsafe fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +#[cfg_attr(test, assert_instr(zip2))] +pub unsafe fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + simd_shuffle2(a, b, [1, 3]) +} + +/// Transpose vectors +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(zip2))] +pub unsafe fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + simd_shuffle2(a, b, [1, 3]) +} + +/// Transpose vectors +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(zip2))] +pub unsafe fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + simd_shuffle2(a, b, [1, 3]) +} + +/// Transpose vectors +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(zip2))] +pub unsafe fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { simd_shuffle2(a, b, [1, 3]) } @@ -2370,7 +2362,15 @@ pub unsafe fn vtrn2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { /// Transpose vectors #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(trn2))] +#[cfg_attr(test, assert_instr(zip2))] +pub unsafe fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + simd_shuffle2(a, b, [1, 3]) +} + +/// Transpose vectors +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(zip2))] pub unsafe fn vtrn2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { simd_shuffle2(a, b, [1, 3]) } @@ -4211,15 +4211,6 @@ mod test { assert_eq!(r, e); } - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1_s32() { - let a: i32x2 = i32x2::new(0, 2); - let b: i32x2 = i32x2::new(1, 3); - let e: i32x2 = i32x2::new(0, 1); - let r: i32x2 = transmute(vtrn1_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - #[simd_test(enable = "neon")] unsafe fn test_vtrn1q_s32() { let a: i32x4 = i32x4::new(0, 2, 4, 6); @@ -4229,15 +4220,6 @@ mod test { assert_eq!(r, e); } - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1q_s64() { - let a: i64x2 = i64x2::new(0, 2); - let b: i64x2 = i64x2::new(1, 3); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vtrn1q_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - #[simd_test(enable = "neon")] unsafe fn test_vtrn1_u8() { let a: u8x8 = u8x8::new(0, 2, 4, 6, 8, 10, 12, 14); @@ -4274,15 +4256,6 @@ mod test { assert_eq!(r, e); } - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1_u32() { - let a: u32x2 = u32x2::new(0, 2); - let b: u32x2 = u32x2::new(1, 3); - let e: u32x2 = u32x2::new(0, 1); - let r: u32x2 = transmute(vtrn1_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - #[simd_test(enable = "neon")] unsafe fn test_vtrn1q_u32() { let a: u32x4 = u32x4::new(0, 2, 4, 6); @@ -4292,15 +4265,6 @@ mod test { assert_eq!(r, e); } - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1q_u64() { - let a: u64x2 = u64x2::new(0, 2); - let b: u64x2 = u64x2::new(1, 3); - let e: u64x2 = u64x2::new(0, 1); - let r: u64x2 = transmute(vtrn1q_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - #[simd_test(enable = "neon")] unsafe fn test_vtrn1_p8() { let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); @@ -4337,6 +4301,42 @@ mod test { assert_eq!(r, e); } + #[simd_test(enable = "neon")] + unsafe fn test_vtrn1_s32() { + let a: i32x2 = i32x2::new(0, 2); + let b: i32x2 = i32x2::new(1, 3); + let e: i32x2 = i32x2::new(0, 1); + let r: i32x2 = transmute(vtrn1_s32(transmute(a), transmute(b))); + assert_eq!(r, e); + } + + #[simd_test(enable = "neon")] + unsafe fn test_vtrn1q_s64() { + let a: i64x2 = i64x2::new(0, 2); + let b: i64x2 = i64x2::new(1, 3); + let e: i64x2 = i64x2::new(0, 1); + let r: i64x2 = transmute(vtrn1q_s64(transmute(a), transmute(b))); + assert_eq!(r, e); + } + + #[simd_test(enable = "neon")] + unsafe fn test_vtrn1_u32() { + let a: u32x2 = u32x2::new(0, 2); + let b: u32x2 = u32x2::new(1, 3); + let e: u32x2 = u32x2::new(0, 1); + let r: u32x2 = transmute(vtrn1_u32(transmute(a), transmute(b))); + assert_eq!(r, e); + } + + #[simd_test(enable = "neon")] + unsafe fn test_vtrn1q_u64() { + let a: u64x2 = u64x2::new(0, 2); + let b: u64x2 = u64x2::new(1, 3); + let e: u64x2 = u64x2::new(0, 1); + let r: u64x2 = transmute(vtrn1q_u64(transmute(a), transmute(b))); + assert_eq!(r, e); + } + #[simd_test(enable = "neon")] unsafe fn test_vtrn1q_p64() { let a: i64x2 = i64x2::new(0, 2); @@ -4346,15 +4346,6 @@ mod test { assert_eq!(r, e); } - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1_f32() { - let a: f32x2 = f32x2::new(0., 2.); - let b: f32x2 = f32x2::new(1., 3.); - let e: f32x2 = f32x2::new(0., 1.); - let r: f32x2 = transmute(vtrn1_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - #[simd_test(enable = "neon")] unsafe fn test_vtrn1q_f32() { let a: f32x4 = f32x4::new(0., 2., 4., 6.); @@ -4364,6 +4355,15 @@ mod test { assert_eq!(r, e); } + #[simd_test(enable = "neon")] + unsafe fn test_vtrn1_f32() { + let a: f32x2 = f32x2::new(0., 2.); + let b: f32x2 = f32x2::new(1., 3.); + let e: f32x2 = f32x2::new(0., 1.); + let r: f32x2 = transmute(vtrn1_f32(transmute(a), transmute(b))); + assert_eq!(r, e); + } + #[simd_test(enable = "neon")] unsafe fn test_vtrn1q_f64() { let a: f64x2 = f64x2::new(0., 2.); @@ -4409,15 +4409,6 @@ mod test { assert_eq!(r, e); } - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2_s32() { - let a: i32x2 = i32x2::new(0, 2); - let b: i32x2 = i32x2::new(1, 3); - let e: i32x2 = i32x2::new(2, 3); - let r: i32x2 = transmute(vtrn2_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - #[simd_test(enable = "neon")] unsafe fn test_vtrn2q_s32() { let a: i32x4 = i32x4::new(0, 2, 4, 6); @@ -4427,15 +4418,6 @@ mod test { assert_eq!(r, e); } - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2q_s64() { - let a: i64x2 = i64x2::new(0, 2); - let b: i64x2 = i64x2::new(1, 3); - let e: i64x2 = i64x2::new(2, 3); - let r: i64x2 = transmute(vtrn2q_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - #[simd_test(enable = "neon")] unsafe fn test_vtrn2_u8() { let a: u8x8 = u8x8::new(0, 2, 4, 6, 8, 10, 12, 14); @@ -4472,15 +4454,6 @@ mod test { assert_eq!(r, e); } - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2_u32() { - let a: u32x2 = u32x2::new(0, 2); - let b: u32x2 = u32x2::new(1, 3); - let e: u32x2 = u32x2::new(2, 3); - let r: u32x2 = transmute(vtrn2_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - #[simd_test(enable = "neon")] unsafe fn test_vtrn2q_u32() { let a: u32x4 = u32x4::new(0, 2, 4, 6); @@ -4490,15 +4463,6 @@ mod test { assert_eq!(r, e); } - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2q_u64() { - let a: u64x2 = u64x2::new(0, 2); - let b: u64x2 = u64x2::new(1, 3); - let e: u64x2 = u64x2::new(2, 3); - let r: u64x2 = transmute(vtrn2q_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - #[simd_test(enable = "neon")] unsafe fn test_vtrn2_p8() { let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); @@ -4535,6 +4499,42 @@ mod test { assert_eq!(r, e); } + #[simd_test(enable = "neon")] + unsafe fn test_vtrn2_s32() { + let a: i32x2 = i32x2::new(0, 2); + let b: i32x2 = i32x2::new(1, 3); + let e: i32x2 = i32x2::new(2, 3); + let r: i32x2 = transmute(vtrn2_s32(transmute(a), transmute(b))); + assert_eq!(r, e); + } + + #[simd_test(enable = "neon")] + unsafe fn test_vtrn2q_s64() { + let a: i64x2 = i64x2::new(0, 2); + let b: i64x2 = i64x2::new(1, 3); + let e: i64x2 = i64x2::new(2, 3); + let r: i64x2 = transmute(vtrn2q_s64(transmute(a), transmute(b))); + assert_eq!(r, e); + } + + #[simd_test(enable = "neon")] + unsafe fn test_vtrn2_u32() { + let a: u32x2 = u32x2::new(0, 2); + let b: u32x2 = u32x2::new(1, 3); + let e: u32x2 = u32x2::new(2, 3); + let r: u32x2 = transmute(vtrn2_u32(transmute(a), transmute(b))); + assert_eq!(r, e); + } + + #[simd_test(enable = "neon")] + unsafe fn test_vtrn2q_u64() { + let a: u64x2 = u64x2::new(0, 2); + let b: u64x2 = u64x2::new(1, 3); + let e: u64x2 = u64x2::new(2, 3); + let r: u64x2 = transmute(vtrn2q_u64(transmute(a), transmute(b))); + assert_eq!(r, e); + } + #[simd_test(enable = "neon")] unsafe fn test_vtrn2q_p64() { let a: i64x2 = i64x2::new(0, 2); @@ -4544,15 +4544,6 @@ mod test { assert_eq!(r, e); } - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2_f32() { - let a: f32x2 = f32x2::new(0., 2.); - let b: f32x2 = f32x2::new(1., 3.); - let e: f32x2 = f32x2::new(2., 3.); - let r: f32x2 = transmute(vtrn2_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - #[simd_test(enable = "neon")] unsafe fn test_vtrn2q_f32() { let a: f32x4 = f32x4::new(0., 2., 4., 6.); @@ -4562,6 +4553,15 @@ mod test { assert_eq!(r, e); } + #[simd_test(enable = "neon")] + unsafe fn test_vtrn2_f32() { + let a: f32x2 = f32x2::new(0., 2.); + let b: f32x2 = f32x2::new(1., 3.); + let e: f32x2 = f32x2::new(2., 3.); + let r: f32x2 = transmute(vtrn2_f32(transmute(a), transmute(b))); + assert_eq!(r, e); + } + #[simd_test(enable = "neon")] unsafe fn test_vtrn2q_f64() { let a: f64x2 = f64x2::new(0., 2.); diff --git a/library/stdarch/crates/stdarch-gen/neon.spec b/library/stdarch/crates/stdarch-gen/neon.spec index ca417151208d..ac4998517172 100644 --- a/library/stdarch/crates/stdarch-gen/neon.spec +++ b/library/stdarch/crates/stdarch-gen/neon.spec @@ -1256,7 +1256,10 @@ b = 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 validate 0, 1, 4, 5, 8, 9, 12, 13, 16, 17, 20, 21, 24, 25, 28, 29 aarch64 = trn1 -generate int*_t, int64x2_t, uint*_t, uint64x2_t, poly8x8_t:poly8x8_t, poly8x16_t:poly8x16_t, poly16x4_t:poly16x4_t, poly16x8_t:poly16x8_t, poly64x2_t:poly64x2_t +generate int8x8_t, int8x16_t, int16x4_t, int16x8_t, int32x4_t, uint8x8_t, uint8x16_t, uint16x4_t, uint16x8_t, uint32x4_t, poly8x8_t, poly8x16_t, poly16x4_t, poly16x8_t + +aarch64 = zip1 +generate int32x2_t, int64x2_t, uint32x2_t, uint64x2_t, poly64x2_t /// Transpose vectors name = vtrn1 @@ -1266,7 +1269,10 @@ b = 1., 3., 5., 7., 9., 11., 13., 15. validate 0., 1., 4., 5., 8., 9., 12., 13. aarch64 = trn1 -generate float32x2_t:float32x2_t, float32x4_t:float32x4_t, float64x2_t:float64x2_t +generate float32x4_t + +aarch64 = zip1 +generate float32x2_t, float64x2_t /// Transpose vectors name = vtrn2 @@ -1276,7 +1282,10 @@ b = 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 validate 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 aarch64 = trn2 -generate int*_t, int64x2_t, uint*_t, uint64x2_t, poly8x8_t:poly8x8_t, poly8x16_t:poly8x16_t, poly16x4_t:poly16x4_t, poly16x8_t:poly16x8_t, poly64x2_t:poly64x2_t +generate int8x8_t, int8x16_t, int16x4_t, int16x8_t, int32x4_t, uint8x8_t, uint8x16_t, uint16x4_t, uint16x8_t, uint32x4_t, poly8x8_t, poly8x16_t, poly16x4_t, poly16x8_t + +aarch64 = zip2 +generate int32x2_t, int64x2_t, uint32x2_t, uint64x2_t, poly64x2_t /// Transpose vectors name = vtrn2 @@ -1286,4 +1295,7 @@ b = 1., 3., 5., 7., 9., 11., 13., 15. validate 2., 3., 6., 7., 10., 11., 14., 15. aarch64 = trn2 -generate float32x2_t:float32x2_t, float32x4_t:float32x4_t, float64x2_t:float64x2_t +generate float32x4_t + +aarch64 = zip2 +generate float32x2_t, float64x2_t diff --git a/library/stdarch/crates/stdarch-gen/src/main.rs b/library/stdarch/crates/stdarch-gen/src/main.rs index f08217f09506..ecba6f7559ec 100644 --- a/library/stdarch/crates/stdarch-gen/src/main.rs +++ b/library/stdarch/crates/stdarch-gen/src/main.rs @@ -1330,7 +1330,7 @@ mod test { tests_aarch64.push('}'); tests_aarch64.push('\n'); - let arm_out_path: PathBuf = PathBuf::from("./crates/core_arch") + let arm_out_path: PathBuf = PathBuf::from(env::var("OUT_DIR").unwrap()) .join("src") .join("arm") .join("neon"); @@ -1340,8 +1340,7 @@ mod test { file_arm.write_all(out_arm.as_bytes())?; file_arm.write_all(tests_arm.as_bytes())?; - //let aarch64_out_path: PathBuf = PathBuf::from(env::var("OUT_DIR").unwrap()) - let aarch64_out_path: PathBuf = PathBuf::from("./crates/core_arch") + let aarch64_out_path: PathBuf = PathBuf::from(env::var("OUT_DIR").unwrap()) .join("src") .join("aarch64") .join("neon");