diff --git a/src/tools/miri/src/shims/x86/sse.rs b/src/tools/miri/src/shims/x86/sse.rs
index de1e695b6d14..0e51a73d0911 100644
--- a/src/tools/miri/src/shims/x86/sse.rs
+++ b/src/tools/miri/src/shims/x86/sse.rs
@@ -141,7 +141,7 @@ pub(super) trait EvalContextExt<'mir, 'tcx: 'mir>:
 
                 let left = this.read_scalar(&this.project_index(&left, 0)?)?.to_f32()?;
                 let right = this.read_scalar(&this.project_index(&right, 0)?)?.to_f32()?;
-                // The difference between the com* and *ucom variants is signaling
+                // The difference between the com* and ucom* variants is signaling
                 // of exceptions when either argument is a quiet NaN. We do not
                 // support accessing the SSE status register from miri (or from Rust,
                 // for that matter), so we treat equally both variants.
diff --git a/src/tools/miri/src/shims/x86/sse2.rs b/src/tools/miri/src/shims/x86/sse2.rs
index 2ef6a9b59ede..a27d37d0fff8 100644
--- a/src/tools/miri/src/shims/x86/sse2.rs
+++ b/src/tools/miri/src/shims/x86/sse2.rs
@@ -637,7 +637,7 @@ pub(super) trait EvalContextExt<'mir, 'tcx: 'mir>:
 
                 let left = this.read_scalar(&this.project_index(&left, 0)?)?.to_f64()?;
                 let right = this.read_scalar(&this.project_index(&right, 0)?)?.to_f64()?;
-                // The difference between the com* and *ucom variants is signaling
+                // The difference between the com* and ucom* variants is signaling
                 // of exceptions when either argument is a quiet NaN. We do not
                 // support accessing the SSE status register from miri (or from Rust,
                 // for that matter), so we treat equally both variants.