The modern styling is apparently to use Title Case for the chip/company, "Arm".
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## Common Target Details
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This documentation covers details that apply to a range of bare-metal targets
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for 32-bit ARM CPUs. The `arm-none-eabi` flavor of the GNU compiler toolchain is
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for 32-bit Arm CPUs. The `arm-none-eabi` flavor of the GNU compiler toolchain is
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often used to assist compilation to these targets.
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Details that apply only to only a specific target in this group are covered in
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@ -11,55 +11,55 @@ their own document.
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### Tier 2 Target List
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- ARM A-Profile Architectures
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- Arm A-Profile Architectures
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- `armv7a-none-eabi`
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- ARM R-Profile Architectures
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- Arm R-Profile Architectures
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- [`armv7r-none-eabi` and `armv7r-none-eabihf`](armv7r-none-eabi.md)
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- [`armebv7r-none-eabi` and `armebv7r-none-eabihf`](armv7r-none-eabi.md)
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- ARM M-Profile Architectures
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- Arm M-Profile Architectures
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- [`thumbv6m-none-eabi`](thumbv6m-none-eabi.md)
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- [`thumbv7m-none-eabi`](thumbv7m-none-eabi.md)
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- [`thumbv7em-none-eabi` and `thumbv7em-none-eabihf`](thumbv7em-none-eabi.md)
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- [`thumbv8m.base-none-eabi`](thumbv8m.base-none-eabi.md)
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- [`thumbv8m.main-none-eabi` and `thumbv8m.main-none-eabihf`](thumbv8m.main-none-eabi.md)
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- *Legacy* ARM Architectures
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- *Legacy* Arm Architectures
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- None
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### Tier 3 Target List
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- ARM A-Profile Architectures
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- Arm A-Profile Architectures
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- `armv7a-none-eabihf`
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- ARM R-Profile Architectures
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- Arm R-Profile Architectures
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- [`armv8r-none-eabihf`](armv8r-none-eabihf.md)
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- ARM M-Profile Architectures
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- Arm M-Profile Architectures
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- None
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- *Legacy* ARM Architectures
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- *Legacy* Arm Architectures
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- [`armv4t-none-eabi` and `thumbv4t-none-eabi`](armv4t-none-eabi.md)
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- [`armv5te-none-eabi` and `thumbv5te-none-eabi`](armv5te-none-eabi.md)
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## Instruction Sets
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There are two 32-bit instruction set architectures (ISAs) defined by ARM:
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There are two 32-bit instruction set architectures (ISAs) defined by Arm:
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- The [*A32 ISA*][a32-isa], with fixed-width 32-bit instructions. Previously
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known as the *ARM* ISA, this originated with the original ARM1 of 1985 and has
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known as the *Arm* ISA, this originated with the original Arm1 of 1985 and has
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been updated by various revisions to the architecture specifications ever
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since.
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- The [*T32 ISA*][t32-isa], with a mix of 16-bit and 32-bit width instructions.
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Note that this term includes both the original 16-bit width *Thumb* ISA
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introduced with the ARMv4T architecture in 1994, and the later 16/32-bit sized
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*Thumb-2* ISA introduced with the ARMv6T2 architecture in 2003.
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introduced with the Armv4T architecture in 1994, and the later 16/32-bit sized
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*Thumb-2* ISA introduced with the Armv6T2 architecture in 2003.
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Again, these ISAs have been revised by subsequent revisions to the relevant ARM
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Again, these ISAs have been revised by subsequent revisions to the relevant Arm
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architecture specifications.
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There is also a 64-bit ISA with fixed-width 32-bit instructions called the *A64
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ISA*, but targets which implement that instruction set generally start with
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`aarch64*` and are discussed elsewhere.
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Rust targets starting with `arm*` generate ARM (A32) code by default, whilst
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targets named `thumb*` generate Thumb (T32) code by default. Most ARM chips
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support both Thumb mode and ARM mode, with the notable exception that M-profile
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Rust targets starting with `arm*` generate Arm (A32) code by default, whilst
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targets named `thumb*` generate Thumb (T32) code by default. Most Arm chips
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support both Thumb mode and Arm mode, with the notable exception that M-profile
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processors (`thumbv*m*-none-eabi*` targets) *only* support Thumb-mode.
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Rust targets ending with `eabi` use the so-called *soft-float ABI*: functions
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@ -92,14 +92,14 @@ instructions.
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## Target CPU and Target Feature options
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It is possible to tell Rust (or LLVM) that you have a specific model of ARM
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It is possible to tell Rust (or LLVM) that you have a specific model of Arm
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processor, using the [`-C target-cpu`][target-cpu] option. You can also control
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whether Rust (or LLVM) will include instructions that target optional hardware
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features, e.g. hardware floating-point, or Advanced SIMD operations, using [`-C
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target-feature`][target-feature].
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It is important to note that selecting a *target-cpu* will typically enable
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*all* the optional features available from ARM on that model of CPU and your
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*all* the optional features available from Arm on that model of CPU and your
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particular implementation of that CPU may not have those features available. In
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that case, you can use `-C target-feature=-option` to turn off the specific CPU
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features you do not have available, leaving you with the optimized instruction
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@ -116,7 +116,7 @@ uses (likely linker related ones):
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```toml
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rustflags = [
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# Usual ARM bare-metal linker setup
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# Usual Arm bare-metal linker setup
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"-Clink-arg=-Tlink.x",
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"-Clink-arg=--nmagic",
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# tell Rust we have a Cortex-M55
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@ -139,7 +139,7 @@ These targets are cross-compiled and use static linking.
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By default, the `lld` linker included with Rust will be used; however, you may
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want to use the GNU linker instead. This can be obtained for Windows/Mac/Linux
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from the [ARM Developer Website][arm-gnu-toolchain], or possibly from your OS's
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from the [Arm Developer Website][arm-gnu-toolchain], or possibly from your OS's
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package manager. To use it, add the following to your `.cargo/config.toml`:
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```toml
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@ -185,7 +185,7 @@ Most of `core` should work as expected, with the following notes:
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specific kind of FPU)
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* Integer division is also emulated in software on some targets, depending on
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the target, `target-cpu` and `target-feature`s.
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* Older ARM architectures (e.g. ARMv4, ARMv5TE and ARMv6-M) are limited to basic
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* Older Arm architectures (e.g. Armv4, Armv5TE and Armv6-M) are limited to basic
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[`load`][atomic-load] and [`store`][atomic-store] operations, and not more
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advanced operations like [`fetch_add`][fetch-add] or
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[`compare_exchange`][compare-exchange].
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