Add Thumb-mode targets for Armv7-R, Armv7-A and Armv8-R.
This commit is contained in:
Jonathan 'theJPster' Pallant
parent
5dd7c0b5ab
commit
96647dde77
12 changed files with 188 additions and 13 deletions
|
|
@ -1596,8 +1596,11 @@ supported_targets! {
|
|||
("armebv7r-none-eabi", armebv7r_none_eabi),
|
||||
("armebv7r-none-eabihf", armebv7r_none_eabihf),
|
||||
("armv7r-none-eabi", armv7r_none_eabi),
|
||||
("thumbv7r-none-eabi", thumbv7r_none_eabi),
|
||||
("armv7r-none-eabihf", armv7r_none_eabihf),
|
||||
("thumbv7r-none-eabihf", thumbv7r_none_eabihf),
|
||||
("armv8r-none-eabihf", armv8r_none_eabihf),
|
||||
("thumbv8r-none-eabihf", thumbv8r_none_eabihf),
|
||||
|
||||
("armv7-rtems-eabihf", armv7_rtems_eabihf),
|
||||
|
||||
|
|
@ -1649,7 +1652,9 @@ supported_targets! {
|
|||
("thumbv8m.main-none-eabihf", thumbv8m_main_none_eabihf),
|
||||
|
||||
("armv7a-none-eabi", armv7a_none_eabi),
|
||||
("thumbv7a-none-eabi", thumbv7a_none_eabi),
|
||||
("armv7a-none-eabihf", armv7a_none_eabihf),
|
||||
("thumbv7a-none-eabihf", thumbv7a_none_eabihf),
|
||||
("armv7a-nuttx-eabi", armv7a_nuttx_eabi),
|
||||
("armv7a-nuttx-eabihf", armv7a_nuttx_eabihf),
|
||||
("armv7a-vex-v5", armv7a_vex_v5),
|
||||
|
|
|
|||
26
compiler/rustc_target/src/spec/targets/thumbv7a_none_eabi.rs
Normal file
26
compiler/rustc_target/src/spec/targets/thumbv7a_none_eabi.rs
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A)
|
||||
|
||||
use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
|
||||
|
||||
pub(crate) fn target() -> Target {
|
||||
Target {
|
||||
llvm_target: "thumbv7a-none-eabi".into(),
|
||||
metadata: TargetMetadata {
|
||||
description: Some("Thumb-mode Bare Armv7-A".into()),
|
||||
tier: Some(2),
|
||||
host_tools: Some(false),
|
||||
std: Some(false),
|
||||
},
|
||||
pointer_width: 32,
|
||||
data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
|
||||
arch: Arch::Arm,
|
||||
options: TargetOptions {
|
||||
abi: Abi::Eabi,
|
||||
llvm_floatabi: Some(FloatAbi::Soft),
|
||||
features: "+soft-float,-neon,+strict-align".into(),
|
||||
max_atomic_width: Some(64),
|
||||
has_thumb_interworking: true,
|
||||
..base::arm_none::opts()
|
||||
},
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A)
|
||||
|
||||
use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
|
||||
|
||||
pub(crate) fn target() -> Target {
|
||||
Target {
|
||||
llvm_target: "thumbv7a-none-eabihf".into(),
|
||||
metadata: TargetMetadata {
|
||||
description: Some("Thumb-mode Bare Armv7-A, hardfloat".into()),
|
||||
tier: Some(2),
|
||||
host_tools: Some(false),
|
||||
std: Some(false),
|
||||
},
|
||||
pointer_width: 32,
|
||||
data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
|
||||
arch: Arch::Arm,
|
||||
options: TargetOptions {
|
||||
abi: Abi::EabiHf,
|
||||
llvm_floatabi: Some(FloatAbi::Hard),
|
||||
features: "+vfp3d16,-neon,+strict-align".into(),
|
||||
max_atomic_width: Some(64),
|
||||
has_thumb_interworking: true,
|
||||
..base::arm_none::opts()
|
||||
},
|
||||
}
|
||||
}
|
||||
25
compiler/rustc_target/src/spec/targets/thumbv7r_none_eabi.rs
Normal file
25
compiler/rustc_target/src/spec/targets/thumbv7r_none_eabi.rs
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
// Targets the Little-endian Cortex-R4/R5 processor (ARMv7-R)
|
||||
|
||||
use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
|
||||
|
||||
pub(crate) fn target() -> Target {
|
||||
Target {
|
||||
llvm_target: "thumbv7r-none-eabi".into(),
|
||||
metadata: TargetMetadata {
|
||||
description: Some("Thumb-mode Bare Armv7-R".into()),
|
||||
tier: Some(2),
|
||||
host_tools: Some(false),
|
||||
std: Some(false),
|
||||
},
|
||||
pointer_width: 32,
|
||||
data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
|
||||
arch: Arch::Arm,
|
||||
options: TargetOptions {
|
||||
abi: Abi::Eabi,
|
||||
llvm_floatabi: Some(FloatAbi::Soft),
|
||||
max_atomic_width: Some(64),
|
||||
has_thumb_interworking: true,
|
||||
..base::arm_none::opts()
|
||||
},
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
// Targets the Little-endian Cortex-R4F/R5F processor (ARMv7-R)
|
||||
|
||||
use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
|
||||
|
||||
pub(crate) fn target() -> Target {
|
||||
Target {
|
||||
llvm_target: "thumbv7r-none-eabihf".into(),
|
||||
metadata: TargetMetadata {
|
||||
description: Some("Thumb-mode Bare Armv7-R, hardfloat".into()),
|
||||
tier: Some(2),
|
||||
host_tools: Some(false),
|
||||
std: Some(false),
|
||||
},
|
||||
pointer_width: 32,
|
||||
data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
|
||||
arch: Arch::Arm,
|
||||
options: TargetOptions {
|
||||
abi: Abi::EabiHf,
|
||||
llvm_floatabi: Some(FloatAbi::Hard),
|
||||
features: "+vfp3d16".into(),
|
||||
max_atomic_width: Some(64),
|
||||
has_thumb_interworking: true,
|
||||
..base::arm_none::opts()
|
||||
},
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
// Targets the Little-endian Cortex-R52 processor (ARMv8-R)
|
||||
|
||||
use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
|
||||
|
||||
pub(crate) fn target() -> Target {
|
||||
Target {
|
||||
llvm_target: "thumbv8r-none-eabihf".into(),
|
||||
metadata: TargetMetadata {
|
||||
description: Some("Thumb-mode Bare Armv8-R, hardfloat".into()),
|
||||
tier: Some(2),
|
||||
host_tools: Some(false),
|
||||
std: Some(false),
|
||||
},
|
||||
pointer_width: 32,
|
||||
data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
|
||||
arch: Arch::Arm,
|
||||
|
||||
options: TargetOptions {
|
||||
abi: Abi::EabiHf,
|
||||
llvm_floatabi: Some(FloatAbi::Hard),
|
||||
// Armv8-R requires a minimum set of floating-point features equivalent to:
|
||||
// fp-armv8, SP-only, with 16 DP (32 SP) registers
|
||||
// LLVM defines Armv8-R to include these features automatically.
|
||||
//
|
||||
// The Cortex-R52 supports these default features and optionally includes:
|
||||
// neon-fp-armv8, SP+DP, with 32 DP registers
|
||||
//
|
||||
// Reference:
|
||||
// Arm Cortex-R52 Processor Technical Reference Manual
|
||||
// - Chapter 15 Advanced SIMD and floating-point support
|
||||
max_atomic_width: Some(64),
|
||||
has_thumb_interworking: true,
|
||||
..base::arm_none::opts()
|
||||
},
|
||||
}
|
||||
}
|
||||
|
|
@ -38,6 +38,11 @@ pub struct Finder {
|
|||
const STAGE0_MISSING_TARGETS: &[&str] = &[
|
||||
// just a dummy comment so the list doesn't get onelined
|
||||
"x86_64-unknown-linux-gnuasan",
|
||||
"thumbv7a-none-eabi",
|
||||
"thumbv7a-none-eabihf",
|
||||
"thumbv7r-none-eabi",
|
||||
"thumbv7r-none-eabihf",
|
||||
"thumbv8r-none-eabihf",
|
||||
];
|
||||
|
||||
/// Minimum version threshold for libstdc++ required when using prebuilt LLVM
|
||||
|
|
|
|||
|
|
@ -411,17 +411,22 @@ target | std | host | notes
|
|||
[`thumbv4t-none-eabi`](platform-support/armv4t-none-eabi.md) | * | | Thumb-mode Bare Armv4T
|
||||
[`thumbv5te-none-eabi`](platform-support/armv5te-none-eabi.md) | * | | Thumb-mode Bare Armv5TE
|
||||
[`thumbv6m-nuttx-eabi`](platform-support/nuttx.md) | ✓ | | ARMv6M with NuttX
|
||||
`thumbv7a-pc-windows-msvc` | | |
|
||||
[`thumbv7a-uwp-windows-msvc`](platform-support/uwp-windows-msvc.md) | | |
|
||||
[`thumbv7a-none-eabi`](platform-support/armv7a-none-eabi.md) | * | | Thumb-mode Bare Armv7-A
|
||||
[`thumbv7a-none-eabihf`](platform-support/armv7a-none-eabi.md) | * | | Thumb-mode Bare Armv7-A, hardfloat
|
||||
[`thumbv7a-nuttx-eabi`](platform-support/nuttx.md) | ✓ | | ARMv7-A with NuttX
|
||||
[`thumbv7a-nuttx-eabihf`](platform-support/nuttx.md) | ✓ | | ARMv7-A with NuttX, hardfloat
|
||||
`thumbv7a-pc-windows-msvc` | | |
|
||||
[`thumbv7a-uwp-windows-msvc`](platform-support/uwp-windows-msvc.md) | | |
|
||||
[`thumbv7em-nuttx-eabi`](platform-support/nuttx.md) | ✓ | | ARMv7EM with NuttX
|
||||
[`thumbv7em-nuttx-eabihf`](platform-support/nuttx.md) | ✓ | | ARMv7EM with NuttX, hardfloat
|
||||
[`thumbv7m-nuttx-eabi`](platform-support/nuttx.md) | ✓ | | ARMv7M with NuttX
|
||||
`thumbv7neon-unknown-linux-musleabihf` | ? | | Thumb2-mode Armv7-A Linux with NEON, musl 1.2.5
|
||||
[`thumbv7r-none-eabi`](platform-support/armv7r-none-eabi.md) | * | | Thumb-mode Bare Armv7-R
|
||||
[`thumbv7r-none-eabihf`](platform-support/armv7r-none-eabi.md) | * | | Thumb-mode Bare Armv7-R, hardfloat
|
||||
[`thumbv8m.base-nuttx-eabi`](platform-support/nuttx.md) | ✓ | | ARMv8M Baseline with NuttX
|
||||
[`thumbv8m.main-nuttx-eabi`](platform-support/nuttx.md) | ✓ | | ARMv8M Mainline with NuttX
|
||||
[`thumbv8m.main-nuttx-eabihf`](platform-support/nuttx.md) | ✓ | | ARMv8M Mainline with NuttX, hardfloat
|
||||
[`thumbv8r-none-eabihf`](platform-support/armv8r-none-eabihf.md) | * | | Thumb-mode Bare Armv8-R, hardfloat
|
||||
[`wasm64-unknown-unknown`](platform-support/wasm64-unknown-unknown.md) | ? | | WebAssembly
|
||||
[`wasm32-wali-linux-musl`](platform-support/wasm32-wali-linux.md) | ? | | WebAssembly with [WALI](https://github.com/arjunr2/WALI)
|
||||
[`wasm32-wasip3`](platform-support/wasm32-wasip3.md) | ✓ | | WebAssembly with WASIp3
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
# `armv7a-none-eabi` and `armv7a-none-eabihf`
|
||||
# `armv7a-none-eabi` and `thumbv7a-none-eabihf`
|
||||
|
||||
* **Tier: 2**
|
||||
* **Tier: 2** (`armv7a-none-eabi`)
|
||||
* **Tier: 3** (`thumbv7a-none-eabi`)
|
||||
* **Library Support:** core and alloc (bare-metal, `#![no_std]`)
|
||||
|
||||
Bare-metal target for CPUs in the Armv7-A architecture family, supporting
|
||||
dual ARM/Thumb mode, with ARM mode as the default.
|
||||
Bare-metal target for CPUs in the Armv7-A architecture family, supporting dual
|
||||
ARM/Thumb mode. The `armv7a-none-eabi` target uses Arm mode by default and
|
||||
the `thumbv7a-none-eabihf` target uses Thumb mode by default.
|
||||
|
||||
Note, this is for processors running in AArch32 mode. For the AArch64 mode
|
||||
added in Armv8-A, see [`aarch64-unknown-none`](aarch64-unknown-none.md) instead.
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
# `armv7r-none-eabi` and `armv7r-none-eabihf`
|
||||
|
||||
* **Tier: 2**
|
||||
* **Tier: 2** (`armv7r-none-eabi`)
|
||||
* **Tier: 3** (`thumbv7r-none-eabi`)
|
||||
* **Library Support:** core and alloc (bare-metal, `#![no_std]`)
|
||||
|
||||
Bare-metal target for CPUs in the Armv7-R architecture family, supporting
|
||||
dual ARM/Thumb mode, with ARM mode as the default.
|
||||
Bare-metal target for CPUs in the Armv7-R architecture family, supporting dual
|
||||
ARM/Thumb mode. The `armv7r-none-eabi` target uses Arm mode by default and
|
||||
the `thumbv7r-none-eabihf` target uses Thumb mode by default.
|
||||
|
||||
Processors in this family include the [Arm Cortex-R4, 5, 7, and 8][cortex-r].
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
# `armv8r-none-eabihf`
|
||||
# `armv8r-none-eabihf` and `thumbv8r-none-eabihf`
|
||||
|
||||
* **Tier: 2**
|
||||
* **Tier: 2**: `armv8r-none-eabihf`
|
||||
* **Tier: 3**: `thumbv8r-none-eabihf`
|
||||
* **Library Support:** core and alloc (bare-metal, `#![no_std]`)
|
||||
|
||||
Bare-metal target for CPUs in the Armv8-R architecture family, supporting
|
||||
dual ARM/Thumb mode, with ARM mode as the default.
|
||||
Bare-metal target for CPUs in the Armv8-R architecture family, supporting dual
|
||||
ARM/Thumb mode. The `armv8r-none-eabi` target uses Arm mode by default and
|
||||
the `thumbv8r-none-eabihf` target uses Thumb mode by default.
|
||||
|
||||
Processors in this family include the Arm [Cortex-R52][cortex-r52]
|
||||
and [Cortex-R52+][cortex-r52-plus].
|
||||
|
|
|
|||
|
|
@ -559,6 +559,21 @@
|
|||
//@ revisions: thumbv5te_none_eabi
|
||||
//@ [thumbv5te_none_eabi] compile-flags: --target thumbv5te-none-eabi
|
||||
//@ [thumbv5te_none_eabi] needs-llvm-components: arm
|
||||
//@ revisions: thumbv7a_none_eabi
|
||||
//@ [thumbv7a_none_eabi] compile-flags: --target thumbv7a-none-eabi
|
||||
//@ [thumbv7a_none_eabi] needs-llvm-components: arm
|
||||
//@ revisions: thumbv7a_none_eabihf
|
||||
//@ [thumbv7a_none_eabihf] compile-flags: --target thumbv7a-none-eabihf
|
||||
//@ [thumbv7a_none_eabihf] needs-llvm-components: arm
|
||||
//@ revisions: thumbv7r_none_eabi
|
||||
//@ [thumbv7r_none_eabi] compile-flags: --target thumbv7r-none-eabi
|
||||
//@ [thumbv7r_none_eabi] needs-llvm-components: arm
|
||||
//@ revisions: thumbv7r_none_eabihf
|
||||
//@ [thumbv7r_none_eabihf] compile-flags: --target thumbv7r-none-eabihf
|
||||
//@ [thumbv7r_none_eabihf] needs-llvm-components: arm
|
||||
//@ revisions: thumbv8r_none_eabihf
|
||||
//@ [thumbv8r_none_eabihf] compile-flags: --target thumbv8r-none-eabihf
|
||||
//@ [thumbv8r_none_eabihf] needs-llvm-components: arm
|
||||
//@ revisions: thumbv6m_none_eabi
|
||||
//@ [thumbv6m_none_eabi] compile-flags: --target thumbv6m-none-eabi
|
||||
//@ [thumbv6m_none_eabi] needs-llvm-components: arm
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue