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Fix: Assembly mistakes in RISC-V Zk extensions

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This commit is contained in:
Gijs Burghoorn 2023-08-15 13:56:49 +02:00 • committed by Amanieu d'Antras
parent 1c5eb32416
commit 992bd5e1a9
3 changed files with 7 additions and 7 deletions
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6
library/stdarch/crates/core_arch/src/riscv32/zk.rs
View file

@ -142,9 +142,6 @@ pub unsafe fn aes32dsi(rs1: u32, rs2: u32, bs: u8) -> u32 {
constify_imm2!(bs, aes32dsi)
}
#[target_feature(enable = "zknd")]
#[cfg_attr(test, assert_instr(aes32dsmi))]
#[inline]
/// AES middle round decryption instruction for RV32.
///
/// This instruction sources a single byte from rs2 according to bs. To this it applies the
@ -166,6 +163,9 @@ pub unsafe fn aes32dsi(rs1: u32, rs2: u32, bs: u8) -> u32 {
/// # Safety
///
/// This function is safe to use if the `zknd` target feature is present.
#[target_feature(enable = "zknd")]
#[cfg_attr(test, assert_instr(aes32dsmi))]
#[inline]
pub unsafe fn aes32dsmi(rs1: u32, rs2: u32, bs: u8) -> u32 {
macro_rules! aes32dsmi {
($imm2:expr) => {{

4
library/stdarch/crates/core_arch/src/riscv64/zk.rs
View file

@ -142,7 +142,7 @@ pub unsafe fn aes64dsm(rs1: u64, rs2: u64) -> u64 {
let value: u64;
unsafe {
asm!(
"aes64esm {rd},{rs1},{rs2}",
"aes64dsm {rd},{rs1},{rs2}",
rd = lateout(reg) value,
rs1 = in(reg) rs1,
rs2 = in(reg) rs2,
@ -378,7 +378,7 @@ pub unsafe fn sha512sum1(rs1: u64) -> u64 {
let value: u64;
unsafe {
asm!(
"sha512sum0 {rd},{rs1}",
"sha512sum1 {rd},{rs1}",
rd = lateout(reg) value,
rs1 = in(reg) rs1,
options(pure, nomem, nostack),

4
library/stdarch/crates/core_arch/src/riscv_shared/zk.rs
View file

@ -267,7 +267,7 @@ pub unsafe fn sha256sum0(rs1: usize) -> usize {
let value: usize;
unsafe {
asm!(
"sha256sig1 {rd},{rs1}",
"sha256sum0 {rd},{rs1}",
rd = lateout(reg) value,
rs1 = in(reg) rs1,
options(pure, nomem, nostack),
@ -302,7 +302,7 @@ pub unsafe fn sha256sum1(rs1: usize) -> usize {
let value: usize;
unsafe {
asm!(
"sha256sig1 {rd},{rs1}",
"sha256sum1 {rd},{rs1}",
rd = lateout(reg) value,
rs1 = in(reg) rs1,
options(pure, nomem, nostack),