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Refactor avx512f: element extraction

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This commit is contained in:
Tobias Decking 2024-06-29 22:13:56 +02:00 • committed by Amanieu d'Antras
parent 9a1d758f03
commit 9f96670b7c
2 changed files with 35 additions and 4 deletions
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2
library/stdarch/crates/core_arch/missing-x86.md
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@ -157,8 +157,6 @@
* [ ] [`_kshiftli_mask16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_kshiftli_mask16)
* [ ] [`_kshiftri_mask16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_kshiftri_mask16)
* [ ] [`_load_mask16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_load_mask16)
* [ ] [`_mm512_cvtsd_f64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtsd_f64)
* [ ] [`_mm512_cvtss_f32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtss_f32)
* [ ] [`_mm512_i32logather_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32logather_epi64)
* [ ] [`_mm512_i32logather_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32logather_pd)
* [ ] [`_mm512_i32loscatter_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_i32loscatter_epi64)

37
library/stdarch/crates/core_arch/src/x86/avx512f.rs
View file

@ -25318,8 +25318,27 @@ pub unsafe fn _mm512_castsi512_pd(a: __m512i) -> __m512d {
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovd))]
pub unsafe fn _mm512_cvtsi512_si32(a: __m512i) -> i32 {
let extract: i32 = simd_extract!(a.as_i32x16(), 0);
extract
simd_extract!(a.as_i32x16(), 0)
}
/// Copy the lower single-precision (32-bit) floating-point element of a to dst.
///
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtss_f32)
#[inline]
#[target_feature(enable = "avx512f")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub unsafe fn _mm512_cvtss_f32(a: __m512) -> f32 {
simd_extract!(a, 0)
}
/// Copy the lower double-precision (64-bit) floating-point element of a to dst.
///
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtsd_f64)
#[inline]
#[target_feature(enable = "avx512f")]
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
pub unsafe fn _mm512_cvtsd_f64(a: __m512d) -> f64 {
simd_extract!(a, 0)
}
/// Broadcast the low packed 32-bit integer from a to all elements of dst.
@ -58278,6 +58297,20 @@ mod tests {
assert_eq!(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_cvtss_f32() {
let a = _mm512_setr_ps(
312.0134, 3., 2., 5., 8., 9., 64., 50., -4., -3., -2., -5., -8., -9., -64., -50.,
);
assert_eq!(_mm512_cvtss_f32(a), 312.0134);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_cvtsd_f64() {
let r = _mm512_cvtsd_f64(_mm512_setr_pd(-1.1, 2.2, 3.3, 4.4, 5.5, 6.6, 7.7, 8.8));
assert_eq!(r, -1.1);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_shuffle_pd() {
let a = _mm512_setr_pd(1., 4., 5., 8., 1., 4., 5., 8.);