From a0b865dc8782500efe9623859017dd5e16f85407 Mon Sep 17 00:00:00 2001
From: bjorn3 <17426603+bjorn3@users.noreply.github.com>
Date: Sat, 8 Nov 2025 13:35:51 +0000
Subject: [PATCH] Fix simd_gather intrinsic

---
 src/intrinsics/simd.rs | 27 +++++++++++----------------
 1 file changed, 11 insertions(+), 16 deletions(-)

diff --git a/src/intrinsics/simd.rs b/src/intrinsics/simd.rs
index 59f46cbefe2d..1504869b89e0 100644
--- a/src/intrinsics/simd.rs
+++ b/src/intrinsics/simd.rs
@@ -1006,15 +1006,6 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
             let lane_clif_ty = fx.clif_type(val_lane_ty).unwrap();
             let ret_lane_layout = fx.layout_of(ret_lane_ty);
 
-            let alignment = generic_args[3].expect_const().to_value().valtree.unwrap_branch()[0]
-                .unwrap_leaf()
-                .to_simd_alignment();
-
-            let memflags = match alignment {
-                SimdAlign::Unaligned => MemFlags::new().with_notrap(),
-                _ => MemFlags::trusted(),
-            };
-
             for lane_idx in 0..ptr_lane_count {
                 let val_lane = val.value_lane(fx, lane_idx).load_scalar(fx);
                 let ptr_lane = ptr.value_lane(fx, lane_idx).load_scalar(fx);
@@ -1030,7 +1021,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
                 fx.bcx.seal_block(if_disabled);
 
                 fx.bcx.switch_to_block(if_enabled);
-                let res = fx.bcx.ins().load(lane_clif_ty, memflags, ptr_lane, 0);
+                let res = fx.bcx.ins().load(lane_clif_ty, MemFlags::trusted(), ptr_lane, 0);
                 fx.bcx.ins().jump(next, &[res.into()]);
 
                 fx.bcx.switch_to_block(if_disabled);
@@ -1059,6 +1050,15 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
             let ret_lane_layout = fx.layout_of(ret_lane_ty);
             let ptr_val = ptr.load_scalar(fx);
 
+            let alignment = generic_args[3].expect_const().to_value().valtree.unwrap_branch()[0]
+                .unwrap_leaf()
+                .to_simd_alignment();
+
+            let memflags = match alignment {
+                SimdAlign::Unaligned => MemFlags::new().with_notrap(),
+                _ => MemFlags::trusted(),
+            };
+
             for lane_idx in 0..ret_lane_count {
                 let val_lane = val.value_lane(fx, lane_idx).load_scalar(fx);
                 let mask_lane = mask.value_lane(fx, lane_idx).load_scalar(fx);
@@ -1074,12 +1074,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
 
                 fx.bcx.switch_to_block(if_enabled);
                 let offset = lane_idx as i32 * lane_clif_ty.bytes() as i32;
-                let res = fx.bcx.ins().load(
-                    lane_clif_ty,
-                    MemFlags::trusted(),
-                    ptr_val,
-                    Offset32::new(offset),
-                );
+                let res = fx.bcx.ins().load(lane_clif_ty, memflags, ptr_val, Offset32::new(offset));
                 fx.bcx.ins().jump(next, &[res.into()]);
 
                 fx.bcx.switch_to_block(if_disabled);