Convert all uses of llvm_asm! to asm! (#1052)
This commit is contained in:
Amanieu d'Antras
GitHub
parent
7accc82569
commit
a1e151e838
12 changed files with 161 additions and 140 deletions
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@ -8,20 +8,29 @@ pub struct SY;
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impl super::super::sealed::Dmb for SY {
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#[inline(always)]
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unsafe fn __dmb(&self) {
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llvm_asm!("mcr p15, 0, r0, c7, c10, 5" : : : "memory" : "volatile")
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asm!(
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"mcr p15, 0, r0, c7, c10, 5",
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options(preserves_flags, nostack)
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)
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}
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}
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impl super::super::sealed::Dsb for SY {
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#[inline(always)]
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unsafe fn __dsb(&self) {
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llvm_asm!("mcr p15, 0, r0, c7, c10, 4" : : : "memory" : "volatile")
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asm!(
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"mcr p15, 0, r0, c7, c10, 4",
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options(preserves_flags, nostack)
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)
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}
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}
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impl super::super::sealed::Isb for SY {
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#[inline(always)]
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unsafe fn __isb(&self) {
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llvm_asm!("mcr p15, 0, r0, c7, c5, 4" : : : "memory" : "volatile")
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asm!(
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"mcr p15, 0, r0, c7, c5, 4",
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options(preserves_flags, nostack)
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)
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}
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}
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@ -80,33 +80,13 @@ pub unsafe fn __yield() {
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// and ARMv7-R edition (ARM DDI 0406C.c) sections D12.4.1 "ARM instruction set support" and D12.4.2
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// "Thumb instruction set support"
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#[cfg(target_feature = "v7")]
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#[cfg(any(target_arch = "arm", doc))]
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#[doc(cfg(target_arch = "arm"))]
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#[inline(always)]
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#[rustc_args_required_const(0)]
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pub unsafe fn __dbg(imm4: u32) {
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macro_rules! call {
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($imm4:expr) => {
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llvm_asm!(concat!("DBG ", stringify!($imm4)) : : : : "volatile")
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}
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}
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match imm4 & 0b1111 {
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0 => call!(0),
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1 => call!(1),
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2 => call!(2),
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3 => call!(3),
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4 => call!(4),
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5 => call!(5),
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6 => call!(6),
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7 => call!(7),
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8 => call!(8),
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9 => call!(9),
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10 => call!(10),
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11 => call!(11),
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12 => call!(12),
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13 => call!(13),
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14 => call!(14),
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_ => call!(15),
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}
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#[rustc_legacy_const_generics(0)]
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pub unsafe fn __dbg<const IMM4: i32>() {
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static_assert_imm4!(IMM4);
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dbg(IMM4);
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}
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/// Generates an unspecified no-op instruction.
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@ -117,13 +97,17 @@ pub unsafe fn __dbg(imm4: u32) {
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/// will increase execution time.
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#[inline(always)]
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pub unsafe fn __nop() {
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llvm_asm!("NOP" : : : : "volatile")
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asm!("nop", options(nomem, nostack, preserves_flags));
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}
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extern "C" {
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#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.hint")]
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#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.hint")]
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fn hint(_: i32);
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#[cfg(target_arch = "arm")]
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#[link_name = "llvm.arm.dbg"]
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fn dbg(_: i32);
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}
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// from LLVM 7.0.1's lib/Target/ARM/{ARMInstrThumb,ARMInstrInfo,ARMInstrThumb2}.td
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@ -4,7 +4,7 @@ macro_rules! rsr {
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impl super::super::sealed::Rsr for $R {
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unsafe fn __rsr(&self) -> u32 {
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let r: u32;
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llvm_asm!(concat!("mrs $0,", stringify!($R)) : "=r"(r) : : : "volatile");
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asm!(concat!("mrs {},", stringify!($R)), out(reg) r, options(nomem, nostack));
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r
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}
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}
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@ -17,7 +17,7 @@ macro_rules! rsrp {
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impl super::super::sealed::Rsrp for $R {
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unsafe fn __rsrp(&self) -> *const u8 {
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let r: *const u8;
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llvm_asm!(concat!("mrs $0,", stringify!($R)) : "=r"(r) : : : "volatile");
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asm!(concat!("mrs {},", stringify!($R)), out(reg) r, options(nomem, nostack));
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r
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}
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}
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@ -29,7 +29,7 @@ macro_rules! wsr {
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($R:ident) => {
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impl super::super::sealed::Wsr for $R {
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unsafe fn __wsr(&self, value: u32) {
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llvm_asm!(concat!("msr ", stringify!($R), ",$0") : : "r"(value) : : "volatile");
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asm!(concat!("msr ", stringify!($R), ", {}"), in(reg) value, options(nomem, nostack));
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}
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}
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};
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@ -40,7 +40,7 @@ macro_rules! wsrp {
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($R:ident) => {
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impl super::super::sealed::Wsrp for $R {
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unsafe fn __wsrp(&self, value: *const u8) {
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llvm_asm!(concat!("msr ", stringify!($R), ",$0") : : "r"(value) : : "volatile");
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asm!(concat!("msr ", stringify!($R), ", {}"), in(reg) value, options(nomem, nostack));
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}
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}
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};
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@ -11,58 +11,41 @@ use stdarch_test::assert_instr;
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/// Inserts a breakpoint instruction.
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///
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/// `val` is a compile-time constant integer in range `[0, 255]`.
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/// `VAL` is a compile-time constant integer in range `[0, 65535]`.
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///
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/// The breakpoint instruction inserted is:
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/// The breakpoint instruction inserted is `BRK` on A64.
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#[cfg(all(target_arch = "aarch64", not(doc)))]
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#[cfg_attr(test, assert_instr(brk, VAL = 0))]
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#[inline(always)]
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#[rustc_legacy_const_generics(0)]
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pub unsafe fn __breakpoint<const VAL: i32>() {
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static_assert_imm16!(VAL);
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asm!("brk {}", const VAL);
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}
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/// Inserts a breakpoint instruction.
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///
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/// * `BKPT` when compiling as T32,
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/// * `BRK` when compiling as A32 or A64.
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/// `VAL` is a compile-time constant integer in range `[0, 255]`.
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///
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/// # Safety
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///
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/// If `val` is out-of-range the behavior is **undefined**.
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/// The breakpoint instruction inserted is `BKPT` on A32/T32.
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///
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/// # Note
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///
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/// [ARM's documentation][arm_docs] defines that `__breakpoint` accepts the
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/// following values for `val`:
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/// following values for `VAL`:
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///
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/// - `0...65535` when compiling as A32 or A64,
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/// - `0...65535` when compiling as A32,
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/// - `0...255` when compiling as T32.
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///
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/// The current implementation only accepts values in range `[0, 255]` - if the
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/// value is out-of-range the behavior is **undefined**.
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/// The current implementation only accepts values in range `[0, 255]`.
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///
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/// [arm_docs]: https://developer.arm.com/docs/100067/latest/compiler-specific-intrinsics/__breakpoint-intrinsic
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr(bkpt, val = 0))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(brk, val = 0))]
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#[cfg(any(target_arch = "arm", doc))]
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#[doc(cfg(target_arch = "arm"))]
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#[cfg_attr(test, assert_instr(bkpt, VAL = 0))]
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#[inline(always)]
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#[rustc_args_required_const(0)]
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pub unsafe fn __breakpoint(val: i32) {
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// Ensure that this compiles correctly on non-arm architectures, so libstd
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// doc builds work. The proper macro will shadow this definition below.
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#[allow(unused_macros)]
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macro_rules! call {
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($e:expr) => {
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()
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};
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}
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#[cfg(target_arch = "arm")]
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macro_rules! call {
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($imm8:expr) => {
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llvm_asm!(concat!("BKPT ", stringify!($imm8)) : : : : "volatile")
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}
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}
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#[cfg(target_arch = "aarch64")]
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macro_rules! call {
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($imm8:expr) => {
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llvm_asm!(concat!("BRK ", stringify!($imm8)) : : : : "volatile")
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}
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}
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// We can't `panic!` inside this intrinsic, so we can't really validate the
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// arguments here. If `val` is out-of-range this macro uses `val == 255`:
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constify_imm8!(val, call);
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#[rustc_legacy_const_generics(0)]
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pub unsafe fn __breakpoint<const VAL: i32>() {
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static_assert_imm8!(VAL);
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asm!("bkpt #{}", const VAL);
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}
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@ -12,7 +12,6 @@
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platform_intrinsics,
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repr_simd,
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simd_ffi,
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llvm_asm,
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proc_macro_hygiene,
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stmt_expr_attributes,
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core_intrinsics,
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@ -58,6 +58,13 @@ macro_rules! static_assert_imm8 {
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};
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}
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#[allow(unused_macros)]
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macro_rules! static_assert_imm16 {
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($imm:ident) => {
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let _ = $crate::core_arch::macros::ValidateConstImm::<$imm, 0, { (1 << 16) - 1 }>::VALID;
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};
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}
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#[allow(unused)]
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macro_rules! static_assert {
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($imm:ident : $ty:ty where $e:expr) => {
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@ -7,10 +7,14 @@ use stdarch_test::assert_instr;
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#[unstable(feature = "simd_x86_bittest", issue = "59414")]
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pub unsafe fn _bittest(p: *const i32, b: i32) -> u8 {
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let r: u8;
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llvm_asm!("btl $2, $1\n\tsetc ${0:b}"
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: "=r"(r)
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: "*m"(p), "r"(b)
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: "cc", "memory");
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asm!(
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"bt [{p}], {b:e}",
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"setc {r}",
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p = in(reg) p,
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b = in(reg) b,
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r = out(reg_byte) r,
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options(readonly, nostack, pure)
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);
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r
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}
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@ -20,10 +24,14 @@ pub unsafe fn _bittest(p: *const i32, b: i32) -> u8 {
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#[unstable(feature = "simd_x86_bittest", issue = "59414")]
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pub unsafe fn _bittestandset(p: *mut i32, b: i32) -> u8 {
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let r: u8;
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llvm_asm!("btsl $2, $1\n\tsetc ${0:b}"
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: "=r"(r), "+*m"(p)
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: "r"(b)
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: "cc", "memory");
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asm!(
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"bts [{p}], {b:e}",
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"setc {r}",
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p = in(reg) p,
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b = in(reg) b,
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r = out(reg_byte) r,
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options(nostack)
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);
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r
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}
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@ -33,10 +41,14 @@ pub unsafe fn _bittestandset(p: *mut i32, b: i32) -> u8 {
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#[unstable(feature = "simd_x86_bittest", issue = "59414")]
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pub unsafe fn _bittestandreset(p: *mut i32, b: i32) -> u8 {
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let r: u8;
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llvm_asm!("btrl $2, $1\n\tsetc ${0:b}"
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: "=r"(r), "+*m"(p)
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: "r"(b)
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: "cc", "memory");
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asm!(
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"btr [{p}], {b:e}",
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"setc {r}",
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p = in(reg) p,
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b = in(reg) b,
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r = out(reg_byte) r,
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options(nostack)
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);
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r
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}
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@ -46,10 +58,14 @@ pub unsafe fn _bittestandreset(p: *mut i32, b: i32) -> u8 {
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#[unstable(feature = "simd_x86_bittest", issue = "59414")]
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pub unsafe fn _bittestandcomplement(p: *mut i32, b: i32) -> u8 {
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let r: u8;
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llvm_asm!("btcl $2, $1\n\tsetc ${0:b}"
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: "=r"(r), "+*m"(p)
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: "r"(b)
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: "cc", "memory");
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asm!(
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"btc [{p}], {b:e}",
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"setc {r}",
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p = in(reg) p,
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b = in(reg) b,
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r = out(reg_byte) r,
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options(nostack)
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);
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r
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}
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@ -125,30 +125,25 @@ pub fn has_cpuid() -> bool {
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// the 21st bit of the EFLAGS register is modifiable or not.
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// If it is, then `cpuid` is available.
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let result: u32;
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let _temp: u32;
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llvm_asm!(r#"
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# Read eflags into $0 and copy it into $1:
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pushfd
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pop $0
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mov $1, $0
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# Flip 21st bit of $0.
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xor $0, 0x200000
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# Set eflags to the value of $0
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#
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# Bit 21st can only be modified if cpuid is available
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push $0
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popfd # A
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# Read eflags into $0:
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pushfd # B
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pop $0
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# xor with the original eflags sets the bits that
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# have been modified:
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xor $0, $1
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"#
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: "=r"(result), "=r"(_temp)
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:
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: "cc", "memory"
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: "intel");
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asm!(
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// Read eflags and save a copy of it
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"pushfd",
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"pop {result}",
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"mov {saved_flags}, {result}",
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// Flip 21st bit of the flags
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"xor {result}, 0x200000",
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// Load the modified flags and read them back.
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// Bit 21 can only be modified if cpuid is available.
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"push {result}",
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"popfd",
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"pushfd",
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"pop {result}",
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// Use xor to find out whether bit 21 has changed
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"xor {result}, {saved_flags}",
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result = out(reg) result,
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saved_flags = out(reg) _,
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options(nomem),
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);
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// There is a race between popfd (A) and pushfd (B)
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// where other bits beyond 21st may have been modified due to
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// interrupts, a debugger stepping through the asm, etc.
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@ -13,7 +13,7 @@
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#[doc(hidden)]
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pub unsafe fn __readeflags() -> u32 {
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let eflags: u32;
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llvm_asm!("pushfd; popl $0" : "=r"(eflags) : : : "volatile");
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asm!("pushfd", "pop {}", out(reg) eflags, options(nomem));
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eflags
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}
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@ -30,7 +30,7 @@ pub unsafe fn __readeflags() -> u32 {
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#[doc(hidden)]
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pub unsafe fn __readeflags() -> u64 {
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let eflags: u64;
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llvm_asm!("pushfq; popq $0" : "=r"(eflags) : : : "volatile");
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asm!("pushfq", "pop {}", out(reg) eflags, options(nomem));
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eflags
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}
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@ -46,7 +46,7 @@ pub unsafe fn __readeflags() -> u64 {
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)]
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#[doc(hidden)]
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pub unsafe fn __writeeflags(eflags: u32) {
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llvm_asm!("pushl $0; popfd" : : "r"(eflags) : "cc", "flags" : "volatile");
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asm!("push {}", "popfd", in(reg) eflags, options(nomem));
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}
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/// Write EFLAGS.
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@ -61,7 +61,7 @@ pub unsafe fn __writeeflags(eflags: u32) {
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)]
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#[doc(hidden)]
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pub unsafe fn __writeeflags(eflags: u64) {
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llvm_asm!("pushq $0; popfq" : : "r"(eflags) : "cc", "flags" : "volatile");
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asm!("push {}", "popfq", in(reg) eflags, options(nomem));
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}
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#[cfg(test)]
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@ -7,10 +7,14 @@ use stdarch_test::assert_instr;
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#[unstable(feature = "simd_x86_bittest", issue = "59414")]
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pub unsafe fn _bittest64(p: *const i64, b: i64) -> u8 {
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let r: u8;
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llvm_asm!("btq $2, $1\n\tsetc ${0:b}"
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: "=r"(r)
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: "*m"(p), "r"(b)
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: "cc", "memory");
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asm!(
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"bt [{p}], {b}",
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"setc {r}",
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p = in(reg) p,
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b = in(reg) b,
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r = out(reg_byte) r,
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options(readonly, nostack, pure)
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);
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r
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}
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@ -20,10 +24,14 @@ pub unsafe fn _bittest64(p: *const i64, b: i64) -> u8 {
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#[unstable(feature = "simd_x86_bittest", issue = "59414")]
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pub unsafe fn _bittestandset64(p: *mut i64, b: i64) -> u8 {
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let r: u8;
|
||||
llvm_asm!("btsq $2, $1\n\tsetc ${0:b}"
|
||||
: "=r"(r), "+*m"(p)
|
||||
: "r"(b)
|
||||
: "cc", "memory");
|
||||
asm!(
|
||||
"bts [{p}], {b}",
|
||||
"setc {r}",
|
||||
p = in(reg) p,
|
||||
b = in(reg) b,
|
||||
r = out(reg_byte) r,
|
||||
options(nostack)
|
||||
);
|
||||
r
|
||||
}
|
||||
|
||||
|
|
@ -33,10 +41,14 @@ pub unsafe fn _bittestandset64(p: *mut i64, b: i64) -> u8 {
|
|||
#[unstable(feature = "simd_x86_bittest", issue = "59414")]
|
||||
pub unsafe fn _bittestandreset64(p: *mut i64, b: i64) -> u8 {
|
||||
let r: u8;
|
||||
llvm_asm!("btrq $2, $1\n\tsetc ${0:b}"
|
||||
: "=r"(r), "+*m"(p)
|
||||
: "r"(b)
|
||||
: "cc", "memory");
|
||||
asm!(
|
||||
"btr [{p}], {b}",
|
||||
"setc {r}",
|
||||
p = in(reg) p,
|
||||
b = in(reg) b,
|
||||
r = out(reg_byte) r,
|
||||
options(nostack)
|
||||
);
|
||||
r
|
||||
}
|
||||
|
||||
|
|
@ -46,10 +58,14 @@ pub unsafe fn _bittestandreset64(p: *mut i64, b: i64) -> u8 {
|
|||
#[unstable(feature = "simd_x86_bittest", issue = "59414")]
|
||||
pub unsafe fn _bittestandcomplement64(p: *mut i64, b: i64) -> u8 {
|
||||
let r: u8;
|
||||
llvm_asm!("btcq $2, $1\n\tsetc ${0:b}"
|
||||
: "=r"(r), "+*m"(p)
|
||||
: "r"(b)
|
||||
: "cc", "memory");
|
||||
asm!(
|
||||
"btc [{p}], {b}",
|
||||
"setc {r}",
|
||||
p = in(reg) p,
|
||||
b = in(reg) b,
|
||||
r = out(reg_byte) r,
|
||||
options(nostack)
|
||||
);
|
||||
r
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -34,7 +34,11 @@ pub(crate) fn detect_features() -> cache::Initializer {
|
|||
// ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
|
||||
let aa64isar0: u64;
|
||||
unsafe {
|
||||
llvm_asm!("mrs $0, ID_AA64ISAR0_EL1" : "=r"(aa64isar0));
|
||||
asm!(
|
||||
"mrs {}, ID_AA64ISAR0_EL1",
|
||||
out(reg) aa64isar0,
|
||||
options(pure, nomem, preserves_flags, nostack)
|
||||
);
|
||||
}
|
||||
|
||||
let aes = bits_shift(aa64isar0, 7, 4) >= 1;
|
||||
|
|
@ -51,7 +55,11 @@ pub(crate) fn detect_features() -> cache::Initializer {
|
|||
// ID_AA64PFR0_EL1 - Processor Feature Register 0
|
||||
let aa64pfr0: u64;
|
||||
unsafe {
|
||||
llvm_asm!("mrs $0, ID_AA64PFR0_EL1" : "=r"(aa64pfr0));
|
||||
asm!(
|
||||
"mrs {}, ID_AA64PFR0_EL1",
|
||||
out(reg) aa64pfr0,
|
||||
options(pure, nomem, preserves_flags, nostack)
|
||||
);
|
||||
}
|
||||
|
||||
let fp = bits_shift(aa64pfr0, 19, 16) < 0xF;
|
||||
|
|
@ -74,7 +82,11 @@ pub(crate) fn detect_features() -> cache::Initializer {
|
|||
// ID_AA64ISAR1_EL1 - Instruction Set Attribute Register 1
|
||||
let aa64isar1: u64;
|
||||
unsafe {
|
||||
llvm_asm!("mrs $0, ID_AA64ISAR1_EL1" : "=r"(aa64isar1));
|
||||
asm!(
|
||||
"mrs {}, ID_AA64ISAR1_EL1",
|
||||
out(reg) aa64isar1,
|
||||
options(pure, nomem, preserves_flags, nostack)
|
||||
);
|
||||
}
|
||||
|
||||
enable_feature(Feature::rcpc, bits_shift(aa64isar1, 23, 20) >= 1);
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
#![feature(const_fn, staged_api, stdsimd, doc_cfg, allow_internal_unstable)]
|
||||
#![allow(clippy::shadow_reuse)]
|
||||
#![deny(clippy::missing_inline_in_public_items)]
|
||||
#![cfg_attr(all(target_os = "freebsd", target_arch = "aarch64"), feature(llvm_asm))]
|
||||
#![cfg_attr(all(target_os = "freebsd", target_arch = "aarch64"), feature(asm))]
|
||||
#![cfg_attr(test, allow(unused_imports))]
|
||||
#![cfg_attr(feature = "std_detect_file_io", feature(vec_spare_capacity))]
|
||||
#![no_std]
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue