From a1f9b6b848f354f0e423bc9bd88f12cfcf4ccd93 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:59:38 +0100 Subject: [PATCH] convert `_mm256_mask_dbsad_epu8` to const generics --- .../crates/core_arch/src/x86/avx512bw.rs | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/library/stdarch/crates/core_arch/src/x86/avx512bw.rs b/library/stdarch/crates/core_arch/src/x86/avx512bw.rs index 49b9864b676e..efcc6fc186eb 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512bw.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512bw.rs @@ -7938,23 +7938,18 @@ pub unsafe fn _mm256_dbsad_epu8(a: __m256i, b: __m256i) -> __m2 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_dbsad_epu8&expand=2112) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(4)] -#[cfg_attr(test, assert_instr(vdbpsadbw, imm8 = 0))] -pub unsafe fn _mm256_mask_dbsad_epu8( +#[rustc_legacy_const_generics(4)] +#[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))] +pub unsafe fn _mm256_mask_dbsad_epu8( src: __m256i, k: __mmask16, a: __m256i, b: __m256i, - imm8: i32, ) -> __m256i { + static_assert_imm8!(IMM8); let a = a.as_u8x32(); let b = b.as_u8x32(); - macro_rules! call { - ($imm8:expr) => { - vdbpsadbw256(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + let r = vdbpsadbw256(a, b, IMM8); transmute(simd_select_bitmask(k, r, src.as_u16x16())) } @@ -16899,9 +16894,9 @@ mod tests { let src = _mm256_set1_epi16(1); let a = _mm256_set1_epi8(2); let b = _mm256_set1_epi8(4); - let r = _mm256_mask_dbsad_epu8(src, 0, a, b, 0); + let r = _mm256_mask_dbsad_epu8::<0>(src, 0, a, b); assert_eq_m256i(r, src); - let r = _mm256_mask_dbsad_epu8(src, 0b11111111_11111111, a, b, 0); + let r = _mm256_mask_dbsad_epu8::<0>(src, 0b11111111_11111111, a, b); let e = _mm256_set1_epi16(8); assert_eq_m256i(r, e); }