From abc99c62595831127e8ac4dfd6ccacd7ccbf9942 Mon Sep 17 00:00:00 2001
From: bjorn3 <bjorn3@users.noreply.github.com>
Date: Fri, 27 Mar 2020 20:55:54 +0100
Subject: [PATCH] Allow storing SIMD vectors in SSA values

---
 src/common.rs          | 12 ++++++++++++
 src/lib.rs             |  9 ++++++---
 src/pretty_clif.rs     |  3 ++-
 src/value_and_place.rs |  2 ++
 4 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/src/common.rs b/src/common.rs
index c807bde15c30..166486c49a17 100644
--- a/src/common.rs
+++ b/src/common.rs
@@ -62,6 +62,18 @@ fn clif_type_from_ty<'tcx>(tcx: TyCtxt<'tcx>, ty: Ty<'tcx>) -> Option<types::Typ
                 pointer_ty(tcx)
             }
         }
+        ty::Adt(adt_def, _) if adt_def.repr.simd() => {
+            let (element, count) = match &tcx.layout_of(ParamEnv::reveal_all().and(ty)).unwrap().abi {
+                Abi::Vector { element, count } => (element.clone(), *count),
+                _ => unreachable!(),
+            };
+
+            match scalar_to_clif_type(tcx, element).by(u16::try_from(count).unwrap()) {
+                // Cranelift currently only implements icmp for 128bit vectors.
+                Some(vector_ty) if vector_ty.bits() == 128 => vector_ty,
+                _ => return None,
+            }
+        }
         ty::Param(_) => bug!("ty param {:?}", ty),
         _ => return None,
     })
diff --git a/src/lib.rs b/src/lib.rs
index 1096dbd227d6..0376672fba7a 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -299,6 +299,8 @@ fn build_isa(sess: &Session, enable_pic: bool) -> Box<dyn isa::TargetIsa + 'stat
     };
     flags_builder.set("tls_model", tls_model).unwrap();
 
+    flags_builder.set("enable_simd", "true").unwrap();
+
     // FIXME(CraneStation/cranelift#732) fix LICM in presence of jump tables
     /*
     use rustc_session::config::OptLevel;
@@ -316,9 +318,10 @@ fn build_isa(sess: &Session, enable_pic: bool) -> Box<dyn isa::TargetIsa + 'stat
     }*/
 
     let flags = settings::Flags::new(flags_builder);
-    cranelift_codegen::isa::lookup(target_triple)
-        .unwrap()
-        .finish(flags)
+
+    let mut isa_builder = cranelift_codegen::isa::lookup(target_triple).unwrap();
+    isa_builder.enable("haswell").unwrap();
+    isa_builder.finish(flags)
 }
 
 /// This is the entrypoint for a hot plugged rustc_codegen_cranelift
diff --git a/src/pretty_clif.rs b/src/pretty_clif.rs
index 0dcd2c269e83..64346c423c8a 100644
--- a/src/pretty_clif.rs
+++ b/src/pretty_clif.rs
@@ -248,7 +248,8 @@ pub(crate) fn write_clif_file<'tcx>(
             let target_triple = crate::target_triple(tcx.sess);
             writeln!(file, "test compile").unwrap();
             writeln!(file, "set is_pic").unwrap();
-            writeln!(file, "target {}", target_triple).unwrap();
+            writeln!(file, "set enable_simd").unwrap();
+            writeln!(file, "target {} haswell", target_triple).unwrap();
             writeln!(file, "").unwrap();
             file.write(clif.as_bytes()).unwrap();
         }
diff --git a/src/value_and_place.rs b/src/value_and_place.rs
index c9516a98bfe4..477a417639e9 100644
--- a/src/value_and_place.rs
+++ b/src/value_and_place.rs
@@ -589,6 +589,8 @@ impl<'tcx> CPlace<'tcx> {
         fx: &mut FunctionCx<'_, 'tcx, impl Backend>,
         field: mir::Field,
     ) -> CPlace<'tcx> {
+        // FIXME handle simd values
+
         let layout = self.layout();
         if let CPlaceInner::VarPair(local, var1, var2) = self.inner {
             let layout = layout.field(&*fx, field.index());