Avx512f (#927)
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ae707fa29d
7 changed files with 8922 additions and 241 deletions
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@ -159,10 +159,10 @@
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* [x] [`_mm512_extractf64x4_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_extractf64x4_pd&expand=5236)
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* [x] [`_mm512_extracti32x4_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_extracti32x4_epi32&expand=5236)
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* [x] [`_mm512_extracti64x4_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_extracti64x4_epi64&expand=5236)
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* [ ] [`_mm512_fixupimm_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fixupimm_pd&expand=5236)
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* [ ] [`_mm512_fixupimm_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fixupimm_ps&expand=5236)
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* [ ] [`_mm512_fixupimm_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fixupimm_round_pd&expand=5236)
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* [ ] [`_mm512_fixupimm_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fixupimm_round_ps&expand=5236)
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* [x] [`_mm512_fixupimm_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fixupimm_pd&expand=5236)
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* [x] [`_mm512_fixupimm_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fixupimm_ps&expand=5236)
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* [x] [`_mm512_fixupimm_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fixupimm_round_pd&expand=5236)
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* [x] [`_mm512_fixupimm_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fixupimm_round_ps&expand=5236)
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* [x] [`_mm512_fmadd_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmadd_pd&expand=5236)
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* [x] [`_mm512_fmadd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmadd_ps&expand=5236)
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* [x] [`_mm512_fmadd_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fmadd_round_pd&expand=5236)
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@ -226,7 +226,7 @@
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* [x] [`_mm512_insertf64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_insertf64x4&expand=5236)
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* [x] [`_mm512_inserti32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_inserti32x4&expand=5236)
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* [x] [`_mm512_inserti64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_inserti64x4&expand=5236)
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* [ ] [`_mm512_int2mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_int2mask&expand=5236)
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* [x] [`_mm512_int2mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_int2mask&expand=5236)
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* [x] [`_mm512_kand`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_kand&expand=5236)
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* [x] [`_mm512_kandn`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_kandn&expand=5236)
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* [x] [`_mm512_kmov`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_kmov&expand=5236)
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@ -251,7 +251,7 @@
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* [x] [`_mm512_mask2_permutex2var_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask2_permutex2var_epi64&expand=5236)
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* [x] [`_mm512_mask2_permutex2var_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask2_permutex2var_pd&expand=5236)
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* [x] [`_mm512_mask2_permutex2var_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask2_permutex2var_ps&expand=5236)
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* [ ] [`_mm512_mask2int`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask2int&expand=5236)
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* [x] [`_mm512_mask2int`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask2int&expand=5236)
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* [x] [`_mm512_mask3_fmadd_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmadd_pd&expand=5236)
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* [x] [`_mm512_mask3_fmadd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmadd_ps&expand=5236)
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* [x] [`_mm512_mask3_fmadd_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask3_fmadd_round_pd&expand=5236)
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@ -450,10 +450,10 @@
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* [x] [`_mm512_mask_extractf64x4_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_extractf64x4_pd&expand=5236)
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* [x] [`_mm512_mask_extracti32x4_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_extracti32x4_epi32&expand=5236)
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* [x] [`_mm512_mask_extracti64x4_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_extracti64x4_epi64&expand=5236)
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* [ ] [`_mm512_mask_fixupimm_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fixupimm_pd&expand=5236)
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* [ ] [`_mm512_mask_fixupimm_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fixupimm_ps&expand=5236)
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* [ ] [`_mm512_mask_fixupimm_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fixupimm_round_pd&expand=5236)
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* [ ] [`_mm512_mask_fixupimm_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fixupimm_round_ps&expand=5236)
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* [x] [`_mm512_mask_fixupimm_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fixupimm_pd&expand=5236)
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* [x] [`_mm512_mask_fixupimm_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fixupimm_ps&expand=5236)
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* [x] [`_mm512_mask_fixupimm_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fixupimm_round_pd&expand=5236)
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* [x] [`_mm512_mask_fixupimm_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fixupimm_round_ps&expand=5236)
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* [x] [`_mm512_mask_fmadd_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmadd_pd&expand=5236)
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* [x] [`_mm512_mask_fmadd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmadd_ps&expand=5236)
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* [x] [`_mm512_mask_fmadd_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fmadd_round_pd&expand=5236)
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@ -541,10 +541,10 @@
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* [x] [`_mm512_mask_min_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_min_ps&expand=5236)
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* [x] [`_mm512_mask_min_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_min_round_pd&expand=5236)
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* [x] [`_mm512_mask_min_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_min_round_ps&expand=5236)
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* [ ] [`_mm512_mask_mov_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mov_epi32&expand=5236)
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* [ ] [`_mm512_mask_mov_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mov_epi64&expand=5236)
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* [ ] [`_mm512_mask_mov_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mov_pd&expand=5236)
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* [ ] [`_mm512_mask_mov_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mov_ps&expand=5236)
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* [x] [`_mm512_mask_mov_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mov_epi32&expand=5236)
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* [x] [`_mm512_mask_mov_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mov_epi64&expand=5236)
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* [x] [`_mm512_mask_mov_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mov_pd&expand=5236)
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* [x] [`_mm512_mask_mov_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_mov_ps&expand=5236)
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* [x] [`_mm512_mask_movedup_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_movedup_pd&expand=5236)
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* [x] [`_mm512_mask_movehdup_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_movehdup_ps&expand=5236)
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* [x] [`_mm512_mask_moveldup_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_moveldup_ps&expand=5236)
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@ -576,29 +576,29 @@
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* [x] [`_mm512_mask_rcp14_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rcp14_pd&expand=5236)
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* [x] [`_mm512_mask_rcp14_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rcp14_ps&expand=5236)
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* [x] [`_mm512_mask_reduce_add_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_add_epi32&expand=5236)
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* [ ] [`_mm512_mask_reduce_add_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_add_epi64&expand=5236)
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* [x] [`_mm512_mask_reduce_add_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_add_epi64&expand=5236)
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* [x] [`_mm512_mask_reduce_add_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_add_pd&expand=5236)
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* [x] [`_mm512_mask_reduce_add_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_add_ps&expand=5236)
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* [x] [`_mm512_mask_reduce_and_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_and_epi32&expand=5236)
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* [ ] [`_mm512_mask_reduce_and_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_and_epi64&expand=5236)
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* [x] [`_mm512_mask_reduce_and_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_and_epi64&expand=5236)
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* [x] [`_mm512_mask_reduce_max_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_max_epi32&expand=5236)
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* [ ] [`_mm512_mask_reduce_max_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_max_epi64&expand=5236)
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* [x] [`_mm512_mask_reduce_max_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_max_epi64&expand=5236)
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* [x] [`_mm512_mask_reduce_max_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_max_epu32&expand=5236)
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* [ ] [`_mm512_mask_reduce_max_epu64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_max_epu64&expand=5236)
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* [x] [`_mm512_mask_reduce_max_epu64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_max_epu64&expand=5236)
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* [x] [`_mm512_mask_reduce_max_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_max_pd&expand=5236)
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* [x] [`_mm512_mask_reduce_max_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_max_ps&expand=5236)
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* [x] [`_mm512_mask_reduce_min_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_min_epi32&expand=5236)
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* [ ] [`_mm512_mask_reduce_min_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_min_epi64&expand=5236)
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* [x] [`_mm512_mask_reduce_min_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_min_epi64&expand=5236)
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* [x] [`_mm512_mask_reduce_min_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_min_epu32&expand=5236)
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* [ ] [`_mm512_mask_reduce_min_epu64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_min_epu64&expand=5236)
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* [x] [`_mm512_mask_reduce_min_epu64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_min_epu64&expand=5236)
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* [x] [`_mm512_mask_reduce_min_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_min_pd&expand=5236)
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* [x] [`_mm512_mask_reduce_min_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_min_ps&expand=5236)
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* [x] [`_mm512_mask_reduce_mul_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_mul_epi32&expand=5236)
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* [ ] [`_mm512_mask_reduce_mul_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_mul_epi64&expand=5236)
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* [x] [`_mm512_mask_reduce_mul_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_mul_epi64&expand=5236)
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* [x] [`_mm512_mask_reduce_mul_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_mul_pd&expand=5236)
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* [x] [`_mm512_mask_reduce_mul_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_mul_ps&expand=5236)
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* [x] [`_mm512_mask_reduce_or_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_or_epi32&expand=5236)
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* [ ] [`_mm512_mask_reduce_or_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_or_epi64&expand=5236)
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* [x] [`_mm512_mask_reduce_or_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_reduce_or_epi64&expand=5236)
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* [x] [`_mm512_mask_rol_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rol_epi32&expand=5236)
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* [x] [`_mm512_mask_rol_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rol_epi64&expand=5236)
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* [x] [`_mm512_mask_rolv_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rolv_epi32&expand=5236)
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@ -607,18 +607,18 @@
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* [x] [`_mm512_mask_ror_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_ror_epi64&expand=5236)
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* [x] [`_mm512_mask_rorv_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rorv_epi32&expand=5236)
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* [x] [`_mm512_mask_rorv_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rorv_epi64&expand=5236)
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* [ ] [`_mm512_mask_roundscale_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_roundscale_pd&expand=5236)
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* [ ] [`_mm512_mask_roundscale_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_roundscale_ps&expand=5236)
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* [ ] [`_mm512_mask_roundscale_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_roundscale_round_pd&expand=5236)
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* [ ] [`_mm512_mask_roundscale_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_roundscale_round_ps&expand=5236)
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* [x] [`_mm512_mask_roundscale_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_roundscale_pd&expand=5236)
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* [x] [`_mm512_mask_roundscale_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_roundscale_ps&expand=5236)
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* [x] [`_mm512_mask_roundscale_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_roundscale_round_pd&expand=5236)
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* [x] [`_mm512_mask_roundscale_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_roundscale_round_ps&expand=5236)
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* [x] [`_mm512_mask_rsqrt14_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rsqrt14_pd&expand=5236)
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* [x] [`_mm512_mask_rsqrt14_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_rsqrt14_ps&expand=5236)
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* [ ] [`_mm512_mask_scalef_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_scalef_pd&expand=5236)
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* [ ] [`_mm512_mask_scalef_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_scalef_ps&expand=5236)
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* [ ] [`_mm512_mask_scalef_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_scalef_round_pd&expand=5236)
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* [ ] [`_mm512_mask_scalef_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_scalef_round_ps&expand=5236)
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* [ ] [`_mm512_mask_set1_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_set1_epi32&expand=5236)
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* [ ] [`_mm512_mask_set1_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_set1_epi64&expand=5236)
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* [x] [`_mm512_mask_scalef_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_scalef_pd&expand=5236)
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* [x] [`_mm512_mask_scalef_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_scalef_ps&expand=5236)
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* [x] [`_mm512_mask_scalef_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_scalef_round_pd&expand=5236)
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* [x] [`_mm512_mask_scalef_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_scalef_round_ps&expand=5236)
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* [x] [`_mm512_mask_set1_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_set1_epi32&expand=5236)
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* [x] [`_mm512_mask_set1_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_set1_epi64&expand=5236)
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* [x] [`_mm512_mask_shuffle_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_shuffle_epi32&expand=5236)
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* [x] [`_mm512_mask_shuffle_f32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_shuffle_f32x4&expand=5236)
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* [x] [`_mm512_mask_shuffle_f64x2`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_shuffle_f64x2&expand=5236)
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|
|
@ -662,12 +662,12 @@
|
|||
* [x] [`_mm512_mask_sub_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sub_ps&expand=5236)
|
||||
* [x] [`_mm512_mask_sub_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sub_round_pd&expand=5236)
|
||||
* [x] [`_mm512_mask_sub_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_sub_round_ps&expand=5236)
|
||||
* [ ] [`_mm512_mask_ternarylogic_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_ternarylogic_epi32&expand=5236)
|
||||
* [ ] [`_mm512_mask_ternarylogic_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_ternarylogic_epi64&expand=5236)
|
||||
* [ ] [`_mm512_mask_test_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_test_epi32_mask&expand=5236)
|
||||
* [ ] [`_mm512_mask_test_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_test_epi64_mask&expand=5236)
|
||||
* [ ] [`_mm512_mask_testn_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_testn_epi32_mask&expand=5236)
|
||||
* [ ] [`_mm512_mask_testn_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_testn_epi64_mask&expand=5236)
|
||||
* [x] [`_mm512_mask_ternarylogic_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_ternarylogic_epi32&expand=5236)
|
||||
* [x] [`_mm512_mask_ternarylogic_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_ternarylogic_epi64&expand=5236)
|
||||
* [x] [`_mm512_mask_test_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_test_epi32_mask&expand=5236)
|
||||
* [x] [`_mm512_mask_test_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_test_epi64_mask&expand=5236)
|
||||
* [x] [`_mm512_mask_testn_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_testn_epi32_mask&expand=5236)
|
||||
* [x] [`_mm512_mask_testn_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_testn_epi64_mask&expand=5236)
|
||||
* [x] [`_mm512_mask_unpackhi_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_unpackhi_epi32&expand=5236)
|
||||
* [x] [`_mm512_mask_unpackhi_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_unpackhi_epi64&expand=5236)
|
||||
* [x] [`_mm512_mask_unpackhi_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_unpackhi_pd&expand=5236)
|
||||
|
|
@ -775,10 +775,10 @@
|
|||
* [x] [`_mm512_maskz_extractf64x4_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_extractf64x4_pd&expand=5236)
|
||||
* [x] [`_mm512_maskz_extracti32x4_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_extracti32x4_epi32&expand=5236)
|
||||
* [x] [`_mm512_maskz_extracti64x4_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_extracti64x4_epi64&expand=5236)
|
||||
* [ ] [`_mm512_maskz_fixupimm_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fixupimm_pd&expand=5236)
|
||||
* [ ] [`_mm512_maskz_fixupimm_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fixupimm_ps&expand=5236)
|
||||
* [ ] [`_mm512_maskz_fixupimm_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fixupimm_round_pd&expand=5236)
|
||||
* [ ] [`_mm512_maskz_fixupimm_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fixupimm_round_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_fixupimm_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fixupimm_pd&expand=5236)
|
||||
* [x] [`_mm512_maskz_fixupimm_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fixupimm_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_fixupimm_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fixupimm_round_pd&expand=5236)
|
||||
* [x] [`_mm512_maskz_fixupimm_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fixupimm_round_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_fmadd_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmadd_pd&expand=5236)
|
||||
* [x] [`_mm512_maskz_fmadd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmadd_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_fmadd_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fmadd_round_pd&expand=5236)
|
||||
|
|
@ -839,10 +839,10 @@
|
|||
* [x] [`_mm512_maskz_min_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_min_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_min_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_min_round_pd&expand=5236)
|
||||
* [x] [`_mm512_maskz_min_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_min_round_ps&expand=5236)
|
||||
* [ ] [`_mm512_maskz_mov_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mov_epi32&expand=5236)
|
||||
* [ ] [`_mm512_maskz_mov_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mov_epi64&expand=5236)
|
||||
* [ ] [`_mm512_maskz_mov_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mov_pd&expand=5236)
|
||||
* [ ] [`_mm512_maskz_mov_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mov_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_mov_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mov_epi32&expand=5236)
|
||||
* [x] [`_mm512_maskz_mov_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mov_epi64&expand=5236)
|
||||
* [x] [`_mm512_maskz_mov_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mov_pd&expand=5236)
|
||||
* [x] [`_mm512_maskz_mov_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_mov_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_movedup_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_movedup_pd&expand=5236)
|
||||
* [x] [`_mm512_maskz_movehdup_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_movehdup_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_moveldup_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_moveldup_ps&expand=5236)
|
||||
|
|
@ -879,18 +879,18 @@
|
|||
* [x] [`_mm512_maskz_ror_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_ror_epi64&expand=5236)
|
||||
* [x] [`_mm512_maskz_rorv_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_rorv_epi32&expand=5236)
|
||||
* [x] [`_mm512_maskz_rorv_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_rorv_epi64&expand=5236)
|
||||
* [ ] [`_mm512_maskz_roundscale_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_roundscale_pd&expand=5236)
|
||||
* [ ] [`_mm512_maskz_roundscale_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_roundscale_ps&expand=5236)
|
||||
* [ ] [`_mm512_maskz_roundscale_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_roundscale_round_pd&expand=5236)
|
||||
* [ ] [`_mm512_maskz_roundscale_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_roundscale_round_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_roundscale_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_roundscale_pd&expand=5236)
|
||||
* [x] [`_mm512_maskz_roundscale_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_roundscale_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_roundscale_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_roundscale_round_pd&expand=5236)
|
||||
* [x] [`_mm512_maskz_roundscale_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_roundscale_round_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_rsqrt14_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_rsqrt14_pd&expand=5236)
|
||||
* [x] [`_mm512_maskz_rsqrt14_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_rsqrt14_ps&expand=5236)
|
||||
* [ ] [`_mm512_maskz_scalef_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_scalef_pd&expand=5236)
|
||||
* [ ] [`_mm512_maskz_scalef_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_scalef_ps&expand=5236)
|
||||
* [ ] [`_mm512_maskz_scalef_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_scalef_round_pd&expand=5236)
|
||||
* [ ] [`_mm512_maskz_scalef_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_scalef_round_ps&expand=5236)
|
||||
* [ ] [`_mm512_maskz_set1_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_set1_epi32&expand=5236)
|
||||
* [ ] [`_mm512_maskz_set1_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_set1_epi64&expand=5236)
|
||||
* [x] [`_mm512_maskz_scalef_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_scalef_pd&expand=5236)
|
||||
* [x] [`_mm512_maskz_scalef_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_scalef_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_scalef_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_scalef_round_pd&expand=5236)
|
||||
* [x] [`_mm512_maskz_scalef_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_scalef_round_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_set1_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_set1_epi32&expand=5236)
|
||||
* [x] [`_mm512_maskz_set1_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_set1_epi64&expand=5236)
|
||||
* [x] [`_mm512_maskz_shuffle_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_shuffle_epi32&expand=5236)
|
||||
* [x] [`_mm512_maskz_shuffle_f32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_shuffle_f32x4&expand=5236)
|
||||
* [x] [`_mm512_maskz_shuffle_f64x2`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_shuffle_f64x2&expand=5236)
|
||||
|
|
@ -926,8 +926,8 @@
|
|||
* [x] [`_mm512_maskz_sub_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sub_ps&expand=5236)
|
||||
* [x] [`_mm512_maskz_sub_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sub_round_pd&expand=5236)
|
||||
* [x] [`_mm512_maskz_sub_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_sub_round_ps&expand=5236)
|
||||
* [ ] [`_mm512_maskz_ternarylogic_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_ternarylogic_epi32&expand=5236)
|
||||
* [ ] [`_mm512_maskz_ternarylogic_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_ternarylogic_epi64&expand=5236)
|
||||
* [x] [`_mm512_maskz_ternarylogic_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_ternarylogic_epi32&expand=5236)
|
||||
* [x] [`_mm512_maskz_ternarylogic_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_ternarylogic_epi64&expand=5236)
|
||||
* [x] [`_mm512_maskz_unpackhi_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_unpackhi_epi32&expand=5236)
|
||||
* [x] [`_mm512_maskz_unpackhi_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_unpackhi_epi64&expand=5236)
|
||||
* [x] [`_mm512_maskz_unpackhi_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_unpackhi_pd&expand=5236)
|
||||
|
|
@ -986,29 +986,29 @@
|
|||
* [x] [`_mm512_rcp14_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rcp14_pd&expand=5236)
|
||||
* [x] [`_mm512_rcp14_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rcp14_ps&expand=5236)
|
||||
* [x] [`_mm512_reduce_add_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_add_epi32&expand=5236)
|
||||
* [ ] [`_mm512_reduce_add_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_add_epi64&expand=5236)
|
||||
* [x] [`_mm512_reduce_add_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_add_epi64&expand=5236)
|
||||
* [x] [`_mm512_reduce_add_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_add_pd&expand=5236)
|
||||
* [x] [`_mm512_reduce_add_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_add_ps&expand=5236)
|
||||
* [x] [`_mm512_reduce_and_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_and_epi32&expand=5236)
|
||||
* [ ] [`_mm512_reduce_and_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_and_epi64&expand=5236)
|
||||
* [x] [`_mm512_reduce_and_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_and_epi64&expand=5236)
|
||||
* [x] [`_mm512_reduce_max_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_max_epi32&expand=5236)
|
||||
* [ ] [`_mm512_reduce_max_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_max_epi64&expand=5236)
|
||||
* [x] [`_mm512_reduce_max_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_max_epi64&expand=5236)
|
||||
* [x] [`_mm512_reduce_max_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_max_epu32&expand=5236)
|
||||
* [ ] [`_mm512_reduce_max_epu64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_max_epu64&expand=5236)
|
||||
* [x] [`_mm512_reduce_max_epu64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_max_epu64&expand=5236)
|
||||
* [x] [`_mm512_reduce_max_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_max_pd&expand=5236)
|
||||
* [x] [`_mm512_reduce_max_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_max_ps&expand=5236)
|
||||
* [x] [`_mm512_reduce_min_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_min_epi32&expand=5236)
|
||||
* [ ] [`_mm512_reduce_min_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_min_epi64&expand=5236)
|
||||
* [x] [`_mm512_reduce_min_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_min_epi64&expand=5236)
|
||||
* [x] [`_mm512_reduce_min_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_min_epu32&expand=5236)
|
||||
* [ ] [`_mm512_reduce_min_epu64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_min_epu64&expand=5236)
|
||||
* [x] [`_mm512_reduce_min_epu64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_min_epu64&expand=5236)
|
||||
* [x] [`_mm512_reduce_min_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_min_pd&expand=5236)
|
||||
* [x] [`_mm512_reduce_min_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_min_ps&expand=5236)
|
||||
* [x] [`_mm512_reduce_mul_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_mul_epi32&expand=5236)
|
||||
* [ ] [`_mm512_reduce_mul_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_mul_epi64&expand=5236)
|
||||
* [x] [`_mm512_reduce_mul_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_mul_epi64&expand=5236)
|
||||
* [x] [`_mm512_reduce_mul_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_mul_pd&expand=5236)
|
||||
* [x] [`_mm512_reduce_mul_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_mul_ps&expand=5236)
|
||||
* [x] [`_mm512_reduce_or_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_or_epi32&expand=5236)
|
||||
* [ ] [`_mm512_reduce_or_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_or_epi64&expand=5236)
|
||||
* [x] [`_mm512_reduce_or_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_reduce_or_epi64&expand=5236)
|
||||
* [x] [`_mm512_rol_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rol_epi32&expand=5236)
|
||||
* [x] [`_mm512_rol_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rol_epi64&expand=5236)
|
||||
* [x] [`_mm512_rolv_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rolv_epi32&expand=5236)
|
||||
|
|
@ -1017,16 +1017,16 @@
|
|||
* [x] [`_mm512_ror_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_ror_epi64&expand=5236)
|
||||
* [x] [`_mm512_rorv_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rorv_epi32&expand=5236)
|
||||
* [x] [`_mm512_rorv_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rorv_epi64&expand=5236)
|
||||
* [ ] [`_mm512_roundscale_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_roundscale_pd&expand=5236)
|
||||
* [ ] [`_mm512_roundscale_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_roundscale_ps&expand=5236)
|
||||
* [ ] [`_mm512_roundscale_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_roundscale_round_pd&expand=5236)
|
||||
* [ ] [`_mm512_roundscale_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_roundscale_round_ps&expand=5236)
|
||||
* [x] [`_mm512_roundscale_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_roundscale_pd&expand=5236)
|
||||
* [x] [`_mm512_roundscale_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_roundscale_ps&expand=5236)
|
||||
* [x] [`_mm512_roundscale_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_roundscale_round_pd&expand=5236)
|
||||
* [x] [`_mm512_roundscale_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_roundscale_round_ps&expand=5236)
|
||||
* [x] [`_mm512_rsqrt14_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rsqrt14_pd&expand=5236)
|
||||
* [x] [`_mm512_rsqrt14_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_rsqrt14_ps&expand=5236)
|
||||
* [ ] [`_mm512_scalef_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_scalef_pd&expand=5236)
|
||||
* [ ] [`_mm512_scalef_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_scalef_ps&expand=5236)
|
||||
* [ ] [`_mm512_scalef_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_scalef_round_pd&expand=5236)
|
||||
* [ ] [`_mm512_scalef_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_scalef_round_ps&expand=5236)
|
||||
* [x] [`_mm512_scalef_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_scalef_pd&expand=5236)
|
||||
* [x] [`_mm512_scalef_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_scalef_ps&expand=5236)
|
||||
* [x] [`_mm512_scalef_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_scalef_round_pd&expand=5236)
|
||||
* [x] [`_mm512_scalef_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_scalef_round_ps&expand=5236)
|
||||
* [x] [`_mm512_set1_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set1_epi16&expand=5236)
|
||||
* [x] [`_mm512_set1_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set1_epi32&expand=5236)
|
||||
* [x] [`_mm512_set1_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set1_epi64&expand=5236)
|
||||
|
|
@ -1096,9 +1096,9 @@
|
|||
* [x] [`_mm512_storeu_epi64`]
|
||||
* [x] [`_mm512_storeu_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_storeu_si512&expand=5236)
|
||||
* [ ] [`_mm512_stream_load_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_stream_load_si512&expand=5236)
|
||||
* [ ] [`_mm512_stream_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_stream_pd&expand=5236)
|
||||
* [ ] [`_mm512_stream_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_stream_ps&expand=5236)
|
||||
* [ ] [`_mm512_stream_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_stream_si512&expand=5236)
|
||||
* [x] [`_mm512_stream_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_stream_pd&expand=5236)
|
||||
* [x] [`_mm512_stream_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_stream_ps&expand=5236)
|
||||
* [x] [`_mm512_stream_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_stream_si512&expand=5236)
|
||||
* [x] [`_mm512_sub_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sub_epi32&expand=5236)
|
||||
* [x] [`_mm512_sub_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sub_epi64&expand=5236)
|
||||
* [x] [`_mm512_sub_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sub_pd&expand=5236)
|
||||
|
|
@ -1106,12 +1106,12 @@
|
|||
* [x] [`_mm512_sub_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sub_round_pd&expand=5236)
|
||||
* [x] [`_mm512_sub_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sub_round_ps&expand=5236)
|
||||
* [ ] [`_mm512_svml_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_svml_round_pd&expand=5236)
|
||||
* [ ] [`_mm512_ternarylogic_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_ternarylogic_epi32&expand=5236)
|
||||
* [ ] [`_mm512_ternarylogic_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_ternarylogic_epi64&expand=5236)
|
||||
* [ ] [`_mm512_test_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_test_epi32_mask&expand=5236)
|
||||
* [ ] [`_mm512_test_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_test_epi64_mask&expand=5236)
|
||||
* [ ] [`_mm512_testn_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_testn_epi32_mask&expand=5236)
|
||||
* [ ] [`_mm512_testn_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_testn_epi64_mask&expand=5236)
|
||||
* [x] [`_mm512_ternarylogic_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_ternarylogic_epi32&expand=5236)
|
||||
* [x] [`_mm512_ternarylogic_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_ternarylogic_epi64&expand=5236)
|
||||
* [x] [`_mm512_test_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_test_epi32_mask&expand=5236)
|
||||
* [x] [`_mm512_test_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_test_epi64_mask&expand=5236)
|
||||
* [x] [`_mm512_testn_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_testn_epi32_mask&expand=5236)
|
||||
* [x] [`_mm512_testn_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_testn_epi64_mask&expand=5236)
|
||||
* [x] [`_mm512_undefined_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_undefined_epi32&expand=5236)
|
||||
* [x] [`_mm512_undefined_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_undefined_pd&expand=5236)
|
||||
* [x] [`_mm512_undefined_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_undefined_ps&expand=5236)
|
||||
|
|
@ -1133,8 +1133,8 @@
|
|||
* [x] [`_mm512_zextps256_ps512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextps256_ps512&expand=5236)
|
||||
* [x] [`_mm512_zextsi128_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextsi128_si512&expand=5236)
|
||||
* [x] [`_mm512_zextsi256_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextsi256_si512&expand=5236)
|
||||
* [ ] [`_mm_add_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_round_sd&expand=5236)
|
||||
* [ ] [`_mm_add_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_round_ss&expand=5236)
|
||||
* [x] [`_mm_add_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_round_sd&expand=5236)
|
||||
* [x] [`_mm_add_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_round_ss&expand=5236)
|
||||
* [x] [`_mm_cmp_round_sd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_round_sd_mask&expand=5236)
|
||||
* [x] [`_mm_cmp_round_ss_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_round_ss_mask&expand=5236)
|
||||
* [x] [`_mm_cmp_sd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_sd_mask&expand=5236)
|
||||
|
|
@ -1200,32 +1200,32 @@
|
|||
* [ ] [`_mm_cvtu32_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtu32_ss&expand=5236)
|
||||
* [ ] [`_mm_cvtu64_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtu64_sd&expand=5236)
|
||||
* [ ] [`_mm_cvtu64_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtu64_ss&expand=5236)
|
||||
* [ ] [`_mm_div_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_div_round_sd&expand=5236)
|
||||
* [ ] [`_mm_div_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_div_round_ss&expand=5236)
|
||||
* [x] [`_mm_div_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_div_round_sd&expand=5236)
|
||||
* [x] [`_mm_div_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_div_round_ss&expand=5236)
|
||||
* [ ] [`_mm_fixupimm_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fixupimm_round_sd&expand=5236)
|
||||
* [ ] [`_mm_fixupimm_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fixupimm_round_ss&expand=5236)
|
||||
* [ ] [`_mm_fixupimm_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fixupimm_sd&expand=5236)
|
||||
* [ ] [`_mm_fixupimm_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fixupimm_ss&expand=5236)
|
||||
* [ ] [`_mm_fmadd_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmadd_round_sd&expand=5236)
|
||||
* [ ] [`_mm_fmadd_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmadd_round_ss&expand=5236)
|
||||
* [x] [`_mm_fmadd_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmadd_round_sd&expand=5236)
|
||||
* [x] [`_mm_fmadd_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmadd_round_ss&expand=5236)
|
||||
* [ ] [`_mm_fmsub_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmsub_round_sd&expand=5236)
|
||||
* [ ] [`_mm_fmsub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fmsub_round_ss&expand=5236)
|
||||
* [ ] [`_mm_fnmadd_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fnmadd_round_sd&expand=5236)
|
||||
* [ ] [`_mm_fnmadd_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fnmadd_round_ss&expand=5236)
|
||||
* [ ] [`_mm_fnmsub_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fnmsub_round_sd&expand=5236)
|
||||
* [ ] [`_mm_fnmsub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fnmsub_round_ss&expand=5236)
|
||||
* [ ] [`_mm_getexp_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getexp_round_sd&expand=5236)
|
||||
* [ ] [`_mm_getexp_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getexp_round_ss&expand=5236)
|
||||
* [ ] [`_mm_getexp_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getexp_sd&expand=5236)
|
||||
* [ ] [`_mm_getexp_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getexp_ss&expand=5236)
|
||||
* [ ] [`_mm_getmant_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getmant_round_sd&expand=5236)
|
||||
* [ ] [`_mm_getmant_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getmant_round_ss&expand=5236)
|
||||
* [ ] [`_mm_getmant_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getmant_sd&expand=5236)
|
||||
* [ ] [`_mm_getmant_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getmant_ss&expand=5236)
|
||||
* [ ] [`_mm_mask3_fmadd_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmadd_round_sd&expand=5236)
|
||||
* [ ] [`_mm_mask3_fmadd_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmadd_round_ss&expand=5236)
|
||||
* [ ] [`_mm_mask3_fmadd_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmadd_sd&expand=5236)
|
||||
* [ ] [`_mm_mask3_fmadd_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmadd_ss&expand=5236)
|
||||
* [x] [`_mm_getexp_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getexp_round_sd&expand=5236)
|
||||
* [x] [`_mm_getexp_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getexp_round_ss&expand=5236)
|
||||
* [x] [`_mm_getexp_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getexp_sd&expand=5236)
|
||||
* [x] [`_mm_getexp_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getexp_ss&expand=5236)
|
||||
* [x] [`_mm_getmant_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getmant_round_sd&expand=5236)
|
||||
* [x] [`_mm_getmant_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getmant_round_ss&expand=5236)
|
||||
* [x] [`_mm_getmant_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getmant_sd&expand=5236)
|
||||
* [x] [`_mm_getmant_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getmant_ss&expand=5236)
|
||||
* [x] [`_mm_mask3_fmadd_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmadd_round_sd&expand=5236)
|
||||
* [x] [`_mm_mask3_fmadd_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmadd_round_ss&expand=5236)
|
||||
* [x] [`_mm_mask3_fmadd_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmadd_sd&expand=5236)
|
||||
* [x] [`_mm_mask3_fmadd_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmadd_ss&expand=5236)
|
||||
* [ ] [`_mm_mask3_fmsub_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmsub_round_sd&expand=5236)
|
||||
* [ ] [`_mm_mask3_fmsub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmsub_round_ss&expand=5236)
|
||||
* [ ] [`_mm_mask3_fmsub_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fmsub_sd&expand=5236)
|
||||
|
|
@ -1238,10 +1238,10 @@
|
|||
* [ ] [`_mm_mask3_fnmsub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fnmsub_round_ss&expand=5236)
|
||||
* [ ] [`_mm_mask3_fnmsub_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fnmsub_sd&expand=5236)
|
||||
* [ ] [`_mm_mask3_fnmsub_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask3_fnmsub_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_add_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_add_round_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_add_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_add_round_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_add_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_add_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_add_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_add_ss&expand=5236)
|
||||
* [x] [`_mm_mask_add_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_add_round_sd&expand=5236)
|
||||
* [x] [`_mm_mask_add_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_add_round_ss&expand=5236)
|
||||
* [x] [`_mm_mask_add_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_add_sd&expand=5236)
|
||||
* [x] [`_mm_mask_add_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_add_ss&expand=5236)
|
||||
* [x] [`_mm_mask_cmp_round_sd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmp_round_sd_mask&expand=5236)
|
||||
* [x] [`_mm_mask_cmp_round_ss_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmp_round_ss_mask&expand=5236)
|
||||
* [x] [`_mm_mask_cmp_sd_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmp_sd_mask&expand=5236)
|
||||
|
|
@ -1250,18 +1250,18 @@
|
|||
* [ ] [`_mm_mask_cvt_roundss_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvt_roundss_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_cvtsd_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtsd_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_cvtss_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtss_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_div_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_div_round_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_div_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_div_round_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_div_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_div_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_div_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_div_ss&expand=5236)
|
||||
* [x] [`_mm_mask_div_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_div_round_sd&expand=5236)
|
||||
* [x] [`_mm_mask_div_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_div_round_ss&expand=5236)
|
||||
* [x] [`_mm_mask_div_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_div_sd&expand=5236)
|
||||
* [x] [`_mm_mask_div_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_div_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_fixupimm_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fixupimm_round_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_fixupimm_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fixupimm_round_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_fixupimm_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fixupimm_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_fixupimm_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fixupimm_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_fmadd_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmadd_round_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_fmadd_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmadd_round_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_fmadd_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmadd_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_fmadd_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmadd_ss&expand=5236)
|
||||
* [x] [`_mm_mask_fmadd_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmadd_round_sd&expand=5236)
|
||||
* [x] [`_mm_mask_fmadd_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmadd_round_ss&expand=5236)
|
||||
* [x] [`_mm_mask_fmadd_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmadd_sd&expand=5236)
|
||||
* [x] [`_mm_mask_fmadd_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmadd_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_fmsub_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmsub_round_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_fmsub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmsub_round_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_fmsub_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fmsub_sd&expand=5236)
|
||||
|
|
@ -1274,72 +1274,72 @@
|
|||
* [ ] [`_mm_mask_fnmsub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fnmsub_round_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_fnmsub_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fnmsub_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_fnmsub_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fnmsub_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_getexp_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getexp_round_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_getexp_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getexp_round_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_getexp_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getexp_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_getexp_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getexp_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_getmant_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getmant_round_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_getmant_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getmant_round_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_getmant_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getmant_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_getmant_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getmant_ss&expand=5236)
|
||||
* [x] [`_mm_mask_getexp_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getexp_round_sd&expand=5236)
|
||||
* [x] [`_mm_mask_getexp_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getexp_round_ss&expand=5236)
|
||||
* [x] [`_mm_mask_getexp_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getexp_sd&expand=5236)
|
||||
* [x] [`_mm_mask_getexp_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getexp_ss&expand=5236)
|
||||
* [x] [`_mm_mask_getmant_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getmant_round_sd&expand=5236)
|
||||
* [x] [`_mm_mask_getmant_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getmant_round_ss&expand=5236)
|
||||
* [x] [`_mm_mask_getmant_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getmant_sd&expand=5236)
|
||||
* [x] [`_mm_mask_getmant_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getmant_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_load_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_load_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_load_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_load_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_max_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_max_round_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_max_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_max_round_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_max_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_max_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_max_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_max_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_min_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_min_round_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_min_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_min_round_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_min_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_min_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_min_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_min_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_move_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_move_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_move_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_move_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_mul_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_mul_round_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_mul_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_mul_round_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_mul_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_mul_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_mul_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_mul_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_rcp14_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_rcp14_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_rcp14_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_rcp14_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_roundscale_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_roundscale_round_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_roundscale_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_roundscale_round_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_roundscale_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_roundscale_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_roundscale_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_roundscale_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_rsqrt14_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_rsqrt14_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_rsqrt14_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_rsqrt14_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_scalef_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_scalef_round_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_scalef_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_scalef_round_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_scalef_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_scalef_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_scalef_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_scalef_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_sqrt_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sqrt_round_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_sqrt_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sqrt_round_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_sqrt_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sqrt_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_sqrt_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sqrt_ss&expand=5236)
|
||||
* [x] [`_mm_mask_max_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_max_round_sd&expand=5236)
|
||||
* [x] [`_mm_mask_max_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_max_round_ss&expand=5236)
|
||||
* [x] [`_mm_mask_max_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_max_sd&expand=5236)
|
||||
* [x] [`_mm_mask_max_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_max_ss&expand=5236)
|
||||
* [x] [`_mm_mask_min_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_min_round_sd&expand=5236)
|
||||
* [x] [`_mm_mask_min_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_min_round_ss&expand=5236)
|
||||
* [x] [`_mm_mask_min_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_min_sd&expand=5236)
|
||||
* [x] [`_mm_mask_min_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_min_ss&expand=5236)
|
||||
* [x] [`_mm_mask_move_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_move_sd&expand=5236)
|
||||
* [x] [`_mm_mask_move_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_move_ss&expand=5236)
|
||||
* [x] [`_mm_mask_mul_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_mul_round_sd&expand=5236)
|
||||
* [x] [`_mm_mask_mul_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_mul_round_ss&expand=5236)
|
||||
* [x] [`_mm_mask_mul_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_mul_sd&expand=5236)
|
||||
* [x] [`_mm_mask_mul_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_mul_ss&expand=5236)
|
||||
* [x] [`_mm_mask_rcp14_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_rcp14_sd&expand=5236)
|
||||
* [x] [`_mm_mask_rcp14_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_rcp14_ss&expand=5236)
|
||||
* [x] [`_mm_mask_roundscale_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_roundscale_round_sd&expand=5236)
|
||||
* [x] [`_mm_mask_roundscale_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_roundscale_round_ss&expand=5236)
|
||||
* [x] [`_mm_mask_roundscale_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_roundscale_sd&expand=5236)
|
||||
* [x] [`_mm_mask_roundscale_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_roundscale_ss&expand=5236)
|
||||
* [x] [`_mm_mask_rsqrt14_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_rsqrt14_sd&expand=5236)
|
||||
* [x] [`_mm_mask_rsqrt14_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_rsqrt14_ss&expand=5236)
|
||||
* [x] [`_mm_mask_scalef_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_scalef_round_sd&expand=5236)
|
||||
* [x] [`_mm_mask_scalef_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_scalef_round_ss&expand=5236)
|
||||
* [x] [`_mm_mask_scalef_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_scalef_sd&expand=5236)
|
||||
* [x] [`_mm_mask_scalef_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_scalef_ss&expand=5236)
|
||||
* [x] [`_mm_mask_sqrt_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sqrt_round_sd&expand=5236)
|
||||
* [x] [`_mm_mask_sqrt_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sqrt_round_ss&expand=5236)
|
||||
* [x] [`_mm_mask_sqrt_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sqrt_sd&expand=5236)
|
||||
* [x] [`_mm_mask_sqrt_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sqrt_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_store_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_store_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_store_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_store_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_sub_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sub_round_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_sub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sub_round_ss&expand=5236)
|
||||
* [ ] [`_mm_mask_sub_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sub_sd&expand=5236)
|
||||
* [ ] [`_mm_mask_sub_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sub_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_add_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_add_round_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_add_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_add_round_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_add_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_add_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_add_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_add_ss&expand=5236)
|
||||
* [x] [`_mm_mask_sub_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sub_round_sd&expand=5236)
|
||||
* [x] [`_mm_mask_sub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sub_round_ss&expand=5236)
|
||||
* [x] [`_mm_mask_sub_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sub_sd&expand=5236)
|
||||
* [x] [`_mm_mask_sub_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_sub_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_add_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_add_round_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_add_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_add_round_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_add_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_add_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_add_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_add_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_cvt_roundsd_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvt_roundsd_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_cvt_roundss_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvt_roundss_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_cvtsd_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtsd_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_cvtss_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtss_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_div_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_div_round_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_div_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_div_round_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_div_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_div_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_div_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_div_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_div_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_div_round_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_div_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_div_round_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_div_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_div_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_div_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_div_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_fixupimm_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fixupimm_round_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_fixupimm_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fixupimm_round_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_fixupimm_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fixupimm_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_fixupimm_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fixupimm_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_fmadd_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmadd_round_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_fmadd_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmadd_round_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_fmadd_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmadd_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_fmadd_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmadd_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_fmadd_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmadd_round_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_fmadd_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmadd_round_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_fmadd_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmadd_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_fmadd_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmadd_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_fmsub_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmsub_round_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_fmsub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmsub_round_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_fmsub_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fmsub_sd&expand=5236)
|
||||
|
|
@ -1352,71 +1352,71 @@
|
|||
* [ ] [`_mm_maskz_fnmsub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fnmsub_round_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_fnmsub_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fnmsub_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_fnmsub_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_fnmsub_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_getexp_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getexp_round_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_getexp_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getexp_round_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_getexp_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getexp_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_getexp_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getexp_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_getmant_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getmant_round_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_getmant_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getmant_round_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_getmant_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getmant_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_getmant_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getmant_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_getexp_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getexp_round_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_getexp_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getexp_round_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_getexp_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getexp_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_getexp_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getexp_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_getmant_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getmant_round_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_getmant_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getmant_round_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_getmant_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getmant_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_getmant_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getmant_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_load_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_load_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_load_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_load_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_max_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_max_round_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_max_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_max_round_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_max_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_max_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_max_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_max_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_min_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_min_round_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_min_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_min_round_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_min_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_min_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_min_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_min_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_move_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_move_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_move_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_move_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_mul_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_mul_round_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_mul_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_mul_round_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_mul_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_mul_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_mul_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_mul_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_rcp14_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_rcp14_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_rcp14_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_rcp14_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_roundscale_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_roundscale_round_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_roundscale_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_roundscale_round_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_roundscale_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_roundscale_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_roundscale_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_roundscale_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_rsqrt14_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_rsqrt14_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_rsqrt14_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_rsqrt14_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_scalef_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_scalef_round_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_scalef_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_scalef_round_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_scalef_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_scalef_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_scalef_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_scalef_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_sqrt_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sqrt_round_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_sqrt_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sqrt_round_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_sqrt_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sqrt_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_sqrt_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sqrt_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_sub_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sub_round_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_sub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sub_round_ss&expand=5236)
|
||||
* [ ] [`_mm_maskz_sub_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sub_sd&expand=5236)
|
||||
* [ ] [`_mm_maskz_sub_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sub_ss&expand=5236)
|
||||
* [ ] [`_mm_max_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_round_sd&expand=5236)
|
||||
* [ ] [`_mm_max_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_round_ss&expand=5236)
|
||||
* [ ] [`_mm_min_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_round_sd&expand=5236)
|
||||
* [ ] [`_mm_min_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_round_ss&expand=5236)
|
||||
* [ ] [`_mm_mul_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mul_round_sd&expand=5236)
|
||||
* [ ] [`_mm_mul_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mul_round_ss&expand=5236)
|
||||
* [ ] [`_mm_rcp14_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_rcp14_sd&expand=5236)
|
||||
* [ ] [`_mm_rcp14_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_rcp14_ss&expand=5236)
|
||||
* [ ] [`_mm_roundscale_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_roundscale_round_sd&expand=5236)
|
||||
* [ ] [`_mm_roundscale_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_roundscale_round_ss&expand=5236)
|
||||
* [ ] [`_mm_roundscale_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_roundscale_sd&expand=5236)
|
||||
* [ ] [`_mm_roundscale_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_roundscale_ss&expand=5236)
|
||||
* [ ] [`_mm_rsqrt14_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_rsqrt14_sd&expand=5236)
|
||||
* [ ] [`_mm_rsqrt14_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_rsqrt14_ss&expand=5236)
|
||||
* [ ] [`_mm_scalef_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_scalef_round_sd&expand=5236)
|
||||
* [ ] [`_mm_scalef_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_scalef_round_ss&expand=5236)
|
||||
* [ ] [`_mm_scalef_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_scalef_sd&expand=5236)
|
||||
* [ ] [`_mm_scalef_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_scalef_ss&expand=5236)
|
||||
* [ ] [`_mm_sqrt_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sqrt_round_sd&expand=5236)
|
||||
* [ ] [`_mm_sqrt_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sqrt_round_ss&expand=5236)
|
||||
* [ ] [`_mm_sub_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_round_sd&expand=5236)
|
||||
* [ ] [`_mm_sub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_round_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_max_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_max_round_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_max_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_max_round_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_max_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_max_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_max_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_max_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_min_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_min_round_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_min_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_min_round_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_min_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_min_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_min_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_min_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_move_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_move_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_move_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_move_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_mul_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_mul_round_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_mul_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_mul_round_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_mul_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_mul_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_mul_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_mul_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_rcp14_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_rcp14_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_rcp14_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_rcp14_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_roundscale_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_roundscale_round_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_roundscale_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_roundscale_round_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_roundscale_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_roundscale_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_roundscale_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_roundscale_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_rsqrt14_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_rsqrt14_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_rsqrt14_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_rsqrt14_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_scalef_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_scalef_round_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_scalef_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_scalef_round_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_scalef_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_scalef_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_scalef_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_scalef_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_sqrt_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sqrt_round_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_sqrt_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sqrt_round_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_sqrt_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sqrt_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_sqrt_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sqrt_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_sub_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sub_round_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_sub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sub_round_ss&expand=5236)
|
||||
* [x] [`_mm_maskz_sub_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sub_sd&expand=5236)
|
||||
* [x] [`_mm_maskz_sub_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_sub_ss&expand=5236)
|
||||
* [x] [`_mm_max_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_round_sd&expand=5236)
|
||||
* [x] [`_mm_max_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_round_ss&expand=5236)
|
||||
* [x] [`_mm_min_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_round_sd&expand=5236)
|
||||
* [x] [`_mm_min_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_round_ss&expand=5236)
|
||||
* [x] [`_mm_mul_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mul_round_sd&expand=5236)
|
||||
* [x] [`_mm_mul_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mul_round_ss&expand=5236)
|
||||
* [x] [`_mm_rcp14_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_rcp14_sd&expand=5236)
|
||||
* [x] [`_mm_rcp14_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_rcp14_ss&expand=5236)
|
||||
* [x] [`_mm_roundscale_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_roundscale_round_sd&expand=5236)
|
||||
* [x] [`_mm_roundscale_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_roundscale_round_ss&expand=5236)
|
||||
* [x] [`_mm_roundscale_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_roundscale_sd&expand=5236)
|
||||
* [x] [`_mm_roundscale_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_roundscale_ss&expand=5236)
|
||||
* [x] [`_mm_rsqrt14_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_rsqrt14_sd&expand=5236)
|
||||
* [x] [`_mm_rsqrt14_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_rsqrt14_ss&expand=5236)
|
||||
* [x] [`_mm_scalef_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_scalef_round_sd&expand=5236)
|
||||
* [x] [`_mm_scalef_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_scalef_round_ss&expand=5236)
|
||||
* [x] [`_mm_scalef_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_scalef_sd&expand=5236)
|
||||
* [x] [`_mm_scalef_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_scalef_ss&expand=5236)
|
||||
* [x] [`_mm_sqrt_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sqrt_round_sd&expand=5236)
|
||||
* [x] [`_mm_sqrt_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sqrt_round_ss&expand=5236)
|
||||
* [x] [`_mm_sub_round_sd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_round_sd&expand=5236)
|
||||
* [x] [`_mm_sub_round_ss`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_round_ss&expand=5236)
|
||||
|
||||
</p>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -733,6 +733,530 @@ macro_rules! constify_imm8_sae {
|
|||
};
|
||||
}
|
||||
|
||||
// Two sae parameters.
|
||||
// This macro enforces that.
|
||||
#[allow(unused)]
|
||||
macro_rules! constify_imm8_roundscale {
|
||||
($imm8:expr, $imm4:expr, $expand:ident) => {
|
||||
#[allow(overflowing_literals)]
|
||||
match ($imm8 & 0b11111111, $imm4) {
|
||||
(0, 4) => $expand!(0, 4),
|
||||
(0, 8) => $expand!(0, 8),
|
||||
(1, 4) => $expand!(1, 4),
|
||||
(1, 8) => $expand!(1, 8),
|
||||
(2, 4) => $expand!(2, 4),
|
||||
(2, 8) => $expand!(2, 8),
|
||||
(3, 4) => $expand!(3, 4),
|
||||
(3, 8) => $expand!(3, 8),
|
||||
(4, 4) => $expand!(4, 4),
|
||||
(4, 8) => $expand!(4, 8),
|
||||
(5, 4) => $expand!(5, 4),
|
||||
(5, 8) => $expand!(5, 8),
|
||||
(6, 4) => $expand!(6, 4),
|
||||
(6, 8) => $expand!(6, 8),
|
||||
(7, 4) => $expand!(7, 4),
|
||||
(7, 8) => $expand!(7, 8),
|
||||
(8, 4) => $expand!(8, 4),
|
||||
(8, 8) => $expand!(8, 8),
|
||||
(9, 4) => $expand!(9, 4),
|
||||
(9, 8) => $expand!(9, 8),
|
||||
(10, 4) => $expand!(10, 4),
|
||||
(10, 8) => $expand!(10, 8),
|
||||
(11, 4) => $expand!(11, 4),
|
||||
(11, 8) => $expand!(11, 8),
|
||||
(12, 4) => $expand!(12, 4),
|
||||
(12, 8) => $expand!(12, 8),
|
||||
(13, 4) => $expand!(13, 4),
|
||||
(13, 8) => $expand!(13, 8),
|
||||
(14, 4) => $expand!(14, 4),
|
||||
(14, 8) => $expand!(14, 8),
|
||||
(15, 4) => $expand!(15, 4),
|
||||
(15, 8) => $expand!(15, 8),
|
||||
(16, 4) => $expand!(16, 4),
|
||||
(16, 8) => $expand!(16, 8),
|
||||
(17, 4) => $expand!(17, 4),
|
||||
(17, 8) => $expand!(17, 8),
|
||||
(18, 4) => $expand!(18, 4),
|
||||
(18, 8) => $expand!(18, 8),
|
||||
(19, 4) => $expand!(19, 4),
|
||||
(19, 8) => $expand!(19, 8),
|
||||
(20, 4) => $expand!(20, 4),
|
||||
(20, 8) => $expand!(20, 8),
|
||||
(21, 4) => $expand!(21, 4),
|
||||
(21, 8) => $expand!(21, 8),
|
||||
(22, 4) => $expand!(22, 4),
|
||||
(22, 8) => $expand!(22, 8),
|
||||
(23, 4) => $expand!(23, 4),
|
||||
(23, 8) => $expand!(23, 8),
|
||||
(24, 4) => $expand!(24, 4),
|
||||
(24, 8) => $expand!(24, 8),
|
||||
(25, 4) => $expand!(25, 4),
|
||||
(25, 8) => $expand!(25, 8),
|
||||
(26, 4) => $expand!(26, 4),
|
||||
(26, 8) => $expand!(26, 8),
|
||||
(27, 4) => $expand!(27, 4),
|
||||
(27, 8) => $expand!(27, 8),
|
||||
(28, 4) => $expand!(28, 4),
|
||||
(28, 8) => $expand!(28, 8),
|
||||
(29, 4) => $expand!(29, 4),
|
||||
(29, 8) => $expand!(29, 8),
|
||||
(30, 4) => $expand!(30, 4),
|
||||
(30, 8) => $expand!(30, 8),
|
||||
(31, 4) => $expand!(31, 4),
|
||||
(31, 8) => $expand!(31, 8),
|
||||
(32, 4) => $expand!(32, 4),
|
||||
(32, 8) => $expand!(32, 8),
|
||||
(33, 4) => $expand!(33, 4),
|
||||
(33, 8) => $expand!(33, 8),
|
||||
(34, 4) => $expand!(34, 4),
|
||||
(34, 8) => $expand!(34, 8),
|
||||
(35, 4) => $expand!(35, 4),
|
||||
(35, 8) => $expand!(35, 8),
|
||||
(36, 4) => $expand!(36, 4),
|
||||
(36, 8) => $expand!(36, 8),
|
||||
(37, 4) => $expand!(37, 4),
|
||||
(37, 8) => $expand!(37, 8),
|
||||
(38, 4) => $expand!(38, 4),
|
||||
(38, 8) => $expand!(38, 8),
|
||||
(39, 4) => $expand!(39, 4),
|
||||
(39, 8) => $expand!(39, 8),
|
||||
(40, 4) => $expand!(40, 4),
|
||||
(40, 8) => $expand!(40, 8),
|
||||
(41, 4) => $expand!(41, 4),
|
||||
(41, 8) => $expand!(41, 8),
|
||||
(42, 4) => $expand!(42, 4),
|
||||
(42, 8) => $expand!(42, 8),
|
||||
(43, 4) => $expand!(43, 4),
|
||||
(43, 8) => $expand!(43, 8),
|
||||
(44, 4) => $expand!(44, 4),
|
||||
(44, 8) => $expand!(44, 8),
|
||||
(45, 4) => $expand!(45, 4),
|
||||
(45, 8) => $expand!(45, 8),
|
||||
(46, 4) => $expand!(46, 4),
|
||||
(46, 8) => $expand!(46, 8),
|
||||
(47, 4) => $expand!(47, 4),
|
||||
(47, 8) => $expand!(47, 8),
|
||||
(48, 4) => $expand!(48, 4),
|
||||
(48, 8) => $expand!(48, 8),
|
||||
(49, 4) => $expand!(49, 4),
|
||||
(49, 8) => $expand!(49, 8),
|
||||
(50, 4) => $expand!(50, 4),
|
||||
(50, 8) => $expand!(50, 8),
|
||||
(51, 4) => $expand!(51, 4),
|
||||
(51, 8) => $expand!(51, 8),
|
||||
(52, 4) => $expand!(52, 4),
|
||||
(52, 8) => $expand!(52, 8),
|
||||
(53, 4) => $expand!(53, 4),
|
||||
(53, 8) => $expand!(53, 8),
|
||||
(54, 4) => $expand!(54, 4),
|
||||
(54, 8) => $expand!(54, 8),
|
||||
(55, 4) => $expand!(55, 4),
|
||||
(55, 8) => $expand!(55, 8),
|
||||
(56, 4) => $expand!(56, 4),
|
||||
(56, 8) => $expand!(56, 8),
|
||||
(57, 4) => $expand!(57, 4),
|
||||
(57, 8) => $expand!(57, 8),
|
||||
(58, 4) => $expand!(58, 4),
|
||||
(58, 8) => $expand!(58, 8),
|
||||
(59, 4) => $expand!(59, 4),
|
||||
(59, 8) => $expand!(59, 8),
|
||||
(60, 4) => $expand!(60, 4),
|
||||
(60, 8) => $expand!(60, 8),
|
||||
(61, 4) => $expand!(61, 4),
|
||||
(61, 8) => $expand!(61, 8),
|
||||
(62, 4) => $expand!(62, 4),
|
||||
(62, 8) => $expand!(62, 8),
|
||||
(63, 4) => $expand!(63, 4),
|
||||
(63, 8) => $expand!(63, 8),
|
||||
(64, 4) => $expand!(64, 4),
|
||||
(64, 8) => $expand!(64, 8),
|
||||
(65, 4) => $expand!(65, 4),
|
||||
(65, 8) => $expand!(65, 8),
|
||||
(66, 4) => $expand!(66, 4),
|
||||
(66, 8) => $expand!(66, 8),
|
||||
(67, 4) => $expand!(67, 4),
|
||||
(67, 8) => $expand!(67, 8),
|
||||
(68, 4) => $expand!(68, 4),
|
||||
(68, 8) => $expand!(68, 8),
|
||||
(69, 4) => $expand!(69, 4),
|
||||
(69, 8) => $expand!(69, 8),
|
||||
(70, 4) => $expand!(70, 4),
|
||||
(70, 8) => $expand!(70, 8),
|
||||
(71, 4) => $expand!(71, 4),
|
||||
(71, 8) => $expand!(71, 8),
|
||||
(72, 4) => $expand!(72, 4),
|
||||
(72, 8) => $expand!(72, 8),
|
||||
(73, 4) => $expand!(73, 4),
|
||||
(73, 8) => $expand!(73, 8),
|
||||
(74, 4) => $expand!(74, 4),
|
||||
(74, 8) => $expand!(74, 8),
|
||||
(75, 4) => $expand!(75, 4),
|
||||
(75, 8) => $expand!(75, 8),
|
||||
(76, 4) => $expand!(76, 4),
|
||||
(76, 8) => $expand!(76, 8),
|
||||
(77, 4) => $expand!(77, 4),
|
||||
(77, 8) => $expand!(77, 8),
|
||||
(78, 4) => $expand!(78, 4),
|
||||
(78, 8) => $expand!(78, 8),
|
||||
(79, 4) => $expand!(79, 4),
|
||||
(79, 8) => $expand!(79, 8),
|
||||
(80, 4) => $expand!(80, 4),
|
||||
(80, 8) => $expand!(80, 8),
|
||||
(81, 4) => $expand!(81, 4),
|
||||
(81, 8) => $expand!(81, 8),
|
||||
(82, 4) => $expand!(82, 4),
|
||||
(82, 8) => $expand!(82, 8),
|
||||
(83, 4) => $expand!(83, 4),
|
||||
(83, 8) => $expand!(83, 8),
|
||||
(84, 4) => $expand!(84, 4),
|
||||
(84, 8) => $expand!(84, 8),
|
||||
(85, 4) => $expand!(85, 4),
|
||||
(85, 8) => $expand!(85, 8),
|
||||
(86, 4) => $expand!(86, 4),
|
||||
(86, 8) => $expand!(86, 8),
|
||||
(87, 4) => $expand!(87, 4),
|
||||
(87, 8) => $expand!(87, 8),
|
||||
(88, 4) => $expand!(88, 4),
|
||||
(88, 8) => $expand!(88, 8),
|
||||
(89, 4) => $expand!(89, 4),
|
||||
(89, 8) => $expand!(89, 8),
|
||||
(90, 4) => $expand!(90, 4),
|
||||
(90, 8) => $expand!(90, 8),
|
||||
(91, 4) => $expand!(91, 4),
|
||||
(91, 8) => $expand!(91, 8),
|
||||
(92, 4) => $expand!(92, 4),
|
||||
(92, 8) => $expand!(92, 8),
|
||||
(93, 4) => $expand!(93, 4),
|
||||
(93, 8) => $expand!(93, 8),
|
||||
(94, 4) => $expand!(94, 4),
|
||||
(94, 8) => $expand!(94, 8),
|
||||
(95, 4) => $expand!(95, 4),
|
||||
(95, 8) => $expand!(95, 8),
|
||||
(96, 4) => $expand!(96, 4),
|
||||
(96, 8) => $expand!(96, 8),
|
||||
(97, 4) => $expand!(97, 4),
|
||||
(97, 8) => $expand!(97, 8),
|
||||
(98, 4) => $expand!(98, 4),
|
||||
(98, 8) => $expand!(98, 8),
|
||||
(99, 4) => $expand!(99, 4),
|
||||
(99, 8) => $expand!(99, 8),
|
||||
(100, 4) => $expand!(100, 4),
|
||||
(100, 8) => $expand!(100, 8),
|
||||
(101, 4) => $expand!(101, 4),
|
||||
(101, 8) => $expand!(101, 8),
|
||||
(102, 4) => $expand!(102, 4),
|
||||
(102, 8) => $expand!(102, 8),
|
||||
(103, 4) => $expand!(103, 4),
|
||||
(103, 8) => $expand!(103, 8),
|
||||
(104, 4) => $expand!(104, 4),
|
||||
(104, 8) => $expand!(104, 8),
|
||||
(105, 4) => $expand!(105, 4),
|
||||
(105, 8) => $expand!(105, 8),
|
||||
(106, 4) => $expand!(106, 4),
|
||||
(106, 8) => $expand!(106, 8),
|
||||
(107, 4) => $expand!(107, 4),
|
||||
(107, 8) => $expand!(107, 8),
|
||||
(108, 4) => $expand!(108, 4),
|
||||
(108, 8) => $expand!(108, 8),
|
||||
(109, 4) => $expand!(109, 4),
|
||||
(109, 8) => $expand!(109, 8),
|
||||
(110, 4) => $expand!(110, 4),
|
||||
(110, 8) => $expand!(110, 8),
|
||||
(111, 4) => $expand!(111, 4),
|
||||
(111, 8) => $expand!(111, 8),
|
||||
(112, 4) => $expand!(112, 4),
|
||||
(112, 8) => $expand!(112, 8),
|
||||
(113, 4) => $expand!(113, 4),
|
||||
(113, 8) => $expand!(113, 8),
|
||||
(114, 4) => $expand!(114, 4),
|
||||
(114, 8) => $expand!(114, 8),
|
||||
(115, 4) => $expand!(115, 4),
|
||||
(115, 8) => $expand!(115, 8),
|
||||
(116, 4) => $expand!(116, 4),
|
||||
(116, 8) => $expand!(116, 8),
|
||||
(117, 4) => $expand!(117, 4),
|
||||
(117, 8) => $expand!(117, 8),
|
||||
(118, 4) => $expand!(118, 4),
|
||||
(118, 8) => $expand!(118, 8),
|
||||
(119, 4) => $expand!(119, 4),
|
||||
(119, 8) => $expand!(119, 8),
|
||||
(120, 4) => $expand!(120, 4),
|
||||
(120, 8) => $expand!(120, 8),
|
||||
(121, 4) => $expand!(121, 4),
|
||||
(121, 8) => $expand!(121, 8),
|
||||
(122, 4) => $expand!(122, 4),
|
||||
(122, 8) => $expand!(122, 8),
|
||||
(123, 4) => $expand!(123, 4),
|
||||
(123, 8) => $expand!(123, 8),
|
||||
(124, 4) => $expand!(124, 4),
|
||||
(124, 8) => $expand!(124, 8),
|
||||
(125, 4) => $expand!(125, 4),
|
||||
(125, 8) => $expand!(125, 8),
|
||||
(126, 4) => $expand!(126, 4),
|
||||
(126, 8) => $expand!(126, 8),
|
||||
(127, 4) => $expand!(127, 4),
|
||||
(127, 8) => $expand!(127, 8),
|
||||
(128, 4) => $expand!(128, 4),
|
||||
(128, 8) => $expand!(128, 8),
|
||||
(129, 4) => $expand!(129, 4),
|
||||
(129, 8) => $expand!(129, 8),
|
||||
(130, 4) => $expand!(130, 4),
|
||||
(130, 8) => $expand!(130, 8),
|
||||
(131, 4) => $expand!(131, 4),
|
||||
(131, 8) => $expand!(131, 8),
|
||||
(132, 4) => $expand!(132, 4),
|
||||
(132, 8) => $expand!(132, 8),
|
||||
(133, 4) => $expand!(133, 4),
|
||||
(133, 8) => $expand!(133, 8),
|
||||
(134, 4) => $expand!(134, 4),
|
||||
(134, 8) => $expand!(134, 8),
|
||||
(135, 4) => $expand!(135, 4),
|
||||
(135, 8) => $expand!(135, 8),
|
||||
(136, 4) => $expand!(136, 4),
|
||||
(136, 8) => $expand!(136, 8),
|
||||
(137, 4) => $expand!(137, 4),
|
||||
(137, 8) => $expand!(137, 8),
|
||||
(138, 4) => $expand!(138, 4),
|
||||
(138, 8) => $expand!(138, 8),
|
||||
(139, 4) => $expand!(139, 4),
|
||||
(139, 8) => $expand!(139, 8),
|
||||
(140, 4) => $expand!(140, 4),
|
||||
(140, 8) => $expand!(140, 8),
|
||||
(141, 4) => $expand!(141, 4),
|
||||
(141, 8) => $expand!(141, 8),
|
||||
(142, 4) => $expand!(142, 4),
|
||||
(142, 8) => $expand!(142, 8),
|
||||
(143, 4) => $expand!(143, 4),
|
||||
(143, 8) => $expand!(143, 8),
|
||||
(144, 4) => $expand!(144, 4),
|
||||
(144, 8) => $expand!(144, 8),
|
||||
(145, 4) => $expand!(145, 4),
|
||||
(145, 8) => $expand!(145, 8),
|
||||
(146, 4) => $expand!(146, 4),
|
||||
(146, 8) => $expand!(146, 8),
|
||||
(147, 4) => $expand!(147, 4),
|
||||
(147, 8) => $expand!(147, 8),
|
||||
(148, 4) => $expand!(148, 4),
|
||||
(148, 8) => $expand!(148, 8),
|
||||
(149, 4) => $expand!(149, 4),
|
||||
(149, 8) => $expand!(149, 8),
|
||||
(150, 4) => $expand!(150, 4),
|
||||
(150, 8) => $expand!(150, 8),
|
||||
(151, 4) => $expand!(151, 4),
|
||||
(151, 8) => $expand!(151, 8),
|
||||
(152, 4) => $expand!(152, 4),
|
||||
(152, 8) => $expand!(152, 8),
|
||||
(153, 4) => $expand!(153, 4),
|
||||
(153, 8) => $expand!(153, 8),
|
||||
(154, 4) => $expand!(154, 4),
|
||||
(154, 8) => $expand!(154, 8),
|
||||
(155, 4) => $expand!(155, 4),
|
||||
(155, 8) => $expand!(155, 8),
|
||||
(156, 4) => $expand!(156, 4),
|
||||
(156, 8) => $expand!(156, 8),
|
||||
(157, 4) => $expand!(157, 4),
|
||||
(157, 8) => $expand!(157, 8),
|
||||
(158, 4) => $expand!(158, 4),
|
||||
(158, 8) => $expand!(158, 8),
|
||||
(159, 4) => $expand!(159, 4),
|
||||
(159, 8) => $expand!(159, 8),
|
||||
(160, 4) => $expand!(160, 4),
|
||||
(160, 8) => $expand!(160, 8),
|
||||
(161, 4) => $expand!(161, 4),
|
||||
(161, 8) => $expand!(161, 8),
|
||||
(162, 4) => $expand!(162, 4),
|
||||
(162, 8) => $expand!(162, 8),
|
||||
(163, 4) => $expand!(163, 4),
|
||||
(163, 8) => $expand!(163, 8),
|
||||
(164, 4) => $expand!(164, 4),
|
||||
(164, 8) => $expand!(164, 8),
|
||||
(165, 4) => $expand!(165, 4),
|
||||
(165, 8) => $expand!(165, 8),
|
||||
(166, 4) => $expand!(166, 4),
|
||||
(166, 8) => $expand!(166, 8),
|
||||
(167, 4) => $expand!(167, 4),
|
||||
(167, 8) => $expand!(167, 8),
|
||||
(168, 4) => $expand!(168, 4),
|
||||
(168, 8) => $expand!(168, 8),
|
||||
(169, 4) => $expand!(169, 4),
|
||||
(169, 8) => $expand!(169, 8),
|
||||
(170, 4) => $expand!(170, 4),
|
||||
(170, 8) => $expand!(170, 8),
|
||||
(171, 4) => $expand!(171, 4),
|
||||
(171, 8) => $expand!(171, 8),
|
||||
(172, 4) => $expand!(172, 4),
|
||||
(172, 8) => $expand!(172, 8),
|
||||
(173, 4) => $expand!(173, 4),
|
||||
(173, 8) => $expand!(173, 8),
|
||||
(174, 4) => $expand!(174, 4),
|
||||
(174, 8) => $expand!(174, 8),
|
||||
(175, 4) => $expand!(175, 4),
|
||||
(175, 8) => $expand!(175, 8),
|
||||
(176, 4) => $expand!(176, 4),
|
||||
(176, 8) => $expand!(176, 8),
|
||||
(177, 4) => $expand!(177, 4),
|
||||
(177, 8) => $expand!(177, 8),
|
||||
(178, 4) => $expand!(178, 4),
|
||||
(178, 8) => $expand!(178, 8),
|
||||
(179, 4) => $expand!(179, 4),
|
||||
(179, 8) => $expand!(179, 8),
|
||||
(180, 4) => $expand!(180, 4),
|
||||
(180, 8) => $expand!(180, 8),
|
||||
(181, 4) => $expand!(181, 4),
|
||||
(181, 8) => $expand!(181, 8),
|
||||
(182, 4) => $expand!(182, 4),
|
||||
(182, 8) => $expand!(182, 8),
|
||||
(183, 4) => $expand!(183, 4),
|
||||
(183, 8) => $expand!(183, 8),
|
||||
(184, 4) => $expand!(184, 4),
|
||||
(184, 8) => $expand!(184, 8),
|
||||
(185, 4) => $expand!(185, 4),
|
||||
(185, 8) => $expand!(185, 8),
|
||||
(186, 4) => $expand!(186, 4),
|
||||
(186, 8) => $expand!(186, 8),
|
||||
(187, 4) => $expand!(187, 4),
|
||||
(187, 8) => $expand!(187, 8),
|
||||
(188, 4) => $expand!(188, 4),
|
||||
(188, 8) => $expand!(188, 8),
|
||||
(189, 4) => $expand!(189, 4),
|
||||
(189, 8) => $expand!(189, 8),
|
||||
(190, 4) => $expand!(190, 4),
|
||||
(190, 8) => $expand!(190, 8),
|
||||
(191, 4) => $expand!(191, 4),
|
||||
(191, 8) => $expand!(191, 8),
|
||||
(192, 4) => $expand!(192, 4),
|
||||
(192, 8) => $expand!(192, 8),
|
||||
(193, 4) => $expand!(193, 4),
|
||||
(193, 8) => $expand!(193, 8),
|
||||
(194, 4) => $expand!(194, 4),
|
||||
(194, 8) => $expand!(194, 8),
|
||||
(195, 4) => $expand!(195, 4),
|
||||
(195, 8) => $expand!(195, 8),
|
||||
(196, 4) => $expand!(196, 4),
|
||||
(196, 8) => $expand!(196, 8),
|
||||
(197, 4) => $expand!(197, 4),
|
||||
(197, 8) => $expand!(197, 8),
|
||||
(198, 4) => $expand!(198, 4),
|
||||
(198, 8) => $expand!(198, 8),
|
||||
(199, 4) => $expand!(199, 4),
|
||||
(199, 8) => $expand!(199, 8),
|
||||
(200, 4) => $expand!(200, 4),
|
||||
(200, 8) => $expand!(200, 8),
|
||||
(201, 4) => $expand!(201, 4),
|
||||
(201, 8) => $expand!(201, 8),
|
||||
(202, 4) => $expand!(202, 4),
|
||||
(202, 8) => $expand!(202, 8),
|
||||
(203, 4) => $expand!(203, 4),
|
||||
(203, 8) => $expand!(203, 8),
|
||||
(204, 4) => $expand!(204, 4),
|
||||
(204, 8) => $expand!(204, 8),
|
||||
(205, 4) => $expand!(205, 4),
|
||||
(205, 8) => $expand!(205, 8),
|
||||
(206, 4) => $expand!(206, 4),
|
||||
(206, 8) => $expand!(206, 8),
|
||||
(207, 4) => $expand!(207, 4),
|
||||
(207, 8) => $expand!(207, 8),
|
||||
(208, 4) => $expand!(208, 4),
|
||||
(208, 8) => $expand!(208, 8),
|
||||
(209, 4) => $expand!(209, 4),
|
||||
(209, 8) => $expand!(209, 8),
|
||||
(210, 4) => $expand!(210, 4),
|
||||
(210, 8) => $expand!(210, 8),
|
||||
(211, 4) => $expand!(211, 4),
|
||||
(211, 8) => $expand!(211, 8),
|
||||
(212, 4) => $expand!(212, 4),
|
||||
(212, 8) => $expand!(212, 8),
|
||||
(213, 4) => $expand!(213, 4),
|
||||
(213, 8) => $expand!(213, 8),
|
||||
(214, 4) => $expand!(214, 4),
|
||||
(214, 8) => $expand!(214, 8),
|
||||
(215, 4) => $expand!(215, 4),
|
||||
(215, 8) => $expand!(215, 8),
|
||||
(216, 4) => $expand!(216, 4),
|
||||
(216, 8) => $expand!(216, 8),
|
||||
(217, 4) => $expand!(217, 4),
|
||||
(217, 8) => $expand!(217, 8),
|
||||
(218, 4) => $expand!(218, 4),
|
||||
(218, 8) => $expand!(218, 8),
|
||||
(219, 4) => $expand!(219, 4),
|
||||
(219, 8) => $expand!(219, 8),
|
||||
(220, 4) => $expand!(220, 4),
|
||||
(220, 8) => $expand!(220, 8),
|
||||
(221, 4) => $expand!(221, 4),
|
||||
(221, 8) => $expand!(221, 8),
|
||||
(222, 4) => $expand!(222, 4),
|
||||
(222, 8) => $expand!(222, 8),
|
||||
(223, 4) => $expand!(223, 4),
|
||||
(223, 8) => $expand!(223, 8),
|
||||
(224, 4) => $expand!(224, 4),
|
||||
(224, 8) => $expand!(224, 8),
|
||||
(225, 4) => $expand!(225, 4),
|
||||
(225, 8) => $expand!(225, 8),
|
||||
(226, 4) => $expand!(226, 4),
|
||||
(226, 8) => $expand!(226, 8),
|
||||
(227, 4) => $expand!(227, 4),
|
||||
(227, 8) => $expand!(227, 8),
|
||||
(228, 4) => $expand!(228, 4),
|
||||
(228, 8) => $expand!(228, 8),
|
||||
(229, 4) => $expand!(229, 4),
|
||||
(229, 8) => $expand!(229, 8),
|
||||
(230, 4) => $expand!(230, 4),
|
||||
(230, 8) => $expand!(230, 8),
|
||||
(231, 4) => $expand!(231, 4),
|
||||
(231, 8) => $expand!(231, 8),
|
||||
(232, 4) => $expand!(232, 4),
|
||||
(232, 8) => $expand!(232, 8),
|
||||
(233, 4) => $expand!(233, 4),
|
||||
(233, 8) => $expand!(233, 8),
|
||||
(234, 4) => $expand!(234, 4),
|
||||
(234, 8) => $expand!(234, 8),
|
||||
(235, 4) => $expand!(235, 4),
|
||||
(235, 8) => $expand!(235, 8),
|
||||
(236, 4) => $expand!(236, 4),
|
||||
(236, 8) => $expand!(236, 8),
|
||||
(237, 4) => $expand!(237, 4),
|
||||
(237, 8) => $expand!(237, 8),
|
||||
(238, 4) => $expand!(238, 4),
|
||||
(238, 8) => $expand!(238, 8),
|
||||
(239, 4) => $expand!(239, 4),
|
||||
(239, 8) => $expand!(239, 8),
|
||||
(240, 4) => $expand!(240, 4),
|
||||
(240, 8) => $expand!(240, 8),
|
||||
(241, 4) => $expand!(241, 4),
|
||||
(241, 8) => $expand!(241, 8),
|
||||
(242, 4) => $expand!(242, 4),
|
||||
(242, 8) => $expand!(242, 8),
|
||||
(243, 4) => $expand!(243, 4),
|
||||
(243, 8) => $expand!(243, 8),
|
||||
(244, 4) => $expand!(244, 4),
|
||||
(244, 8) => $expand!(244, 8),
|
||||
(245, 4) => $expand!(245, 4),
|
||||
(245, 8) => $expand!(245, 8),
|
||||
(246, 4) => $expand!(246, 4),
|
||||
(246, 8) => $expand!(246, 8),
|
||||
(247, 4) => $expand!(247, 4),
|
||||
(247, 8) => $expand!(247, 8),
|
||||
(248, 4) => $expand!(248, 4),
|
||||
(248, 8) => $expand!(248, 8),
|
||||
(249, 4) => $expand!(249, 4),
|
||||
(249, 8) => $expand!(249, 8),
|
||||
(250, 4) => $expand!(250, 4),
|
||||
(250, 8) => $expand!(250, 8),
|
||||
(251, 4) => $expand!(251, 4),
|
||||
(251, 8) => $expand!(251, 8),
|
||||
(252, 4) => $expand!(252, 4),
|
||||
(252, 8) => $expand!(252, 8),
|
||||
(253, 4) => $expand!(253, 4),
|
||||
(253, 8) => $expand!(253, 8),
|
||||
(254, 4) => $expand!(254, 4),
|
||||
(254, 8) => $expand!(254, 8),
|
||||
(255, 4) => $expand!(255, 4),
|
||||
(255, 8) => $expand!(255, 8),
|
||||
(_, _) => panic!("Invalid sae value"),
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
#[cfg(test)]
|
||||
macro_rules! assert_approx_eq {
|
||||
($a:expr, $b:expr, $eps:expr) => {{
|
||||
|
|
|
|||
|
|
@ -451,6 +451,24 @@ impl m128Ext for __m128 {
|
|||
}
|
||||
}
|
||||
|
||||
#[allow(non_camel_case_types)]
|
||||
#[unstable(feature = "stdsimd_internal", issue = "none")]
|
||||
pub(crate) trait m128dExt: Sized {
|
||||
fn as_m128d(self) -> __m128d;
|
||||
|
||||
#[inline]
|
||||
fn as_f64x2(self) -> crate::core_arch::simd::f64x2 {
|
||||
unsafe { transmute(self.as_m128d()) }
|
||||
}
|
||||
}
|
||||
|
||||
impl m128dExt for __m128d {
|
||||
#[inline]
|
||||
fn as_m128d(self) -> Self {
|
||||
self
|
||||
}
|
||||
}
|
||||
|
||||
#[allow(non_camel_case_types)]
|
||||
#[unstable(feature = "stdsimd_internal", issue = "none")]
|
||||
pub(crate) trait m256Ext: Sized {
|
||||
|
|
|
|||
|
|
@ -71,6 +71,21 @@ pub unsafe fn get_m256(a: __m256, idx: usize) -> f32 {
|
|||
transmute::<_, [f32; 8]>(a)[idx]
|
||||
}
|
||||
|
||||
#[target_feature(enable = "avx512f")]
|
||||
pub unsafe fn get_m512(a: __m512, idx: usize) -> f32 {
|
||||
transmute::<_, [f32; 16]>(a)[idx]
|
||||
}
|
||||
|
||||
#[target_feature(enable = "avx512f")]
|
||||
pub unsafe fn get_m512d(a: __m512d, idx: usize) -> f64 {
|
||||
transmute::<_, [f64; 8]>(a)[idx]
|
||||
}
|
||||
|
||||
#[target_feature(enable = "avx512f")]
|
||||
pub unsafe fn get_m512i(a: __m512i, idx: usize) -> i64 {
|
||||
transmute::<_, [i64; 8]>(a)[idx]
|
||||
}
|
||||
|
||||
// These intrinsics doesn't exist on x86 b/c it requires a 64-bit register,
|
||||
// which doesn't exist on x86!
|
||||
#[cfg(target_arch = "x86")]
|
||||
|
|
|
|||
|
|
@ -68,6 +68,44 @@ mod tests {
|
|||
assert_eq_m512i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_mov_epi64() {
|
||||
let src = _mm512_set1_epi64(1);
|
||||
let a = _mm512_set1_epi64(2);
|
||||
let r = _mm512_mask_mov_epi64(src, 0, a);
|
||||
assert_eq_m512i(r, src);
|
||||
let r = _mm512_mask_mov_epi64(src, 0b11111111, a);
|
||||
assert_eq_m512i(r, a);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_maskz_mov_epi64() {
|
||||
let a = _mm512_set1_epi64(2);
|
||||
let r = _mm512_maskz_mov_epi64(0, a);
|
||||
assert_eq_m512i(r, _mm512_setzero_si512());
|
||||
let r = _mm512_maskz_mov_epi64(0b11111111, a);
|
||||
assert_eq_m512i(r, a);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_mov_pd() {
|
||||
let src = _mm512_set1_pd(1.);
|
||||
let a = _mm512_set1_pd(2.);
|
||||
let r = _mm512_mask_mov_pd(src, 0, a);
|
||||
assert_eq_m512d(r, src);
|
||||
let r = _mm512_mask_mov_pd(src, 0b11111111, a);
|
||||
assert_eq_m512d(r, a);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_maskz_mov_pd() {
|
||||
let a = _mm512_set1_pd(2.);
|
||||
let r = _mm512_maskz_mov_pd(0, a);
|
||||
assert_eq_m512d(r, _mm512_setzero_pd());
|
||||
let r = _mm512_maskz_mov_pd(0b11111111, a);
|
||||
assert_eq_m512d(r, a);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_add_epi64() {
|
||||
let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
|
||||
|
|
@ -995,6 +1033,130 @@ mod tests {
|
|||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_roundscale_pd() {
|
||||
let a = _mm512_set1_pd(1.1);
|
||||
let r = _mm512_roundscale_pd(a, 0);
|
||||
let e = _mm512_set1_pd(1.0);
|
||||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_roundscale_pd() {
|
||||
let a = _mm512_set1_pd(1.1);
|
||||
let r = _mm512_mask_roundscale_pd(a, 0, a, 0);
|
||||
let e = _mm512_set1_pd(1.1);
|
||||
assert_eq_m512d(r, e);
|
||||
let r = _mm512_mask_roundscale_pd(a, 0b11111111, a, 0);
|
||||
let e = _mm512_set1_pd(1.0);
|
||||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_maskz_roundscale_pd() {
|
||||
let a = _mm512_set1_pd(1.1);
|
||||
let r = _mm512_maskz_roundscale_pd(0, a, 0);
|
||||
assert_eq_m512d(r, _mm512_setzero_pd());
|
||||
let r = _mm512_maskz_roundscale_pd(0b11111111, a, 0);
|
||||
let e = _mm512_set1_pd(1.0);
|
||||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_scalef_pd() {
|
||||
let a = _mm512_set1_pd(1.);
|
||||
let b = _mm512_set1_pd(3.);
|
||||
let r = _mm512_scalef_pd(a, b);
|
||||
let e = _mm512_set1_pd(8.);
|
||||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_scalef_pd() {
|
||||
let a = _mm512_set1_pd(1.);
|
||||
let b = _mm512_set1_pd(3.);
|
||||
let r = _mm512_mask_scalef_pd(a, 0, a, b);
|
||||
assert_eq_m512d(r, a);
|
||||
let r = _mm512_mask_scalef_pd(a, 0b11110000, a, b);
|
||||
let e = _mm512_set_pd(8., 8., 8., 8., 1., 1., 1., 1.);
|
||||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_maskz_scalef_pd() {
|
||||
let a = _mm512_set1_pd(1.);
|
||||
let b = _mm512_set1_pd(3.);
|
||||
let r = _mm512_maskz_scalef_pd(0, a, b);
|
||||
assert_eq_m512d(r, _mm512_setzero_pd());
|
||||
let r = _mm512_maskz_scalef_pd(0b11110000, a, b);
|
||||
let e = _mm512_set_pd(8., 8., 8., 8., 0., 0., 0., 0.);
|
||||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_fixupimm_pd() {
|
||||
let a = _mm512_set1_pd(f64::NAN);
|
||||
let b = _mm512_set1_pd(f64::MAX);
|
||||
let c = _mm512_set1_epi64(i32::MAX as i64);
|
||||
let r = _mm512_fixupimm_pd(a, b, c, 5);
|
||||
let e = _mm512_set1_pd(0.0);
|
||||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_fixupimm_pd() {
|
||||
let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
|
||||
let b = _mm512_set1_pd(f64::MAX);
|
||||
let c = _mm512_set1_epi64(i32::MAX as i64);
|
||||
let r = _mm512_mask_fixupimm_pd(a, 0b11110000, b, c, 5);
|
||||
let e = _mm512_set_pd(0., 0., 0., 0., 1., 1., 1., 1.);
|
||||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_maskz_fixupimm_pd() {
|
||||
let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
|
||||
let b = _mm512_set1_pd(f64::MAX);
|
||||
let c = _mm512_set1_epi64(i32::MAX as i64);
|
||||
let r = _mm512_maskz_fixupimm_pd(0b11110000, a, b, c, 5);
|
||||
let e = _mm512_set_pd(0., 0., 0., 0., 0., 0., 0., 0.);
|
||||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_ternarylogic_epi64() {
|
||||
let a = _mm512_set1_epi64(1 << 2);
|
||||
let b = _mm512_set1_epi64(1 << 1);
|
||||
let c = _mm512_set1_epi64(1 << 0);
|
||||
let r = _mm512_ternarylogic_epi64(a, b, c, 8);
|
||||
let e = _mm512_set1_epi64(0);
|
||||
assert_eq_m512i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_ternarylogic_epi64() {
|
||||
let src = _mm512_set1_epi64(1 << 2);
|
||||
let a = _mm512_set1_epi64(1 << 1);
|
||||
let b = _mm512_set1_epi64(1 << 0);
|
||||
let r = _mm512_mask_ternarylogic_epi64(src, 0, a, b, 8);
|
||||
assert_eq_m512i(r, src);
|
||||
let r = _mm512_mask_ternarylogic_epi64(src, 0b11111111, a, b, 8);
|
||||
let e = _mm512_set1_epi64(0);
|
||||
assert_eq_m512i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_maskz_ternarylogic_epi64() {
|
||||
let a = _mm512_set1_epi64(1 << 2);
|
||||
let b = _mm512_set1_epi64(1 << 1);
|
||||
let c = _mm512_set1_epi64(1 << 0);
|
||||
let r = _mm512_maskz_ternarylogic_epi64(0, a, b, c, 9);
|
||||
assert_eq_m512i(r, _mm512_setzero_si512());
|
||||
let r = _mm512_maskz_ternarylogic_epi64(0b11111111, a, b, c, 8);
|
||||
let e = _mm512_set1_epi64(0);
|
||||
assert_eq_m512i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_getmant_pd() {
|
||||
let a = _mm512_set1_pd(10.);
|
||||
|
|
@ -2686,6 +2848,109 @@ mod tests {
|
|||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_roundscale_round_pd() {
|
||||
let a = _mm512_set1_pd(1.1);
|
||||
let r = _mm512_roundscale_round_pd(a, 0, _MM_FROUND_CUR_DIRECTION);
|
||||
let e = _mm512_set1_pd(1.0);
|
||||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_roundscale_round_pd() {
|
||||
let a = _mm512_set1_pd(1.1);
|
||||
let r = _mm512_mask_roundscale_round_pd(a, 0, a, 0, _MM_FROUND_CUR_DIRECTION);
|
||||
let e = _mm512_set1_pd(1.1);
|
||||
assert_eq_m512d(r, e);
|
||||
let r = _mm512_mask_roundscale_round_pd(a, 0b11111111, a, 0, _MM_FROUND_CUR_DIRECTION);
|
||||
let e = _mm512_set1_pd(1.0);
|
||||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_maskz_roundscale_round_pd() {
|
||||
let a = _mm512_set1_pd(1.1);
|
||||
let r = _mm512_maskz_roundscale_round_pd(0, a, 0, _MM_FROUND_CUR_DIRECTION);
|
||||
assert_eq_m512d(r, _mm512_setzero_pd());
|
||||
let r = _mm512_maskz_roundscale_round_pd(0b11111111, a, 0, _MM_FROUND_CUR_DIRECTION);
|
||||
let e = _mm512_set1_pd(1.0);
|
||||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_scalef_round_pd() {
|
||||
let a = _mm512_set1_pd(1.);
|
||||
let b = _mm512_set1_pd(3.);
|
||||
let r = _mm512_scalef_round_pd(a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
|
||||
let e = _mm512_set1_pd(8.);
|
||||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_scalef_round_pd() {
|
||||
let a = _mm512_set1_pd(1.);
|
||||
let b = _mm512_set1_pd(3.);
|
||||
let r =
|
||||
_mm512_mask_scalef_round_pd(a, 0, a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
|
||||
assert_eq_m512d(r, a);
|
||||
let r = _mm512_mask_scalef_round_pd(
|
||||
a,
|
||||
0b11110000,
|
||||
a,
|
||||
b,
|
||||
_MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
|
||||
);
|
||||
let e = _mm512_set_pd(8., 8., 8., 8., 1., 1., 1., 1.);
|
||||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_maskz_scalef_round_pd() {
|
||||
let a = _mm512_set1_pd(1.);
|
||||
let b = _mm512_set1_pd(3.);
|
||||
let r =
|
||||
_mm512_maskz_scalef_round_pd(0, a, b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
|
||||
assert_eq_m512d(r, _mm512_setzero_pd());
|
||||
let r = _mm512_maskz_scalef_round_pd(
|
||||
0b11110000,
|
||||
a,
|
||||
b,
|
||||
_MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC,
|
||||
);
|
||||
let e = _mm512_set_pd(8., 8., 8., 8., 0., 0., 0., 0.);
|
||||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_fixupimm_round_pd() {
|
||||
let a = _mm512_set1_pd(f64::NAN);
|
||||
let b = _mm512_set1_pd(f64::MAX);
|
||||
let c = _mm512_set1_epi64(i32::MAX as i64);
|
||||
let r = _mm512_fixupimm_round_pd(a, b, c, 5, _MM_FROUND_CUR_DIRECTION);
|
||||
let e = _mm512_set1_pd(0.0);
|
||||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_fixupimm_round_pd() {
|
||||
let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
|
||||
let b = _mm512_set1_pd(f64::MAX);
|
||||
let c = _mm512_set1_epi64(i32::MAX as i64);
|
||||
let r = _mm512_mask_fixupimm_round_pd(a, 0b11110000, b, c, 5, _MM_FROUND_CUR_DIRECTION);
|
||||
let e = _mm512_set_pd(0., 0., 0., 0., 1., 1., 1., 1.);
|
||||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_maskz_fixupimm_round_pd() {
|
||||
let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
|
||||
let b = _mm512_set1_pd(f64::MAX);
|
||||
let c = _mm512_set1_epi64(i32::MAX as i64);
|
||||
let r = _mm512_maskz_fixupimm_round_pd(0b11110000, a, b, c, 5, _MM_FROUND_CUR_DIRECTION);
|
||||
let e = _mm512_set_pd(0., 0., 0., 0., 0., 0., 0., 0.);
|
||||
assert_eq_m512d(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_getmant_round_pd() {
|
||||
let a = _mm512_set1_pd(10.);
|
||||
|
|
@ -5681,6 +5946,13 @@ mod tests {
|
|||
assert_eq!(8, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_reduce_add_epi64() {
|
||||
let a = _mm512_set1_epi64(1);
|
||||
let e: i64 = _mm512_mask_reduce_add_epi64(0b11110000, a);
|
||||
assert_eq!(4, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_reduce_add_pd() {
|
||||
let a = _mm512_set1_pd(1.);
|
||||
|
|
@ -5695,6 +5967,20 @@ mod tests {
|
|||
assert_eq!(4., e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_reduce_mul_epi64() {
|
||||
let a = _mm512_set1_epi64(2);
|
||||
let e: i64 = _mm512_reduce_mul_epi64(a);
|
||||
assert_eq!(256, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_reduce_mul_epi64() {
|
||||
let a = _mm512_set1_epi64(2);
|
||||
let e: i64 = _mm512_mask_reduce_mul_epi64(0b11110000, a);
|
||||
assert_eq!(16, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_reduce_mul_pd() {
|
||||
let a = _mm512_set1_pd(2.);
|
||||
|
|
@ -5709,6 +5995,34 @@ mod tests {
|
|||
assert_eq!(16., e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_reduce_max_epi64() {
|
||||
let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
|
||||
let e: i64 = _mm512_reduce_max_epi64(a);
|
||||
assert_eq!(7, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_reduce_max_epi64() {
|
||||
let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
|
||||
let e: i64 = _mm512_mask_reduce_max_epi64(0b11110000, a);
|
||||
assert_eq!(3, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_reduce_max_epu64() {
|
||||
let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
|
||||
let e: u64 = _mm512_reduce_max_epu64(a);
|
||||
assert_eq!(7, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_reduce_max_epu64() {
|
||||
let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
|
||||
let e: u64 = _mm512_mask_reduce_max_epu64(0b11110000, a);
|
||||
assert_eq!(3, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_reduce_max_pd() {
|
||||
let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
|
||||
|
|
@ -5723,6 +6037,34 @@ mod tests {
|
|||
assert_eq!(3., e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_reduce_min_epi64() {
|
||||
let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
|
||||
let e: i64 = _mm512_reduce_min_epi64(a);
|
||||
assert_eq!(0, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_reduce_min_epi64() {
|
||||
let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
|
||||
let e: i64 = _mm512_mask_reduce_min_epi64(0b11110000, a);
|
||||
assert_eq!(0, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_reduce_min_epu64() {
|
||||
let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
|
||||
let e: u64 = _mm512_reduce_min_epu64(a);
|
||||
assert_eq!(0, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_reduce_min_epu64() {
|
||||
let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
|
||||
let e: u64 = _mm512_mask_reduce_min_epu64(0b11110000, a);
|
||||
assert_eq!(0, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_reduce_min_pd() {
|
||||
let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
|
||||
|
|
@ -5737,6 +6079,34 @@ mod tests {
|
|||
assert_eq!(0., e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_reduce_and_epi64() {
|
||||
let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
|
||||
let e: i64 = _mm512_reduce_and_epi64(a);
|
||||
assert_eq!(0, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_reduce_and_epi64() {
|
||||
let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
|
||||
let e: i64 = _mm512_mask_reduce_and_epi64(0b11110000, a);
|
||||
assert_eq!(1, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_reduce_or_epi64() {
|
||||
let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
|
||||
let e: i64 = _mm512_reduce_or_epi64(a);
|
||||
assert_eq!(3, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_reduce_or_epi64() {
|
||||
let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
|
||||
let e: i64 = _mm512_mask_reduce_or_epi64(0b11110000, a);
|
||||
assert_eq!(1, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_extractf64x4_pd() {
|
||||
let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
|
||||
|
|
@ -5925,4 +6295,95 @@ mod tests {
|
|||
_mm512_store_pd(&mut r as *mut _ as *mut f64, a);
|
||||
assert_eq_m512d(r, a);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_test_epi64_mask() {
|
||||
let a = _mm512_set1_epi64(1 << 0);
|
||||
let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
|
||||
let r = _mm512_test_epi64_mask(a, b);
|
||||
let e: __mmask8 = 0b11111111;
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_test_epi64_mask() {
|
||||
let a = _mm512_set1_epi64(1 << 0);
|
||||
let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
|
||||
let r = _mm512_mask_test_epi64_mask(0, a, b);
|
||||
assert_eq!(r, 0);
|
||||
let r = _mm512_mask_test_epi64_mask(0b11111111, a, b);
|
||||
let e: __mmask8 = 0b11111111;
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_testn_epi64_mask() {
|
||||
let a = _mm512_set1_epi64(1 << 0);
|
||||
let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
|
||||
let r = _mm512_testn_epi64_mask(a, b);
|
||||
let e: __mmask8 = 0b00000000;
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_testn_epi64_mask() {
|
||||
let a = _mm512_set1_epi64(1 << 0);
|
||||
let b = _mm512_set1_epi64(1 << 1);
|
||||
let r = _mm512_mask_testn_epi64_mask(0, a, b);
|
||||
assert_eq!(r, 0);
|
||||
let r = _mm512_mask_testn_epi64_mask(0b11111111, a, b);
|
||||
let e: __mmask8 = 0b11111111;
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_stream_pd() {
|
||||
#[repr(align(64))]
|
||||
struct Memory {
|
||||
pub data: [f64; 8],
|
||||
}
|
||||
let a = _mm512_set1_pd(7.0);
|
||||
let mut mem = Memory { data: [-1.0; 8] };
|
||||
|
||||
_mm512_stream_pd(&mut mem.data[0] as *mut f64, a);
|
||||
for i in 0..8 {
|
||||
assert_eq!(mem.data[i], get_m512d(a, i));
|
||||
}
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_stream_si512() {
|
||||
#[repr(align(64))]
|
||||
struct Memory {
|
||||
pub data: [i64; 8],
|
||||
}
|
||||
let a = _mm512_set1_epi64(7);
|
||||
let mut mem = Memory { data: [-1; 8] };
|
||||
|
||||
_mm512_stream_si512(&mut mem.data[0] as *mut i64, a);
|
||||
for i in 0..8 {
|
||||
assert_eq!(mem.data[i], get_m512i(a, i));
|
||||
}
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_mask_set1_epi64() {
|
||||
let src = _mm512_set1_epi64(2);
|
||||
let a: i64 = 11;
|
||||
let r = _mm512_mask_set1_epi64(src, 0, a);
|
||||
assert_eq_m512i(r, src);
|
||||
let r = _mm512_mask_set1_epi64(src, 0b11111111, a);
|
||||
let e = _mm512_set1_epi64(11);
|
||||
assert_eq_m512i(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "avx512f")]
|
||||
unsafe fn test_mm512_maskz_set1_epi64() {
|
||||
let a: i64 = 11;
|
||||
let r = _mm512_maskz_set1_epi64(0, a);
|
||||
assert_eq_m512i(r, _mm512_setzero_si512());
|
||||
let r = _mm512_maskz_set1_epi64(0b11111111, a);
|
||||
let e = _mm512_set1_epi64(11);
|
||||
assert_eq_m512i(r, e);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -577,7 +577,24 @@ fn matches(rust: &Function, intel: &Intrinsic) -> Result<(), String> {
|
|||
| "_mm512_setr4_epi64"
|
||||
| "_mm512_set_epi64"
|
||||
| "_mm512_setr_epi64"
|
||||
| "_mm512_reduce_add_epi64" => true,
|
||||
| "_mm512_reduce_add_epi64"
|
||||
| "_mm512_mask_reduce_add_epi64"
|
||||
| "_mm512_reduce_mul_epi64"
|
||||
| "_mm512_mask_reduce_mul_epi64"
|
||||
| "_mm512_reduce_max_epi64"
|
||||
| "_mm512_mask_reduce_max_epi64"
|
||||
| "_mm512_reduce_max_epu64"
|
||||
| "_mm512_mask_reduce_max_epu64"
|
||||
| "_mm512_reduce_min_epi64"
|
||||
| "_mm512_mask_reduce_min_epi64"
|
||||
| "_mm512_reduce_min_epu64"
|
||||
| "_mm512_mask_reduce_min_epu64"
|
||||
| "_mm512_reduce_and_epi64"
|
||||
| "_mm512_mask_reduce_and_epi64"
|
||||
| "_mm512_reduce_or_epi64"
|
||||
| "_mm512_mask_reduce_or_epi64"
|
||||
| "_mm512_mask_set1_epi64"
|
||||
| "_mm512_maskz_set1_epi64" => true,
|
||||
|
||||
// These return a 64-bit argument but they're assembled from other
|
||||
// 32-bit registers, so these work on 32-bit just fine. See #308 for
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue