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Avx512f avx512vl (#1001)

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minybot 2021-02-14 12:59:05 -05:00 • committed by GitHub
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library/stdarch/crates/core_arch/avx512f.md
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@ -1569,343 +1569,211 @@
* [ ] [`_mm512_mask_i32loscatter_epi64`] //not in llvm
* [ ] [`_mm512_i32loscatter_pd`] //not in llvm
* [ ] [`_mm512_mask_i32loscatter_pd`] //not in llvm
* [x] [`_mm512_castpd128_pd512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd128_pd512&expand=5236)
* [x] [`_mm512_castpd256_pd512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd256_pd512&expand=5236)
* [x] [`_mm512_castpd512_pd128`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd512_pd128&expand=5236)
* [x] [`_mm512_castpd512_pd256`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd512_pd256&expand=5236)
* [x] [`_mm512_castpd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd_ps&expand=5236)
* [x] [`_mm512_castpd_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd_si512&expand=5236)
* [x] [`_mm512_castps128_ps512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castps128_ps512&expand=5236)
* [x] [`_mm512_castps256_ps512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castps256_ps512&expand=5236)
* [x] [`_mm512_castps512_ps128`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castps512_ps128&expand=5236)
* [x] [`_mm512_castps512_ps256`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castps512_ps256&expand=5236)
* [x] [`_mm512_castps_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castps_pd&expand=5236)
* [x] [`_mm512_castps_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castps_si512&expand=5236)
* [x] [`_mm512_castsi128_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castsi128_si512&expand=5236)
* [x] [`_mm512_castsi256_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castsi256_si512&expand=5236)
* [x] [`_mm512_castsi512_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castsi512_pd&expand=5236)
* [x] [`_mm512_castsi512_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castsi512_ps&expand=5236)
* [x] [`_mm512_castsi512_si128`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castsi512_si128&expand=5236)
* [x] [`_mm512_castsi512_si256`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castsi512_si256&expand=5236)
* [x] [`_mm512_cvt_roundepi32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundepi32_ps&expand=5236)
* [x] [`_mm512_cvt_roundepu32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundepu32_ps&expand=5236)
* [x] [`_mm512_cvt_roundpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundpd_epi32&expand=5236)
* [x] [`_mm512_cvt_roundpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundpd_epu32&expand=5236)
* [x] [`_mm512_cvt_roundpd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundpd_ps&expand=5236)
* [x] [`_mm512_cvt_roundph_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundph_ps&expand=5236)
* [x] [`_mm512_cvt_roundps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundps_epi32&expand=5236)
* [x] [`_mm512_cvt_roundps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundps_epu32&expand=5236)
* [x] [`_mm512_cvt_roundps_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundps_pd&expand=5236)
* [x] [`_mm512_cvt_roundps_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvt_roundps_ph&expand=5236)
* [x] [`_mm512_cvtepi16_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi16_epi32&expand=5236)
* [x] [`_mm512_cvtepi16_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi16_epi64&expand=5236)
* [x] [`_mm512_cvtepi32_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi32_epi16&expand=5236)
* [x] [`_mm512_cvtepi32_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi32_epi64&expand=5236)
* [x] [`_mm512_cvtepi32_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi32_epi8&expand=5236)
* [x] [`_mm512_cvtepi32_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi32_pd&expand=5236)
* [x] [`_mm512_cvtepi32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi32_ps&expand=5236)
* [x] [`_mm512_cvtepi32lo_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi32lo_pd&expand=5236)
* [x] [`_mm512_cvtepi64_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi64_epi16&expand=5236)
* [x] [`_mm512_cvtepi64_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi64_epi32&expand=5236)
* [x] [`_mm512_cvtepi64_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi64_epi8&expand=5236)
* [x] [`_mm512_cvtepi8_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi8_epi32&expand=5236)
* [x] [`_mm512_cvtepi8_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepi8_epi64&expand=5236)
* [x] [`_mm512_cvtepu16_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepu16_epi32&expand=5236)
* [x] [`_mm512_cvtepu16_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepu16_epi64&expand=5236)
* [x] [`_mm512_cvtepu32_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepu32_epi64&expand=5236)
* [x] [`_mm512_cvtepu32_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepu32_pd&expand=5236)
* [x] [`_mm512_cvtepu32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepu32_ps&expand=5236)
* [x] [`_mm512_cvtepu32lo_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepu32lo_pd&expand=5236)
* [x] [`_mm512_cvtepu8_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepu8_epi32&expand=5236)
* [x] [`_mm512_cvtepu8_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtepu8_epi64&expand=5236)
* [x] [`_mm512_cvtpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtpd_epi32&expand=5236)
* [x] [`_mm512_cvtpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtpd_epu32&expand=5236)
* [x] [`_mm512_cvtpd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtpd_ps&expand=5236)
* [x] [`_mm512_cvtpd_pslo`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtpd_pslo&expand=5236)
* [x] [`_mm512_cvtph_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtph_ps&expand=5236)
* [x] [`_mm512_cvtps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtps_epi32&expand=5236)
* [x] [`_mm512_cvtps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtps_epu32&expand=5236)
* [x] [`_mm512_cvtps_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtps_pd&expand=5236)
* [x] [`_mm512_cvtps_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtps_ph&expand=5236)
* [x] [`_mm512_cvtpslo_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtpslo_pd&expand=5236)
* [x] [`_mm512_cvtsepi32_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtsepi32_epi16&expand=5236)
* [x] [`_mm512_cvtsepi32_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtsepi32_epi8&expand=5236)
* [x] [`_mm512_cvtsepi64_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtsepi64_epi16&expand=5236)
* [x] [`_mm512_cvtsepi64_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtsepi64_epi32&expand=5236)
* [x] [`_mm512_cvtsepi64_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtsepi64_epi8&expand=5236)
* [x] [`_mm512_cvtt_roundpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtt_roundpd_epi32&expand=5236)
* [x] [`_mm512_cvtt_roundpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtt_roundpd_epu32&expand=5236)
* [x] [`_mm512_cvtt_roundps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtt_roundps_epi32&expand=5236)
* [x] [`_mm512_cvtt_roundps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtt_roundps_epu32&expand=5236)
* [x] [`_mm512_cvttpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvttpd_epi32&expand=5236)
* [x] [`_mm512_cvttpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvttpd_epu32&expand=5236)
* [x] [`_mm512_cvttps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvttps_epi32&expand=5236)
* [x] [`_mm512_cvttps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvttps_epu32&expand=5236)
* [x] [`_mm512_cvtusepi32_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtusepi32_epi16&expand=5236)
* [x] [`_mm512_cvtusepi32_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtusepi32_epi8&expand=5236)
* [x] [`_mm512_cvtusepi64_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtusepi64_epi16&expand=5236)
* [x] [`_mm512_cvtusepi64_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtusepi64_epi32&expand=5236)
* [x] [`_mm512_cvtusepi64_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtusepi64_epi8&expand=5236)
* [x] [`_mm512_extractf32x4_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_extractf32x4_ps&expand=5236)
* [x] [`_mm512_extractf64x4_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_extractf64x4_pd&expand=5236)
* [x] [`_mm512_extracti32x4_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_extracti32x4_epi32&expand=5236)
* [x] [`_mm512_extracti64x4_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_extracti64x4_epi64&expand=5236)
* [x] [`_mm512_insertf32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_insertf32x4&expand=5236)
* [x] [`_mm512_insertf64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_insertf64x4&expand=5236)
* [x] [`_mm512_inserti32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_inserti32x4&expand=5236)
* [x] [`_mm512_inserti64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_inserti64x4&expand=5236)
* [x] [`_mm512_int2mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_int2mask&expand=5236)
* [x] [`_mm512_kand`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_kand&expand=5236)
* [x] [`_mm512_kandn`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_kandn&expand=5236)
* [x] [`_mm512_kmov`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_kmov&expand=5236)
* [x] [`_mm512_knot`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_knot&expand=5236)
* [x] [`_mm512_kor`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_kor&expand=5236)
* [x] [`_mm512_kortestc`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_kortestc&expand=5236)
* [ ] [`_mm512_kortestz`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_kortestz&expand=5236)
* [x] [`_mm512_kunpackb`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_kunpackb&expand=5236)
* [x] [`_mm512_kxnor`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_kxnor&expand=5236)
* [x] [`_mm512_kxor`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_kxor&expand=5236)
* [x] [`_mm512_load_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_load_epi32&expand=5236)
* [x] [`_mm512_load_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_load_epi64&expand=5236)
* [x] [`_mm512_load_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_load_pd&expand=5236)
* [x] [`_mm512_load_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_load_ps&expand=5236)
* [x] [`_mm512_load_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_load_si512&expand=5236)
* [x] [`_mm512_loadu_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_loadu_pd&expand=5236)
* [x] [`_mm512_loadu_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_loadu_ps&expand=5236)
* [x] [`_mm512_loadu_epi32`]
* [x] [`_mm512_loadu_epi64`]
* [x] [`_mm512_loadu_si512`]
* [x] [`_mm512_mask2int`]
* [x] [`_mm512_inserti32x4`]
* [x] [`_mm512_mask_inserti32x4`]
* [x] [`_mm512_maskz_inserti32x4`]
* [x] [`_mm256_inserti32x4`]
* [x] [`_mm256_mask_inserti32x4`]
* [x] [`_mm256_maskz_inserti32x4`]
* [x] [`_mm512_inserti64x4`]
* [x] [`_mm512_mask_inserti64x4`]
* [x] [`_mm512_maskz_inserti64x4`]
* [x] [`_mm512_insertf32x4`]
* [x] [`_mm512_mask_insertf32x4`]
* [x] [`_mm512_maskz_insertf32x4`]
* [x] [`_mm256_insertf32x4`]
* [x] [`_mm256_mask_insertf32x4`]
* [x] [`_mm256_maskz_insertf32x4`]
* [x] [`_mm512_insertf64x4`]
* [x] [`_mm512_mask_insertf64x4`]
* [x] [`_mm512_maskz_insertf64x4`]
* [x] [`_mm512_extracti32x4_epi32`]
* [x] [`_mm512_mask_extracti32x4_epi32`]
* [x] [`_mm512_maskz_extracti32x4_epi32`]
* [x] [`_mm256_extracti32x4_epi32`]
* [x] [`_mm256_mask_extracti32x4_epi32`]
* [x] [`_mm256_maskz_extracti32x4_epi32`]
* [x] [`_mm512_extracti64x4_epi64`]
* [x] [`_mm512_mask_extracti64x4_epi64`]
* [x] [`_mm512_maskz_extracti64x4_epi64`]
* [x] [`_mm512_extractf32x4_ps`]
* [x] [`_mm512_mask_extractf32x4_ps`]
* [x] [`_mm512_maskz_extractf32x4_ps`]
* [x] [`_mm256_extractf32x4_ps`]
* [x] [`_mm256_mask_extractf32x4_ps`]
* [x] [`_mm256_maskz_extractf32x4_ps`]
* [x] [`_mm512_extractf64x4_pd`]
* [x] [`_mm512_mask_extractf64x4_pd`]
* [x] [`_mm512_maskz_extractf64x4_pd`]
* [x] [`_mm512_maskz_compress_epi32`]
* [x] [`_mm512_mask_compress_epi32`]
* [x] [`_mm_mask_compress_epi32`]
* [x] [`_mm_maskz_compress_epi32`]
* [x] [`_mm256_mask_compress_epi32`]
* [x] [`_mm256_maskz_compress_epi32`]
* [x] [`_mm512_mask_compress_epi64`]
* [x] [`_mm512_mask_compress_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_compress_pd&expand=5236)
* [x] [`_mm512_mask_compress_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_compress_ps&expand=5236)
* [ ] [`_mm512_mask_compressstoreu_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_compressstoreu_epi32&expand=5236)
* [ ] [`_mm512_mask_compressstoreu_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_compressstoreu_epi64&expand=5236)
* [ ] [`_mm512_mask_compressstoreu_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_compressstoreu_pd&expand=5236)
* [ ] [`_mm512_mask_compressstoreu_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_compressstoreu_ps&expand=5236)
* [x] [`_mm512_mask_cvt_roundepi32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundepi32_ps&expand=5236)
* [x] [`_mm512_mask_cvt_roundepu32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundepu32_ps&expand=5236)
* [x] [`_mm512_mask_cvt_roundpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundpd_epi32&expand=5236)
* [x] [`_mm512_mask_cvt_roundpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundpd_epu32&expand=5236)
* [x] [`_mm512_mask_cvt_roundpd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundpd_ps&expand=5236)
* [x] [`_mm512_mask_cvt_roundph_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundph_ps&expand=5236)
* [x] [`_mm512_mask_cvt_roundps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundps_epi32&expand=5236)
* [x] [`_mm512_mask_cvt_roundps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundps_epu32&expand=5236)
* [x] [`_mm512_mask_cvt_roundps_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundps_pd&expand=5236)
* [x] [`_mm512_mask_cvt_roundps_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvt_roundps_ph&expand=5236)
* [x] [`_mm512_mask_cvtepi16_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi16_epi32&expand=5236)
* [x] [`_mm512_mask_cvtepi16_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi16_epi64&expand=5236)
* [x] [`_mm512_mask_cvtepi32_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi32_epi16&expand=5236)
* [x] [`_mm512_mask_cvtepi32_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi32_epi64&expand=5236)
* [x] [`_mm512_mask_cvtepi32_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi32_epi8&expand=5236)
* [x] [`_mm512_mask_cvtepi32_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi32_pd&expand=5236)
* [x] [`_mm512_mask_cvtepi32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi32_ps&expand=5236)
* [ ] [`_mm512_mask_cvtepi32_storeu_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi32_storeu_epi16&expand=5236)
* [ ] [`_mm512_mask_cvtepi32_storeu_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi32_storeu_epi8&expand=5236)
* [x] [`_mm512_mask_cvtepi32lo_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi32lo_pd&expand=5236)
* [x] [`_mm512_mask_cvtepi64_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi64_epi16&expand=5236)
* [x] [`_mm512_mask_cvtepi64_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi64_epi32&expand=5236)
* [x] [`_mm512_mask_cvtepi64_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi64_epi8&expand=5236)
* [ ] [`_mm512_mask_cvtepi64_storeu_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi64_storeu_epi16&expand=5236)
* [ ] [`_mm512_mask_cvtepi64_storeu_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi64_storeu_epi32&expand=5236)
* [ ] [`_mm512_mask_cvtepi64_storeu_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi64_storeu_epi8&expand=5236)
* [x] [`_mm512_mask_cvtepi8_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi8_epi32&expand=5236)
* [x] [`_mm512_mask_cvtepi8_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepi8_epi64&expand=5236)
* [x] [`_mm512_mask_cvtepu16_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepu16_epi32&expand=5236)
* [x] [`_mm512_mask_cvtepu16_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepu16_epi64&expand=5236)
* [x] [`_mm512_mask_cvtepu32_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepu32_epi64&expand=5236)
* [x] [`_mm512_mask_cvtepu32_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepu32_pd&expand=5236)
* [x] [`_mm512_mask_cvtepu32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepu32_ps&expand=5236)
* [x] [`_mm512_mask_cvtepu32lo_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepu32lo_pd&expand=5236)
* [x] [`_mm512_mask_cvtepu8_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepu8_epi32&expand=5236)
* [x] [`_mm512_mask_cvtepu8_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtepu8_epi64&expand=5236)
* [x] [`_mm512_mask_cvtpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtpd_epi32&expand=5236)
* [x] [`_mm512_mask_cvtpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtpd_epu32&expand=5236)
* [x] [`_mm512_mask_cvtpd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtpd_ps&expand=5236)
* [x] [`_mm512_mask_cvtpd_pslo`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtpd_pslo&expand=5236)
* [x] [`_mm512_mask_cvtph_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtph_ps&expand=5236)
* [x] [`_mm512_mask_cvtps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtps_epi32&expand=5236)
* [x] [`_mm512_mask_cvtps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtps_epu32&expand=5236)
* [x] [`_mm512_mask_cvtps_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtps_pd&expand=5236)
* [x] [`_mm512_mask_cvtps_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtps_ph&expand=5236)
* [x] [`_mm512_mask_cvtpslo_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtpslo_pd&expand=5236)
* [x] [`_mm512_mask_cvtsepi32_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtsepi32_epi16&expand=5236)
* [x] [`_mm512_mask_cvtsepi32_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtsepi32_epi8&expand=5236)
* [ ] [`_mm512_mask_cvtsepi32_storeu_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtsepi32_storeu_epi16&expand=5236)
* [ ] [`_mm512_mask_cvtsepi32_storeu_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtsepi32_storeu_epi8&expand=5236)
* [x] [`_mm512_mask_cvtsepi64_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtsepi64_epi16&expand=5236)
* [x] [`_mm512_mask_cvtsepi64_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtsepi64_epi32&expand=5236)
* [x] [`_mm512_mask_cvtsepi64_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtsepi64_epi8&expand=5236)
* [ ] [`_mm512_mask_cvtsepi64_storeu_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtsepi64_storeu_epi16&expand=5236)
* [ ] [`_mm512_mask_cvtsepi64_storeu_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtsepi64_storeu_epi32&expand=5236)
* [ ] [`_mm512_mask_cvtsepi64_storeu_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtsepi64_storeu_epi8&expand=5236)
* [x] [`_mm512_mask_cvtt_roundpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtt_roundpd_epi32&expand=5236)
* [x] [`_mm512_mask_cvtt_roundpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtt_roundpd_epu32&expand=5236)
* [x] [`_mm512_mask_cvtt_roundps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtt_roundps_epi32&expand=5236)
* [x] [`_mm512_mask_cvtt_roundps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtt_roundps_epu32&expand=5236)
* [x] [`_mm512_mask_cvttpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvttpd_epi32&expand=5236)
* [x] [`_mm512_mask_cvttpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvttpd_epu32&expand=5236)
* [x] [`_mm512_mask_cvttps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvttps_epi32&expand=5236)
* [x] [`_mm512_mask_cvttps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvttps_epu32&expand=5236)
* [x] [`_mm512_mask_cvtusepi32_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi32_epi16&expand=5236)
* [x] [`_mm512_mask_cvtusepi32_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi32_epi8&expand=5236)
* [ ] [`_mm512_mask_cvtusepi32_storeu_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi32_storeu_epi16&expand=5236)
* [ ] [`_mm512_mask_cvtusepi32_storeu_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi32_storeu_epi8&expand=5236)
* [x] [`_mm512_mask_cvtusepi64_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi64_epi16&expand=5236)
* [x] [`_mm512_mask_cvtusepi64_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi64_epi32&expand=5236)
* [x] [`_mm512_mask_cvtusepi64_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi64_epi8&expand=5236)
* [ ] [`_mm512_mask_cvtusepi64_storeu_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi64_storeu_epi16&expand=5236)
* [ ] [`_mm512_mask_cvtusepi64_storeu_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi64_storeu_epi32&expand=5236)
* [ ] [`_mm512_mask_cvtusepi64_storeu_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtusepi64_storeu_epi8&expand=5236)
* [x] [`_mm512_mask_expand_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_expand_epi32&expand=5236)
* [x] [`_mm512_mask_expand_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_expand_epi64&expand=5236)
* [x] [`_mm512_mask_expand_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_expand_pd&expand=5236)
* [x] [`_mm512_mask_expand_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_expand_ps&expand=5236)
* [ ] [`_mm512_mask_expandloadu_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_expandloadu_epi32&expand=5236)
* [ ] [`_mm512_mask_expandloadu_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_expandloadu_epi64&expand=5236)
* [ ] [`_mm512_mask_expandloadu_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_expandloadu_pd&expand=5236)
* [ ] [`_mm512_mask_expandloadu_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_expandloadu_ps&expand=5236)
* [x] [`_mm512_mask_extractf32x4_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_extractf32x4_ps&expand=5236)
* [x] [`_mm512_mask_extractf64x4_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_extractf64x4_pd&expand=5236)
* [x] [`_mm512_mask_extracti32x4_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_extracti32x4_epi32&expand=5236)
* [x] [`_mm512_mask_extracti64x4_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_extracti64x4_epi64&expand=5236)
* [x] [`_mm512_mask_insertf32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_insertf32x4&expand=5236)
* [x] [`_mm512_mask_insertf64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_insertf64x4&expand=5236)
* [x] [`_mm512_mask_inserti32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_inserti32x4&expand=5236)
* [x] [`_mm512_mask_inserti64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_inserti64x4&expand=5236)
* [ ] [`_mm512_mask_load_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_load_epi32&expand=5236)
* [ ] [`_mm512_mask_load_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_load_epi64&expand=5236)
* [ ] [`_mm512_mask_load_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_load_pd&expand=5236)
* [ ] [`_mm512_mask_load_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_load_ps&expand=5236)
* [ ] [`_mm512_mask_loadu_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_loadu_epi32&expand=5236)
* [ ] [`_mm512_mask_loadu_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_loadu_epi64&expand=5236)
* [ ] [`_mm512_mask_loadu_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_loadu_pd&expand=5236)
* [ ] [`_mm512_mask_loadu_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_loadu_ps&expand=5236)
* [x] [`_mm512_mask_set1_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_set1_epi32&expand=5236)
* [x] [`_mm512_mask_set1_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_set1_epi64&expand=5236)
* [ ] [`_mm512_mask_store_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_store_epi32&expand=5236)
* [ ] [`_mm512_mask_store_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_store_epi64&expand=5236)
* [ ] [`_mm512_mask_store_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_store_pd&expand=5236)
* [ ] [`_mm512_mask_store_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_store_ps&expand=5236)
* [ ] [`_mm512_mask_storeu_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_storeu_epi32&expand=5236)
* [ ] [`_mm512_mask_storeu_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_storeu_epi64&expand=5236)
* [ ] [`_mm512_mask_storeu_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_storeu_pd&expand=5236)
* [ ] [`_mm512_mask_storeu_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_storeu_ps&expand=5236)
* [x] [`_mm512_mask_ternarylogic_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_ternarylogic_epi32&expand=5236)
* [x] [`_mm512_mask_ternarylogic_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_ternarylogic_epi64&expand=5236)
* [x] [`_mm512_mask_test_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_test_epi32_mask&expand=5236)
* [x] [`_mm512_mask_test_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_test_epi64_mask&expand=5236)
* [x] [`_mm512_mask_testn_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_testn_epi32_mask&expand=5236)
* [x] [`_mm512_mask_testn_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_testn_epi64_mask&expand=5236)
* [x] [`_mm512_maskz_compress_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_compress_epi32&expand=5236)
* [x] [`_mm512_maskz_compress_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_compress_epi64&expand=5236)
* [x] [`_mm512_maskz_compress_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_compress_pd&expand=5236)
* [x] [`_mm512_maskz_compress_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_compress_ps&expand=5236)
* [x] [`_mm512_maskz_cvt_roundepi32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundepi32_ps&expand=5236)
* [x] [`_mm512_maskz_cvt_roundepu32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundepu32_ps&expand=5236)
* [x] [`_mm512_maskz_cvt_roundpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundpd_epi32&expand=5236)
* [x] [`_mm512_maskz_cvt_roundpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundpd_epu32&expand=5236)
* [x] [`_mm512_maskz_cvt_roundpd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundpd_ps&expand=5236)
* [x] [`_mm512_maskz_cvt_roundph_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundph_ps&expand=5236)
* [x] [`_mm512_maskz_cvt_roundps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundps_epi32&expand=5236)
* [x] [`_mm512_maskz_cvt_roundps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundps_epu32&expand=5236)
* [x] [`_mm512_maskz_cvt_roundps_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundps_pd&expand=5236)
* [x] [`_mm512_maskz_cvt_roundps_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundps_ph&expand=5236)
* [x] [`_mm512_maskz_cvtepi16_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi16_epi32&expand=5236)
* [x] [`_mm512_maskz_cvtepi16_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi16_epi64&expand=5236)
* [x] [`_mm512_maskz_cvtepi32_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi32_epi16&expand=5236)
* [x] [`_mm512_maskz_cvtepi32_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi32_epi64&expand=5236)
* [x] [`_mm512_maskz_cvtepi32_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi32_epi8&expand=5236)
* [x] [`_mm512_maskz_cvtepi32_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi32_pd&expand=5236)
* [x] [`_mm512_maskz_cvtepi32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi32_ps&expand=5236)
* [x] [`_mm512_maskz_cvtepi64_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi64_epi16&expand=5236)
* [x] [`_mm512_maskz_cvtepi64_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi64_epi32&expand=5236)
* [x] [`_mm512_maskz_cvtepi64_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi64_epi8&expand=5236)
* [x] [`_mm512_maskz_cvtepi8_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi8_epi32&expand=5236)
* [x] [`_mm512_maskz_cvtepi8_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepi8_epi64&expand=5236)
* [x] [`_mm512_maskz_cvtepu16_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepu16_epi32&expand=5236)
* [x] [`_mm512_maskz_cvtepu16_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepu16_epi64&expand=5236)
* [x] [`_mm512_maskz_cvtepu32_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepu32_epi64&expand=5236)
* [x] [`_mm512_maskz_cvtepu32_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepu32_pd&expand=5236)
* [x] [`_mm512_maskz_cvtepu32_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepu32_ps&expand=5236)
* [x] [`_mm512_maskz_cvtepu8_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepu8_epi32&expand=5236)
* [x] [`_mm512_maskz_cvtepu8_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtepu8_epi64&expand=5236)
* [x] [`_mm512_maskz_cvtpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtpd_epi32&expand=5236)
* [x] [`_mm512_maskz_cvtpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtpd_epu32&expand=5236)
* [x] [`_mm512_maskz_cvtpd_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtpd_ps&expand=5236)
* [x] [`_mm512_maskz_cvtph_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtph_ps&expand=5236)
* [x] [`_mm512_maskz_cvtps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtps_epi32&expand=5236)
* [x] [`_mm512_maskz_cvtps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtps_epu32&expand=5236)
* [x] [`_mm512_maskz_cvtps_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtps_pd&expand=5236)
* [x] [`_mm512_maskz_cvtps_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtps_ph&expand=5236)
* [x] [`_mm512_maskz_cvtsepi32_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtsepi32_epi16&expand=5236)
* [x] [`_mm512_maskz_cvtsepi32_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtsepi32_epi8&expand=5236)
* [x] [`_mm512_maskz_cvtsepi64_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtsepi64_epi16&expand=5236)
* [x] [`_mm512_maskz_cvtsepi64_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtsepi64_epi32&expand=5236)
* [x] [`_mm512_maskz_cvtsepi64_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtsepi64_epi8&expand=5236)
* [x] [`_mm512_maskz_cvtt_roundpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtt_roundpd_epi32&expand=5236)
* [x] [`_mm512_maskz_cvtt_roundpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtt_roundpd_epu32&expand=5236)
* [x] [`_mm512_maskz_cvtt_roundps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtt_roundps_epi32&expand=5236)
* [x] [`_mm512_maskz_cvtt_roundps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtt_roundps_epu32&expand=5236)
* [x] [`_mm512_maskz_cvttpd_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvttpd_epi32&expand=5236)
* [x] [`_mm512_maskz_cvttpd_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvttpd_epu32&expand=5236)
* [x] [`_mm512_maskz_cvttps_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvttps_epi32&expand=5236)
* [x] [`_mm512_maskz_cvttps_epu32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvttps_epu32&expand=5236)
* [x] [`_mm512_maskz_cvtusepi32_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtusepi32_epi16&expand=5236)
* [x] [`_mm512_maskz_cvtusepi32_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtusepi32_epi8&expand=5236)
* [x] [`_mm512_maskz_cvtusepi64_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtusepi64_epi16&expand=5236)
* [x] [`_mm512_maskz_cvtusepi64_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtusepi64_epi32&expand=5236)
* [x] [`_mm512_maskz_cvtusepi64_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtusepi64_epi8&expand=5236)
* [x] [`_mm512_maskz_expand_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_expand_epi32&expand=5236)
* [x] [`_mm512_maskz_expand_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_expand_epi64&expand=5236)
* [x] [`_mm512_maskz_expand_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_expand_pd&expand=5236)
* [x] [`_mm512_maskz_expand_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_expand_ps&expand=5236)
* [ ] [`_mm512_maskz_expandloadu_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_expandloadu_epi32&expand=5236)
* [ ] [`_mm512_maskz_expandloadu_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_expandloadu_epi64&expand=5236)
* [ ] [`_mm512_maskz_expandloadu_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_expandloadu_pd&expand=5236)
* [ ] [`_mm512_maskz_expandloadu_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_expandloadu_ps&expand=5236)
* [x] [`_mm512_maskz_extractf32x4_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_extractf32x4_ps&expand=5236)
* [x] [`_mm512_maskz_extractf64x4_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_extractf64x4_pd&expand=5236)
* [x] [`_mm512_maskz_extracti32x4_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_extracti32x4_epi32&expand=5236)
* [x] [`_mm512_maskz_extracti64x4_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_extracti64x4_epi64&expand=5236)
* [x] [`_mm512_maskz_insertf32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_insertf32x4&expand=5236)
* [x] [`_mm512_maskz_insertf64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_insertf64x4&expand=5236)
* [x] [`_mm512_maskz_inserti32x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_inserti32x4&expand=5236)
* [x] [`_mm512_maskz_inserti64x4`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_inserti64x4&expand=5236)
* [ ] [`_mm512_maskz_load_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_load_epi32&expand=5236)
* [ ] [`_mm512_maskz_load_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_load_epi64&expand=5236)
* [ ] [`_mm512_maskz_load_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_load_pd&expand=5236)
* [ ] [`_mm512_maskz_load_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_load_ps&expand=5236)
* [ ] [`_mm512_maskz_loadu_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_loadu_epi32&expand=5236)
* [ ] [`_mm512_maskz_loadu_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_loadu_epi64&expand=5236)
* [ ] [`_mm512_maskz_loadu_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_loadu_pd&expand=5236)
* [ ] [`_mm512_maskz_loadu_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_loadu_ps&expand=5236)
* [x] [`_mm512_maskz_compress_epi64`]
* [x] [`_mm_mask_compress_epi64`]
* [x] [`_mm_maskz_compress_epi64`]
* [x] [`_mm256_mask_compress_epi64`]
* [x] [`_mm256_maskz_compress_epi64`]
* [x] [`_mm512_mask_compress_ps`]
* [x] [`_mm512_maskz_compress_ps`]
* [x] [`_mm_mask_compress_ps`]
* [x] [`_mm_maskz_compress_ps`]
* [x] [`_mm256_mask_compress_ps`]
* [x] [`_mm256_maskz_compress_ps`]
* [x] [`_mm512_mask_compress_pd`]
* [x] [`_mm512_maskz_compress_pd`]
* [x] [`_mm_mask_compress_pd`]
* [x] [`_mm_maskz_compress_pd`]
* [x] [`_mm256_mask_compress_pd`]
* [x] [`_mm256_maskz_compress_pd`]
* [ ] [`_mm512_mask_compressstoreu_epi32`] //need i1
* [_] [`_mm_mask_compressstoreu_epi32`] //need i1
* [_] [`_mm256_mask_compressstoreu_epi32`] //need i1
* [ ] [`_mm512_mask_compressstoreu_epi64`] //need i1
* [_] [`_mm_mask_compressstoreu_epi64`] //need i1
* [_] [`_mm256_mask_compressstoreu_epi64`] //need i1
* [ ] [`_mm512_mask_compressstoreu_ps`] //need i1
* [_] [`_mm_mask_compressstoreu_ps`] //need i1
* [_] [`_mm256_mask_compressstoreu_ps`] //need i1
* [ ] [`_mm512_mask_compressstoreu_pd`] //need i1
* [_] [`_mm_mask_compressstoreu_pd`] //need i1
* [_] [`_mm256_mask_compressstoreu_pd`] //need i1
* [x] [`_mm512_mask_expand_epi32`]
* [x] [`_mm512_maskz_expand_epi32`]
* [x] [`_mm_mask_expand_epi32`]
* [x] [`_mm_maskz_expand_epi32`]
* [x] [`_mm256_mask_expand_epi32`]
* [x] [`_mm256_maskz_expand_epi32`]
* [x] [`_mm512_mask_expand_epi64`]
* [x] [`_mm512_maskz_expand_epi64`]
* [x] [`_mm_mask_expand_epi64`]
* [x] [`_mm_maskz_expand_epi64`]
* [x] [`_mm256_mask_expand_epi64`]
* [x] [`_mm256_maskz_expand_epi64`]
* [x] [`_mm512_mask_expand_ps`]
* [x] [`_mm512_maskz_expand_ps`]
* [x] [`_mm_mask_expand_ps`]
* [x] [`_mm_maskz_expand_ps`]
* [x] [`_mm256_mask_expand_ps`]
* [x] [`_mm256_maskz_expand_ps`]
* [x] [`_mm512_mask_expand_pd`]
* [x] [`_mm512_maskz_expand_pd`]
* [x] [`_mm_mask_expand_pd`]
* [x] [`_mm_maskz_expand_pd`]
* [x] [`_mm256_mask_expand_pd`]
* [x] [`_mm256_maskz_expand_pd`]
* [ ] [`_mm512_mask_expandloadu_epi32`] //need i1
* [ ] [`_mm512_maskz_expandloadu_epi32`] //need i1
* [_] [`_mm_mask_expandloadu_epi32`] //need i1
* [_] [`_mm_maskz_expandloadu_epi32`] //need i1
* [_] [`_mm256_mask_expandloadu_epi32`] //need i1
* [_] [`_mm256_maskz_expandloadu_epi32`] //need i1
* [ ] [`_mm512_mask_expandloadu_epi64`] //need i1
* [ ] [`_mm512_maskz_expandloadu_epi64`] //need i1
* [_] [`_mm_mask_expandloadu_epi64`] //need i1
* [_] [`_mm_maskz_expandloadu_epi64`] //need i1
* [_] [`_mm256_mask_expandloadu_epi64`] //need i1
* [_] [`_mm256_maskz_expandloadu_epi64`] //need i1
* [ ] [`_mm512_mask_expandloadu_ps`] //need i1
* [ ] [`_mm512_maskz_expandloadu_ps`] //need i1
* [_] [`_mm_mask_expandloadu_ps`] //need i1
* [_] [`_mm_maskz_expandloadu_ps`] //need i1
* [_] [`_mm256_mask_expandloadu_ps`] //need i1
* [_] [`_mm256_maskz_expandloadu_ps`] //need i1
* [ ] [`_mm512_mask_expandloadu_pd`] //need i1
* [ ] [`_mm512_maskz_expandloadu_pd`] //need i1
* [_] [`_mm_mask_expandloadu_pd`] //need i1
* [_] [`_mm_maskz_expandloadu_pd`] //need i1
* [_] [`_mm256_mask_expandloadu_pd`] //need i1
* [_] [`_mm256_maskz_expandloadu_pd`] //need i1
* [x] [`_mm512_zextpd128_pd512`]
* [x] [`_mm512_zextpd256_pd512`]
* [x] [`_mm512_zextps128_ps512`]
* [x] [`_mm512_zextps256_ps512`]
* [x] [`_mm512_zextsi128_si512`]
* [x] [`_mm512_zextsi256_si512`]
* [x] [`_mm512_undefined_epi32`]
* [x] [`_mm512_undefined_pd`]
* [x] [`_mm512_undefined_ps`]
* [x] [`_mm512_undefined`]
* [ ] [`_mm512_svml_round_pd`] //not in llvm
* [x] [`_mm512_ternarylogic_epi32`]
* [x] [`_mm512_mask_ternarylogic_epi32`]
* [x] [`_mm512_maskz_ternarylogic_epi32`]
* [x] [`_mm_mask_ternarylogic_epi32`]
* [x] [`_mm_maskz_ternarylogic_epi32`]
* [x] [`_mm_ternarylogic_epi32`]
* [x] [`_mm256_mask_ternarylogic_epi32`]
* [x] [`_mm256_maskz_ternarylogic_epi32`]
* [x] [`_mm256_ternarylogic_epi32`]
* [x] [`_mm512_ternarylogic_epi64`]
* [x] [`_mm512_mask_ternarylogic_epi64`]
* [x] [`_mm512_maskz_ternarylogic_epi64`]
* [x] [`_mm_mask_ternarylogic_epi64`]
* [x] [`_mm_maskz_ternarylogic_epi64`]
* [x] [`_mm_ternarylogic_epi64`]
* [x] [`_mm256_mask_ternarylogic_epi64`]
* [x] [`_mm256_maskz_ternarylogic_epi64`]
* [x] [`_mm256_ternarylogic_epi64`]
* [x] [`_mm512_test_epi32_mask`]
* [x] [`_mm512_mask_test_epi32_mask`]
* [x] [`_mm_mask_test_epi32_mask`]
* [x] [`_mm_test_epi32_mask`]
* [x] [`_mm256_mask_test_epi32_mask`]
* [x] [`_mm256_test_epi32_mask`]
* [x] [`_mm512_test_epi64_mask`]
* [x] [`_mm512_mask_test_epi64_mask`]
* [x] [`_mm_mask_test_epi64_mask`]
* [x] [`_mm_test_epi64_mask`]
* [x] [`_mm256_mask_test_epi64_mask`]
* [x] [`_mm256_test_epi64_mask`]
* [x] [`_mm512_testn_epi32_mask`]
* [x] [`_mm512_mask_testn_epi32_mask`]
* [x] [`_mm_mask_testn_epi32_mask`]
* [x] [`_mm_testn_epi32_mask`]
* [x] [`_mm256_mask_testn_epi32_mask`]
* [x] [`_mm256_testn_epi32_mask`]
* [x] [`_mm512_testn_epi64_mask`]
* [x] [`_mm512_mask_testn_epi64_mask`]
* [x] [`_mm_mask_testn_epi64_mask`]
* [x] [`_mm_testn_epi64_mask`]
* [x] [`_mm256_mask_testn_epi64_mask`]
* [x] [`_mm256_testn_epi64_mask`]
* [x] [`_mm512_set1_epi8`]
* [x] [`_mm512_set1_epi16`]
* [x] [`_mm512_set1_epi32`]
* [x] [`_mm512_mask_set1_epi32`]
* [x] [`_mm512_maskz_set1_epi32`]
* [x] [`_mm_mask_set1_epi32`]
* [x] [`_mm_maskz_set1_epi32`]
* [x] [`_mm256_mask_set1_epi32`]
* [x] [`_mm256_maskz_set1_epi32`]
* [x] [`_mm512_set1_epi64`]
* [x] [`_mm512_mask_set1_epi64`]
* [x] [`_mm512_maskz_set1_epi64`]
* [x] [`_mm512_maskz_ternarylogic_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_ternarylogic_epi32&expand=5236)
* [x] [`_mm512_maskz_ternarylogic_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_ternarylogic_epi64&expand=5236)
* [x] [`_mm512_set1_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set1_epi16&expand=5236)
* [x] [`_mm512_set1_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set1_epi32&expand=5236)
* [x] [`_mm512_set1_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set1_epi64&expand=5236)
* [x] [`_mm512_set1_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set1_epi8&expand=5236)
* [x] [`_mm512_set1_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set1_pd&expand=5236)
* [x] [`_mm512_set1_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set1_ps&expand=5236)
* [x] [`_mm512_set4_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set4_epi32&expand=5236)
* [x] [`_mm512_set4_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set4_epi64&expand=5236)
* [x] [`_mm512_set4_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set4_pd&expand=5236)
* [x] [`_mm512_set4_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set4_ps&expand=5236)
* [x] [`_mm512_set_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set_epi16&expand=5236)
* [x] [`_mm512_set_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set_epi32&expand=5236)
* [x] [`_mm512_set_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set_epi64&expand=5236)
* [x] [`_mm512_set_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set_epi8&expand=5236)
* [x] [`_mm512_set_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set_pd&expand=5236)
* [x] [`_mm512_set_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set_ps&expand=5236)
* [x] [`_mm512_setr4_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setr4_epi32&expand=5236)
* [x] [`_mm512_setr4_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setr4_epi64&expand=5236)
* [x] [`_mm512_setr4_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setr4_pd&expand=5236)
* [x] [`_mm512_setr4_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setr4_ps&expand=5236)
* [x] [`_mm_mask_set1_epi64`]
* [x] [`_mm_maskz_set1_epi64`]
* [x] [`_mm256_mask_set1_epi64`]
* [x] [`_mm256_maskz_set1_epi64`]
* [x] [`_mm512_set1_ps`]
* [x] [`_mm512_set1_pd`]
* [x] [`_mm512_set4_epi32`]
* [x] [`_mm512_set4_epi64`]
* [x] [`_mm512_set4_pd`]
* [x] [`_mm512_set4_ps`]
* [x] [`_mm512_set_epi16`]
* [x] [`_mm512_set_epi32`]
* [x] [`_mm512_set_epi64`]
* [x] [`_mm512_set_epi8`]
* [x] [`_mm512_set_pd`]
* [x] [`_mm512_set_ps`]
* [x] [`_mm512_setr4_epi32`]
* [x] [`_mm512_setr4_epi64`]
* [x] [`_mm512_setr4_pd`]
* [x] [`_mm512_setr4_ps`]
* [x] [`_mm512_setr_epi32`]
* [x] [`_mm512_setr_epi64`]
* [x] [`_mm512_setr_pd`]
@ -1915,37 +1783,407 @@
* [x] [`_mm512_setzero_ps`]
* [x] [`_mm512_setzero_si512`]
* [x] [`_mm512_setzero`]
* [x] [`_mm512_store_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_store_epi32&expand=5236)
* [x] [`_mm512_store_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_store_epi64&expand=5236)
* [x] [`_mm512_store_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_store_pd&expand=5236)
* [x] [`_mm512_store_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_store_ps&expand=5236)
* [x] [`_mm512_store_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_store_si512&expand=5236)
* [x] [`_mm512_storeu_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_storeu_pd&expand=5236)
* [x] [`_mm512_storeu_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_storeu_ps&expand=5236)
* [x] [`_mm512_load_epi32`]
* [ ] [`_mm512_mask_load_epi32`] //need i1
* [ ] [`_mm512_maskz_load_epi32`] //need i1
* [x] [`_mm_load_epi32`]
* [_] [`_mm_mask_load_epi32`] //need i1
* [_] [`_mm_maskz_load_epi32`] //need i1
* [x] [`_mm256_load_epi32`]
* [_] [`_mm256_mask_load_epi32`] //need i1
* [_] [`_mm256_maskz_load_epi32`] //need i1
* [x] [`_mm512_load_epi64`]
* [ ] [`_mm512_mask_load_epi64`] //need i1
* [ ] [`_mm512_maskz_load_epi64`] //need i1
* [x] [`_mm_load_epi64`] //need i1
* [_] [`_mm_mask_load_epi64`] //need i1
* [_] [`_mm_maskz_load_epi64`] //need i1
* [x] [`_mm256_load_epi64`] //need i1
* [_] [`_mm256_mask_load_epi64`] //need i1
* [_] [`_mm256_maskz_load_epi64`] //need i1
* [x] [`_mm512_load_ps`]
* [ ] [`_mm512_mask_load_ps`] //need i1
* [ ] [`_mm512_maskz_load_ps`] //need i1
* [_] [`_mm_maskz_load_ps`] //need i
* [_] [`_mm_mask_load_ps`] //need i1
* [_] [`_mm_maskz_load_ps`] //need i1
* [_] [`_mm256_mask_load_ps`] //need i1
* [_] [`_mm256_maskz_load_ps`] //need i1
* [x] [`_mm512_load_pd`]
* [ ] [`_mm512_mask_load_pd`] //need i1
* [ ] [`_mm512_maskz_load_pd`] //need i1
* [_] [`_mm_mask_load_pd`] //need i1
* [_] [`_mm_maskz_load_pd`] //need i1
* [_] [`_mm256_mask_load_pd`] //need i1
* [_] [`_mm256_maskz_load_pd`] //need i1
* [x] [`_mm512_load_si512`]
* [x] [`_mm512_loadu_epi32`]
* [ ] [`_mm512_mask_loadu_epi32`] //need i1
* [x] [`_mm_loadu_epi32`]
* [_] [`_mm_mask_loadu_epi32`] //need i1
* [_] [`_mm_maskz_loadu_epi32`] //need i1
* [ ] [`_mm512_maskz_loadu_epi32`] //need i1
* [x] [`_mm256_loadu_epi32`]
* [_] [`_mm256_mask_loadu_epi32`] //need i1
* [_] [`_mm256_maskz_loadu_epi32`] //need i1
* [x] [`_mm512_loadu_epi64`]
* [ ] [`_mm512_mask_loadu_epi64`] //need i1
* [ ] [`_mm512_maskz_loadu_epi64`] //need i1
* [x] [`_mm_loadu_epi64`]
* [_] [`_mm_mask_loadu_epi64`] //need i1
* [_] [`_mm_maskz_loadu_epi64`] //need i1
* [x] [`_mm256_loadu_epi64`]
* [_] [`_mm256_mask_loadu_epi64`] //need i1
* [_] [`_mm256_maskz_loadu_epi64`] //need i1
* [x] [`_mm512_loadu_ps`]
* [ ] [`_mm512_mask_loadu_ps`] //need i1
* [ ] [`_mm512_maskz_loadu_ps`] //need i1
* [_] [`_mm_mask_loadu_ps`] //need i1
* [_] [`_mm_maskz_loadu_ps`] //need i1
* [_] [`_mm256_mask_loadu_ps`] //need i1
* [_] [`_mm256_maskz_loadu_ps`] //need i1
* [x] [`_mm512_loadu_pd`]
* [ ] [`_mm512_mask_loadu_pd`] //need i1
* [ ] [`_mm512_maskz_loadu_pd`] //need i1
* [_] [`_mm_mask_loadu_pd`] //need i1
* [_] [`_mm_maskz_loadu_pd`] //need i1
* [_] [`_mm256_mask_loadu_pd`] //need i1
* [_] [`_mm256_maskz_loadu_pd`] //need i1
* [x] [`_mm512_loadu_si512`]
* [x] [`_mm512_store_epi32`]
* [ ] [`_mm512_mask_store_epi32`] //need i1
* [_] [`_mm_mask_store_epi32`] //need i1
* [x] [`_mm_store_epi32`]
* [_] [`_mm256_mask_store_epi32`] //need i1
* [x] [`_mm256_store_epi32`]
* [x] [`_mm512_store_epi64`]
* [ ] [`_mm512_mask_store_epi64`] //need i1
* [_] [`_mm_mask_store_epi64`] //need i1
* [x] [`_mm_store_epi64`]
* [_] [`_mm256_mask_store_epi64`] //need i1
* [x] [`_mm256_store_epi64`]
* [x] [`_mm512_store_ps`]
* [ ] [`_mm512_mask_store_ps`] //need i1
* [_] [`_mm_mask_store_ps`] //need i1
* [_] [`_mm256_mask_store_ps`] //need i1
* [x] [`_mm512_store_pd`]
* [ ] [`_mm512_mask_store_pd`] //need i1
* [_] [`_mm_mask_store_pd`] //need i1
* [_] [`_mm256_mask_store_pd`] //need i1
* [x] [`_mm512_store_si512`]
* [x] [`_mm512_storeu_epi32`]
* [ ] [`_mm512_mask_storeu_epi32`] //need i1
* [_] [`_mm_mask_storeu_epi32`] //need i1
* [x] [`_mm_storeu_epi32`]
* [_] [`_mm256_mask_storeu_epi32`] //need i1
* [x] [`_mm256_storeu_epi32`]
* [x] [`_mm512_storeu_epi64`]
* [x] [`_mm512_storeu_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_storeu_si512&expand=5236)
* [ ] [`_mm512_stream_load_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_stream_load_si512&expand=5236)
* [x] [`_mm512_stream_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_stream_pd&expand=5236)
* [x] [`_mm512_stream_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_stream_ps&expand=5236)
* [x] [`_mm512_stream_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_stream_si512&expand=5236)
* [ ] [`_mm512_svml_round_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_svml_round_pd&expand=5236)
* [x] [`_mm512_ternarylogic_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_ternarylogic_epi32&expand=5236)
* [x] [`_mm512_ternarylogic_epi64`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_ternarylogic_epi64&expand=5236)
* [x] [`_mm512_test_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_test_epi32_mask&expand=5236)
* [x] [`_mm512_test_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_test_epi64_mask&expand=5236)
* [x] [`_mm512_testn_epi32_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_testn_epi32_mask&expand=5236)
* [x] [`_mm512_testn_epi64_mask`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_testn_epi64_mask&expand=5236)
* [x] [`_mm512_undefined_epi32`]
* [x] [`_mm512_undefined_pd`]
* [x] [`_mm512_undefined_ps`]
* [x] [`_mm512_undefined`]
* [x] [`_mm512_zextpd128_pd512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextpd128_pd512&expand=5236)
* [x] [`_mm512_zextpd256_pd512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextpd256_pd512&expand=5236)
* [x] [`_mm512_zextps128_ps512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextps128_ps512&expand=5236)
* [x] [`_mm512_zextps256_ps512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextps256_ps512&expand=5236)
* [x] [`_mm512_zextsi128_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextsi128_si512&expand=5236)
* [x] [`_mm512_zextsi256_si512`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextsi256_si512&expand=5236)
* [ ] [`_mm512_mask_storeu_epi64`] //need i1
* [_] [`_mm_mask_storeu_epi64`] //need i1
* [x] [`_mm_storeu_epi64`]
* [_] [`_mm256_mask_storeu_epi64`] //need i1
* [x] [`_mm256_storeu_epi64`]
* [x] [`_mm512_storeu_ps`]
* [ ] [`_mm512_mask_storeu_ps`] //need i1
* [_] [`_mm_mask_storeu_ps`] //need i1
* [_] [`_mm256_mask_storeu_ps`] //need i1
* [x] [`_mm512_storeu_pd`]
* [ ] [`_mm512_mask_storeu_pd`] //need i1
* [_] [`_mm_mask_storeu_pd`] //need i1
* [_] [`_mm256_mask_storeu_pd`] //need i1
* [x] [`_mm512_storeu_si512`]
* [ ] [`_mm512_stream_load_si512`] //stream_load_si256, ... not implment yet
* [x] [`_mm512_stream_pd`]
* [x] [`_mm512_stream_ps`]
* [x] [`_mm512_stream_si512`]
* [x] [`_mm512_castpd128_pd512`]
* [x] [`_mm512_castpd256_pd512`]
* [x] [`_mm512_castpd512_pd128`]
* [x] [`_mm512_castpd512_pd256`]
* [x] [`_mm512_castpd_ps`]
* [x] [`_mm512_castpd_si512`]
* [x] [`_mm512_castps128_ps512`]
* [x] [`_mm512_castps256_ps512`]
* [x] [`_mm512_castps512_ps128`]
* [x] [`_mm512_castps512_ps256`]
* [x] [`_mm512_castps_pd`]
* [x] [`_mm512_castps_si512`]
* [x] [`_mm512_castsi128_si512`]
* [x] [`_mm512_castsi256_si512`]
* [x] [`_mm512_castsi512_pd`]
* [x] [`_mm512_castsi512_ps`]
* [x] [`_mm512_castsi512_si128`]
* [x] [`_mm512_castsi512_si256`]
* [x] [`_mm512_cvt_roundps_ph`]
* [x] [`_mm512_mask_cvt_roundps_ph`]
* [x] [`_mm512_maskz_cvt_roundps_ph`]
* [x] [`_mm_mask_cvt_roundps_ph`]
* [x] [`_mm_maskz_cvt_roundps_ph`]
* [x] [`_mm256_mask_cvt_roundps_ph`]
* [x] [`_mm256_maskz_cvt_roundps_ph`]
* [x] [`_mm512_cvtepi16_epi32`]
* [x] [`_mm512_mask_cvtepi16_epi32`]
* [x] [`_mm512_maskz_cvtepi16_epi32`]
* [x] [`_mm_mask_cvtepi16_epi32`]
* [x] [`_mm_maskz_cvtepi16_epi32`]
* [x] [`_mm256_mask_cvtepi16_epi32`]
* [x] [`_mm256_maskz_cvtepi16_epi32`]
* [x] [`_mm512_cvtepi16_epi64`]
* [x] [`_mm512_mask_cvtepi16_epi64`]
* [x] [`_mm512_maskz_cvtepi16_epi64`]
* [x] [`_mm_mask_cvtepi16_epi64`]
* [x] [`_mm_maskz_cvtepi16_epi64`]
* [x] [`_mm256_mask_cvtepi16_epi64`]
* [x] [`_mm256_maskz_cvtepi16_epi64`]
* [x] [`_mm512_cvtepi32_epi16`]
* [x] [`_mm512_mask_cvtepi32_epi16`]
* [x] [`_mm512_maskz_cvtepi32_epi16`]
* [x] [`_mm512_mask_cvtepi32_storeu_epi16`]
* [x] [`_mm_mask_cvtepi32_storeu_epi16`]
* [x] [`_mm256_mask_cvtepi32_storeu_epi16`]
* [x] [`_mm_cvtepi32_epi16`]
* [x] [`_mm_mask_cvtepi32_epi16`]
* [x] [`_mm_maskz_cvtepi32_epi16`]
* [x] [`_mm256_cvtepi32_epi16`]
* [x] [`_mm256_mask_cvtepi32_epi16`]
* [x] [`_mm256_maskz_cvtepi32_epi16`]
* [x] [`_mm512_cvtepi32_epi64`]
* [x] [`_mm512_mask_cvtepi32_epi64`]
* [x] [`_mm512_maskz_cvtepi32_epi64`]
* [x] [`_mm_mask_cvtepi32_epi64`]
* [x] [`_mm_maskz_cvtepi32_epi64`]
* [x] [`_mm256_mask_cvtepi32_epi64`]
* [x] [`_mm256_maskz_cvtepi32_epi64`]
* [x] [`_mm512_cvtepi32_epi8`]
* [x] [`_mm512_mask_cvtepi32_epi8`]
* [x] [`_mm512_maskz_cvtepi32_epi8`]
* [x] [`_mm512_mask_cvtepi32_storeu_epi8`]
* [x] [`_mm_mask_cvtepi32_storeu_epi8`]
* [x] [`_mm256_mask_cvtepi32_storeu_epi8`]
* [x] [`_mm_cvtepi32_epi8`]
* [x] [`_mm_mask_cvtepi32_epi8`]
* [x] [`_mm_maskz_cvtepi32_epi8`]
* [x] [`_mm256_cvtepi32_epi8`]
* [x] [`_mm256_mask_cvtepi32_epi8`]
* [x] [`_mm256_maskz_cvtepi32_epi8`]
* [x] [`_mm512_cvtepi32_ps`]
* [x] [`_mm512_mask_cvtepi32_ps`]
* [x] [`_mm512_maskz_cvtepi32_ps`]
* [x] [`_mm_mask_cvtepi32_ps`]
* [x] [`_mm_maskz_cvtepi32_ps`]
* [x] [`_mm256_mask_cvtepi32_ps`]
* [x] [`_mm256_maskz_cvtepi32_ps`]
* [x] [`_mm512_cvtepi32_pd`]
* [x] [`_mm512_mask_cvtepi32_pd`]
* [x] [`_mm512_maskz_cvtepi32_pd`]
* [x] [`_mm_mask_cvtepi32_pd`]
* [x] [`_mm_maskz_cvtepi32_pd`]
* [x] [`_mm256_mask_cvtepi32_pd`]
* [x] [`_mm256_maskz_cvtepi32_pd`]
* [x] [`_mm512_cvtepi32lo_pd`]
* [x] [`_mm512_mask_cvtepi32lo_pd`]
* [x] [`_mm512_cvtepi64_epi16`]
* [x] [`_mm512_mask_cvtepi64_epi16`]
* [x] [`_mm512_maskz_cvtepi64_epi16`]
* [x] [`_mm_cvtepi64_epi16`]
* [x] [`_mm_mask_cvtepi64_epi16`]
* [x] [`_mm_maskz_cvtepi64_epi16`]
* [x] [`_mm256_cvtepi64_epi16`]
* [x] [`_mm256_mask_cvtepi64_epi16`]
* [x] [`_mm256_maskz_cvtepi64_epi16`]
* [x] [`_mm512_mask_cvtepi64_storeu_epi16`]
* [x] [`_mm_mask_cvtepi64_storeu_epi16`]
* [x] [`_mm256_mask_cvtepi64_storeu_epi16`]
* [x] [`_mm512_cvtepi64_epi8`]
* [x] [`_mm512_mask_cvtepi64_epi8`]
* [x] [`_mm512_maskz_cvtepi64_epi8`]
* [x] [`_mm_cvtepi64_epi8`]
* [x] [`_mm_mask_cvtepi64_epi8`]
* [x] [`_mm_maskz_cvtepi64_epi8`]
* [x] [`_mm256_cvtepi64_epi8`]
* [x] [`_mm256_mask_cvtepi64_epi8`]
* [x] [`_mm256_maskz_cvtepi64_epi8`]
* [x] [`_mm512_mask_cvtepi64_storeu_epi8`]
* [x] [`_mm_mask_cvtepi64_storeu_epi8`]
* [x] [`_mm256_mask_cvtepi64_storeu_epi8`]
* [x] [`_mm512_cvtepi64_epi32`]
* [x] [`_mm512_mask_cvtepi64_epi32`]
* [x] [`_mm512_maskz_cvtepi64_epi32`]
* [x] [`_mm_cvtepi64_epi32`]
* [x] [`_mm_mask_cvtepi64_epi32`]
* [x] [`_mm_maskz_cvtepi64_epi32`]
* [x] [`_mm256_cvtepi64_epi32`]
* [x] [`_mm256_mask_cvtepi64_epi32`]
* [x] [`_mm256_maskz_cvtepi64_epi32`]
* [x] [`_mm512_mask_cvtepi64_storeu_epi32`]
* [x] [`_mm_mask_cvtepi64_storeu_epi32`]
* [x] [`_mm256_mask_cvtepi64_storeu_epi32`]
* [x] [`_mm512_cvtepi8_epi32`]
* [x] [`_mm512_mask_cvtepi8_epi32`]
* [x] [`_mm512_maskz_cvtepi8_epi32`]
* [x] [`_mm_mask_cvtepi8_epi32`]
* [x] [`_mm_maskz_cvtepi8_epi32`]
* [x] [`_mm256_mask_cvtepi8_epi32`]
* [x] [`_mm256_maskz_cvtepi8_epi32`]
* [x] [`_mm512_mask_cvtsepi64_epi32`]
* [x] [`_mm512_mask_cvtsepi64_epi8`]
* [ ] [`_mm512_mask_cvtsepi64_storeu_epi16`]
* [ ] [`_mm512_mask_cvtsepi64_storeu_epi32`]
* [ ] [`_mm512_mask_cvtsepi64_storeu_epi8`]
* [x] [`_mm512_cvt_roundepi32_ps`]
* [x] [`_mm512_cvt_roundepu32_ps`]
* [x] [`_mm512_cvt_roundpd_epi32`]
* [x] [`_mm512_cvt_roundpd_epu32`]
* [x] [`_mm512_cvt_roundpd_ps`]
* [x] [`_mm512_cvt_roundph_ps`]
* [x] [`_mm512_cvt_roundps_epi32`]
* [x] [`_mm512_cvt_roundps_epu32`]
* [x] [`_mm512_cvt_roundps_pd`]
* [x] [`_mm512_mask_cvtsepi64_epi16`]
* [x] [`_mm512_cvtepi8_epi64`]
* [x] [`_mm512_cvtepu16_epi32`]
* [x] [`_mm512_cvtepu16_epi64`]
* [x] [`_mm512_cvtepu32_epi64`]
* [x] [`_mm512_cvtepu32_pd`]
* [x] [`_mm512_cvtepu32_ps`]
* [x] [`_mm512_cvtepu32lo_pd`]
* [x] [`_mm512_cvtepu8_epi32`]
* [x] [`_mm512_cvtepu8_epi64`]
* [x] [`_mm512_cvtpd_epi32`]
* [x] [`_mm512_cvtpd_epu32`]
* [x] [`_mm512_cvtpd_ps`]
* [x] [`_mm512_cvtpd_pslo`]
* [x] [`_mm512_cvtph_ps`]
* [x] [`_mm512_cvtps_epi32`]
* [x] [`_mm512_cvtps_epu32`]
* [x] [`_mm512_cvtps_pd`]
* [x] [`_mm512_cvtps_ph`]
* [x] [`_mm512_cvtpslo_pd`]
* [x] [`_mm512_cvtsepi32_epi16`]
* [x] [`_mm512_cvtsepi32_epi8`]
* [x] [`_mm512_cvtsepi64_epi16`]
* [x] [`_mm512_cvtsepi64_epi32`]
* [x] [`_mm512_cvtsepi64_epi8`]
* [x] [`_mm512_cvtt_roundpd_epi32`]
* [x] [`_mm512_cvtt_roundpd_epu32`]
* [x] [`_mm512_cvtt_roundps_epi32`]
* [x] [`_mm512_cvtt_roundps_epu32`]
* [x] [`_mm512_cvttpd_epi32`]
* [x] [`_mm512_cvttpd_epu32`]
* [x] [`_mm512_cvttps_epi32`]
* [x] [`_mm512_cvttps_epu32`]
* [x] [`_mm512_cvtusepi32_epi16`]
* [x] [`_mm512_cvtusepi32_epi8`]
* [x] [`_mm512_cvtusepi64_epi16`]
* [x] [`_mm512_cvtusepi64_epi32`]
* [x] [`_mm512_cvtusepi64_epi8`]
* [x] [`_mm512_int2mask`]
* [x] [`_mm512_kand`]
* [x] [`_mm512_kandn`]
* [x] [`_mm512_kmov`]
* [x] [`_mm512_knot`]
* [x] [`_mm512_kor`]
* [x] [`_mm512_kortestc`]
* [ ] [`_mm512_kortestz`]
* [x] [`_mm512_kunpackb`]
* [x] [`_mm512_kxnor`]
* [x] [`_mm512_kxor`]
* [x] [`_mm512_mask2int`]
* [x] [`_mm512_mask_cvt_roundepi32_ps`]
* [x] [`_mm512_mask_cvt_roundepu32_ps`]
* [x] [`_mm512_mask_cvt_roundpd_epi32`]
* [x] [`_mm512_mask_cvt_roundpd_epu32`]
* [x] [`_mm512_mask_cvt_roundpd_ps`]
* [x] [`_mm512_mask_cvt_roundph_ps`]
* [x] [`_mm512_mask_cvt_roundps_epi32`]
* [x] [`_mm512_mask_cvt_roundps_epu32`]
* [x] [`_mm512_mask_cvt_roundps_pd`]
* [x] [`_mm512_mask_cvtepi8_epi64`]
* [x] [`_mm512_mask_cvtepu16_epi32`]
* [x] [`_mm512_mask_cvtepu16_epi64`]
* [x] [`_mm512_mask_cvtepu32_epi64`]
* [x] [`_mm512_mask_cvtepu32_pd`]
* [x] [`_mm512_mask_cvtepu32_ps`]
* [x] [`_mm512_mask_cvtepu32lo_pd`]
* [x] [`_mm512_mask_cvtepu8_epi32`]
* [x] [`_mm512_mask_cvtepu8_epi64`]
* [x] [`_mm512_mask_cvtpd_epi32`]
* [x] [`_mm512_mask_cvtpd_epu32`]
* [x] [`_mm512_mask_cvtpd_ps`]
* [x] [`_mm512_mask_cvtpd_pslo`]
* [x] [`_mm512_mask_cvtph_ps`]
* [x] [`_mm512_mask_cvtps_epi32`]
* [x] [`_mm512_mask_cvtps_epu32`]
* [x] [`_mm512_mask_cvtps_pd`]
* [x] [`_mm512_mask_cvtps_ph`]
* [x] [`_mm512_mask_cvtpslo_pd`]
* [x] [`_mm512_mask_cvtsepi32_epi16`]
* [x] [`_mm512_mask_cvtsepi32_epi8`]
* [ ] [`_mm512_mask_cvtsepi32_storeu_epi16`]
* [ ] [`_mm512_mask_cvtsepi32_storeu_epi8`]
* [x] [`_mm512_mask_cvtt_roundpd_epi32`]
* [x] [`_mm512_mask_cvtt_roundpd_epu32`]
* [x] [`_mm512_mask_cvtt_roundps_epi32`]
* [x] [`_mm512_mask_cvtt_roundps_epu32`]
* [x] [`_mm512_mask_cvttpd_epi32`]
* [x] [`_mm512_mask_cvttpd_epu32`]
* [x] [`_mm512_mask_cvttps_epi32`]
* [x] [`_mm512_mask_cvttps_epu32`]
* [x] [`_mm512_mask_cvtusepi32_epi16`]
* [x] [`_mm512_mask_cvtusepi32_epi8`]
* [ ] [`_mm512_mask_cvtusepi32_storeu_epi16`]
* [ ] [`_mm512_mask_cvtusepi32_storeu_epi8`]
* [x] [`_mm512_mask_cvtusepi64_epi16`]
* [x] [`_mm512_mask_cvtusepi64_epi32`]
* [x] [`_mm512_mask_cvtusepi64_epi8`]
* [ ] [`_mm512_mask_cvtusepi64_storeu_epi16`]
* [ ] [`_mm512_mask_cvtusepi64_storeu_epi32`]
* [ ] [`_mm512_mask_cvtusepi64_storeu_epi8`]
* [x] [`_mm512_maskz_cvt_roundepi32_ps`]
* [x] [`_mm512_maskz_cvt_roundepu32_ps`]
* [x] [`_mm512_maskz_cvt_roundpd_epi32`]
* [x] [`_mm512_maskz_cvt_roundpd_epu32`]
* [x] [`_mm512_maskz_cvt_roundpd_ps`]
* [x] [`_mm512_maskz_cvt_roundph_ps`]
* [x] [`_mm512_maskz_cvt_roundps_epi32`]
* [x] [`_mm512_maskz_cvt_roundps_epu32`]
* [x] [`_mm512_maskz_cvt_roundps_pd`]
* [x] [`_mm512_maskz_cvtepi8_epi64`]
* [x] [`_mm512_maskz_cvtepu16_epi32`]
* [x] [`_mm512_maskz_cvtepu16_epi64`]
* [x] [`_mm512_maskz_cvtepu32_epi64`]
* [x] [`_mm512_maskz_cvtepu32_pd`]
* [x] [`_mm512_maskz_cvtepu32_ps`]
* [x] [`_mm512_maskz_cvtepu8_epi32`]
* [x] [`_mm512_maskz_cvtepu8_epi64`]
* [x] [`_mm512_maskz_cvtpd_epi32`]
* [x] [`_mm512_maskz_cvtpd_epu32`]
* [x] [`_mm512_maskz_cvtpd_ps`]
* [x] [`_mm512_maskz_cvtph_ps`]
* [x] [`_mm512_maskz_cvtps_epi32`]
* [x] [`_mm512_maskz_cvtps_epu32`]
* [x] [`_mm512_maskz_cvtps_pd`]
* [x] [`_mm512_maskz_cvtps_ph`]
* [x] [`_mm512_maskz_cvtsepi32_epi16`]
* [x] [`_mm512_maskz_cvtsepi32_epi8`]
* [x] [`_mm512_maskz_cvtsepi64_epi16`]
* [x] [`_mm512_maskz_cvtsepi64_epi32`]
* [x] [`_mm512_maskz_cvtsepi64_epi8`]
* [x] [`_mm512_maskz_cvtt_roundpd_epi32`]
* [x] [`_mm512_maskz_cvtt_roundpd_epu32`]
* [x] [`_mm512_maskz_cvtt_roundps_epi32`]
* [x] [`_mm512_maskz_cvtt_roundps_epu32`]
* [x] [`_mm512_maskz_cvttpd_epi32`]
* [x] [`_mm512_maskz_cvttpd_epu32`]
* [x] [`_mm512_maskz_cvttps_epi32`]
* [x] [`_mm512_maskz_cvttps_epu32`]
* [x] [`_mm512_maskz_cvtusepi32_epi16`]
* [x] [`_mm512_maskz_cvtusepi32_epi8`]
* [x] [`_mm512_maskz_cvtusepi64_epi16`]
* [x] [`_mm512_maskz_cvtusepi64_epi32`]
* [x] [`_mm512_maskz_cvtusepi64_epi8`]
* [x] [`_mm_add_round_sd`]
* [x] [`_mm_add_round_ss`]
* [x] [`_mm_cmp_round_sd_mask`]

56
library/stdarch/crates/core_arch/src/x86/avx512bf16.rs
View file

@ -356,6 +356,7 @@ mod tests {
let b: __m128 = transmute(b_array);
let c: __m128bh = _mm_cvtne2ps_pbh(a, b);
let result: [u16; 8] = transmute(c.as_u16x8());
#[rustfmt::skip]
let expected_result: [u16; 8] = [
0b1_10000110_0110010,
0b1_10000010_0101000,
@ -373,6 +374,7 @@ mod tests {
unsafe fn test_mm_mask_cvtne2ps_pbh() {
let a_array = [178.125_f32, 10.5_f32, 3.75_f32, 50.25_f32];
let b_array = [-178.125_f32, -10.5_f32, -3.75_f32, -50.25_f32];
#[rustfmt::skip]
let src_array: [u16; 8] = [
0b0_10000110_0110010,
0b0_10000010_0101000,
@ -389,6 +391,7 @@ mod tests {
let k: __mmask8 = 0b1111_1111;
let c: __m128bh = _mm_mask_cvtne2ps_pbh(src, k, a, b);
let result: [u16; 8] = transmute(c.as_u16x8());
#[rustfmt::skip]
let expected_result: [u16; 8] = [
0b1_10000110_0110010,
0b1_10000010_0101000,
@ -416,6 +419,7 @@ mod tests {
let k: __mmask8 = 0b1111_1111;
let c: __m128bh = _mm_maskz_cvtne2ps_pbh(k, a, b);
let result: [u16; 8] = transmute(c.as_u16x8());
#[rustfmt::skip]
let expected_result: [u16; 8] = [
0b1_10000110_0110010,
0b1_10000010_0101000,
@ -430,6 +434,7 @@ mod tests {
let k = 0b0011_1100;
let c = _mm_maskz_cvtne2ps_pbh(k, a, b);
let result: [u16; 8] = transmute(c.as_u16x8());
#[rustfmt::skip]
let expected_result: [u16; 8] = [
0,
0,
@ -445,6 +450,7 @@ mod tests {
#[simd_test(enable = "avx512bf16,avx512vl")]
unsafe fn test_mm256_cvtne2ps_pbh() {
#[rustfmt::skip]
let a_array = [
178.125_f32,
10.5_f32,
@ -469,6 +475,7 @@ mod tests {
let b: __m256 = transmute(b_array);
let c: __m256bh = _mm256_cvtne2ps_pbh(a, b);
let result: [u16; 16] = transmute(c.as_u16x16());
#[rustfmt::skip]
let expected_result: [u16; 16] = [
0b1_10000110_0110010,
0b1_10000010_0101000,
@ -492,6 +499,7 @@ mod tests {
#[simd_test(enable = "avx512bf16,avx512vl")]
unsafe fn test_mm256_mask_cvtne2ps_pbh() {
#[rustfmt::skip]
let a_array = [
178.125_f32,
10.5_f32,
@ -536,6 +544,7 @@ mod tests {
let k: __mmask16 = 0xffff;
let c: __m256bh = _mm256_mask_cvtne2ps_pbh(src, k, a, b);
let result: [u16; 16] = transmute(c.as_u16x16());
#[rustfmt::skip]
let expected_result: [u16; 16] = [
0b1_10000110_0110010,
0b1_10000010_0101000,
@ -564,6 +573,7 @@ mod tests {
#[simd_test(enable = "avx512bf16,avx512vl")]
unsafe fn test_mm256_maskz_cvtne2ps_pbh() {
#[rustfmt::skip]
let a_array = [
178.125_f32,
10.5_f32,
@ -589,6 +599,7 @@ mod tests {
let k: __mmask16 = 0xffff;
let c: __m256bh = _mm256_maskz_cvtne2ps_pbh(k, a, b);
let result: [u16; 16] = transmute(c.as_u16x16());
#[rustfmt::skip]
let expected_result: [u16; 16] = [
0b1_10000110_0110010,
0b1_10000010_0101000,
@ -611,6 +622,7 @@ mod tests {
let k: __mmask16 = 0b0110_1100_0011_0110;
let c: __m256bh = _mm256_maskz_cvtne2ps_pbh(k, a, b);
let result: [u16; 16] = transmute(c.as_u16x16());
#[rustfmt::skip]
let expected_result: [u16; 16] = [
0,
0b1_10000010_0101000,
@ -634,6 +646,7 @@ mod tests {
#[simd_test(enable = "avx512bf16,avx512f")]
unsafe fn test_mm512_cvtne2ps_pbh() {
#[rustfmt::skip]
let a_array = [
178.125_f32,
10.5_f32,
@ -674,6 +687,7 @@ mod tests {
let b: __m512 = transmute(b_array);
let c: __m512bh = _mm512_cvtne2ps_pbh(a, b);
let result: [u16; 32] = transmute(c.as_u16x32());
#[rustfmt::skip]
let expected_result: [u16; 32] = [
0b1_10000110_0110010,
0b1_10000010_0101000,
@ -713,6 +727,7 @@ mod tests {
#[simd_test(enable = "avx512bf16,avx512f")]
unsafe fn test_mm512_mask_cvtne2ps_pbh() {
#[rustfmt::skip]
let a_array = [
178.125_f32,
10.5_f32,
@ -789,6 +804,7 @@ mod tests {
let k: __mmask32 = 0xffffffff;
let c: __m512bh = _mm512_mask_cvtne2ps_pbh(src, k, a, b);
let result: [u16; 32] = transmute(c.as_u16x32());
#[rustfmt::skip]
let expected_result: [u16; 32] = [
0b1_10000110_0110010,
0b1_10000010_0101000,
@ -833,6 +849,7 @@ mod tests {
#[simd_test(enable = "avx512bf16,avx512f")]
unsafe fn test_mm512_maskz_cvtne2ps_pbh() {
#[rustfmt::skip]
let a_array = [
178.125_f32,
10.5_f32,
@ -874,6 +891,7 @@ mod tests {
let k: __mmask32 = 0xffffffff;
let c: __m512bh = _mm512_maskz_cvtne2ps_pbh(k, a, b);
let result: [u16; 32] = transmute(c.as_u16x32());
#[rustfmt::skip]
let expected_result: [u16; 32] = [
0b1_10000110_0110010,
0b1_10000010_0101000,
@ -912,6 +930,7 @@ mod tests {
let k: __mmask32 = 0b1100_1010_1001_0110_1010_0011_0101_0110;
let c: __m512bh = _mm512_maskz_cvtne2ps_pbh(k, a, b);
let result: [u16; 32] = transmute(c.as_u16x32());
#[rustfmt::skip]
let expected_result: [u16; 32] = [
0,
0b1_10000010_0101000,
@ -951,6 +970,7 @@ mod tests {
#[simd_test(enable = "avx512bf16,avx512vl")]
unsafe fn test_mm256_cvtneps_pbh() {
#[rustfmt::skip]
let a_array = [
178.125_f32,
10.5_f32,
@ -964,6 +984,7 @@ mod tests {
let a: __m256 = transmute(a_array);
let c: __m128bh = _mm256_cvtneps_pbh(a);
let result: [u16; 8] = transmute(c.as_u16x8());
#[rustfmt::skip]
let expected_result: [u16; 8] = [
0b0_10000110_0110010,
0b0_10000010_0101000,
@ -979,6 +1000,7 @@ mod tests {
#[simd_test(enable = "avx512bf16,avx512vl")]
unsafe fn test_mm256_mask_cvtneps_pbh() {
#[rustfmt::skip]
let a_array = [
178.125_f32,
10.5_f32,
@ -1004,6 +1026,7 @@ mod tests {
let k: __mmask8 = 0xff;
let b = _mm256_mask_cvtneps_pbh(src, k, a);
let result: [u16; 8] = transmute(b.as_u16x8());
#[rustfmt::skip]
let expected_result: [u16; 8] = [
0b0_10000110_0110010,
0b0_10000010_0101000,
@ -1024,6 +1047,7 @@ mod tests {
#[simd_test(enable = "avx512bf16,avx512vl")]
unsafe fn test_mm256_maskz_cvtneps_pbh() {
#[rustfmt::skip]
let a_array = [
178.125_f32,
10.5_f32,
@ -1038,6 +1062,7 @@ mod tests {
let k: __mmask8 = 0xff;
let b = _mm256_maskz_cvtneps_pbh(k, a);
let result: [u16; 8] = transmute(b.as_u16x8());
#[rustfmt::skip]
let expected_result: [u16; 8] = [
0b0_10000110_0110010,
0b0_10000010_0101000,
@ -1059,6 +1084,7 @@ mod tests {
#[simd_test(enable = "avx512bf16,avx512f")]
unsafe fn test_mm512_cvtneps_pbh() {
#[rustfmt::skip]
let a_array = [
178.125_f32,
10.5_f32,
@ -1080,6 +1106,7 @@ mod tests {
let a: __m512 = transmute(a_array);
let c: __m256bh = _mm512_cvtneps_pbh(a);
let result: [u16; 16] = transmute(c.as_u16x16());
#[rustfmt::skip]
let expected_result: [u16; 16] = [
0b0_10000110_0110010,
0b0_10000010_0101000,
@ -1103,6 +1130,7 @@ mod tests {
#[simd_test(enable = "avx512bf16,avx512f")]
unsafe fn test_mm512_mask_cvtneps_pbh() {
#[rustfmt::skip]
let a_array = [
178.125_f32,
10.5_f32,
@ -1144,6 +1172,7 @@ mod tests {
let k: __mmask16 = 0xffff;
let c: __m256bh = _mm512_mask_cvtneps_pbh(src, k, a);
let result: [u16; 16] = transmute(c.as_u16x16());
#[rustfmt::skip]
let expected_result: [u16; 16] = [
0b0_10000110_0110010,
0b0_10000010_0101000,
@ -1172,6 +1201,7 @@ mod tests {
#[simd_test(enable = "avx512bf16,avx512f")]
unsafe fn test_mm512_maskz_cvtneps_pbh() {
#[rustfmt::skip]
let a_array = [
178.125_f32,
10.5_f32,
@ -1194,6 +1224,7 @@ mod tests {
let k: __mmask16 = 0xffff;
let c: __m256bh = _mm512_maskz_cvtneps_pbh(k, a);
let result: [u16; 16] = transmute(c.as_u16x16());
#[rustfmt::skip]
let expected_result: [u16; 16] = [
0b0_10000110_0110010,
0b0_10000010_0101000,
@ -1216,6 +1247,7 @@ mod tests {
let k: __mmask16 = 0x653a;
let c: __m256bh = _mm512_maskz_cvtneps_pbh(k, a);
let result: [u16; 16] = transmute(c.as_u16x16());
#[rustfmt::skip]
let expected_result: [u16; 16] = [
0,
0b0_10000010_0101000,
@ -1306,6 +1338,7 @@ mod tests {
#[simd_test(enable = "avx512bf16,avx512vl")]
unsafe fn test_mm256_dpbf16_ps() {
#[rustfmt::skip]
let a_array = [
8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32,
];
@ -1314,6 +1347,7 @@ mod tests {
];
let a1: __m256 = transmute(a_array);
let b1: __m256 = transmute(b_array);
#[rustfmt::skip]
let src: __m256 = transmute([
1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32,
]);
@ -1321,6 +1355,7 @@ mod tests {
let b: __m256bh = _mm256_cvtne2ps_pbh(b1, b1);
let c: __m256 = _mm256_dpbf16_ps(src, a, b);
let result: [f32; 8] = transmute(c.as_f32x8());
#[rustfmt::skip]
let expected_result: [f32; 8] = [
-18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32,
];
@ -1329,6 +1364,7 @@ mod tests {
#[simd_test(enable = "avx512bf16,avx512vl")]
unsafe fn test_mm256_mask_dpbf16_ps() {
#[rustfmt::skip]
let a_array = [
8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32,
];
@ -1338,6 +1374,7 @@ mod tests {
let a1: __m256 = transmute(a_array);
let b1: __m256 = transmute(b_array);
let k: __mmask8 = 0x33;
#[rustfmt::skip]
let src: __m256 = transmute([
1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32,
]);
@ -1345,6 +1382,7 @@ mod tests {
let b: __m256bh = _mm256_cvtne2ps_pbh(b1, b1);
let c: __m256 = _mm256_mask_dpbf16_ps(src, k, a, b);
let result: [f32; 8] = transmute(c.as_f32x8());
#[rustfmt::skip]
let expected_result: [f32; 8] = [
-18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32, -18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32,
];
@ -1352,6 +1390,7 @@ mod tests {
let k: __mmask8 = 0xff;
let c: __m256 = _mm256_mask_dpbf16_ps(src, k, a, b);
let result: [f32; 8] = transmute(c.as_f32x8());
#[rustfmt::skip]
let expected_result: [f32; 8] = [
-18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32,
];
@ -1359,6 +1398,7 @@ mod tests {
let k: __mmask8 = 0;
let c: __m256 = _mm256_mask_dpbf16_ps(src, k, a, b);
let result: [f32; 8] = transmute(c.as_f32x8());
#[rustfmt::skip]
let expected_result: [f32; 8] = [
1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32,
];
@ -1367,6 +1407,7 @@ mod tests {
#[simd_test(enable = "avx512bf16,avx512vl")]
unsafe fn test_mm256_maskz_dpbf16_ps() {
#[rustfmt::skip]
let a_array = [
8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32,
];
@ -1376,6 +1417,7 @@ mod tests {
let a1: __m256 = transmute(a_array);
let b1: __m256 = transmute(b_array);
let k: __mmask8 = 0x33;
#[rustfmt::skip]
let src: __m256 = transmute([
1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32,
]);
@ -1383,6 +1425,7 @@ mod tests {
let b: __m256bh = _mm256_cvtne2ps_pbh(b1, b1);
let c: __m256 = _mm256_maskz_dpbf16_ps(k, src, a, b);
let result: [f32; 8] = transmute(c.as_f32x8());
#[rustfmt::skip]
let expected_result: [f32; 8] = [
-18.0_f32, -52.0_f32, 0.0, 0.0, -18.0_f32, -52.0_f32, 0.0, 0.0,
];
@ -1390,6 +1433,7 @@ mod tests {
let k: __mmask8 = 0xff;
let c: __m256 = _mm256_maskz_dpbf16_ps(k, src, a, b);
let result: [f32; 8] = transmute(c.as_f32x8());
#[rustfmt::skip]
let expected_result: [f32; 8] = [
-18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32,
];
@ -1403,6 +1447,7 @@ mod tests {
#[simd_test(enable = "avx512bf16,avx512f")]
unsafe fn test_mm512_dpbf16_ps() {
#[rustfmt::skip]
let a_array = [
8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32,
8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32,
@ -1421,6 +1466,7 @@ mod tests {
let b: __m512bh = _mm512_cvtne2ps_pbh(b1, b1);
let c: __m512 = _mm512_dpbf16_ps(src, a, b);
let result: [f32; 16] = transmute(c.as_f32x16());
#[rustfmt::skip]
let expected_result: [f32; 16] = [
-18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32,
-18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32,
@ -1430,6 +1476,7 @@ mod tests {
#[simd_test(enable = "avx512bf16,avx512f")]
unsafe fn test_mm512_mask_dpbf16_ps() {
#[rustfmt::skip]
let a_array = [
8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32,
8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32,
@ -1441,6 +1488,7 @@ mod tests {
let a1: __m512 = transmute(a_array);
let b1: __m512 = transmute(b_array);
let k: __mmask16 = 0x3333;
#[rustfmt::skip]
let src: __m512 = transmute([
1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32,
2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32,
@ -1449,6 +1497,7 @@ mod tests {
let b: __m512bh = _mm512_cvtne2ps_pbh(b1, b1);
let c: __m512 = _mm512_mask_dpbf16_ps(src, k, a, b);
let result: [f32; 16] = transmute(c.as_f32x16());
#[rustfmt::skip]
let expected_result: [f32; 16] = [
-18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32, -18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32,
-18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32, -18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32,
@ -1457,6 +1506,7 @@ mod tests {
let k: __mmask16 = 0xffff;
let c: __m512 = _mm512_mask_dpbf16_ps(src, k, a, b);
let result: [f32; 16] = transmute(c.as_f32x16());
#[rustfmt::skip]
let expected_result: [f32; 16] = [
-18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32,
-18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32,
@ -1465,6 +1515,7 @@ mod tests {
let k: __mmask16 = 0;
let c: __m512 = _mm512_mask_dpbf16_ps(src, k, a, b);
let result: [f32; 16] = transmute(c.as_f32x16());
#[rustfmt::skip]
let expected_result: [f32; 16] = [
1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32,
2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32,
@ -1474,6 +1525,7 @@ mod tests {
#[simd_test(enable = "avx512bf16,avx512f")]
unsafe fn test_mm512_maskz_dpbf16_ps() {
#[rustfmt::skip]
let a_array = [
8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32,
8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32,
@ -1485,6 +1537,7 @@ mod tests {
let a1: __m512 = transmute(a_array);
let b1: __m512 = transmute(b_array);
let k: __mmask16 = 0x3333;
#[rustfmt::skip]
let src: __m512 = transmute([
1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32,
2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32,
@ -1493,6 +1546,7 @@ mod tests {
let b: __m512bh = _mm512_cvtne2ps_pbh(b1, b1);
let c: __m512 = _mm512_maskz_dpbf16_ps(k, src, a, b);
let result: [f32; 16] = transmute(c.as_f32x16());
#[rustfmt::skip]
let expected_result: [f32; 16] = [
-18.0_f32, -52.0_f32, 0.0, 0.0, -18.0_f32, -52.0_f32, 0.0, 0.0, -18.0_f32, -52.0_f32,
0.0, 0.0, -18.0_f32, -52.0_f32, 0.0, 0.0,
@ -1501,6 +1555,7 @@ mod tests {
let k: __mmask16 = 0xffff;
let c: __m512 = _mm512_maskz_dpbf16_ps(k, src, a, b);
let result: [f32; 16] = transmute(c.as_f32x16());
#[rustfmt::skip]
let expected_result: [f32; 16] = [
-18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32,
-18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32,
@ -1509,6 +1564,7 @@ mod tests {
let k: __mmask16 = 0;
let c: __m512 = _mm512_maskz_dpbf16_ps(k, src, a, b);
let result: [f32; 16] = transmute(c.as_f32x16());
#[rustfmt::skip]
let expected_result: [f32; 16] = [
0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0,
];

4172
library/stdarch/crates/core_arch/src/x86/avx512f.rs
View file

File diff suppressed because it is too large Load diff

831
library/stdarch/crates/core_arch/src/x86_64/avx512f.rs
View file

@ -2668,6 +2668,74 @@ mod tests {
assert_eq_m512i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_ternarylogic_epi64() {
let a = _mm256_set1_epi64x(1 << 2);
let b = _mm256_set1_epi64x(1 << 1);
let c = _mm256_set1_epi64x(1 << 0);
let r = _mm256_ternarylogic_epi64(a, b, c, 8);
let e = _mm256_set1_epi64x(0);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_ternarylogic_epi64() {
let src = _mm256_set1_epi64x(1 << 2);
let a = _mm256_set1_epi64x(1 << 1);
let b = _mm256_set1_epi64x(1 << 0);
let r = _mm256_mask_ternarylogic_epi64(src, 0, a, b, 8);
assert_eq_m256i(r, src);
let r = _mm256_mask_ternarylogic_epi64(src, 0b00001111, a, b, 8);
let e = _mm256_set1_epi64x(0);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_maskz_ternarylogic_epi64() {
let a = _mm256_set1_epi64x(1 << 2);
let b = _mm256_set1_epi64x(1 << 1);
let c = _mm256_set1_epi64x(1 << 0);
let r = _mm256_maskz_ternarylogic_epi64(0, a, b, c, 9);
assert_eq_m256i(r, _mm256_setzero_si256());
let r = _mm256_maskz_ternarylogic_epi64(0b00001111, a, b, c, 8);
let e = _mm256_set1_epi64x(0);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_ternarylogic_epi64() {
let a = _mm_set1_epi64x(1 << 2);
let b = _mm_set1_epi64x(1 << 1);
let c = _mm_set1_epi64x(1 << 0);
let r = _mm_ternarylogic_epi64(a, b, c, 8);
let e = _mm_set1_epi64x(0);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_ternarylogic_epi64() {
let src = _mm_set1_epi64x(1 << 2);
let a = _mm_set1_epi64x(1 << 1);
let b = _mm_set1_epi64x(1 << 0);
let r = _mm_mask_ternarylogic_epi64(src, 0, a, b, 8);
assert_eq_m128i(r, src);
let r = _mm_mask_ternarylogic_epi64(src, 0b00000011, a, b, 8);
let e = _mm_set1_epi64x(0);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_maskz_ternarylogic_epi64() {
let a = _mm_set1_epi64x(1 << 2);
let b = _mm_set1_epi64x(1 << 1);
let c = _mm_set1_epi64x(1 << 0);
let r = _mm_maskz_ternarylogic_epi64(0, a, b, c, 9);
assert_eq_m128i(r, _mm_setzero_si128());
let r = _mm_maskz_ternarylogic_epi64(0b00000011, a, b, c, 8);
let e = _mm_set1_epi64x(0);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_getmant_pd() {
let a = _mm512_set1_pd(10.);
@ -2943,6 +3011,48 @@ mod tests {
assert_eq_m512i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_cvtepi16_epi64() {
let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
let src = _mm256_set1_epi64x(-1);
let r = _mm256_mask_cvtepi16_epi64(src, 0, a);
assert_eq_m256i(r, src);
let r = _mm256_mask_cvtepi16_epi64(src, 0b00001111, a);
let e = _mm256_set_epi64x(12, 13, 14, 15);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_maskz_cvtepi16_epi64() {
let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
let r = _mm256_maskz_cvtepi16_epi64(0, a);
assert_eq_m256i(r, _mm256_setzero_si256());
let r = _mm256_maskz_cvtepi16_epi64(0b00001111, a);
let e = _mm256_set_epi64x(12, 13, 14, 15);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_cvtepi16_epi64() {
let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
let src = _mm_set1_epi64x(-1);
let r = _mm_mask_cvtepi16_epi64(src, 0, a);
assert_eq_m128i(r, src);
let r = _mm_mask_cvtepi16_epi64(src, 0b00000011, a);
let e = _mm_set_epi64x(14, 15);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_maskz_cvtepi16_epi64() {
let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
let r = _mm_maskz_cvtepi16_epi64(0, a);
assert_eq_m128i(r, _mm_setzero_si128());
let r = _mm_maskz_cvtepi16_epi64(0b00000011, a);
let e = _mm_set_epi64x(14, 15);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_cvtepu16_epi64() {
let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
@ -3001,6 +3111,48 @@ mod tests {
assert_eq_m512i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_cvtepi32_epi64() {
let a = _mm_set_epi32(8, 9, 10, 11);
let src = _mm256_set1_epi64x(-1);
let r = _mm256_mask_cvtepi32_epi64(src, 0, a);
assert_eq_m256i(r, src);
let r = _mm256_mask_cvtepi32_epi64(src, 0b00001111, a);
let e = _mm256_set_epi64x(8, 9, 10, 11);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_maskz_cvtepi32_epi64() {
let a = _mm_set_epi32(8, 9, 10, 11);
let r = _mm256_maskz_cvtepi32_epi64(0, a);
assert_eq_m256i(r, _mm256_setzero_si256());
let r = _mm256_maskz_cvtepi32_epi64(0b00001111, a);
let e = _mm256_set_epi64x(8, 9, 10, 11);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_cvtepi32_epi64() {
let a = _mm_set_epi32(8, 9, 10, 11);
let src = _mm_set1_epi64x(0);
let r = _mm_mask_cvtepi32_epi64(src, 0, a);
assert_eq_m128i(r, src);
let r = _mm_mask_cvtepi32_epi64(src, 0b00000011, a);
let e = _mm_set_epi64x(10, 11);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_maskz_cvtepi32_epi64() {
let a = _mm_set_epi32(8, 9, 10, 11);
let r = _mm_maskz_cvtepi32_epi64(0, a);
assert_eq_m128i(r, _mm_setzero_si128());
let r = _mm_maskz_cvtepi32_epi64(0b00000011, a);
let e = _mm_set_epi64x(10, 11);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_cvtepu32_epi64() {
let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
@ -3059,6 +3211,48 @@ mod tests {
assert_eq_m512d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_cvtepi32_pd() {
let a = _mm_set_epi32(12, 13, 14, 15);
let src = _mm256_set1_pd(-1.);
let r = _mm256_mask_cvtepi32_pd(src, 0, a);
assert_eq_m256d(r, src);
let r = _mm256_mask_cvtepi32_pd(src, 0b00001111, a);
let e = _mm256_set_pd(12., 13., 14., 15.);
assert_eq_m256d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_maskz_cvtepi32_pd() {
let a = _mm_set_epi32(12, 13, 14, 15);
let r = _mm256_maskz_cvtepi32_pd(0, a);
assert_eq_m256d(r, _mm256_setzero_pd());
let r = _mm256_maskz_cvtepi32_pd(0b00001111, a);
let e = _mm256_set_pd(12., 13., 14., 15.);
assert_eq_m256d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_cvtepi32_pd() {
let a = _mm_set_epi32(12, 13, 14, 15);
let src = _mm_set1_pd(-1.);
let r = _mm_mask_cvtepi32_pd(src, 0, a);
assert_eq_m128d(r, src);
let r = _mm_mask_cvtepi32_pd(src, 0b00000011, a);
let e = _mm_set_pd(14., 15.);
assert_eq_m128d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_maskz_cvtepi32_pd() {
let a = _mm_set_epi32(12, 13, 14, 15);
let r = _mm_maskz_cvtepi32_pd(0, a);
assert_eq_m128d(r, _mm_setzero_pd());
let r = _mm_maskz_cvtepi32_pd(0b00000011, a);
let e = _mm_set_pd(14., 15.);
assert_eq_m128d(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_cvtepu32_pd() {
let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
@ -3155,6 +3349,64 @@ mod tests {
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_cvtepi64_epi32() {
let a = _mm256_set_epi64x(1, 2, 3, 4);
let r = _mm256_cvtepi64_epi32(a);
let e = _mm_set_epi32(1, 2, 3, 4);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_cvtepi64_epi32() {
let a = _mm256_set_epi64x(1, 2, 3, 4);
let src = _mm_set1_epi32(0);
let r = _mm256_mask_cvtepi64_epi32(src, 0, a);
assert_eq_m128i(r, src);
let r = _mm256_mask_cvtepi64_epi32(src, 0b00001111, a);
let e = _mm_set_epi32(1, 2, 3, 4);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_maskz_cvtepi64_epi32() {
let a = _mm256_set_epi64x(1, 2, 3, 4);
let r = _mm256_maskz_cvtepi64_epi32(0, a);
assert_eq_m128i(r, _mm_setzero_si128());
let r = _mm256_maskz_cvtepi64_epi32(0b00001111, a);
let e = _mm_set_epi32(1, 2, 3, 4);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_cvtepi64_epi32() {
let a = _mm_set_epi64x(3, 4);
let r = _mm_cvtepi64_epi32(a);
let e = _mm_set_epi32(0, 0, 3, 4);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_cvtepi64_epi32() {
let a = _mm_set_epi64x(3, 4);
let src = _mm_set1_epi32(0);
let r = _mm_mask_cvtepi64_epi32(src, 0, a);
assert_eq_m128i(r, src);
let r = _mm_mask_cvtepi64_epi32(src, 0b00000011, a);
let e = _mm_set_epi32(0, 0, 3, 4);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_maskz_cvtepi64_epi32() {
let a = _mm_set_epi64x(3, 4);
let r = _mm_maskz_cvtepi64_epi32(0, a);
assert_eq_m128i(r, _mm_setzero_si128());
let r = _mm_maskz_cvtepi64_epi32(0b00000011, a);
let e = _mm_set_epi32(0, 0, 3, 4);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_cvtepi64_epi16() {
let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
@ -3184,6 +3436,64 @@ mod tests {
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_cvtepi64_epi16() {
let a = _mm256_set_epi64x(12, 13, 14, 15);
let r = _mm256_cvtepi64_epi16(a);
let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_cvtepi64_epi16() {
let a = _mm256_set_epi64x(12, 13, 14, 15);
let src = _mm_set1_epi16(0);
let r = _mm256_mask_cvtepi64_epi16(src, 0, a);
assert_eq_m128i(r, src);
let r = _mm256_mask_cvtepi64_epi16(src, 0b11111111, a);
let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_maskz_cvtepi64_epi16() {
let a = _mm256_set_epi64x(12, 13, 14, 15);
let r = _mm256_maskz_cvtepi64_epi16(0, a);
assert_eq_m128i(r, _mm_setzero_si128());
let r = _mm256_maskz_cvtepi64_epi16(0b11111111, a);
let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_cvtepi64_epi16() {
let a = _mm_set_epi64x(14, 15);
let r = _mm_cvtepi64_epi16(a);
let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_cvtepi64_epi16() {
let a = _mm_set_epi64x(14, 15);
let src = _mm_set1_epi16(0);
let r = _mm_mask_cvtepi64_epi16(src, 0, a);
assert_eq_m128i(r, src);
let r = _mm_mask_cvtepi64_epi16(src, 0b11111111, a);
let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_maskz_cvtepi64_epi16() {
let a = _mm_set_epi64x(14, 15);
let r = _mm_maskz_cvtepi64_epi16(0, a);
assert_eq_m128i(r, _mm_setzero_si128());
let r = _mm_maskz_cvtepi64_epi16(0b11111111, a);
let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_cvtepi64_epi8() {
let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
@ -3213,6 +3523,64 @@ mod tests {
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_cvtepi64_epi8() {
let a = _mm256_set_epi64x(12, 13, 14, 15);
let r = _mm256_cvtepi64_epi8(a);
let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_cvtepi64_epi8() {
let a = _mm256_set_epi64x(12, 13, 14, 15);
let src = _mm_set1_epi8(0);
let r = _mm256_mask_cvtepi64_epi8(src, 0, a);
assert_eq_m128i(r, src);
let r = _mm256_mask_cvtepi64_epi8(src, 0b00001111, a);
let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_maskz_cvtepi64_epi8() {
let a = _mm256_set_epi64x(12, 13, 14, 15);
let r = _mm256_maskz_cvtepi64_epi8(0, a);
assert_eq_m128i(r, _mm_setzero_si128());
let r = _mm256_maskz_cvtepi64_epi8(0b00001111, a);
let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_cvtepi64_epi8() {
let a = _mm_set_epi64x(14, 15);
let r = _mm_cvtepi64_epi8(a);
let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_cvtepi64_epi8() {
let a = _mm_set_epi64x(14, 15);
let src = _mm_set1_epi8(0);
let r = _mm_mask_cvtepi64_epi8(src, 0, a);
assert_eq_m128i(r, src);
let r = _mm_mask_cvtepi64_epi8(src, 0b00000011, a);
let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_maskz_cvtepi64_epi8() {
let a = _mm_set_epi64x(14, 15);
let r = _mm_maskz_cvtepi64_epi8(0, a);
assert_eq_m128i(r, _mm_setzero_si128());
let r = _mm_maskz_cvtepi64_epi8(0b00000011, a);
let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_cvtsepi64_epi32() {
let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
@ -9673,6 +10041,8 @@ mod tests {
unsafe fn test_mm512_mask_compress_epi64() {
let src = _mm512_set1_epi64(200);
let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
let r = _mm512_mask_compress_epi64(src, 0, a);
assert_eq_m512i(r, src);
let r = _mm512_mask_compress_epi64(src, 0b01010101, a);
let e = _mm512_set_epi64(200, 200, 200, 200, 1, 3, 5, 7);
assert_eq_m512i(r, e);
@ -9681,15 +10051,61 @@ mod tests {
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_maskz_compress_epi64() {
let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
let r = _mm512_maskz_compress_epi64(0, a);
assert_eq_m512i(r, _mm512_setzero_si512());
let r = _mm512_maskz_compress_epi64(0b01010101, a);
let e = _mm512_set_epi64(0, 0, 0, 0, 1, 3, 5, 7);
assert_eq_m512i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_compress_epi64() {
let src = _mm256_set1_epi64x(200);
let a = _mm256_set_epi64x(0, 1, 2, 3);
let r = _mm256_mask_compress_epi64(src, 0, a);
assert_eq_m256i(r, src);
let r = _mm256_mask_compress_epi64(src, 0b00000101, a);
let e = _mm256_set_epi64x(200, 200, 1, 3);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_maskz_compress_epi64() {
let a = _mm256_set_epi64x(0, 1, 2, 3);
let r = _mm256_maskz_compress_epi64(0, a);
assert_eq_m256i(r, _mm256_setzero_si256());
let r = _mm256_maskz_compress_epi64(0b00000101, a);
let e = _mm256_set_epi64x(0, 0, 1, 3);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_compress_epi64() {
let src = _mm_set1_epi64x(200);
let a = _mm_set_epi64x(0, 1);
let r = _mm_mask_compress_epi64(src, 0, a);
assert_eq_m128i(r, src);
let r = _mm_mask_compress_epi64(src, 0b00000001, a);
let e = _mm_set_epi64x(200, 1);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_maskz_compress_epi64() {
let a = _mm_set_epi64x(0, 1);
let r = _mm_maskz_compress_epi64(0, a);
assert_eq_m128i(r, _mm_setzero_si128());
let r = _mm_maskz_compress_epi64(0b00000001, a);
let e = _mm_set_epi64x(0, 1);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_mask_compress_pd() {
let src = _mm512_set1_pd(200.);
let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
let r = _mm512_mask_compress_pd(src, 0, a);
assert_eq_m512d(r, src);
let r = _mm512_mask_compress_pd(src, 0b01010101, a);
let e = _mm512_set_pd(200., 200., 200., 200., 1., 3., 5., 7.);
assert_eq_m512d(r, e);
@ -9698,15 +10114,61 @@ mod tests {
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_maskz_compress_pd() {
let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
let r = _mm512_maskz_compress_pd(0, a);
assert_eq_m512d(r, _mm512_setzero_pd());
let r = _mm512_maskz_compress_pd(0b01010101, a);
let e = _mm512_set_pd(0., 0., 0., 0., 1., 3., 5., 7.);
assert_eq_m512d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_compress_pd() {
let src = _mm256_set1_pd(200.);
let a = _mm256_set_pd(0., 1., 2., 3.);
let r = _mm256_mask_compress_pd(src, 0, a);
assert_eq_m256d(r, src);
let r = _mm256_mask_compress_pd(src, 0b00000101, a);
let e = _mm256_set_pd(200., 200., 1., 3.);
assert_eq_m256d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_maskz_compress_pd() {
let a = _mm256_set_pd(0., 1., 2., 3.);
let r = _mm256_maskz_compress_pd(0, a);
assert_eq_m256d(r, _mm256_setzero_pd());
let r = _mm256_maskz_compress_pd(0b00000101, a);
let e = _mm256_set_pd(0., 0., 1., 3.);
assert_eq_m256d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_compress_pd() {
let src = _mm_set1_pd(200.);
let a = _mm_set_pd(0., 1.);
let r = _mm_mask_compress_pd(src, 0, a);
assert_eq_m128d(r, src);
let r = _mm_mask_compress_pd(src, 0b00000001, a);
let e = _mm_set_pd(200., 1.);
assert_eq_m128d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_maskz_compress_pd() {
let a = _mm_set_pd(0., 1.);
let r = _mm_maskz_compress_pd(0, a);
assert_eq_m128d(r, _mm_setzero_pd());
let r = _mm_maskz_compress_pd(0b00000001, a);
let e = _mm_set_pd(0., 1.);
assert_eq_m128d(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_mask_expand_epi64() {
let src = _mm512_set1_epi64(200);
let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
let r = _mm512_mask_expand_epi64(src, 0, a);
assert_eq_m512i(r, src);
let r = _mm512_mask_expand_epi64(src, 0b01010101, a);
let e = _mm512_set_epi64(200, 4, 200, 5, 200, 6, 200, 7);
assert_eq_m512i(r, e);
@ -9715,15 +10177,61 @@ mod tests {
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_maskz_expand_epi64() {
let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
let r = _mm512_maskz_expand_epi64(0, a);
assert_eq_m512i(r, _mm512_setzero_si512());
let r = _mm512_maskz_expand_epi64(0b01010101, a);
let e = _mm512_set_epi64(0, 4, 0, 5, 0, 6, 0, 7);
assert_eq_m512i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_expand_epi64() {
let src = _mm256_set1_epi64x(200);
let a = _mm256_set_epi64x(0, 1, 2, 3);
let r = _mm256_mask_expand_epi64(src, 0, a);
assert_eq_m256i(r, src);
let r = _mm256_mask_expand_epi64(src, 0b00000101, a);
let e = _mm256_set_epi64x(200, 2, 200, 3);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_maskz_expand_epi64() {
let a = _mm256_set_epi64x(0, 1, 2, 3);
let r = _mm256_maskz_expand_epi64(0, a);
assert_eq_m256i(r, _mm256_setzero_si256());
let r = _mm256_maskz_expand_epi64(0b00000101, a);
let e = _mm256_set_epi64x(0, 2, 0, 3);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_expand_epi64() {
let src = _mm_set1_epi64x(200);
let a = _mm_set_epi64x(0, 1);
let r = _mm_mask_expand_epi64(src, 0, a);
assert_eq_m128i(r, src);
let r = _mm_mask_expand_epi64(src, 0b00000001, a);
let e = _mm_set_epi64x(200, 1);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_maskz_expand_epi64() {
let a = _mm_set_epi64x(0, 1);
let r = _mm_maskz_expand_epi64(0, a);
assert_eq_m128i(r, _mm_setzero_si128());
let r = _mm_maskz_expand_epi64(0b00000001, a);
let e = _mm_set_epi64x(0, 1);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_mask_expand_pd() {
let src = _mm512_set1_pd(200.);
let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
let r = _mm512_mask_expand_pd(src, 0, a);
assert_eq_m512d(r, src);
let r = _mm512_mask_expand_pd(src, 0b01010101, a);
let e = _mm512_set_pd(200., 4., 200., 5., 200., 6., 200., 7.);
assert_eq_m512d(r, e);
@ -9732,11 +10240,55 @@ mod tests {
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_maskz_expand_pd() {
let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
let r = _mm512_maskz_expand_pd(0, a);
assert_eq_m512d(r, _mm512_setzero_pd());
let r = _mm512_maskz_expand_pd(0b01010101, a);
let e = _mm512_set_pd(0., 4., 0., 5., 0., 6., 0., 7.);
assert_eq_m512d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_expand_pd() {
let src = _mm256_set1_pd(200.);
let a = _mm256_set_pd(0., 1., 2., 3.);
let r = _mm256_mask_expand_pd(src, 0, a);
assert_eq_m256d(r, src);
let r = _mm256_mask_expand_pd(src, 0b00000101, a);
let e = _mm256_set_pd(200., 2., 200., 3.);
assert_eq_m256d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_maskz_expand_pd() {
let a = _mm256_set_pd(0., 1., 2., 3.);
let r = _mm256_maskz_expand_pd(0, a);
assert_eq_m256d(r, _mm256_setzero_pd());
let r = _mm256_maskz_expand_pd(0b00000101, a);
let e = _mm256_set_pd(0., 2., 0., 3.);
assert_eq_m256d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_expand_pd() {
let src = _mm_set1_pd(200.);
let a = _mm_set_pd(0., 1.);
let r = _mm_mask_expand_pd(src, 0, a);
assert_eq_m128d(r, src);
let r = _mm_mask_expand_pd(src, 0b00000001, a);
let e = _mm_set_pd(200., 1.);
assert_eq_m128d(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_maskz_expand_pd() {
let a = _mm_set_pd(0., 1.);
let r = _mm_maskz_expand_pd(0, a);
assert_eq_m128d(r, _mm_setzero_pd());
let r = _mm_maskz_expand_pd(0b00000001, a);
let e = _mm_set_pd(0., 1.);
assert_eq_m128d(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_loadu_epi64() {
let a = &[4, 3, 2, 5, -8, -9, -64, -50];
@ -9746,6 +10298,105 @@ mod tests {
assert_eq_m512i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_loadu_epi64() {
let a = &[4, 3, 2, 5];
let p = a.as_ptr();
let r = _mm256_loadu_epi64(black_box(p));
let e = _mm256_setr_epi64x(4, 3, 2, 5);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_loadu_epi64() {
let a = &[4, 3];
let p = a.as_ptr();
let r = _mm_loadu_epi64(black_box(p));
let e = _mm_setr_epi64x(4, 3);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_mask_cvtepi64_storeu_epi16() {
let a = _mm512_set1_epi64(9);
let mut r = _mm_undefined_si128();
_mm512_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
let e = _mm_set1_epi16(9);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_cvtepi64_storeu_epi16() {
let a = _mm256_set1_epi32(9);
let mut r = _mm_set1_epi16(0);
_mm256_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
let e = _mm_set_epi16(0, 0, 0, 0, 9, 9, 9, 9);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_cvtepi64_storeu_epi16() {
let a = _mm_set1_epi32(9);
let mut r = _mm_set1_epi16(0);
_mm_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 9, 9);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_mask_cvtepi64_storeu_epi8() {
let a = _mm512_set1_epi64(9);
let mut r = _mm_set1_epi8(0);
_mm512_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 9, 9, 9, 9);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_cvtepi64_storeu_epi8() {
let a = _mm256_set1_epi32(9);
let mut r = _mm_set1_epi8(0);
_mm256_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_cvtepi64_storeu_epi8() {
let a = _mm_set1_epi32(9);
let mut r = _mm_set1_epi8(0);
_mm_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_mask_cvtepi64_storeu_epi32() {
let a = _mm512_set1_epi64(9);
let mut r = _mm256_undefined_si256();
_mm512_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
let e = _mm256_set1_epi32(9);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_cvtepi64_storeu_epi32() {
let a = _mm256_set1_epi32(9);
let mut r = _mm_set1_epi32(0);
_mm256_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
let e = _mm_set_epi32(9, 9, 9, 9);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_cvtepi64_storeu_epi32() {
let a = _mm_set1_epi32(9);
let mut r = _mm_set1_epi16(0);
_mm_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
let e = _mm_set_epi32(0, 0, 9, 9);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_storeu_epi64() {
let a = _mm512_set1_epi64(9);
@ -9754,6 +10405,22 @@ mod tests {
assert_eq_m512i(r, a);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_storeu_epi64() {
let a = _mm256_set1_epi64x(9);
let mut r = _mm256_set1_epi64x(0);
_mm256_storeu_epi64(&mut r as *mut _ as *mut i64, a);
assert_eq_m256i(r, a);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_storeu_epi64() {
let a = _mm_set1_epi64x(9);
let mut r = _mm_set1_epi64x(0);
_mm_storeu_epi64(&mut r as *mut _ as *mut i64, a);
assert_eq_m128i(r, a);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_load_epi64() {
#[repr(align(64))]
@ -9769,6 +10436,32 @@ mod tests {
assert_eq_m512i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_load_epi64() {
#[repr(align(64))]
struct Align {
data: [i64; 4],
}
let a = Align { data: [4, 3, 2, 5] };
let p = (a.data).as_ptr();
let r = _mm256_load_epi64(black_box(p));
let e = _mm256_set_epi64x(5, 2, 3, 4);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_load_epi64() {
#[repr(align(64))]
struct Align {
data: [i64; 2],
}
let a = Align { data: [4, 3] };
let p = (a.data).as_ptr();
let r = _mm_load_epi64(black_box(p));
let e = _mm_set_epi64x(3, 4);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_store_epi64() {
let a = _mm512_set1_epi64(9);
@ -9777,6 +10470,22 @@ mod tests {
assert_eq_m512i(r, a);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_store_epi64() {
let a = _mm256_set1_epi64x(9);
let mut r = _mm256_set1_epi64x(0);
_mm256_store_epi64(&mut r as *mut _ as *mut i64, a);
assert_eq_m256i(r, a);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_store_epi64() {
let a = _mm_set1_epi64x(9);
let mut r = _mm_set1_epi64x(0);
_mm_store_epi64(&mut r as *mut _ as *mut i64, a);
assert_eq_m128i(r, a);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_load_pd() {
#[repr(align(64))]
@ -9820,6 +10529,46 @@ mod tests {
assert_eq!(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_test_epi64_mask() {
let a = _mm256_set1_epi64x(1 << 0);
let b = _mm256_set1_epi64x(1 << 0 | 1 << 1);
let r = _mm256_test_epi64_mask(a, b);
let e: __mmask8 = 0b00001111;
assert_eq!(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_test_epi64_mask() {
let a = _mm256_set1_epi64x(1 << 0);
let b = _mm256_set1_epi64x(1 << 0 | 1 << 1);
let r = _mm256_mask_test_epi64_mask(0, a, b);
assert_eq!(r, 0);
let r = _mm256_mask_test_epi64_mask(0b00001111, a, b);
let e: __mmask8 = 0b00001111;
assert_eq!(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_test_epi64_mask() {
let a = _mm_set1_epi64x(1 << 0);
let b = _mm_set1_epi64x(1 << 0 | 1 << 1);
let r = _mm_test_epi64_mask(a, b);
let e: __mmask8 = 0b00000011;
assert_eq!(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_test_epi64_mask() {
let a = _mm_set1_epi64x(1 << 0);
let b = _mm_set1_epi64x(1 << 0 | 1 << 1);
let r = _mm_mask_test_epi64_mask(0, a, b);
assert_eq!(r, 0);
let r = _mm_mask_test_epi64_mask(0b00000011, a, b);
let e: __mmask8 = 0b00000011;
assert_eq!(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_testn_epi64_mask() {
let a = _mm512_set1_epi64(1 << 0);
@ -9840,6 +10589,46 @@ mod tests {
assert_eq!(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_testn_epi64_mask() {
let a = _mm256_set1_epi64x(1 << 0);
let b = _mm256_set1_epi64x(1 << 1);
let r = _mm256_testn_epi64_mask(a, b);
let e: __mmask8 = 0b00001111;
assert_eq!(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_testn_epi64_mask() {
let a = _mm256_set1_epi64x(1 << 0);
let b = _mm256_set1_epi64x(1 << 1);
let r = _mm256_mask_testn_epi64_mask(0, a, b);
assert_eq!(r, 0);
let r = _mm256_mask_testn_epi64_mask(0b11111111, a, b);
let e: __mmask8 = 0b00001111;
assert_eq!(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_testn_epi64_mask() {
let a = _mm_set1_epi64x(1 << 0);
let b = _mm_set1_epi64x(1 << 1);
let r = _mm_testn_epi64_mask(a, b);
let e: __mmask8 = 0b00000011;
assert_eq!(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_testn_epi64_mask() {
let a = _mm_set1_epi64x(1 << 0);
let b = _mm_set1_epi64x(1 << 1);
let r = _mm_mask_testn_epi64_mask(0, a, b);
assert_eq!(r, 0);
let r = _mm_mask_testn_epi64_mask(0b11111111, a, b);
let e: __mmask8 = 0b00000011;
assert_eq!(r, e);
}
#[simd_test(enable = "avx512f")]
unsafe fn test_mm512_stream_pd() {
#[repr(align(64))]
@ -9890,4 +10679,46 @@ mod tests {
let e = _mm512_set1_epi64(11);
assert_eq_m512i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_mask_set1_epi64() {
let src = _mm256_set1_epi64x(2);
let a: i64 = 11;
let r = _mm256_mask_set1_epi64(src, 0, a);
assert_eq_m256i(r, src);
let r = _mm256_mask_set1_epi64(src, 0b00001111, a);
let e = _mm256_set1_epi64x(11);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm256_maskz_set1_epi64() {
let a: i64 = 11;
let r = _mm256_maskz_set1_epi64(0, a);
assert_eq_m256i(r, _mm256_setzero_si256());
let r = _mm256_maskz_set1_epi64(0b00001111, a);
let e = _mm256_set1_epi64x(11);
assert_eq_m256i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_mask_set1_epi64() {
let src = _mm_set1_epi64x(2);
let a: i64 = 11;
let r = _mm_mask_set1_epi64(src, 0, a);
assert_eq_m128i(r, src);
let r = _mm_mask_set1_epi64(src, 0b00000011, a);
let e = _mm_set1_epi64x(11);
assert_eq_m128i(r, e);
}
#[simd_test(enable = "avx512f,avx512vl")]
unsafe fn test_mm_maskz_set1_epi64() {
let a: i64 = 11;
let r = _mm_maskz_set1_epi64(0, a);
assert_eq_m128i(r, _mm_setzero_si128());
let r = _mm_maskz_set1_epi64(0b00000011, a);
let e = _mm_set1_epi64x(11);
assert_eq_m128i(r, e);
}
}

4
library/stdarch/crates/stdarch-verify/tests/x86-intel.rs
View file

@ -595,6 +595,10 @@ fn matches(rust: &Function, intel: &Intrinsic) -> Result<(), String> {
| "_mm256_setr_epi64x"
| "_mm256_set1_epi64x"
| "_mm512_set1_epi64"
| "_mm256_mask_set1_epi64"
| "_mm256_maskz_set1_epi64"
| "_mm_mask_set1_epi64"
| "_mm_maskz_set1_epi64"
| "_mm512_set4_epi64"
| "_mm512_setr4_epi64"
| "_mm512_set_epi64"