convert _mm512_maskz_slli_epi16 to const generics
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1 changed files with 7 additions and 11 deletions
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@ -5040,16 +5040,12 @@ pub unsafe fn _mm512_mask_slli_epi16<const IMM8: u32>(
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_slli_epi16&expand=5300)
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#[inline]
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#[target_feature(enable = "avx512bw")]
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#[cfg_attr(test, assert_instr(vpsllw, imm8 = 5))]
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#[rustc_args_required_const(2)]
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pub unsafe fn _mm512_maskz_slli_epi16(k: __mmask32, a: __m512i, imm8: u32) -> __m512i {
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#[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn _mm512_maskz_slli_epi16<const IMM8: u32>(k: __mmask32, a: __m512i) -> __m512i {
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static_assert_imm_u8!(IMM8);
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let a = a.as_i16x32();
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macro_rules! call {
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($imm8:expr) => {
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vpslliw(a, $imm8)
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};
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}
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let shf = constify_imm8_sae!(imm8, call);
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let shf = vpslliw(a, IMM8);
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let zero = _mm512_setzero_si512().as_i16x32();
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transmute(simd_select_bitmask(k, shf, zero))
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}
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@ -14490,9 +14486,9 @@ mod tests {
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#[simd_test(enable = "avx512bw")]
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unsafe fn test_mm512_maskz_slli_epi16() {
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let a = _mm512_set1_epi16(1 << 15);
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let r = _mm512_maskz_slli_epi16(0, a, 1);
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let r = _mm512_maskz_slli_epi16::<1>(0, a);
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assert_eq_m512i(r, _mm512_setzero_si512());
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let r = _mm512_maskz_slli_epi16(0b11111111_11111111_11111111_11111111, a, 1);
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let r = _mm512_maskz_slli_epi16::<1>(0b11111111_11111111_11111111_11111111, a);
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let e = _mm512_set1_epi16(0);
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assert_eq_m512i(r, e);
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}
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