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Fix CI

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This commit is contained in:
Amanieu d'Antras 2023-04-08 21:52:09 +02:00
parent acee6b804a
commit c66be336c6
4 changed files with 6 additions and 11 deletions
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2
library/stdarch/crates/core_arch/src/x86/avx.rs
View file

@ -2436,8 +2436,6 @@ pub unsafe fn _mm256_set1_ps(a: f32) -> __m256 {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_set1_epi8)
#[inline]
#[target_feature(enable = "avx")]
#[cfg_attr(test, assert_instr(vpshufb))]
#[cfg_attr(test, assert_instr(vinsertf128))]
// This intrinsic has no corresponding instruction.
#[stable(feature = "simd_x86", since = "1.27.0")]
pub unsafe fn _mm256_set1_epi8(a: i8) -> __m256i {

1
library/stdarch/crates/core_arch/src/x86/avx2.rs
View file

@ -3592,7 +3592,6 @@ pub unsafe fn _mm256_cvtsd_f64(a: __m256d) -> f64 {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtsi256_si32)
#[inline]
#[target_feature(enable = "avx2")]
//#[cfg_attr(test, assert_instr(movd))] FIXME
#[stable(feature = "simd_x86", since = "1.27.0")]
pub unsafe fn _mm256_cvtsi256_si32(a: __m256i) -> i32 {
simd_extract(a.as_i32x8(), 0)

12
library/stdarch/crates/core_arch/src/x86/avx512bw.rs
View file

@ -7386,7 +7386,7 @@ pub unsafe fn _mm_maskz_set1_epi16(k: __mmask8, a: i16) -> __m128i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_set1_epi8&expand=4970)
#[inline]
#[target_feature(enable = "avx512bw")]
#[cfg_attr(test, assert_instr(vpbroadcastb))]
#[cfg_attr(test, assert_instr(vpbroadcast))]
pub unsafe fn _mm512_mask_set1_epi8(src: __m512i, k: __mmask64, a: i8) -> __m512i {
let r = _mm512_set1_epi8(a).as_i8x64();
transmute(simd_select_bitmask(k, r, src.as_i8x64()))
@ -7397,7 +7397,7 @@ pub unsafe fn _mm512_mask_set1_epi8(src: __m512i, k: __mmask64, a: i8) -> __m512
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_set1_epi8&expand=4971)
#[inline]
#[target_feature(enable = "avx512bw")]
#[cfg_attr(test, assert_instr(vpbroadcastb))]
#[cfg_attr(test, assert_instr(vpbroadcast))]
pub unsafe fn _mm512_maskz_set1_epi8(k: __mmask64, a: i8) -> __m512i {
let r = _mm512_set1_epi8(a).as_i8x64();
let zero = _mm512_setzero_si512().as_i8x64();
@ -7409,7 +7409,7 @@ pub unsafe fn _mm512_maskz_set1_epi8(k: __mmask64, a: i8) -> __m512i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_set1_epi8&expand=4967)
#[inline]
#[target_feature(enable = "avx512bw,avx512vl")]
#[cfg_attr(test, assert_instr(vpbroadcastb))]
#[cfg_attr(test, assert_instr(vpbroadcast))]
pub unsafe fn _mm256_mask_set1_epi8(src: __m256i, k: __mmask32, a: i8) -> __m256i {
let r = _mm256_set1_epi8(a).as_i8x32();
transmute(simd_select_bitmask(k, r, src.as_i8x32()))
@ -7420,7 +7420,7 @@ pub unsafe fn _mm256_mask_set1_epi8(src: __m256i, k: __mmask32, a: i8) -> __m256
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_set1_epi8&expand=4968)
#[inline]
#[target_feature(enable = "avx512bw,avx512vl")]
#[cfg_attr(test, assert_instr(vpbroadcastb))]
#[cfg_attr(test, assert_instr(vpbroadcast))]
pub unsafe fn _mm256_maskz_set1_epi8(k: __mmask32, a: i8) -> __m256i {
let r = _mm256_set1_epi8(a).as_i8x32();
let zero = _mm256_setzero_si256().as_i8x32();
@ -7432,7 +7432,7 @@ pub unsafe fn _mm256_maskz_set1_epi8(k: __mmask32, a: i8) -> __m256i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_set1_epi8&expand=4964)
#[inline]
#[target_feature(enable = "avx512bw,avx512vl")]
#[cfg_attr(test, assert_instr(vpbroadcastb))]
#[cfg_attr(test, assert_instr(vpbroadcast))]
pub unsafe fn _mm_mask_set1_epi8(src: __m128i, k: __mmask16, a: i8) -> __m128i {
let r = _mm_set1_epi8(a).as_i8x16();
transmute(simd_select_bitmask(k, r, src.as_i8x16()))
@ -7443,7 +7443,7 @@ pub unsafe fn _mm_mask_set1_epi8(src: __m128i, k: __mmask16, a: i8) -> __m128i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_set1_epi8&expand=4965)
#[inline]
#[target_feature(enable = "avx512bw,avx512vl")]
#[cfg_attr(test, assert_instr(vpbroadcastb))]
#[cfg_attr(test, assert_instr(vpbroadcast))]
pub unsafe fn _mm_maskz_set1_epi8(k: __mmask16, a: i8) -> __m128i {
let r = _mm_set1_epi8(a).as_i8x16();
let zero = _mm_setzero_si128().as_i8x16();

2
library/stdarch/crates/core_arch/src/x86/sse2.rs
View file

@ -949,7 +949,6 @@ pub unsafe fn _mm_cvtps_epi32(a: __m128) -> __m128i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsi32_si128)
#[inline]
#[target_feature(enable = "sse2")]
#[cfg_attr(all(test, target_arch = "x86_64"), assert_instr(movd))]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub unsafe fn _mm_cvtsi32_si128(a: i32) -> __m128i {
transmute(i32x4::new(a, 0, 0, 0))
@ -960,7 +959,6 @@ pub unsafe fn _mm_cvtsi32_si128(a: i32) -> __m128i {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsi128_si32)
#[inline]
#[target_feature(enable = "sse2")]
#[cfg_attr(all(test, not(target_os = "windows")), assert_instr(movd))]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub unsafe fn _mm_cvtsi128_si32(a: __m128i) -> i32 {
simd_extract(a.as_i32x4(), 0)