diff --git a/.gitmodules b/.gitmodules index 8617643a1202..b11b47ec108b 100644 --- a/.gitmodules +++ b/.gitmodules @@ -25,7 +25,7 @@ [submodule "src/llvm-project"] path = src/llvm-project url = https://github.com/rust-lang/llvm-project.git - branch = rustc/21.1-2025-08-01 + branch = rustc/22.1-2026-01-27 shallow = true [submodule "src/doc/embedded-book"] path = src/doc/embedded-book diff --git a/Cargo.lock b/Cargo.lock index c7c95a33bc86..6be4565374af 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -184,9 +184,9 @@ checksum = "7c02d123df017efcdfbd739ef81735b36c5ba83ec3c59c80a9d7ecc718f92e50" [[package]] name = "askama" -version = "0.15.1" +version = "0.15.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "bb7125972258312e79827b60c9eb93938334100245081cf701a2dee981b17427" +checksum = "08e1676b346cadfec169374f949d7490fd80a24193d37d2afce0c047cf695e57" dependencies = [ "askama_macros", "itoa", @@ -197,9 +197,9 @@ dependencies = [ [[package]] name = "askama_derive" -version = "0.15.1" +version = "0.15.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "8ba5e7259a1580c61571e3116ebaaa01e3c001b2132b17c4cc5c70780ca3e994" +checksum = "7661ff56517787343f376f75db037426facd7c8d3049cef8911f1e75016f3a37" dependencies = [ "askama_parser", "basic-toml", @@ -214,18 +214,18 @@ dependencies = [ [[package]] name = "askama_macros" -version = "0.15.1" +version = "0.15.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "236ce20b77cb13506eaf5024899f4af6e12e8825f390bd943c4c37fd8f322e46" +checksum = "713ee4dbfd1eb719c2dab859465b01fa1d21cb566684614a713a6b7a99a4e47b" dependencies = [ "askama_derive", ] [[package]] name = "askama_parser" -version = "0.15.1" +version = "0.15.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f3c63392767bb2df6aa65a6e1e3b80fd89bb7af6d58359b924c0695620f1512e" +checksum = "1d62d674238a526418b30c0def480d5beadb9d8964e7f38d635b03bf639c704c" dependencies = [ "rustc-hash 2.1.1", "serde", diff --git a/compiler/rustc_attr_parsing/src/attributes/allow_unstable.rs b/compiler/rustc_attr_parsing/src/attributes/allow_unstable.rs index 7323db06a8f1..d825d770fa35 100644 --- a/compiler/rustc_attr_parsing/src/attributes/allow_unstable.rs +++ b/compiler/rustc_attr_parsing/src/attributes/allow_unstable.rs @@ -57,7 +57,7 @@ impl CombineAttributeParser for AllowConstFnUnstableParser { const PATH: &[Symbol] = &[sym::rustc_allow_const_fn_unstable]; type Item = Symbol; const CONVERT: ConvertFn = - |items, first_span| AttributeKind::AllowConstFnUnstable(items, first_span); + |items, first_span| AttributeKind::RustcAllowConstFnUnstable(items, first_span); const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[ Allow(Target::Fn), Allow(Target::Method(MethodKind::Inherent)), diff --git a/compiler/rustc_attr_parsing/src/attributes/codegen_attrs.rs b/compiler/rustc_attr_parsing/src/attributes/codegen_attrs.rs index 063fa12d3896..485307622291 100644 --- a/compiler/rustc_attr_parsing/src/attributes/codegen_attrs.rs +++ b/compiler/rustc_attr_parsing/src/attributes/codegen_attrs.rs @@ -181,7 +181,7 @@ impl SingleAttributeParser for ObjcClassParser { cx.emit_err(NullOnObjcClass { span: nv.value_span }); return None; } - Some(AttributeKind::ObjcClass { classname, span: cx.attr_span }) + Some(AttributeKind::RustcObjcClass { classname, span: cx.attr_span }) } } @@ -213,7 +213,7 @@ impl SingleAttributeParser for ObjcSelectorParser { cx.emit_err(NullOnObjcSelector { span: nv.value_span }); return None; } - Some(AttributeKind::ObjcSelector { methname, span: cx.attr_span }) + Some(AttributeKind::RustcObjcSelector { methname, span: cx.attr_span }) } } diff --git a/compiler/rustc_attr_parsing/src/attributes/confusables.rs b/compiler/rustc_attr_parsing/src/attributes/confusables.rs index 0b7ac989346a..1897fed1e250 100644 --- a/compiler/rustc_attr_parsing/src/attributes/confusables.rs +++ b/compiler/rustc_attr_parsing/src/attributes/confusables.rs @@ -43,7 +43,7 @@ impl AttributeParser for ConfusablesParser { return None; } - Some(AttributeKind::Confusables { + Some(AttributeKind::RustcConfusables { symbols: self.confusables, first_span: self.first_span.unwrap(), }) diff --git a/compiler/rustc_attr_parsing/src/attributes/dummy.rs b/compiler/rustc_attr_parsing/src/attributes/dummy.rs index 0a7d95f31799..9f97af48afa0 100644 --- a/compiler/rustc_attr_parsing/src/attributes/dummy.rs +++ b/compiler/rustc_attr_parsing/src/attributes/dummy.rs @@ -16,6 +16,6 @@ impl SingleAttributeParser for DummyParser { const TEMPLATE: AttributeTemplate = template!(Word); // Anything, really fn convert(_: &mut AcceptContext<'_, '_, S>, _: &ArgParser) -> Option { - Some(AttributeKind::Dummy) + Some(AttributeKind::RustcDummy) } } diff --git a/compiler/rustc_attr_parsing/src/attributes/link_attrs.rs b/compiler/rustc_attr_parsing/src/attributes/link_attrs.rs index a636b449ca56..548f53a986b8 100644 --- a/compiler/rustc_attr_parsing/src/attributes/link_attrs.rs +++ b/compiler/rustc_attr_parsing/src/attributes/link_attrs.rs @@ -529,7 +529,7 @@ impl NoArgsAttributeParser for StdInternalSymbolParser { Allow(Target::Static), Allow(Target::ForeignStatic), ]); - const CREATE: fn(Span) -> AttributeKind = AttributeKind::StdInternalSymbol; + const CREATE: fn(Span) -> AttributeKind = AttributeKind::RustcStdInternalSymbol; } pub(crate) struct LinkOrdinalParser; diff --git a/compiler/rustc_attr_parsing/src/attributes/lint_helpers.rs b/compiler/rustc_attr_parsing/src/attributes/lint_helpers.rs index 8ca5f0f7228e..60e83a6083ed 100644 --- a/compiler/rustc_attr_parsing/src/attributes/lint_helpers.rs +++ b/compiler/rustc_attr_parsing/src/attributes/lint_helpers.rs @@ -11,7 +11,7 @@ impl NoArgsAttributeParser for AsPtrParser { Allow(Target::Method(MethodKind::Trait { body: true })), Allow(Target::Method(MethodKind::TraitImpl)), ]); - const CREATE: fn(Span) -> AttributeKind = AttributeKind::AsPtr; + const CREATE: fn(Span) -> AttributeKind = AttributeKind::RustcAsPtr; } pub(crate) struct PubTransparentParser; @@ -23,7 +23,7 @@ impl NoArgsAttributeParser for PubTransparentParser { Allow(Target::Enum), Allow(Target::Union), ]); - const CREATE: fn(Span) -> AttributeKind = AttributeKind::PubTransparent; + const CREATE: fn(Span) -> AttributeKind = AttributeKind::RustcPubTransparent; } pub(crate) struct PassByValueParser; @@ -35,7 +35,7 @@ impl NoArgsAttributeParser for PassByValueParser { Allow(Target::Enum), Allow(Target::TyAlias), ]); - const CREATE: fn(Span) -> AttributeKind = AttributeKind::PassByValue; + const CREATE: fn(Span) -> AttributeKind = AttributeKind::RustcPassByValue; } pub(crate) struct RustcShouldNotBeCalledOnConstItems; diff --git a/compiler/rustc_attr_parsing/src/attributes/stability.rs b/compiler/rustc_attr_parsing/src/attributes/stability.rs index 8d27e2e276dd..1f01cadcb43e 100644 --- a/compiler/rustc_attr_parsing/src/attributes/stability.rs +++ b/compiler/rustc_attr_parsing/src/attributes/stability.rs @@ -173,7 +173,7 @@ impl AttributeParser for BodyStabilityParser { fn finalize(self, _cx: &FinalizeContext<'_, '_, S>) -> Option { let (stability, span) = self.stability?; - Some(AttributeKind::BodyStability { stability, span }) + Some(AttributeKind::RustcBodyStability { stability, span }) } } @@ -185,7 +185,7 @@ impl NoArgsAttributeParser for ConstStabilityIndirectParser { Allow(Target::Fn), Allow(Target::Method(MethodKind::Inherent)), ]); - const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::ConstStabilityIndirect; + const CREATE: fn(Span) -> AttributeKind = |_| AttributeKind::RustcConstStabilityIndirect; } #[derive(Default)] @@ -258,7 +258,7 @@ impl AttributeParser for ConstStabilityParser { let (stability, span) = self.stability?; - Some(AttributeKind::ConstStability { stability, span }) + Some(AttributeKind::RustcConstStability { stability, span }) } } diff --git a/compiler/rustc_attr_parsing/src/attributes/traits.rs b/compiler/rustc_attr_parsing/src/attributes/traits.rs index c0db5b4d442a..bfea02e789a0 100644 --- a/compiler/rustc_attr_parsing/src/attributes/traits.rs +++ b/compiler/rustc_attr_parsing/src/attributes/traits.rs @@ -50,7 +50,11 @@ impl SingleAttributeParser for SkipDuringMethodDispatchParser { cx.duplicate_key(arg.span(), key); } } - Some(AttributeKind::SkipDuringMethodDispatch { array, boxed_slice, span: cx.attr_span }) + Some(AttributeKind::RustcSkipDuringMethodDispatch { + array, + boxed_slice, + span: cx.attr_span, + }) } } @@ -59,7 +63,7 @@ impl NoArgsAttributeParser for ParenSugarParser { const PATH: &[Symbol] = &[sym::rustc_paren_sugar]; const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Trait)]); - const CREATE: fn(Span) -> AttributeKind = AttributeKind::ParenSugar; + const CREATE: fn(Span) -> AttributeKind = AttributeKind::RustcParenSugar; } pub(crate) struct TypeConstParser; @@ -91,7 +95,7 @@ impl NoArgsAttributeParser for DenyExplicitImplParser { const PATH: &[Symbol] = &[sym::rustc_deny_explicit_impl]; const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Trait)]); - const CREATE: fn(Span) -> AttributeKind = AttributeKind::DenyExplicitImpl; + const CREATE: fn(Span) -> AttributeKind = AttributeKind::RustcDenyExplicitImpl; } pub(crate) struct DynIncompatibleTraitParser; @@ -99,7 +103,7 @@ impl NoArgsAttributeParser for DynIncompatibleTraitParser { const PATH: &[Symbol] = &[sym::rustc_dyn_incompatible_trait]; const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Trait)]); - const CREATE: fn(Span) -> AttributeKind = AttributeKind::DynIncompatibleTrait; + const CREATE: fn(Span) -> AttributeKind = AttributeKind::RustcDynIncompatibleTrait; } // Specialization @@ -109,7 +113,7 @@ impl NoArgsAttributeParser for SpecializationTraitParser { const PATH: &[Symbol] = &[sym::rustc_specialization_trait]; const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Trait)]); - const CREATE: fn(Span) -> AttributeKind = AttributeKind::SpecializationTrait; + const CREATE: fn(Span) -> AttributeKind = AttributeKind::RustcSpecializationTrait; } pub(crate) struct UnsafeSpecializationMarkerParser; @@ -117,7 +121,7 @@ impl NoArgsAttributeParser for UnsafeSpecializationMarkerParser { const PATH: &[Symbol] = &[sym::rustc_unsafe_specialization_marker]; const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Trait)]); - const CREATE: fn(Span) -> AttributeKind = AttributeKind::UnsafeSpecializationMarker; + const CREATE: fn(Span) -> AttributeKind = AttributeKind::RustcUnsafeSpecializationMarker; } // Coherence @@ -127,7 +131,7 @@ impl NoArgsAttributeParser for CoinductiveParser { const PATH: &[Symbol] = &[sym::rustc_coinductive]; const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Trait)]); - const CREATE: fn(Span) -> AttributeKind = AttributeKind::Coinductive; + const CREATE: fn(Span) -> AttributeKind = AttributeKind::RustcCoinductive; } pub(crate) struct AllowIncoherentImplParser; @@ -136,7 +140,7 @@ impl NoArgsAttributeParser for AllowIncoherentImplParser { const ON_DUPLICATE: OnDuplicate = OnDuplicate::Error; const ALLOWED_TARGETS: AllowedTargets = AllowedTargets::AllowList(&[Allow(Target::Method(MethodKind::Inherent))]); - const CREATE: fn(Span) -> AttributeKind = AttributeKind::AllowIncoherentImpl; + const CREATE: fn(Span) -> AttributeKind = AttributeKind::RustcAllowIncoherentImpl; } pub(crate) struct FundamentalParser; diff --git a/compiler/rustc_attr_parsing/src/attributes/transparency.rs b/compiler/rustc_attr_parsing/src/attributes/transparency.rs index 5b8b3cd151eb..7fa4487b7c69 100644 --- a/compiler/rustc_attr_parsing/src/attributes/transparency.rs +++ b/compiler/rustc_attr_parsing/src/attributes/transparency.rs @@ -32,6 +32,6 @@ impl SingleAttributeParser for TransparencyParser { } None => None, } - .map(AttributeKind::MacroTransparency) + .map(AttributeKind::RustcMacroTransparency) } } diff --git a/compiler/rustc_attr_parsing/src/target_checking.rs b/compiler/rustc_attr_parsing/src/target_checking.rs index 79aa06e9475c..fb005477f0fa 100644 --- a/compiler/rustc_attr_parsing/src/target_checking.rs +++ b/compiler/rustc_attr_parsing/src/target_checking.rs @@ -205,7 +205,7 @@ pub(crate) fn allowed_targets_applied( ]; const IMPL_LIKE: &[Target] = &[Target::Impl { of_trait: false }, Target::Impl { of_trait: true }]; - const ADT_LIKE: &[Target] = &[Target::Struct, Target::Enum]; + const ADT_LIKE: &[Target] = &[Target::Struct, Target::Enum, Target::Union]; let mut added_fake_targets = Vec::new(); filter_targets( diff --git a/compiler/rustc_borrowck/src/diagnostics/bound_region_errors.rs b/compiler/rustc_borrowck/src/diagnostics/bound_region_errors.rs index 254d28d243ff..6ed07cf9b1c8 100644 --- a/compiler/rustc_borrowck/src/diagnostics/bound_region_errors.rs +++ b/compiler/rustc_borrowck/src/diagnostics/bound_region_errors.rs @@ -169,7 +169,7 @@ pub(crate) trait TypeOpInfo<'tcx> { let placeholder_region = ty::Region::new_placeholder( tcx, - ty::Placeholder::new(adjusted_universe.into(), placeholder.bound), + ty::PlaceholderRegion::new(adjusted_universe.into(), placeholder.bound), ); let error_region = @@ -179,7 +179,7 @@ pub(crate) trait TypeOpInfo<'tcx> { adjusted_universe.map(|adjusted| { ty::Region::new_placeholder( tcx, - ty::Placeholder::new(adjusted.into(), error_placeholder.bound), + ty::PlaceholderRegion::new(adjusted.into(), error_placeholder.bound), ) }) } else { diff --git a/compiler/rustc_borrowck/src/diagnostics/move_errors.rs b/compiler/rustc_borrowck/src/diagnostics/move_errors.rs index f83931d37599..986ade57fb31 100644 --- a/compiler/rustc_borrowck/src/diagnostics/move_errors.rs +++ b/compiler/rustc_borrowck/src/diagnostics/move_errors.rs @@ -1,3 +1,4 @@ +use rustc_abi::FieldIdx; use rustc_data_structures::fx::FxHashSet; use rustc_errors::{Applicability, Diag}; use rustc_hir::intravisit::Visitor; @@ -7,7 +8,7 @@ use rustc_middle::mir::*; use rustc_middle::ty::{self, Ty, TyCtxt}; use rustc_mir_dataflow::move_paths::{LookupResult, MovePathIndex}; use rustc_span::def_id::DefId; -use rustc_span::{BytePos, DUMMY_SP, ExpnKind, MacroKind, Span}; +use rustc_span::{BytePos, ExpnKind, MacroKind, Span}; use rustc_trait_selection::error_reporting::traits::FindExprBySpan; use rustc_trait_selection::infer::InferCtxtExt; use tracing::debug; @@ -472,49 +473,30 @@ impl<'infcx, 'tcx> MirBorrowckCtxt<'_, 'infcx, 'tcx> { if def_id.as_local() == Some(self.mir_def_id()) && let Some(upvar_field) = upvar_field => { - let closure_kind_ty = closure_args.as_closure().kind_ty(); - let closure_kind = match closure_kind_ty.to_opt_closure_kind() { - Some(kind @ (ty::ClosureKind::Fn | ty::ClosureKind::FnMut)) => kind, - Some(ty::ClosureKind::FnOnce) => { - bug!("closure kind does not match first argument type") - } - None => bug!("closure kind not inferred by borrowck"), - }; - let capture_description = - format!("captured variable in an `{closure_kind}` closure"); - - let upvar = &self.upvars[upvar_field.index()]; - let upvar_hir_id = upvar.get_root_variable(); - let upvar_name = upvar.to_string(tcx); - let upvar_span = tcx.hir_span(upvar_hir_id); - - let place_name = self.describe_any_place(move_place.as_ref()); - - let place_description = - if self.is_upvar_field_projection(move_place.as_ref()).is_some() { - format!("{place_name}, a {capture_description}") - } else { - format!("{place_name}, as `{upvar_name}` is a {capture_description}") - }; - - debug!( - "report: closure_kind_ty={:?} closure_kind={:?} place_description={:?}", - closure_kind_ty, closure_kind, place_description, - ); - - let closure_span = tcx.def_span(def_id); - - self.cannot_move_out_of(span, &place_description) - .with_span_label(upvar_span, "captured outer variable") - .with_span_label( - closure_span, - format!("captured by this `{closure_kind}` closure"), - ) - .with_span_help( - self.get_closure_bound_clause_span(*def_id), - "`Fn` and `FnMut` closures require captured values to be able to be \ - consumed multiple times, but `FnOnce` closures may consume them only once", - ) + self.report_closure_move_error( + span, + move_place, + *def_id, + closure_args.as_closure().kind_ty(), + upvar_field, + ty::Asyncness::No, + ) + } + ty::CoroutineClosure(def_id, closure_args) + if def_id.as_local() == Some(self.mir_def_id()) + && let Some(upvar_field) = upvar_field + && self + .get_closure_bound_clause_span(*def_id, ty::Asyncness::Yes) + .is_some() => + { + self.report_closure_move_error( + span, + move_place, + *def_id, + closure_args.as_coroutine_closure().kind_ty(), + upvar_field, + ty::Asyncness::Yes, + ) } _ => { let source = self.borrowed_content_source(deref_base); @@ -563,45 +545,134 @@ impl<'infcx, 'tcx> MirBorrowckCtxt<'_, 'infcx, 'tcx> { err } - fn get_closure_bound_clause_span(&self, def_id: DefId) -> Span { + fn report_closure_move_error( + &self, + span: Span, + move_place: Place<'tcx>, + def_id: DefId, + closure_kind_ty: Ty<'tcx>, + upvar_field: FieldIdx, + asyncness: ty::Asyncness, + ) -> Diag<'infcx> { + let tcx = self.infcx.tcx; + + let closure_kind = match closure_kind_ty.to_opt_closure_kind() { + Some(kind @ (ty::ClosureKind::Fn | ty::ClosureKind::FnMut)) => kind, + Some(ty::ClosureKind::FnOnce) => { + bug!("closure kind does not match first argument type") + } + None => bug!("closure kind not inferred by borrowck"), + }; + + let async_prefix = if asyncness.is_async() { "Async" } else { "" }; + let capture_description = + format!("captured variable in an `{async_prefix}{closure_kind}` closure"); + + let upvar = &self.upvars[upvar_field.index()]; + let upvar_hir_id = upvar.get_root_variable(); + let upvar_name = upvar.to_string(tcx); + let upvar_span = tcx.hir_span(upvar_hir_id); + + let place_name = self.describe_any_place(move_place.as_ref()); + + let place_description = if self.is_upvar_field_projection(move_place.as_ref()).is_some() { + format!("{place_name}, a {capture_description}") + } else { + format!("{place_name}, as `{upvar_name}` is a {capture_description}") + }; + + debug!(?closure_kind_ty, ?closure_kind, ?place_description); + + let closure_span = tcx.def_span(def_id); + + let help_msg = format!( + "`{async_prefix}Fn` and `{async_prefix}FnMut` closures require captured values to \ + be able to be consumed multiple times, but `{async_prefix}FnOnce` closures may \ + consume them only once" + ); + + let mut err = self + .cannot_move_out_of(span, &place_description) + .with_span_label(upvar_span, "captured outer variable") + .with_span_label( + closure_span, + format!("captured by this `{async_prefix}{closure_kind}` closure"), + ); + + if let Some(bound_span) = self.get_closure_bound_clause_span(def_id, asyncness) { + err.span_help(bound_span, help_msg); + } else if !asyncness.is_async() { + // For sync closures, always emit the help message even without a span. + // For async closures, we only enter this branch if we found a valid span + // (due to the match guard), so no fallback is needed. + err.help(help_msg); + } + + err + } + + fn get_closure_bound_clause_span( + &self, + def_id: DefId, + asyncness: ty::Asyncness, + ) -> Option { let tcx = self.infcx.tcx; let typeck_result = tcx.typeck(self.mir_def_id()); // Check whether the closure is an argument to a call, if so, // get the instantiated where-bounds of that call. let closure_hir_id = tcx.local_def_id_to_hir_id(def_id.expect_local()); - let hir::Node::Expr(parent) = tcx.parent_hir_node(closure_hir_id) else { return DUMMY_SP }; + let hir::Node::Expr(parent) = tcx.parent_hir_node(closure_hir_id) else { return None }; let predicates = match parent.kind { hir::ExprKind::Call(callee, _) => { - let Some(ty) = typeck_result.node_type_opt(callee.hir_id) else { return DUMMY_SP }; - let ty::FnDef(fn_def_id, args) = ty.kind() else { return DUMMY_SP }; + let ty = typeck_result.node_type_opt(callee.hir_id)?; + let ty::FnDef(fn_def_id, args) = ty.kind() else { return None }; tcx.predicates_of(fn_def_id).instantiate(tcx, args) } hir::ExprKind::MethodCall(..) => { - let Some((_, method)) = typeck_result.type_dependent_def(parent.hir_id) else { - return DUMMY_SP; - }; + let (_, method) = typeck_result.type_dependent_def(parent.hir_id)?; let args = typeck_result.node_args(parent.hir_id); tcx.predicates_of(method).instantiate(tcx, args) } - _ => return DUMMY_SP, + _ => return None, }; - // Check whether one of the where-bounds requires the closure to impl `Fn[Mut]`. + // Check whether one of the where-bounds requires the closure to impl `Fn[Mut]` + // or `AsyncFn[Mut]`. for (pred, span) in predicates.predicates.iter().zip(predicates.spans.iter()) { - if let Some(clause) = pred.as_trait_clause() - && let ty::Closure(clause_closure_def_id, _) = clause.self_ty().skip_binder().kind() - && *clause_closure_def_id == def_id - && (tcx.lang_items().fn_mut_trait() == Some(clause.def_id()) - || tcx.lang_items().fn_trait() == Some(clause.def_id())) - { - // Found `` - // We point at the `Fn()` or `FnMut()` bound that coerced the closure, which - // could be changed to `FnOnce()` to avoid the move error. - return *span; + let dominated_by_fn_trait = self + .closure_clause_kind(*pred, def_id, asyncness) + .is_some_and(|kind| matches!(kind, ty::ClosureKind::Fn | ty::ClosureKind::FnMut)); + if dominated_by_fn_trait { + // Found `` or + // ``. + // We point at the bound that coerced the closure, which could be changed + // to `FnOnce()` or `AsyncFnOnce()` to avoid the move error. + return Some(*span); } } - DUMMY_SP + None + } + + /// If `pred` is a trait clause binding the closure `def_id` to `Fn`/`FnMut`/`FnOnce` + /// (or their async equivalents based on `asyncness`), returns the corresponding + /// `ClosureKind`. Otherwise returns `None`. + fn closure_clause_kind( + &self, + pred: ty::Clause<'tcx>, + def_id: DefId, + asyncness: ty::Asyncness, + ) -> Option { + let tcx = self.infcx.tcx; + let clause = pred.as_trait_clause()?; + let kind = match asyncness { + ty::Asyncness::Yes => tcx.async_fn_trait_kind_from_def_id(clause.def_id()), + ty::Asyncness::No => tcx.fn_trait_kind_from_def_id(clause.def_id()), + }?; + match clause.self_ty().skip_binder().kind() { + ty::Closure(id, _) | ty::CoroutineClosure(id, _) if *id == def_id => Some(kind), + _ => None, + } } fn add_move_hints(&self, error: GroupedMoveError<'tcx>, err: &mut Diag<'_>, span: Span) { diff --git a/compiler/rustc_borrowck/src/handle_placeholders.rs b/compiler/rustc_borrowck/src/handle_placeholders.rs index 60be521c29af..2a7dc8ba1016 100644 --- a/compiler/rustc_borrowck/src/handle_placeholders.rs +++ b/compiler/rustc_borrowck/src/handle_placeholders.rs @@ -62,57 +62,23 @@ impl scc::Annotations for SccAnnotations<'_, '_, RegionTracker> { } #[derive(Copy, Debug, Clone, PartialEq, Eq)] -enum PlaceholderReachability { - /// This SCC reaches no placeholders. - NoPlaceholders, - /// This SCC reaches at least one placeholder. - Placeholders { - /// The largest-universed placeholder we can reach - max_universe: (UniverseIndex, RegionVid), +struct PlaceholderReachability { + /// The largest-universed placeholder we can reach + max_universe: (UniverseIndex, RegionVid), - /// The placeholder with the smallest ID - min_placeholder: RegionVid, + /// The placeholder with the smallest ID + min_placeholder: RegionVid, - /// The placeholder with the largest ID - max_placeholder: RegionVid, - }, + /// The placeholder with the largest ID + max_placeholder: RegionVid, } impl PlaceholderReachability { /// Merge the reachable placeholders of two graph components. - fn merge(self, other: PlaceholderReachability) -> PlaceholderReachability { - use PlaceholderReachability::*; - match (self, other) { - (NoPlaceholders, NoPlaceholders) => NoPlaceholders, - (NoPlaceholders, p @ Placeholders { .. }) - | (p @ Placeholders { .. }, NoPlaceholders) => p, - ( - Placeholders { - min_placeholder: min_pl, - max_placeholder: max_pl, - max_universe: max_u, - }, - Placeholders { min_placeholder, max_placeholder, max_universe }, - ) => Placeholders { - min_placeholder: min_pl.min(min_placeholder), - max_placeholder: max_pl.max(max_placeholder), - max_universe: max_u.max(max_universe), - }, - } - } - - fn max_universe(&self) -> Option<(UniverseIndex, RegionVid)> { - match self { - Self::NoPlaceholders => None, - Self::Placeholders { max_universe, .. } => Some(*max_universe), - } - } - - /// If we have reached placeholders, determine if they can - /// be named from this universe. - fn can_be_named_by(&self, from: UniverseIndex) -> bool { - self.max_universe() - .is_none_or(|(max_placeholder_universe, _)| from.can_name(max_placeholder_universe)) + fn merge(&mut self, other: &Self) { + self.max_universe = self.max_universe.max(other.max_universe); + self.min_placeholder = self.min_placeholder.min(other.min_placeholder); + self.max_placeholder = self.max_placeholder.max(other.max_placeholder); } } @@ -120,7 +86,7 @@ impl PlaceholderReachability { /// the values of its elements. This annotates a single SCC. #[derive(Copy, Debug, Clone)] pub(crate) struct RegionTracker { - reachable_placeholders: PlaceholderReachability, + reachable_placeholders: Option, /// The largest universe nameable from this SCC. /// It is the smallest nameable universes of all @@ -135,13 +101,13 @@ impl RegionTracker { pub(crate) fn new(rvid: RegionVid, definition: &RegionDefinition<'_>) -> Self { let reachable_placeholders = if matches!(definition.origin, NllRegionVariableOrigin::Placeholder(_)) { - PlaceholderReachability::Placeholders { + Some(PlaceholderReachability { max_universe: (definition.universe, rvid), min_placeholder: rvid, max_placeholder: rvid, - } + }) } else { - PlaceholderReachability::NoPlaceholders + None }; Self { @@ -159,43 +125,46 @@ impl RegionTracker { } pub(crate) fn max_placeholder_universe_reached(self) -> UniverseIndex { - if let Some((universe, _)) = self.reachable_placeholders.max_universe() { - universe - } else { - UniverseIndex::ROOT - } + self.reachable_placeholders.map(|pls| pls.max_universe.0).unwrap_or(UniverseIndex::ROOT) + } + + /// Can all reachable placeholders be named from `from`? + /// True vacuously in case no placeholders were reached. + fn placeholders_can_be_named_by(&self, from: UniverseIndex) -> bool { + self.reachable_placeholders.is_none_or(|pls| from.can_name(pls.max_universe.0)) } /// Determine if we can name all the placeholders in `other`. pub(crate) fn can_name_all_placeholders(&self, other: Self) -> bool { - other.reachable_placeholders.can_be_named_by(self.max_nameable_universe.0) + // HACK: We first check whether we can name the highest existential universe + // of `other`. This only exists to avoid errors in case that scc already + // depends on a placeholder it cannot name itself. + self.max_nameable_universe().can_name(other.max_nameable_universe()) + || other.placeholders_can_be_named_by(self.max_nameable_universe.0) } /// If this SCC reaches a placeholder it can't name, return it. fn unnameable_placeholder(&self) -> Option<(UniverseIndex, RegionVid)> { - self.reachable_placeholders.max_universe().filter(|&(placeholder_universe, _)| { - !self.max_nameable_universe().can_name(placeholder_universe) - }) + self.reachable_placeholders + .filter(|pls| !self.max_nameable_universe().can_name(pls.max_universe.0)) + .map(|pls| pls.max_universe) } } impl scc::Annotation for RegionTracker { - fn merge_scc(self, other: Self) -> Self { + fn update_scc(&mut self, other: &Self) { trace!("{:?} << {:?}", self.representative, other.representative); - - Self { - representative: self.representative.min(other.representative), - max_nameable_universe: self.max_nameable_universe.min(other.max_nameable_universe), - reachable_placeholders: self.reachable_placeholders.merge(other.reachable_placeholders), - } + self.representative = self.representative.min(other.representative); + self.update_reachable(other); } - fn merge_reached(self, other: Self) -> Self { - Self { - max_nameable_universe: self.max_nameable_universe.min(other.max_nameable_universe), - reachable_placeholders: self.reachable_placeholders.merge(other.reachable_placeholders), - representative: self.representative, - } + fn update_reachable(&mut self, other: &Self) { + self.max_nameable_universe = self.max_nameable_universe.min(other.max_nameable_universe); + match (self.reachable_placeholders.as_mut(), other.reachable_placeholders.as_ref()) { + (None, None) | (Some(_), None) => (), + (None, Some(theirs)) => self.reachable_placeholders = Some(*theirs), + (Some(ours), Some(theirs)) => ours.merge(theirs), + }; } } diff --git a/compiler/rustc_borrowck/src/region_infer/graphviz.rs b/compiler/rustc_borrowck/src/region_infer/graphviz.rs index 526e1850c2ef..ceb33d82deba 100644 --- a/compiler/rustc_borrowck/src/region_infer/graphviz.rs +++ b/compiler/rustc_borrowck/src/region_infer/graphviz.rs @@ -52,7 +52,7 @@ fn render_region_vid<'tcx>( format!(" (for<{}>)", tcx.item_name(def_id)) } ty::BoundRegionKind::ClosureEnv | ty::BoundRegionKind::Anon => " (for<'_>)".to_string(), - ty::BoundRegionKind::NamedAnon(_) => { + ty::BoundRegionKind::NamedForPrinting(_) => { bug!("only used for pretty printing") } }, diff --git a/compiler/rustc_borrowck/src/region_infer/values.rs b/compiler/rustc_borrowck/src/region_infer/values.rs index 0063af25d781..1dd3bc831f45 100644 --- a/compiler/rustc_borrowck/src/region_infer/values.rs +++ b/compiler/rustc_borrowck/src/region_infer/values.rs @@ -10,8 +10,8 @@ use rustc_middle::ty::{self, RegionVid}; use rustc_mir_dataflow::points::{DenseLocationMap, PointIndex}; use tracing::debug; +use crate::BorrowIndex; use crate::polonius::LiveLoans; -use crate::{BorrowIndex, TyCtxt}; rustc_index::newtype_index! { /// A single integer representing a `ty::Placeholder`. @@ -420,18 +420,18 @@ impl ToElementIndex<'_> for RegionVid { impl<'tcx> ToElementIndex<'tcx> for ty::PlaceholderRegion<'tcx> { fn add_to_row(self, values: &mut RegionValues<'tcx, N>, row: N) -> bool where - Self: Into, ty::BoundRegion>>, + Self: Into>, { - let placeholder: ty::Placeholder, ty::BoundRegion> = self.into(); + let placeholder: ty::PlaceholderRegion<'tcx> = self.into(); let index = values.placeholder_indices.lookup_index(placeholder); values.placeholders.insert(row, index) } fn contained_in_row(self, values: &RegionValues<'tcx, N>, row: N) -> bool where - Self: Into, ty::BoundRegion>>, + Self: Into>, { - let placeholder: ty::Placeholder, ty::BoundRegion> = self.into(); + let placeholder: ty::PlaceholderRegion<'tcx> = self.into(); let index = values.placeholder_indices.lookup_index(placeholder); values.placeholders.contains(row, index) } diff --git a/compiler/rustc_borrowck/src/type_check/mod.rs b/compiler/rustc_borrowck/src/type_check/mod.rs index 676b45e9974c..98b4e4d81b92 100644 --- a/compiler/rustc_borrowck/src/type_check/mod.rs +++ b/compiler/rustc_borrowck/src/type_check/mod.rs @@ -775,7 +775,7 @@ impl<'a, 'tcx> Visitor<'tcx> for TypeChecker<'a, 'tcx> { ty::BoundRegionKind::Anon => sym::anon, ty::BoundRegionKind::Named(def_id) => tcx.item_name(def_id), ty::BoundRegionKind::ClosureEnv => sym::env, - ty::BoundRegionKind::NamedAnon(_) => { + ty::BoundRegionKind::NamedForPrinting(_) => { bug!("only used for pretty printing") } }; diff --git a/compiler/rustc_borrowck/src/type_check/relate_tys.rs b/compiler/rustc_borrowck/src/type_check/relate_tys.rs index 045507ceb4b4..e2d684e12a81 100644 --- a/compiler/rustc_borrowck/src/type_check/relate_tys.rs +++ b/compiler/rustc_borrowck/src/type_check/relate_tys.rs @@ -174,7 +174,7 @@ impl<'a, 'b, 'tcx> NllTypeRelating<'a, 'b, 'tcx> { let infcx = self.type_checker.infcx; let mut lazy_universe = None; let delegate = FnMutDelegate { - regions: &mut |br: ty::BoundRegion| { + regions: &mut |br: ty::BoundRegion<'tcx>| { // The first time this closure is called, create a // new universe for the placeholders we will make // from here out. @@ -191,10 +191,10 @@ impl<'a, 'b, 'tcx> NllTypeRelating<'a, 'b, 'tcx> { placeholder_reg }, - types: &mut |_bound_ty: ty::BoundTy| { + types: &mut |_bound_ty: ty::BoundTy<'tcx>| { unreachable!("we only replace regions in nll_relate, not types") }, - consts: &mut |_bound_const: ty::BoundConst| { + consts: &mut |_bound_const: ty::BoundConst<'tcx>| { unreachable!("we only replace regions in nll_relate, not consts") }, }; @@ -218,7 +218,7 @@ impl<'a, 'b, 'tcx> NllTypeRelating<'a, 'b, 'tcx> { let infcx = self.type_checker.infcx; let mut reg_map = FxHashMap::default(); let delegate = FnMutDelegate { - regions: &mut |br: ty::BoundRegion| { + regions: &mut |br: ty::BoundRegion<'tcx>| { if let Some(ex_reg_var) = reg_map.get(&br) { *ex_reg_var } else { @@ -230,10 +230,10 @@ impl<'a, 'b, 'tcx> NllTypeRelating<'a, 'b, 'tcx> { ex_reg_var } }, - types: &mut |_bound_ty: ty::BoundTy| { + types: &mut |_bound_ty: ty::BoundTy<'tcx>| { unreachable!("we only replace regions in nll_relate, not types") }, - consts: &mut |_bound_const: ty::BoundConst| { + consts: &mut |_bound_const: ty::BoundConst<'tcx>| { unreachable!("we only replace regions in nll_relate, not consts") }, }; @@ -268,7 +268,7 @@ impl<'a, 'b, 'tcx> NllTypeRelating<'a, 'b, 'tcx> { ty::BoundRegionKind::Anon => sym::anon, ty::BoundRegionKind::Named(def_id) => self.type_checker.tcx().item_name(def_id), ty::BoundRegionKind::ClosureEnv => sym::env, - ty::BoundRegionKind::NamedAnon(_) => bug!("only used for pretty printing"), + ty::BoundRegionKind::NamedForPrinting(_) => bug!("only used for pretty printing"), }; if cfg!(debug_assertions) { diff --git a/compiler/rustc_codegen_llvm/src/builder.rs b/compiler/rustc_codegen_llvm/src/builder.rs index ca4805a93e01..4ffc836f5559 100644 --- a/compiler/rustc_codegen_llvm/src/builder.rs +++ b/compiler/rustc_codegen_llvm/src/builder.rs @@ -188,19 +188,6 @@ impl<'a, 'll, CX: Borrow>> GenericBuilder<'a, 'll, CX> { load } } - - fn memset(&mut self, ptr: &'ll Value, fill_byte: &'ll Value, size: &'ll Value, align: Align) { - unsafe { - llvm::LLVMRustBuildMemSet( - self.llbuilder, - ptr, - align.bytes() as c_uint, - fill_byte, - size, - false, - ); - } - } } /// Empty string, to be used where LLVM expects an instruction name, indicating diff --git a/compiler/rustc_codegen_llvm/src/builder/gpu_offload.rs b/compiler/rustc_codegen_llvm/src/builder/gpu_offload.rs index f1735b9a0f58..402861eda870 100644 --- a/compiler/rustc_codegen_llvm/src/builder/gpu_offload.rs +++ b/compiler/rustc_codegen_llvm/src/builder/gpu_offload.rs @@ -19,8 +19,6 @@ pub(crate) struct OffloadGlobals<'ll> { pub launcher_fn: &'ll llvm::Value, pub launcher_ty: &'ll llvm::Type, - pub bin_desc: &'ll llvm::Type, - pub kernel_args_ty: &'ll llvm::Type, pub offload_entry_ty: &'ll llvm::Type, @@ -31,8 +29,8 @@ pub(crate) struct OffloadGlobals<'ll> { pub ident_t_global: &'ll llvm::Value, - pub register_lib: &'ll llvm::Value, - pub unregister_lib: &'ll llvm::Value, + // FIXME(offload): Drop this, once we fully automated our offload compilation pipeline, since + // LLVM will initialize them for us if it sees gpu kernels being registered. pub init_rtls: &'ll llvm::Value, } @@ -44,15 +42,6 @@ impl<'ll> OffloadGlobals<'ll> { let (begin_mapper, _, end_mapper, mapper_fn_ty) = gen_tgt_data_mappers(cx); let ident_t_global = generate_at_one(cx); - let tptr = cx.type_ptr(); - let ti32 = cx.type_i32(); - let tgt_bin_desc_ty = vec![ti32, tptr, tptr, tptr]; - let bin_desc = cx.type_named_struct("struct.__tgt_bin_desc"); - cx.set_struct_body(bin_desc, &tgt_bin_desc_ty, false); - - let reg_lib_decl = cx.type_func(&[cx.type_ptr()], cx.type_void()); - let register_lib = declare_offload_fn(&cx, "__tgt_register_lib", reg_lib_decl); - let unregister_lib = declare_offload_fn(&cx, "__tgt_unregister_lib", reg_lib_decl); let init_ty = cx.type_func(&[], cx.type_void()); let init_rtls = declare_offload_fn(cx, "__tgt_init_all_rtls", init_ty); @@ -63,20 +52,84 @@ impl<'ll> OffloadGlobals<'ll> { OffloadGlobals { launcher_fn, launcher_ty, - bin_desc, kernel_args_ty, offload_entry_ty, begin_mapper, end_mapper, mapper_fn_ty, ident_t_global, - register_lib, - unregister_lib, init_rtls, } } } +// We need to register offload before using it. We also should unregister it once we are done, for +// good measures. Previously we have done so before and after each individual offload intrinsic +// call, but that comes at a performance cost. The repeated (un)register calls might also confuse +// the LLVM ompOpt pass, which tries to move operations to a better location. The easiest solution, +// which we copy from clang, is to just have those two calls once, in the global ctor/dtor section +// of the final binary. +pub(crate) fn register_offload<'ll>(cx: &CodegenCx<'ll, '_>) { + // First we check quickly whether we already have done our setup, in which case we return early. + // Shouldn't be needed for correctness. + let register_lib_name = "__tgt_register_lib"; + if cx.get_function(register_lib_name).is_some() { + return; + } + + let reg_lib_decl = cx.type_func(&[cx.type_ptr()], cx.type_void()); + let register_lib = declare_offload_fn(&cx, register_lib_name, reg_lib_decl); + let unregister_lib = declare_offload_fn(&cx, "__tgt_unregister_lib", reg_lib_decl); + + let ptr_null = cx.const_null(cx.type_ptr()); + let const_struct = cx.const_struct(&[cx.get_const_i32(0), ptr_null, ptr_null, ptr_null], false); + let omp_descriptor = + add_global(cx, ".omp_offloading.descriptor", const_struct, InternalLinkage); + // @.omp_offloading.descriptor = internal constant %__tgt_bin_desc { i32 1, ptr @.omp_offloading.device_images, ptr @__start_llvm_offload_entries, ptr @__stop_llvm_offload_entries } + // @.omp_offloading.descriptor = internal constant %__tgt_bin_desc { i32 0, ptr null, ptr null, ptr null } + + let atexit = cx.type_func(&[cx.type_ptr()], cx.type_i32()); + let atexit_fn = declare_offload_fn(cx, "atexit", atexit); + + let desc_ty = cx.type_func(&[], cx.type_void()); + let reg_name = ".omp_offloading.descriptor_reg"; + let unreg_name = ".omp_offloading.descriptor_unreg"; + let desc_reg_fn = declare_offload_fn(cx, reg_name, desc_ty); + let desc_unreg_fn = declare_offload_fn(cx, unreg_name, desc_ty); + llvm::set_linkage(desc_reg_fn, InternalLinkage); + llvm::set_linkage(desc_unreg_fn, InternalLinkage); + llvm::set_section(desc_reg_fn, c".text.startup"); + llvm::set_section(desc_unreg_fn, c".text.startup"); + + // define internal void @.omp_offloading.descriptor_reg() section ".text.startup" { + // entry: + // call void @__tgt_register_lib(ptr @.omp_offloading.descriptor) + // %0 = call i32 @atexit(ptr @.omp_offloading.descriptor_unreg) + // ret void + // } + let bb = Builder::append_block(cx, desc_reg_fn, "entry"); + let mut a = Builder::build(cx, bb); + a.call(reg_lib_decl, None, None, register_lib, &[omp_descriptor], None, None); + a.call(atexit, None, None, atexit_fn, &[desc_unreg_fn], None, None); + a.ret_void(); + + // define internal void @.omp_offloading.descriptor_unreg() section ".text.startup" { + // entry: + // call void @__tgt_unregister_lib(ptr @.omp_offloading.descriptor) + // ret void + // } + let bb = Builder::append_block(cx, desc_unreg_fn, "entry"); + let mut a = Builder::build(cx, bb); + a.call(reg_lib_decl, None, None, unregister_lib, &[omp_descriptor], None, None); + a.ret_void(); + + // @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 101, ptr @.omp_offloading.descriptor_reg, ptr null }] + let args = vec![cx.get_const_i32(101), desc_reg_fn, ptr_null]; + let const_struct = cx.const_struct(&args, false); + let arr = cx.const_array(cx.val_ty(const_struct), &[const_struct]); + add_global(cx, "llvm.global_ctors", arr, AppendingLinkage); +} + pub(crate) struct OffloadKernelDims<'ll> { num_workgroups: &'ll Value, threads_per_block: &'ll Value, @@ -487,9 +540,6 @@ pub(crate) fn gen_call_handling<'ll, 'tcx>( let tgt_decl = offload_globals.launcher_fn; let tgt_target_kernel_ty = offload_globals.launcher_ty; - // %struct.__tgt_bin_desc = type { i32, ptr, ptr, ptr } - let tgt_bin_desc = offload_globals.bin_desc; - let tgt_kernel_decl = offload_globals.kernel_args_ty; let begin_mapper_decl = offload_globals.begin_mapper; let end_mapper_decl = offload_globals.end_mapper; @@ -513,12 +563,9 @@ pub(crate) fn gen_call_handling<'ll, 'tcx>( } // Step 0) - // %struct.__tgt_bin_desc = type { i32, ptr, ptr, ptr } - // %6 = alloca %struct.__tgt_bin_desc, align 8 unsafe { llvm::LLVMRustPositionBuilderPastAllocas(&builder.llbuilder, builder.llfn()); } - let tgt_bin_desc_alloca = builder.direct_alloca(tgt_bin_desc, Align::EIGHT, "EmptyDesc"); let ty = cx.type_array(cx.type_ptr(), num_args); // Baseptr are just the input pointer to the kernel, stored in a local alloca @@ -536,7 +583,6 @@ pub(crate) fn gen_call_handling<'ll, 'tcx>( unsafe { llvm::LLVMPositionBuilderAtEnd(&builder.llbuilder, bb); } - builder.memset(tgt_bin_desc_alloca, cx.get_const_i8(0), cx.get_const_i64(32), Align::EIGHT); // Now we allocate once per function param, a copy to be passed to one of our maps. let mut vals = vec![]; @@ -574,15 +620,9 @@ pub(crate) fn gen_call_handling<'ll, 'tcx>( geps.push(gep); } - let mapper_fn_ty = cx.type_func(&[cx.type_ptr()], cx.type_void()); - let register_lib_decl = offload_globals.register_lib; - let unregister_lib_decl = offload_globals.unregister_lib; let init_ty = cx.type_func(&[], cx.type_void()); let init_rtls_decl = offload_globals.init_rtls; - // FIXME(offload): Later we want to add them to the wrapper code, rather than our main function. - // call void @__tgt_register_lib(ptr noundef %6) - builder.call(mapper_fn_ty, None, None, register_lib_decl, &[tgt_bin_desc_alloca], None, None); // call void @__tgt_init_all_rtls() builder.call(init_ty, None, None, init_rtls_decl, &[], None, None); @@ -679,6 +719,4 @@ pub(crate) fn gen_call_handling<'ll, 'tcx>( num_args, s_ident_t, ); - - builder.call(mapper_fn_ty, None, None, unregister_lib_decl, &[tgt_bin_desc_alloca], None, None); } diff --git a/compiler/rustc_codegen_llvm/src/common.rs b/compiler/rustc_codegen_llvm/src/common.rs index b0cf9925019d..f2261ab79340 100644 --- a/compiler/rustc_codegen_llvm/src/common.rs +++ b/compiler/rustc_codegen_llvm/src/common.rs @@ -124,6 +124,10 @@ impl<'ll, CX: Borrow>> GenericCx<'ll, CX> { pub(crate) fn const_null(&self, t: &'ll Type) -> &'ll Value { unsafe { llvm::LLVMConstNull(t) } } + + pub(crate) fn const_struct(&self, elts: &[&'ll Value], packed: bool) -> &'ll Value { + struct_in_context(self.llcx(), elts, packed) + } } impl<'ll, 'tcx> ConstCodegenMethods for CodegenCx<'ll, 'tcx> { diff --git a/compiler/rustc_codegen_llvm/src/intrinsic.rs b/compiler/rustc_codegen_llvm/src/intrinsic.rs index 50e627cf6bdf..e035f0809d68 100644 --- a/compiler/rustc_codegen_llvm/src/intrinsic.rs +++ b/compiler/rustc_codegen_llvm/src/intrinsic.rs @@ -30,7 +30,9 @@ use tracing::debug; use crate::abi::FnAbiLlvmExt; use crate::builder::Builder; use crate::builder::autodiff::{adjust_activity_to_abi, generate_enzyme_call}; -use crate::builder::gpu_offload::{OffloadKernelDims, gen_call_handling, gen_define_handling}; +use crate::builder::gpu_offload::{ + OffloadKernelDims, gen_call_handling, gen_define_handling, register_offload, +}; use crate::context::CodegenCx; use crate::declare::declare_raw_fn; use crate::errors::{ @@ -1402,6 +1404,7 @@ fn codegen_offload<'ll, 'tcx>( return; } }; + register_offload(cx); let offload_data = gen_define_handling(&cx, &metadata, target_symbol, offload_globals); gen_call_handling(bx, &offload_data, &args, &types, &metadata, offload_globals, &offload_dims); } diff --git a/compiler/rustc_codegen_ssa/src/back/linker.rs b/compiler/rustc_codegen_ssa/src/back/linker.rs index 1b75db51140b..db49f92e39ac 100644 --- a/compiler/rustc_codegen_ssa/src/back/linker.rs +++ b/compiler/rustc_codegen_ssa/src/back/linker.rs @@ -1208,10 +1208,23 @@ impl<'a> Linker for EmLinker<'a> { fn set_output_kind( &mut self, - _output_kind: LinkOutputKind, + output_kind: LinkOutputKind, _crate_type: CrateType, _out_filename: &Path, ) { + match output_kind { + LinkOutputKind::DynamicNoPicExe | LinkOutputKind::DynamicPicExe => { + self.cmd.arg("-sMAIN_MODULE=2"); + } + LinkOutputKind::DynamicDylib | LinkOutputKind::StaticDylib => { + self.cmd.arg("-sSIDE_MODULE=2"); + } + // -fno-pie is the default on Emscripten. + LinkOutputKind::StaticNoPicExe | LinkOutputKind::StaticPicExe => {} + LinkOutputKind::WasiReactorExe => { + unreachable!(); + } + } } fn link_dylib_by_name(&mut self, name: &str, _verbatim: bool, _as_needed: bool) { diff --git a/compiler/rustc_codegen_ssa/src/codegen_attrs.rs b/compiler/rustc_codegen_ssa/src/codegen_attrs.rs index 4cb390e7d569..9ecb7ab9fd45 100644 --- a/compiler/rustc_codegen_ssa/src/codegen_attrs.rs +++ b/compiler/rustc_codegen_ssa/src/codegen_attrs.rs @@ -189,7 +189,7 @@ fn process_builtin_attrs( }, AttributeKind::FfiConst(_) => codegen_fn_attrs.flags |= CodegenFnAttrFlags::FFI_CONST, AttributeKind::FfiPure(_) => codegen_fn_attrs.flags |= CodegenFnAttrFlags::FFI_PURE, - AttributeKind::StdInternalSymbol(_) => { + AttributeKind::RustcStdInternalSymbol(_) => { codegen_fn_attrs.flags |= CodegenFnAttrFlags::RUSTC_STD_INTERNAL_SYMBOL } AttributeKind::Linkage(linkage, span) => { @@ -217,10 +217,10 @@ fn process_builtin_attrs( AttributeKind::Sanitize { span, .. } => { interesting_spans.sanitize = Some(*span); } - AttributeKind::ObjcClass { classname, .. } => { + AttributeKind::RustcObjcClass { classname, .. } => { codegen_fn_attrs.objc_class = Some(*classname); } - AttributeKind::ObjcSelector { methname, .. } => { + AttributeKind::RustcObjcSelector { methname, .. } => { codegen_fn_attrs.objc_selector = Some(*methname); } AttributeKind::EiiForeignItem => { diff --git a/compiler/rustc_const_eval/src/check_consts/mod.rs b/compiler/rustc_const_eval/src/check_consts/mod.rs index e9824400ab7a..1adba200caaf 100644 --- a/compiler/rustc_const_eval/src/check_consts/mod.rs +++ b/compiler/rustc_const_eval/src/check_consts/mod.rs @@ -83,7 +83,7 @@ pub fn rustc_allow_const_fn_unstable( ) -> bool { let attrs = tcx.hir_attrs(tcx.local_def_id_to_hir_id(def_id)); - find_attr!(attrs, AttributeKind::AllowConstFnUnstable(syms, _) if syms.contains(&feature_gate)) + find_attr!(attrs, AttributeKind::RustcAllowConstFnUnstable(syms, _) if syms.contains(&feature_gate)) } /// Returns `true` if the given `def_id` (trait or function) is "safe to expose on stable". diff --git a/compiler/rustc_const_eval/src/const_eval/dyn_trait.rs b/compiler/rustc_const_eval/src/const_eval/dyn_trait.rs new file mode 100644 index 000000000000..0976a7283ef3 --- /dev/null +++ b/compiler/rustc_const_eval/src/const_eval/dyn_trait.rs @@ -0,0 +1,178 @@ +use rustc_middle::mir::interpret::{CtfeProvenance, InterpResult, Scalar, interp_ok}; +use rustc_middle::ty::{Region, Ty}; +use rustc_middle::{span_bug, ty}; +use rustc_span::def_id::DefId; +use rustc_span::sym; + +use crate::const_eval::CompileTimeMachine; +use crate::interpret::{Immediate, InterpCx, MPlaceTy, MemoryKind, Writeable}; +impl<'tcx> InterpCx<'tcx, CompileTimeMachine<'tcx>> { + pub(crate) fn write_dyn_trait_type_info( + &mut self, + dyn_place: impl Writeable<'tcx, CtfeProvenance>, + data: &'tcx ty::List>>, + region: Region<'tcx>, + ) -> InterpResult<'tcx> { + let tcx = self.tcx.tcx; + + // Find the principal trait ref (for super trait collection), collect auto traits, + // and collect all projection predicates (used when computing TypeId for each supertrait). + let mut principal: Option>> = None; + let mut auto_traits_def_ids: Vec> = Vec::new(); + let mut projections: Vec>> = Vec::new(); + + for b in data.iter() { + match b.skip_binder() { + ty::ExistentialPredicate::Trait(tr) => principal = Some(b.rebind(tr)), + ty::ExistentialPredicate::AutoTrait(did) => auto_traits_def_ids.push(b.rebind(did)), + ty::ExistentialPredicate::Projection(p) => projections.push(b.rebind(p)), + } + } + + // This is to make principal dyn type include Trait and projection predicates, excluding auto traits. + let principal_ty: Option> = principal.map(|_tr| { + let preds = tcx + .mk_poly_existential_predicates_from_iter(data.iter().filter(|b| { + !matches!(b.skip_binder(), ty::ExistentialPredicate::AutoTrait(_)) + })); + Ty::new_dynamic(tcx, preds, region) + }); + + // DynTrait { predicates: &'static [Trait] } + for (field_idx, field) in + dyn_place.layout().ty.ty_adt_def().unwrap().non_enum_variant().fields.iter_enumerated() + { + let field_place = self.project_field(&dyn_place, field_idx)?; + match field.name { + sym::predicates => { + self.write_dyn_trait_predicates_slice( + &field_place, + principal_ty, + &auto_traits_def_ids, + region, + )?; + } + other => { + span_bug!(self.tcx.def_span(field.did), "unimplemented DynTrait field {other}") + } + } + } + + interp_ok(()) + } + + fn mk_dyn_principal_auto_trait_ty( + &self, + auto_trait_def_id: ty::Binder<'tcx, DefId>, + region: Region<'tcx>, + ) -> Ty<'tcx> { + let tcx = self.tcx.tcx; + + // Preserve the binder vars from the original auto-trait predicate. + let pred_inner = ty::ExistentialPredicate::AutoTrait(auto_trait_def_id.skip_binder()); + let pred = ty::Binder::bind_with_vars(pred_inner, auto_trait_def_id.bound_vars()); + + let preds = tcx.mk_poly_existential_predicates_from_iter([pred].into_iter()); + Ty::new_dynamic(tcx, preds, region) + } + + fn write_dyn_trait_predicates_slice( + &mut self, + slice_place: &impl Writeable<'tcx, CtfeProvenance>, + principal_ty: Option>, + auto_trait_def_ids: &[ty::Binder<'tcx, DefId>], + region: Region<'tcx>, + ) -> InterpResult<'tcx> { + let tcx = self.tcx.tcx; + + // total entries in DynTrait predicates + let total_len = principal_ty.map(|_| 1).unwrap_or(0) + auto_trait_def_ids.len(); + + // element type = DynTraitPredicate + let slice_ty = slice_place.layout().ty.builtin_deref(false).unwrap(); // [DynTraitPredicate] + let elem_ty = slice_ty.sequence_element_type(tcx); // DynTraitPredicate + + let arr_layout = self.layout_of(Ty::new_array(tcx, elem_ty, total_len as u64))?; + let arr_place = self.allocate(arr_layout, MemoryKind::Stack)?; + let mut elems = self.project_array_fields(&arr_place)?; + + // principal entry (if any) - NOT an auto trait + if let Some(principal_ty) = principal_ty { + let Some((_i, elem_place)) = elems.next(self)? else { + span_bug!(self.tcx.span, "DynTrait.predicates length computed wrong (principal)"); + }; + self.write_dyn_trait_predicate(elem_place, principal_ty, false)?; + } + + // auto trait entries - these ARE auto traits + for auto in auto_trait_def_ids { + let Some((_i, elem_place)) = elems.next(self)? else { + span_bug!(self.tcx.span, "DynTrait.predicates length computed wrong (auto)"); + }; + let auto_ty = self.mk_dyn_principal_auto_trait_ty(*auto, region); + self.write_dyn_trait_predicate(elem_place, auto_ty, true)?; + } + + let arr_place = arr_place.map_provenance(CtfeProvenance::as_immutable); + let imm = Immediate::new_slice(arr_place.ptr(), total_len as u64, self); + self.write_immediate(imm, slice_place) + } + + fn write_dyn_trait_predicate( + &mut self, + predicate_place: MPlaceTy<'tcx>, + trait_ty: Ty<'tcx>, + is_auto: bool, + ) -> InterpResult<'tcx> { + // DynTraitPredicate { trait_ty: Trait } + for (field_idx, field) in predicate_place + .layout + .ty + .ty_adt_def() + .unwrap() + .non_enum_variant() + .fields + .iter_enumerated() + { + let field_place = self.project_field(&predicate_place, field_idx)?; + match field.name { + sym::trait_ty => { + // Now write the Trait struct + self.write_trait(field_place, trait_ty, is_auto)?; + } + other => { + span_bug!( + self.tcx.def_span(field.did), + "unimplemented DynTraitPredicate field {other}" + ) + } + } + } + interp_ok(()) + } + fn write_trait( + &mut self, + trait_place: MPlaceTy<'tcx>, + trait_ty: Ty<'tcx>, + is_auto: bool, + ) -> InterpResult<'tcx> { + // Trait { ty: TypeId, is_auto: bool } + for (field_idx, field) in + trait_place.layout.ty.ty_adt_def().unwrap().non_enum_variant().fields.iter_enumerated() + { + let field_place = self.project_field(&trait_place, field_idx)?; + match field.name { + sym::ty => { + self.write_type_id(trait_ty, &field_place)?; + } + sym::is_auto => { + self.write_scalar(Scalar::from_bool(is_auto), &field_place)?; + } + other => { + span_bug!(self.tcx.def_span(field.did), "unimplemented Trait field {other}") + } + } + } + interp_ok(()) + } +} diff --git a/compiler/rustc_const_eval/src/const_eval/mod.rs b/compiler/rustc_const_eval/src/const_eval/mod.rs index e70488b81c4c..c17ff8621a50 100644 --- a/compiler/rustc_const_eval/src/const_eval/mod.rs +++ b/compiler/rustc_const_eval/src/const_eval/mod.rs @@ -9,6 +9,7 @@ use tracing::instrument; use crate::interpret::InterpCx; mod dummy_machine; +mod dyn_trait; mod error; mod eval_queries; mod fn_queries; diff --git a/compiler/rustc_const_eval/src/const_eval/type_info.rs b/compiler/rustc_const_eval/src/const_eval/type_info.rs index 3fcf6f94b5bf..f8881f0968bb 100644 --- a/compiler/rustc_const_eval/src/const_eval/type_info.rs +++ b/compiler/rustc_const_eval/src/const_eval/type_info.rs @@ -129,13 +129,18 @@ impl<'tcx> InterpCx<'tcx, CompileTimeMachine<'tcx>> { variant } + ty::Dynamic(predicates, region) => { + let (variant, variant_place) = downcast(sym::DynTrait)?; + let dyn_place = self.project_field(&variant_place, FieldIdx::ZERO)?; + self.write_dyn_trait_type_info(dyn_place, *predicates, *region)?; + variant + } ty::Adt(_, _) | ty::Foreign(_) | ty::Pat(_, _) | ty::FnDef(..) | ty::FnPtr(..) | ty::UnsafeBinder(..) - | ty::Dynamic(..) | ty::Closure(..) | ty::CoroutineClosure(..) | ty::Coroutine(..) diff --git a/compiler/rustc_data_structures/src/graph/scc/mod.rs b/compiler/rustc_data_structures/src/graph/scc/mod.rs index 91cbe3c533bb..954e4116fb55 100644 --- a/compiler/rustc_data_structures/src/graph/scc/mod.rs +++ b/compiler/rustc_data_structures/src/graph/scc/mod.rs @@ -27,26 +27,18 @@ mod tests; /// the max/min element of the SCC, or all of the above. /// /// Concretely, the both merge operations must commute, e.g. where `merge` -/// is `merge_scc` and `merge_reached`: `a.merge(b) == b.merge(a)` +/// is `update_scc` and `update_reached`: `a.merge(b) == b.merge(a)` /// /// In general, what you want is probably always min/max according /// to some ordering, potentially with side constraints (min x such /// that P holds). pub trait Annotation: Debug + Copy { /// Merge two existing annotations into one during - /// path compression.o - fn merge_scc(self, other: Self) -> Self; + /// path compression. + fn update_scc(&mut self, other: &Self); /// Merge a successor into this annotation. - fn merge_reached(self, other: Self) -> Self; - - fn update_scc(&mut self, other: Self) { - *self = self.merge_scc(other) - } - - fn update_reachable(&mut self, other: Self) { - *self = self.merge_reached(other) - } + fn update_reachable(&mut self, other: &Self); } /// An accumulator for annotations. @@ -70,12 +62,8 @@ impl Annotations for NoAnnotations { /// The empty annotation, which does nothing. impl Annotation for () { - fn merge_reached(self, _other: Self) -> Self { - () - } - fn merge_scc(self, _other: Self) -> Self { - () - } + fn update_reachable(&mut self, _other: &Self) {} + fn update_scc(&mut self, _other: &Self) {} } /// Strongly connected components (SCC) of a graph. The type `N` is @@ -614,7 +602,7 @@ where *min_depth = successor_min_depth; *min_cycle_root = successor_node; } - current_component_annotation.update_scc(successor_annotation); + current_component_annotation.update_scc(&successor_annotation); } // The starting node `node` is succeeded by a fully identified SCC // which is now added to the set under `scc_index`. @@ -629,7 +617,7 @@ where // the `successors_stack` for later. trace!(?node, ?successor_scc_index); successors_stack.push(successor_scc_index); - current_component_annotation.update_reachable(successor_annotation); + current_component_annotation.update_reachable(&successor_annotation); } // `node` has no more (direct) successors; search recursively. None => { diff --git a/compiler/rustc_data_structures/src/graph/scc/tests.rs b/compiler/rustc_data_structures/src/graph/scc/tests.rs index 8f04baf51f35..4626861c3e00 100644 --- a/compiler/rustc_data_structures/src/graph/scc/tests.rs +++ b/compiler/rustc_data_structures/src/graph/scc/tests.rs @@ -32,12 +32,12 @@ impl Maxes { } impl Annotation for MaxReached { - fn merge_scc(self, other: Self) -> Self { - Self(std::cmp::max(other.0, self.0)) + fn update_scc(&mut self, other: &Self) { + self.0 = self.0.max(other.0); } - fn merge_reached(self, other: Self) -> Self { - Self(std::cmp::max(other.0, self.0)) + fn update_reachable(&mut self, other: &Self) { + self.0 = self.0.max(other.0); } } @@ -75,13 +75,12 @@ impl Annotations for MinMaxes { } impl Annotation for MinMaxIn { - fn merge_scc(self, other: Self) -> Self { - Self { min: std::cmp::min(self.min, other.min), max: std::cmp::max(self.max, other.max) } + fn update_scc(&mut self, other: &Self) { + self.min = self.min.min(other.min); + self.max = self.max.max(other.max); } - fn merge_reached(self, _other: Self) -> Self { - self - } + fn update_reachable(&mut self, _other: &Self) {} } #[test] diff --git a/compiler/rustc_expand/src/base.rs b/compiler/rustc_expand/src/base.rs index 653f2071d898..6b3c7fe97932 100644 --- a/compiler/rustc_expand/src/base.rs +++ b/compiler/rustc_expand/src/base.rs @@ -963,13 +963,16 @@ impl SyntaxExtension { let stability = find_attr!(attrs, AttributeKind::Stability { stability, .. } => *stability); // FIXME(jdonszelmann): make it impossible to miss the or_else in the typesystem - if let Some(sp) = find_attr!(attrs, AttributeKind::ConstStability { span, .. } => *span) { + if let Some(sp) = + find_attr!(attrs, AttributeKind::RustcConstStability { span, .. } => *span) + { sess.dcx().emit_err(errors::MacroConstStability { span: sp, head_span: sess.source_map().guess_head_span(span), }); } - if let Some(sp) = find_attr!(attrs, AttributeKind::BodyStability{ span, .. } => *span) { + if let Some(sp) = find_attr!(attrs, AttributeKind::RustcBodyStability{ span, .. } => *span) + { sess.dcx().emit_err(errors::MacroBodyStability { span: sp, head_span: sess.source_map().guess_head_span(span), diff --git a/compiler/rustc_expand/src/mbe/macro_rules.rs b/compiler/rustc_expand/src/mbe/macro_rules.rs index 8d2cc23f9763..7cd96211de50 100644 --- a/compiler/rustc_expand/src/mbe/macro_rules.rs +++ b/compiler/rustc_expand/src/mbe/macro_rules.rs @@ -819,7 +819,7 @@ pub fn compile_declarative_macro( } assert!(!kinds.is_empty()); - let transparency = find_attr!(attrs, AttributeKind::MacroTransparency(x) => *x) + let transparency = find_attr!(attrs, AttributeKind::RustcMacroTransparency(x) => *x) .unwrap_or(Transparency::fallback(macro_rules)); if let Some(guar) = guar { diff --git a/compiler/rustc_hir/src/attrs/data_structures.rs b/compiler/rustc_hir/src/attrs/data_structures.rs index 8a7dee15d4f4..ef9ee4b6fb2d 100644 --- a/compiler/rustc_hir/src/attrs/data_structures.rs +++ b/compiler/rustc_hir/src/attrs/data_structures.rs @@ -746,31 +746,15 @@ pub enum AttributeKind { // FIXME(#82232, #143834): temporarily renamed to mitigate `#[align]` nameres ambiguity Align { align: Align, span: Span }, - /// Represents `#[rustc_allow_const_fn_unstable]`. - AllowConstFnUnstable(ThinVec, Span), - - /// Represents `#[rustc_allow_incoherent_impl]`. - AllowIncoherentImpl(Span), - /// Represents `#[allow_internal_unsafe]`. AllowInternalUnsafe(Span), /// Represents `#[allow_internal_unstable]`. AllowInternalUnstable(ThinVec<(Symbol, Span)>, Span), - /// Represents `#[rustc_as_ptr]` (used by the `dangling_pointers_from_temporaries` lint). - AsPtr(Span), - /// Represents `#[automatically_derived]` AutomaticallyDerived(Span), - /// Represents `#[rustc_default_body_unstable]`. - BodyStability { - stability: DefaultBodyStability, - /// Span of the `#[rustc_default_body_unstable(...)]` attribute - span: Span, - }, - /// Represents the trace attribute of `#[cfg_attr]` CfgAttrTrace, @@ -780,9 +764,6 @@ pub enum AttributeKind { /// Represents `#[cfi_encoding]` CfiEncoding { encoding: Symbol }, - /// Represents `#[rustc_coinductive]`. - Coinductive(Span), - /// Represents `#[cold]`. Cold(Span), @@ -792,26 +773,9 @@ pub enum AttributeKind { /// Represents `#[compiler_builtins]`. CompilerBuiltins, - /// Represents `#[rustc_confusables]`. - Confusables { - symbols: ThinVec, - // FIXME(jdonszelmann): remove when target validation code is moved - first_span: Span, - }, - /// Represents `#[const_continue]`. ConstContinue(Span), - /// Represents `#[rustc_const_stable]` and `#[rustc_const_unstable]`. - ConstStability { - stability: PartialConstStability, - /// Span of the `#[rustc_const_stable(...)]` or `#[rustc_const_unstable(...)]` attribute - span: Span, - }, - - /// Represents `#[rustc_const_stable_indirect]`. - ConstStabilityIndirect, - /// Represents `#[coroutine]`. Coroutine(Span), @@ -830,9 +794,6 @@ pub enum AttributeKind { /// Represents `#[debugger_visualizer]`. DebuggerVisualizer(ThinVec), - /// Represents `#[rustc_deny_explicit_impl]`. - DenyExplicitImpl(Span), - /// Represents [`#[deprecated]`](https://doc.rust-lang.org/stable/reference/attributes/diagnostics.html#the-deprecated-attribute). Deprecation { deprecation: Deprecation, span: Span }, @@ -848,12 +809,6 @@ pub enum AttributeKind { /// i.e. doc comments. DocComment { style: AttrStyle, kind: DocFragmentKind, span: Span, comment: Symbol }, - /// Represents `#[rustc_dummy]`. - Dummy, - - /// Represents `#[rustc_dyn_incompatible_trait]`. - DynIncompatibleTrait(Span), - /// Implementation detail of `#[eii]` EiiDeclaration(EiiDecl), @@ -920,9 +875,6 @@ pub enum AttributeKind { /// Represents [`#[macro_export]`](https://doc.rust-lang.org/reference/macros-by-example.html#r-macro.decl.scope.path). MacroExport { span: Span, local_inner_macros: bool }, - /// Represents `#[rustc_macro_transparency]`. - MacroTransparency(Transparency), - /// Represents `#[macro_use]`. MacroUse { span: Span, arguments: MacroUseArgs }, @@ -978,24 +930,12 @@ pub enum AttributeKind { /// Represents `#[non_exhaustive]` NonExhaustive(Span), - /// Represents `#[rustc_objc_class]` - ObjcClass { classname: Symbol, span: Span }, - - /// Represents `#[rustc_objc_selector]` - ObjcSelector { methname: Symbol, span: Span }, - /// Represents `#[optimize(size|speed)]` Optimize(OptimizeAttr, Span), /// Represents `#[panic_runtime]` PanicRuntime, - /// Represents `#[rustc_paren_sugar]`. - ParenSugar(Span), - - /// Represents `#[rustc_pass_by_value]` (used by the `rustc_pass_by_value` lint). - PassByValue(Span), - /// Represents `#[patchable_function_entry]` PatchableFunctionEntry { prefix: u8, entry: u8 }, @@ -1023,9 +963,6 @@ pub enum AttributeKind { /// Represents `#[profiler_runtime]` ProfilerRuntime, - /// Represents `#[rustc_pub_transparent]` (used by the `repr_transparent_external_private_fields` lint). - PubTransparent(Span), - /// Represents [`#[recursion_limit]`](https://doc.rust-lang.org/reference/attributes/limits.html#the-recursion_limit-attribute) RecursionLimit { attr_span: Span, limit_span: Span, limit: Limit }, @@ -1041,15 +978,55 @@ pub enum AttributeKind { /// Represents `#[rustc_allocator_zeroed_variant]` RustcAllocatorZeroedVariant { name: Symbol }, + /// Represents `#[rustc_allow_const_fn_unstable]`. + RustcAllowConstFnUnstable(ThinVec, Span), + + /// Represents `#[rustc_allow_incoherent_impl]`. + RustcAllowIncoherentImpl(Span), + + /// Represents `#[rustc_as_ptr]` (used by the `dangling_pointers_from_temporaries` lint). + RustcAsPtr(Span), + + /// Represents `#[rustc_default_body_unstable]`. + RustcBodyStability { + stability: DefaultBodyStability, + /// Span of the `#[rustc_default_body_unstable(...)]` attribute + span: Span, + }, /// Represents `#[rustc_builtin_macro]`. RustcBuiltinMacro { builtin_name: Option, helper_attrs: ThinVec, span: Span }, /// Represents `#[rustc_coherence_is_core]` RustcCoherenceIsCore(Span), + /// Represents `#[rustc_coinductive]`. + RustcCoinductive(Span), + + /// Represents `#[rustc_confusables]`. + RustcConfusables { + symbols: ThinVec, + // FIXME(jdonszelmann): remove when target validation code is moved + first_span: Span, + }, + /// Represents `#[rustc_const_stable]` and `#[rustc_const_unstable]`. + RustcConstStability { + stability: PartialConstStability, + /// Span of the `#[rustc_const_stable(...)]` or `#[rustc_const_unstable(...)]` attribute + span: Span, + }, + + /// Represents `#[rustc_const_stable_indirect]`. + RustcConstStabilityIndirect, + /// Represents `#[rustc_deallocator]` RustcDeallocator, + /// Represents `#[rustc_deny_explicit_impl]`. + RustcDenyExplicitImpl(Span), + + /// Represents `#[rustc_dummy]`. + RustcDummy, + /// Represents `#[rustc_dump_def_parents]` RustcDumpDefParents, @@ -1065,6 +1042,9 @@ pub enum AttributeKind { /// Represents `#[rustc_dump_vtable]` RustcDumpVtable(Span), + /// Represents `#[rustc_dyn_incompatible_trait]`. + RustcDynIncompatibleTrait(Span), + /// Represents `#[rustc_has_incoherent_inherent_impls]` RustcHasIncoherentInherentImpls, @@ -1089,6 +1069,9 @@ pub enum AttributeKind { /// Represents `#[rustc_lint_untracked_query_information]` RustcLintUntrackedQueryInformation, + /// Represents `#[rustc_macro_transparency]`. + RustcMacroTransparency(Transparency), + /// Represents `#[rustc_main]`. RustcMain, @@ -1104,15 +1087,30 @@ pub enum AttributeKind { /// Represents `#[rustc_nounwind]` RustcNounwind, + /// Represents `#[rustc_objc_class]` + RustcObjcClass { classname: Symbol, span: Span }, + + /// Represents `#[rustc_objc_selector]` + RustcObjcSelector { methname: Symbol, span: Span }, + /// Represents `#[rustc_object_lifetime_default]`. RustcObjectLifetimeDefault, /// Represents `#[rustc_offload_kernel]` RustcOffloadKernel, + /// Represents `#[rustc_paren_sugar]`. + RustcParenSugar(Span), + + /// Represents `#[rustc_pass_by_value]` (used by the `rustc_pass_by_value` lint). + RustcPassByValue(Span), + /// Represents `#[rustc_pass_indirectly_in_non_rustic_abis]` RustcPassIndirectlyInNonRusticAbis(Span), + /// Represents `#[rustc_pub_transparent]` (used by the `repr_transparent_external_private_fields` lint). + RustcPubTransparent(Span), + /// Represents `#[rustc_reallocator]` RustcReallocator, @@ -1130,6 +1128,18 @@ pub enum AttributeKind { /// Represents `#[rustc_simd_monomorphize_lane_limit = "N"]`. RustcSimdMonomorphizeLaneLimit(Limit), + /// Represents `#[rustc_skip_during_method_dispatch]`. + RustcSkipDuringMethodDispatch { array: bool, boxed_slice: bool, span: Span }, + + /// Represents `#[rustc_specialization_trait]`. + RustcSpecializationTrait(Span), + + /// Represents `#[rustc_std_internal_symbol]`. + RustcStdInternalSymbol(Span), + + /// Represents `#[rustc_unsafe_specialization_marker]`. + RustcUnsafeSpecializationMarker(Span), + /// Represents `#[rustc_variance]` RustcVariance, @@ -1151,22 +1161,12 @@ pub enum AttributeKind { /// Represents `#[should_panic]` ShouldPanic { reason: Option, span: Span }, - /// Represents `#[rustc_skip_during_method_dispatch]`. - SkipDuringMethodDispatch { array: bool, boxed_slice: bool, span: Span }, - - /// Represents `#[rustc_specialization_trait]`. - SpecializationTrait(Span), - /// Represents `#[stable]`, `#[unstable]` and `#[rustc_allowed_through_unstable_modules]`. Stability { stability: Stability, /// Span of the attribute. span: Span, }, - - /// Represents `#[rustc_std_internal_symbol]`. - StdInternalSymbol(Span), - /// Represents `#[target_feature(enable = "...")]` and /// `#[unsafe(force_target_feature(enable = "...")]`. TargetFeature { features: ThinVec<(Symbol, Span)>, attr_span: Span, was_forced: bool }, @@ -1183,9 +1183,6 @@ pub enum AttributeKind { /// Represents `#[type_length_limit]` TypeLengthLimit { attr_span: Span, limit_span: Span, limit: Limit }, - /// Represents `#[rustc_unsafe_specialization_marker]`. - UnsafeSpecializationMarker(Span), - /// Represents `#[unstable_feature_bound]`. UnstableFeatureBound(ThinVec<(Symbol, Span)>), diff --git a/compiler/rustc_hir/src/attrs/encode_cross_crate.rs b/compiler/rustc_hir/src/attrs/encode_cross_crate.rs index 356575416ade..631b07ff1da2 100644 --- a/compiler/rustc_hir/src/attrs/encode_cross_crate.rs +++ b/compiler/rustc_hir/src/attrs/encode_cross_crate.rs @@ -19,37 +19,26 @@ impl AttributeKind { match self { // tidy-alphabetical-start Align { .. } => No, - AllowConstFnUnstable(..) => No, - AllowIncoherentImpl(..) => No, AllowInternalUnsafe(..) => Yes, AllowInternalUnstable(..) => Yes, - AsPtr(..) => Yes, AutomaticallyDerived(..) => Yes, - BodyStability { .. } => No, CfgAttrTrace => Yes, CfgTrace(..) => Yes, CfiEncoding { .. } => Yes, - Coinductive(..) => No, Cold(..) => No, CollapseDebugInfo(..) => Yes, CompilerBuiltins => No, - Confusables { .. } => Yes, ConstContinue(..) => No, - ConstStability { .. } => Yes, - ConstStabilityIndirect => No, Coroutine(..) => No, Coverage(..) => No, CrateName { .. } => No, CrateType(_) => No, CustomMir(_, _, _) => Yes, DebuggerVisualizer(..) => No, - DenyExplicitImpl(..) => No, Deprecation { .. } => Yes, DoNotRecommend { .. } => Yes, Doc(_) => Yes, DocComment { .. } => Yes, - Dummy => No, - DynIncompatibleTrait(..) => No, EiiDeclaration(_) => Yes, EiiForeignItem => No, EiiImpls(..) => No, @@ -69,7 +58,6 @@ impl AttributeKind { LoopMatch(..) => No, MacroEscape(..) => No, MacroExport { .. } => Yes, - MacroTransparency(..) => Yes, MacroUse { .. } => No, Marker(..) => No, MayDangle(..) => No, @@ -87,12 +75,8 @@ impl AttributeKind { NoMangle(..) => Yes, // Needed for rustdoc NoStd(..) => No, NonExhaustive(..) => Yes, // Needed for rustdoc - ObjcClass { .. } => No, - ObjcSelector { .. } => No, Optimize(..) => No, PanicRuntime => No, - ParenSugar(..) => No, - PassByValue(..) => Yes, PatchableFunctionEntry { .. } => Yes, Path(..) => No, PatternComplexityLimit { .. } => No, @@ -102,20 +86,30 @@ impl AttributeKind { ProcMacroAttribute(..) => No, ProcMacroDerive { .. } => No, ProfilerRuntime => No, - PubTransparent(..) => Yes, RecursionLimit { .. } => No, Repr { .. } => No, RustcAllocator => No, RustcAllocatorZeroed => No, RustcAllocatorZeroedVariant { .. } => Yes, + RustcAllowConstFnUnstable(..) => No, + RustcAllowIncoherentImpl(..) => No, + RustcAsPtr(..) => Yes, + RustcBodyStability { .. } => No, RustcBuiltinMacro { .. } => Yes, RustcCoherenceIsCore(..) => No, + RustcCoinductive(..) => No, + RustcConfusables { .. } => Yes, + RustcConstStability { .. } => Yes, + RustcConstStabilityIndirect => No, RustcDeallocator => No, + RustcDenyExplicitImpl(..) => No, + RustcDummy => No, RustcDumpDefParents => No, RustcDumpItemBounds => No, RustcDumpPredicates => No, RustcDumpUserArgs => No, RustcDumpVtable(..) => No, + RustcDynIncompatibleTrait(..) => No, RustcHasIncoherentInherentImpls => Yes, RustcLayoutScalarValidRangeEnd(..) => Yes, RustcLayoutScalarValidRangeStart(..) => Yes, @@ -124,32 +118,38 @@ impl AttributeKind { RustcLintOptTy => Yes, RustcLintQueryInstability => Yes, RustcLintUntrackedQueryInformation => Yes, + RustcMacroTransparency(..) => Yes, RustcMain => No, RustcMustImplementOneOf { .. } => No, RustcNeverReturnsNullPointer => Yes, RustcNoImplicitAutorefs => Yes, RustcNounwind => No, + RustcObjcClass { .. } => No, + RustcObjcSelector { .. } => No, RustcObjectLifetimeDefault => No, RustcOffloadKernel => Yes, + RustcParenSugar(..) => No, + RustcPassByValue(..) => Yes, RustcPassIndirectlyInNonRusticAbis(..) => No, + RustcPubTransparent(..) => Yes, RustcReallocator => No, RustcScalableVector { .. } => Yes, RustcShouldNotBeCalledOnConstItems(..) => Yes, RustcSimdMonomorphizeLaneLimit(..) => Yes, // Affects layout computation, which needs to work cross-crate + RustcSkipDuringMethodDispatch { .. } => No, + RustcSpecializationTrait(..) => No, + RustcStdInternalSymbol(..) => No, + RustcUnsafeSpecializationMarker(..) => No, RustcVariance => No, RustcVarianceOfOpaques => No, Sanitize { .. } => No, ShouldPanic { .. } => No, - SkipDuringMethodDispatch { .. } => No, - SpecializationTrait(..) => No, Stability { .. } => Yes, - StdInternalSymbol(..) => No, TargetFeature { .. } => No, ThreadLocal => No, TrackCaller(..) => Yes, TypeConst(..) => Yes, TypeLengthLimit { .. } => No, - UnsafeSpecializationMarker(..) => No, UnstableFeatureBound(..) => No, Used { .. } => No, WindowsSubsystem(..) => No, diff --git a/compiler/rustc_hir_analysis/messages.ftl b/compiler/rustc_hir_analysis/messages.ftl index d9f8eba65c4a..33b8d3c82965 100644 --- a/compiler/rustc_hir_analysis/messages.ftl +++ b/compiler/rustc_hir_analysis/messages.ftl @@ -224,6 +224,10 @@ hir_analysis_impl_not_marked_default = `{$ident}` specializes an item from a par hir_analysis_impl_not_marked_default_err = `{$ident}` specializes an item from a parent `impl`, but that item is not marked `default` .note = parent implementation is in crate `{$cname}` +hir_analysis_impl_unpin_for_pin_projected_type = explicit impls for the `Unpin` trait are not permitted for structurally pinned types + .label = impl of `Unpin` not allowed + .help = `{$adt_name}` is structurally pinned because it is marked as `#[pin_v2]` + hir_analysis_inherent_dyn = cannot define inherent `impl` for a dyn auto trait .label = impl requires at least one non-auto trait .note = define and implement a new trait or type instead diff --git a/compiler/rustc_hir_analysis/src/check/check.rs b/compiler/rustc_hir_analysis/src/check/check.rs index f2b06e1cde71..c00122bce559 100644 --- a/compiler/rustc_hir_analysis/src/check/check.rs +++ b/compiler/rustc_hir_analysis/src/check/check.rs @@ -1701,7 +1701,10 @@ pub(super) fn check_transparent<'tcx>(tcx: TyCtxt<'tcx>, adt: ty::AdtDef<'tcx>) ty::Array(ty, _) => check_unsuited(tcx, typing_env, *ty), ty::Adt(def, args) => { if !def.did().is_local() - && !find_attr!(tcx.get_all_attrs(def.did()), AttributeKind::PubTransparent(_)) + && !find_attr!( + tcx.get_all_attrs(def.did()), + AttributeKind::RustcPubTransparent(_) + ) { let non_exhaustive = def.is_variant_list_non_exhaustive() || def.variants().iter().any(ty::VariantDef::is_field_list_non_exhaustive); diff --git a/compiler/rustc_hir_analysis/src/check/compare_impl_item.rs b/compiler/rustc_hir_analysis/src/check/compare_impl_item.rs index 4534cfcf962e..dd7b03c9dac3 100644 --- a/compiler/rustc_hir_analysis/src/check/compare_impl_item.rs +++ b/compiler/rustc_hir_analysis/src/check/compare_impl_item.rs @@ -592,7 +592,7 @@ pub(super) fn collect_return_position_impl_trait_in_trait_tys<'tcx>( ty, Ty::new_placeholder( tcx, - ty::Placeholder::new( + ty::PlaceholderType::new( universe, ty::BoundTy { var: idx, kind: ty::BoundTyKind::Anon }, ), @@ -2551,7 +2551,7 @@ fn param_env_with_gat_bounds<'tcx>( } }; - let mut bound_vars: smallvec::SmallVec<[ty::BoundVariableKind; 8]> = + let mut bound_vars: smallvec::SmallVec<[ty::BoundVariableKind<'tcx>; 8]> = smallvec::SmallVec::with_capacity(tcx.generics_of(impl_ty.def_id).own_params.len()); // Extend the impl's identity args with late-bound GAT vars let normalize_impl_ty_args = ty::GenericArgs::identity_for_item(tcx, container_id) @@ -2587,7 +2587,7 @@ fn param_env_with_gat_bounds<'tcx>( ty::Const::new_bound( tcx, ty::INNERMOST, - ty::BoundConst { var: ty::BoundVar::from_usize(bound_vars.len() - 1) }, + ty::BoundConst::new(ty::BoundVar::from_usize(bound_vars.len() - 1)), ) .into() } diff --git a/compiler/rustc_hir_analysis/src/coherence/builtin.rs b/compiler/rustc_hir_analysis/src/coherence/builtin.rs index 61562cc1e4f3..f81913a9c86f 100644 --- a/compiler/rustc_hir_analysis/src/coherence/builtin.rs +++ b/compiler/rustc_hir_analysis/src/coherence/builtin.rs @@ -38,6 +38,7 @@ pub(super) fn check_trait<'tcx>( checker.check(lang_items.drop_trait(), visit_implementation_of_drop)?; checker.check(lang_items.async_drop_trait(), visit_implementation_of_drop)?; checker.check(lang_items.copy_trait(), visit_implementation_of_copy)?; + checker.check(lang_items.unpin_trait(), visit_implementation_of_unpin)?; checker.check(lang_items.const_param_ty_trait(), |checker| { visit_implementation_of_const_param_ty(checker) })?; @@ -134,6 +135,41 @@ fn visit_implementation_of_copy(checker: &Checker<'_>) -> Result<(), ErrorGuaran } } +fn visit_implementation_of_unpin(checker: &Checker<'_>) -> Result<(), ErrorGuaranteed> { + let tcx = checker.tcx; + let impl_header = checker.impl_header; + let impl_did = checker.impl_def_id; + debug!("visit_implementation_of_unpin: impl_did={:?}", impl_did); + + let self_type = impl_header.trait_ref.instantiate_identity().self_ty(); + debug!("visit_implementation_of_unpin: self_type={:?}", self_type); + + let span = tcx.def_span(impl_did); + + if tcx.features().pin_ergonomics() { + match self_type.kind() { + // Soundness concerns: a type `T` annotated with `#[pin_v2]` is allowed to project + // `Pin<&mut T>` to its field `Pin<&mut U>` safely (even if `U: !Unpin`). + // If `T` is allowed to impl `Unpin` manually (note that `Unpin` is a safe trait, + // which cannot carry safety properties), then `&mut U` could be obtained from + // `&mut T` that dereferenced by `Pin<&mut T>`, which breaks the safety contract of + // `Pin<&mut U>` for `U: !Unpin`. + ty::Adt(adt, _) if adt.is_pin_project() => { + return Err(tcx.dcx().emit_err(crate::errors::ImplUnpinForPinProjectedType { + span, + adt_span: tcx.def_span(adt.did()), + adt_name: tcx.item_name(adt.did()), + })); + } + ty::Adt(_, _) => {} + _ => { + return Err(tcx.dcx().span_delayed_bug(span, "impl of `Unpin` for a non-adt type")); + } + }; + } + Ok(()) +} + fn visit_implementation_of_const_param_ty(checker: &Checker<'_>) -> Result<(), ErrorGuaranteed> { let tcx = checker.tcx; let header = checker.impl_header; diff --git a/compiler/rustc_hir_analysis/src/coherence/inherent_impls.rs b/compiler/rustc_hir_analysis/src/coherence/inherent_impls.rs index fe47f3258846..edaf33e493c0 100644 --- a/compiler/rustc_hir_analysis/src/coherence/inherent_impls.rs +++ b/compiler/rustc_hir_analysis/src/coherence/inherent_impls.rs @@ -91,7 +91,7 @@ impl<'tcx> InherentCollect<'tcx> { for &impl_item in items { if !find_attr!( self.tcx.get_all_attrs(impl_item), - AttributeKind::AllowIncoherentImpl(_) + AttributeKind::RustcAllowIncoherentImpl(_) ) { let impl_span = self.tcx.def_span(impl_def_id); return Err(self.tcx.dcx().emit_err(errors::InherentTyOutsideRelevant { @@ -125,7 +125,7 @@ impl<'tcx> InherentCollect<'tcx> { for &impl_item in items { if !find_attr!( self.tcx.get_all_attrs(impl_item), - AttributeKind::AllowIncoherentImpl(_) + AttributeKind::RustcAllowIncoherentImpl(_) ) { let span = self.tcx.def_span(impl_def_id); return Err(self.tcx.dcx().emit_err(errors::InherentTyOutsidePrimitive { diff --git a/compiler/rustc_hir_analysis/src/collect.rs b/compiler/rustc_hir_analysis/src/collect.rs index dd399f9d90de..f50aff187f25 100644 --- a/compiler/rustc_hir_analysis/src/collect.rs +++ b/compiler/rustc_hir_analysis/src/collect.rs @@ -889,7 +889,7 @@ fn trait_def(tcx: TyCtxt<'_>, def_id: LocalDefId) -> ty::TraitDef { let attrs = tcx.get_all_attrs(def_id); - let paren_sugar = find_attr!(attrs, AttributeKind::ParenSugar(_)); + let paren_sugar = find_attr!(attrs, AttributeKind::RustcParenSugar(_)); if paren_sugar && !tcx.features().unboxed_closures() { tcx.dcx().emit_err(errors::ParenSugarAttribute { span: item.span }); } @@ -897,22 +897,23 @@ fn trait_def(tcx: TyCtxt<'_>, def_id: LocalDefId) -> ty::TraitDef { // Only regular traits can be marker. let is_marker = !is_alias && find_attr!(attrs, AttributeKind::Marker(_)); - let rustc_coinductive = find_attr!(attrs, AttributeKind::Coinductive(_)); + let rustc_coinductive = find_attr!(attrs, AttributeKind::RustcCoinductive(_)); let is_fundamental = find_attr!(attrs, AttributeKind::Fundamental); let [skip_array_during_method_dispatch, skip_boxed_slice_during_method_dispatch] = find_attr!( attrs, - AttributeKind::SkipDuringMethodDispatch { array, boxed_slice, span: _ } => [*array, *boxed_slice] + AttributeKind::RustcSkipDuringMethodDispatch { array, boxed_slice, span: _ } => [*array, *boxed_slice] ) .unwrap_or([false; 2]); - let specialization_kind = if find_attr!(attrs, AttributeKind::UnsafeSpecializationMarker(_)) { - ty::trait_def::TraitSpecializationKind::Marker - } else if find_attr!(attrs, AttributeKind::SpecializationTrait(_)) { - ty::trait_def::TraitSpecializationKind::AlwaysApplicable - } else { - ty::trait_def::TraitSpecializationKind::None - }; + let specialization_kind = + if find_attr!(attrs, AttributeKind::RustcUnsafeSpecializationMarker(_)) { + ty::trait_def::TraitSpecializationKind::Marker + } else if find_attr!(attrs, AttributeKind::RustcSpecializationTrait(_)) { + ty::trait_def::TraitSpecializationKind::AlwaysApplicable + } else { + ty::trait_def::TraitSpecializationKind::None + }; let must_implement_one_of = find_attr!( attrs, @@ -923,9 +924,9 @@ fn trait_def(tcx: TyCtxt<'_>, def_id: LocalDefId) -> ty::TraitDef { .collect::>() ); - let deny_explicit_impl = find_attr!(attrs, AttributeKind::DenyExplicitImpl(_)); + let deny_explicit_impl = find_attr!(attrs, AttributeKind::RustcDenyExplicitImpl(_)); let force_dyn_incompatible = - find_attr!(attrs, AttributeKind::DynIncompatibleTrait(span) => *span); + find_attr!(attrs, AttributeKind::RustcDynIncompatibleTrait(span) => *span); ty::TraitDef { def_id: def_id.to_def_id(), diff --git a/compiler/rustc_hir_analysis/src/collect/item_bounds.rs b/compiler/rustc_hir_analysis/src/collect/item_bounds.rs index 7025f7ac84b0..a01ee2d31a3d 100644 --- a/compiler/rustc_hir_analysis/src/collect/item_bounds.rs +++ b/compiler/rustc_hir_analysis/src/collect/item_bounds.rs @@ -241,7 +241,7 @@ struct MapAndCompressBoundVars<'tcx> { binder: ty::DebruijnIndex, /// List of bound vars that remain unsubstituted because they were not /// mentioned in the GAT's args. - still_bound_vars: Vec, + still_bound_vars: Vec>, /// Subtle invariant: If the `GenericArg` is bound, then it should be /// stored with the debruijn index of `INNERMOST` so it can be shifted /// correctly during substitution. @@ -330,7 +330,8 @@ impl<'tcx> TypeFolder> for MapAndCompressBoundVars<'tcx> { } else { let var = ty::BoundVar::from_usize(self.still_bound_vars.len()); self.still_bound_vars.push(ty::BoundVariableKind::Const); - let mapped = ty::Const::new_bound(self.tcx, ty::INNERMOST, ty::BoundConst { var }); + let mapped = + ty::Const::new_bound(self.tcx, ty::INNERMOST, ty::BoundConst::new(var)); self.mapping.insert(old_bound.var, mapped.into()); mapped }; diff --git a/compiler/rustc_hir_analysis/src/collect/resolve_bound_vars.rs b/compiler/rustc_hir_analysis/src/collect/resolve_bound_vars.rs index 02443b577d38..26f79d374075 100644 --- a/compiler/rustc_hir_analysis/src/collect/resolve_bound_vars.rs +++ b/compiler/rustc_hir_analysis/src/collect/resolve_bound_vars.rs @@ -63,9 +63,9 @@ impl ResolvedArg { struct BoundVarContext<'a, 'tcx> { tcx: TyCtxt<'tcx>, - rbv: &'a mut ResolveBoundVars, + rbv: &'a mut ResolveBoundVars<'tcx>, disambiguator: &'a mut DisambiguatorState, - scope: ScopeRef<'a>, + scope: ScopeRef<'a, 'tcx>, opaque_capture_errors: RefCell>, } @@ -76,7 +76,7 @@ struct OpaqueHigherRankedLifetimeCaptureErrors { } #[derive(Debug)] -enum Scope<'a> { +enum Scope<'a, 'tcx> { /// Declares lifetimes, and each can be early-bound or late-bound. /// The `DebruijnIndex` of late-bound lifetimes starts at `1` and /// it should be shifted by the number of `Binder`s in between the @@ -94,7 +94,7 @@ enum Scope<'a> { /// to append to. hir_id: HirId, - s: ScopeRef<'a>, + s: ScopeRef<'a, 'tcx>, /// If this binder comes from a where clause, specify how it was created. /// This is used to diagnose inaccessible lifetimes in APIT: @@ -110,7 +110,7 @@ enum Scope<'a> { /// e.g., `(&T, fn(&T) -> &T);` becomes `(&'_ T, for<'a> fn(&'a T) -> &'a T)`. Body { id: hir::BodyId, - s: ScopeRef<'a>, + s: ScopeRef<'a, 'tcx>, }, /// Use a specific lifetime (if `Some`) or leave it unset (to be @@ -118,7 +118,7 @@ enum Scope<'a> { /// for the default choice of lifetime in a trait object type. ObjectLifetimeDefault { lifetime: Option, - s: ScopeRef<'a>, + s: ScopeRef<'a, 'tcx>, }, /// When we have nested trait refs, we concatenate late bound vars for inner @@ -126,12 +126,12 @@ enum Scope<'a> { /// lifetimes encountered when identifying the trait that an associated type /// is declared on. Supertrait { - bound_vars: Vec, - s: ScopeRef<'a>, + bound_vars: Vec>, + s: ScopeRef<'a, 'tcx>, }, TraitRefBoundary { - s: ScopeRef<'a>, + s: ScopeRef<'a, 'tcx>, }, /// Remap lifetimes that appear in opaque types to fresh lifetime parameters. Given: @@ -148,7 +148,7 @@ enum Scope<'a> { /// Mapping from each captured lifetime `'a` to the duplicate generic parameter `'b`. captures: &'a RefCell>, - s: ScopeRef<'a>, + s: ScopeRef<'a, 'tcx>, }, /// Disallows capturing late-bound vars from parent scopes. @@ -157,7 +157,7 @@ enum Scope<'a> { /// since we don't do something more correct like replacing any captured /// late-bound vars with early-bound params in the const's own generics. LateBoundary { - s: ScopeRef<'a>, + s: ScopeRef<'a, 'tcx>, what: &'static str, deny_late_regions: bool, }, @@ -167,7 +167,7 @@ enum Scope<'a> { }, } -impl<'a> Scope<'a> { +impl<'a, 'tcx> Scope<'a, 'tcx> { // A helper for debugging scopes without printing parent scopes fn debug_truncated(&self) -> impl fmt::Debug { fmt::from_fn(move |f| match self { @@ -227,7 +227,7 @@ enum BinderScopeType { Concatenating, } -type ScopeRef<'a> = &'a Scope<'a>; +type ScopeRef<'a, 'tcx> = &'a Scope<'a, 'tcx>; /// Adds query implementations to the [Providers] vtable, see [`rustc_middle::query`] pub(crate) fn provide(providers: &mut Providers) { @@ -253,7 +253,7 @@ pub(crate) fn provide(providers: &mut Providers) { /// You should not read the result of this query directly, but rather use /// `named_variable_map`, `late_bound_vars_map`, etc. #[instrument(level = "debug", skip(tcx))] -fn resolve_bound_vars(tcx: TyCtxt<'_>, local_def_id: hir::OwnerId) -> ResolveBoundVars { +fn resolve_bound_vars(tcx: TyCtxt<'_>, local_def_id: hir::OwnerId) -> ResolveBoundVars<'_> { let mut rbv = ResolveBoundVars::default(); let mut visitor = BoundVarContext { tcx, @@ -287,7 +287,7 @@ fn resolve_bound_vars(tcx: TyCtxt<'_>, local_def_id: hir::OwnerId) -> ResolveBou rbv } -fn late_arg_as_bound_arg<'tcx>(param: &GenericParam<'tcx>) -> ty::BoundVariableKind { +fn late_arg_as_bound_arg<'tcx>(param: &GenericParam<'tcx>) -> ty::BoundVariableKind<'tcx> { let def_id = param.def_id.to_def_id(); match param.kind { GenericParamKind::Lifetime { .. } => { @@ -301,7 +301,9 @@ fn late_arg_as_bound_arg<'tcx>(param: &GenericParam<'tcx>) -> ty::BoundVariableK /// Turn a [`ty::GenericParamDef`] into a bound arg. Generally, this should only /// be used when turning early-bound vars into late-bound vars when lowering /// return type notation. -fn generic_param_def_as_bound_arg(param: &ty::GenericParamDef) -> ty::BoundVariableKind { +fn generic_param_def_as_bound_arg<'tcx>( + param: &ty::GenericParamDef, +) -> ty::BoundVariableKind<'tcx> { match param.kind { ty::GenericParamDefKind::Lifetime => { ty::BoundVariableKind::Region(ty::BoundRegionKind::Named(param.def_id)) @@ -329,7 +331,9 @@ fn opaque_captures_all_in_scope_lifetimes<'tcx>(opaque: &'tcx hir::OpaqueTy<'tcx impl<'a, 'tcx> BoundVarContext<'a, 'tcx> { /// Returns the binders in scope and the type of `Binder` that should be created for a poly trait ref. - fn poly_trait_ref_binder_info(&mut self) -> (Vec, BinderScopeType) { + fn poly_trait_ref_binder_info( + &mut self, + ) -> (Vec>, BinderScopeType) { let mut scope = self.scope; let mut supertrait_bound_vars = vec![]; loop { @@ -364,7 +368,7 @@ impl<'a, 'tcx> BoundVarContext<'a, 'tcx> { Scope::Binder { hir_id, .. } => { // Nested poly trait refs have the binders concatenated - let mut full_binders = + let mut full_binders: Vec> = self.rbv.late_bound_vars.get_mut_or_insert_default(hir_id.local_id).clone(); full_binders.extend(supertrait_bound_vars); break (full_binders, BinderScopeType::Concatenating); @@ -1094,7 +1098,7 @@ fn object_lifetime_default(tcx: TyCtxt<'_>, param_def_id: LocalDefId) -> ObjectL } impl<'a, 'tcx> BoundVarContext<'a, 'tcx> { - fn with(&mut self, wrap_scope: Scope<'_>, f: F) + fn with(&mut self, wrap_scope: Scope<'_, 'tcx>, f: F) where F: for<'b> FnOnce(&mut BoundVarContext<'b, 'tcx>), { @@ -1115,7 +1119,7 @@ impl<'a, 'tcx> BoundVarContext<'a, 'tcx> { *self.opaque_capture_errors.borrow_mut() = this.opaque_capture_errors.into_inner(); } - fn record_late_bound_vars(&mut self, hir_id: HirId, binder: Vec) { + fn record_late_bound_vars(&mut self, hir_id: HirId, binder: Vec>) { if let Some(old) = self.rbv.late_bound_vars.insert(hir_id.local_id, binder) { bug!( "overwrote bound vars for {hir_id:?}:\nold={old:?}\nnew={:?}", @@ -1931,7 +1935,7 @@ impl<'a, 'tcx> BoundVarContext<'a, 'tcx> { def_id: DefId, assoc_ident: Ident, assoc_tag: ty::AssocTag, - ) -> Option<(Vec, &'tcx ty::AssocItem)> { + ) -> Option<(Vec>, &'tcx ty::AssocItem)> { let trait_defines_associated_item_named = |trait_def_id: DefId| { tcx.associated_items(trait_def_id).find_by_ident_and_kind( tcx, @@ -1942,7 +1946,7 @@ impl<'a, 'tcx> BoundVarContext<'a, 'tcx> { }; use smallvec::{SmallVec, smallvec}; - let mut stack: SmallVec<[(DefId, SmallVec<[ty::BoundVariableKind; 8]>); 8]> = + let mut stack: SmallVec<[(DefId, SmallVec<[ty::BoundVariableKind<'tcx>; 8]>); 8]> = smallvec![(def_id, smallvec![])]; let mut visited: FxHashSet = FxHashSet::default(); loop { diff --git a/compiler/rustc_hir_analysis/src/errors.rs b/compiler/rustc_hir_analysis/src/errors.rs index 2a77d0b997e2..f0c9023c522c 100644 --- a/compiler/rustc_hir_analysis/src/errors.rs +++ b/compiler/rustc_hir_analysis/src/errors.rs @@ -1690,3 +1690,14 @@ pub(crate) struct EiiWithGenerics { pub eii_name: Symbol, pub impl_name: Symbol, } + +#[derive(Diagnostic)] +#[diag(hir_analysis_impl_unpin_for_pin_projected_type)] +pub(crate) struct ImplUnpinForPinProjectedType { + #[primary_span] + #[label] + pub span: Span, + #[help] + pub adt_span: Span, + pub adt_name: Symbol, +} diff --git a/compiler/rustc_hir_analysis/src/hir_ty_lowering/bounds.rs b/compiler/rustc_hir_analysis/src/hir_ty_lowering/bounds.rs index d6441702b268..3515ce4ea939 100644 --- a/compiler/rustc_hir_analysis/src/hir_ty_lowering/bounds.rs +++ b/compiler/rustc_hir_analysis/src/hir_ty_lowering/bounds.rs @@ -362,7 +362,7 @@ impl<'tcx> dyn HirTyLowerer<'tcx> + '_ { param_ty: Ty<'tcx>, hir_bounds: I, bounds: &mut Vec<(ty::Clause<'tcx>, Span)>, - bound_vars: &'tcx ty::List, + bound_vars: &'tcx ty::List>, predicate_filter: PredicateFilter, overlapping_assoc_constraints: OverlappingAsssocItemConstraints, ) where @@ -1000,7 +1000,9 @@ impl<'tcx> TypeVisitor> for GenericParamAndBoundVarCollector<'_, 't .delayed_bug(format!("unexpected bound region kind: {:?}", br.kind)); return ControlFlow::Break(guar); } - ty::BoundRegionKind::NamedAnon(_) => bug!("only used for pretty printing"), + ty::BoundRegionKind::NamedForPrinting(_) => { + bug!("only used for pretty printing") + } }); } _ => {} diff --git a/compiler/rustc_hir_analysis/src/hir_ty_lowering/mod.rs b/compiler/rustc_hir_analysis/src/hir_ty_lowering/mod.rs index 867c588e302d..9f84f652698b 100644 --- a/compiler/rustc_hir_analysis/src/hir_ty_lowering/mod.rs +++ b/compiler/rustc_hir_analysis/src/hir_ty_lowering/mod.rs @@ -2310,7 +2310,7 @@ impl<'tcx> dyn HirTyLowerer<'tcx> + '_ { Some(rbv::ResolvedArg::LateBound(debruijn, index, _)) => ty::Const::new_bound( tcx, debruijn, - ty::BoundConst { var: ty::BoundVar::from_u32(index) }, + ty::BoundConst::new(ty::BoundVar::from_u32(index)), ), Some(rbv::ResolvedArg::Error(guar)) => ty::Const::new_error(tcx, guar), arg => bug!("unexpected bound var resolution for {:?}: {arg:?}", path_hir_id), @@ -3196,8 +3196,8 @@ impl<'tcx> dyn HirTyLowerer<'tcx> + '_ { #[instrument(level = "trace", skip(self, generate_err))] fn validate_late_bound_regions<'cx>( &'cx self, - constrained_regions: FxIndexSet, - referenced_regions: FxIndexSet, + constrained_regions: FxIndexSet>, + referenced_regions: FxIndexSet>, generate_err: impl Fn(&str) -> Diag<'cx>, ) { for br in referenced_regions.difference(&constrained_regions) { diff --git a/compiler/rustc_hir_typeck/src/method/suggest.rs b/compiler/rustc_hir_typeck/src/method/suggest.rs index b2803f4347e3..cd25b866b098 100644 --- a/compiler/rustc_hir_typeck/src/method/suggest.rs +++ b/compiler/rustc_hir_typeck/src/method/suggest.rs @@ -13,7 +13,9 @@ use rustc_data_structures::fx::{FxIndexMap, FxIndexSet}; use rustc_data_structures::sorted_map::SortedMap; use rustc_data_structures::unord::UnordSet; use rustc_errors::codes::*; -use rustc_errors::{Applicability, Diag, MultiSpan, StashKey, pluralize, struct_span_code_err}; +use rustc_errors::{ + Applicability, Diag, MultiSpan, StashKey, listify, pluralize, struct_span_code_err, +}; use rustc_hir::attrs::AttributeKind; use rustc_hir::def::{CtorKind, DefKind, Res}; use rustc_hir::def_id::DefId; @@ -50,6 +52,51 @@ use crate::errors::{self, CandidateTraitNote, NoAssociatedItem}; use crate::method::probe::UnsatisfiedPredicates; use crate::{Expectation, FnCtxt}; +/// Tracks trait bounds and detects duplicates between ref and non-ref versions of self types. +/// This is used to condense error messages when the same trait bound appears for both +/// `T` and `&T` (or `&mut T`). +struct TraitBoundDuplicateTracker { + trait_def_ids: FxIndexSet, + seen_ref: FxIndexSet, + seen_non_ref: FxIndexSet, + has_ref_dupes: bool, +} + +impl TraitBoundDuplicateTracker { + fn new() -> Self { + Self { + trait_def_ids: FxIndexSet::default(), + seen_ref: FxIndexSet::default(), + seen_non_ref: FxIndexSet::default(), + has_ref_dupes: false, + } + } + + /// Track a trait bound. `is_ref` indicates whether the self type is a reference. + fn track(&mut self, def_id: DefId, is_ref: bool) { + self.trait_def_ids.insert(def_id); + if is_ref { + if self.seen_non_ref.contains(&def_id) { + self.has_ref_dupes = true; + } + self.seen_ref.insert(def_id); + } else { + if self.seen_ref.contains(&def_id) { + self.has_ref_dupes = true; + } + self.seen_non_ref.insert(def_id); + } + } + + fn has_ref_dupes(&self) -> bool { + self.has_ref_dupes + } + + fn into_trait_def_ids(self) -> FxIndexSet { + self.trait_def_ids + } +} + impl<'a, 'tcx> FnCtxt<'a, 'tcx> { fn is_slice_ty(&self, ty: Ty<'tcx>, span: Span) -> bool { self.autoderef(span, ty) @@ -1004,6 +1051,7 @@ impl<'a, 'tcx> FnCtxt<'a, 'tcx> { item_ident: Ident, item_kind: &str, bound_spans: SortedMap>, + unsatisfied_predicates: &UnsatisfiedPredicates<'tcx>, ) { let mut ty_span = match rcvr_ty.kind() { ty::Param(param_type) => { @@ -1012,13 +1060,61 @@ impl<'a, 'tcx> FnCtxt<'a, 'tcx> { ty::Adt(def, _) if def.did().is_local() => Some(self.tcx.def_span(def.did())), _ => None, }; + let rcvr_ty_str = self.tcx.short_string(rcvr_ty, err.long_ty_path()); + let mut tracker = TraitBoundDuplicateTracker::new(); + for (predicate, _parent_pred, _cause) in unsatisfied_predicates { + if let ty::PredicateKind::Clause(ty::ClauseKind::Trait(pred)) = + predicate.kind().skip_binder() + && let self_ty = pred.trait_ref.self_ty() + && self_ty.peel_refs() == rcvr_ty + { + let is_ref = matches!(self_ty.kind(), ty::Ref(..)); + tracker.track(pred.trait_ref.def_id, is_ref); + } + } + let has_ref_dupes = tracker.has_ref_dupes(); + let mut missing_trait_names = tracker + .into_trait_def_ids() + .into_iter() + .map(|def_id| format!("`{}`", self.tcx.def_path_str(def_id))) + .collect::>(); + missing_trait_names.sort(); + let should_condense = + has_ref_dupes && missing_trait_names.len() > 1 && matches!(rcvr_ty.kind(), ty::Adt(..)); + let missing_trait_list = if should_condense { + Some(match missing_trait_names.as_slice() { + [only] => only.clone(), + [first, second] => format!("{first} or {second}"), + [rest @ .., last] => format!("{} or {last}", rest.join(", ")), + [] => String::new(), + }) + } else { + None + }; for (span, mut bounds) in bound_spans { if !self.tcx.sess.source_map().is_span_accessible(span) { continue; } bounds.sort(); bounds.dedup(); - let pre = if Some(span) == ty_span { + let is_ty_span = Some(span) == ty_span; + if is_ty_span && should_condense { + ty_span.take(); + let label = if let Some(missing_trait_list) = &missing_trait_list { + format!( + "{item_kind} `{item_ident}` not found for this {} because `{rcvr_ty_str}` doesn't implement {missing_trait_list}", + rcvr_ty.prefix_string(self.tcx) + ) + } else { + format!( + "{item_kind} `{item_ident}` not found for this {}", + rcvr_ty.prefix_string(self.tcx) + ) + }; + err.span_label(span, label); + continue; + } + let pre = if is_ty_span { ty_span.take(); format!( "{item_kind} `{item_ident}` not found for this {} because it ", @@ -1248,6 +1344,7 @@ impl<'a, 'tcx> FnCtxt<'a, 'tcx> { item_ident, item_kind, bound_spans, + unsatisfied_predicates, ); self.note_derefed_ty_has_method(&mut err, source, rcvr_ty, item_ident, expected); @@ -1507,6 +1604,7 @@ impl<'a, 'tcx> FnCtxt<'a, 'tcx> { bound_spans: &mut SortedMap>, ) { let tcx = self.tcx; + let rcvr_ty_str = self.tcx.short_string(rcvr_ty, err.long_ty_path()); let mut type_params = FxIndexMap::default(); // Pick out the list of unimplemented traits on the receiver. @@ -1798,6 +1896,27 @@ impl<'a, 'tcx> FnCtxt<'a, 'tcx> { let mut spanned_predicates: Vec<_> = spanned_predicates.into_iter().collect(); spanned_predicates.sort_by_key(|(span, _)| *span); for (_, (primary_spans, span_labels, predicates)) in spanned_predicates { + let mut tracker = TraitBoundDuplicateTracker::new(); + let mut all_trait_bounds_for_rcvr = true; + for pred in &predicates { + match pred.kind().skip_binder() { + ty::PredicateKind::Clause(ty::ClauseKind::Trait(pred)) => { + let self_ty = pred.trait_ref.self_ty(); + if self_ty.peel_refs() != rcvr_ty { + all_trait_bounds_for_rcvr = false; + break; + } + let is_ref = matches!(self_ty.kind(), ty::Ref(..)); + tracker.track(pred.trait_ref.def_id, is_ref); + } + _ => { + all_trait_bounds_for_rcvr = false; + break; + } + } + } + let has_ref_dupes = tracker.has_ref_dupes(); + let trait_def_ids = tracker.into_trait_def_ids(); let mut preds: Vec<_> = predicates .iter() .filter_map(|pred| format_pred(**pred)) @@ -1805,7 +1924,27 @@ impl<'a, 'tcx> FnCtxt<'a, 'tcx> { .collect(); preds.sort(); preds.dedup(); - let msg = if let [pred] = &preds[..] { + let availability_note = if all_trait_bounds_for_rcvr + && has_ref_dupes + && trait_def_ids.len() > 1 + && matches!(rcvr_ty.kind(), ty::Adt(..)) + { + let mut trait_names = trait_def_ids + .into_iter() + .map(|def_id| format!("`{}`", tcx.def_path_str(def_id))) + .collect::>(); + trait_names.sort(); + listify(&trait_names, |name| name.to_string()).map(|traits| { + format!( + "for `{item_ident}` to be available, `{rcvr_ty_str}` must implement {traits}" + ) + }) + } else { + None + }; + let msg = if let Some(availability_note) = availability_note { + availability_note + } else if let [pred] = &preds[..] { format!("trait bound {pred} was not satisfied") } else { format!("the following trait bounds were not satisfied:\n{}", preds.join("\n"),) @@ -2103,7 +2242,7 @@ impl<'a, 'tcx> FnCtxt<'a, 'tcx> { for inherent_method in self.tcx.associated_items(inherent_impl_did).in_definition_order() { - if let Some(candidates) = find_attr!(self.tcx.get_all_attrs(inherent_method.def_id), AttributeKind::Confusables{symbols, ..} => symbols) + if let Some(candidates) = find_attr!(self.tcx.get_all_attrs(inherent_method.def_id), AttributeKind::RustcConfusables{symbols, ..} => symbols) && candidates.contains(&item_name.name) && inherent_method.is_fn() { @@ -3281,6 +3420,63 @@ impl<'a, 'tcx> FnCtxt<'a, 'tcx> { } } + /// Checks if we can suggest a derive macro for the unmet trait bound. + /// Returns Some(list_of_derives) if possible, or None if not. + fn consider_suggesting_derives_for_ty( + &self, + trait_pred: ty::TraitPredicate<'tcx>, + adt: ty::AdtDef<'tcx>, + ) -> Option> { + let diagnostic_name = self.tcx.get_diagnostic_name(trait_pred.def_id())?; + + let can_derive = match diagnostic_name { + sym::Default + | sym::Eq + | sym::PartialEq + | sym::Ord + | sym::PartialOrd + | sym::Clone + | sym::Copy + | sym::Hash + | sym::Debug => true, + _ => false, + }; + + if !can_derive { + return None; + } + + let trait_def_id = trait_pred.def_id(); + let self_ty = trait_pred.self_ty(); + + // We need to check if there is already a manual implementation of the trait + // for this specific ADT to avoid suggesting `#[derive(..)]` that would conflict. + if self.tcx.non_blanket_impls_for_ty(trait_def_id, self_ty).any(|impl_def_id| { + self.tcx + .type_of(impl_def_id) + .instantiate_identity() + .ty_adt_def() + .is_some_and(|def| def.did() == adt.did()) + }) { + return None; + } + + let mut derives = Vec::new(); + let self_name = self_ty.to_string(); + let self_span = self.tcx.def_span(adt.did()); + + for super_trait in supertraits(self.tcx, ty::Binder::dummy(trait_pred.trait_ref)) { + if let Some(parent_diagnostic_name) = self.tcx.get_diagnostic_name(super_trait.def_id()) + { + derives.push((self_name.clone(), self_span, parent_diagnostic_name)); + } + } + + derives.push((self_name, self_span, diagnostic_name)); + + Some(derives) + } + fn note_predicate_source_and_get_derives( &self, err: &mut Diag<'_>, @@ -3298,35 +3494,8 @@ impl<'a, 'tcx> FnCtxt<'a, 'tcx> { Some(adt) if adt.did().is_local() => adt, _ => continue, }; - if let Some(diagnostic_name) = self.tcx.get_diagnostic_name(trait_pred.def_id()) { - let can_derive = match diagnostic_name { - sym::Default - | sym::Eq - | sym::PartialEq - | sym::Ord - | sym::PartialOrd - | sym::Clone - | sym::Copy - | sym::Hash - | sym::Debug => true, - _ => false, - }; - if can_derive { - let self_name = trait_pred.self_ty().to_string(); - let self_span = self.tcx.def_span(adt.did()); - for super_trait in - supertraits(self.tcx, ty::Binder::dummy(trait_pred.trait_ref)) - { - if let Some(parent_diagnostic_name) = - self.tcx.get_diagnostic_name(super_trait.def_id()) - { - derives.push((self_name.clone(), self_span, parent_diagnostic_name)); - } - } - derives.push((self_name, self_span, diagnostic_name)); - } else { - traits.push(trait_pred.def_id()); - } + if let Some(new_derives) = self.consider_suggesting_derives_for_ty(trait_pred, adt) { + derives.extend(new_derives); } else { traits.push(trait_pred.def_id()); } diff --git a/compiler/rustc_infer/src/infer/canonical/canonicalizer.rs b/compiler/rustc_infer/src/infer/canonical/canonicalizer.rs index 23f6fee406a5..89ea6324d854 100644 --- a/compiler/rustc_infer/src/infer/canonical/canonicalizer.rs +++ b/compiler/rustc_infer/src/infer/canonical/canonicalizer.rs @@ -684,19 +684,19 @@ impl<'cx, 'tcx> Canonicalizer<'cx, 'tcx> { CanonicalVarKind::Region(u) => CanonicalVarKind::Region(reverse_universe_map[&u]), CanonicalVarKind::Const(u) => CanonicalVarKind::Const(reverse_universe_map[&u]), CanonicalVarKind::PlaceholderTy(placeholder) => { - CanonicalVarKind::PlaceholderTy(ty::Placeholder::new( + CanonicalVarKind::PlaceholderTy(ty::PlaceholderType::new( reverse_universe_map[&placeholder.universe], placeholder.bound, )) } CanonicalVarKind::PlaceholderRegion(placeholder) => { - CanonicalVarKind::PlaceholderRegion(ty::Placeholder::new( + CanonicalVarKind::PlaceholderRegion(ty::PlaceholderRegion::new( reverse_universe_map[&placeholder.universe], placeholder.bound, )) } CanonicalVarKind::PlaceholderConst(placeholder) => { - CanonicalVarKind::PlaceholderConst(ty::Placeholder::new( + CanonicalVarKind::PlaceholderConst(ty::PlaceholderConst::new( reverse_universe_map[&placeholder.universe], placeholder.bound, )) diff --git a/compiler/rustc_infer/src/infer/mod.rs b/compiler/rustc_infer/src/infer/mod.rs index c9ea420944e2..e15b25500bb5 100644 --- a/compiler/rustc_infer/src/infer/mod.rs +++ b/compiler/rustc_infer/src/infer/mod.rs @@ -447,7 +447,7 @@ pub enum RegionVariableOrigin<'tcx> { /// Region variables created when instantiating a binder with /// existential variables, e.g. when calling a function or method. - BoundRegion(Span, ty::BoundRegionKind, BoundRegionConversionTime), + BoundRegion(Span, ty::BoundRegionKind<'tcx>, BoundRegionConversionTime), UpvarRegion(ty::UpvarId, Span), @@ -1300,13 +1300,13 @@ impl<'tcx> InferCtxt<'tcx> { } impl<'tcx> BoundVarReplacerDelegate<'tcx> for ToFreshVars<'tcx> { - fn replace_region(&mut self, br: ty::BoundRegion) -> ty::Region<'tcx> { + fn replace_region(&mut self, br: ty::BoundRegion<'tcx>) -> ty::Region<'tcx> { self.args[br.var.index()].expect_region() } - fn replace_ty(&mut self, bt: ty::BoundTy) -> Ty<'tcx> { + fn replace_ty(&mut self, bt: ty::BoundTy<'tcx>) -> Ty<'tcx> { self.args[bt.var.index()].expect_ty() } - fn replace_const(&mut self, bc: ty::BoundConst) -> ty::Const<'tcx> { + fn replace_const(&mut self, bc: ty::BoundConst<'tcx>) -> ty::Const<'tcx> { self.args[bc.var.index()].expect_const() } } diff --git a/compiler/rustc_infer/src/infer/outlives/test_type_match.rs b/compiler/rustc_infer/src/infer/outlives/test_type_match.rs index 7be5daf61056..479daf67a8ba 100644 --- a/compiler/rustc_infer/src/infer/outlives/test_type_match.rs +++ b/compiler/rustc_infer/src/infer/outlives/test_type_match.rs @@ -91,7 +91,7 @@ pub(super) fn can_match_erased_ty<'tcx>( struct MatchAgainstHigherRankedOutlives<'tcx> { tcx: TyCtxt<'tcx>, pattern_depth: ty::DebruijnIndex, - map: FxHashMap>, + map: FxHashMap, ty::Region<'tcx>>, } impl<'tcx> MatchAgainstHigherRankedOutlives<'tcx> { @@ -115,7 +115,7 @@ impl<'tcx> MatchAgainstHigherRankedOutlives<'tcx> { #[instrument(level = "trace", skip(self))] fn bind( &mut self, - br: ty::BoundRegion, + br: ty::BoundRegion<'tcx>, value: ty::Region<'tcx>, ) -> RelateResult<'tcx, ty::Region<'tcx>> { match self.map.entry(br) { diff --git a/compiler/rustc_infer/src/infer/relate/higher_ranked.rs b/compiler/rustc_infer/src/infer/relate/higher_ranked.rs index 7a0f70e979b8..324725a079bb 100644 --- a/compiler/rustc_infer/src/infer/relate/higher_ranked.rs +++ b/compiler/rustc_infer/src/infer/relate/higher_ranked.rs @@ -33,13 +33,13 @@ impl<'tcx> InferCtxt<'tcx> { let next_universe = self.create_next_universe(); let delegate = FnMutDelegate { - regions: &mut |br: ty::BoundRegion| { + regions: &mut |br: ty::BoundRegion<'tcx>| { ty::Region::new_placeholder(self.tcx, ty::PlaceholderRegion::new(next_universe, br)) }, - types: &mut |bound_ty: ty::BoundTy| { + types: &mut |bound_ty: ty::BoundTy<'tcx>| { Ty::new_placeholder(self.tcx, ty::PlaceholderType::new(next_universe, bound_ty)) }, - consts: &mut |bound_const: ty::BoundConst| { + consts: &mut |bound_const: ty::BoundConst<'tcx>| { ty::Const::new_placeholder( self.tcx, ty::PlaceholderConst::new(next_universe, bound_const), diff --git a/compiler/rustc_lint/src/dangling.rs b/compiler/rustc_lint/src/dangling.rs index af4457f4314b..71ea801a408e 100644 --- a/compiler/rustc_lint/src/dangling.rs +++ b/compiler/rustc_lint/src/dangling.rs @@ -268,7 +268,7 @@ fn lint_expr(cx: &LateContext<'_>, expr: &Expr<'_>) { && let ty = cx.typeck_results().expr_ty(receiver) && owns_allocation(cx.tcx, ty) && let Some(fn_id) = cx.typeck_results().type_dependent_def_id(expr.hir_id) - && find_attr!(cx.tcx.get_all_attrs(fn_id), AttributeKind::AsPtr(_)) + && find_attr!(cx.tcx.get_all_attrs(fn_id), AttributeKind::RustcAsPtr(_)) { // FIXME: use `emit_node_lint` when `#[primary_span]` is added. cx.tcx.emit_node_span_lint( diff --git a/compiler/rustc_lint/src/impl_trait_overcaptures.rs b/compiler/rustc_lint/src/impl_trait_overcaptures.rs index f6c2e5946079..1cdc5e4a1b36 100644 --- a/compiler/rustc_lint/src/impl_trait_overcaptures.rs +++ b/compiler/rustc_lint/src/impl_trait_overcaptures.rs @@ -211,7 +211,7 @@ where // When we get into a binder, we need to add its own bound vars to the scope. let mut added = vec![]; for arg in t.bound_vars() { - let arg: ty::BoundVariableKind = arg; + let arg: ty::BoundVariableKind<'tcx> = arg; match arg { ty::BoundVariableKind::Region(ty::BoundRegionKind::Named(def_id)) | ty::BoundVariableKind::Ty(ty::BoundTyKind::Param(def_id)) => { diff --git a/compiler/rustc_lint/src/pass_by_value.rs b/compiler/rustc_lint/src/pass_by_value.rs index f4a506d50a41..3823c9aa1861 100644 --- a/compiler/rustc_lint/src/pass_by_value.rs +++ b/compiler/rustc_lint/src/pass_by_value.rs @@ -44,7 +44,7 @@ fn path_for_pass_by_value(cx: &LateContext<'_>, ty: &hir::Ty<'_>) -> Option + if find_attr!(cx.tcx.get_all_attrs(def_id), AttributeKind::RustcPassByValue(_)) => { let name = cx.tcx.item_ident(def_id); let path_segment = path.segments.last().unwrap(); @@ -52,7 +52,10 @@ fn path_for_pass_by_value(cx: &LateContext<'_>, ty: &hir::Ty<'_>) -> Option { if let ty::Adt(adt, args) = cx.tcx.type_of(did).instantiate_identity().kind() { - if find_attr!(cx.tcx.get_all_attrs(adt.did()), AttributeKind::PassByValue(_)) { + if find_attr!( + cx.tcx.get_all_attrs(adt.did()), + AttributeKind::RustcPassByValue(_) + ) { return Some(cx.tcx.def_path_str_with_args(adt.did(), args)); } } diff --git a/compiler/rustc_lint/src/unused.rs b/compiler/rustc_lint/src/unused.rs index 506a16355e22..5516298c5e85 100644 --- a/compiler/rustc_lint/src/unused.rs +++ b/compiler/rustc_lint/src/unused.rs @@ -539,10 +539,19 @@ impl<'tcx> LateLintPass<'tcx> for UnusedResults { ); } MustUsePath::Def(span, def_id, reason) => { - let span = span.find_ancestor_not_from_macro().unwrap_or(*span); + let ancenstor_span = span.find_ancestor_not_from_macro().unwrap_or(*span); + let is_redundant_let_ignore = cx + .sess() + .source_map() + .span_to_prev_source(ancenstor_span) + .ok() + .map(|prev| prev.trim_end().ends_with("let _ =")) + .unwrap_or(false); + let suggestion_span = + if is_redundant_let_ignore { *span } else { ancenstor_span }; cx.emit_span_lint( UNUSED_MUST_USE, - span, + ancenstor_span, UnusedDef { pre: descr_pre, post: descr_post, @@ -551,11 +560,13 @@ impl<'tcx> LateLintPass<'tcx> for UnusedResults { note: *reason, suggestion: (!is_inner).then_some(if expr_is_from_block { UnusedDefSuggestion::BlockTailExpr { - before_span: span.shrink_to_lo(), - after_span: span.shrink_to_hi(), + before_span: suggestion_span.shrink_to_lo(), + after_span: suggestion_span.shrink_to_hi(), } } else { - UnusedDefSuggestion::NormalExpr { span: span.shrink_to_lo() } + UnusedDefSuggestion::NormalExpr { + span: suggestion_span.shrink_to_lo(), + } }), }, ); diff --git a/compiler/rustc_macros/src/diagnostics/diagnostic_builder.rs b/compiler/rustc_macros/src/diagnostics/diagnostic_builder.rs index cbc70b55d7ee..25110fd4f908 100644 --- a/compiler/rustc_macros/src/diagnostics/diagnostic_builder.rs +++ b/compiler/rustc_macros/src/diagnostics/diagnostic_builder.rs @@ -2,6 +2,7 @@ use proc_macro2::{Ident, Span, TokenStream}; use quote::{format_ident, quote, quote_spanned}; +use syn::parse::ParseStream; use syn::spanned::Spanned; use syn::{Attribute, Meta, Path, Token, Type, parse_quote}; use synstructure::{BindingInfo, Structure, VariantInfo}; @@ -11,7 +12,7 @@ use crate::diagnostics::error::{ DiagnosticDeriveError, span_err, throw_invalid_attr, throw_span_err, }; use crate::diagnostics::utils::{ - FieldInfo, FieldInnerTy, FieldMap, HasFieldMap, SetOnce, SpannedOption, SubdiagnosticKind, + FieldInfo, FieldInnerTy, FieldMap, SetOnce, SpannedOption, SubdiagnosticKind, build_field_mapping, is_doc_comment, report_error_if_not_applied_to_span, report_type_error, should_generate_arg, type_is_bool, type_is_unit, type_matches_path, }; @@ -42,19 +43,13 @@ pub(crate) struct DiagnosticDeriveVariantBuilder { /// Slug is a mandatory part of the struct attribute as corresponds to the Fluent message that /// has the actual diagnostic message. - pub slug: SpannedOption, + pub slug: Option, /// Error codes are a optional part of the struct attribute - this is only set to detect /// multiple specifications. pub code: SpannedOption<()>, } -impl HasFieldMap for DiagnosticDeriveVariantBuilder { - fn get_field_binding(&self, field: &String) -> Option<&TokenStream> { - self.field_map.get(field) - } -} - impl DiagnosticDeriveKind { /// Call `f` for the struct or for each variant of the enum, returning a `TokenStream` with the /// tokens from `f` wrapped in an `match` expression. Emits errors for use of derive on unions @@ -111,7 +106,7 @@ impl DiagnosticDeriveKind { impl DiagnosticDeriveVariantBuilder { pub(crate) fn primary_message(&self) -> Option<&Path> { - match self.slug.value_ref() { + match self.slug.as_ref() { None => { span_err(self.span, "diagnostic slug not specified") .help( @@ -169,7 +164,7 @@ impl DiagnosticDeriveVariantBuilder { &self, attr: &Attribute, ) -> Result, DiagnosticDeriveError> { - let Some(subdiag) = SubdiagnosticVariant::from_attr(attr, self)? else { + let Some(subdiag) = SubdiagnosticVariant::from_attr(attr, &self.field_map)? else { // Some attributes aren't errors - like documentation comments - but also aren't // subdiagnostics. return Ok(None); @@ -191,7 +186,7 @@ impl DiagnosticDeriveVariantBuilder { SubdiagnosticKind::MultipartSuggestion { .. } => unreachable!(), }); - Ok(Some((subdiag.kind, slug, subdiag.no_span))) + Ok(Some((subdiag.kind, slug, false))) } /// Establishes state in the `DiagnosticDeriveBuilder` resulting from the struct @@ -209,47 +204,54 @@ impl DiagnosticDeriveVariantBuilder { let name = attr.path().segments.last().unwrap().ident.to_string(); let name = name.as_str(); - let mut first = true; - if name == "diag" { let mut tokens = TokenStream::new(); - attr.parse_nested_meta(|nested| { - let path = &nested.path; + attr.parse_args_with(|input: ParseStream<'_>| { + let mut input = &*input; + let slug_recovery_point = input.fork(); - if first && (nested.input.is_empty() || nested.input.peek(Token![,])) { - self.slug.set_once(path.clone(), path.span().unwrap()); - first = false; - return Ok(()); + let slug = input.parse::()?; + if input.is_empty() || input.peek(Token![,]) { + self.slug = Some(slug); + } else { + input = &slug_recovery_point; } - first = false; - - let Ok(nested) = nested.value() else { - span_err( - nested.input.span().unwrap(), - "diagnostic slug must be the first argument", - ) - .emit(); - return Ok(()); - }; - - if path.is_ident("code") { - self.code.set_once((), path.span().unwrap()); - - let code = nested.parse::()?; - tokens.extend(quote! { - diag.code(#code); - }); - } else { - span_err(path.span().unwrap(), "unknown argument") - .note("only the `code` parameter is valid after the slug") + while !input.is_empty() { + input.parse::()?; + // Allow trailing comma + if input.is_empty() { + break; + } + let arg_name: Path = input.parse::()?; + if input.peek(Token![,]) { + span_err( + arg_name.span().unwrap(), + "diagnostic slug must be the first argument", + ) .emit(); - - // consume the buffer so we don't have syntax errors from syn - let _ = nested.parse::(); + continue; + } + let arg_name = arg_name.require_ident()?; + input.parse::()?; + let arg_value = input.parse::()?; + match arg_name.to_string().as_str() { + "code" => { + self.code.set_once((), arg_name.span().unwrap()); + tokens.extend(quote! { + diag.code(#arg_value); + }); + } + _ => { + span_err(arg_name.span().unwrap(), "unknown argument") + .note("only the `code` parameter is valid after the slug") + .emit(); + } + } } Ok(()) })?; + return Ok(tokens); } diff --git a/compiler/rustc_macros/src/diagnostics/subdiagnostic.rs b/compiler/rustc_macros/src/diagnostics/subdiagnostic.rs index dcd0116d804d..db2a19ab85ba 100644 --- a/compiler/rustc_macros/src/diagnostics/subdiagnostic.rs +++ b/compiler/rustc_macros/src/diagnostics/subdiagnostic.rs @@ -1,9 +1,10 @@ #![deny(unused_must_use)] -use proc_macro2::TokenStream; +use proc_macro2::{Ident, TokenStream}; use quote::{format_ident, quote}; +use syn::parse::ParseStream; use syn::spanned::Spanned; -use syn::{Attribute, Meta, MetaList, Path}; +use syn::{Attribute, Meta, MetaList, Path, Token}; use synstructure::{BindingInfo, Structure, VariantInfo}; use super::utils::SubdiagnosticVariant; @@ -11,10 +12,10 @@ use crate::diagnostics::error::{ DiagnosticDeriveError, invalid_attr, span_err, throw_invalid_attr, throw_span_err, }; use crate::diagnostics::utils::{ - AllowMultipleAlternatives, FieldInfo, FieldInnerTy, FieldMap, HasFieldMap, SetOnce, - SpannedOption, SubdiagnosticKind, build_field_mapping, build_suggestion_code, is_doc_comment, - new_code_ident, report_error_if_not_applied_to_applicability, - report_error_if_not_applied_to_span, should_generate_arg, + AllowMultipleAlternatives, FieldInfo, FieldInnerTy, FieldMap, SetOnce, SpannedOption, + SubdiagnosticKind, build_field_mapping, build_suggestion_code, is_doc_comment, new_code_ident, + report_error_if_not_applied_to_applicability, report_error_if_not_applied_to_span, + should_generate_arg, }; /// The central struct for constructing the `add_to_diag` method from an annotated struct. @@ -142,12 +143,6 @@ struct SubdiagnosticDeriveVariantBuilder<'parent, 'a> { is_enum: bool, } -impl<'parent, 'a> HasFieldMap for SubdiagnosticDeriveVariantBuilder<'parent, 'a> { - fn get_field_binding(&self, field: &String) -> Option<&TokenStream> { - self.fields.get(field) - } -} - /// Provides frequently-needed information about the diagnostic kinds being derived for this type. #[derive(Clone, Copy, Debug)] struct KindsStatistics { @@ -187,14 +182,12 @@ impl<'a> FromIterator<&'a SubdiagnosticKind> for KindsStatistics { } impl<'parent, 'a> SubdiagnosticDeriveVariantBuilder<'parent, 'a> { - fn identify_kind( - &mut self, - ) -> Result, DiagnosticDeriveError> { + fn identify_kind(&mut self) -> Result, DiagnosticDeriveError> { let mut kind_slugs = vec![]; for attr in self.variant.ast().attrs { - let Some(SubdiagnosticVariant { kind, slug, no_span }) = - SubdiagnosticVariant::from_attr(attr, self)? + let Some(SubdiagnosticVariant { kind, slug }) = + SubdiagnosticVariant::from_attr(attr, &self.fields)? else { // Some attributes aren't errors - like documentation comments - but also aren't // subdiagnostics. @@ -213,7 +206,7 @@ impl<'parent, 'a> SubdiagnosticDeriveVariantBuilder<'parent, 'a> { ); }; - kind_slugs.push((kind, slug, no_span)); + kind_slugs.push((kind, slug)); } Ok(kind_slugs) @@ -437,23 +430,35 @@ impl<'parent, 'a> SubdiagnosticDeriveVariantBuilder<'parent, 'a> { let mut code = None; - list.parse_nested_meta(|nested| { - if nested.path.is_ident("code") { - let code_field = new_code_ident(); - let span = nested.path.span().unwrap(); - let formatting_init = build_suggestion_code( - &code_field, - nested, - self, - AllowMultipleAlternatives::No, - ); - code.set_once((code_field, formatting_init), span); - } else { - span_err( - nested.path.span().unwrap(), - "`code` is the only valid nested attribute", - ) - .emit(); + list.parse_args_with(|input: ParseStream<'_>| { + while !input.is_empty() { + let arg_name = input.parse::()?; + match arg_name.to_string().as_str() { + "code" => { + let code_field = new_code_ident(); + let formatting_init = build_suggestion_code( + &code_field, + input, + &self.fields, + AllowMultipleAlternatives::No, + )?; + code.set_once( + (code_field, formatting_init), + arg_name.span().unwrap(), + ); + } + _ => { + span_err( + arg_name.span().unwrap(), + "`code` is the only valid nested attribute", + ) + .emit(); + } + } + if input.is_empty() { + break; + } + input.parse::()?; } Ok(()) })?; @@ -492,8 +497,7 @@ impl<'parent, 'a> SubdiagnosticDeriveVariantBuilder<'parent, 'a> { pub(crate) fn into_tokens(&mut self) -> Result { let kind_slugs = self.identify_kind()?; - let kind_stats: KindsStatistics = - kind_slugs.iter().map(|(kind, _slug, _no_span)| kind).collect(); + let kind_stats: KindsStatistics = kind_slugs.iter().map(|(kind, _slug)| kind).collect(); let init = if kind_stats.has_multipart_suggestion { quote! { let mut suggestions = Vec::new(); } @@ -526,17 +530,13 @@ impl<'parent, 'a> SubdiagnosticDeriveVariantBuilder<'parent, 'a> { let diag = &self.parent.diag; let mut calls = TokenStream::new(); - for (kind, slug, no_span) in kind_slugs { + for (kind, slug) in kind_slugs { let message = format_ident!("__message"); calls.extend( quote! { let #message = #diag.eagerly_translate(crate::fluent_generated::#slug); }, ); - let name = format_ident!( - "{}{}", - if span_field.is_some() && !no_span { "span_" } else { "" }, - kind - ); + let name = format_ident!("{}{}", if span_field.is_some() { "span_" } else { "" }, kind); let call = match kind { SubdiagnosticKind::Suggestion { suggestion_kind, @@ -588,9 +588,7 @@ impl<'parent, 'a> SubdiagnosticDeriveVariantBuilder<'parent, 'a> { } } _ => { - if let Some(span) = span_field - && !no_span - { + if let Some(span) = span_field { quote! { #diag.#name(#span, #message); } } else { quote! { #diag.#name(#message); } diff --git a/compiler/rustc_macros/src/diagnostics/utils.rs b/compiler/rustc_macros/src/diagnostics/utils.rs index c310b99d5351..f084ba60ae3f 100644 --- a/compiler/rustc_macros/src/diagnostics/utils.rs +++ b/compiler/rustc_macros/src/diagnostics/utils.rs @@ -6,7 +6,7 @@ use std::str::FromStr; use proc_macro::Span; use proc_macro2::{Ident, TokenStream}; use quote::{ToTokens, format_ident, quote}; -use syn::meta::ParseNestedMeta; +use syn::parse::ParseStream; use syn::punctuated::Punctuated; use syn::spanned::Spanned; use syn::{Attribute, Field, LitStr, Meta, Path, Token, Type, TypeTuple, parenthesized}; @@ -261,108 +261,104 @@ impl SetOnce for SpannedOption { pub(super) type FieldMap = HashMap; -pub(crate) trait HasFieldMap { - /// Returns the binding for the field with the given name, if it exists on the type. - fn get_field_binding(&self, field: &String) -> Option<&TokenStream>; +/// In the strings in the attributes supplied to this macro, we want callers to be able to +/// reference fields in the format string. For example: +/// +/// ```ignore (not-usage-example) +/// /// Suggest `==` when users wrote `===`. +/// #[suggestion(slug = "parser-not-javascript-eq", code = "{lhs} == {rhs}")] +/// struct NotJavaScriptEq { +/// #[primary_span] +/// span: Span, +/// lhs: Ident, +/// rhs: Ident, +/// } +/// ``` +/// +/// We want to automatically pick up that `{lhs}` refers `self.lhs` and `{rhs}` refers to +/// `self.rhs`, then generate this call to `format!`: +/// +/// ```ignore (not-usage-example) +/// format!("{lhs} == {rhs}", lhs = self.lhs, rhs = self.rhs) +/// ``` +/// +/// This function builds the entire call to `format!`. +pub(super) fn build_format( + field_map: &FieldMap, + input: &str, + span: proc_macro2::Span, +) -> TokenStream { + // This set is used later to generate the final format string. To keep builds reproducible, + // the iteration order needs to be deterministic, hence why we use a `BTreeSet` here + // instead of a `HashSet`. + let mut referenced_fields: BTreeSet = BTreeSet::new(); - /// In the strings in the attributes supplied to this macro, we want callers to be able to - /// reference fields in the format string. For example: - /// - /// ```ignore (not-usage-example) - /// /// Suggest `==` when users wrote `===`. - /// #[suggestion(slug = "parser-not-javascript-eq", code = "{lhs} == {rhs}")] - /// struct NotJavaScriptEq { - /// #[primary_span] - /// span: Span, - /// lhs: Ident, - /// rhs: Ident, - /// } - /// ``` - /// - /// We want to automatically pick up that `{lhs}` refers `self.lhs` and `{rhs}` refers to - /// `self.rhs`, then generate this call to `format!`: - /// - /// ```ignore (not-usage-example) - /// format!("{lhs} == {rhs}", lhs = self.lhs, rhs = self.rhs) - /// ``` - /// - /// This function builds the entire call to `format!`. - fn build_format(&self, input: &str, span: proc_macro2::Span) -> TokenStream { - // This set is used later to generate the final format string. To keep builds reproducible, - // the iteration order needs to be deterministic, hence why we use a `BTreeSet` here - // instead of a `HashSet`. - let mut referenced_fields: BTreeSet = BTreeSet::new(); + // At this point, we can start parsing the format string. + let mut it = input.chars().peekable(); - // At this point, we can start parsing the format string. - let mut it = input.chars().peekable(); - - // Once the start of a format string has been found, process the format string and spit out - // the referenced fields. Leaves `it` sitting on the closing brace of the format string, so - // the next call to `it.next()` retrieves the next character. - while let Some(c) = it.next() { - if c != '{' { - continue; - } - if *it.peek().unwrap_or(&'\0') == '{' { - assert_eq!(it.next().unwrap(), '{'); - continue; - } - let mut eat_argument = || -> Option { - let mut result = String::new(); - // Format specifiers look like: - // - // format := '{' [ argument ] [ ':' format_spec ] '}' . - // - // Therefore, we only need to eat until ':' or '}' to find the argument. - while let Some(c) = it.next() { - result.push(c); - let next = *it.peek().unwrap_or(&'\0'); - if next == '}' { - break; - } else if next == ':' { - // Eat the ':' character. - assert_eq!(it.next().unwrap(), ':'); - break; - } - } - // Eat until (and including) the matching '}' - while it.next()? != '}' { - continue; - } - Some(result) - }; - - if let Some(referenced_field) = eat_argument() { - referenced_fields.insert(referenced_field); - } + // Once the start of a format string has been found, process the format string and spit out + // the referenced fields. Leaves `it` sitting on the closing brace of the format string, so + // the next call to `it.next()` retrieves the next character. + while let Some(c) = it.next() { + if c != '{' { + continue; } + if *it.peek().unwrap_or(&'\0') == '{' { + assert_eq!(it.next().unwrap(), '{'); + continue; + } + let mut eat_argument = || -> Option { + let mut result = String::new(); + // Format specifiers look like: + // + // format := '{' [ argument ] [ ':' format_spec ] '}' . + // + // Therefore, we only need to eat until ':' or '}' to find the argument. + while let Some(c) = it.next() { + result.push(c); + let next = *it.peek().unwrap_or(&'\0'); + if next == '}' { + break; + } else if next == ':' { + // Eat the ':' character. + assert_eq!(it.next().unwrap(), ':'); + break; + } + } + // Eat until (and including) the matching '}' + while it.next()? != '}' { + continue; + } + Some(result) + }; - // At this point, `referenced_fields` contains a set of the unique fields that were - // referenced in the format string. Generate the corresponding "x = self.x" format - // string parameters: - let args = referenced_fields.into_iter().map(|field: String| { - let field_ident = format_ident!("{}", field); - let value = match self.get_field_binding(&field) { - Some(value) => value.clone(), - // This field doesn't exist. Emit a diagnostic. - None => { - span_err( - span.unwrap(), - format!("`{field}` doesn't refer to a field on this type"), - ) + if let Some(referenced_field) = eat_argument() { + referenced_fields.insert(referenced_field); + } + } + + // At this point, `referenced_fields` contains a set of the unique fields that were + // referenced in the format string. Generate the corresponding "x = self.x" format + // string parameters: + let args = referenced_fields.into_iter().map(|field: String| { + let field_ident = format_ident!("{}", field); + let value = match field_map.get(&field) { + Some(value) => value.clone(), + // This field doesn't exist. Emit a diagnostic. + None => { + span_err(span.unwrap(), format!("`{field}` doesn't refer to a field on this type")) .emit(); - quote! { - "{#field}" - } + quote! { + "{#field}" } - }; - quote! { - #field_ident = #value } - }); + }; quote! { - format!(#input #(,#args)*) + #field_ident = #value } + }); + quote! { + format!(#input #(,#args)*) } } @@ -428,76 +424,63 @@ pub(super) enum AllowMultipleAlternatives { } fn parse_suggestion_values( - nested: ParseNestedMeta<'_>, + nested: ParseStream<'_>, allow_multiple: AllowMultipleAlternatives, ) -> syn::Result> { - let values = if let Ok(val) = nested.value() { - vec![val.parse()?] - } else { - let content; - parenthesized!(content in nested.input); + if nested.parse::().is_ok() { + return Ok(vec![nested.parse::()?]); + } - if let AllowMultipleAlternatives::No = allow_multiple { + let content; + parenthesized!(content in nested); + if let AllowMultipleAlternatives::No = allow_multiple { + span_err(content.span().unwrap(), "expected exactly one string literal for `code = ...`") + .emit(); + return Ok(vec![]); + } + + let literals = Punctuated::::parse_terminated(&content); + Ok(match literals { + Ok(p) if p.is_empty() => { span_err( - nested.input.span().unwrap(), - "expected exactly one string literal for `code = ...`", + content.span().unwrap(), + "expected at least one string literal for `code(...)`", ) .emit(); vec![] - } else { - let literals = Punctuated::::parse_terminated(&content); - - match literals { - Ok(p) if p.is_empty() => { - span_err( - content.span().unwrap(), - "expected at least one string literal for `code(...)`", - ) - .emit(); - vec![] - } - Ok(p) => p.into_iter().collect(), - Err(_) => { - span_err( - content.span().unwrap(), - "`code(...)` must contain only string literals", - ) - .emit(); - vec![] - } - } } - }; - - Ok(values) + Ok(p) => p.into_iter().collect(), + Err(_) => { + span_err(content.span().unwrap(), "`code(...)` must contain only string literals") + .emit(); + vec![] + } + }) } /// Constructs the `format!()` invocation(s) necessary for a `#[suggestion*(code = "foo")]` or /// `#[suggestion*(code("foo", "bar"))]` attribute field pub(super) fn build_suggestion_code( code_field: &Ident, - nested: ParseNestedMeta<'_>, - fields: &impl HasFieldMap, + nested: ParseStream<'_>, + fields: &FieldMap, allow_multiple: AllowMultipleAlternatives, -) -> TokenStream { - let values = match parse_suggestion_values(nested, allow_multiple) { - Ok(x) => x, - Err(e) => return e.into_compile_error(), - }; +) -> Result { + let values = parse_suggestion_values(nested, allow_multiple)?; - if let AllowMultipleAlternatives::Yes = allow_multiple { + Ok(if let AllowMultipleAlternatives::Yes = allow_multiple { let formatted_strings: Vec<_> = values .into_iter() - .map(|value| fields.build_format(&value.value(), value.span())) + .map(|value| build_format(fields, &value.value(), value.span())) .collect(); quote! { let #code_field = [#(#formatted_strings),*].into_iter(); } } else if let [value] = values.as_slice() { - let formatted_str = fields.build_format(&value.value(), value.span()); + let formatted_str = build_format(fields, &value.value(), value.span()); quote! { let #code_field = #formatted_str; } } else { // error handled previously quote! { let #code_field = String::new(); } - } + }) } /// Possible styles for suggestion subdiagnostics. @@ -605,16 +588,15 @@ pub(super) enum SubdiagnosticKind { pub(super) struct SubdiagnosticVariant { pub(super) kind: SubdiagnosticKind, pub(super) slug: Option, - pub(super) no_span: bool, } impl SubdiagnosticVariant { /// Constructs a `SubdiagnosticVariant` from a field or type attribute such as `#[note]`, - /// `#[error(parser::add_paren, no_span)]` or `#[suggestion(code = "...")]`. Returns the + /// `#[error(parser::add_paren)]` or `#[suggestion(code = "...")]`. Returns the /// `SubdiagnosticKind` and the diagnostic slug, if specified. pub(super) fn from_attr( attr: &Attribute, - fields: &impl HasFieldMap, + fields: &FieldMap, ) -> Result, DiagnosticDeriveError> { // Always allow documentation comments. if is_doc_comment(attr) { @@ -694,7 +676,7 @@ impl SubdiagnosticVariant { | SubdiagnosticKind::HelpOnce | SubdiagnosticKind::Warn | SubdiagnosticKind::MultipartSuggestion { .. } => { - return Ok(Some(SubdiagnosticVariant { kind, slug: None, no_span: false })); + return Ok(Some(SubdiagnosticVariant { kind, slug: None })); } SubdiagnosticKind::Suggestion { .. } => { throw_span_err!(span, "suggestion without `code = \"...\"`") @@ -709,112 +691,93 @@ impl SubdiagnosticVariant { let mut code = None; let mut suggestion_kind = None; - let mut first = true; let mut slug = None; - let mut no_span = false; - list.parse_nested_meta(|nested| { - if nested.input.is_empty() || nested.input.peek(Token![,]) { - if first { - slug = Some(nested.path); - } else if nested.path.is_ident("no_span") { - no_span = true; - } else { - span_err(nested.input.span().unwrap(), "a diagnostic slug must be the first argument to the attribute").emit(); + list.parse_args_with(|input: ParseStream<'_>| { + let mut is_first = true; + while !input.is_empty() { + let arg_name: Path = input.parse::()?; + let arg_name_span = arg_name.span().unwrap(); + if input.is_empty() || input.parse::().is_ok() { + if is_first { + slug = Some(arg_name); + is_first = false; + } else { + span_err(arg_name_span, "a diagnostic slug must be the first argument to the attribute").emit(); + } + continue } + is_first = false; - first = false; - return Ok(()); - } + match (arg_name.require_ident()?.to_string().as_str(), &mut kind) { + ("code", SubdiagnosticKind::Suggestion { code_field, .. }) => { + let code_init = build_suggestion_code( + &code_field, + &input, + fields, + AllowMultipleAlternatives::Yes, + )?; + code.set_once(code_init, arg_name_span); + } + ( + "applicability", + SubdiagnosticKind::Suggestion { applicability, .. } + | SubdiagnosticKind::MultipartSuggestion { applicability, .. }, + ) => { + input.parse::()?; + let value = input.parse::()?; + let value = Applicability::from_str(&value.value()).unwrap_or_else(|()| { + span_err(value.span().unwrap(), "invalid applicability").emit(); + Applicability::Unspecified + }); + applicability.set_once(value, span); + } + ( + "style", + SubdiagnosticKind::Suggestion { .. } + | SubdiagnosticKind::MultipartSuggestion { .. }, + ) => { + input.parse::()?; + let value = input.parse::()?; - first = false; + let value = value.value().parse().unwrap_or_else(|()| { + span_err(value.span().unwrap(), "invalid suggestion style") + .help("valid styles are `normal`, `short`, `hidden`, `verbose` and `tool-only`") + .emit(); + SuggestionKind::Normal + }); - let nested_name = nested.path.segments.last().unwrap().ident.to_string(); - let nested_name = nested_name.as_str(); + suggestion_kind.set_once(value, span); + } - let path_span = nested.path.span().unwrap(); - let val_span = nested.input.span().unwrap(); - macro_rules! get_string { - () => {{ - let Ok(value) = nested.value().and_then(|x| x.parse::()) else { - span_err(val_span, "expected `= \"xxx\"`").emit(); - return Ok(()); - }; - value - }}; - } - - let mut has_errors = false; - let input = nested.input; - - match (nested_name, &mut kind) { - ("code", SubdiagnosticKind::Suggestion { code_field, .. }) => { - let code_init = build_suggestion_code( - code_field, - nested, - fields, - AllowMultipleAlternatives::Yes, - ); - code.set_once(code_init, path_span); - } - ( - "applicability", - SubdiagnosticKind::Suggestion { applicability, .. } - | SubdiagnosticKind::MultipartSuggestion { applicability, .. }, - ) => { - let value = get_string!(); - let value = Applicability::from_str(&value.value()).unwrap_or_else(|()| { - span_err(value.span().unwrap(), "invalid applicability").emit(); - has_errors = true; - Applicability::Unspecified - }); - applicability.set_once(value, span); - } - ( - "style", - SubdiagnosticKind::Suggestion { .. } - | SubdiagnosticKind::MultipartSuggestion { .. }, - ) => { - let value = get_string!(); - - let value = value.value().parse().unwrap_or_else(|()| { - span_err(value.span().unwrap(), "invalid suggestion style") - .help("valid styles are `normal`, `short`, `hidden`, `verbose` and `tool-only`") + // Invalid nested attribute + (_, SubdiagnosticKind::Suggestion { .. }) => { + span_err(arg_name_span, "invalid nested attribute") + .help( + "only `style`, `code` and `applicability` are valid nested attributes", + ) .emit(); - has_errors = true; - SuggestionKind::Normal - }); - - suggestion_kind.set_once(value, span); + // Consume the rest of the input to avoid spamming errors + let _ = input.parse::(); + } + (_, SubdiagnosticKind::MultipartSuggestion { .. }) => { + span_err(arg_name_span, "invalid nested attribute") + .help("only `style` and `applicability` are valid nested attributes") + .emit(); + // Consume the rest of the input to avoid spamming errors + let _ = input.parse::(); + } + _ => { + span_err(arg_name_span, "no nested attribute expected here").emit(); + // Consume the rest of the input to avoid spamming errors + let _ = input.parse::(); + } } - // Invalid nested attribute - (_, SubdiagnosticKind::Suggestion { .. }) => { - span_err(path_span, "invalid nested attribute") - .help( - "only `no_span`, `style`, `code` and `applicability` are valid nested attributes", - ) - .emit(); - has_errors = true; - } - (_, SubdiagnosticKind::MultipartSuggestion { .. }) => { - span_err(path_span, "invalid nested attribute") - .help("only `no_span`, `style` and `applicability` are valid nested attributes") - .emit(); - has_errors = true; - } - _ => { - span_err(path_span, "only `no_span` is a valid nested attribute").emit(); - has_errors = true; - } + if input.is_empty() { break } + input.parse::()?; } - - if has_errors { - // Consume the rest of the input to avoid spamming errors - let _ = input.parse::(); - } - Ok(()) })?; @@ -851,7 +814,7 @@ impl SubdiagnosticVariant { | SubdiagnosticKind::Warn => {} } - Ok(Some(SubdiagnosticVariant { kind, slug, no_span })) + Ok(Some(SubdiagnosticVariant { kind, slug })) } } diff --git a/compiler/rustc_middle/src/middle/resolve_bound_vars.rs b/compiler/rustc_middle/src/middle/resolve_bound_vars.rs index 51a079e8bc12..d625e9ea08cc 100644 --- a/compiler/rustc_middle/src/middle/resolve_bound_vars.rs +++ b/compiler/rustc_middle/src/middle/resolve_bound_vars.rs @@ -48,7 +48,7 @@ pub enum ObjectLifetimeDefault { /// Maps the id of each bound variable reference to the variable decl /// that it corresponds to. #[derive(Debug, Default, HashStable)] -pub struct ResolveBoundVars { +pub struct ResolveBoundVars<'tcx> { // Maps from every use of a named (not anonymous) bound var to a // `ResolvedArg` describing how that variable is bound. pub defs: SortedMap, @@ -59,7 +59,7 @@ pub struct ResolveBoundVars { // - closures // - trait refs // - bound types (like `T` in `for<'a> T<'a>: Foo`) - pub late_bound_vars: SortedMap>, + pub late_bound_vars: SortedMap>>, // List captured variables for each opaque type. pub opaque_captured_lifetimes: LocalDefIdMap>, diff --git a/compiler/rustc_middle/src/query/erase.rs b/compiler/rustc_middle/src/query/erase.rs index 940cc30c17e6..32071595ec28 100644 --- a/compiler/rustc_middle/src/query/erase.rs +++ b/compiler/rustc_middle/src/query/erase.rs @@ -1,3 +1,10 @@ +//! To improve compile times and code size for the compiler itself, query +//! values are "erased" in some contexts (e.g. inside in-memory cache types), +//! to reduce the number of generic instantiations created during codegen. +//! +//! See for some bootstrap-time +//! and performance benchmarks. + use std::ffi::OsStr; use std::intrinsics::transmute_unchecked; use std::mem::MaybeUninit; @@ -14,138 +21,169 @@ use crate::ty::adjustment::CoerceUnsizedInfo; use crate::ty::{self, Ty, TyCtxt}; use crate::{mir, traits}; +/// Internal implementation detail of [`Erased`]. #[derive(Copy, Clone)] -pub struct Erased { - // We use `MaybeUninit` here so we can store any value - // in `data` since we aren't actually storing a `T`. - data: MaybeUninit, +pub struct ErasedData { + /// We use `MaybeUninit` here to make sure it's legal to store a transmuted + /// value that isn't actually of type `Storage`. + data: MaybeUninit, } -pub trait EraseType: Copy { - type Result: Copy; +/// Trait for types that can be erased into [`Erased`]. +/// +/// Erasing and unerasing values is performed by [`erase_val`] and [`restore_val`]. +/// +/// FIXME: This whole trait could potentially be replaced by `T: Copy` and the +/// storage type `[u8; size_of::()]` when support for that is more mature. +pub trait Erasable: Copy { + /// Storage type to used for erased values of this type. + /// Should be `[u8; N]`, where N is equal to `size_of::`. + /// + /// [`ErasedData`] wraps this storage type in `MaybeUninit` to ensure that + /// transmutes to/from erased storage are well-defined. + type Storage: Copy; } -// Allow `type_alias_bounds` since compilation will fail without `EraseType`. -#[allow(type_alias_bounds)] -pub type Erase = Erased; +/// A value of `T` that has been "erased" into some opaque storage type. +/// +/// This is helpful for reducing the number of concrete instantiations needed +/// during codegen when building the compiler. +/// +/// Using an opaque type alias allows the type checker to enforce that +/// `Erased` and `Erased` are still distinct types, while allowing +/// monomorphization to see that they might actually use the same storage type. +pub type Erased = ErasedData; +/// Erases a value of type `T` into `Erased`. +/// +/// `Erased` and `Erased` are type-checked as distinct types, but codegen +/// can see whether they actually have the same storage type. +/// +/// FIXME: This might have soundness issues with erasable types that don't +/// implement the same auto-traits as `[u8; _]`; see +/// #[inline(always)] -#[define_opaque(Erase)] -pub fn erase(src: T) -> Erase { +#[define_opaque(Erased)] +pub fn erase_val(value: T) -> Erased { // Ensure the sizes match const { - if size_of::() != size_of::() { - panic!("size of T must match erased type T::Result") + if size_of::() != size_of::() { + panic!("size of T must match erased type ::Storage") } }; - Erased::<::Result> { + ErasedData::<::Storage> { // `transmute_unchecked` is needed here because it does not have `transmute`'s size check - // (and thus allows to transmute between `T` and `MaybeUninit`) (we do the size + // (and thus allows to transmute between `T` and `MaybeUninit`) (we do the size // check ourselves in the `const` block above). // // `transmute_copy` is also commonly used for this (and it would work here since - // `EraseType: Copy`), but `transmute_unchecked` better explains the intent. + // `Erasable: Copy`), but `transmute_unchecked` better explains the intent. // // SAFETY: It is safe to transmute to MaybeUninit for types with the same sizes. - data: unsafe { transmute_unchecked::>(src) }, + data: unsafe { transmute_unchecked::>(value) }, } } -/// Restores an erased value. +/// Restores an erased value to its real type. +/// +/// This relies on the fact that `Erased` and `Erased` are type-checked +/// as distinct types, even if they use the same storage type. #[inline(always)] -#[define_opaque(Erase)] -pub fn restore(value: Erase) -> T { - let value: Erased<::Result> = value; - // See comment in `erase` for why we use `transmute_unchecked`. +#[define_opaque(Erased)] +pub fn restore_val(erased_value: Erased) -> T { + let ErasedData { data }: ErasedData<::Storage> = erased_value; + // See comment in `erase_val` for why we use `transmute_unchecked`. // - // SAFETY: Due to the use of impl Trait in `Erase` the only way to safely create an instance - // of `Erase` is to call `erase`, so we know that `value.data` is a valid instance of `T` of - // the right size. - unsafe { transmute_unchecked::, T>(value.data) } + // SAFETY: Due to the use of impl Trait in `Erased` the only way to safely create an instance + // of `Erased` is to call `erase_val`, so we know that `erased_value.data` is a valid instance + // of `T` of the right size. + unsafe { transmute_unchecked::, T>(data) } } -impl EraseType for &'_ T { - type Result = [u8; size_of::<&'static ()>()]; +// FIXME(#151565): Using `T: ?Sized` here should let us remove the separate +// impls for fat reference types. +impl Erasable for &'_ T { + type Storage = [u8; size_of::<&'static ()>()]; } -impl EraseType for &'_ [T] { - type Result = [u8; size_of::<&'static [()]>()]; +impl Erasable for &'_ [T] { + type Storage = [u8; size_of::<&'static [()]>()]; } -impl EraseType for &'_ OsStr { - type Result = [u8; size_of::<&'static OsStr>()]; +impl Erasable for &'_ OsStr { + type Storage = [u8; size_of::<&'static OsStr>()]; } -impl EraseType for &'_ ty::List { - type Result = [u8; size_of::<&'static ty::List<()>>()]; +impl Erasable for &'_ ty::List { + type Storage = [u8; size_of::<&'static ty::List<()>>()]; } -impl EraseType for &'_ ty::ListWithCachedTypeInfo { - type Result = [u8; size_of::<&'static ty::ListWithCachedTypeInfo<()>>()]; +impl Erasable for &'_ ty::ListWithCachedTypeInfo { + type Storage = [u8; size_of::<&'static ty::ListWithCachedTypeInfo<()>>()]; } -impl EraseType for &'_ rustc_index::IndexSlice { - type Result = [u8; size_of::<&'static rustc_index::IndexSlice>()]; +impl Erasable for &'_ rustc_index::IndexSlice { + type Storage = [u8; size_of::<&'static rustc_index::IndexSlice>()]; } -impl EraseType for Result<&'_ T, traits::query::NoSolution> { - type Result = [u8; size_of::>()]; +impl Erasable for Result<&'_ T, traits::query::NoSolution> { + type Storage = [u8; size_of::>()]; } -impl EraseType for Result<&'_ [T], traits::query::NoSolution> { - type Result = [u8; size_of::>()]; +impl Erasable for Result<&'_ [T], traits::query::NoSolution> { + type Storage = [u8; size_of::>()]; } -impl EraseType for Result<&'_ T, rustc_errors::ErrorGuaranteed> { - type Result = [u8; size_of::>()]; +impl Erasable for Result<&'_ T, rustc_errors::ErrorGuaranteed> { + type Storage = [u8; size_of::>()]; } -impl EraseType for Result<&'_ [T], rustc_errors::ErrorGuaranteed> { - type Result = [u8; size_of::>()]; +impl Erasable for Result<&'_ [T], rustc_errors::ErrorGuaranteed> { + type Storage = [u8; size_of::>()]; } -impl EraseType for Result<&'_ T, traits::CodegenObligationError> { - type Result = [u8; size_of::>()]; +impl Erasable for Result<&'_ T, traits::CodegenObligationError> { + type Storage = [u8; size_of::>()]; } -impl EraseType for Result<&'_ T, &'_ ty::layout::FnAbiError<'_>> { - type Result = [u8; size_of::>>()]; +impl Erasable for Result<&'_ T, &'_ ty::layout::FnAbiError<'_>> { + type Storage = [u8; size_of::>>()]; } -impl EraseType for Result<(&'_ T, crate::thir::ExprId), rustc_errors::ErrorGuaranteed> { - type Result = [u8; size_of::< +impl Erasable for Result<(&'_ T, crate::thir::ExprId), rustc_errors::ErrorGuaranteed> { + type Storage = [u8; size_of::< Result<(&'static (), crate::thir::ExprId), rustc_errors::ErrorGuaranteed>, >()]; } -impl EraseType for Result>, rustc_errors::ErrorGuaranteed> { - type Result = +impl Erasable for Result>, rustc_errors::ErrorGuaranteed> { + type Storage = [u8; size_of::>, rustc_errors::ErrorGuaranteed>>()]; } -impl EraseType for Result { - type Result = [u8; size_of::>()]; +impl Erasable for Result { + type Storage = [u8; size_of::>()]; } -impl EraseType +impl Erasable for Result>>, rustc_errors::ErrorGuaranteed> { - type Result = [u8; size_of::< + type Storage = [u8; size_of::< Result>>, rustc_errors::ErrorGuaranteed>, >()]; } -impl EraseType for Result, traits::query::NoSolution> { - type Result = [u8; size_of::, traits::query::NoSolution>>()]; +impl Erasable for Result, traits::query::NoSolution> { + type Storage = [u8; size_of::, traits::query::NoSolution>>()]; } -impl EraseType for Result> { - type Result = [u8; size_of::>>()]; +impl Erasable for Result> { + type Storage = [u8; size_of::>>()]; } -impl EraseType for Result>, &ty::layout::LayoutError<'_>> { - type Result = [u8; size_of::< +impl Erasable for Result>, &ty::layout::LayoutError<'_>> { + type Storage = [u8; size_of::< Result< rustc_abi::TyAndLayout<'static, Ty<'static>>, &'static ty::layout::LayoutError<'static>, @@ -153,35 +191,36 @@ impl EraseType for Result>, &ty::layout::Layou >()]; } -impl EraseType for Result, mir::interpret::ErrorHandled> { - type Result = [u8; size_of::, mir::interpret::ErrorHandled>>()]; +impl Erasable for Result, mir::interpret::ErrorHandled> { + type Storage = + [u8; size_of::, mir::interpret::ErrorHandled>>()]; } -impl EraseType for Result { - type Result = [u8; size_of::>()]; +impl Erasable for Result { + type Storage = [u8; size_of::>()]; } -impl EraseType for Option<(mir::ConstValue, Ty<'_>)> { - type Result = [u8; size_of::)>>()]; +impl Erasable for Option<(mir::ConstValue, Ty<'_>)> { + type Storage = [u8; size_of::)>>()]; } -impl EraseType for EvalToValTreeResult<'_> { - type Result = [u8; size_of::>()]; +impl Erasable for EvalToValTreeResult<'_> { + type Storage = [u8; size_of::>()]; } -impl EraseType for Result<&'_ ty::List>, ty::util::AlwaysRequiresDrop> { - type Result = +impl Erasable for Result<&'_ ty::List>, ty::util::AlwaysRequiresDrop> { + type Storage = [u8; size_of::>, ty::util::AlwaysRequiresDrop>>()]; } -impl EraseType for Result>, CyclePlaceholder> { - type Result = [u8; size_of::>, CyclePlaceholder>>()]; +impl Erasable for Result>, CyclePlaceholder> { + type Storage = [u8; size_of::>, CyclePlaceholder>>()]; } -impl EraseType +impl Erasable for Result<(&'_ [Spanned>], &'_ [Spanned>]), NormalizationErrorInMono> { - type Result = [u8; size_of::< + type Storage = [u8; size_of::< Result< (&'static [Spanned>], &'static [Spanned>]), NormalizationErrorInMono, @@ -189,86 +228,89 @@ impl EraseType >()]; } -impl EraseType for Result<&'_ TokenStream, ()> { - type Result = [u8; size_of::>()]; +impl Erasable for Result<&'_ TokenStream, ()> { + type Storage = [u8; size_of::>()]; } -impl EraseType for Option<&'_ T> { - type Result = [u8; size_of::>()]; +impl Erasable for Option<&'_ T> { + type Storage = [u8; size_of::>()]; } -impl EraseType for Option<&'_ [T]> { - type Result = [u8; size_of::>()]; +impl Erasable for Option<&'_ [T]> { + type Storage = [u8; size_of::>()]; } -impl EraseType for Option<&'_ OsStr> { - type Result = [u8; size_of::>()]; +impl Erasable for Option<&'_ OsStr> { + type Storage = [u8; size_of::>()]; } -impl EraseType for Option> { - type Result = [u8; size_of::>>()]; +impl Erasable for Option> { + type Storage = [u8; size_of::>>()]; } -impl EraseType for ty::ImplTraitHeader<'_> { - type Result = [u8; size_of::>()]; +impl Erasable for ty::ImplTraitHeader<'_> { + type Storage = [u8; size_of::>()]; } -impl EraseType for Option>> { - type Result = [u8; size_of::>>>()]; +impl Erasable for Option>> { + type Storage = [u8; size_of::>>>()]; } -impl EraseType for rustc_hir::MaybeOwner<'_> { - type Result = [u8; size_of::>()]; +impl Erasable for rustc_hir::MaybeOwner<'_> { + type Storage = [u8; size_of::>()]; } -impl EraseType for ty::EarlyBinder<'_, T> { - type Result = T::Result; +impl Erasable for ty::EarlyBinder<'_, T> { + type Storage = T::Storage; } -impl EraseType for ty::Binder<'_, ty::FnSig<'_>> { - type Result = [u8; size_of::>>()]; +impl Erasable for ty::Binder<'_, ty::FnSig<'_>> { + type Storage = [u8; size_of::>>()]; } -impl EraseType for ty::Binder<'_, ty::CoroutineWitnessTypes>> { - type Result = +impl Erasable for ty::Binder<'_, ty::CoroutineWitnessTypes>> { + type Storage = [u8; size_of::>>>()]; } -impl EraseType for ty::Binder<'_, &'_ ty::List>> { - type Result = [u8; size_of::>>>()]; +impl Erasable for ty::Binder<'_, &'_ ty::List>> { + type Storage = [u8; size_of::>>>()]; } -impl EraseType for (&'_ T0, &'_ T1) { - type Result = [u8; size_of::<(&'static (), &'static ())>()]; +impl Erasable for (&'_ T0, &'_ T1) { + type Storage = [u8; size_of::<(&'static (), &'static ())>()]; } -impl EraseType for (solve::QueryResult<'_>, &'_ T0) { - type Result = [u8; size_of::<(solve::QueryResult<'static>, &'static ())>()]; +impl Erasable for (solve::QueryResult<'_>, &'_ T0) { + type Storage = [u8; size_of::<(solve::QueryResult<'static>, &'static ())>()]; } -impl EraseType for (&'_ T0, &'_ [T1]) { - type Result = [u8; size_of::<(&'static (), &'static [()])>()]; +impl Erasable for (&'_ T0, &'_ [T1]) { + type Storage = [u8; size_of::<(&'static (), &'static [()])>()]; } -impl EraseType for (&'_ [T0], &'_ [T1]) { - type Result = [u8; size_of::<(&'static [()], &'static [()])>()]; +impl Erasable for (&'_ [T0], &'_ [T1]) { + type Storage = [u8; size_of::<(&'static [()], &'static [()])>()]; } -impl EraseType for (&'_ T0, Result<(), ErrorGuaranteed>) { - type Result = [u8; size_of::<(&'static (), Result<(), ErrorGuaranteed>)>()]; +impl Erasable for (&'_ T0, Result<(), ErrorGuaranteed>) { + type Storage = [u8; size_of::<(&'static (), Result<(), ErrorGuaranteed>)>()]; } -macro_rules! trivial { +macro_rules! impl_erasable_for_simple_types { ($($ty:ty),+ $(,)?) => { $( - impl EraseType for $ty { - type Result = [u8; size_of::<$ty>()]; + impl Erasable for $ty { + type Storage = [u8; size_of::<$ty>()]; } )* } } -trivial! { +// For concrete types with no lifetimes, the erased storage for `Foo` is +// `[u8; size_of::()]`. +impl_erasable_for_simple_types! { + // FIXME(#151565): Add `tidy-alphabetical-{start,end}` and sort this. (), bool, Option<(rustc_span::def_id::DefId, rustc_session::config::EntryFnType)>, @@ -346,7 +388,6 @@ trivial! { rustc_middle::ty::AssocContainer, rustc_middle::ty::Asyncness, rustc_middle::ty::AsyncDestructor, - rustc_middle::ty::BoundVariableKind, rustc_middle::ty::AnonConstKind, rustc_middle::ty::Destructor, rustc_middle::ty::fast_reject::SimplifiedType, @@ -378,17 +419,23 @@ trivial! { usize, } -macro_rules! tcx_lifetime { +macro_rules! impl_erasable_for_single_lifetime_types { ($($($fake_path:ident)::+),+ $(,)?) => { $( - impl<'tcx> EraseType for $($fake_path)::+<'tcx> { - type Result = [u8; size_of::<$($fake_path)::+<'static>>()]; + impl<'tcx> Erasable for $($fake_path)::+<'tcx> { + type Storage = [u8; size_of::<$($fake_path)::+<'static>>()]; } )* } } -tcx_lifetime! { +// For types containing a single lifetime and no other generics, e.g. +// `Foo<'tcx>`, the erased storage is `[u8; size_of::>()]`. +// +// FIXME(#151565): Some of the hand-written impls above that only use one +// lifetime can probably be migrated here. +impl_erasable_for_single_lifetime_types! { + // FIXME(#151565): Add `tidy-alphabetical-{start,end}` and sort this. rustc_middle::middle::exported_symbols::ExportedSymbol, rustc_middle::mir::Const, rustc_middle::mir::DestructuredConstant, @@ -415,6 +462,7 @@ tcx_lifetime! { rustc_middle::ty::ConstConditions, rustc_middle::ty::inhabitedness::InhabitedPredicate, rustc_middle::ty::Instance, + rustc_middle::ty::BoundVariableKind, rustc_middle::ty::InstanceKind, rustc_middle::ty::layout::FnAbiError, rustc_middle::ty::layout::LayoutError, diff --git a/compiler/rustc_middle/src/query/inner.rs b/compiler/rustc_middle/src/query/inner.rs index ee828ae55f7a..e41d23f82f12 100644 --- a/compiler/rustc_middle/src/query/inner.rs +++ b/compiler/rustc_middle/src/query/inner.rs @@ -11,7 +11,7 @@ use rustc_span::{DUMMY_SP, ErrorGuaranteed, Span}; use crate::dep_graph; use crate::query::IntoQueryParam; -use crate::query::erase::{self, Erase, EraseType}; +use crate::query::erase::{self, Erasable, Erased}; use crate::ty::TyCtxt; /// Shared implementation of `tcx.$query(..)` and `tcx.at(span).$query(..)` @@ -63,15 +63,15 @@ pub(crate) fn query_ensure_error_guaranteed<'tcx, Cache, T>( check_cache: bool, ) -> Result<(), ErrorGuaranteed> where - Cache: QueryCache>>, - Result: EraseType, + Cache: QueryCache>>, + Result: Erasable, { let key = key.into_query_param(); if let Some(res) = try_get_cached(tcx, query_cache, &key) { - erase::restore(res).map(drop) + erase::restore_val(res).map(drop) } else { execute_query(tcx, DUMMY_SP, key, QueryMode::Ensure { check_cache }) - .map(erase::restore) + .map(erase::restore_val) .map(|res| res.map(drop)) // Either we actually executed the query, which means we got a full `Result`, // or we can just assume the query succeeded, because it was green in the @@ -90,17 +90,17 @@ pub(crate) fn query_feed<'tcx, Cache, Value>( hasher: Option, &Value) -> Fingerprint>, cache: &Cache, key: Cache::Key, - erased: Erase, + erased: Erased, ) where - Cache: QueryCache>, + Cache: QueryCache>, Cache::Key: DepNodeParams>, - Value: EraseType + Debug, + Value: Erasable + Debug, { - let value = erase::restore::(erased); + let value = erase::restore_val::(erased); match try_get_cached(tcx, cache, &key) { Some(old) => { - let old = erase::restore::(old); + let old = erase::restore_val::(old); if let Some(hasher) = hasher { let (value_hash, old_hash): (Fingerprint, Fingerprint) = tcx .with_stable_hashing_context(|mut hcx| { diff --git a/compiler/rustc_middle/src/query/mod.rs b/compiler/rustc_middle/src/query/mod.rs index 0a4faa1b6247..ad63251363e2 100644 --- a/compiler/rustc_middle/src/query/mod.rs +++ b/compiler/rustc_middle/src/query/mod.rs @@ -121,8 +121,7 @@ use crate::mir::interpret::{ use crate::mir::mono::{ CodegenUnit, CollectionMode, MonoItem, MonoItemPartitions, NormalizationErrorInMono, }; -use crate::query::erase::{Erase, erase, restore}; -use crate::query::plumbing::{CyclePlaceholder, DynamicQuery}; +use crate::query::plumbing::CyclePlaceholder; use crate::traits::query::{ CanonicalAliasGoal, CanonicalDropckOutlivesGoal, CanonicalImpliedOutlivesBoundsGoal, CanonicalMethodAutoderefStepsGoal, CanonicalPredicateGoal, CanonicalTypeOpAscribeUserTypeGoal, @@ -2116,7 +2115,7 @@ rustc_queries! { /// Does lifetime resolution on items. Importantly, we can't resolve /// lifetimes directly on things like trait methods, because of trait params. /// See `rustc_resolve::late::lifetimes` for details. - query resolve_bound_vars(owner_id: hir::OwnerId) -> &'tcx ResolveBoundVars { + query resolve_bound_vars(owner_id: hir::OwnerId) -> &'tcx ResolveBoundVars<'tcx> { arena_cache desc { |tcx| "resolving lifetimes for `{}`", tcx.def_path_str(owner_id) } } @@ -2145,7 +2144,7 @@ rustc_queries! { separate_provide_extern } query late_bound_vars_map(owner_id: hir::OwnerId) - -> &'tcx SortedMap> { + -> &'tcx SortedMap>> { desc { |tcx| "looking up late bound vars inside `{}`", tcx.def_path_str(owner_id) } } /// For an opaque type, return the list of (captured lifetime, inner generic param). diff --git a/compiler/rustc_middle/src/query/plumbing.rs b/compiler/rustc_middle/src/query/plumbing.rs index 9ee8d743e64a..7b85dac41aef 100644 --- a/compiler/rustc_middle/src/query/plumbing.rs +++ b/compiler/rustc_middle/src/query/plumbing.rs @@ -14,11 +14,14 @@ use crate::dep_graph; use crate::dep_graph::DepKind; use crate::query::on_disk_cache::{CacheEncoder, EncodedDepNodeIndex, OnDiskCache}; use crate::query::{ - DynamicQueries, ExternProviders, Providers, QueryArenas, QueryCaches, QueryEngine, QueryStates, + ExternProviders, PerQueryVTables, Providers, QueryArenas, QueryCaches, QueryEngine, QueryStates, }; use crate::ty::TyCtxt; -pub struct DynamicQuery<'tcx, C: QueryCache> { +/// Stores function pointers and other metadata for a particular query. +/// +/// Used indirectly by query plumbing in `rustc_query_system`, via a trait. +pub struct QueryVTable<'tcx, C: QueryCache> { pub name: &'static str, pub eval_always: bool, pub dep_kind: DepKind, @@ -62,7 +65,7 @@ pub struct QuerySystem<'tcx> { pub states: QueryStates<'tcx>, pub arenas: WorkerLocal>, pub caches: QueryCaches<'tcx>, - pub dynamic_queries: DynamicQueries<'tcx>, + pub query_vtables: PerQueryVTables<'tcx>, /// This provides access to the incremental compilation on-disk cache for query results. /// Do not access this directly. It is only meant to be used by @@ -263,6 +266,7 @@ macro_rules! define_callbacks { pub mod queries { $(pub mod $name { use super::super::*; + use $crate::query::erase::{self, Erased}; pub type Key<'tcx> = $($K)*; pub type Value<'tcx> = $V; @@ -285,29 +289,33 @@ macro_rules! define_callbacks { #[inline(always)] pub fn provided_to_erased<'tcx>( _tcx: TyCtxt<'tcx>, - value: ProvidedValue<'tcx>, - ) -> Erase> { - erase(query_if_arena!([$($modifiers)*] + provided_value: ProvidedValue<'tcx>, + ) -> Erased> { + // Store the provided value in an arena and get a reference + // to it, for queries with `arena_cache`. + let value: Value<'tcx> = query_if_arena!([$($modifiers)*] { use $crate::query::arena_cached::ArenaCached; if mem::needs_drop::<<$V as ArenaCached<'tcx>>::Allocated>() { <$V as ArenaCached>::alloc_in_arena( |v| _tcx.query_system.arenas.$name.alloc(v), - value, + provided_value, ) } else { <$V as ArenaCached>::alloc_in_arena( |v| _tcx.arena.dropless.alloc(v), - value, + provided_value, ) } } - (value) - )) + // Otherwise, the provided value is the value. + (provided_value) + ); + erase::erase_val(value) } - pub type Storage<'tcx> = <$($K)* as keys::Key>::Cache>; + pub type Storage<'tcx> = <$($K)* as keys::Key>::Cache>; // Ensure that keys grow no larger than 88 bytes by accident. // Increase this limit if necessary, but do try to keep the size low if possible @@ -408,7 +416,9 @@ macro_rules! define_callbacks { #[inline(always)] pub fn $name(self, key: query_helper_param_ty!($($K)*)) -> $V { - restore::<$V>(crate::query::inner::query_get_at( + use $crate::query::{erase, inner}; + + erase::restore_val::<$V>(inner::query_get_at( self.tcx, self.tcx.query_system.fns.engine.$name, &self.tcx.query_system.caches.$name, @@ -418,9 +428,12 @@ macro_rules! define_callbacks { })* } - pub struct DynamicQueries<'tcx> { + /// Holds a `QueryVTable` for each query. + /// + /// ("Per" just makes this pluralized name more visually distinct.) + pub struct PerQueryVTables<'tcx> { $( - pub $name: DynamicQuery<'tcx, queries::$name::Storage<'tcx>>, + pub $name: ::rustc_middle::query::plumbing::QueryVTable<'tcx, queries::$name::Storage<'tcx>>, )* } @@ -474,7 +487,7 @@ macro_rules! define_callbacks { Span, queries::$name::Key<'tcx>, QueryMode, - ) -> Option>,)* + ) -> Option<$crate::query::erase::Erased<$V>>,)* } }; } diff --git a/compiler/rustc_middle/src/ty/codec.rs b/compiler/rustc_middle/src/ty/codec.rs index 75b1317e022b..4856df3a6222 100644 --- a/compiler/rustc_middle/src/ty/codec.rs +++ b/compiler/rustc_middle/src/ty/codec.rs @@ -427,11 +427,11 @@ impl<'tcx, D: TyDecoder<'tcx>> RefDecodable<'tcx, D> for [Spanned } } -impl<'tcx, D: TyDecoder<'tcx>> RefDecodable<'tcx, D> for ty::List { +impl<'tcx, D: TyDecoder<'tcx>> RefDecodable<'tcx, D> for ty::List> { fn decode(decoder: &mut D) -> &'tcx Self { let len = decoder.read_usize(); decoder.interner().mk_bound_variable_kinds_from_iter( - (0..len).map::(|_| Decodable::decode(decoder)), + (0..len).map::, _>(|_| Decodable::decode(decoder)), ) } } @@ -495,7 +495,7 @@ impl_decodable_via_ref! { &'tcx ty::List>, &'tcx traits::ImplSource<'tcx, ()>, &'tcx mir::Body<'tcx>, - &'tcx ty::List, + &'tcx ty::List>, &'tcx ty::List>, &'tcx ty::ListWithCachedTypeInfo>, } diff --git a/compiler/rustc_middle/src/ty/consts.rs b/compiler/rustc_middle/src/ty/consts.rs index da3caf0bb210..5581ad5669aa 100644 --- a/compiler/rustc_middle/src/ty/consts.rs +++ b/compiler/rustc_middle/src/ty/consts.rs @@ -94,7 +94,7 @@ impl<'tcx> Const<'tcx> { pub fn new_bound( tcx: TyCtxt<'tcx>, debruijn: ty::DebruijnIndex, - bound_const: ty::BoundConst, + bound_const: ty::BoundConst<'tcx>, ) -> Const<'tcx> { Const::new(tcx, ty::ConstKind::Bound(ty::BoundVarIndexKind::Bound(debruijn), bound_const)) } @@ -103,7 +103,7 @@ impl<'tcx> Const<'tcx> { pub fn new_canonical_bound(tcx: TyCtxt<'tcx>, var: ty::BoundVar) -> Const<'tcx> { Const::new( tcx, - ty::ConstKind::Bound(ty::BoundVarIndexKind::Canonical, ty::BoundConst { var }), + ty::ConstKind::Bound(ty::BoundVarIndexKind::Canonical, ty::BoundConst::new(var)), ) } @@ -183,13 +183,13 @@ impl<'tcx> rustc_type_ir::inherent::Const> for Const<'tcx> { fn new_bound( interner: TyCtxt<'tcx>, debruijn: ty::DebruijnIndex, - bound_const: ty::BoundConst, + bound_const: ty::BoundConst<'tcx>, ) -> Self { Const::new_bound(interner, debruijn, bound_const) } fn new_anon_bound(tcx: TyCtxt<'tcx>, debruijn: ty::DebruijnIndex, var: ty::BoundVar) -> Self { - Const::new_bound(tcx, debruijn, ty::BoundConst { var }) + Const::new_bound(tcx, debruijn, ty::BoundConst::new(var)) } fn new_canonical_bound(tcx: TyCtxt<'tcx>, var: rustc_type_ir::BoundVar) -> Self { diff --git a/compiler/rustc_middle/src/ty/context.rs b/compiler/rustc_middle/src/ty/context.rs index f015d0edc56c..a6960523f6cf 100644 --- a/compiler/rustc_middle/src/ty/context.rs +++ b/compiler/rustc_middle/src/ty/context.rs @@ -108,9 +108,8 @@ impl<'tcx> Interner for TyCtxt<'tcx> { type GenericArgsSlice = &'tcx [ty::GenericArg<'tcx>]; type GenericArg = ty::GenericArg<'tcx>; type Term = ty::Term<'tcx>; - type BoundVarKinds = &'tcx List; + type BoundVarKinds = &'tcx List>; - type BoundVarKind = ty::BoundVariableKind; type PredefinedOpaques = solve::PredefinedOpaques<'tcx>; fn mk_predefined_opaques_in_body( @@ -144,10 +143,8 @@ impl<'tcx> Interner for TyCtxt<'tcx> { type FnInputTys = &'tcx [Ty<'tcx>]; type ParamTy = ParamTy; - type BoundTy = ty::BoundTy; type Symbol = Symbol; - type PlaceholderTy = ty::PlaceholderType<'tcx>; type ErrorGuaranteed = ErrorGuaranteed; type BoundExistentialPredicates = &'tcx List>; @@ -157,10 +154,8 @@ impl<'tcx> Interner for TyCtxt<'tcx> { type Safety = hir::Safety; type Abi = ExternAbi; type Const = ty::Const<'tcx>; - type PlaceholderConst = ty::PlaceholderConst<'tcx>; type ParamConst = ty::ParamConst; - type BoundConst = ty::BoundConst; type ValueConst = ty::Value<'tcx>; type ExprConst = ty::Expr<'tcx>; type ValTree = ty::ValTree<'tcx>; @@ -169,8 +164,6 @@ impl<'tcx> Interner for TyCtxt<'tcx> { type Region = Region<'tcx>; type EarlyParamRegion = ty::EarlyParamRegion; type LateParamRegion = ty::LateParamRegion; - type BoundRegion = ty::BoundRegion; - type PlaceholderRegion = ty::PlaceholderRegion<'tcx>; type RegionAssumptions = &'tcx ty::List>; @@ -776,6 +769,13 @@ impl<'tcx> Interner for TyCtxt<'tcx> { ) -> (QueryResult<'tcx>, &'tcx inspect::Probe>) { self.evaluate_root_goal_for_proof_tree_raw(canonical_goal) } + + fn item_name(self, id: DefId) -> Symbol { + let id = id.into_query_param(); + self.opt_item_name(id).unwrap_or_else(|| { + bug!("item_name: no name for {:?}", self.def_path(id)); + }) + } } macro_rules! bidirectional_lang_item_map { @@ -938,7 +938,7 @@ pub struct CtxtInterners<'tcx> { const_: InternedSet<'tcx, WithCachedTypeInfo>>, pat: InternedSet<'tcx, PatternKind<'tcx>>, const_allocation: InternedSet<'tcx, Allocation>, - bound_variable_kinds: InternedSet<'tcx, List>, + bound_variable_kinds: InternedSet<'tcx, List>>, layout: InternedSet<'tcx, LayoutData>, adt_def: InternedSet<'tcx, AdtDefData>, external_constraints: InternedSet<'tcx, ExternalConstraintsData>>, @@ -2530,7 +2530,7 @@ nop_list_lift! { type_lists; Ty<'a> => Ty<'tcx> } nop_list_lift! { poly_existential_predicates; PolyExistentialPredicate<'a> => PolyExistentialPredicate<'tcx> } -nop_list_lift! { bound_variable_kinds; ty::BoundVariableKind => ty::BoundVariableKind } +nop_list_lift! { bound_variable_kinds; ty::BoundVariableKind<'a> => ty::BoundVariableKind<'tcx> } // This is the impl for `&'a GenericArgs<'a>`. nop_list_lift! { args; GenericArg<'a> => GenericArg<'tcx> } @@ -2817,7 +2817,7 @@ slice_interners!( poly_existential_predicates: intern_poly_existential_predicates(PolyExistentialPredicate<'tcx>), projs: pub mk_projs(ProjectionKind), place_elems: pub mk_place_elems(PlaceElem<'tcx>), - bound_variable_kinds: pub mk_bound_variable_kinds(ty::BoundVariableKind), + bound_variable_kinds: pub mk_bound_variable_kinds(ty::BoundVariableKind<'tcx>), fields: pub mk_fields(FieldIdx), local_def_ids: intern_local_def_ids(LocalDefId), captures: intern_captures(&'tcx ty::CapturedPlace<'tcx>), @@ -3242,7 +3242,7 @@ impl<'tcx> TyCtxt<'tcx> { pub fn mk_bound_variable_kinds_from_iter(self, iter: I) -> T::Output where I: Iterator, - T: CollectAndApply>, + T: CollectAndApply, &'tcx List>>, { T::collect_and_apply(iter, |xs| self.mk_bound_variable_kinds(xs)) } @@ -3362,7 +3362,7 @@ impl<'tcx> TyCtxt<'tcx> { self.is_late_bound_map(id.owner).is_some_and(|set| set.contains(&id.local_id)) } - pub fn late_bound_vars(self, id: HirId) -> &'tcx List { + pub fn late_bound_vars(self, id: HirId) -> &'tcx List> { self.mk_bound_variable_kinds( &self .late_bound_vars_map(id.owner) diff --git a/compiler/rustc_middle/src/ty/fold.rs b/compiler/rustc_middle/src/ty/fold.rs index ee29afcff638..3d9148d6ed7b 100644 --- a/compiler/rustc_middle/src/ty/fold.rs +++ b/compiler/rustc_middle/src/ty/fold.rs @@ -3,7 +3,7 @@ use rustc_hir::def_id::DefId; use rustc_type_ir::data_structures::DelayedMap; use crate::ty::{ - self, Binder, BoundConst, BoundTy, Ty, TyCtxt, TypeFoldable, TypeFolder, TypeSuperFoldable, + self, Binder, BoundTy, Ty, TyCtxt, TypeFoldable, TypeFolder, TypeSuperFoldable, TypeVisitableExt, }; @@ -58,28 +58,28 @@ where /// gets mapped to the same result. `BoundVarReplacer` caches by using /// a `DelayedMap` which does not cache the first few types it encounters. pub trait BoundVarReplacerDelegate<'tcx> { - fn replace_region(&mut self, br: ty::BoundRegion) -> ty::Region<'tcx>; - fn replace_ty(&mut self, bt: ty::BoundTy) -> Ty<'tcx>; - fn replace_const(&mut self, bc: ty::BoundConst) -> ty::Const<'tcx>; + fn replace_region(&mut self, br: ty::BoundRegion<'tcx>) -> ty::Region<'tcx>; + fn replace_ty(&mut self, bt: ty::BoundTy<'tcx>) -> Ty<'tcx>; + fn replace_const(&mut self, bc: ty::BoundConst<'tcx>) -> ty::Const<'tcx>; } /// A simple delegate taking 3 mutable functions. The used functions must /// always return the same result for each bound variable, no matter how /// frequently they are called. pub struct FnMutDelegate<'a, 'tcx> { - pub regions: &'a mut (dyn FnMut(ty::BoundRegion) -> ty::Region<'tcx> + 'a), - pub types: &'a mut (dyn FnMut(ty::BoundTy) -> Ty<'tcx> + 'a), - pub consts: &'a mut (dyn FnMut(ty::BoundConst) -> ty::Const<'tcx> + 'a), + pub regions: &'a mut (dyn FnMut(ty::BoundRegion<'tcx>) -> ty::Region<'tcx> + 'a), + pub types: &'a mut (dyn FnMut(ty::BoundTy<'tcx>) -> Ty<'tcx> + 'a), + pub consts: &'a mut (dyn FnMut(ty::BoundConst<'tcx>) -> ty::Const<'tcx> + 'a), } impl<'a, 'tcx> BoundVarReplacerDelegate<'tcx> for FnMutDelegate<'a, 'tcx> { - fn replace_region(&mut self, br: ty::BoundRegion) -> ty::Region<'tcx> { + fn replace_region(&mut self, br: ty::BoundRegion<'tcx>) -> ty::Region<'tcx> { (self.regions)(br) } - fn replace_ty(&mut self, bt: ty::BoundTy) -> Ty<'tcx> { + fn replace_ty(&mut self, bt: ty::BoundTy<'tcx>) -> Ty<'tcx> { (self.types)(bt) } - fn replace_const(&mut self, bc: ty::BoundConst) -> ty::Const<'tcx> { + fn replace_const(&mut self, bc: ty::BoundConst<'tcx>) -> ty::Const<'tcx> { (self.consts)(bc) } } @@ -207,13 +207,14 @@ impl<'tcx> TyCtxt<'tcx> { self, value: Binder<'tcx, T>, mut fld_r: F, - ) -> (T, FxIndexMap>) + ) -> (T, FxIndexMap, ty::Region<'tcx>>) where - F: FnMut(ty::BoundRegion) -> ty::Region<'tcx>, + F: FnMut(ty::BoundRegion<'tcx>) -> ty::Region<'tcx>, T: TypeFoldable>, { let mut region_map = FxIndexMap::default(); - let real_fld_r = |br: ty::BoundRegion| *region_map.entry(br).or_insert_with(|| fld_r(br)); + let real_fld_r = + |br: ty::BoundRegion<'tcx>| *region_map.entry(br).or_insert_with(|| fld_r(br)); let value = self.instantiate_bound_regions_uncached(value, real_fld_r); (value, region_map) } @@ -224,7 +225,7 @@ impl<'tcx> TyCtxt<'tcx> { mut replace_regions: F, ) -> T where - F: FnMut(ty::BoundRegion) -> ty::Region<'tcx>, + F: FnMut(ty::BoundRegion<'tcx>) -> ty::Region<'tcx>, T: TypeFoldable>, { let value = value.skip_binder(); @@ -292,14 +293,14 @@ impl<'tcx> TyCtxt<'tcx> { self.replace_escaping_bound_vars_uncached( value, FnMutDelegate { - regions: &mut |r: ty::BoundRegion| { + regions: &mut |r: ty::BoundRegion<'tcx>| { ty::Region::new_bound( self, ty::INNERMOST, ty::BoundRegion { var: shift_bv(r.var), kind: r.kind }, ) }, - types: &mut |t: ty::BoundTy| { + types: &mut |t: ty::BoundTy<'tcx>| { Ty::new_bound( self, ty::INNERMOST, @@ -307,11 +308,7 @@ impl<'tcx> TyCtxt<'tcx> { ) }, consts: &mut |c| { - ty::Const::new_bound( - self, - ty::INNERMOST, - ty::BoundConst { var: shift_bv(c.var) }, - ) + ty::Const::new_bound(self, ty::INNERMOST, ty::BoundConst::new(shift_bv(c.var))) }, }, ) @@ -333,10 +330,10 @@ impl<'tcx> TyCtxt<'tcx> { { struct Anonymize<'a, 'tcx> { tcx: TyCtxt<'tcx>, - map: &'a mut FxIndexMap, + map: &'a mut FxIndexMap>, } impl<'tcx> BoundVarReplacerDelegate<'tcx> for Anonymize<'_, 'tcx> { - fn replace_region(&mut self, br: ty::BoundRegion) -> ty::Region<'tcx> { + fn replace_region(&mut self, br: ty::BoundRegion<'tcx>) -> ty::Region<'tcx> { let entry = self.map.entry(br.var); let index = entry.index(); let var = ty::BoundVar::from_usize(index); @@ -346,7 +343,7 @@ impl<'tcx> TyCtxt<'tcx> { let br = ty::BoundRegion { var, kind }; ty::Region::new_bound(self.tcx, ty::INNERMOST, br) } - fn replace_ty(&mut self, bt: ty::BoundTy) -> Ty<'tcx> { + fn replace_ty(&mut self, bt: ty::BoundTy<'tcx>) -> Ty<'tcx> { let entry = self.map.entry(bt.var); let index = entry.index(); let var = ty::BoundVar::from_usize(index); @@ -355,12 +352,12 @@ impl<'tcx> TyCtxt<'tcx> { .expect_ty(); Ty::new_bound(self.tcx, ty::INNERMOST, BoundTy { var, kind }) } - fn replace_const(&mut self, bc: ty::BoundConst) -> ty::Const<'tcx> { + fn replace_const(&mut self, bc: ty::BoundConst<'tcx>) -> ty::Const<'tcx> { let entry = self.map.entry(bc.var); let index = entry.index(); let var = ty::BoundVar::from_usize(index); let () = entry.or_insert_with(|| ty::BoundVariableKind::Const).expect_const(); - ty::Const::new_bound(self.tcx, ty::INNERMOST, BoundConst { var }) + ty::Const::new_bound(self.tcx, ty::INNERMOST, ty::BoundConst::new(var)) } } diff --git a/compiler/rustc_middle/src/ty/mod.rs b/compiler/rustc_middle/src/ty/mod.rs index ce713dcf42f5..3e3c9e27186a 100644 --- a/compiler/rustc_middle/src/ty/mod.rs +++ b/compiler/rustc_middle/src/ty/mod.rs @@ -97,13 +97,13 @@ pub use self::predicate::{ RegionOutlivesPredicate, SubtypePredicate, TraitPredicate, TraitRef, TypeOutlivesPredicate, }; pub use self::region::{ - BoundRegion, BoundRegionKind, EarlyParamRegion, LateParamRegion, LateParamRegionKind, Region, - RegionKind, RegionVid, + EarlyParamRegion, LateParamRegion, LateParamRegionKind, Region, RegionKind, RegionVid, }; pub use self::sty::{ - AliasTy, Article, Binder, BoundTy, BoundTyKind, BoundVariableKind, CanonicalPolyFnSig, - CoroutineArgsExt, EarlyBinder, FnSig, InlineConstArgs, InlineConstArgsParts, ParamConst, - ParamTy, PolyFnSig, TyKind, TypeAndMut, TypingMode, UpvarArgs, + AliasTy, Article, Binder, BoundConst, BoundRegion, BoundRegionKind, BoundTy, BoundTyKind, + BoundVariableKind, CanonicalPolyFnSig, CoroutineArgsExt, EarlyBinder, FnSig, InlineConstArgs, + InlineConstArgsParts, ParamConst, ParamTy, PlaceholderConst, PlaceholderRegion, + PlaceholderType, PolyFnSig, TyKind, TypeAndMut, TypingMode, UpvarArgs, }; pub use self::trait_def::TraitDef; pub use self::typeck_results::{ @@ -914,100 +914,6 @@ impl<'tcx> DefinitionSiteHiddenType<'tcx> { } } -pub type PlaceholderRegion<'tcx> = ty::Placeholder, BoundRegion>; - -impl<'tcx> rustc_type_ir::inherent::PlaceholderLike> for PlaceholderRegion<'tcx> { - type Bound = BoundRegion; - - fn universe(self) -> UniverseIndex { - self.universe - } - - fn var(self) -> BoundVar { - self.bound.var - } - - fn with_updated_universe(self, ui: UniverseIndex) -> Self { - ty::Placeholder::new(ui, self.bound) - } - - fn new(ui: UniverseIndex, bound: BoundRegion) -> Self { - ty::Placeholder::new(ui, bound) - } - - fn new_anon(ui: UniverseIndex, var: BoundVar) -> Self { - ty::Placeholder::new(ui, BoundRegion { var, kind: BoundRegionKind::Anon }) - } -} - -pub type PlaceholderType<'tcx> = ty::Placeholder, BoundTy>; - -impl<'tcx> rustc_type_ir::inherent::PlaceholderLike> for PlaceholderType<'tcx> { - type Bound = BoundTy; - - fn universe(self) -> UniverseIndex { - self.universe - } - - fn var(self) -> BoundVar { - self.bound.var - } - - fn with_updated_universe(self, ui: UniverseIndex) -> Self { - ty::Placeholder::new(ui, self.bound) - } - - fn new(ui: UniverseIndex, bound: BoundTy) -> Self { - ty::Placeholder::new(ui, bound) - } - - fn new_anon(ui: UniverseIndex, var: BoundVar) -> Self { - ty::Placeholder::new(ui, BoundTy { var, kind: BoundTyKind::Anon }) - } -} - -#[derive(Copy, Clone, Debug, PartialEq, Eq, Hash, HashStable)] -#[derive(TyEncodable, TyDecodable)] -pub struct BoundConst { - pub var: BoundVar, -} - -impl<'tcx> rustc_type_ir::inherent::BoundVarLike> for BoundConst { - fn var(self) -> BoundVar { - self.var - } - - fn assert_eq(self, var: ty::BoundVariableKind) { - var.expect_const() - } -} - -pub type PlaceholderConst<'tcx> = ty::Placeholder, BoundConst>; - -impl<'tcx> rustc_type_ir::inherent::PlaceholderLike> for PlaceholderConst<'tcx> { - type Bound = BoundConst; - - fn universe(self) -> UniverseIndex { - self.universe - } - - fn var(self) -> BoundVar { - self.bound.var - } - - fn with_updated_universe(self, ui: UniverseIndex) -> Self { - ty::Placeholder::new(ui, self.bound) - } - - fn new(ui: UniverseIndex, bound: BoundConst) -> Self { - ty::Placeholder::new(ui, bound) - } - - fn new_anon(ui: UniverseIndex, var: BoundVar) -> Self { - ty::Placeholder::new(ui, BoundConst { var }) - } -} - pub type Clauses<'tcx> = &'tcx ListWithCachedTypeInfo>; impl<'tcx> rustc_type_ir::Flags for Clauses<'tcx> { diff --git a/compiler/rustc_middle/src/ty/print/pretty.rs b/compiler/rustc_middle/src/ty/print/pretty.rs index 76a4f61e6714..02b804c1ab29 100644 --- a/compiler/rustc_middle/src/ty/print/pretty.rs +++ b/compiler/rustc_middle/src/ty/print/pretty.rs @@ -197,7 +197,7 @@ pub struct RegionHighlightMode<'tcx> { /// This is used when you have a signature like `fn foo(x: &u32, /// y: &'a u32)` and we want to give a name to the region of the /// reference `x`. - highlight_bound_region: Option<(ty::BoundRegionKind, usize)>, + highlight_bound_region: Option<(ty::BoundRegionKind<'tcx>, usize)>, } impl<'tcx> RegionHighlightMode<'tcx> { @@ -246,7 +246,7 @@ impl<'tcx> RegionHighlightMode<'tcx> { /// Highlight the given bound region. /// We can only highlight one bound region at a time. See /// the field `highlight_bound_region` for more detailed notes. - pub fn highlighting_bound_region(&mut self, br: ty::BoundRegionKind, number: usize) { + pub fn highlighting_bound_region(&mut self, br: ty::BoundRegionKind<'tcx>, number: usize) { assert!(self.highlight_bound_region.is_none()); self.highlight_bound_region = Some((br, number)); } @@ -2639,12 +2639,12 @@ impl<'tcx> FmtPrinter<'_, 'tcx> { struct RegionFolder<'a, 'tcx> { tcx: TyCtxt<'tcx>, current_index: ty::DebruijnIndex, - region_map: UnordMap>, + region_map: UnordMap, ty::Region<'tcx>>, name: &'a mut ( dyn FnMut( Option, // Debruijn index of the folded late-bound region ty::DebruijnIndex, // Index corresponding to binder level - ty::BoundRegion, + ty::BoundRegion<'tcx>, ) -> ty::Region<'tcx> + 'a ), @@ -2717,7 +2717,7 @@ impl<'tcx> FmtPrinter<'_, 'tcx> { &mut self, value: &ty::Binder<'tcx, T>, mode: WrapBinderMode, - ) -> Result<(T, UnordMap>), fmt::Error> + ) -> Result<(T, UnordMap, ty::Region<'tcx>>), fmt::Error> where T: TypeFoldable>, { @@ -2810,12 +2810,12 @@ impl<'tcx> FmtPrinter<'_, 'tcx> { // see issue #102392. let mut name = |lifetime_idx: Option, binder_level_idx: ty::DebruijnIndex, - br: ty::BoundRegion| { + br: ty::BoundRegion<'tcx>| { let (name, kind) = if let Some(name) = br.kind.get_name(tcx) { (name, br.kind) } else { let name = next_name(self); - (name, ty::BoundRegionKind::NamedAnon(name)) + (name, ty::BoundRegionKind::NamedForPrinting(name)) }; if let Some(lt_idx) = lifetime_idx { diff --git a/compiler/rustc_middle/src/ty/region.rs b/compiler/rustc_middle/src/ty/region.rs index 61994d928dec..a497501ef19d 100644 --- a/compiler/rustc_middle/src/ty/region.rs +++ b/compiler/rustc_middle/src/ty/region.rs @@ -50,7 +50,7 @@ impl<'tcx> Region<'tcx> { pub fn new_bound( tcx: TyCtxt<'tcx>, debruijn: ty::DebruijnIndex, - bound_region: ty::BoundRegion, + bound_region: ty::BoundRegion<'tcx>, ) -> Region<'tcx> { // Use a pre-interned one when possible. if let ty::BoundRegion { var, kind: ty::BoundRegionKind::Anon } = bound_region @@ -160,7 +160,7 @@ impl<'tcx> rustc_type_ir::inherent::Region> for Region<'tcx> { fn new_bound( interner: TyCtxt<'tcx>, debruijn: ty::DebruijnIndex, - var: ty::BoundRegion, + var: ty::BoundRegion<'tcx>, ) -> Self { Region::new_bound(interner, debruijn, var) } @@ -388,7 +388,7 @@ pub struct LateParamRegion { pub kind: LateParamRegionKind, } -/// When liberating bound regions, we map their [`BoundRegionKind`] +/// When liberating bound regions, we map their [`ty::BoundRegionKind`] /// to this as we need to track the index of anonymous regions. We /// otherwise end up liberating multiple bound regions to the same /// late-bound region. @@ -397,7 +397,7 @@ pub struct LateParamRegion { pub enum LateParamRegionKind { /// An anonymous region parameter for a given fn (&T) /// - /// Unlike [`BoundRegionKind::Anon`], this tracks the index of the + /// Unlike [`ty::BoundRegionKind::Anon`], this tracks the index of the /// liberated bound region. /// /// We should ideally never liberate anonymous regions, but do so for the @@ -418,12 +418,14 @@ pub enum LateParamRegionKind { } impl LateParamRegionKind { - pub fn from_bound(var: BoundVar, br: BoundRegionKind) -> LateParamRegionKind { + pub fn from_bound(var: BoundVar, br: ty::BoundRegionKind<'_>) -> LateParamRegionKind { match br { - BoundRegionKind::Anon => LateParamRegionKind::Anon(var.as_u32()), - BoundRegionKind::Named(def_id) => LateParamRegionKind::Named(def_id), - BoundRegionKind::ClosureEnv => LateParamRegionKind::ClosureEnv, - BoundRegionKind::NamedAnon(name) => LateParamRegionKind::NamedAnon(var.as_u32(), name), + ty::BoundRegionKind::Anon => LateParamRegionKind::Anon(var.as_u32()), + ty::BoundRegionKind::Named(def_id) => LateParamRegionKind::Named(def_id), + ty::BoundRegionKind::ClosureEnv => LateParamRegionKind::ClosureEnv, + ty::BoundRegionKind::NamedForPrinting(name) => { + LateParamRegionKind::NamedAnon(var.as_u32(), name) + } } } @@ -450,81 +452,6 @@ impl LateParamRegionKind { } } -#[derive(Clone, PartialEq, Eq, Hash, TyEncodable, TyDecodable, Copy)] -#[derive(HashStable)] -pub enum BoundRegionKind { - /// An anonymous region parameter for a given fn (&T) - Anon, - - /// An anonymous region parameter with a `Symbol` name. - /// - /// Used to give late-bound regions names for things like pretty printing. - NamedAnon(Symbol), - - /// Late-bound regions that appear in the AST. - Named(DefId), - - /// Anonymous region for the implicit env pointer parameter - /// to a closure - ClosureEnv, -} - -#[derive(Copy, Clone, PartialEq, Eq, Hash, TyEncodable, TyDecodable)] -#[derive(HashStable)] -pub struct BoundRegion { - pub var: BoundVar, - pub kind: BoundRegionKind, -} - -impl<'tcx> rustc_type_ir::inherent::BoundVarLike> for BoundRegion { - fn var(self) -> BoundVar { - self.var - } - - fn assert_eq(self, var: ty::BoundVariableKind) { - assert_eq!(self.kind, var.expect_region()) - } -} - -impl core::fmt::Debug for BoundRegion { - fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { - match self.kind { - BoundRegionKind::Anon => write!(f, "{:?}", self.var), - BoundRegionKind::ClosureEnv => write!(f, "{:?}.Env", self.var), - BoundRegionKind::Named(def) => { - write!(f, "{:?}.Named({:?})", self.var, def) - } - BoundRegionKind::NamedAnon(symbol) => { - write!(f, "{:?}.NamedAnon({:?})", self.var, symbol) - } - } - } -} - -impl BoundRegionKind { - pub fn is_named(&self, tcx: TyCtxt<'_>) -> bool { - self.get_name(tcx).is_some() - } - - pub fn get_name(&self, tcx: TyCtxt<'_>) -> Option { - match *self { - BoundRegionKind::Named(def_id) => { - let name = tcx.item_name(def_id); - if name != kw::UnderscoreLifetime { Some(name) } else { None } - } - BoundRegionKind::NamedAnon(name) => Some(name), - _ => None, - } - } - - pub fn get_id(&self) -> Option { - match *self { - BoundRegionKind::Named(id) => Some(id), - _ => None, - } - } -} - // Some types are used a lot. Make sure they don't unintentionally get bigger. #[cfg(target_pointer_width = "64")] mod size_asserts { diff --git a/compiler/rustc_middle/src/ty/structural_impls.rs b/compiler/rustc_middle/src/ty/structural_impls.rs index 314d2ba39632..8707b03e4b8f 100644 --- a/compiler/rustc_middle/src/ty/structural_impls.rs +++ b/compiler/rustc_middle/src/ty/structural_impls.rs @@ -65,21 +65,6 @@ impl<'tcx> fmt::Debug for ty::adjustment::PatAdjustment<'tcx> { } } -impl fmt::Debug for ty::BoundRegionKind { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - match *self { - ty::BoundRegionKind::Anon => write!(f, "BrAnon"), - ty::BoundRegionKind::NamedAnon(name) => { - write!(f, "BrNamedAnon({name})") - } - ty::BoundRegionKind::Named(did) => { - write!(f, "BrNamed({did:?})") - } - ty::BoundRegionKind::ClosureEnv => write!(f, "BrEnv"), - } - } -} - impl fmt::Debug for ty::LateParamRegion { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { write!(f, "ReLateParam({:?}, {:?})", self.scope, self.kind) @@ -175,15 +160,6 @@ impl<'tcx> fmt::Debug for ty::Const<'tcx> { } } -impl fmt::Debug for ty::BoundTy { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - match self.kind { - ty::BoundTyKind::Anon => write!(f, "{:?}", self.var), - ty::BoundTyKind::Param(def_id) => write!(f, "{def_id:?}"), - } - } -} - impl<'tcx> fmt::Debug for GenericArg<'tcx> { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { match self.kind() { @@ -255,7 +231,8 @@ TrivialTypeTraversalImpls! { crate::ty::AdtKind, crate::ty::AssocItem, crate::ty::AssocKind, - crate::ty::BoundRegion, + crate::ty::BoundRegion<'tcx>, + crate::ty::BoundTy<'tcx>, crate::ty::ScalarInt, crate::ty::UserTypeAnnotationIndex, crate::ty::abstract_const::NotConstEvaluatable, @@ -284,7 +261,6 @@ TrivialTypeTraversalImpls! { TrivialTypeTraversalAndLiftImpls! { // tidy-alphabetical-start crate::mir::RuntimeChecks, - crate::ty::BoundTy, crate::ty::ParamTy, crate::ty::instance::ReifyReason, rustc_hir::def_id::DefId, diff --git a/compiler/rustc_middle/src/ty/sty.rs b/compiler/rustc_middle/src/ty/sty.rs index b0b5a783b00e..4c5bd85e6b72 100644 --- a/compiler/rustc_middle/src/ty/sty.rs +++ b/compiler/rustc_middle/src/ty/sty.rs @@ -13,7 +13,7 @@ use rustc_hir as hir; use rustc_hir::LangItem; use rustc_hir::def_id::DefId; use rustc_macros::{HashStable, TyDecodable, TyEncodable, TypeFoldable, extension}; -use rustc_span::{DUMMY_SP, Span, Symbol, sym}; +use rustc_span::{DUMMY_SP, Span, Symbol, kw, sym}; use rustc_type_ir::TyKind::*; use rustc_type_ir::solve::SizedTraitKind; use rustc_type_ir::walk::TypeWalker; @@ -26,8 +26,8 @@ use crate::infer::canonical::Canonical; use crate::traits::ObligationCause; use crate::ty::InferTy::*; use crate::ty::{ - self, AdtDef, BoundRegionKind, Discr, GenericArg, GenericArgs, GenericArgsRef, List, ParamEnv, - Region, Ty, TyCtxt, TypeFlags, TypeSuperVisitable, TypeVisitable, TypeVisitor, UintTy, + self, AdtDef, Discr, GenericArg, GenericArgs, GenericArgsRef, List, ParamEnv, Region, Ty, + TyCtxt, TypeFlags, TypeSuperVisitable, TypeVisitable, TypeVisitor, UintTy, }; // Re-export and re-parameterize some `I = TyCtxt<'tcx>` types here @@ -40,6 +40,15 @@ pub type Binder<'tcx, T> = ir::Binder, T>; pub type EarlyBinder<'tcx, T> = ir::EarlyBinder, T>; pub type TypingMode<'tcx> = ir::TypingMode>; pub type Placeholder<'tcx, T> = ir::Placeholder, T>; +pub type PlaceholderRegion<'tcx> = ir::PlaceholderRegion>; +pub type PlaceholderType<'tcx> = ir::PlaceholderType>; +pub type PlaceholderConst<'tcx> = ir::PlaceholderConst>; +pub type BoundTy<'tcx> = ir::BoundTy>; +pub type BoundConst<'tcx> = ir::BoundConst>; +pub type BoundRegion<'tcx> = ir::BoundRegion>; +pub type BoundVariableKind<'tcx> = ir::BoundVariableKind>; +pub type BoundRegionKind<'tcx> = ir::BoundRegionKind>; +pub type BoundTyKind<'tcx> = ir::BoundTyKind>; pub trait Article { fn article(&self) -> &'static str; @@ -257,37 +266,6 @@ impl<'tcx> InlineConstArgs<'tcx> { } } -#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, TyEncodable, TyDecodable)] -#[derive(HashStable)] -pub enum BoundVariableKind { - Ty(BoundTyKind), - Region(BoundRegionKind), - Const, -} - -impl BoundVariableKind { - pub fn expect_region(self) -> BoundRegionKind { - match self { - BoundVariableKind::Region(lt) => lt, - _ => bug!("expected a region, but found another kind"), - } - } - - pub fn expect_ty(self) -> BoundTyKind { - match self { - BoundVariableKind::Ty(ty) => ty, - _ => bug!("expected a type, but found another kind"), - } - } - - pub fn expect_const(self) { - match self { - BoundVariableKind::Const => (), - _ => bug!("expected a const, but found another kind"), - } - } -} - pub type PolyFnSig<'tcx> = Binder<'tcx, FnSig<'tcx>>; pub type CanonicalPolyFnSig<'tcx> = Canonical<'tcx, Binder<'tcx, FnSig<'tcx>>>; @@ -381,30 +359,6 @@ impl ParamConst { } } -#[derive(Clone, Copy, PartialEq, Eq, Hash, TyEncodable, TyDecodable)] -#[derive(HashStable)] -pub struct BoundTy { - pub var: BoundVar, - pub kind: BoundTyKind, -} - -impl<'tcx> rustc_type_ir::inherent::BoundVarLike> for BoundTy { - fn var(self) -> BoundVar { - self.var - } - - fn assert_eq(self, var: ty::BoundVariableKind) { - assert_eq!(self.kind, var.expect_ty()) - } -} - -#[derive(Clone, Copy, PartialEq, Eq, Hash, Debug, TyEncodable, TyDecodable)] -#[derive(HashStable)] -pub enum BoundTyKind { - Anon, - Param(DefId), -} - /// Constructors for `Ty` impl<'tcx> Ty<'tcx> { /// Avoid using this in favour of more specific `new_*` methods, where possible. @@ -479,7 +433,7 @@ impl<'tcx> Ty<'tcx> { pub fn new_bound( tcx: TyCtxt<'tcx>, index: ty::DebruijnIndex, - bound_ty: ty::BoundTy, + bound_ty: ty::BoundTy<'tcx>, ) -> Ty<'tcx> { // Use a pre-interned one when possible. if let ty::BoundTy { var, kind: ty::BoundTyKind::Anon } = bound_ty @@ -961,7 +915,11 @@ impl<'tcx> rustc_type_ir::inherent::Ty> for Ty<'tcx> { Ty::new_placeholder(tcx, placeholder) } - fn new_bound(interner: TyCtxt<'tcx>, debruijn: ty::DebruijnIndex, var: ty::BoundTy) -> Self { + fn new_bound( + interner: TyCtxt<'tcx>, + debruijn: ty::DebruijnIndex, + var: ty::BoundTy<'tcx>, + ) -> Self { Ty::new_bound(interner, debruijn, var) } @@ -2135,6 +2093,12 @@ impl<'tcx> rustc_type_ir::inherent::Tys> for &'tcx ty::List rustc_type_ir::inherent::Symbol> for Symbol { + fn is_kw_underscore_lifetime(self) -> bool { + self == kw::UnderscoreLifetime + } +} + // Some types are used a lot. Make sure they don't unintentionally get bigger. #[cfg(target_pointer_width = "64")] mod size_asserts { diff --git a/compiler/rustc_middle/src/ty/visit.rs b/compiler/rustc_middle/src/ty/visit.rs index e84ac56b31df..8f79f8e3564e 100644 --- a/compiler/rustc_middle/src/ty/visit.rs +++ b/compiler/rustc_middle/src/ty/visit.rs @@ -113,7 +113,7 @@ impl<'tcx> TyCtxt<'tcx> { pub fn collect_constrained_late_bound_regions( self, value: Binder<'tcx, T>, - ) -> FxIndexSet + ) -> FxIndexSet> where T: TypeFoldable>, { @@ -124,7 +124,7 @@ impl<'tcx> TyCtxt<'tcx> { pub fn collect_referenced_late_bound_regions( self, value: Binder<'tcx, T>, - ) -> FxIndexSet + ) -> FxIndexSet> where T: TypeFoldable>, { @@ -135,7 +135,7 @@ impl<'tcx> TyCtxt<'tcx> { self, value: Binder<'tcx, T>, just_constrained: bool, - ) -> FxIndexSet + ) -> FxIndexSet> where T: TypeFoldable>, { @@ -149,9 +149,9 @@ impl<'tcx> TyCtxt<'tcx> { /// Collects all the late-bound regions at the innermost binding level /// into a hash set. -struct LateBoundRegionsCollector { +struct LateBoundRegionsCollector<'tcx> { current_index: ty::DebruijnIndex, - regions: FxIndexSet, + regions: FxIndexSet>, /// `true` if we only want regions that are known to be /// "constrained" when you equate this type with another type. In @@ -163,13 +163,13 @@ struct LateBoundRegionsCollector { just_constrained: bool, } -impl LateBoundRegionsCollector { +impl LateBoundRegionsCollector<'_> { fn new(just_constrained: bool) -> Self { Self { current_index: ty::INNERMOST, regions: Default::default(), just_constrained } } } -impl<'tcx> TypeVisitor> for LateBoundRegionsCollector { +impl<'tcx> TypeVisitor> for LateBoundRegionsCollector<'tcx> { fn visit_binder>>(&mut self, t: &Binder<'tcx, T>) { self.current_index.shift_in(1); t.super_visit_with(self); diff --git a/compiler/rustc_mir_transform/src/lib.rs b/compiler/rustc_mir_transform/src/lib.rs index 2f8c6b876398..0e6a1a414e45 100644 --- a/compiler/rustc_mir_transform/src/lib.rs +++ b/compiler/rustc_mir_transform/src/lib.rs @@ -91,20 +91,32 @@ macro_rules! declare_passes { )+ )* - static PASS_NAMES: LazyLock> = LazyLock::new(|| [ + static PASS_NAMES: LazyLock> = LazyLock::new(|| { + let mut set = FxIndexSet::default(); // Fake marker pass - "PreCodegen", + set.insert("PreCodegen"); $( $( - stringify!($pass_name), - $( - $( - $mod_name::$pass_name::$ident.name(), - )* - )? + set.extend(pass_names!($mod_name : $pass_name $( { $($ident),* } )? )); )+ )* - ].into_iter().collect()); + set + }); + }; +} + +macro_rules! pass_names { + // pass groups: only pass names inside are considered pass_names + ($mod_name:ident : $pass_group:ident { $($pass_name:ident),* $(,)? }) => { + [ + $( + $mod_name::$pass_group::$pass_name.name(), + )* + ] + }; + // lone pass names: stringify the struct or enum name + ($mod_name:ident : $pass_name:ident) => { + [stringify!($pass_name)] }; } diff --git a/compiler/rustc_mir_transform/src/promote_consts.rs b/compiler/rustc_mir_transform/src/promote_consts.rs index 6e7b93a5e719..3d1537b95efa 100644 --- a/compiler/rustc_mir_transform/src/promote_consts.rs +++ b/compiler/rustc_mir_transform/src/promote_consts.rs @@ -485,47 +485,33 @@ impl<'tcx> Validator<'_, 'tcx> { if lhs_ty.is_integral() { let sz = lhs_ty.primitive_size(self.tcx); // Integer division: the RHS must be a non-zero const. - let rhs_val = match rhs { - Operand::Constant(c) - if self.should_evaluate_for_promotion_checks(c.const_) => - { - c.const_.try_eval_scalar_int(self.tcx, self.typing_env) - } - _ => None, - }; - match rhs_val.map(|x| x.to_uint(sz)) { + let rhs_val = if let Operand::Constant(rhs_c) = rhs + && self.should_evaluate_for_promotion_checks(rhs_c.const_) + && let Some(rhs_val) = + rhs_c.const_.try_eval_scalar_int(self.tcx, self.typing_env) // for the zero test, int vs uint does not matter - Some(x) if x != 0 => {} // okay - _ => return Err(Unpromotable), // value not known or 0 -- not okay - } + && rhs_val.to_uint(sz) != 0 + { + rhs_val + } else { + // value not known or 0 -- not okay + return Err(Unpromotable); + }; // Furthermore, for signed division, we also have to exclude `int::MIN / // -1`. - if lhs_ty.is_signed() { - match rhs_val.map(|x| x.to_int(sz)) { - Some(-1) | None => { - // The RHS is -1 or unknown, so we have to be careful. - // But is the LHS int::MIN? - let lhs_val = match lhs { - Operand::Constant(c) - if self.should_evaluate_for_promotion_checks( - c.const_, - ) => - { - c.const_ - .try_eval_scalar_int(self.tcx, self.typing_env) - } - _ => None, - }; - let lhs_min = sz.signed_int_min(); - match lhs_val.map(|x| x.to_int(sz)) { - // okay - Some(x) if x != lhs_min => {} - - // value not known or int::MIN -- not okay - _ => return Err(Unpromotable), - } - } - _ => {} + if lhs_ty.is_signed() && rhs_val.to_int(sz) == -1 { + // The RHS is -1, so we have to be careful. But is the LHS int::MIN? + if let Operand::Constant(lhs_c) = lhs + && self.should_evaluate_for_promotion_checks(lhs_c.const_) + && let Some(lhs_val) = + lhs_c.const_.try_eval_scalar_int(self.tcx, self.typing_env) + && let lhs_min = sz.signed_int_min() + && lhs_val.to_int(sz) != lhs_min + { + // okay + } else { + // value not known or int::MIN -- not okay + return Err(Unpromotable); } } } diff --git a/compiler/rustc_next_trait_solver/src/canonical/canonicalizer.rs b/compiler/rustc_next_trait_solver/src/canonical/canonicalizer.rs index 61a2dcd226b7..ce2be24adc58 100644 --- a/compiler/rustc_next_trait_solver/src/canonical/canonicalizer.rs +++ b/compiler/rustc_next_trait_solver/src/canonical/canonicalizer.rs @@ -3,7 +3,8 @@ use rustc_type_ir::inherent::*; use rustc_type_ir::solve::{Goal, QueryInput}; use rustc_type_ir::{ self as ty, Canonical, CanonicalParamEnvCacheEntry, CanonicalVarKind, Flags, InferCtxtLike, - Interner, TypeFlags, TypeFoldable, TypeFolder, TypeSuperFoldable, TypeVisitableExt, + Interner, PlaceholderConst, PlaceholderType, TypeFlags, TypeFoldable, TypeFolder, + TypeSuperFoldable, TypeVisitableExt, }; use crate::delegate::SolverDelegate; @@ -357,13 +358,13 @@ impl<'a, D: SolverDelegate, I: Interner> Canonicalizer<'a, D, I> { }, ty::Placeholder(placeholder) => match self.canonicalize_mode { CanonicalizeMode::Input { .. } => CanonicalVarKind::PlaceholderTy( - PlaceholderLike::new_anon(ty::UniverseIndex::ROOT, self.variables.len().into()), + PlaceholderType::new_anon(ty::UniverseIndex::ROOT, self.variables.len().into()), ), CanonicalizeMode::Response { .. } => CanonicalVarKind::PlaceholderTy(placeholder), }, ty::Param(_) => match self.canonicalize_mode { CanonicalizeMode::Input { .. } => CanonicalVarKind::PlaceholderTy( - PlaceholderLike::new_anon(ty::UniverseIndex::ROOT, self.variables.len().into()), + PlaceholderType::new_anon(ty::UniverseIndex::ROOT, self.variables.len().into()), ), CanonicalizeMode::Response { .. } => panic!("param ty in response: {t:?}"), }, @@ -513,17 +514,23 @@ impl, I: Interner> TypeFolder for Canonicaliz ty::InferConst::Fresh(_) => todo!(), }, ty::ConstKind::Placeholder(placeholder) => match self.canonicalize_mode { - CanonicalizeMode::Input { .. } => CanonicalVarKind::PlaceholderConst( - PlaceholderLike::new_anon(ty::UniverseIndex::ROOT, self.variables.len().into()), - ), + CanonicalizeMode::Input { .. } => { + CanonicalVarKind::PlaceholderConst(PlaceholderConst::new_anon( + ty::UniverseIndex::ROOT, + self.variables.len().into(), + )) + } CanonicalizeMode::Response { .. } => { CanonicalVarKind::PlaceholderConst(placeholder) } }, ty::ConstKind::Param(_) => match self.canonicalize_mode { - CanonicalizeMode::Input { .. } => CanonicalVarKind::PlaceholderConst( - PlaceholderLike::new_anon(ty::UniverseIndex::ROOT, self.variables.len().into()), - ), + CanonicalizeMode::Input { .. } => { + CanonicalVarKind::PlaceholderConst(PlaceholderConst::new_anon( + ty::UniverseIndex::ROOT, + self.variables.len().into(), + )) + } CanonicalizeMode::Response { .. } => panic!("param ty in response: {c:?}"), }, // FIXME: See comment above -- we could fold the region separately or something. diff --git a/compiler/rustc_next_trait_solver/src/canonical/mod.rs b/compiler/rustc_next_trait_solver/src/canonical/mod.rs index 96fea09013a1..1f64f09fe787 100644 --- a/compiler/rustc_next_trait_solver/src/canonical/mod.rs +++ b/compiler/rustc_next_trait_solver/src/canonical/mod.rs @@ -177,9 +177,9 @@ where } } ty::GenericArgKind::Const(c) => { - if let ty::ConstKind::Bound(index_kind, bv) = c.kind() { + if let ty::ConstKind::Bound(index_kind, bc) = c.kind() { assert!(matches!(index_kind, ty::BoundVarIndexKind::Canonical)); - opt_values[bv.var()] = Some(*original_value); + opt_values[bc.var()] = Some(*original_value); } } } diff --git a/compiler/rustc_next_trait_solver/src/placeholder.rs b/compiler/rustc_next_trait_solver/src/placeholder.rs index c8016759f239..31fce0601697 100644 --- a/compiler/rustc_next_trait_solver/src/placeholder.rs +++ b/compiler/rustc_next_trait_solver/src/placeholder.rs @@ -3,8 +3,8 @@ use core::panic; use rustc_type_ir::data_structures::IndexMap; use rustc_type_ir::inherent::*; use rustc_type_ir::{ - self as ty, InferCtxtLike, Interner, TypeFoldable, TypeFolder, TypeSuperFoldable, - TypeVisitableExt, + self as ty, InferCtxtLike, Interner, PlaceholderConst, PlaceholderRegion, PlaceholderType, + TypeFoldable, TypeFolder, TypeSuperFoldable, TypeVisitableExt, }; pub struct BoundVarReplacer<'a, Infcx, I = ::Interner> @@ -16,9 +16,9 @@ where // These three maps track the bound variable that were replaced by placeholders. It might be // nice to remove these since we already have the `kind` in the placeholder; we really just need // the `var` (but we *could* bring that into scope if we were to track them as we pass them). - mapped_regions: IndexMap, - mapped_types: IndexMap, - mapped_consts: IndexMap, + mapped_regions: IndexMap, ty::BoundRegion>, + mapped_types: IndexMap, ty::BoundTy>, + mapped_consts: IndexMap, ty::BoundConst>, // The current depth relative to *this* folding, *not* the entire normalization. In other words, // the depth of binders we've passed here. current_index: ty::DebruijnIndex, @@ -40,9 +40,9 @@ where value: T, ) -> ( T, - IndexMap, - IndexMap, - IndexMap, + IndexMap, ty::BoundRegion>, + IndexMap, ty::BoundTy>, + IndexMap, ty::BoundConst>, ) { let mut replacer = BoundVarReplacer { infcx, @@ -103,7 +103,7 @@ where if debruijn >= self.current_index => { let universe = self.universe_for(debruijn); - let p = PlaceholderLike::new(universe, br); + let p = PlaceholderRegion::new(universe, br); self.mapped_regions.insert(p, br); Region::new_placeholder(self.cx(), p) } @@ -126,7 +126,7 @@ where if debruijn >= self.current_index => { let universe = self.universe_for(debruijn); - let p = PlaceholderLike::new(universe, bound_ty); + let p = PlaceholderType::new(universe, bound_ty); self.mapped_types.insert(p, bound_ty); Ty::new_placeholder(self.cx(), p) } @@ -150,7 +150,7 @@ where if debruijn >= self.current_index => { let universe = self.universe_for(debruijn); - let p = PlaceholderLike::new(universe, bound_const); + let p = PlaceholderConst::new(universe, bound_const); self.mapped_consts.insert(p, bound_const); Const::new_placeholder(self.cx(), p) } diff --git a/compiler/rustc_parse/messages.ftl b/compiler/rustc_parse/messages.ftl index 449d0b964fd4..3f3300117460 100644 --- a/compiler/rustc_parse/messages.ftl +++ b/compiler/rustc_parse/messages.ftl @@ -98,6 +98,8 @@ parse_bare_cr = {$double_quotes -> } .escape = escape the character +parse_bare_cr_in_frontmatter = bare CR not allowed in frontmatter + parse_bare_cr_in_raw_string = bare CR not allowed in raw string parse_binder_and_polarity = `for<...>` binder not allowed with `{$polarity}` trait polarity modifier @@ -352,7 +354,6 @@ parse_frontmatter_length_mismatch = frontmatter close does not match the opening parse_frontmatter_too_many_dashes = too many `-` symbols: frontmatter openings may be delimited by up to 255 `-` symbols, but found {$len_opening} parse_frontmatter_unclosed = unclosed frontmatter .note = frontmatter opening here was not closed - parse_function_body_equals_expr = function body cannot be `= expression;` .suggestion = surround the expression with `{"{"}` and `{"}"}` instead of `=` and `;` diff --git a/compiler/rustc_parse/src/errors.rs b/compiler/rustc_parse/src/errors.rs index 42327c7e343d..4e789a321649 100644 --- a/compiler/rustc_parse/src/errors.rs +++ b/compiler/rustc_parse/src/errors.rs @@ -829,6 +829,13 @@ pub(crate) struct FrontmatterTooManyDashes { pub len_opening: usize, } +#[derive(Diagnostic)] +#[diag(parse_bare_cr_in_frontmatter)] +pub(crate) struct BareCrFrontmatter { + #[primary_span] + pub span: Span, +} + #[derive(Diagnostic)] #[diag(parse_leading_plus_not_supported)] pub(crate) struct LeadingPlusNotSupported { diff --git a/compiler/rustc_parse/src/lexer/mod.rs b/compiler/rustc_parse/src/lexer/mod.rs index 7c969dd7f9f4..f9bf50de091a 100644 --- a/compiler/rustc_parse/src/lexer/mod.rs +++ b/compiler/rustc_parse/src/lexer/mod.rs @@ -598,9 +598,9 @@ impl<'psess, 'src> Lexer<'psess, 'src> { let s = self.str_from(start); let real_start = s.find("---").unwrap(); let frontmatter_opening_pos = BytePos(real_start as u32) + start; - let s_new = &s[real_start..]; - let within = s_new.trim_start_matches('-'); - let len_opening = s_new.len() - within.len(); + let real_s = &s[real_start..]; + let within = real_s.trim_start_matches('-'); + let len_opening = real_s.len() - within.len(); let frontmatter_opening_end_pos = frontmatter_opening_pos + BytePos(len_opening as u32); if has_invalid_preceding_whitespace { @@ -614,8 +614,8 @@ impl<'psess, 'src> Lexer<'psess, 'src> { }); } + let line_end = real_s.find('\n').unwrap_or(real_s.len()); if invalid_infostring { - let line_end = s[real_start..].find('\n').unwrap_or(s[real_start..].len()); let span = self.mk_sp( frontmatter_opening_end_pos, frontmatter_opening_pos + BytePos(line_end as u32), @@ -623,10 +623,18 @@ impl<'psess, 'src> Lexer<'psess, 'src> { self.dcx().emit_err(errors::FrontmatterInvalidInfostring { span }); } - let last_line_start = within.rfind('\n').map_or(0, |i| i + 1); - let last_line = &within[last_line_start..]; + let last_line_start = real_s.rfind('\n').map_or(0, |i| i + 1); + + let content = &real_s[line_end..last_line_start]; + if let Some(cr_offset) = content.find('\r') { + let cr_pos = start + BytePos((real_start + line_end + cr_offset) as u32); + let span = self.mk_sp(cr_pos, cr_pos + BytePos(1 as u32)); + self.dcx().emit_err(errors::BareCrFrontmatter { span }); + } + + let last_line = &real_s[last_line_start..]; let last_line_trimmed = last_line.trim_start_matches(is_horizontal_whitespace); - let last_line_start_pos = frontmatter_opening_end_pos + BytePos(last_line_start as u32); + let last_line_start_pos = frontmatter_opening_pos + BytePos(last_line_start as u32); let frontmatter_span = self.mk_sp(frontmatter_opening_pos, self.pos); self.psess.gated_spans.gate(sym::frontmatter, frontmatter_span); diff --git a/compiler/rustc_parse/src/parser/expr.rs b/compiler/rustc_parse/src/parser/expr.rs index c31a4798b471..44c6acec8866 100644 --- a/compiler/rustc_parse/src/parser/expr.rs +++ b/compiler/rustc_parse/src/parser/expr.rs @@ -2760,9 +2760,13 @@ impl<'a> Parser<'a> { let (mut cond, _) = self.parse_expr_res(Restrictions::NO_STRUCT_LITERAL | Restrictions::ALLOW_LET, attrs)?; - CondChecker::new(self, let_chains_policy).visit_expr(&mut cond); - - Ok(cond) + let mut checker = CondChecker::new(self, let_chains_policy); + checker.visit_expr(&mut cond); + Ok(if let Some(guar) = checker.found_incorrect_let_chain { + self.mk_expr_err(cond.span, guar) + } else { + cond + }) } /// Parses a `let $pat = $expr` pseudo-expression. @@ -3484,13 +3488,19 @@ impl<'a> Parser<'a> { let if_span = self.prev_token.span; let mut cond = self.parse_match_guard_condition()?; - CondChecker::new(self, LetChainsPolicy::AlwaysAllowed).visit_expr(&mut cond); + let mut checker = CondChecker::new(self, LetChainsPolicy::AlwaysAllowed); + checker.visit_expr(&mut cond); if has_let_expr(&cond) { let span = if_span.to(cond.span); self.psess.gated_spans.gate(sym::if_let_guard, span); } - Ok(Some(cond)) + + Ok(Some(if let Some(guar) = checker.found_incorrect_let_chain { + self.mk_expr_err(cond.span, guar) + } else { + cond + })) } fn parse_match_arm_pat_and_guard(&mut self) -> PResult<'a, (Pat, Option>)> { @@ -3511,13 +3521,23 @@ impl<'a> Parser<'a> { let ast::PatKind::Paren(subpat) = pat.kind else { unreachable!() }; let ast::PatKind::Guard(_, mut cond) = subpat.kind else { unreachable!() }; self.psess.gated_spans.ungate_last(sym::guard_patterns, cond.span); - CondChecker::new(self, LetChainsPolicy::AlwaysAllowed).visit_expr(&mut cond); + let mut checker = CondChecker::new(self, LetChainsPolicy::AlwaysAllowed); + checker.visit_expr(&mut cond); + let right = self.prev_token.span; self.dcx().emit_err(errors::ParenthesesInMatchPat { span: vec![left, right], sugg: errors::ParenthesesInMatchPatSugg { left, right }, }); - Ok((self.mk_pat(span, ast::PatKind::Wild), Some(cond))) + + Ok(( + self.mk_pat(span, ast::PatKind::Wild), + (if let Some(guar) = checker.found_incorrect_let_chain { + Some(self.mk_expr_err(cond.span, guar)) + } else { + Some(cond) + }), + )) } else { Ok((pat, self.parse_match_arm_guard()?)) } @@ -4208,6 +4228,7 @@ struct CondChecker<'a> { forbid_let_reason: Option, missing_let: Option, comparison: Option, + found_incorrect_let_chain: Option, } impl<'a> CondChecker<'a> { @@ -4218,6 +4239,7 @@ impl<'a> CondChecker<'a> { missing_let: None, comparison: None, let_chains_policy, + found_incorrect_let_chain: None, depth: 0, } } @@ -4236,12 +4258,19 @@ impl MutVisitor for CondChecker<'_> { NotSupportedOr(or_span) => { self.parser.dcx().emit_err(errors::OrInLetChain { span: or_span }) } - _ => self.parser.dcx().emit_err(errors::ExpectedExpressionFoundLet { - span, - reason, - missing_let: self.missing_let, - comparison: self.comparison, - }), + _ => { + let guar = + self.parser.dcx().emit_err(errors::ExpectedExpressionFoundLet { + span, + reason, + missing_let: self.missing_let, + comparison: self.comparison, + }); + if let Some(_) = self.missing_let { + self.found_incorrect_let_chain = Some(guar); + } + guar + } }; *recovered = Recovered::Yes(error); } else if self.depth > 1 { diff --git a/compiler/rustc_parse_format/src/lib.rs b/compiler/rustc_parse_format/src/lib.rs index 490af1257760..3d8b97b2fde3 100644 --- a/compiler/rustc_parse_format/src/lib.rs +++ b/compiler/rustc_parse_format/src/lib.rs @@ -758,7 +758,7 @@ impl<'input> Parser<'input> { } /// Parses a word starting at the current position. A word is the same as a - /// Rust identifier, except that it can't start with `_` character. + /// Rust identifier or keyword, except that it can't be a bare `_` character. fn word(&mut self) -> &'input str { let index = self.input_vec_index; match self.peek() { diff --git a/compiler/rustc_passes/src/check_attr.rs b/compiler/rustc_passes/src/check_attr.rs index cdd141f9233e..541870607b63 100644 --- a/compiler/rustc_passes/src/check_attr.rs +++ b/compiler/rustc_passes/src/check_attr.rs @@ -150,7 +150,7 @@ impl<'tcx> CheckAttrVisitor<'tcx> { span: attr_span, stability: Stability { level, feature }, } - | AttributeKind::ConstStability { + | AttributeKind::RustcConstStability { span: attr_span, stability: PartialConstStability { level, feature, .. }, }, @@ -168,7 +168,7 @@ impl<'tcx> CheckAttrVisitor<'tcx> { Attribute::Parsed(AttributeKind::AllowInternalUnsafe(attr_span) | AttributeKind::AllowInternalUnstable(.., attr_span)) => { self.check_macro_only_attr(*attr_span, span, target, attrs) } - Attribute::Parsed(AttributeKind::AllowConstFnUnstable(_, first_span)) => { + Attribute::Parsed(AttributeKind::RustcAllowConstFnUnstable(_, first_span)) => { self.check_rustc_allow_const_fn_unstable(hir_id, *first_span, span, target) } Attribute::Parsed(AttributeKind::Deprecation {span: attr_span, .. }) => { @@ -180,7 +180,7 @@ impl<'tcx> CheckAttrVisitor<'tcx> { Attribute::Parsed(AttributeKind::RustcObjectLifetimeDefault) => { self.check_object_lifetime_default(hir_id); } - &Attribute::Parsed(AttributeKind::PubTransparent(attr_span)) => { + &Attribute::Parsed(AttributeKind::RustcPubTransparent(attr_span)) => { self.check_rustc_pub_transparent(attr_span, span, attrs) } Attribute::Parsed(AttributeKind::Align { align, span: attr_span }) => { @@ -226,29 +226,21 @@ impl<'tcx> CheckAttrVisitor<'tcx> { Attribute::Parsed(AttributeKind::DoNotRecommend{attr_span}) => {self.check_do_not_recommend(*attr_span, hir_id, target, item)}, Attribute::Parsed( // tidy-alphabetical-start - AttributeKind::AllowIncoherentImpl(..) - | AttributeKind::AsPtr(..) + AttributeKind::RustcAllowIncoherentImpl(..) | AttributeKind::AutomaticallyDerived(..) - | AttributeKind::BodyStability { .. } | AttributeKind::CfgAttrTrace | AttributeKind::CfgTrace(..) | AttributeKind::CfiEncoding { .. } - | AttributeKind::Coinductive(..) | AttributeKind::Cold(..) | AttributeKind::CollapseDebugInfo(..) | AttributeKind::CompilerBuiltins - | AttributeKind::Confusables { .. } - | AttributeKind::ConstStabilityIndirect | AttributeKind::Coroutine(..) | AttributeKind::Coverage (..) | AttributeKind::CrateName { .. } | AttributeKind::CrateType(..) | AttributeKind::DebuggerVisualizer(..) - | AttributeKind::DenyExplicitImpl(..) // `#[doc]` is actually a lot more than just doc comments, so is checked below | AttributeKind::DocComment {..} - | AttributeKind::Dummy - | AttributeKind::DynIncompatibleTrait(..) | AttributeKind::EiiDeclaration { .. } | AttributeKind::EiiForeignItem | AttributeKind::ExportName { .. } @@ -262,7 +254,6 @@ impl<'tcx> CheckAttrVisitor<'tcx> { | AttributeKind::LinkSection { .. } | AttributeKind::Linkage(..) | AttributeKind::MacroEscape( .. ) - | AttributeKind::MacroTransparency(_) | AttributeKind::MacroUse { .. } | AttributeKind::Marker(..) | AttributeKind::MoveSizeLimit { .. } @@ -277,12 +268,8 @@ impl<'tcx> CheckAttrVisitor<'tcx> { | AttributeKind::NoMain | AttributeKind::NoMangle(..) | AttributeKind::NoStd { .. } - | AttributeKind::ObjcClass { .. } - | AttributeKind::ObjcSelector { .. } | AttributeKind::Optimize(..) | AttributeKind::PanicRuntime - | AttributeKind::ParenSugar(..) - | AttributeKind::PassByValue (..) | AttributeKind::PatchableFunctionEntry { .. } | AttributeKind::Path(..) | AttributeKind::PatternComplexityLimit { .. } @@ -295,14 +282,22 @@ impl<'tcx> CheckAttrVisitor<'tcx> { | AttributeKind::RustcAllocator | AttributeKind::RustcAllocatorZeroed | AttributeKind::RustcAllocatorZeroedVariant { .. } + | AttributeKind::RustcAsPtr(..) + | AttributeKind::RustcBodyStability { .. } | AttributeKind::RustcBuiltinMacro { .. } | AttributeKind::RustcCoherenceIsCore(..) + | AttributeKind::RustcCoinductive(..) + | AttributeKind::RustcConfusables { .. } + | AttributeKind::RustcConstStabilityIndirect | AttributeKind::RustcDeallocator + | AttributeKind::RustcDenyExplicitImpl(..) + | AttributeKind::RustcDummy | AttributeKind::RustcDumpDefParents | AttributeKind::RustcDumpItemBounds | AttributeKind::RustcDumpPredicates | AttributeKind::RustcDumpUserArgs | AttributeKind::RustcDumpVtable(..) + | AttributeKind::RustcDynIncompatibleTrait(..) | AttributeKind::RustcHasIncoherentInherentImpls | AttributeKind::RustcLayoutScalarValidRangeEnd(..) | AttributeKind::RustcLayoutScalarValidRangeStart(..) @@ -310,26 +305,31 @@ impl<'tcx> CheckAttrVisitor<'tcx> { | AttributeKind::RustcLintOptTy | AttributeKind::RustcLintQueryInstability | AttributeKind::RustcLintUntrackedQueryInformation + | AttributeKind::RustcMacroTransparency(_) | AttributeKind::RustcMain | AttributeKind::RustcNeverReturnsNullPointer | AttributeKind::RustcNoImplicitAutorefs | AttributeKind::RustcNounwind + | AttributeKind::RustcObjcClass { .. } + | AttributeKind::RustcObjcSelector { .. } | AttributeKind::RustcOffloadKernel + | AttributeKind::RustcParenSugar(..) + | AttributeKind::RustcPassByValue (..) | AttributeKind::RustcPassIndirectlyInNonRusticAbis(..) | AttributeKind::RustcReallocator | AttributeKind::RustcScalableVector { .. } | AttributeKind::RustcShouldNotBeCalledOnConstItems(..) | AttributeKind::RustcSimdMonomorphizeLaneLimit(..) + | AttributeKind::RustcSkipDuringMethodDispatch { .. } + | AttributeKind::RustcSpecializationTrait(..) + | AttributeKind::RustcStdInternalSymbol (..) + | AttributeKind::RustcUnsafeSpecializationMarker(..) | AttributeKind::RustcVariance | AttributeKind::RustcVarianceOfOpaques | AttributeKind::ShouldPanic { .. } - | AttributeKind::SkipDuringMethodDispatch { .. } - | AttributeKind::SpecializationTrait(..) - | AttributeKind::StdInternalSymbol (..) | AttributeKind::ThreadLocal | AttributeKind::TypeConst{..} | AttributeKind::TypeLengthLimit { .. } - | AttributeKind::UnsafeSpecializationMarker(..) | AttributeKind::UnstableFeatureBound(..) | AttributeKind::Used { .. } | AttributeKind::WindowsSubsystem(..) diff --git a/compiler/rustc_passes/src/lib_features.rs b/compiler/rustc_passes/src/lib_features.rs index 8d0ef88610af..1f92643815fd 100644 --- a/compiler/rustc_passes/src/lib_features.rs +++ b/compiler/rustc_passes/src/lib_features.rs @@ -30,10 +30,10 @@ impl<'tcx> LibFeatureCollector<'tcx> { Attribute::Parsed(AttributeKind::Stability { stability, span }) => { (stability.feature, stability.level, *span) } - Attribute::Parsed(AttributeKind::ConstStability { stability, span }) => { + Attribute::Parsed(AttributeKind::RustcConstStability { stability, span }) => { (stability.feature, stability.level, *span) } - Attribute::Parsed(AttributeKind::BodyStability { stability, span }) => { + Attribute::Parsed(AttributeKind::RustcBodyStability { stability, span }) => { (stability.feature, stability.level, *span) } _ => return None, diff --git a/compiler/rustc_passes/src/stability.rs b/compiler/rustc_passes/src/stability.rs index 9d94c4cc6225..657b362d5ca1 100644 --- a/compiler/rustc_passes/src/stability.rs +++ b/compiler/rustc_passes/src/stability.rs @@ -197,7 +197,7 @@ fn lookup_default_body_stability( let attrs = tcx.hir_attrs(tcx.local_def_id_to_hir_id(def_id)); // FIXME: check that this item can have body stability - find_attr!(attrs, AttributeKind::BodyStability { stability, .. } => *stability) + find_attr!(attrs, AttributeKind::RustcBodyStability { stability, .. } => *stability) } #[instrument(level = "debug", skip(tcx))] @@ -214,7 +214,7 @@ fn lookup_const_stability(tcx: TyCtxt<'_>, def_id: LocalDefId) -> Option, def_id: LocalDefId) -> Option *stability); + find_attr!(attrs, AttributeKind::RustcConstStability { stability, span: _ } => *stability); // After checking the immediate attributes, get rid of the span and compute implied // const stability: inherit feature gate from regular stability. @@ -393,7 +393,7 @@ impl<'tcx> MissingStabilityAnnotations<'tcx> { if let Some(fn_sig) = fn_sig && !fn_sig.header.is_const() && const_stab.is_some() - && find_attr_span!(ConstStability).is_some() + && find_attr_span!(RustcConstStability).is_some() { self.tcx.dcx().emit_err(errors::MissingConstErr { fn_sig_span: fn_sig.span }); } @@ -403,7 +403,7 @@ impl<'tcx> MissingStabilityAnnotations<'tcx> { && let Some(fn_sig) = fn_sig && const_stab.is_const_stable() && !stab.is_some_and(|s| s.is_stable()) - && let Some(const_span) = find_attr_span!(ConstStability) + && let Some(const_span) = find_attr_span!(RustcConstStability) { self.tcx .dcx() @@ -413,7 +413,7 @@ impl<'tcx> MissingStabilityAnnotations<'tcx> { if let Some(stab) = &const_stab && stab.is_const_stable() && stab.const_stable_indirect - && let Some(span) = find_attr_span!(ConstStability) + && let Some(span) = find_attr_span!(RustcConstStability) { self.tcx.dcx().emit_err(errors::RustcConstStableIndirectPairing { span }); } @@ -602,7 +602,7 @@ impl<'tcx> Visitor<'tcx> for Checker<'tcx> { let stab = find_attr!(attrs, AttributeKind::Stability{stability, span} => (*stability, *span)); // FIXME(jdonszelmann): make it impossible to miss the or_else in the typesystem - let const_stab = find_attr!(attrs, AttributeKind::ConstStability{stability, ..} => *stability); + let const_stab = find_attr!(attrs, AttributeKind::RustcConstStability{stability, ..} => *stability); let unstable_feature_stab = find_attr!(attrs, AttributeKind::UnstableFeatureBound(i) => i) diff --git a/compiler/rustc_privacy/src/lib.rs b/compiler/rustc_privacy/src/lib.rs index 8656ec6e39ae..73446ddcf7e4 100644 --- a/compiler/rustc_privacy/src/lib.rs +++ b/compiler/rustc_privacy/src/lib.rs @@ -497,7 +497,7 @@ impl<'tcx> EmbargoVisitor<'tcx> { let hir_id = self.tcx.local_def_id_to_hir_id(local_def_id); let attrs = self.tcx.hir_attrs(hir_id); - if find_attr!(attrs, AttributeKind::MacroTransparency(x) => *x) + if find_attr!(attrs, AttributeKind::RustcMacroTransparency(x) => *x) .unwrap_or(Transparency::fallback(md.macro_rules)) != Transparency::Opaque { diff --git a/compiler/rustc_public/src/unstable/convert/internal.rs b/compiler/rustc_public/src/unstable/convert/internal.rs index 73a3fed111b3..8594f6510041 100644 --- a/compiler/rustc_public/src/unstable/convert/internal.rs +++ b/compiler/rustc_public/src/unstable/convert/internal.rs @@ -433,7 +433,7 @@ where } impl RustcInternal for BoundVariableKind { - type T<'tcx> = rustc_ty::BoundVariableKind; + type T<'tcx> = rustc_ty::BoundVariableKind<'tcx>; fn internal<'tcx>( &self, diff --git a/compiler/rustc_public/src/unstable/convert/stable/ty.rs b/compiler/rustc_public/src/unstable/convert/stable/ty.rs index cee144122c0e..70cdae43126c 100644 --- a/compiler/rustc_public/src/unstable/convert/stable/ty.rs +++ b/compiler/rustc_public/src/unstable/convert/stable/ty.rs @@ -271,7 +271,7 @@ impl<'tcx> Stable<'tcx> for ty::FnSig<'tcx> { } } -impl<'tcx> Stable<'tcx> for ty::BoundTyKind { +impl<'tcx> Stable<'tcx> for ty::BoundTyKind<'tcx> { type T = crate::ty::BoundTyKind; fn stable<'cx>( @@ -290,7 +290,7 @@ impl<'tcx> Stable<'tcx> for ty::BoundTyKind { } } -impl<'tcx> Stable<'tcx> for ty::BoundRegionKind { +impl<'tcx> Stable<'tcx> for ty::BoundRegionKind<'tcx> { type T = crate::ty::BoundRegionKind; fn stable<'cx>( @@ -307,12 +307,12 @@ impl<'tcx> Stable<'tcx> for ty::BoundRegionKind { cx.tcx.item_name(*def_id).to_string(), ), ty::BoundRegionKind::ClosureEnv => BoundRegionKind::BrEnv, - ty::BoundRegionKind::NamedAnon(_) => bug!("only used for pretty printing"), + ty::BoundRegionKind::NamedForPrinting(_) => bug!("only used for pretty printing"), } } } -impl<'tcx> Stable<'tcx> for ty::BoundVariableKind { +impl<'tcx> Stable<'tcx> for ty::BoundVariableKind<'tcx> { type T = crate::ty::BoundVariableKind; fn stable<'cx>( @@ -546,7 +546,7 @@ impl<'tcx> Stable<'tcx> for ty::ParamTy { } } -impl<'tcx> Stable<'tcx> for ty::BoundTy { +impl<'tcx> Stable<'tcx> for ty::BoundTy<'tcx> { type T = crate::ty::BoundTy; fn stable<'cx>( &self, diff --git a/compiler/rustc_public/src/unstable/internal_cx/mod.rs b/compiler/rustc_public/src/unstable/internal_cx/mod.rs index 601ca4fb5cfd..4da86b9442f1 100644 --- a/compiler/rustc_public/src/unstable/internal_cx/mod.rs +++ b/compiler/rustc_public/src/unstable/internal_cx/mod.rs @@ -78,7 +78,10 @@ impl<'tcx> InternalCx<'tcx> for TyCtxt<'tcx> { fn mk_bound_variable_kinds_from_iter(self, iter: I) -> T::Output where I: Iterator, - T: ty::CollectAndApply>, + T: ty::CollectAndApply< + ty::BoundVariableKind<'tcx>, + &'tcx List>, + >, { TyCtxt::mk_bound_variable_kinds_from_iter(self, iter) } diff --git a/compiler/rustc_public/src/unstable/mod.rs b/compiler/rustc_public/src/unstable/mod.rs index 2b69fb5408cf..583493c23d66 100644 --- a/compiler/rustc_public/src/unstable/mod.rs +++ b/compiler/rustc_public/src/unstable/mod.rs @@ -47,7 +47,10 @@ pub trait InternalCx<'tcx>: Copy + Clone { fn mk_bound_variable_kinds_from_iter(self, iter: I) -> T::Output where I: Iterator, - T: ty::CollectAndApply>; + T: ty::CollectAndApply< + ty::BoundVariableKind<'tcx>, + &'tcx List>, + >; fn mk_place_elems(self, v: &[mir::PlaceElem<'tcx>]) -> &'tcx List>; diff --git a/compiler/rustc_query_impl/src/lib.rs b/compiler/rustc_query_impl/src/lib.rs index e8983bfa1ddb..382b8750a1ce 100644 --- a/compiler/rustc_query_impl/src/lib.rs +++ b/compiler/rustc_query_impl/src/lib.rs @@ -10,19 +10,17 @@ use rustc_data_structures::stable_hasher::HashStable; use rustc_data_structures::sync::AtomicU64; use rustc_middle::arena::Arena; use rustc_middle::dep_graph::{self, DepKind, DepKindVTable, DepNodeIndex}; -use rustc_middle::query::erase::{Erase, erase, restore}; use rustc_middle::query::on_disk_cache::{CacheEncoder, EncodedDepNodeIndex, OnDiskCache}; -use rustc_middle::query::plumbing::{DynamicQuery, QuerySystem, QuerySystemFns}; +use rustc_middle::query::plumbing::{QuerySystem, QuerySystemFns, QueryVTable}; use rustc_middle::query::{ - AsLocalKey, DynamicQueries, ExternProviders, Providers, QueryCaches, QueryEngine, QueryStates, - queries, + AsLocalKey, ExternProviders, Providers, QueryCaches, QueryEngine, QueryStates, queries, }; use rustc_middle::ty::TyCtxt; use rustc_query_system::Value; use rustc_query_system::dep_graph::SerializedDepNodeIndex; use rustc_query_system::ich::StableHashingContext; use rustc_query_system::query::{ - CycleError, CycleErrorHandling, HashResult, QueryCache, QueryConfig, QueryMap, QueryMode, + CycleError, CycleErrorHandling, HashResult, QueryCache, QueryDispatcher, QueryMap, QueryMode, QueryStackDeferred, QueryState, get_query_incr, get_query_non_incr, }; use rustc_span::{ErrorGuaranteed, Span}; @@ -37,45 +35,54 @@ pub use crate::plumbing::{QueryCtxt, query_key_hash_verify_all}; mod profiling_support; pub use self::profiling_support::alloc_self_profile_query_strings; -struct DynamicConfig< +/// Combines a [`QueryVTable`] with some additional compile-time booleans +/// to implement [`QueryDispatcher`], for use by code in [`rustc_query_system`]. +/// +/// Baking these boolean flags into the type gives a modest but measurable +/// improvement to compiler perf and compiler code size; see +/// . +struct SemiDynamicQueryDispatcher< 'tcx, C: QueryCache, const ANON: bool, const DEPTH_LIMIT: bool, const FEEDABLE: bool, > { - dynamic: &'tcx DynamicQuery<'tcx, C>, + vtable: &'tcx QueryVTable<'tcx, C>, } +// Manually implement Copy/Clone, because deriving would put trait bounds on the cache type. impl<'tcx, C: QueryCache, const ANON: bool, const DEPTH_LIMIT: bool, const FEEDABLE: bool> Copy - for DynamicConfig<'tcx, C, ANON, DEPTH_LIMIT, FEEDABLE> + for SemiDynamicQueryDispatcher<'tcx, C, ANON, DEPTH_LIMIT, FEEDABLE> { } impl<'tcx, C: QueryCache, const ANON: bool, const DEPTH_LIMIT: bool, const FEEDABLE: bool> Clone - for DynamicConfig<'tcx, C, ANON, DEPTH_LIMIT, FEEDABLE> + for SemiDynamicQueryDispatcher<'tcx, C, ANON, DEPTH_LIMIT, FEEDABLE> { fn clone(&self) -> Self { *self } } +// This is `impl QueryDispatcher for SemiDynamicQueryDispatcher`. impl<'tcx, C: QueryCache, const ANON: bool, const DEPTH_LIMIT: bool, const FEEDABLE: bool> - QueryConfig> for DynamicConfig<'tcx, C, ANON, DEPTH_LIMIT, FEEDABLE> + QueryDispatcher for SemiDynamicQueryDispatcher<'tcx, C, ANON, DEPTH_LIMIT, FEEDABLE> where for<'a> C::Key: HashStable>, { + type Qcx = QueryCtxt<'tcx>; type Key = C::Key; type Value = C::Value; type Cache = C; #[inline(always)] fn name(self) -> &'static str { - self.dynamic.name + self.vtable.name } #[inline(always)] fn cache_on_disk(self, tcx: TyCtxt<'tcx>, key: &Self::Key) -> bool { - (self.dynamic.cache_on_disk)(tcx, key) + (self.vtable.cache_on_disk)(tcx, key) } #[inline(always)] @@ -90,33 +97,30 @@ where // This is just manually doing the subfield referencing through pointer math. unsafe { &*(&qcx.tcx.query_system.states as *const QueryStates<'tcx>) - .byte_add(self.dynamic.query_state) + .byte_add(self.vtable.query_state) .cast::>>() } } #[inline(always)] - fn query_cache<'a>(self, qcx: QueryCtxt<'tcx>) -> &'a Self::Cache - where - 'tcx: 'a, - { + fn query_cache<'a>(self, qcx: QueryCtxt<'tcx>) -> &'a Self::Cache { // Safety: // This is just manually doing the subfield referencing through pointer math. unsafe { &*(&qcx.tcx.query_system.caches as *const QueryCaches<'tcx>) - .byte_add(self.dynamic.query_cache) + .byte_add(self.vtable.query_cache) .cast::() } } #[inline(always)] fn execute_query(self, tcx: TyCtxt<'tcx>, key: Self::Key) -> Self::Value { - (self.dynamic.execute_query)(tcx, key) + (self.vtable.execute_query)(tcx, key) } #[inline(always)] fn compute(self, qcx: QueryCtxt<'tcx>, key: Self::Key) -> Self::Value { - (self.dynamic.compute)(qcx.tcx, key) + (self.vtable.compute)(qcx.tcx, key) } #[inline(always)] @@ -127,8 +131,8 @@ where prev_index: SerializedDepNodeIndex, index: DepNodeIndex, ) -> Option { - if self.dynamic.can_load_from_disk { - (self.dynamic.try_load_from_disk)(qcx.tcx, key, prev_index, index) + if self.vtable.can_load_from_disk { + (self.vtable.try_load_from_disk)(qcx.tcx, key, prev_index, index) } else { None } @@ -141,7 +145,7 @@ where key: &Self::Key, index: SerializedDepNodeIndex, ) -> bool { - (self.dynamic.loadable_from_disk)(qcx.tcx, key, index) + (self.vtable.loadable_from_disk)(qcx.tcx, key, index) } fn value_from_cycle_error( @@ -150,12 +154,12 @@ where cycle_error: &CycleError, guar: ErrorGuaranteed, ) -> Self::Value { - (self.dynamic.value_from_cycle_error)(tcx, cycle_error, guar) + (self.vtable.value_from_cycle_error)(tcx, cycle_error, guar) } #[inline(always)] fn format_value(self) -> fn(&Self::Value) -> String { - self.dynamic.format_value + self.vtable.format_value } #[inline(always)] @@ -165,7 +169,7 @@ where #[inline(always)] fn eval_always(self) -> bool { - self.dynamic.eval_always + self.vtable.eval_always } #[inline(always)] @@ -180,31 +184,40 @@ where #[inline(always)] fn dep_kind(self) -> DepKind { - self.dynamic.dep_kind + self.vtable.dep_kind } #[inline(always)] fn cycle_error_handling(self) -> CycleErrorHandling { - self.dynamic.cycle_error_handling + self.vtable.cycle_error_handling } #[inline(always)] fn hash_result(self) -> HashResult { - self.dynamic.hash_result + self.vtable.hash_result } } -/// This is implemented per query. It allows restoring query values from their erased state -/// and constructing a QueryConfig. -trait QueryConfigRestored<'tcx> { - type RestoredValue; - type Config: QueryConfig>; +/// Provides access to vtable-like operations for a query +/// (by creating a [`QueryDispatcher`]), +/// but also keeps track of the "unerased" value type of the query +/// (i.e. the actual result type in the query declaration). +/// +/// This trait allows some per-query code to be defined in generic functions +/// with a trait bound, instead of having to be defined inline within a macro +/// expansion. +/// +/// There is one macro-generated implementation of this trait for each query, +/// on the type `rustc_query_impl::query_impl::$name::QueryType`. +trait QueryDispatcherUnerased<'tcx> { + type UnerasedValue; + type Dispatcher: QueryDispatcher>; const NAME: &'static &'static str; - fn config(tcx: TyCtxt<'tcx>) -> Self::Config; - fn restore(value: >>::Value) - -> Self::RestoredValue; + fn query_dispatcher(tcx: TyCtxt<'tcx>) -> Self::Dispatcher; + + fn restore_val(value: ::Value) -> Self::UnerasedValue; } pub fn query_system<'a>( @@ -217,7 +230,7 @@ pub fn query_system<'a>( states: Default::default(), arenas: Default::default(), caches: Default::default(), - dynamic_queries: dynamic_queries(), + query_vtables: make_query_vtables(), on_disk_cache, fns: QuerySystemFns { engine: engine(incremental), diff --git a/compiler/rustc_query_impl/src/plumbing.rs b/compiler/rustc_query_impl/src/plumbing.rs index 0c3fcf25c655..c71352c3fd20 100644 --- a/compiler/rustc_query_impl/src/plumbing.rs +++ b/compiler/rustc_query_impl/src/plumbing.rs @@ -27,14 +27,14 @@ use rustc_middle::ty::{self, TyCtxt}; use rustc_query_system::dep_graph::{DepNodeParams, HasDepContext}; use rustc_query_system::ich::StableHashingContext; use rustc_query_system::query::{ - QueryCache, QueryConfig, QueryContext, QueryJobId, QueryMap, QuerySideEffect, + QueryCache, QueryContext, QueryDispatcher, QueryJobId, QueryMap, QuerySideEffect, QueryStackDeferred, QueryStackFrame, QueryStackFrameExtra, force_query, }; use rustc_query_system::{QueryOverflow, QueryOverflowNote}; use rustc_serialize::{Decodable, Encodable}; use rustc_span::def_id::LOCAL_CRATE; -use crate::QueryConfigRestored; +use crate::QueryDispatcherUnerased; /// Implements [`QueryContext`] for use by [`rustc_query_system`], since that /// crate does not have direct access to [`TyCtxt`]. @@ -281,7 +281,10 @@ macro_rules! feedable { macro_rules! hash_result { ([][$V:ty]) => {{ - Some(|hcx, result| dep_graph::hash_result(hcx, &restore::<$V>(*result))) + Some(|hcx, result| { + let result = ::rustc_middle::query::erase::restore_val::<$V>(*result); + ::rustc_query_system::dep_graph::hash_result(hcx, &result) + }) }}; ([(no_hash) $($rest:tt)*][$V:ty]) => {{ None @@ -387,13 +390,13 @@ pub(crate) fn create_query_frame< } pub(crate) fn encode_query_results<'a, 'tcx, Q>( - query: Q::Config, + query: Q::Dispatcher, qcx: QueryCtxt<'tcx>, encoder: &mut CacheEncoder<'a, 'tcx>, query_result_index: &mut EncodedDepNodeIndex, ) where - Q: super::QueryConfigRestored<'tcx>, - Q::RestoredValue: Encodable>, + Q: QueryDispatcherUnerased<'tcx>, + Q::UnerasedValue: Encodable>, { let _timer = qcx.tcx.prof.generic_activity_with_arg("encode_query_results_for", query.name()); @@ -408,13 +411,13 @@ pub(crate) fn encode_query_results<'a, 'tcx, Q>( // Encode the type check tables with the `SerializedDepNodeIndex` // as tag. - encoder.encode_tagged(dep_node, &Q::restore(*value)); + encoder.encode_tagged(dep_node, &Q::restore_val(*value)); } }); } pub(crate) fn query_key_hash_verify<'tcx>( - query: impl QueryConfig>, + query: impl QueryDispatcher>, qcx: QueryCtxt<'tcx>, ) { let _timer = qcx.tcx.prof.generic_activity_with_arg("query_key_hash_verify_for", query.name()); @@ -442,7 +445,7 @@ pub(crate) fn query_key_hash_verify<'tcx>( fn try_load_from_on_disk_cache<'tcx, Q>(query: Q, tcx: TyCtxt<'tcx>, dep_node: DepNode) where - Q: QueryConfig>, + Q: QueryDispatcher>, { debug_assert!(tcx.dep_graph.is_green(&dep_node)); @@ -488,7 +491,7 @@ where fn force_from_dep_node<'tcx, Q>(query: Q, tcx: TyCtxt<'tcx>, dep_node: DepNode) -> bool where - Q: QueryConfig>, + Q: QueryDispatcher>, { // We must avoid ever having to call `force_from_dep_node()` for a // `DepNode::codegen_unit`: @@ -521,9 +524,9 @@ pub(crate) fn make_dep_kind_vtable_for_query<'tcx, Q>( is_eval_always: bool, ) -> DepKindVTable<'tcx> where - Q: QueryConfigRestored<'tcx>, + Q: QueryDispatcherUnerased<'tcx>, { - let fingerprint_style = >>::Key::fingerprint_style(); + let fingerprint_style = ::Key::fingerprint_style(); if is_anon || !fingerprint_style.reconstructible() { return DepKindVTable { @@ -541,10 +544,10 @@ where is_eval_always, fingerprint_style, force_from_dep_node: Some(|tcx, dep_node, _| { - force_from_dep_node(Q::config(tcx), tcx, dep_node) + force_from_dep_node(Q::query_dispatcher(tcx), tcx, dep_node) }), try_load_from_on_disk_cache: Some(|tcx, dep_node| { - try_load_from_on_disk_cache(Q::config(tcx), tcx, dep_node) + try_load_from_on_disk_cache(Q::query_dispatcher(tcx), tcx, dep_node) }), name: Q::NAME, } @@ -597,6 +600,7 @@ macro_rules! define_queries { pub(crate) mod query_impl { $(pub(crate) mod $name { use super::super::*; use std::marker::PhantomData; + use ::rustc_middle::query::erase::{self, Erased}; pub(crate) mod get_query_incr { use super::*; @@ -609,11 +613,11 @@ macro_rules! define_queries { span: Span, key: queries::$name::Key<'tcx>, mode: QueryMode, - ) -> Option>> { + ) -> Option>> { #[cfg(debug_assertions)] let _guard = tracing::span!(tracing::Level::TRACE, stringify!($name), ?key).entered(); get_query_incr( - QueryType::config(tcx), + QueryType::query_dispatcher(tcx), QueryCtxt::new(tcx), span, key, @@ -631,9 +635,9 @@ macro_rules! define_queries { span: Span, key: queries::$name::Key<'tcx>, __mode: QueryMode, - ) -> Option>> { + ) -> Option>> { Some(get_query_non_incr( - QueryType::config(tcx), + QueryType::query_dispatcher(tcx), QueryCtxt::new(tcx), span, key, @@ -641,10 +645,10 @@ macro_rules! define_queries { } } - pub(crate) fn dynamic_query<'tcx>() - -> DynamicQuery<'tcx, queries::$name::Storage<'tcx>> + pub(crate) fn make_query_vtable<'tcx>() + -> QueryVTable<'tcx, queries::$name::Storage<'tcx>> { - DynamicQuery { + QueryVTable { name: stringify!($name), eval_always: is_eval_always!([$($modifiers)*]), dep_kind: dep_graph::dep_kinds::$name, @@ -652,7 +656,7 @@ macro_rules! define_queries { query_state: std::mem::offset_of!(QueryStates<'tcx>, $name), query_cache: std::mem::offset_of!(QueryCaches<'tcx>, $name), cache_on_disk: |tcx, key| ::rustc_middle::query::cached::$name(tcx, key), - execute_query: |tcx, key| erase(tcx.$name(key)), + execute_query: |tcx, key| erase::erase_val(tcx.$name(key)), compute: |tcx, key| { #[cfg(debug_assertions)] let _guard = tracing::span!(tracing::Level::TRACE, stringify!($name), ?key).entered(); @@ -690,7 +694,7 @@ macro_rules! define_queries { }), value_from_cycle_error: |tcx, cycle, guar| { let result: queries::$name::Value<'tcx> = Value::from_cycle_error(tcx, cycle, guar); - erase(result) + erase::erase_val(result) }, loadable_from_disk: |_tcx, _key, _index| { should_ever_cache_on_disk!([$($modifiers)*] { @@ -701,7 +705,7 @@ macro_rules! define_queries { }) }, hash_result: hash_result!([$($modifiers)*][queries::$name::Value<'tcx>]), - format_value: |value| format!("{:?}", restore::>(*value)), + format_value: |value| format!("{:?}", erase::restore_val::>(*value)), } } @@ -710,9 +714,9 @@ macro_rules! define_queries { data: PhantomData<&'tcx ()> } - impl<'tcx> QueryConfigRestored<'tcx> for QueryType<'tcx> { - type RestoredValue = queries::$name::Value<'tcx>; - type Config = DynamicConfig< + impl<'tcx> QueryDispatcherUnerased<'tcx> for QueryType<'tcx> { + type UnerasedValue = queries::$name::Value<'tcx>; + type Dispatcher = SemiDynamicQueryDispatcher< 'tcx, queries::$name::Storage<'tcx>, { is_anon!([$($modifiers)*]) }, @@ -723,15 +727,15 @@ macro_rules! define_queries { const NAME: &'static &'static str = &stringify!($name); #[inline(always)] - fn config(tcx: TyCtxt<'tcx>) -> Self::Config { - DynamicConfig { - dynamic: &tcx.query_system.dynamic_queries.$name, + fn query_dispatcher(tcx: TyCtxt<'tcx>) -> Self::Dispatcher { + SemiDynamicQueryDispatcher { + vtable: &tcx.query_system.query_vtables.$name, } } #[inline(always)] - fn restore(value: >>::Value) -> Self::RestoredValue { - restore::>(value) + fn restore_val(value: ::Value) -> Self::UnerasedValue { + erase::restore_val::>(value) } } @@ -782,7 +786,7 @@ macro_rules! define_queries { query_result_index: &mut EncodedDepNodeIndex ) { $crate::plumbing::encode_query_results::>( - query_impl::$name::QueryType::config(tcx), + query_impl::$name::QueryType::query_dispatcher(tcx), QueryCtxt::new(tcx), encoder, query_result_index, @@ -792,7 +796,7 @@ macro_rules! define_queries { pub(crate) fn query_key_hash_verify<'tcx>(tcx: TyCtxt<'tcx>) { $crate::plumbing::query_key_hash_verify( - query_impl::$name::QueryType::config(tcx), + query_impl::$name::QueryType::query_dispatcher(tcx), QueryCtxt::new(tcx), ) } @@ -810,10 +814,10 @@ macro_rules! define_queries { } } - pub fn dynamic_queries<'tcx>() -> DynamicQueries<'tcx> { - DynamicQueries { + pub fn make_query_vtables<'tcx>() -> ::rustc_middle::query::PerQueryVTables<'tcx> { + ::rustc_middle::query::PerQueryVTables { $( - $name: query_impl::$name::dynamic_query(), + $name: query_impl::$name::make_query_vtable(), )* } } diff --git a/compiler/rustc_query_system/src/query/config.rs b/compiler/rustc_query_system/src/query/dispatcher.rs similarity index 52% rename from compiler/rustc_query_system/src/query/config.rs rename to compiler/rustc_query_system/src/query/dispatcher.rs index 66b04aa7b467..1ca76a70364c 100644 --- a/compiler/rustc_query_system/src/query/config.rs +++ b/compiler/rustc_query_system/src/query/dispatcher.rs @@ -1,5 +1,3 @@ -//! Query configuration and description traits. - use std::fmt::Debug; use std::hash::Hash; @@ -7,19 +5,35 @@ use rustc_data_structures::fingerprint::Fingerprint; use rustc_span::ErrorGuaranteed; use super::QueryStackFrameExtra; -use crate::dep_graph::{DepKind, DepNode, DepNodeParams, SerializedDepNodeIndex}; +use crate::dep_graph::{DepKind, DepNode, DepNodeParams, HasDepContext, SerializedDepNodeIndex}; use crate::ich::StableHashingContext; use crate::query::caches::QueryCache; use crate::query::{CycleError, CycleErrorHandling, DepNodeIndex, QueryContext, QueryState}; pub type HashResult = Option, &V) -> Fingerprint>; -pub trait QueryConfig: Copy { +/// Unambiguous shorthand for `::DepContext`. +#[expect(type_alias_bounds)] +type DepContextOf = + <::Qcx as HasDepContext>::DepContext; + +/// Trait that can be used as a vtable for a single query, providing operations +/// and metadata for that query. +/// +/// Implemented by `rustc_query_impl::SemiDynamicQueryDispatcher`, which +/// mostly delegates to `rustc_middle::query::plumbing::QueryVTable`. +/// Those types are not visible from this `rustc_query_system` crate. +/// +/// "Dispatcher" should be understood as a near-synonym of "vtable". +pub trait QueryDispatcher: Copy { fn name(self) -> &'static str; + /// Query context used by this dispatcher, i.e. `rustc_query_impl::QueryCtxt`. + type Qcx: QueryContext; + // `Key` and `Value` are `Copy` instead of `Clone` to ensure copying them stays cheap, // but it isn't necessary. - type Key: DepNodeParams + Eq + Hash + Copy + Debug; + type Key: DepNodeParams> + Eq + Hash + Copy + Debug; type Value: Copy; type Cache: QueryCache; @@ -27,36 +41,40 @@ pub trait QueryConfig: Copy { fn format_value(self) -> fn(&Self::Value) -> String; // Don't use this method to access query results, instead use the methods on TyCtxt - fn query_state<'a>(self, tcx: Qcx) -> &'a QueryState - where - Qcx: 'a; + fn query_state<'a>( + self, + tcx: Self::Qcx, + ) -> &'a QueryState::QueryInfo>; // Don't use this method to access query results, instead use the methods on TyCtxt - fn query_cache<'a>(self, tcx: Qcx) -> &'a Self::Cache - where - Qcx: 'a; + fn query_cache<'a>(self, tcx: Self::Qcx) -> &'a Self::Cache; - fn cache_on_disk(self, tcx: Qcx::DepContext, key: &Self::Key) -> bool; + fn cache_on_disk(self, tcx: DepContextOf, key: &Self::Key) -> bool; // Don't use this method to compute query results, instead use the methods on TyCtxt - fn execute_query(self, tcx: Qcx::DepContext, k: Self::Key) -> Self::Value; + fn execute_query(self, tcx: DepContextOf, k: Self::Key) -> Self::Value; - fn compute(self, tcx: Qcx, key: Self::Key) -> Self::Value; + fn compute(self, tcx: Self::Qcx, key: Self::Key) -> Self::Value; fn try_load_from_disk( self, - tcx: Qcx, + tcx: Self::Qcx, key: &Self::Key, prev_index: SerializedDepNodeIndex, index: DepNodeIndex, ) -> Option; - fn loadable_from_disk(self, qcx: Qcx, key: &Self::Key, idx: SerializedDepNodeIndex) -> bool; + fn loadable_from_disk( + self, + qcx: Self::Qcx, + key: &Self::Key, + idx: SerializedDepNodeIndex, + ) -> bool; /// Synthesize an error value to let compilation continue after a cycle. fn value_from_cycle_error( self, - tcx: Qcx::DepContext, + tcx: DepContextOf, cycle_error: &CycleError, guar: ErrorGuaranteed, ) -> Self::Value; @@ -71,7 +89,7 @@ pub trait QueryConfig: Copy { fn hash_result(self) -> HashResult; // Just here for convenience and checking that the key matches the kind, don't override this. - fn construct_dep_node(self, tcx: Qcx::DepContext, key: &Self::Key) -> DepNode { + fn construct_dep_node(self, tcx: DepContextOf, key: &Self::Key) -> DepNode { DepNode::construct(tcx, self.dep_kind(), key) } } diff --git a/compiler/rustc_query_system/src/query/mod.rs b/compiler/rustc_query_system/src/query/mod.rs index 3ff980fa9bc5..701253d50fcc 100644 --- a/compiler/rustc_query_system/src/query/mod.rs +++ b/compiler/rustc_query_system/src/query/mod.rs @@ -13,7 +13,7 @@ use rustc_span::Span; use rustc_span::def_id::DefId; pub use self::caches::{DefIdCache, DefaultCache, QueryCache, SingleCache, VecCache}; -pub use self::config::{HashResult, QueryConfig}; +pub use self::dispatcher::{HashResult, QueryDispatcher}; pub use self::job::{ QueryInfo, QueryJob, QueryJobId, QueryJobInfo, QueryMap, break_query_cycles, print_query_stack, report_cycle, @@ -22,7 +22,7 @@ pub use self::plumbing::*; use crate::dep_graph::{DepKind, DepNodeIndex, HasDepContext, SerializedDepNodeIndex}; mod caches; -mod config; +mod dispatcher; mod job; mod plumbing; diff --git a/compiler/rustc_query_system/src/query/plumbing.rs b/compiler/rustc_query_system/src/query/plumbing.rs index 5be4ee145208..7e9f83e8fe82 100644 --- a/compiler/rustc_query_system/src/query/plumbing.rs +++ b/compiler/rustc_query_system/src/query/plumbing.rs @@ -18,8 +18,10 @@ use rustc_errors::{Diag, FatalError, StashKey}; use rustc_span::{DUMMY_SP, Span}; use tracing::instrument; -use super::{QueryConfig, QueryStackFrameExtra}; -use crate::dep_graph::{DepContext, DepGraphData, DepNode, DepNodeIndex, DepNodeParams}; +use super::{QueryDispatcher, QueryStackFrameExtra}; +use crate::dep_graph::{ + DepContext, DepGraphData, DepNode, DepNodeIndex, DepNodeParams, HasDepContext, +}; use crate::ich::StableHashingContext; use crate::query::caches::QueryCache; use crate::query::job::{QueryInfo, QueryJob, QueryJobId, QueryJobInfo, QueryLatch, report_cycle}; @@ -124,24 +126,22 @@ where #[cold] #[inline(never)] -fn mk_cycle(query: Q, qcx: Qcx, cycle_error: CycleError) -> Q::Value +fn mk_cycle(query: Q, qcx: Q::Qcx, cycle_error: CycleError) -> Q::Value where - Q: QueryConfig, - Qcx: QueryContext, + Q: QueryDispatcher, { let error = report_cycle(qcx.dep_context().sess(), &cycle_error); handle_cycle_error(query, qcx, &cycle_error, error) } -fn handle_cycle_error( +fn handle_cycle_error( query: Q, - qcx: Qcx, + qcx: Q::Qcx, cycle_error: &CycleError, error: Diag<'_>, ) -> Q::Value where - Q: QueryConfig, - Qcx: QueryContext, + Q: QueryDispatcher, { match query.cycle_error_handling() { CycleErrorHandling::Error => { @@ -272,15 +272,14 @@ where #[cold] #[inline(never)] -fn cycle_error( +fn cycle_error( query: Q, - qcx: Qcx, + qcx: Q::Qcx, try_execute: QueryJobId, span: Span, ) -> (Q::Value, Option) where - Q: QueryConfig, - Qcx: QueryContext, + Q: QueryDispatcher, { // Ensure there was no errors collecting all active jobs. // We need the complete map to ensure we find a cycle to break. @@ -291,17 +290,16 @@ where } #[inline(always)] -fn wait_for_query( +fn wait_for_query( query: Q, - qcx: Qcx, + qcx: Q::Qcx, span: Span, key: Q::Key, - latch: QueryLatch, + latch: QueryLatch<::QueryInfo>, current: Option, ) -> (Q::Value, Option) where - Q: QueryConfig, - Qcx: QueryContext, + Q: QueryDispatcher, { // For parallel queries, we'll block and wait until the query running // in another thread has completed. Record how long we wait in the @@ -341,16 +339,15 @@ where } #[inline(never)] -fn try_execute_query( +fn try_execute_query( query: Q, - qcx: Qcx, + qcx: Q::Qcx, span: Span, key: Q::Key, dep_node: Option, ) -> (Q::Value, Option) where - Q: QueryConfig, - Qcx: QueryContext, + Q: QueryDispatcher, { let state = query.query_state(qcx); let key_hash = sharded::make_hash(&key); @@ -382,7 +379,7 @@ where // Drop the lock before we start executing the query drop(state_lock); - execute_job::<_, _, INCR>(query, qcx, state, key, key_hash, id, dep_node) + execute_job::(query, qcx, state, key, key_hash, id, dep_node) } Entry::Occupied(mut entry) => { match &mut entry.get_mut().1 { @@ -411,18 +408,17 @@ where } #[inline(always)] -fn execute_job( +fn execute_job( query: Q, - qcx: Qcx, - state: &QueryState, + qcx: Q::Qcx, + state: &QueryState::QueryInfo>, key: Q::Key, key_hash: u64, id: QueryJobId, dep_node: Option, ) -> (Q::Value, Option) where - Q: QueryConfig, - Qcx: QueryContext, + Q: QueryDispatcher, { // Use `JobOwner` so the query will be poisoned if executing it panics. let job_owner = JobOwner { state, key }; @@ -484,15 +480,14 @@ where // Fast path for when incr. comp. is off. #[inline(always)] -fn execute_job_non_incr( +fn execute_job_non_incr( query: Q, - qcx: Qcx, + qcx: Q::Qcx, key: Q::Key, job_id: QueryJobId, ) -> (Q::Value, DepNodeIndex) where - Q: QueryConfig, - Qcx: QueryContext, + Q: QueryDispatcher, { debug_assert!(!qcx.dep_context().dep_graph().is_fully_enabled()); @@ -521,17 +516,16 @@ where } #[inline(always)] -fn execute_job_incr( +fn execute_job_incr( query: Q, - qcx: Qcx, - dep_graph_data: &DepGraphData, + qcx: Q::Qcx, + dep_graph_data: &DepGraphData<::Deps>, key: Q::Key, mut dep_node_opt: Option, job_id: QueryJobId, ) -> (Q::Value, DepNodeIndex) where - Q: QueryConfig, - Qcx: QueryContext, + Q: QueryDispatcher, { if !query.anon() && !query.eval_always() { // `to_dep_node` is expensive for some `DepKind`s. @@ -577,16 +571,15 @@ where } #[inline(always)] -fn try_load_from_disk_and_cache_in_memory( +fn try_load_from_disk_and_cache_in_memory( query: Q, - dep_graph_data: &DepGraphData, - qcx: Qcx, + dep_graph_data: &DepGraphData<::Deps>, + qcx: Q::Qcx, key: &Q::Key, dep_node: &DepNode, ) -> Option<(Q::Value, DepNodeIndex)> where - Q: QueryConfig, - Qcx: QueryContext, + Q: QueryDispatcher, { // Note this function can be called concurrently from the same query // We must ensure that this is handled correctly. @@ -764,15 +757,14 @@ fn incremental_verify_ich_failed( /// /// Note: The optimization is only available during incr. comp. #[inline(never)] -fn ensure_must_run( +fn ensure_must_run( query: Q, - qcx: Qcx, + qcx: Q::Qcx, key: &Q::Key, check_cache: bool, ) -> (bool, Option) where - Q: QueryConfig, - Qcx: QueryContext, + Q: QueryDispatcher, { if query.eval_always() { return (true, None); @@ -817,27 +809,25 @@ pub enum QueryMode { } #[inline(always)] -pub fn get_query_non_incr(query: Q, qcx: Qcx, span: Span, key: Q::Key) -> Q::Value +pub fn get_query_non_incr(query: Q, qcx: Q::Qcx, span: Span, key: Q::Key) -> Q::Value where - Q: QueryConfig, - Qcx: QueryContext, + Q: QueryDispatcher, { debug_assert!(!qcx.dep_context().dep_graph().is_fully_enabled()); - ensure_sufficient_stack(|| try_execute_query::(query, qcx, span, key, None).0) + ensure_sufficient_stack(|| try_execute_query::(query, qcx, span, key, None).0) } #[inline(always)] -pub fn get_query_incr( +pub fn get_query_incr( query: Q, - qcx: Qcx, + qcx: Q::Qcx, span: Span, key: Q::Key, mode: QueryMode, ) -> Option where - Q: QueryConfig, - Qcx: QueryContext, + Q: QueryDispatcher, { debug_assert!(qcx.dep_context().dep_graph().is_fully_enabled()); @@ -851,19 +841,17 @@ where None }; - let (result, dep_node_index) = ensure_sufficient_stack(|| { - try_execute_query::<_, _, true>(query, qcx, span, key, dep_node) - }); + let (result, dep_node_index) = + ensure_sufficient_stack(|| try_execute_query::(query, qcx, span, key, dep_node)); if let Some(dep_node_index) = dep_node_index { qcx.dep_context().dep_graph().read_index(dep_node_index) } Some(result) } -pub fn force_query(query: Q, qcx: Qcx, key: Q::Key, dep_node: DepNode) +pub fn force_query(query: Q, qcx: Q::Qcx, key: Q::Key, dep_node: DepNode) where - Q: QueryConfig, - Qcx: QueryContext, + Q: QueryDispatcher, { // We may be concurrently trying both execute and force a query. // Ensure that only one of them runs the query. @@ -875,6 +863,6 @@ where debug_assert!(!query.anon()); ensure_sufficient_stack(|| { - try_execute_query::<_, _, true>(query, qcx, DUMMY_SP, key, Some(dep_node)) + try_execute_query::(query, qcx, DUMMY_SP, key, Some(dep_node)) }); } diff --git a/compiler/rustc_resolve/src/build_reduced_graph.rs b/compiler/rustc_resolve/src/build_reduced_graph.rs index aa458024b89e..f0dffd8829da 100644 --- a/compiler/rustc_resolve/src/build_reduced_graph.rs +++ b/compiler/rustc_resolve/src/build_reduced_graph.rs @@ -26,7 +26,7 @@ use rustc_middle::metadata::{ModChild, Reexport}; use rustc_middle::ty::{Feed, Visibility}; use rustc_middle::{bug, span_bug}; use rustc_span::hygiene::{ExpnId, LocalExpnId, MacroKind}; -use rustc_span::{Ident, Macros20NormalizedIdent, Span, Symbol, kw, sym}; +use rustc_span::{Ident, Span, Symbol, kw, sym}; use thin_vec::ThinVec; use tracing::debug; @@ -36,9 +36,9 @@ use crate::imports::{ImportData, ImportKind}; use crate::macros::{MacroRulesDecl, MacroRulesScope, MacroRulesScopeRef}; use crate::ref_mut::CmCell; use crate::{ - BindingKey, Decl, DeclData, DeclKind, ExternPreludeEntry, Finalize, MacroData, Module, - ModuleKind, ModuleOrUniformRoot, ParentScope, PathResult, ResolutionError, Resolver, Segment, - Used, VisResolutionError, errors, + BindingKey, Decl, DeclData, DeclKind, ExternPreludeEntry, Finalize, IdentKey, MacroData, + Module, ModuleKind, ModuleOrUniformRoot, ParentScope, PathResult, ResolutionError, Resolver, + Segment, Used, VisResolutionError, errors, }; type Res = def::Res; @@ -48,20 +48,23 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { /// and report an error in case of a collision. pub(crate) fn plant_decl_into_local_module( &mut self, - ident: Macros20NormalizedIdent, + ident: IdentKey, + orig_ident_span: Span, ns: Namespace, decl: Decl<'ra>, ) { - if let Err(old_decl) = self.try_plant_decl_into_local_module(ident, ns, decl, false) { - self.report_conflict(ident.0, ns, old_decl, decl); + if let Err(old_decl) = + self.try_plant_decl_into_local_module(ident, orig_ident_span, ns, decl, false) + { + self.report_conflict(ident, ns, old_decl, decl); } } - /// Create a name definitinon from the given components, and put it into the local module. + /// Create a name definition from the given components, and put it into the local module. fn define_local( &mut self, parent: Module<'ra>, - ident: Ident, + orig_ident: Ident, ns: Namespace, res: Res, vis: Visibility, @@ -69,15 +72,16 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { expn_id: LocalExpnId, ) { let decl = self.arenas.new_def_decl(res, vis.to_def_id(), span, expn_id, Some(parent)); - let ident = Macros20NormalizedIdent::new(ident); - self.plant_decl_into_local_module(ident, ns, decl); + let ident = IdentKey::new(orig_ident); + self.plant_decl_into_local_module(ident, orig_ident.span, ns, decl); } - /// Create a name definitinon from the given components, and put it into the extern module. + /// Create a name definition from the given components, and put it into the extern module. fn define_extern( &self, parent: Module<'ra>, - ident: Macros20NormalizedIdent, + ident: IdentKey, + orig_ident_span: Span, ns: Namespace, child_index: usize, res: Res, @@ -102,7 +106,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { let key = BindingKey::new_disambiguated(ident, ns, || (child_index + 1).try_into().unwrap()); // 0 indicates no underscore if self - .resolution_or_default(parent, key) + .resolution_or_default(parent, key, orig_ident_span) .borrow_mut_unchecked() .non_glob_decl .replace(decl) @@ -279,8 +283,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { .unwrap_or_else(|| res.def_id()), ) }; - let ModChild { ident, res, vis, ref reexport_chain } = *child; - let ident = Macros20NormalizedIdent::new(ident); + let ModChild { ident: orig_ident, res, vis, ref reexport_chain } = *child; + let ident = IdentKey::new(orig_ident); let span = child_span(self, reexport_chain, res); let res = res.expect_non_local(); let expansion = parent_scope.expansion; @@ -293,7 +297,18 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { // Record primary definitions. let define_extern = |ns| { - self.define_extern(parent, ident, ns, child_index, res, vis, span, expansion, ambig) + self.define_extern( + parent, + ident, + orig_ident.span, + ns, + child_index, + res, + vis, + span, + expansion, + ambig, + ) }; match res { Res::Def( @@ -533,8 +548,8 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> { if target.name != kw::Underscore { self.r.per_ns(|this, ns| { if !type_ns_only || ns == TypeNS { - let key = BindingKey::new(Macros20NormalizedIdent::new(target), ns); - this.resolution_or_default(current_module, key) + let key = BindingKey::new(IdentKey::new(target), ns); + this.resolution_or_default(current_module, key, target.span) .borrow_mut(this) .single_imports .insert(import); @@ -974,7 +989,7 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> { &mut self, orig_name: Option, item: &Item, - ident: Ident, + orig_ident: Ident, local_def_id: LocalDefId, vis: Visibility, ) { @@ -983,7 +998,7 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> { let parent = parent_scope.module; let expansion = parent_scope.expansion; - let (used, module, decl) = if orig_name.is_none() && ident.name == kw::SelfLower { + let (used, module, decl) = if orig_name.is_none() && orig_ident.name == kw::SelfLower { self.r.dcx().emit_err(errors::ExternCrateSelfRequiresRenaming { span: sp }); return; } else if orig_name == Some(kw::SelfLower) { @@ -1008,7 +1023,7 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> { }) .unwrap_or((true, None, self.r.dummy_decl)); let import = self.r.arenas.alloc_import(ImportData { - kind: ImportKind::ExternCrate { source: orig_name, target: ident, id: item.id }, + kind: ImportKind::ExternCrate { source: orig_name, target: orig_ident, id: item.id }, root_id: item.id, parent_scope, imported_module: CmCell::new(module), @@ -1026,7 +1041,7 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> { } self.r.potentially_unused_imports.push(import); let import_decl = self.r.new_import_decl(decl, import); - let ident = Macros20NormalizedIdent::new(ident); + let ident = IdentKey::new(orig_ident); if ident.name != kw::Underscore && parent == self.r.graph_root { // FIXME: this error is technically unnecessary now when extern prelude is split into // two scopes, remove it with lang team approval. @@ -1045,20 +1060,20 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> { Entry::Occupied(mut occupied) => { let entry = occupied.get_mut(); if entry.item_decl.is_some() { - let msg = format!("extern crate `{ident}` already in extern prelude"); + let msg = format!("extern crate `{orig_ident}` already in extern prelude"); self.r.tcx.dcx().span_delayed_bug(item.span, msg); } else { - entry.item_decl = Some((import_decl, orig_name.is_some())); + entry.item_decl = Some((import_decl, orig_ident.span, orig_name.is_some())); } entry } Entry::Vacant(vacant) => vacant.insert(ExternPreludeEntry { - item_decl: Some((import_decl, true)), + item_decl: Some((import_decl, orig_ident.span, true)), flag_decl: None, }), }; } - self.r.plant_decl_into_local_module(ident, TypeNS, import_decl); + self.r.plant_decl_into_local_module(ident, orig_ident.span, TypeNS, import_decl); } /// Constructs the reduced graph for one foreign item. @@ -1159,7 +1174,7 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> { if let Some(span) = import_all { let import = macro_use_import(self, span, false); self.r.potentially_unused_imports.push(import); - module.for_each_child_mut(self, |this, ident, ns, binding| { + module.for_each_child_mut(self, |this, ident, _, ns, binding| { if ns == MacroNS { let import = if this.r.is_accessible_from(binding.vis(), this.parent_scope.module) { @@ -1270,7 +1285,7 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> { let expansion = parent_scope.expansion; let feed = self.r.feed(item.id); let def_id = feed.key(); - let (res, ident, span, macro_rules) = match &item.kind { + let (res, orig_ident, span, macro_rules) = match &item.kind { ItemKind::MacroDef(ident, def) => { (self.res(def_id), *ident, item.span, def.macro_rules) } @@ -1293,8 +1308,8 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> { self.r.local_macro_def_scopes.insert(def_id, parent_scope.module); if macro_rules { - let ident = Macros20NormalizedIdent::new(ident); - self.r.macro_names.insert(ident.0); + let ident = IdentKey::new(orig_ident); + self.r.macro_names.insert(ident); let is_macro_export = ast::attr::contains_name(&item.attrs, sym::macro_export); let vis = if is_macro_export { Visibility::Public @@ -1326,10 +1341,10 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> { }); self.r.import_use_map.insert(import, Used::Other); let import_decl = self.r.new_import_decl(decl, import); - self.r.plant_decl_into_local_module(ident, MacroNS, import_decl); + self.r.plant_decl_into_local_module(ident, orig_ident.span, MacroNS, import_decl); } else { - self.r.check_reserved_macro_name(ident.0, res); - self.insert_unused_macro(ident.0, def_id, item.id); + self.r.check_reserved_macro_name(ident.name, orig_ident.span, res); + self.insert_unused_macro(orig_ident, def_id, item.id); } self.r.feed_visibility(feed, vis); let scope = self.r.arenas.alloc_macro_rules_scope(MacroRulesScope::Def( @@ -1337,6 +1352,7 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> { parent_macro_rules_scope: parent_scope.macro_rules, decl, ident, + orig_ident_span: orig_ident.span, }), )); self.r.macro_rules_scopes.insert(def_id, scope); @@ -1352,9 +1368,9 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> { _ => self.resolve_visibility(&item.vis), }; if !vis.is_public() { - self.insert_unused_macro(ident, def_id, item.id); + self.insert_unused_macro(orig_ident, def_id, item.id); } - self.r.define_local(module, ident, MacroNS, res, vis, span, expansion); + self.r.define_local(module, orig_ident, MacroNS, res, vis, span, expansion); self.r.feed_visibility(feed, vis); self.parent_scope.macro_rules } @@ -1496,7 +1512,7 @@ impl<'a, 'ra, 'tcx> Visitor<'a> for BuildReducedGraphVisitor<'a, 'ra, 'tcx> { { // Don't add underscore names, they cannot be looked up anyway. let impl_def_id = self.r.tcx.local_parent(local_def_id); - let key = BindingKey::new(Macros20NormalizedIdent::new(ident), ns); + let key = BindingKey::new(IdentKey::new(ident), ns); self.r.impl_binding_keys.entry(impl_def_id).or_default().insert(key); } diff --git a/compiler/rustc_resolve/src/check_unused.rs b/compiler/rustc_resolve/src/check_unused.rs index 3724fcfce40f..45fdea82d47b 100644 --- a/compiler/rustc_resolve/src/check_unused.rs +++ b/compiler/rustc_resolve/src/check_unused.rs @@ -33,10 +33,10 @@ use rustc_session::lint::BuiltinLintDiag; use rustc_session::lint::builtin::{ MACRO_USE_EXTERN_CRATE, UNUSED_EXTERN_CRATES, UNUSED_IMPORTS, UNUSED_QUALIFICATIONS, }; -use rustc_span::{DUMMY_SP, Ident, Macros20NormalizedIdent, Span, kw}; +use rustc_span::{DUMMY_SP, Ident, Span, kw}; use crate::imports::{Import, ImportKind}; -use crate::{DeclKind, LateDecl, Resolver, module_to_string}; +use crate::{DeclKind, IdentKey, LateDecl, Resolver, module_to_string}; struct UnusedImport { use_tree: ast::UseTree, @@ -203,7 +203,7 @@ impl<'a, 'ra, 'tcx> UnusedImportCheckVisitor<'a, 'ra, 'tcx> { if self .r .extern_prelude - .get(&Macros20NormalizedIdent::new(extern_crate.ident)) + .get(&IdentKey::new(extern_crate.ident)) .is_none_or(|entry| entry.introduced_by_item()) { continue; diff --git a/compiler/rustc_resolve/src/diagnostics.rs b/compiler/rustc_resolve/src/diagnostics.rs index a5b3def4b5f8..5c401c3bf828 100644 --- a/compiler/rustc_resolve/src/diagnostics.rs +++ b/compiler/rustc_resolve/src/diagnostics.rs @@ -32,9 +32,7 @@ use rustc_span::edit_distance::find_best_match_for_name; use rustc_span::edition::Edition; use rustc_span::hygiene::MacroKind; use rustc_span::source_map::{SourceMap, Spanned}; -use rustc_span::{ - BytePos, DUMMY_SP, Ident, Macros20NormalizedIdent, Span, Symbol, SyntaxContext, kw, sym, -}; +use rustc_span::{BytePos, DUMMY_SP, Ident, Span, Symbol, SyntaxContext, kw, sym}; use thin_vec::{ThinVec, thin_vec}; use tracing::{debug, instrument}; @@ -47,10 +45,10 @@ use crate::imports::{Import, ImportKind}; use crate::late::{DiagMetadata, PatternSource, Rib}; use crate::{ AmbiguityError, AmbiguityKind, AmbiguityWarning, BindingError, BindingKey, Decl, DeclKind, - Finalize, ForwardGenericParamBanReason, HasGenericParams, LateDecl, MacroRulesScope, Module, - ModuleKind, ModuleOrUniformRoot, ParentScope, PathResult, PrivacyError, ResolutionError, - Resolver, Scope, ScopeSet, Segment, UseError, Used, VisResolutionError, errors as errs, - path_names_to_string, + Finalize, ForwardGenericParamBanReason, HasGenericParams, IdentKey, LateDecl, MacroRulesScope, + Module, ModuleKind, ModuleOrUniformRoot, ParentScope, PathResult, PrivacyError, + ResolutionError, Resolver, Scope, ScopeSet, Segment, UseError, Used, VisResolutionError, + errors as errs, path_names_to_string, }; type Res = def::Res; @@ -81,24 +79,14 @@ pub(crate) struct TypoSuggestion { } impl TypoSuggestion { - pub(crate) fn typo_from_ident(ident: Ident, res: Res) -> TypoSuggestion { - Self { - candidate: ident.name, - span: Some(ident.span), - res, - target: SuggestionTarget::SimilarlyNamed, - } + pub(crate) fn new(candidate: Symbol, span: Span, res: Res) -> TypoSuggestion { + Self { candidate, span: Some(span), res, target: SuggestionTarget::SimilarlyNamed } } pub(crate) fn typo_from_name(candidate: Symbol, res: Res) -> TypoSuggestion { Self { candidate, span: None, res, target: SuggestionTarget::SimilarlyNamed } } - pub(crate) fn single_item_from_ident(ident: Ident, res: Res) -> TypoSuggestion { - Self { - candidate: ident.name, - span: Some(ident.span), - res, - target: SuggestionTarget::SingleItem, - } + pub(crate) fn single_item(candidate: Symbol, span: Span, res: Res) -> TypoSuggestion { + Self { candidate, span: Some(span), res, target: SuggestionTarget::SingleItem } } } @@ -212,7 +200,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { pub(crate) fn report_conflict( &mut self, - ident: Ident, + ident: IdentKey, ns: Namespace, old_binding: Decl<'ra>, new_binding: Decl<'ra>, @@ -324,10 +312,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { // Check if the target of the use for both bindings is the same. let duplicate = new_binding.res().opt_def_id() == old_binding.res().opt_def_id(); let has_dummy_span = new_binding.span.is_dummy() || old_binding.span.is_dummy(); - let from_item = self - .extern_prelude - .get(&Macros20NormalizedIdent::new(ident)) - .is_none_or(|entry| entry.introduced_by_item()); + let from_item = + self.extern_prelude.get(&ident).is_none_or(|entry| entry.introduced_by_item()); // Only suggest removing an import if both bindings are to the same def, if both spans // aren't dummy spans. Further, if both bindings are imports, then the ident must have // been introduced by an item. @@ -531,10 +517,10 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { filter_fn: &impl Fn(Res) -> bool, ctxt: Option, ) { - module.for_each_child(self, |_this, ident, _ns, binding| { + module.for_each_child(self, |_this, ident, orig_ident_span, _ns, binding| { let res = binding.res(); - if filter_fn(res) && ctxt.is_none_or(|ctxt| ctxt == ident.span.ctxt()) { - names.push(TypoSuggestion::typo_from_ident(ident.0, res)); + if filter_fn(res) && ctxt.is_none_or(|ctxt| ctxt == *ident.ctxt) { + names.push(TypoSuggestion::new(ident.name, orig_ident_span, res)); } }); } @@ -1187,11 +1173,11 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { let res = Res::NonMacroAttr(NonMacroAttrKind::DeriveHelper); if filter_fn(res) { suggestions.extend( - this.helper_attrs - .get(&expn_id) - .into_iter() - .flatten() - .map(|(ident, _)| TypoSuggestion::typo_from_ident(ident.0, res)), + this.helper_attrs.get(&expn_id).into_iter().flatten().map( + |&(ident, orig_ident_span, _)| { + TypoSuggestion::new(ident.name, orig_ident_span, res) + }, + ), ); } } @@ -1202,8 +1188,11 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { if let MacroRulesScope::Def(macro_rules_def) = macro_rules_scope.get() { let res = macro_rules_def.decl.res(); if filter_fn(res) { - suggestions - .push(TypoSuggestion::typo_from_ident(macro_rules_def.ident.0, res)) + suggestions.push(TypoSuggestion::new( + macro_rules_def.ident.name, + macro_rules_def.orig_ident_span, + res, + )) } } } @@ -1233,9 +1222,9 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { } Scope::ExternPreludeItems => { // Add idents from both item and flag scopes. - suggestions.extend(this.extern_prelude.keys().filter_map(|ident| { + suggestions.extend(this.extern_prelude.iter().filter_map(|(ident, entry)| { let res = Res::Def(DefKind::Mod, CRATE_DEF_ID.to_def_id()); - filter_fn(res).then_some(TypoSuggestion::typo_from_ident(ident.0, res)) + filter_fn(res).then_some(TypoSuggestion::new(ident.name, entry.span(), res)) })); } Scope::ExternPreludeFlags => {} @@ -1244,7 +1233,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { suggestions.extend( this.registered_tools .iter() - .map(|ident| TypoSuggestion::typo_from_ident(*ident, res)), + .map(|ident| TypoSuggestion::new(ident.name, ident.span, res)), ); } Scope::StdLibPrelude => { @@ -1329,7 +1318,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { } { let in_module_is_extern = !in_module.def_id().is_local(); - in_module.for_each_child(self, |this, ident, ns, name_binding| { + in_module.for_each_child(self, |this, ident, orig_ident_span, ns, name_binding| { // Avoid non-importable candidates. if name_binding.is_assoc_item() && !this.tcx.features().import_trait_associated_functions() @@ -1382,7 +1371,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { if ident.name == lookup_ident.name && ns == namespace && in_module != parent_scope.module - && !ident.span.normalize_to_macros_2_0().from_expansion() + && ident.ctxt.is_root() && filter_fn(res) { // create the path @@ -1395,7 +1384,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { }; segms.append(&mut path_segments.clone()); - segms.push(ast::PathSegment::from_ident(ident.0)); + segms.push(ast::PathSegment::from_ident(ident.orig(orig_ident_span))); let path = Path { span: name_binding.span, segments: segms, tokens: None }; if child_accessible @@ -1468,7 +1457,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { if let Some(def_id) = name_binding.res().module_like_def_id() { // form the path let mut path_segments = path_segments.clone(); - path_segments.push(ast::PathSegment::from_ident(ident.0)); + path_segments.push(ast::PathSegment::from_ident(ident.orig(orig_ident_span))); let alias_import = if let DeclKind::Import { import, .. } = name_binding.kind && let ImportKind::ExternCrate { source: Some(_), .. } = import.kind @@ -1557,8 +1546,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { ); if lookup_ident.span.at_least_rust_2018() { - for &ident in self.extern_prelude.keys() { - if ident.span.from_expansion() { + for (ident, entry) in &self.extern_prelude { + if entry.span().from_expansion() { // Idents are adjusted to the root context before being // resolved in the extern prelude, so reporting this to the // user is no help. This skips the injected @@ -1582,7 +1571,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { self.resolutions(parent_scope.module).borrow().iter().any( |(key, name_resolution)| { if key.ns == TypeNS - && key.ident == ident + && key.ident == *ident && let Some(decl) = name_resolution.borrow().best_decl() { match decl.res() { @@ -1601,7 +1590,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { if needs_disambiguation { crate_path.push(ast::PathSegment::path_root(rustc_span::DUMMY_SP)); } - crate_path.push(ast::PathSegment::from_ident(ident.0)); + crate_path.push(ast::PathSegment::from_ident(ident.orig(entry.span()))); suggestions.extend(self.lookup_import_candidates_from_module( lookup_ident, @@ -1777,7 +1766,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { return; } - if self.macro_names.contains(&ident.normalize_to_macros_2_0()) { + if self.macro_names.contains(&IdentKey::new(ident)) { err.subdiagnostic(AddedMacroUse); return; } @@ -2007,8 +1996,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { matches!(scope2, Scope::ExternPreludeFlags) && self .extern_prelude - .get(&Macros20NormalizedIdent::new(ident)) - .is_some_and(|entry| entry.item_decl.map(|(b, _)| b) == Some(b1)) + .get(&IdentKey::new(ident)) + .is_some_and(|entry| entry.item_decl.map(|(b, ..)| b) == Some(b1)) }; let (b1, b2, scope1, scope2, swapped) = if b2.span.is_dummy() && !b1.span.is_dummy() { // We have to print the span-less alternative first, otherwise formatting looks bad. @@ -2914,7 +2903,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { return None; } - let binding_key = BindingKey::new(Macros20NormalizedIdent::new(ident), MacroNS); + let binding_key = BindingKey::new(IdentKey::new(ident), MacroNS); let binding = self.resolution(crate_module, binding_key)?.binding()?; let Res::Def(DefKind::Macro(kinds), _) = binding.res() else { return None; diff --git a/compiler/rustc_resolve/src/effective_visibilities.rs b/compiler/rustc_resolve/src/effective_visibilities.rs index 295635a60547..55518276a4f0 100644 --- a/compiler/rustc_resolve/src/effective_visibilities.rs +++ b/compiler/rustc_resolve/src/effective_visibilities.rs @@ -96,13 +96,10 @@ impl<'a, 'ra, 'tcx> EffectiveVisibilitiesVisitor<'a, 'ra, 'tcx> { // is the maximum value among visibilities of declarations corresponding to that def id. for (decl, eff_vis) in visitor.import_effective_visibilities.iter() { let DeclKind::Import { import, .. } = decl.kind else { unreachable!() }; - if !decl.is_ambiguity_recursive() { - if let Some(node_id) = import.id() { - r.effective_visibilities.update_eff_vis(r.local_def_id(node_id), eff_vis, r.tcx) - } - } else if decl.ambiguity.get().is_some() - && eff_vis.is_public_at_level(Level::Reexported) - { + if let Some(node_id) = import.id() { + r.effective_visibilities.update_eff_vis(r.local_def_id(node_id), eff_vis, r.tcx) + } + if decl.ambiguity.get().is_some() && eff_vis.is_public_at_level(Level::Reexported) { exported_ambiguities.insert(*decl); } } @@ -123,31 +120,13 @@ impl<'a, 'ra, 'tcx> EffectiveVisibilitiesVisitor<'a, 'ra, 'tcx> { // Set the given effective visibility level to `Level::Direct` and // sets the rest of the `use` chain to `Level::Reexported` until // we hit the actual exported item. - // - // If the binding is ambiguous, put the root ambiguity binding and all reexports - // leading to it into the table. They are used by the `ambiguous_glob_reexports` - // lint. For all bindings added to the table this way `is_ambiguity` returns true. - let is_ambiguity = - |decl: Decl<'ra>, warn: bool| decl.ambiguity.get().is_some() && !warn; let mut parent_id = ParentId::Def(module_id); - let mut warn_ambiguity = decl.warn_ambiguity.get(); while let DeclKind::Import { source_decl, .. } = decl.kind { self.update_import(decl, parent_id); - - if is_ambiguity(decl, warn_ambiguity) { - // Stop at the root ambiguity, further bindings in the chain should not - // be reexported because the root ambiguity blocks any access to them. - // (Those further bindings are most likely not ambiguities themselves.) - break; - } - parent_id = ParentId::Import(decl); decl = source_decl; - warn_ambiguity |= source_decl.warn_ambiguity.get(); } - if !is_ambiguity(decl, warn_ambiguity) - && let Some(def_id) = decl.res().opt_def_id().and_then(|id| id.as_local()) - { + if let Some(def_id) = decl.res().opt_def_id().and_then(|id| id.as_local()) { self.update_def(def_id, decl.vis().expect_local(), parent_id); } } diff --git a/compiler/rustc_resolve/src/errors.rs b/compiler/rustc_resolve/src/errors.rs index d614219e8eab..205f2c6aa539 100644 --- a/compiler/rustc_resolve/src/errors.rs +++ b/compiler/rustc_resolve/src/errors.rs @@ -601,7 +601,7 @@ pub(crate) struct ProcMacroDeriveResolutionFallback { #[label] pub span: Span, pub ns_descr: &'static str, - pub ident: Ident, + pub ident: Symbol, } #[derive(LintDiagnostic)] @@ -1151,7 +1151,7 @@ pub(crate) struct CannotUseThroughAnImport { pub(crate) struct NameReservedInAttributeNamespace { #[primary_span] pub(crate) span: Span, - pub(crate) ident: Ident, + pub(crate) ident: Symbol, } #[derive(Diagnostic)] diff --git a/compiler/rustc_resolve/src/ident.rs b/compiler/rustc_resolve/src/ident.rs index 78c6cf39b630..26dca5e6e508 100644 --- a/compiler/rustc_resolve/src/ident.rs +++ b/compiler/rustc_resolve/src/ident.rs @@ -10,11 +10,12 @@ use rustc_session::lint::builtin::PROC_MACRO_DERIVE_RESOLUTION_FALLBACK; use rustc_session::parse::feature_err; use rustc_span::edition::Edition; use rustc_span::hygiene::{ExpnId, ExpnKind, LocalExpnId, MacroKind, SyntaxContext}; -use rustc_span::{Ident, Macros20NormalizedIdent, Span, kw, sym}; +use rustc_span::{Ident, Span, kw, sym}; use smallvec::SmallVec; use tracing::{debug, instrument}; use crate::errors::{ParamKindInEnumDiscriminant, ParamKindInNonTrivialAnonConst}; +use crate::hygiene::Macros20NormalizedSyntaxContext; use crate::imports::{Import, NameResolution}; use crate::late::{ ConstantHasGenerics, DiagMetadata, NoConstantGenericsReason, PathSource, Rib, RibKind, @@ -22,7 +23,7 @@ use crate::late::{ use crate::macros::{MacroRulesScope, sub_namespace_match}; use crate::{ AmbiguityError, AmbiguityKind, AmbiguityWarning, BindingKey, CmResolver, Decl, DeclKind, - Determinacy, Finalize, ImportKind, LateDecl, Module, ModuleKind, ModuleOrUniformRoot, + Determinacy, Finalize, IdentKey, ImportKind, LateDecl, Module, ModuleKind, ModuleOrUniformRoot, ParentScope, PathResult, PrivacyError, Res, ResolutionError, Resolver, Scope, ScopeSet, Segment, Stage, Used, errors, }; @@ -61,7 +62,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { CmResolver<'_, 'ra, 'tcx>, Scope<'ra>, UsePrelude, - Span, + Macros20NormalizedSyntaxContext, ) -> ControlFlow, ) -> Option { // General principles: @@ -127,7 +128,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { TypeNS | ValueNS => Scope::ModuleNonGlobs(module, None), MacroNS => Scope::DeriveHelpers(parent_scope.expansion), }; - let mut ctxt = orig_ctxt.normalize_to_macros_2_0(); + let mut ctxt = Macros20NormalizedSyntaxContext::new(orig_ctxt.ctxt()); let mut use_prelude = !module.no_implicit_prelude; loop { @@ -198,7 +199,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { Scope::ModuleGlobs(..) if module_only => break, Scope::ModuleGlobs(..) if module_and_extern_prelude => match ns { TypeNS => { - ctxt.adjust(ExpnId::root()); + ctxt.update_unchecked(|ctxt| ctxt.adjust(ExpnId::root())); Scope::ExternPreludeItems } ValueNS | MacroNS => break, @@ -210,7 +211,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { Scope::ModuleNonGlobs(parent_module, lint_id.or(prev_lint_id)) } None => { - ctxt.adjust(ExpnId::root()); + ctxt.update_unchecked(|ctxt| ctxt.adjust(ExpnId::root())); match ns { TypeNS => Scope::ExternPreludeItems, ValueNS => Scope::StdLibPrelude, @@ -240,12 +241,12 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { fn hygienic_lexical_parent( &self, module: Module<'ra>, - span: &mut Span, + ctxt: &mut Macros20NormalizedSyntaxContext, derive_fallback_lint_id: Option, ) -> Option<(Module<'ra>, Option)> { - let ctxt = span.ctxt(); - if !module.expansion.outer_expn_is_descendant_of(ctxt) { - return Some((self.expn_def_scope(span.remove_mark()), None)); + if !module.expansion.outer_expn_is_descendant_of(**ctxt) { + let expn_id = ctxt.update_unchecked(|ctxt| ctxt.remove_mark()); + return Some((self.expn_def_scope(expn_id), None)); } if let ModuleKind::Block = module.kind { @@ -275,7 +276,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { let ext = &self.get_macro_by_def_id(def_id).ext; if ext.builtin_name.is_none() && ext.macro_kinds() == MacroKinds::DERIVE - && parent.expansion.outer_expn_is_descendant_of(ctxt) + && parent.expansion.outer_expn_is_descendant_of(**ctxt) { return Some((parent, derive_fallback_lint_id)); } @@ -439,11 +440,10 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { orig_ident.span, derive_fallback_lint_id, |mut this, scope, use_prelude, ctxt| { - let ident = Ident::new(orig_ident.name, ctxt); - // The passed `ctxt` is already normalized, so avoid expensive double normalization. - let ident = Macros20NormalizedIdent(ident); + let ident = IdentKey { name: orig_ident.name, ctxt }; let res = match this.reborrow().resolve_ident_in_scope( ident, + orig_ident.span, ns, scope, use_prelude, @@ -515,7 +515,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { fn resolve_ident_in_scope<'r>( mut self: CmResolver<'r, 'ra, 'tcx>, - ident: Macros20NormalizedIdent, + ident: IdentKey, + orig_ident_span: Span, ns: Namespace, scope: Scope<'ra>, use_prelude: UsePrelude, @@ -531,7 +532,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { if let Some(decl) = self .helper_attrs .get(&expn_id) - .and_then(|attrs| attrs.iter().rfind(|(i, _)| ident == *i).map(|(_, d)| *d)) + .and_then(|attrs| attrs.iter().rfind(|(i, ..)| ident == *i).map(|(.., d)| *d)) { Ok(decl) } else { @@ -587,6 +588,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { let decl = self.reborrow().resolve_ident_in_module_non_globs_unadjusted( module, ident, + orig_ident_span, ns, adjusted_parent_scope, if matches!(scope_set, ScopeSet::Module(..)) { @@ -604,11 +606,11 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { self.get_mut().lint_buffer.buffer_lint( PROC_MACRO_DERIVE_RESOLUTION_FALLBACK, lint_id, - ident.span, + orig_ident_span, errors::ProcMacroDeriveResolutionFallback { - span: ident.span, + span: orig_ident_span, ns_descr: ns.descr(), - ident: ident.0, + ident: ident.name, }, ); } @@ -637,6 +639,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { let binding = self.reborrow().resolve_ident_in_module_globs_unadjusted( module, ident, + orig_ident_span, ns, adjusted_parent_scope, if matches!(scope_set, ScopeSet::Module(..)) { @@ -654,11 +657,11 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { self.get_mut().lint_buffer.buffer_lint( PROC_MACRO_DERIVE_RESOLUTION_FALLBACK, lint_id, - ident.span, + orig_ident_span, errors::ProcMacroDeriveResolutionFallback { - span: ident.span, + span: orig_ident_span, ns_descr: ns.descr(), - ident: ident.0, + ident: ident.name, }, ); } @@ -683,7 +686,11 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { None => Err(Determinacy::Determined), }, Scope::ExternPreludeItems => { - match self.reborrow().extern_prelude_get_item(ident, finalize.is_some()) { + match self.reborrow().extern_prelude_get_item( + ident, + orig_ident_span, + finalize.is_some(), + ) { Some(decl) => Ok(decl), None => Err(Determinacy::determined( self.graph_root.unexpanded_invocations.borrow().is_empty(), @@ -691,7 +698,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { } } Scope::ExternPreludeFlags => { - match self.extern_prelude_get_flag(ident, finalize.is_some()) { + match self.extern_prelude_get_flag(ident, orig_ident_span, finalize.is_some()) { Some(decl) => Ok(decl), None => Err(Determinacy::Determined), } @@ -704,7 +711,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { let mut result = Err(Determinacy::Determined); if let Some(prelude) = self.prelude && let Ok(decl) = self.reborrow().resolve_ident_in_scope_set( - ident.0, + ident.orig(orig_ident_span.with_ctxt(*ident.ctxt)), ScopeSet::Module(ns, prelude), parent_scope, None, @@ -723,26 +730,26 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { Some(decl) => { if matches!(ident.name, sym::f16) && !self.tcx.features().f16() - && !ident.span.allows_unstable(sym::f16) + && !orig_ident_span.allows_unstable(sym::f16) && finalize.is_some() { feature_err( self.tcx.sess, sym::f16, - ident.span, + orig_ident_span, "the type `f16` is unstable", ) .emit(); } if matches!(ident.name, sym::f128) && !self.tcx.features().f128() - && !ident.span.allows_unstable(sym::f128) + && !orig_ident_span.allows_unstable(sym::f128) && finalize.is_some() { feature_err( self.tcx.sess, sym::f128, - ident.span, + orig_ident_span, "the type `f128` is unstable", ) .emit(); @@ -1001,7 +1008,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { fn resolve_ident_in_module_non_globs_unadjusted<'r>( mut self: CmResolver<'r, 'ra, 'tcx>, module: Module<'ra>, - ident: Macros20NormalizedIdent, + ident: IdentKey, + orig_ident_span: Span, ns: Namespace, parent_scope: &ParentScope<'ra>, shadowing: Shadowing, @@ -1016,7 +1024,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { // doesn't need to be mutable. It will fail when there is a cycle of imports, and without // the exclusive access infinite recursion will crash the compiler with stack overflow. let resolution = &*self - .resolution_or_default(module, key) + .resolution_or_default(module, key, orig_ident_span) .try_borrow_mut_unchecked() .map_err(|_| ControlFlow::Continue(Determined))?; @@ -1024,7 +1032,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { if let Some(finalize) = finalize { return self.get_mut().finalize_module_binding( - ident.0, + ident, + orig_ident_span, binding, parent_scope, module, @@ -1064,7 +1073,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { fn resolve_ident_in_module_globs_unadjusted<'r>( mut self: CmResolver<'r, 'ra, 'tcx>, module: Module<'ra>, - ident: Macros20NormalizedIdent, + ident: IdentKey, + orig_ident_span: Span, ns: Namespace, parent_scope: &ParentScope<'ra>, shadowing: Shadowing, @@ -1077,7 +1087,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { // doesn't need to be mutable. It will fail when there is a cycle of imports, and without // the exclusive access infinite recursion will crash the compiler with stack overflow. let resolution = &*self - .resolution_or_default(module, key) + .resolution_or_default(module, key, orig_ident_span) .try_borrow_mut_unchecked() .map_err(|_| ControlFlow::Continue(Determined))?; @@ -1085,7 +1095,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { if let Some(finalize) = finalize { return self.get_mut().finalize_module_binding( - ident.0, + ident, + orig_ident_span, binding, parent_scope, module, @@ -1154,8 +1165,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { None => return Err(ControlFlow::Continue(Undetermined)), }; let tmp_parent_scope; - let (mut adjusted_parent_scope, mut ident) = (parent_scope, ident); - match ident.0.span.glob_adjust(module.expansion, glob_import.span) { + let (mut adjusted_parent_scope, mut ctxt) = (parent_scope, *ident.ctxt); + match ctxt.glob_adjust(module.expansion, glob_import.span) { Some(Some(def)) => { tmp_parent_scope = ParentScope { module: self.expn_def_scope(def), ..*parent_scope }; @@ -1165,7 +1176,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { None => continue, }; let result = self.reborrow().resolve_ident_in_scope_set( - ident.0, + ident.orig(orig_ident_span.with_ctxt(ctxt)), ScopeSet::Module(ns, module), adjusted_parent_scope, None, @@ -1191,7 +1202,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { fn finalize_module_binding( &mut self, - ident: Ident, + ident: IdentKey, + orig_ident_span: Span, binding: Option>, parent_scope: &ParentScope<'ra>, module: Module<'ra>, @@ -1204,6 +1216,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { return Err(ControlFlow::Continue(Determined)); }; + let ident = ident.orig(orig_ident_span); if !self.is_accessible_from(binding.vis(), parent_scope.module) { if report_private { self.privacy_errors.push(PrivacyError { diff --git a/compiler/rustc_resolve/src/imports.rs b/compiler/rustc_resolve/src/imports.rs index f5933afd0134..7ff24bc612df 100644 --- a/compiler/rustc_resolve/src/imports.rs +++ b/compiler/rustc_resolve/src/imports.rs @@ -20,7 +20,7 @@ use rustc_session::lint::builtin::{ use rustc_session::parse::feature_err; use rustc_span::edit_distance::find_best_match_for_name; use rustc_span::hygiene::LocalExpnId; -use rustc_span::{Ident, Macros20NormalizedIdent, Span, Symbol, kw, sym}; +use rustc_span::{Ident, Span, Symbol, kw, sym}; use tracing::debug; use crate::Namespace::{self, *}; @@ -33,8 +33,8 @@ use crate::errors::{ use crate::ref_mut::CmCell; use crate::{ AmbiguityError, BindingKey, CmResolver, Decl, DeclData, DeclKind, Determinacy, Finalize, - ImportSuggestion, Module, ModuleOrUniformRoot, ParentScope, PathResult, PerNS, ResolutionError, - Resolver, ScopeSet, Segment, Used, module_to_string, names_to_string, + IdentKey, ImportSuggestion, Module, ModuleOrUniformRoot, ParentScope, PathResult, PerNS, + ResolutionError, Resolver, ScopeSet, Segment, Used, module_to_string, names_to_string, }; type Res = def::Res; @@ -239,18 +239,23 @@ impl<'ra> ImportData<'ra> { } /// Records information about the resolution of a name in a namespace of a module. -#[derive(Clone, Default, Debug)] +#[derive(Clone, Debug)] pub(crate) struct NameResolution<'ra> { /// Single imports that may define the name in the namespace. /// Imports are arena-allocated, so it's ok to use pointers as keys. pub single_imports: FxIndexSet>, /// The non-glob declaration for this name, if it is known to exist. - pub non_glob_decl: Option>, + pub non_glob_decl: Option> = None, /// The glob declaration for this name, if it is known to exist. - pub glob_decl: Option>, + pub glob_decl: Option> = None, + pub orig_ident_span: Span, } impl<'ra> NameResolution<'ra> { + pub(crate) fn new(orig_ident_span: Span) -> Self { + NameResolution { single_imports: FxIndexSet::default(), orig_ident_span, .. } + } + /// Returns the binding for the name if it is known or None if it not known. pub(crate) fn binding(&self) -> Option> { self.best_decl().and_then(|binding| { @@ -417,14 +422,15 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { /// and return existing declaration if there is a collision. pub(crate) fn try_plant_decl_into_local_module( &mut self, - ident: Macros20NormalizedIdent, + ident: IdentKey, + orig_ident_span: Span, ns: Namespace, decl: Decl<'ra>, warn_ambiguity: bool, ) -> Result<(), Decl<'ra>> { let module = decl.parent_module.unwrap(); let res = decl.res(); - self.check_reserved_macro_name(ident.0, res); + self.check_reserved_macro_name(ident.name, orig_ident_span, res); // Even if underscore names cannot be looked up, we still need to add them to modules, // because they can be fetched by glob imports from those modules, and bring traits // into scope both directly and through glob imports. @@ -432,46 +438,52 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { module.underscore_disambiguator.update_unchecked(|d| d + 1); module.underscore_disambiguator.get() }); - self.update_local_resolution(module, key, warn_ambiguity, |this, resolution| { - if let Some(old_decl) = resolution.best_decl() { - assert_ne!(decl, old_decl); - assert!(!decl.warn_ambiguity.get()); - if res == Res::Err && old_decl.res() != Res::Err { - // Do not override real declarations with `Res::Err`s from error recovery. - return Ok(()); - } - match (old_decl.is_glob_import(), decl.is_glob_import()) { - (true, true) => { - resolution.glob_decl = - Some(this.select_glob_decl(old_decl, decl, warn_ambiguity)); + self.update_local_resolution( + module, + key, + orig_ident_span, + warn_ambiguity, + |this, resolution| { + if let Some(old_decl) = resolution.best_decl() { + assert_ne!(decl, old_decl); + assert!(!decl.warn_ambiguity.get()); + if res == Res::Err && old_decl.res() != Res::Err { + // Do not override real declarations with `Res::Err`s from error recovery. + return Ok(()); } - (old_glob @ true, false) | (old_glob @ false, true) => { - let (glob_decl, non_glob_decl) = - if old_glob { (old_decl, decl) } else { (decl, old_decl) }; - resolution.non_glob_decl = Some(non_glob_decl); - if let Some(old_glob_decl) = resolution.glob_decl - && old_glob_decl != glob_decl - { + match (old_decl.is_glob_import(), decl.is_glob_import()) { + (true, true) => { resolution.glob_decl = - Some(this.select_glob_decl(old_glob_decl, glob_decl, false)); - } else { - resolution.glob_decl = Some(glob_decl); + Some(this.select_glob_decl(old_decl, decl, warn_ambiguity)); + } + (old_glob @ true, false) | (old_glob @ false, true) => { + let (glob_decl, non_glob_decl) = + if old_glob { (old_decl, decl) } else { (decl, old_decl) }; + resolution.non_glob_decl = Some(non_glob_decl); + if let Some(old_glob_decl) = resolution.glob_decl + && old_glob_decl != glob_decl + { + resolution.glob_decl = + Some(this.select_glob_decl(old_glob_decl, glob_decl, false)); + } else { + resolution.glob_decl = Some(glob_decl); + } + } + (false, false) => { + return Err(old_decl); } } - (false, false) => { - return Err(old_decl); + } else { + if decl.is_glob_import() { + resolution.glob_decl = Some(decl); + } else { + resolution.non_glob_decl = Some(decl); } } - } else { - if decl.is_glob_import() { - resolution.glob_decl = Some(decl); - } else { - resolution.non_glob_decl = Some(decl); - } - } - Ok(()) - }) + Ok(()) + }, + ) } // Use `f` to mutate the resolution of the name in the module. @@ -480,6 +492,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { &mut self, module: Module<'ra>, key: BindingKey, + orig_ident_span: Span, warn_ambiguity: bool, f: F, ) -> T @@ -489,7 +502,9 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { // Ensure that `resolution` isn't borrowed when defining in the module's glob importers, // during which the resolution might end up getting re-defined via a glob cycle. let (binding, t, warn_ambiguity) = { - let resolution = &mut *self.resolution_or_default(module, key).borrow_mut_unchecked(); + let resolution = &mut *self + .resolution_or_default(module, key, orig_ident_span) + .borrow_mut_unchecked(); let old_decl = resolution.binding(); let t = f(self, resolution); @@ -510,7 +525,10 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { // Define or update `binding` in `module`s glob importers. for import in glob_importers.iter() { let mut ident = key.ident; - let scope = match ident.0.span.reverse_glob_adjust(module.expansion, import.span) { + let scope = match ident + .ctxt + .update_unchecked(|ctxt| ctxt.reverse_glob_adjust(module.expansion, import.span)) + { Some(Some(def)) => self.expn_def_scope(def), Some(None) => import.parent_scope.module, None => continue, @@ -519,6 +537,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { let import_decl = self.new_import_decl(binding, *import); let _ = self.try_plant_decl_into_local_module( ident, + orig_ident_span, key.ns, import_decl, warn_ambiguity, @@ -540,14 +559,26 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { let dummy_decl = self.new_import_decl(dummy_decl, import); self.per_ns(|this, ns| { let module = import.parent_scope.module; - let ident = Macros20NormalizedIdent::new(target); - let _ = this.try_plant_decl_into_local_module(ident, ns, dummy_decl, false); + let ident = IdentKey::new(target); + let _ = this.try_plant_decl_into_local_module( + ident, + target.span, + ns, + dummy_decl, + false, + ); // Don't remove underscores from `single_imports`, they were never added. if target.name != kw::Underscore { let key = BindingKey::new(ident, ns); - this.update_local_resolution(module, key, false, |_, resolution| { - resolution.single_imports.swap_remove(&import); - }) + this.update_local_resolution( + module, + key, + target.span, + false, + |_, resolution| { + resolution.single_imports.swap_remove(&import); + }, + ) } }); self.record_use(target, dummy_decl, Used::Other); @@ -687,7 +718,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { import.root_id, import.root_span, BuiltinLintDiag::AmbiguousGlobReexports { - name: key.ident.to_string(), + name: key.ident.name.to_string(), namespace: key.ns.descr().to_string(), first_reexport_span: import.root_span, duplicate_reexport_span: amb_binding.span, @@ -922,7 +953,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { // We need the `target`, `source` can be extracted. let import_decl = this.new_import_decl(binding, import); this.get_mut_unchecked().plant_decl_into_local_module( - Macros20NormalizedIdent::new(target), + IdentKey::new(target), + target.span, ns, import_decl, ); @@ -931,10 +963,11 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { Err(Determinacy::Determined) => { // Don't remove underscores from `single_imports`, they were never added. if target.name != kw::Underscore { - let key = BindingKey::new(Macros20NormalizedIdent::new(target), ns); + let key = BindingKey::new(IdentKey::new(target), ns); this.get_mut_unchecked().update_local_resolution( parent, key, + target.span, false, |_, resolution| { resolution.single_imports.swap_remove(&import); @@ -1531,15 +1564,19 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { .borrow() .iter() .filter_map(|(key, resolution)| { - resolution.borrow().binding().map(|binding| (*key, binding)) + let resolution = resolution.borrow(); + resolution.binding().map(|binding| (*key, binding, resolution.orig_ident_span)) }) .collect::>(); - for (mut key, binding) in bindings { - let scope = match key.ident.0.span.reverse_glob_adjust(module.expansion, import.span) { - Some(Some(def)) => self.expn_def_scope(def), - Some(None) => import.parent_scope.module, - None => continue, - }; + for (mut key, binding, orig_ident_span) in bindings { + let scope = + match key.ident.ctxt.update_unchecked(|ctxt| { + ctxt.reverse_glob_adjust(module.expansion, import.span) + }) { + Some(Some(def)) => self.expn_def_scope(def), + Some(None) => import.parent_scope.module, + None => continue, + }; if self.is_accessible_from(binding.vis(), scope) { let import_decl = self.new_import_decl(binding, import); let warn_ambiguity = self @@ -1548,6 +1585,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { .is_some_and(|binding| binding.warn_ambiguity_recursive()); let _ = self.try_plant_decl_into_local_module( key.ident, + orig_ident_span, key.ns, import_decl, warn_ambiguity, @@ -1575,19 +1613,16 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { let mut children = Vec::new(); let mut ambig_children = Vec::new(); - module.for_each_child(self, |this, ident, _, binding| { + module.for_each_child(self, |this, ident, orig_ident_span, _, binding| { let res = binding.res().expect_non_local(); if res != def::Res::Err { - let child = |reexport_chain| ModChild { - ident: ident.0, - res, - vis: binding.vis(), - reexport_chain, - }; + let ident = ident.orig(orig_ident_span); + let child = + |reexport_chain| ModChild { ident, res, vis: binding.vis(), reexport_chain }; if let Some((ambig_binding1, ambig_binding2)) = binding.descent_to_ambiguity() { let main = child(ambig_binding1.reexport_chain(this)); let second = ModChild { - ident: ident.0, + ident, res: ambig_binding2.res().expect_non_local(), vis: ambig_binding2.vis(), reexport_chain: ambig_binding2.reexport_chain(this), diff --git a/compiler/rustc_resolve/src/late.rs b/compiler/rustc_resolve/src/late.rs index 7a7261cf7b95..4faf7715de6e 100644 --- a/compiler/rustc_resolve/src/late.rs +++ b/compiler/rustc_resolve/src/late.rs @@ -37,15 +37,15 @@ use rustc_session::config::{CrateType, ResolveDocLinks}; use rustc_session::lint; use rustc_session::parse::feature_err; use rustc_span::source_map::{Spanned, respan}; -use rustc_span::{BytePos, DUMMY_SP, Ident, Macros20NormalizedIdent, Span, Symbol, kw, sym}; +use rustc_span::{BytePos, DUMMY_SP, Ident, Span, Symbol, kw, sym}; use smallvec::{SmallVec, smallvec}; use thin_vec::ThinVec; use tracing::{debug, instrument, trace}; use crate::{ - BindingError, BindingKey, Decl, Finalize, LateDecl, Module, ModuleOrUniformRoot, ParentScope, - PathResult, ResolutionError, Resolver, Segment, Stage, TyCtxt, UseError, Used, errors, - path_names_to_string, rustdoc, + BindingError, BindingKey, Decl, Finalize, IdentKey, LateDecl, Module, ModuleOrUniformRoot, + ParentScope, PathResult, ResolutionError, Resolver, Segment, Stage, TyCtxt, UseError, Used, + errors, path_names_to_string, rustdoc, }; mod diagnostics; @@ -3650,7 +3650,7 @@ impl<'a, 'ast, 'ra, 'tcx> LateResolutionVisitor<'a, 'ast, 'ra, 'tcx> { return; }; ident.span.normalize_to_macros_2_0_and_adjust(module.expansion); - let key = BindingKey::new(Macros20NormalizedIdent::new(ident), ns); + let key = BindingKey::new(IdentKey::new(ident), ns); let mut decl = self.r.resolution(module, key).and_then(|r| r.best_decl()); debug!(?decl); if decl.is_none() { @@ -3661,7 +3661,7 @@ impl<'a, 'ast, 'ra, 'tcx> LateResolutionVisitor<'a, 'ast, 'ra, 'tcx> { TypeNS => ValueNS, _ => ns, }; - let key = BindingKey::new(Macros20NormalizedIdent::new(ident), ns); + let key = BindingKey::new(IdentKey::new(ident), ns); decl = self.r.resolution(module, key).and_then(|r| r.best_decl()); debug!(?decl); } diff --git a/compiler/rustc_resolve/src/late/diagnostics.rs b/compiler/rustc_resolve/src/late/diagnostics.rs index c5d15dcc91af..a3ee17ec4a9a 100644 --- a/compiler/rustc_resolve/src/late/diagnostics.rs +++ b/compiler/rustc_resolve/src/late/diagnostics.rs @@ -1620,22 +1620,24 @@ impl<'ast, 'ra, 'tcx> LateResolutionVisitor<'_, 'ast, 'ra, 'tcx> { if let PathResult::Module(ModuleOrUniformRoot::Module(module)) = self.resolve_path(mod_path, None, None, *source) { - let targets: Vec<_> = - self.r - .resolutions(module) - .borrow() - .iter() - .filter_map(|(key, resolution)| { - resolution.borrow().best_decl().map(|binding| binding.res()).and_then( - |res| if filter_fn(res) { Some((*key, res)) } else { None }, - ) + let targets: Vec<_> = self + .r + .resolutions(module) + .borrow() + .iter() + .filter_map(|(key, resolution)| { + let resolution = resolution.borrow(); + resolution.best_decl().map(|binding| binding.res()).and_then(|res| { + if filter_fn(res) { + Some((key.ident.name, resolution.orig_ident_span, res)) + } else { + None + } }) - .collect(); - if let [target] = targets.as_slice() { - return Some(TypoSuggestion::single_item_from_ident( - target.0.ident.0, - target.1, - )); + }) + .collect(); + if let &[(name, orig_ident_span, res)] = targets.as_slice() { + return Some(TypoSuggestion::single_item(name, orig_ident_span, res)); } } } @@ -2662,7 +2664,7 @@ impl<'ast, 'ra, 'tcx> LateResolutionVisitor<'_, 'ast, 'ra, 'tcx> { // Locals and type parameters for (ident, &res) in &rib.bindings { if filter_fn(res) && ident.span.ctxt() == rib_ctxt { - names.push(TypoSuggestion::typo_from_ident(*ident, res)); + names.push(TypoSuggestion::new(ident.name, ident.span, res)); } } @@ -2824,7 +2826,7 @@ impl<'ast, 'ra, 'tcx> LateResolutionVisitor<'_, 'ast, 'ra, 'tcx> { break; } - in_module.for_each_child(self.r, |r, ident, _, name_binding| { + in_module.for_each_child(self.r, |r, ident, orig_ident_span, _, name_binding| { // abort if the module is already found or if name_binding is private external if result.is_some() || !name_binding.vis().is_visible_locally() { return; @@ -2832,7 +2834,7 @@ impl<'ast, 'ra, 'tcx> LateResolutionVisitor<'_, 'ast, 'ra, 'tcx> { if let Some(module_def_id) = name_binding.res().module_like_def_id() { // form the path let mut path_segments = path_segments.clone(); - path_segments.push(ast::PathSegment::from_ident(ident.0)); + path_segments.push(ast::PathSegment::from_ident(ident.orig(orig_ident_span))); let doc_visible = doc_visible && (module_def_id.is_local() || !r.tcx.is_doc_hidden(module_def_id)); if module_def_id == def_id { @@ -2868,10 +2870,10 @@ impl<'ast, 'ra, 'tcx> LateResolutionVisitor<'_, 'ast, 'ra, 'tcx> { fn collect_enum_ctors(&self, def_id: DefId) -> Option> { self.find_module(def_id).map(|(enum_module, enum_import_suggestion)| { let mut variants = Vec::new(); - enum_module.for_each_child(self.r, |_, ident, _, name_binding| { + enum_module.for_each_child(self.r, |_, ident, orig_ident_span, _, name_binding| { if let Res::Def(DefKind::Ctor(CtorOf::Variant, kind), def_id) = name_binding.res() { let mut segms = enum_import_suggestion.path.segments.clone(); - segms.push(ast::PathSegment::from_ident(ident.0)); + segms.push(ast::PathSegment::from_ident(ident.orig(orig_ident_span))); let path = Path { span: name_binding.span, segments: segms, tokens: None }; variants.push((path, def_id, kind)); } diff --git a/compiler/rustc_resolve/src/lib.rs b/compiler/rustc_resolve/src/lib.rs index c60b7aa50313..5fe1be039a88 100644 --- a/compiler/rustc_resolve/src/lib.rs +++ b/compiler/rustc_resolve/src/lib.rs @@ -33,6 +33,7 @@ use std::sync::Arc; use diagnostics::{ImportSuggestion, LabelSuggestion, Suggestion}; use effective_visibilities::EffectiveVisibilitiesVisitor; use errors::{ParamKindInEnumDiscriminant, ParamKindInNonTrivialAnonConst}; +use hygiene::Macros20NormalizedSyntaxContext; use imports::{Import, ImportData, ImportKind, NameResolution, PendingDecl}; use late::{ ForwardGenericParamBanReason, HasGenericParams, PathSource, PatternSource, @@ -75,7 +76,7 @@ use rustc_query_system::ich::StableHashingContext; use rustc_session::config::CrateType; use rustc_session::lint::builtin::PRIVATE_MACRO_USE; use rustc_span::hygiene::{ExpnId, LocalExpnId, MacroKind, SyntaxContext, Transparency}; -use rustc_span::{DUMMY_SP, Ident, Macros20NormalizedIdent, Span, Symbol, kw, sym}; +use rustc_span::{DUMMY_SP, Ident, Span, Symbol, kw, sym}; use smallvec::{SmallVec, smallvec}; use tracing::debug; @@ -552,6 +553,40 @@ impl ModuleKind { } } +/// Combination of a symbol and its macros 2.0 normalized hygiene context. +/// Used as a key in various kinds of name containers, including modules (as a part of slightly +/// larger `BindingKey`) and preludes. +/// +/// Often passed around together with `orig_ident_span: Span`, which is an unnormalized span +/// of the original `Ident` from which `IdentKey` was obtained. This span is not used in map keys, +/// but used in a number of other scenarios - diagnostics, edition checks, `allow_unstable` checks +/// and similar. This is required because macros 2.0 normalization is lossy and the normalized +/// spans / syntax contexts no longer contain parts of macro backtraces, while the original span +/// contains everything. +#[derive(Clone, Copy, PartialEq, Eq, Hash, Debug)] +struct IdentKey { + name: Symbol, + ctxt: Macros20NormalizedSyntaxContext, +} + +impl IdentKey { + #[inline] + fn new(ident: Ident) -> IdentKey { + IdentKey { name: ident.name, ctxt: Macros20NormalizedSyntaxContext::new(ident.span.ctxt()) } + } + + #[inline] + fn with_root_ctxt(name: Symbol) -> Self { + let ctxt = Macros20NormalizedSyntaxContext::new_unchecked(SyntaxContext::root()); + IdentKey { name, ctxt } + } + + #[inline] + fn orig(self, orig_ident_span: Span) -> Ident { + Ident::new(self.name, orig_ident_span) + } +} + /// A key that identifies a binding in a given `Module`. /// /// Multiple bindings in the same module can have the same key (in a valid @@ -560,7 +595,7 @@ impl ModuleKind { struct BindingKey { /// The identifier for the binding, always the `normalize_to_macros_2_0` version of the /// identifier. - ident: Macros20NormalizedIdent, + ident: IdentKey, ns: Namespace, /// When we add an underscore binding (with ident `_`) to some module, this field has /// a non-zero value that uniquely identifies this binding in that module. @@ -571,12 +606,12 @@ struct BindingKey { } impl BindingKey { - fn new(ident: Macros20NormalizedIdent, ns: Namespace) -> Self { + fn new(ident: IdentKey, ns: Namespace) -> Self { BindingKey { ident, ns, disambiguator: 0 } } fn new_disambiguated( - ident: Macros20NormalizedIdent, + ident: IdentKey, ns: Namespace, disambiguator: impl FnOnce() -> u32, ) -> BindingKey { @@ -623,16 +658,7 @@ struct ModuleData<'ra> { /// Used to memoize the traits in this module for faster searches through all traits in scope. traits: CmRefCell< - Option< - Box< - [( - Macros20NormalizedIdent, - Decl<'ra>, - Option>, - bool, /* lint ambiguous */ - )], - >, - >, + Option, Option>, bool /* lint ambiguous */)]>>, >, /// Span of the module itself. Used for error reporting. @@ -699,11 +725,12 @@ impl<'ra> Module<'ra> { fn for_each_child<'tcx, R: AsRef>>( self, resolver: &R, - mut f: impl FnMut(&R, Macros20NormalizedIdent, Namespace, Decl<'ra>), + mut f: impl FnMut(&R, IdentKey, Span, Namespace, Decl<'ra>), ) { for (key, name_resolution) in resolver.as_ref().resolutions(self).borrow().iter() { - if let Some(decl) = name_resolution.borrow().best_decl() { - f(resolver, key.ident, key.ns, decl); + let name_resolution = name_resolution.borrow(); + if let Some(decl) = name_resolution.best_decl() { + f(resolver, key.ident, name_resolution.orig_ident_span, key.ns, decl); } } } @@ -711,11 +738,12 @@ impl<'ra> Module<'ra> { fn for_each_child_mut<'tcx, R: AsMut>>( self, resolver: &mut R, - mut f: impl FnMut(&mut R, Macros20NormalizedIdent, Namespace, Decl<'ra>), + mut f: impl FnMut(&mut R, IdentKey, Span, Namespace, Decl<'ra>), ) { for (key, name_resolution) in resolver.as_mut().resolutions(self).borrow().iter() { - if let Some(decl) = name_resolution.borrow().best_decl() { - f(resolver, key.ident, key.ns, decl); + let name_resolution = name_resolution.borrow(); + if let Some(decl) = name_resolution.best_decl() { + f(resolver, key.ident, name_resolution.orig_ident_span, key.ns, decl); } } } @@ -725,13 +753,13 @@ impl<'ra> Module<'ra> { let mut traits = self.traits.borrow_mut(resolver.as_ref()); if traits.is_none() { let mut collected_traits = Vec::new(); - self.for_each_child(resolver, |r, name, ns, binding| { + self.for_each_child(resolver, |r, ident, _, ns, binding| { if ns != TypeNS { return; } if let Res::Def(DefKind::Trait | DefKind::TraitAlias, def_id) = binding.res() { collected_traits.push(( - name, + ident.name, binding, r.as_ref().get_module(def_id), binding.is_ambiguity_recursive(), @@ -1081,14 +1109,14 @@ struct ExternPreludeEntry<'ra> { /// Name declaration from an `extern crate` item. /// The boolean flag is true is `item_decl` is non-redundant, happens either when /// `flag_decl` is `None`, or when `extern crate` introducing `item_decl` used renaming. - item_decl: Option<(Decl<'ra>, /* introduced by item */ bool)>, + item_decl: Option<(Decl<'ra>, Span, /* introduced by item */ bool)>, /// Name declaration from an `--extern` flag, lazily populated on first use. flag_decl: Option, /* finalized */ bool)>>, } impl ExternPreludeEntry<'_> { fn introduced_by_item(&self) -> bool { - matches!(self.item_decl, Some((_, true))) + matches!(self.item_decl, Some((.., true))) } fn flag() -> Self { @@ -1097,11 +1125,18 @@ impl ExternPreludeEntry<'_> { flag_decl: Some(CacheCell::new((PendingDecl::Pending, false))), } } + + fn span(&self) -> Span { + match self.item_decl { + Some((_, span, _)) => span, + None => DUMMY_SP, + } + } } struct DeriveData { resolutions: Vec, - helper_attrs: Vec<(usize, Macros20NormalizedIdent)>, + helper_attrs: Vec<(usize, IdentKey, Span)>, has_derive_copy: bool, } @@ -1137,7 +1172,7 @@ pub struct Resolver<'ra, 'tcx> { assert_speculative: bool, prelude: Option> = None, - extern_prelude: FxIndexMap>, + extern_prelude: FxIndexMap>, /// N.B., this is used only for better diagnostics, not name resolution itself. field_names: LocalDefIdMap> = Default::default(), @@ -1228,8 +1263,8 @@ pub struct Resolver<'ra, 'tcx> { dummy_decl: Decl<'ra>, builtin_type_decls: FxHashMap>, builtin_attr_decls: FxHashMap>, - registered_tool_decls: FxHashMap>, - macro_names: FxHashSet = default::fx_hash_set(), + registered_tool_decls: FxHashMap>, + macro_names: FxHashSet = default::fx_hash_set(), builtin_macros: FxHashMap = default::fx_hash_map(), registered_tools: &'tcx RegisteredTools, macro_use_prelude: FxIndexMap>, @@ -1265,7 +1300,7 @@ pub struct Resolver<'ra, 'tcx> { /// `macro_rules` scopes produced by `macro_rules` item definitions. macro_rules_scopes: FxHashMap> = default::fx_hash_map(), /// Helper attributes that are in scope for the given expansion. - helper_attrs: FxHashMap)>> = default::fx_hash_map(), + helper_attrs: FxHashMap)>> = default::fx_hash_map(), /// Ready or in-progress results of resolving paths inside the `#[derive(...)]` attribute /// with the given `ExpnId`. derive_data: FxHashMap = default::fx_hash_map(), @@ -1409,8 +1444,11 @@ impl<'ra> ResolverArenas<'ra> { fn alloc_import(&'ra self, import: ImportData<'ra>) -> Import<'ra> { Interned::new_unchecked(self.imports.alloc(import)) } - fn alloc_name_resolution(&'ra self) -> &'ra CmRefCell> { - self.name_resolutions.alloc(Default::default()) + fn alloc_name_resolution( + &'ra self, + orig_ident_span: Span, + ) -> &'ra CmRefCell> { + self.name_resolutions.alloc(CmRefCell::new(NameResolution::new(orig_ident_span))) } fn alloc_macro_rules_scope(&'ra self, scope: MacroRulesScope<'ra>) -> MacroRulesScopeRef<'ra> { self.dropless.alloc(CacheCell::new(scope)) @@ -1580,7 +1618,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { && let name = Symbol::intern(name) && name.can_be_raw() { - let ident = Macros20NormalizedIdent::with_dummy_span(name); + let ident = IdentKey::with_root_ctxt(name); Some((ident, ExternPreludeEntry::flag())) } else { None @@ -1589,10 +1627,10 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { .collect(); if !attr::contains_name(attrs, sym::no_core) { - let ident = Macros20NormalizedIdent::with_dummy_span(sym::core); + let ident = IdentKey::with_root_ctxt(sym::core); extern_prelude.insert(ident, ExternPreludeEntry::flag()); if !attr::contains_name(attrs, sym::no_std) { - let ident = Macros20NormalizedIdent::with_dummy_span(sym::std); + let ident = IdentKey::with_root_ctxt(sym::std); extern_prelude.insert(ident, ExternPreludeEntry::flag()); } } @@ -1637,10 +1675,10 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { .collect(), registered_tool_decls: registered_tools .iter() - .map(|ident| { + .map(|&ident| { let res = Res::ToolMod; let decl = arenas.new_pub_def_decl(res, ident.span, LocalExpnId::ROOT); - (*ident, decl) + (IdentKey::new(ident), decl) }) .collect(), registered_tools, @@ -1940,7 +1978,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { { if self.trait_may_have_item(trait_module, assoc_item) { let def_id = trait_binding.res().def_id(); - let import_ids = self.find_transitive_imports(&trait_binding.kind, trait_name.0); + let import_ids = self.find_transitive_imports(&trait_binding.kind, trait_name); found_traits.push(TraitCandidate { def_id, import_ids, lint_ambiguous }); } } @@ -1969,7 +2007,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { fn find_transitive_imports( &mut self, mut kind: &DeclKind<'_>, - trait_name: Ident, + trait_name: Symbol, ) -> SmallVec<[LocalDefId; 1]> { let mut import_ids = smallvec![]; while let DeclKind::Import { import, source_decl, .. } = kind { @@ -2004,11 +2042,12 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { &self, module: Module<'ra>, key: BindingKey, + orig_ident_span: Span, ) -> &'ra CmRefCell> { self.resolutions(module) .borrow_mut_unchecked() .entry(key) - .or_insert_with(|| self.arenas.alloc_name_resolution()) + .or_insert_with(|| self.arenas.alloc_name_resolution(orig_ident_span)) } /// Test if AmbiguityError ambi is any identical to any one inside ambiguity_errors @@ -2082,8 +2121,9 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { // Avoid marking `extern crate` items that refer to a name from extern prelude, // but not introduce it, as used if they are accessed from lexical scope. if used == Used::Scope - && let Some(entry) = self.extern_prelude.get(&Macros20NormalizedIdent::new(ident)) - && entry.item_decl == Some((used_decl, false)) + && let Some(entry) = self.extern_prelude.get(&IdentKey::new(ident)) + && let Some((item_decl, _, false)) = entry.item_decl + && item_decl == used_decl { return; } @@ -2094,7 +2134,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { if let Some(id) = import.id() { self.used_imports.insert(id); } - self.add_to_glob_map(import, ident); + self.add_to_glob_map(import, ident.name); self.record_use_inner( ident, source_decl, @@ -2105,10 +2145,10 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { } #[inline] - fn add_to_glob_map(&mut self, import: Import<'_>, ident: Ident) { + fn add_to_glob_map(&mut self, import: Import<'_>, name: Symbol) { if let ImportKind::Glob { id, .. } = import.kind { let def_id = self.local_def_id(id); - self.glob_map.entry(def_id).or_default().insert(ident.name); + self.glob_map.entry(def_id).or_default().insert(name); } } @@ -2230,13 +2270,14 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { fn extern_prelude_get_item<'r>( mut self: CmResolver<'r, 'ra, 'tcx>, - ident: Macros20NormalizedIdent, + ident: IdentKey, + orig_ident_span: Span, finalize: bool, ) -> Option> { let entry = self.extern_prelude.get(&ident); - entry.and_then(|entry| entry.item_decl).map(|(decl, _)| { + entry.and_then(|entry| entry.item_decl).map(|(decl, ..)| { if finalize { - self.get_mut().record_use(ident.0, decl, Used::Scope); + self.get_mut().record_use(ident.orig(orig_ident_span), decl, Used::Scope); } decl }) @@ -2244,7 +2285,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { fn extern_prelude_get_flag( &self, - ident: Macros20NormalizedIdent, + ident: IdentKey, + orig_ident_span: Span, finalize: bool, ) -> Option> { let entry = self.extern_prelude.get(&ident); @@ -2253,14 +2295,18 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { let decl = match pending_decl { PendingDecl::Ready(decl) => { if finalize && !finalized { - self.cstore_mut().process_path_extern(self.tcx, ident.name, ident.span); + self.cstore_mut().process_path_extern( + self.tcx, + ident.name, + orig_ident_span, + ); } decl } PendingDecl::Pending => { debug_assert!(!finalized); let crate_id = if finalize { - self.cstore_mut().process_path_extern(self.tcx, ident.name, ident.span) + self.cstore_mut().process_path_extern(self.tcx, ident.name, orig_ident_span) } else { self.cstore_mut().maybe_process_path_extern(self.tcx, ident.name) }; @@ -2675,3 +2721,40 @@ mod ref_mut { } } } + +mod hygiene { + use rustc_span::SyntaxContext; + + /// A newtype around `SyntaxContext` that can only keep contexts produced by + /// [SyntaxContext::normalize_to_macros_2_0]. + #[derive(Clone, Copy, PartialEq, Eq, Hash, Debug)] + pub(crate) struct Macros20NormalizedSyntaxContext(SyntaxContext); + + impl Macros20NormalizedSyntaxContext { + #[inline] + pub(crate) fn new(ctxt: SyntaxContext) -> Macros20NormalizedSyntaxContext { + Macros20NormalizedSyntaxContext(ctxt.normalize_to_macros_2_0()) + } + + #[inline] + pub(crate) fn new_unchecked(ctxt: SyntaxContext) -> Macros20NormalizedSyntaxContext { + debug_assert_eq!(ctxt, ctxt.normalize_to_macros_2_0()); + Macros20NormalizedSyntaxContext(ctxt) + } + + /// The passed closure must preserve the context's normalized-ness. + #[inline] + pub(crate) fn update_unchecked(&mut self, f: impl FnOnce(&mut SyntaxContext) -> R) -> R { + let ret = f(&mut self.0); + debug_assert_eq!(self.0, self.0.normalize_to_macros_2_0()); + ret + } + } + + impl std::ops::Deref for Macros20NormalizedSyntaxContext { + type Target = SyntaxContext; + fn deref(&self) -> &Self::Target { + &self.0 + } + } +} diff --git a/compiler/rustc_resolve/src/macros.rs b/compiler/rustc_resolve/src/macros.rs index 8f05ad7924e3..b7d83d9e130c 100644 --- a/compiler/rustc_resolve/src/macros.rs +++ b/compiler/rustc_resolve/src/macros.rs @@ -29,16 +29,17 @@ use rustc_session::parse::feature_err; use rustc_span::edit_distance::find_best_match_for_name; use rustc_span::edition::Edition; use rustc_span::hygiene::{self, AstPass, ExpnData, ExpnKind, LocalExpnId, MacroKind}; -use rustc_span::{DUMMY_SP, Ident, Macros20NormalizedIdent, Span, Symbol, kw, sym}; +use rustc_span::{DUMMY_SP, Ident, Span, Symbol, kw, sym}; use crate::Namespace::*; use crate::errors::{ self, AddAsNonDerive, CannotDetermineMacroResolution, CannotFindIdentInThisScope, MacroExpectedFound, RemoveSurroundingDerive, }; +use crate::hygiene::Macros20NormalizedSyntaxContext; use crate::imports::Import; use crate::{ - BindingKey, CacheCell, CmResolver, Decl, DeclKind, DeriveData, Determinacy, Finalize, + BindingKey, CacheCell, CmResolver, Decl, DeclKind, DeriveData, Determinacy, Finalize, IdentKey, InvocationParent, MacroData, ModuleKind, ModuleOrUniformRoot, ParentScope, PathResult, ResolutionError, Resolver, ScopeSet, Segment, Used, }; @@ -52,7 +53,8 @@ pub(crate) struct MacroRulesDecl<'ra> { pub(crate) decl: Decl<'ra>, /// `macro_rules` scope into which the `macro_rules` item was planted. pub(crate) parent_macro_rules_scope: MacroRulesScopeRef<'ra>, - pub(crate) ident: Macros20NormalizedIdent, + pub(crate) ident: IdentKey, + pub(crate) orig_ident_span: Span, } /// The scope introduced by a `macro_rules!` macro. @@ -412,9 +414,12 @@ impl<'ra, 'tcx> ResolverExpand for Resolver<'ra, 'tcx> { Ok((Some(ext), _)) => { if !ext.helper_attrs.is_empty() { let span = resolution.path.segments.last().unwrap().ident.span; - entry.helper_attrs.extend(ext.helper_attrs.iter().map(|name| { - (i, Macros20NormalizedIdent::new(Ident::new(*name, span))) - })); + let ctxt = Macros20NormalizedSyntaxContext::new(span.ctxt()); + entry.helper_attrs.extend( + ext.helper_attrs + .iter() + .map(|&name| (i, IdentKey { name, ctxt }, span)), + ); } entry.has_derive_copy |= ext.builtin_name == Some(sym::Copy); ext @@ -430,13 +435,14 @@ impl<'ra, 'tcx> ResolverExpand for Resolver<'ra, 'tcx> { } } // Sort helpers in a stable way independent from the derive resolution order. - entry.helper_attrs.sort_by_key(|(i, _)| *i); + entry.helper_attrs.sort_by_key(|(i, ..)| *i); let helper_attrs = entry .helper_attrs .iter() - .map(|(_, ident)| { + .map(|&(_, ident, orig_ident_span)| { let res = Res::NonMacroAttr(NonMacroAttrKind::DeriveHelper); - (*ident, self.arenas.new_pub_def_decl(res, ident.span, expn_id)) + let decl = self.arenas.new_pub_def_decl(res, orig_ident_span, expn_id); + (ident, orig_ident_span, decl) }) .collect(); self.helper_attrs.insert(expn_id, helper_attrs); @@ -532,14 +538,14 @@ impl<'ra, 'tcx> ResolverExpand for Resolver<'ra, 'tcx> { } let mut idents = Vec::new(); - target_trait.for_each_child(self, |this, ident, ns, _binding| { + target_trait.for_each_child(self, |this, ident, orig_ident_span, ns, _binding| { // FIXME: Adjust hygiene for idents from globs, like for glob imports. if let Some(overriding_keys) = this.impl_binding_keys.get(&impl_def_id) && overriding_keys.contains(&BindingKey::new(ident, ns)) { // The name is overridden, do not produce it from the glob delegation. } else { - idents.push((ident.0, None)); + idents.push((ident.orig(orig_ident_span), None)); } }); Ok(idents) @@ -1145,14 +1151,13 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> { } } - pub(crate) fn check_reserved_macro_name(&self, ident: Ident, res: Res) { + pub(crate) fn check_reserved_macro_name(&self, name: Symbol, span: Span, res: Res) { // Reserve some names that are not quite covered by the general check // performed on `Resolver::builtin_attrs`. - if ident.name == sym::cfg || ident.name == sym::cfg_attr { + if name == sym::cfg || name == sym::cfg_attr { let macro_kinds = self.get_macro(res).map(|macro_data| macro_data.ext.macro_kinds()); if macro_kinds.is_some() && sub_namespace_match(macro_kinds, Some(MacroKind::Attr)) { - self.dcx() - .emit_err(errors::NameReservedInAttributeNamespace { span: ident.span, ident }); + self.dcx().emit_err(errors::NameReservedInAttributeNamespace { span, ident: name }); } } } diff --git a/compiler/rustc_span/src/hygiene.rs b/compiler/rustc_span/src/hygiene.rs index d94d82835d65..2e8037b3f9e4 100644 --- a/compiler/rustc_span/src/hygiene.rs +++ b/compiler/rustc_span/src/hygiene.rs @@ -837,11 +837,7 @@ impl SyntaxContext { /// ``` /// This returns `None` if the context cannot be glob-adjusted. /// Otherwise, it returns the scope to use when privacy checking (see `adjust` for details). - pub(crate) fn glob_adjust( - &mut self, - expn_id: ExpnId, - glob_span: Span, - ) -> Option> { + pub fn glob_adjust(&mut self, expn_id: ExpnId, glob_span: Span) -> Option> { HygieneData::with(|data| { let mut scope = None; let mut glob_ctxt = data.normalize_to_macros_2_0(glob_span.ctxt()); @@ -865,7 +861,7 @@ impl SyntaxContext { /// assert!(self.glob_adjust(expansion, glob_ctxt) == Some(privacy_checking_scope)); /// } /// ``` - pub(crate) fn reverse_glob_adjust( + pub fn reverse_glob_adjust( &mut self, expn_id: ExpnId, glob_span: Span, diff --git a/compiler/rustc_span/src/lib.rs b/compiler/rustc_span/src/lib.rs index 69f91cfab9e4..a178f3260d30 100644 --- a/compiler/rustc_span/src/lib.rs +++ b/compiler/rustc_span/src/lib.rs @@ -63,8 +63,7 @@ pub use span_encoding::{DUMMY_SP, Span}; pub mod symbol; pub use symbol::{ - ByteSymbol, Ident, MacroRulesNormalizedIdent, Macros20NormalizedIdent, STDLIB_STABLE_CRATES, - Symbol, kw, sym, + ByteSymbol, Ident, MacroRulesNormalizedIdent, STDLIB_STABLE_CRATES, Symbol, kw, sym, }; mod analyze_source_file; @@ -1312,30 +1311,6 @@ impl Span { mark } - #[inline] - pub fn glob_adjust(&mut self, expn_id: ExpnId, glob_span: Span) -> Option> { - let mut mark = None; - *self = self.map_ctxt(|mut ctxt| { - mark = ctxt.glob_adjust(expn_id, glob_span); - ctxt - }); - mark - } - - #[inline] - pub fn reverse_glob_adjust( - &mut self, - expn_id: ExpnId, - glob_span: Span, - ) -> Option> { - let mut mark = None; - *self = self.map_ctxt(|mut ctxt| { - mark = ctxt.reverse_glob_adjust(expn_id, glob_span); - ctxt - }); - mark - } - #[inline] pub fn normalize_to_macros_2_0(self) -> Span { self.map_ctxt(|ctxt| ctxt.normalize_to_macros_2_0()) diff --git a/compiler/rustc_span/src/symbol.rs b/compiler/rustc_span/src/symbol.rs index c4391c3ec4fc..b80d624bc496 100644 --- a/compiler/rustc_span/src/symbol.rs +++ b/compiler/rustc_span/src/symbol.rs @@ -3,7 +3,6 @@ //! type, and vice versa. use std::hash::{Hash, Hasher}; -use std::ops::Deref; use std::{fmt, str}; use rustc_arena::DroplessArena; @@ -186,6 +185,7 @@ symbols! { AtomicU64, AtomicU128, AtomicUsize, + AutoTrait, BTreeEntry, BTreeMap, BTreeSet, @@ -231,6 +231,7 @@ symbols! { Display, DoubleEndedIterator, Duration, + DynTrait, Encodable, Encoder, Enumerate, @@ -1297,6 +1298,7 @@ symbols! { io_stdout, irrefutable_let_patterns, is, + is_auto, is_val_statically_known, isa_attribute, isize, @@ -1750,6 +1752,7 @@ symbols! { precise_capturing_in_traits, precise_pointer_size_matching, precision, + predicates, pref_align_of, prefetch_read_data, prefetch_read_instruction, @@ -2297,6 +2300,7 @@ symbols! { trace_macros, track_caller, trait_alias, + trait_ty, trait_upcasting, transmute, transmute_generic_consts, @@ -2748,7 +2752,7 @@ impl fmt::Display for IdentPrinter { } } -/// An newtype around `Ident` that calls [Ident::normalize_to_macro_rules] on +/// A newtype around `Ident` that calls [Ident::normalize_to_macro_rules] on /// construction for "local variable hygiene" comparisons. /// /// Use this type when you need to compare identifiers according to macro_rules hygiene. @@ -2775,48 +2779,6 @@ impl fmt::Display for MacroRulesNormalizedIdent { } } -/// An newtype around `Ident` that calls [Ident::normalize_to_macros_2_0] on -/// construction for "item hygiene" comparisons. -/// -/// Identifiers with same string value become same if they came from the same macro 2.0 macro -/// (e.g., `macro` item, but not `macro_rules` item) and stay different if they came from -/// different macro 2.0 macros. -#[derive(Copy, Clone, Eq, PartialEq, Hash)] -pub struct Macros20NormalizedIdent(pub Ident); - -impl Macros20NormalizedIdent { - #[inline] - pub fn new(ident: Ident) -> Self { - Macros20NormalizedIdent(ident.normalize_to_macros_2_0()) - } - - // dummy_span does not need to be normalized, so we can use `Ident` directly - pub fn with_dummy_span(name: Symbol) -> Self { - Macros20NormalizedIdent(Ident::with_dummy_span(name)) - } -} - -impl fmt::Debug for Macros20NormalizedIdent { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - fmt::Debug::fmt(&self.0, f) - } -} - -impl fmt::Display for Macros20NormalizedIdent { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - fmt::Display::fmt(&self.0, f) - } -} - -/// By impl Deref, we can access the wrapped Ident as if it were a normal Ident -/// such as `norm_ident.name` instead of `norm_ident.0.name`. -impl Deref for Macros20NormalizedIdent { - type Target = Ident; - fn deref(&self) -> &Self::Target { - &self.0 - } -} - /// An interned UTF-8 string. /// /// Internally, a `Symbol` is implemented as an index, and all operations diff --git a/compiler/rustc_target/src/spec/targets/wasm32_unknown_emscripten.rs b/compiler/rustc_target/src/spec/targets/wasm32_unknown_emscripten.rs index 47623c34dce3..fb735b54dd82 100644 --- a/compiler/rustc_target/src/spec/targets/wasm32_unknown_emscripten.rs +++ b/compiler/rustc_target/src/spec/targets/wasm32_unknown_emscripten.rs @@ -19,6 +19,8 @@ pub(crate) fn target() -> Target { pre_link_args, post_link_args, relocation_model: RelocModel::Pic, + crt_static_respected: true, + crt_static_default: true, panic_strategy: PanicStrategy::Unwind, no_default_libraries: false, families: cvs!["unix", "wasm"], diff --git a/compiler/rustc_trait_selection/src/error_reporting/infer/nice_region_error/placeholder_relation.rs b/compiler/rustc_trait_selection/src/error_reporting/infer/nice_region_error/placeholder_relation.rs index 3bab09bc587f..05a1e3fe95dd 100644 --- a/compiler/rustc_trait_selection/src/error_reporting/infer/nice_region_error/placeholder_relation.rs +++ b/compiler/rustc_trait_selection/src/error_reporting/infer/nice_region_error/placeholder_relation.rs @@ -34,14 +34,18 @@ impl<'tcx> NiceRegionError<'_, 'tcx> { (Some(self.tcx().def_span(def_id)), Some(self.tcx().item_name(def_id))) } ty::BoundRegionKind::Anon | ty::BoundRegionKind::ClosureEnv => (None, None), - ty::BoundRegionKind::NamedAnon(_) => bug!("only used for pretty printing"), + ty::BoundRegionKind::NamedForPrinting(_) => { + bug!("only used for pretty printing") + } }; let (sup_span, sup_symbol) = match *sup_name { ty::BoundRegionKind::Named(def_id) => { (Some(self.tcx().def_span(def_id)), Some(self.tcx().item_name(def_id))) } ty::BoundRegionKind::Anon | ty::BoundRegionKind::ClosureEnv => (None, None), - ty::BoundRegionKind::NamedAnon(_) => bug!("only used for pretty printing"), + ty::BoundRegionKind::NamedForPrinting(_) => { + bug!("only used for pretty printing") + } }; let diag = match (sub_span, sup_span, sub_symbol, sup_symbol) { (Some(sub_span), Some(sup_span), Some(sub_symbol), Some(sup_symbol)) => { diff --git a/compiler/rustc_trait_selection/src/error_reporting/infer/region.rs b/compiler/rustc_trait_selection/src/error_reporting/infer/region.rs index fdaf2d619dd5..b11461cd0e32 100644 --- a/compiler/rustc_trait_selection/src/error_reporting/infer/region.rs +++ b/compiler/rustc_trait_selection/src/error_reporting/infer/region.rs @@ -1052,7 +1052,7 @@ impl<'a, 'tcx> TypeErrCtxt<'a, 'tcx> { } fn report_inference_failure(&self, var_origin: RegionVariableOrigin<'tcx>) -> Diag<'_> { - let br_string = |br: ty::BoundRegionKind| { + let br_string = |br: ty::BoundRegionKind<'tcx>| { let mut s = match br { ty::BoundRegionKind::Named(def_id) => self.tcx.item_name(def_id).to_string(), _ => String::new(), diff --git a/compiler/rustc_trait_selection/src/traits/coherence.rs b/compiler/rustc_trait_selection/src/traits/coherence.rs index 2aae5f2cde1e..9f59f6c59250 100644 --- a/compiler/rustc_trait_selection/src/traits/coherence.rs +++ b/compiler/rustc_trait_selection/src/traits/coherence.rs @@ -566,7 +566,7 @@ fn plug_infer_with_placeholders<'tcx>( ty, Ty::new_placeholder( self.infcx.tcx, - ty::Placeholder::new( + ty::PlaceholderType::new( self.universe, ty::BoundTy { var: self.next_var(), kind: ty::BoundTyKind::Anon }, ), @@ -592,9 +592,9 @@ fn plug_infer_with_placeholders<'tcx>( ct, ty::Const::new_placeholder( self.infcx.tcx, - ty::Placeholder::new( + ty::PlaceholderConst::new( self.universe, - ty::BoundConst { var: self.next_var() }, + ty::BoundConst::new(self.next_var()), ), ), ) @@ -623,7 +623,7 @@ fn plug_infer_with_placeholders<'tcx>( r, ty::Region::new_placeholder( self.infcx.tcx, - ty::Placeholder::new( + ty::PlaceholderRegion::new( self.universe, ty::BoundRegion { var: self.next_var(), diff --git a/compiler/rustc_trait_selection/src/traits/mod.rs b/compiler/rustc_trait_selection/src/traits/mod.rs index 5839a8c2e295..4e027a301cc8 100644 --- a/compiler/rustc_trait_selection/src/traits/mod.rs +++ b/compiler/rustc_trait_selection/src/traits/mod.rs @@ -772,7 +772,7 @@ fn replace_param_and_infer_args_with_placeholder<'tcx>( self.idx += 1; ty::Const::new_placeholder( self.tcx, - ty::PlaceholderConst::new(ty::UniverseIndex::ROOT, ty::BoundConst { var: idx }), + ty::PlaceholderConst::new(ty::UniverseIndex::ROOT, ty::BoundConst::new(idx)), ) } else { c.super_fold_with(self) diff --git a/compiler/rustc_trait_selection/src/traits/util.rs b/compiler/rustc_trait_selection/src/traits/util.rs index 19ccf6a55bf1..c3f46aa51c73 100644 --- a/compiler/rustc_trait_selection/src/traits/util.rs +++ b/compiler/rustc_trait_selection/src/traits/util.rs @@ -220,9 +220,9 @@ pub fn with_replaced_escaping_bound_vars< /// The inverse of [`BoundVarReplacer`]: replaces placeholders with the bound vars from which they came. pub struct PlaceholderReplacer<'a, 'tcx> { infcx: &'a InferCtxt<'tcx>, - mapped_regions: FxIndexMap, ty::BoundRegion>, - mapped_types: FxIndexMap, ty::BoundTy>, - mapped_consts: FxIndexMap, ty::BoundConst>, + mapped_regions: FxIndexMap, ty::BoundRegion<'tcx>>, + mapped_types: FxIndexMap, ty::BoundTy<'tcx>>, + mapped_consts: FxIndexMap, ty::BoundConst<'tcx>>, universe_indices: &'a [Option], current_index: ty::DebruijnIndex, } @@ -230,9 +230,9 @@ pub struct PlaceholderReplacer<'a, 'tcx> { impl<'a, 'tcx> PlaceholderReplacer<'a, 'tcx> { pub fn replace_placeholders>>( infcx: &'a InferCtxt<'tcx>, - mapped_regions: FxIndexMap, ty::BoundRegion>, - mapped_types: FxIndexMap, ty::BoundTy>, - mapped_consts: FxIndexMap, ty::BoundConst>, + mapped_regions: FxIndexMap, ty::BoundRegion<'tcx>>, + mapped_types: FxIndexMap, ty::BoundTy<'tcx>>, + mapped_consts: FxIndexMap, ty::BoundConst<'tcx>>, universe_indices: &'a [Option], value: T, ) -> T { diff --git a/compiler/rustc_ty_utils/src/ty.rs b/compiler/rustc_ty_utils/src/ty.rs index bb25a14ef744..d6a29aba22b9 100644 --- a/compiler/rustc_ty_utils/src/ty.rs +++ b/compiler/rustc_ty_utils/src/ty.rs @@ -210,7 +210,7 @@ struct ImplTraitInTraitFinder<'a, 'tcx> { tcx: TyCtxt<'tcx>, predicates: &'a mut Vec>, fn_def_id: DefId, - bound_vars: &'tcx ty::List, + bound_vars: &'tcx ty::List>, seen: FxHashSet, depth: ty::DebruijnIndex, } diff --git a/compiler/rustc_type_ir/src/binder.rs b/compiler/rustc_type_ir/src/binder.rs index b5c9080154ce..fc8b39f7c01f 100644 --- a/compiler/rustc_type_ir/src/binder.rs +++ b/compiler/rustc_type_ir/src/binder.rs @@ -1,11 +1,14 @@ use std::fmt; +use std::hash::Hash; use std::marker::PhantomData; use std::ops::{ControlFlow, Deref}; use derive_where::derive_where; #[cfg(feature = "nightly")] use rustc_macros::{Decodable_NoContext, Encodable_NoContext, HashStable_NoContext}; -use rustc_type_ir_macros::{GenericTypeVisitable, TypeFoldable_Generic, TypeVisitable_Generic}; +use rustc_type_ir_macros::{ + GenericTypeVisitable, Lift_Generic, TypeFoldable_Generic, TypeVisitable_Generic, +}; use tracing::instrument; use crate::data_structures::SsoHashSet; @@ -23,8 +26,11 @@ use crate::{self as ty, DebruijnIndex, Interner, UniverseIndex}; /// for more details. /// /// `Decodable` and `Encodable` are implemented for `Binder` using the `impl_binder_encode_decode!` macro. -#[derive_where(Clone, Hash, PartialEq, Debug; I: Interner, T)] +// FIXME(derive-where#136): Need to use separate `derive_where` for +// `Copy` and `Ord` to prevent the emitted `Clone` and `PartialOrd` +// impls from incorrectly relying on `T: Copy` and `T: Ord`. #[derive_where(Copy; I: Interner, T: Copy)] +#[derive_where(Clone, Hash, PartialEq, Debug; I: Interner, T)] #[derive(GenericTypeVisitable)] #[cfg_attr(feature = "nightly", derive(HashStable_NoContext))] pub struct Binder { @@ -359,9 +365,12 @@ impl TypeVisitor for ValidateBoundVars { /// `instantiate`. /// /// See for more details. -#[derive_where(Clone, PartialEq, Ord, Hash, Debug; I: Interner, T)] -#[derive_where(PartialOrd; I: Interner, T: Ord)] +// FIXME(derive-where#136): Need to use separate `derive_where` for +// `Copy` and `Ord` to prevent the emitted `Clone` and `PartialOrd` +// impls from incorrectly relying on `T: Copy` and `T: Ord`. +#[derive_where(Ord; I: Interner, T: Ord)] #[derive_where(Copy; I: Interner, T: Copy)] +#[derive_where(Clone, PartialOrd, PartialEq, Hash, Debug; I: Interner, T)] #[derive(GenericTypeVisitable)] #[cfg_attr( feature = "nightly", @@ -955,11 +964,12 @@ pub enum BoundVarIndexKind { /// The "placeholder index" fully defines a placeholder region, type, or const. Placeholders are /// identified by both a universe, as well as a name residing within that universe. Distinct bound /// regions/types/consts within the same universe simply have an unknown relationship to one -/// another. -#[derive_where(Clone, PartialEq, Ord, Hash; I: Interner, T)] -#[derive_where(PartialOrd; I: Interner, T: Ord)] -#[derive_where(Copy; I: Interner, T: Copy, T)] -#[derive_where(Eq; T)] +// FIXME(derive-where#136): Need to use separate `derive_where` for +// `Copy` and `Ord` to prevent the emitted `Clone` and `PartialOrd` +// impls from incorrectly relying on `T: Copy` and `T: Ord`. +#[derive_where(Ord; I: Interner, T: Ord)] +#[derive_where(Copy; I: Interner, T: Copy)] +#[derive_where(Clone, PartialOrd, PartialEq, Eq, Hash; I: Interner, T)] #[derive(TypeVisitable_Generic, TypeFoldable_Generic)] #[cfg_attr( feature = "nightly", @@ -973,12 +983,6 @@ pub struct Placeholder { _tcx: PhantomData I>, } -impl Placeholder { - pub fn new(universe: UniverseIndex, bound: T) -> Self { - Placeholder { universe, bound, _tcx: PhantomData } - } -} - impl fmt::Debug for ty::Placeholder { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { if self.universe == ty::UniverseIndex::ROOT { @@ -1003,3 +1007,321 @@ where }) } } + +#[derive_where(Clone, Copy, PartialEq, Eq, Hash; I: Interner)] +#[derive(Lift_Generic)] +#[cfg_attr( + feature = "nightly", + derive(Encodable_NoContext, Decodable_NoContext, HashStable_NoContext) +)] + +pub enum BoundRegionKind { + /// An anonymous region parameter for a given fn (&T) + Anon, + + /// An anonymous region parameter with a `Symbol` name. + /// + /// Used to give late-bound regions names for things like pretty printing. + NamedForPrinting(I::Symbol), + + /// Late-bound regions that appear in the AST. + Named(I::DefId), + + /// Anonymous region for the implicit env pointer parameter + /// to a closure + ClosureEnv, +} + +impl fmt::Debug for ty::BoundRegionKind { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match *self { + ty::BoundRegionKind::Anon => write!(f, "BrAnon"), + ty::BoundRegionKind::NamedForPrinting(name) => { + write!(f, "BrNamedForPrinting({:?})", name) + } + ty::BoundRegionKind::Named(did) => { + write!(f, "BrNamed({did:?})") + } + ty::BoundRegionKind::ClosureEnv => write!(f, "BrEnv"), + } + } +} + +impl BoundRegionKind { + pub fn is_named(&self, tcx: I) -> bool { + self.get_name(tcx).is_some() + } + + pub fn get_name(&self, tcx: I) -> Option { + match *self { + ty::BoundRegionKind::Named(def_id) => { + let name = tcx.item_name(def_id); + if name.is_kw_underscore_lifetime() { None } else { Some(name) } + } + ty::BoundRegionKind::NamedForPrinting(name) => Some(name), + _ => None, + } + } + + pub fn get_id(&self) -> Option { + match *self { + ty::BoundRegionKind::Named(id) => Some(id), + _ => None, + } + } +} + +#[derive_where(Clone, Copy, PartialEq, Eq, Debug, Hash; I: Interner)] +#[derive(Lift_Generic)] +#[cfg_attr( + feature = "nightly", + derive(Encodable_NoContext, Decodable_NoContext, HashStable_NoContext) +)] +pub enum BoundTyKind { + Anon, + Param(I::DefId), +} + +#[derive_where(Clone, Copy, PartialEq, Eq, Debug, Hash; I: Interner)] +#[derive(Lift_Generic)] +#[cfg_attr( + feature = "nightly", + derive(Encodable_NoContext, Decodable_NoContext, HashStable_NoContext) +)] +pub enum BoundVariableKind { + Ty(BoundTyKind), + Region(BoundRegionKind), + Const, +} + +impl BoundVariableKind { + pub fn expect_region(self) -> BoundRegionKind { + match self { + BoundVariableKind::Region(lt) => lt, + _ => panic!("expected a region, but found another kind"), + } + } + + pub fn expect_ty(self) -> BoundTyKind { + match self { + BoundVariableKind::Ty(ty) => ty, + _ => panic!("expected a type, but found another kind"), + } + } + + pub fn expect_const(self) { + match self { + BoundVariableKind::Const => (), + _ => panic!("expected a const, but found another kind"), + } + } +} + +#[derive_where(Clone, Copy, PartialEq, Eq, Hash; I: Interner)] +#[cfg_attr( + feature = "nightly", + derive(Encodable_NoContext, HashStable_NoContext, Decodable_NoContext) +)] +pub struct BoundRegion { + pub var: ty::BoundVar, + pub kind: BoundRegionKind, +} + +impl core::fmt::Debug for BoundRegion { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + match self.kind { + BoundRegionKind::Anon => write!(f, "{:?}", self.var), + BoundRegionKind::ClosureEnv => write!(f, "{:?}.Env", self.var), + BoundRegionKind::Named(def) => { + write!(f, "{:?}.Named({:?})", self.var, def) + } + BoundRegionKind::NamedForPrinting(symbol) => { + write!(f, "{:?}.NamedAnon({:?})", self.var, symbol) + } + } + } +} + +impl BoundRegion { + pub fn var(self) -> ty::BoundVar { + self.var + } + + pub fn assert_eq(self, var: BoundVariableKind) { + assert_eq!(self.kind, var.expect_region()) + } +} + +pub type PlaceholderRegion = ty::Placeholder>; + +impl PlaceholderRegion { + pub fn universe(self) -> UniverseIndex { + self.universe + } + + pub fn var(self) -> ty::BoundVar { + self.bound.var() + } + + pub fn with_updated_universe(self, ui: UniverseIndex) -> Self { + Self { universe: ui, bound: self.bound, _tcx: PhantomData } + } + + pub fn new(ui: UniverseIndex, bound: BoundRegion) -> Self { + Self { universe: ui, bound, _tcx: PhantomData } + } + + pub fn new_anon(ui: UniverseIndex, var: ty::BoundVar) -> Self { + let bound = BoundRegion { var, kind: BoundRegionKind::Anon }; + Self { universe: ui, bound, _tcx: PhantomData } + } +} + +#[derive_where(Clone, Copy, PartialEq, Eq, Hash; I: Interner)] +#[cfg_attr( + feature = "nightly", + derive(Encodable_NoContext, Decodable_NoContext, HashStable_NoContext) +)] +pub struct BoundTy { + pub var: ty::BoundVar, + pub kind: BoundTyKind, +} + +impl Lift for BoundTy +where + BoundTyKind: Lift>, +{ + type Lifted = BoundTy; + + fn lift_to_interner(self, cx: U) -> Option { + Some(BoundTy { var: self.var, kind: self.kind.lift_to_interner(cx)? }) + } +} + +impl fmt::Debug for ty::BoundTy { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self.kind { + ty::BoundTyKind::Anon => write!(f, "{:?}", self.var), + ty::BoundTyKind::Param(def_id) => write!(f, "{def_id:?}"), + } + } +} + +impl BoundTy { + pub fn var(self) -> ty::BoundVar { + self.var + } + + pub fn assert_eq(self, var: BoundVariableKind) { + assert_eq!(self.kind, var.expect_ty()) + } +} + +pub type PlaceholderType = ty::Placeholder>; + +impl PlaceholderType { + pub fn universe(self) -> UniverseIndex { + self.universe + } + + pub fn var(self) -> ty::BoundVar { + self.bound.var + } + + pub fn with_updated_universe(self, ui: UniverseIndex) -> Self { + Self { universe: ui, bound: self.bound, _tcx: PhantomData } + } + + pub fn new(ui: UniverseIndex, bound: BoundTy) -> Self { + Self { universe: ui, bound, _tcx: PhantomData } + } + + pub fn new_anon(ui: UniverseIndex, var: ty::BoundVar) -> Self { + let bound = BoundTy { var, kind: BoundTyKind::Anon }; + Self { universe: ui, bound, _tcx: PhantomData } + } +} + +#[derive_where(Clone, Copy, PartialEq, Debug, Eq, Hash; I: Interner)] +#[cfg_attr( + feature = "nightly", + derive(Encodable_NoContext, Decodable_NoContext, HashStable_NoContext) +)] +pub struct BoundConst { + pub var: ty::BoundVar, + #[derive_where(skip(Debug))] + pub _tcx: PhantomData I>, +} + +impl BoundConst { + pub fn var(self) -> ty::BoundVar { + self.var + } + + pub fn assert_eq(self, var: BoundVariableKind) { + var.expect_const() + } + + pub fn new(var: ty::BoundVar) -> Self { + Self { var, _tcx: PhantomData } + } +} + +pub type PlaceholderConst = ty::Placeholder>; + +impl PlaceholderConst { + pub fn universe(self) -> UniverseIndex { + self.universe + } + + pub fn var(self) -> ty::BoundVar { + self.bound.var + } + + pub fn with_updated_universe(self, ui: UniverseIndex) -> Self { + Self { universe: ui, bound: self.bound, _tcx: PhantomData } + } + + pub fn new(ui: UniverseIndex, bound: BoundConst) -> Self { + Self { universe: ui, bound, _tcx: PhantomData } + } + + pub fn new_anon(ui: UniverseIndex, var: ty::BoundVar) -> Self { + let bound = BoundConst::new(var); + Self { universe: ui, bound, _tcx: PhantomData } + } + + pub fn find_const_ty_from_env(self, env: I::ParamEnv) -> I::Ty { + let mut candidates = env.caller_bounds().iter().filter_map(|clause| { + // `ConstArgHasType` are never desugared to be higher ranked. + match clause.kind().skip_binder() { + ty::ClauseKind::ConstArgHasType(placeholder_ct, ty) => { + assert!(!(placeholder_ct, ty).has_escaping_bound_vars()); + + match placeholder_ct.kind() { + ty::ConstKind::Placeholder(placeholder_ct) if placeholder_ct == self => { + Some(ty) + } + _ => None, + } + } + _ => None, + } + }); + + // N.B. it may be tempting to fix ICEs by making this function return + // `Option>` instead of `Ty<'tcx>`; however, this is generally + // considered to be a bandaid solution, since it hides more important + // underlying issues with how we construct generics and predicates of + // items. It's advised to fix the underlying issue rather than trying + // to modify this function. + let ty = candidates.next().unwrap_or_else(|| { + panic!("cannot find `{self:?}` in param-env: {env:#?}"); + }); + assert!( + candidates.next().is_none(), + "did not expect duplicate `ConstParamHasTy` for `{self:?}` in param-env: {env:#?}" + ); + ty + } +} diff --git a/compiler/rustc_type_ir/src/canonical.rs b/compiler/rustc_type_ir/src/canonical.rs index 12d222258b0c..8e7414674c6e 100644 --- a/compiler/rustc_type_ir/src/canonical.rs +++ b/compiler/rustc_type_ir/src/canonical.rs @@ -108,7 +108,7 @@ pub enum CanonicalVarKind { Float, /// A "placeholder" that represents "any type". - PlaceholderTy(I::PlaceholderTy), + PlaceholderTy(ty::PlaceholderType), /// Region variable `'?R`. Region(UniverseIndex), @@ -116,13 +116,13 @@ pub enum CanonicalVarKind { /// A "placeholder" that represents "any region". Created when you /// are solving a goal like `for<'a> T: Foo<'a>` to represent the /// bound region `'a`. - PlaceholderRegion(I::PlaceholderRegion), + PlaceholderRegion(ty::PlaceholderRegion), /// Some kind of const inference variable. Const(UniverseIndex), /// A "placeholder" that represents "any const". - PlaceholderConst(I::PlaceholderConst), + PlaceholderConst(ty::PlaceholderConst), } impl Eq for CanonicalVarKind {} diff --git a/compiler/rustc_type_ir/src/const_kind.rs b/compiler/rustc_type_ir/src/const_kind.rs index 5b136ae03121..b215230ea443 100644 --- a/compiler/rustc_type_ir/src/const_kind.rs +++ b/compiler/rustc_type_ir/src/const_kind.rs @@ -26,10 +26,10 @@ pub enum ConstKind { Infer(InferConst), /// Bound const variable, used only when preparing a trait query. - Bound(BoundVarIndexKind, I::BoundConst), + Bound(BoundVarIndexKind, ty::BoundConst), /// A placeholder const - universally quantified higher-ranked const. - Placeholder(I::PlaceholderConst), + Placeholder(ty::PlaceholderConst), /// An unnormalized const item such as an anon const or assoc const or free const item. /// Right now anything other than anon consts does not actually work properly but this diff --git a/compiler/rustc_type_ir/src/error.rs b/compiler/rustc_type_ir/src/error.rs index 502622aa50ca..eba4c7c6644a 100644 --- a/compiler/rustc_type_ir/src/error.rs +++ b/compiler/rustc_type_ir/src/error.rs @@ -33,7 +33,7 @@ pub enum TypeError { ArgCount, RegionsDoesNotOutlive(I::Region, I::Region), - RegionsInsufficientlyPolymorphic(I::BoundRegion, I::Region), + RegionsInsufficientlyPolymorphic(ty::BoundRegion, I::Region), RegionsPlaceholderMismatch, Sorts(ExpectedFound), diff --git a/compiler/rustc_type_ir/src/inherent.rs b/compiler/rustc_type_ir/src/inherent.rs index 4323b1ca6469..89cb236d38c6 100644 --- a/compiler/rustc_type_ir/src/inherent.rs +++ b/compiler/rustc_type_ir/src/inherent.rs @@ -12,7 +12,7 @@ use crate::elaborate::Elaboratable; use crate::fold::{TypeFoldable, TypeSuperFoldable}; use crate::relate::Relate; use crate::solve::{AdtDestructorKind, SizedTraitKind}; -use crate::visit::{Flags, TypeSuperVisitable, TypeVisitable, TypeVisitableExt}; +use crate::visit::{Flags, TypeSuperVisitable, TypeVisitable}; use crate::{self as ty, CollectAndApply, Interner, UpcastFrom}; pub trait Ty>: @@ -42,9 +42,9 @@ pub trait Ty>: fn new_param(interner: I, param: I::ParamTy) -> Self; - fn new_placeholder(interner: I, param: I::PlaceholderTy) -> Self; + fn new_placeholder(interner: I, param: ty::PlaceholderType) -> Self; - fn new_bound(interner: I, debruijn: ty::DebruijnIndex, var: I::BoundTy) -> Self; + fn new_bound(interner: I, debruijn: ty::DebruijnIndex, var: ty::BoundTy) -> Self; fn new_anon_bound(interner: I, debruijn: ty::DebruijnIndex, var: ty::BoundVar) -> Self; @@ -228,7 +228,7 @@ pub trait Region>: + Flags + Relate { - fn new_bound(interner: I, debruijn: ty::DebruijnIndex, var: I::BoundRegion) -> Self; + fn new_bound(interner: I, debruijn: ty::DebruijnIndex, var: ty::BoundRegion) -> Self; fn new_anon_bound(interner: I, debruijn: ty::DebruijnIndex, var: ty::BoundVar) -> Self; @@ -236,7 +236,7 @@ pub trait Region>: fn new_static(interner: I) -> Self; - fn new_placeholder(interner: I, var: I::PlaceholderRegion) -> Self; + fn new_placeholder(interner: I, var: ty::PlaceholderRegion) -> Self; fn is_bound(self) -> bool { matches!(self.kind(), ty::ReBound(..)) @@ -260,13 +260,13 @@ pub trait Const>: fn new_var(interner: I, var: ty::ConstVid) -> Self; - fn new_bound(interner: I, debruijn: ty::DebruijnIndex, bound_const: I::BoundConst) -> Self; + fn new_bound(interner: I, debruijn: ty::DebruijnIndex, bound_const: ty::BoundConst) -> Self; fn new_anon_bound(interner: I, debruijn: ty::DebruijnIndex, var: ty::BoundVar) -> Self; fn new_canonical_bound(interner: I, var: ty::BoundVar) -> Self; - fn new_placeholder(interner: I, param: I::PlaceholderConst) -> Self; + fn new_placeholder(interner: I, param: ty::PlaceholderConst) -> Self; fn new_unevaluated(interner: I, uv: ty::UnevaluatedConst) -> Self; @@ -543,68 +543,12 @@ pub trait Clauses>: { } -/// Common capabilities of placeholder kinds -pub trait PlaceholderLike: Copy + Debug + Hash + Eq { - fn universe(self) -> ty::UniverseIndex; - fn var(self) -> ty::BoundVar; - - type Bound: BoundVarLike; - fn new(ui: ty::UniverseIndex, bound: Self::Bound) -> Self; - fn new_anon(ui: ty::UniverseIndex, var: ty::BoundVar) -> Self; - fn with_updated_universe(self, ui: ty::UniverseIndex) -> Self; -} - -pub trait PlaceholderConst: PlaceholderLike { - fn find_const_ty_from_env(self, env: I::ParamEnv) -> I::Ty; -} -impl PlaceholderConst for I::PlaceholderConst { - fn find_const_ty_from_env(self, env: I::ParamEnv) -> I::Ty { - let mut candidates = env.caller_bounds().iter().filter_map(|clause| { - // `ConstArgHasType` are never desugared to be higher ranked. - match clause.kind().skip_binder() { - ty::ClauseKind::ConstArgHasType(placeholder_ct, ty) => { - assert!(!(placeholder_ct, ty).has_escaping_bound_vars()); - - match placeholder_ct.kind() { - ty::ConstKind::Placeholder(placeholder_ct) if placeholder_ct == self => { - Some(ty) - } - _ => None, - } - } - _ => None, - } - }); - - // N.B. it may be tempting to fix ICEs by making this function return - // `Option>` instead of `Ty<'tcx>`; however, this is generally - // considered to be a bandaid solution, since it hides more important - // underlying issues with how we construct generics and predicates of - // items. It's advised to fix the underlying issue rather than trying - // to modify this function. - let ty = candidates.next().unwrap_or_else(|| { - panic!("cannot find `{self:?}` in param-env: {env:#?}"); - }); - assert!( - candidates.next().is_none(), - "did not expect duplicate `ConstParamHasTy` for `{self:?}` in param-env: {env:#?}" - ); - ty - } -} - pub trait IntoKind { type Kind; fn kind(self) -> Self::Kind; } -pub trait BoundVarLike: Copy + Debug + Hash + Eq { - fn var(self) -> ty::BoundVar; - - fn assert_eq(self, var: I::BoundVarKind); -} - pub trait ParamLike: Copy + Debug + Hash + Eq { fn index(self) -> u32; } @@ -768,3 +712,7 @@ impl<'a, S: SliceLike> SliceLike for &'a S { (*self).as_slice() } } + +pub trait Symbol: Copy + Hash + PartialEq + Eq + Debug { + fn is_kw_underscore_lifetime(self) -> bool; +} diff --git a/compiler/rustc_type_ir/src/interner.rs b/compiler/rustc_type_ir/src/interner.rs index 0ab27a65c687..59ae6733fb84 100644 --- a/compiler/rustc_type_ir/src/interner.rs +++ b/compiler/rustc_type_ir/src/interner.rs @@ -61,8 +61,12 @@ pub trait Interner: type GenericArg: GenericArg; type Term: Term; - type BoundVarKinds: Copy + Debug + Hash + Eq + SliceLike + Default; - type BoundVarKind: Copy + Debug + Hash + Eq; + type BoundVarKinds: Copy + + Debug + + Hash + + Eq + + SliceLike> + + Default; type PredefinedOpaques: Copy + Debug @@ -120,9 +124,7 @@ pub trait Interner: type Tys: Tys; type FnInputTys: Copy + Debug + Hash + Eq + SliceLike + TypeVisitable; type ParamTy: ParamLike; - type BoundTy: BoundVarLike; - type PlaceholderTy: PlaceholderLike; - type Symbol: Copy + Hash + PartialEq + Eq + Debug; + type Symbol: Symbol; // Things stored inside of tys type ErrorGuaranteed: Copy + Debug + Hash + Eq; @@ -149,8 +151,6 @@ pub trait Interner: // Kinds of consts type Const: Const; type ParamConst: Copy + Debug + Hash + Eq + ParamLike; - type BoundConst: BoundVarLike; - type PlaceholderConst: PlaceholderConst; type ValueConst: ValueConst; type ExprConst: ExprConst; type ValTree: ValTree; @@ -160,8 +160,6 @@ pub trait Interner: type Region: Region; type EarlyParamRegion: ParamLike; type LateParamRegion: Copy + Debug + Hash + Eq; - type BoundRegion: BoundVarLike; - type PlaceholderRegion: PlaceholderLike; type RegionAssumptions: Copy + Debug @@ -411,6 +409,8 @@ pub trait Interner: self, canonical_goal: CanonicalInput, ) -> (QueryResult, Self::Probe); + + fn item_name(self, item_index: Self::DefId) -> Self::Symbol; } /// Imagine you have a function `F: FnOnce(&[T]) -> R`, plus an iterator `iter` diff --git a/compiler/rustc_type_ir/src/outlives.rs b/compiler/rustc_type_ir/src/outlives.rs index c7dccea6adc1..300e5c0b4695 100644 --- a/compiler/rustc_type_ir/src/outlives.rs +++ b/compiler/rustc_type_ir/src/outlives.rs @@ -14,7 +14,7 @@ use crate::{self as ty, Interner}; pub enum Component { Region(I::Region), Param(I::ParamTy), - Placeholder(I::PlaceholderTy), + Placeholder(ty::PlaceholderType), UnresolvedInferenceVariable(ty::InferTy), // Projections like `T::Foo` are tricky because a constraint like diff --git a/compiler/rustc_type_ir/src/region_kind.rs b/compiler/rustc_type_ir/src/region_kind.rs index 9acf9ff8557e..e08c274f9f14 100644 --- a/compiler/rustc_type_ir/src/region_kind.rs +++ b/compiler/rustc_type_ir/src/region_kind.rs @@ -8,7 +8,7 @@ use rustc_macros::{Decodable_NoContext, Encodable_NoContext, HashStable_NoContex use rustc_type_ir_macros::GenericTypeVisitable; use self::RegionKind::*; -use crate::{BoundVarIndexKind, Interner}; +use crate::{BoundRegion, BoundVarIndexKind, Interner, PlaceholderRegion}; rustc_index::newtype_index! { /// A **region** **v**ariable **ID**. @@ -149,7 +149,7 @@ pub enum RegionKind { /// Bound regions inside of types **must not** be erased, as they impact trait /// selection and the `TypeId` of that type. `for<'a> fn(&'a ())` and /// `fn(&'static ())` are different types and have to be treated as such. - ReBound(BoundVarIndexKind, I::BoundRegion), + ReBound(BoundVarIndexKind, BoundRegion), /// Late-bound function parameters are represented using a `ReBound`. When /// inside of a function, we convert these bound variables to placeholder @@ -170,7 +170,7 @@ pub enum RegionKind { /// Should not exist outside of type inference. /// /// Used when instantiating a `forall` binder via `infcx.enter_forall`. - RePlaceholder(I::PlaceholderRegion), + RePlaceholder(PlaceholderRegion), /// Erased region, used by trait selection, in MIR and during codegen. ReErased, @@ -214,9 +214,9 @@ impl fmt::Debug for RegionKind { impl HashStable for RegionKind where I::EarlyParamRegion: HashStable, - I::BoundRegion: HashStable, I::LateParamRegion: HashStable, - I::PlaceholderRegion: HashStable, + I::DefId: HashStable, + I::Symbol: HashStable, { #[inline] fn hash_stable(&self, hcx: &mut CTX, hasher: &mut StableHasher) { diff --git a/compiler/rustc_type_ir/src/ty_kind.rs b/compiler/rustc_type_ir/src/ty_kind.rs index 498797bef653..7cb71387e868 100644 --- a/compiler/rustc_type_ir/src/ty_kind.rs +++ b/compiler/rustc_type_ir/src/ty_kind.rs @@ -233,7 +233,7 @@ pub enum TyKind { /// /// [1]: https://rustc-dev-guide.rust-lang.org/traits/hrtb.html /// [2]: https://rustc-dev-guide.rust-lang.org/traits/canonical-queries.html - Bound(BoundVarIndexKind, I::BoundTy), + Bound(BoundVarIndexKind, ty::BoundTy), /// A placeholder type, used during higher ranked subtyping to instantiate /// bound variables. @@ -243,7 +243,7 @@ pub enum TyKind { /// to the bound variable's index from the binder from which it was instantiated), /// and `U` is the universe index in which it is instantiated, or totally omitted /// if the universe index is zero. - Placeholder(I::PlaceholderTy), + Placeholder(ty::PlaceholderType), /// A type variable used during type checking. /// diff --git a/library/Cargo.lock b/library/Cargo.lock index 608e7e412c3b..4801f92c63e5 100644 --- a/library/Cargo.lock +++ b/library/Cargo.lock @@ -274,9 +274,9 @@ dependencies = [ [[package]] name = "rustc-demangle" -version = "0.1.26" +version = "0.1.27" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "56f7d92ca342cea22a06f2121d944b4fd82af56988c270852495420f961d4ace" +checksum = "b50b8869d9fc858ce7266cce0194bd74df58b9d0e3f6df3a9fc8eb470d95c09d" dependencies = [ "rustc-std-workspace-core", ] diff --git a/library/alloc/Cargo.toml b/library/alloc/Cargo.toml index fb1f8c86dbfd..541257b6cda6 100644 --- a/library/alloc/Cargo.toml +++ b/library/alloc/Cargo.toml @@ -21,7 +21,6 @@ compiler_builtins = { path = "../compiler-builtins/compiler-builtins", features [features] compiler-builtins-mem = ['compiler_builtins/mem'] compiler-builtins-c = ["compiler_builtins/c"] -compiler-builtins-no-f16-f128 = ["compiler_builtins/no-f16-f128"] # Choose algorithms that are optimized for binary size instead of runtime performance optimize_for_size = ["core/optimize_for_size"] diff --git a/library/alloc/src/collections/linked_list.rs b/library/alloc/src/collections/linked_list.rs index 6cab5728a281..3889fca30bc8 100644 --- a/library/alloc/src/collections/linked_list.rs +++ b/library/alloc/src/collections/linked_list.rs @@ -854,7 +854,6 @@ impl LinkedList { /// # Examples /// /// ``` - /// #![feature(push_mut)] /// use std::collections::LinkedList; /// /// let mut dl = LinkedList::from([1, 2, 3]); @@ -863,7 +862,7 @@ impl LinkedList { /// *ptr += 4; /// assert_eq!(dl.front().unwrap(), &6); /// ``` - #[unstable(feature = "push_mut", issue = "135974")] + #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] #[must_use = "if you don't need a reference to the value, use `LinkedList::push_front` instead"] pub fn push_front_mut(&mut self, elt: T) -> &mut T { let mut node = @@ -926,7 +925,6 @@ impl LinkedList { /// # Examples /// /// ``` - /// #![feature(push_mut)] /// use std::collections::LinkedList; /// /// let mut dl = LinkedList::from([1, 2, 3]); @@ -935,7 +933,7 @@ impl LinkedList { /// *ptr += 4; /// assert_eq!(dl.back().unwrap(), &6); /// ``` - #[unstable(feature = "push_mut", issue = "135974")] + #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] #[must_use = "if you don't need a reference to the value, use `LinkedList::push_back` instead"] pub fn push_back_mut(&mut self, elt: T) -> &mut T { let mut node = diff --git a/library/alloc/src/collections/vec_deque/mod.rs b/library/alloc/src/collections/vec_deque/mod.rs index c51317a1a68f..eda29db44257 100644 --- a/library/alloc/src/collections/vec_deque/mod.rs +++ b/library/alloc/src/collections/vec_deque/mod.rs @@ -2168,7 +2168,6 @@ impl VecDeque { /// # Examples /// /// ``` - /// #![feature(push_mut)] /// use std::collections::VecDeque; /// /// let mut d = VecDeque::from([1, 2, 3]); @@ -2176,7 +2175,7 @@ impl VecDeque { /// *x -= 1; /// assert_eq!(d.front(), Some(&7)); /// ``` - #[unstable(feature = "push_mut", issue = "135974")] + #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] #[must_use = "if you don't need a reference to the value, use `VecDeque::push_front` instead"] pub fn push_front_mut(&mut self, value: T) -> &mut T { if self.is_full() { @@ -2212,7 +2211,6 @@ impl VecDeque { /// # Examples /// /// ``` - /// #![feature(push_mut)] /// use std::collections::VecDeque; /// /// let mut d = VecDeque::from([1, 2, 3]); @@ -2220,7 +2218,7 @@ impl VecDeque { /// *x += 1; /// assert_eq!(d.back(), Some(&10)); /// ``` - #[unstable(feature = "push_mut", issue = "135974")] + #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] #[must_use = "if you don't need a reference to the value, use `VecDeque::push_back` instead"] pub fn push_back_mut(&mut self, value: T) -> &mut T { if self.is_full() { @@ -2419,7 +2417,6 @@ impl VecDeque { /// # Examples /// /// ``` - /// #![feature(push_mut)] /// use std::collections::VecDeque; /// /// let mut vec_deque = VecDeque::from([1, 2, 3]); @@ -2428,7 +2425,7 @@ impl VecDeque { /// *x += 7; /// assert_eq!(vec_deque, &[1, 12, 2, 3]); /// ``` - #[unstable(feature = "push_mut", issue = "135974")] + #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] #[must_use = "if you don't need a reference to the value, use `VecDeque::insert` instead"] pub fn insert_mut(&mut self, index: usize, value: T) -> &mut T { assert!(index <= self.len(), "index out of bounds"); diff --git a/library/alloc/src/collections/vec_deque/splice.rs b/library/alloc/src/collections/vec_deque/splice.rs index cd98af7341de..d7b9a96291c3 100644 --- a/library/alloc/src/collections/vec_deque/splice.rs +++ b/library/alloc/src/collections/vec_deque/splice.rs @@ -143,7 +143,11 @@ impl Drain<'_, T, A> { let new_tail_start = tail_start + additional; unsafe { - deque.wrap_copy(tail_start, new_tail_start, self.tail_len); + deque.wrap_copy( + deque.to_physical_idx(tail_start), + deque.to_physical_idx(new_tail_start), + self.tail_len, + ); } self.drain_len += additional; } diff --git a/library/alloc/src/fmt.rs b/library/alloc/src/fmt.rs index 3d7c580be8c9..e3ff2ba51aba 100644 --- a/library/alloc/src/fmt.rs +++ b/library/alloc/src/fmt.rs @@ -136,9 +136,10 @@ //! padding specified by fill/alignment will be used to take up the required //! space (see below). //! -//! The value for the width can also be provided as a [`usize`] in the list of -//! parameters by adding a postfix `$`, indicating that the second argument is -//! a [`usize`] specifying the width. +//! The width can also be provided dynamically by referencing another argument +//! with a `$` suffix. Use `{:N$}` to reference the Nth positional argument +//! (where N is an integer), or `{:name$}` to reference a named argument. The +//! referenced argument must be of type [`usize`]. //! //! Referring to an argument with the dollar syntax does not affect the "next //! argument" counter, so it's usually a good idea to refer to arguments by @@ -236,7 +237,8 @@ //! //! 2. An integer or name followed by dollar sign `.N$`: //! -//! use format *argument* `N` (which must be a `usize`) as the precision. +//! use the value of format *argument* `N` (which must be a `usize`) as the precision. +//! An integer refers to a positional argument, and a name refers to a named argument. //! //! 3. An asterisk `.*`: //! @@ -363,7 +365,10 @@ //! - `ws` is any character for which [`char::is_whitespace`] returns `true`, has no semantic //! meaning and is completely optional, //! - `integer` is a decimal integer that may contain leading zeroes and must fit into an `usize` and -//! - `identifier` is an `IDENTIFIER_OR_KEYWORD` (not an `IDENTIFIER`) as defined by the [Rust language reference](https://doc.rust-lang.org/reference/identifiers.html). +//! - `identifier` is an `IDENTIFIER_OR_KEYWORD` (not an `IDENTIFIER`) as +//! defined by the [Rust language +//! reference](https://doc.rust-lang.org/reference/identifiers.html), except +//! for a bare `_`. //! //! # Formatting traits //! diff --git a/library/alloc/src/vec/mod.rs b/library/alloc/src/vec/mod.rs index aaf22e80ec60..6cbe89d9da4f 100644 --- a/library/alloc/src/vec/mod.rs +++ b/library/alloc/src/vec/mod.rs @@ -1003,9 +1003,6 @@ const impl Vec { /// # Examples /// /// ``` - /// #![feature(push_mut)] - /// - /// /// let mut vec = vec![1, 2]; /// let last = vec.push_mut(3); /// assert_eq!(*last, 3); @@ -1023,7 +1020,7 @@ const impl Vec { /// vector's elements to a larger allocation. This expensive operation is /// offset by the *capacity* *O*(1) insertions it allows. #[inline] - #[unstable(feature = "push_mut", issue = "135974")] + #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] #[must_use = "if you don't need a reference to the value, use `Vec::push` instead"] pub fn push_mut(&mut self, value: T) -> &mut T { // Inform codegen that the length does not change across grow_one(). @@ -2196,7 +2193,6 @@ impl Vec { /// # Examples /// /// ``` - /// #![feature(push_mut)] /// let mut vec = vec![1, 3, 5, 9]; /// let x = vec.insert_mut(3, 6); /// *x += 1; @@ -2210,7 +2206,7 @@ impl Vec { /// the insertion index is 0. #[cfg(not(no_global_oom_handling))] #[inline] - #[unstable(feature = "push_mut", issue = "135974")] + #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] #[track_caller] #[must_use = "if you don't need a reference to the value, use `Vec::insert` instead"] pub fn insert_mut(&mut self, index: usize, element: T) -> &mut T { @@ -2689,7 +2685,6 @@ impl Vec { /// Takes *O*(1) time. #[inline] #[unstable(feature = "vec_push_within_capacity", issue = "100486")] - // #[unstable(feature = "push_mut", issue = "135974")] pub fn push_within_capacity(&mut self, value: T) -> Result<&mut T, T> { if self.len == self.buf.capacity() { return Err(value); diff --git a/library/alloctests/tests/vec_deque.rs b/library/alloctests/tests/vec_deque.rs index e06d18250a51..92853fe00fd6 100644 --- a/library/alloctests/tests/vec_deque.rs +++ b/library/alloctests/tests/vec_deque.rs @@ -2336,3 +2336,14 @@ fn test_splice_forget() { std::mem::forget(v.splice(2..4, a)); assert_eq!(v, &[1, 2]); } + +#[test] +fn test_splice_wrapping() { + let mut vec = VecDeque::with_capacity(10); + vec.push_front(7u8); + vec.push_back(9); + + vec.splice(1..1, [8]); + + assert_eq!(Vec::from(vec), [7, 8, 9]); +} diff --git a/library/compiler-builtins/builtins-shim/Cargo.toml b/library/compiler-builtins/builtins-shim/Cargo.toml index ac77224f5ce1..746d5b21dc3f 100644 --- a/library/compiler-builtins/builtins-shim/Cargo.toml +++ b/library/compiler-builtins/builtins-shim/Cargo.toml @@ -47,10 +47,6 @@ c = ["dep:cc"] # the generic versions on all platforms. no-asm = [] -# Workaround for codegen backends which haven't yet implemented `f16` and -# `f128` support. Disabled any intrinsics which use those types. -no-f16-f128 = [] - # Flag this library as the unstable compiler-builtins lib compiler-builtins = [] diff --git a/library/compiler-builtins/builtins-test/Cargo.toml b/library/compiler-builtins/builtins-test/Cargo.toml index 9346ea65420b..550f736a76db 100644 --- a/library/compiler-builtins/builtins-test/Cargo.toml +++ b/library/compiler-builtins/builtins-test/Cargo.toml @@ -33,7 +33,6 @@ utest-macros = { git = "https://github.com/japaric/utest" } default = ["mangled-names"] c = ["compiler_builtins/c"] no-asm = ["compiler_builtins/no-asm"] -no-f16-f128 = ["compiler_builtins/no-f16-f128"] mem = ["compiler_builtins/mem"] mangled-names = ["compiler_builtins/mangled-names"] # Skip tests that rely on f128 symbols being available on the system diff --git a/library/compiler-builtins/ci/run.sh b/library/compiler-builtins/ci/run.sh index bc94d42fe837..0c07b32c74b9 100755 --- a/library/compiler-builtins/ci/run.sh +++ b/library/compiler-builtins/ci/run.sh @@ -36,8 +36,6 @@ else "${test_builtins[@]}" --features c --release "${test_builtins[@]}" --features no-asm "${test_builtins[@]}" --features no-asm --release - "${test_builtins[@]}" --features no-f16-f128 - "${test_builtins[@]}" --features no-f16-f128 --release "${test_builtins[@]}" --benches "${test_builtins[@]}" --benches --release @@ -63,8 +61,6 @@ symcheck+=(-- build-and-check) "${symcheck[@]}" "$target" -- -p compiler_builtins --features c --release "${symcheck[@]}" "$target" -- -p compiler_builtins --features no-asm "${symcheck[@]}" "$target" -- -p compiler_builtins --features no-asm --release -"${symcheck[@]}" "$target" -- -p compiler_builtins --features no-f16-f128 -"${symcheck[@]}" "$target" -- -p compiler_builtins --features no-f16-f128 --release run_intrinsics_test() { build_args=(--verbose --manifest-path builtins-test-intrinsics/Cargo.toml) diff --git a/library/compiler-builtins/compiler-builtins/Cargo.toml b/library/compiler-builtins/compiler-builtins/Cargo.toml index 0845861dcfe3..496dde2d4cf2 100644 --- a/library/compiler-builtins/compiler-builtins/Cargo.toml +++ b/library/compiler-builtins/compiler-builtins/Cargo.toml @@ -45,10 +45,6 @@ c = ["dep:cc"] # the generic versions on all platforms. no-asm = [] -# Workaround for codegen backends which haven't yet implemented `f16` and -# `f128` support. Disabled any intrinsics which use those types. -no-f16-f128 = [] - # Flag this library as the unstable compiler-builtins lib compiler-builtins = [] diff --git a/library/compiler-builtins/compiler-builtins/configure.rs b/library/compiler-builtins/compiler-builtins/configure.rs index 79e238abc0f6..f16da6b58f81 100644 --- a/library/compiler-builtins/compiler-builtins/configure.rs +++ b/library/compiler-builtins/compiler-builtins/configure.rs @@ -95,16 +95,13 @@ pub fn configure_aliases(target: &Target) { * * https://github.com/rust-lang/rustc_codegen_cranelift/blob/c713ffab3c6e28ab4b4dd4e392330f786ea657ad/src/lib.rs#L196-L226 */ - // If the feature is set, disable both of these types. - let no_f16_f128 = target.cargo_features.iter().any(|s| s == "no-f16-f128"); - println!("cargo::rustc-check-cfg=cfg(f16_enabled)"); - if target.reliable_f16 && !no_f16_f128 { + if target.reliable_f16 { println!("cargo::rustc-cfg=f16_enabled"); } println!("cargo::rustc-check-cfg=cfg(f128_enabled)"); - if target.reliable_f128 && !no_f16_f128 { + if target.reliable_f128 { println!("cargo::rustc-cfg=f128_enabled"); } } diff --git a/library/compiler-builtins/libm/configure.rs b/library/compiler-builtins/libm/configure.rs index 857a30229716..ee65a3a8d624 100644 --- a/library/compiler-builtins/libm/configure.rs +++ b/library/compiler-builtins/libm/configure.rs @@ -143,16 +143,13 @@ fn emit_f16_f128_cfg(cfg: &Config) { /* See the compiler-builtins configure file for info about the meaning of these options */ - // If the feature is set, disable both of these types. - let no_f16_f128 = cfg.cargo_features.iter().any(|s| s == "no-f16-f128"); - println!("cargo:rustc-check-cfg=cfg(f16_enabled)"); - if cfg.reliable_f16 && !no_f16_f128 { + if cfg.reliable_f16 { println!("cargo:rustc-cfg=f16_enabled"); } println!("cargo:rustc-check-cfg=cfg(f128_enabled)"); - if cfg.reliable_f128 && !no_f16_f128 { + if cfg.reliable_f128 { println!("cargo:rustc-cfg=f128_enabled"); } } diff --git a/library/core/src/mem/type_info.rs b/library/core/src/mem/type_info.rs index 30a70165b095..8b30803c97c9 100644 --- a/library/core/src/mem/type_info.rs +++ b/library/core/src/mem/type_info.rs @@ -47,6 +47,8 @@ pub enum TypeKind { Array(Array), /// Slices. Slice(Slice), + /// Dynamic Traits. + DynTrait(DynTrait), /// Primitive boolean type. Bool(Bool), /// Primitive character type. @@ -105,6 +107,36 @@ pub struct Slice { pub element_ty: TypeId, } +/// Compile-time type information about dynamic traits. +/// FIXME(#146922): Add super traits and generics +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +pub struct DynTrait { + /// The predicates of a dynamic trait. + pub predicates: &'static [DynTraitPredicate], +} + +/// Compile-time type information about a dynamic trait predicate. +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +pub struct DynTraitPredicate { + /// The type of the trait as a dynamic trait type. + pub trait_ty: Trait, +} + +/// Compile-time type information about a trait. +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +pub struct Trait { + /// The TypeId of the trait as a dynamic type + pub ty: TypeId, + /// Whether the trait is an auto trait + pub is_auto: bool, +} + /// Compile-time type information about `bool`. #[derive(Debug)] #[non_exhaustive] diff --git a/library/core/src/ptr/const_ptr.rs b/library/core/src/ptr/const_ptr.rs index 00b71f9a997c..2566d1471ab7 100644 --- a/library/core/src/ptr/const_ptr.rs +++ b/library/core/src/ptr/const_ptr.rs @@ -1386,6 +1386,43 @@ impl *const T { pub const fn cast_uninit(self) -> *const MaybeUninit { self as _ } + + /// Forms a raw slice from a pointer and a length. + /// + /// The `len` argument is the number of **elements**, not the number of bytes. + /// + /// This function is safe, but actually using the return value is unsafe. + /// See the documentation of [`slice::from_raw_parts`] for slice safety requirements. + /// + /// [`slice::from_raw_parts`]: crate::slice::from_raw_parts + /// + /// # Examples + /// + /// ```rust + /// #![feature(ptr_cast_slice)] + /// // create a slice pointer when starting out with a pointer to the first element + /// let x = [5, 6, 7]; + /// let raw_pointer = x.as_ptr(); + /// let slice = raw_pointer.cast_slice(3); + /// assert_eq!(unsafe { &*slice }[2], 7); + /// ``` + /// + /// You must ensure that the pointer is valid and not null before dereferencing + /// the raw slice. A slice reference must never have a null pointer, even if it's empty. + /// + /// ```rust,should_panic + /// #![feature(ptr_cast_slice)] + /// use std::ptr; + /// let danger: *const [u8] = ptr::null::().cast_slice(0); + /// unsafe { + /// danger.as_ref().expect("references must not be null"); + /// } + /// ``` + #[inline] + #[unstable(feature = "ptr_cast_slice", issue = "149103")] + pub const fn cast_slice(self, len: usize) -> *const [T] { + slice_from_raw_parts(self, len) + } } impl *const MaybeUninit { /// Casts from a maybe-uninitialized type to its initialized version. diff --git a/library/core/src/ptr/mut_ptr.rs b/library/core/src/ptr/mut_ptr.rs index 11e0a83bd7ec..20e71bc2a1a5 100644 --- a/library/core/src/ptr/mut_ptr.rs +++ b/library/core/src/ptr/mut_ptr.rs @@ -1655,6 +1655,51 @@ impl *mut T { pub const fn cast_uninit(self) -> *mut MaybeUninit { self as _ } + + /// Forms a raw mutable slice from a pointer and a length. + /// + /// The `len` argument is the number of **elements**, not the number of bytes. + /// + /// Performs the same functionality as [`cast_slice`] on a `*const T`, except that a + /// raw mutable slice is returned, as opposed to a raw immutable slice. + /// + /// This function is safe, but actually using the return value is unsafe. + /// See the documentation of [`slice::from_raw_parts_mut`] for slice safety requirements. + /// + /// [`slice::from_raw_parts_mut`]: crate::slice::from_raw_parts_mut + /// [`cast_slice`]: pointer::cast_slice + /// + /// # Examples + /// + /// ```rust + /// #![feature(ptr_cast_slice)] + /// + /// let x = &mut [5, 6, 7]; + /// let slice = x.as_mut_ptr().cast_slice(3); + /// + /// unsafe { + /// (*slice)[2] = 99; // assign a value at an index in the slice + /// }; + /// + /// assert_eq!(unsafe { &*slice }[2], 99); + /// ``` + /// + /// You must ensure that the pointer is valid and not null before dereferencing + /// the raw slice. A slice reference must never have a null pointer, even if it's empty. + /// + /// ```rust,should_panic + /// #![feature(ptr_cast_slice)] + /// use std::ptr; + /// let danger: *mut [u8] = ptr::null_mut::().cast_slice(0); + /// unsafe { + /// danger.as_mut().expect("references must not be null"); + /// } + /// ``` + #[inline] + #[unstable(feature = "ptr_cast_slice", issue = "149103")] + pub const fn cast_slice(self, len: usize) -> *mut [T] { + slice_from_raw_parts_mut(self, len) + } } impl *mut MaybeUninit { /// Casts from a maybe-uninitialized type to its initialized version. diff --git a/library/core/src/ptr/non_null.rs b/library/core/src/ptr/non_null.rs index cb43d095f5d1..7b9e638289bf 100644 --- a/library/core/src/ptr/non_null.rs +++ b/library/core/src/ptr/non_null.rs @@ -1377,6 +1377,35 @@ impl NonNull { pub const fn cast_uninit(self) -> NonNull> { self.cast() } + + /// Creates a non-null raw slice from a thin pointer and a length. + /// + /// The `len` argument is the number of **elements**, not the number of bytes. + /// + /// This function is safe, but dereferencing the return value is unsafe. + /// See the documentation of [`slice::from_raw_parts`] for slice safety requirements. + /// + /// # Examples + /// + /// ```rust + /// #![feature(ptr_cast_slice)] + /// use std::ptr::NonNull; + /// + /// // create a slice pointer when starting out with a pointer to the first element + /// let mut x = [5, 6, 7]; + /// let nonnull_pointer = NonNull::new(x.as_mut_ptr()).unwrap(); + /// let slice = nonnull_pointer.cast_slice(3); + /// assert_eq!(unsafe { slice.as_ref()[2] }, 7); + /// ``` + /// + /// (Note that this example artificially demonstrates a use of this method, + /// but `let slice = NonNull::from(&x[..]);` would be a better way to write code like this.) + #[inline] + #[must_use] + #[unstable(feature = "ptr_cast_slice", issue = "149103")] + pub const fn cast_slice(self, len: usize) -> NonNull<[T]> { + NonNull::slice_from_raw_parts(self, len) + } } impl NonNull> { /// Casts from a maybe-uninitialized type to its initialized version. diff --git a/library/core/src/slice/cmp.rs b/library/core/src/slice/cmp.rs index c3ff928a3277..2390ca74a8e0 100644 --- a/library/core/src/slice/cmp.rs +++ b/library/core/src/slice/cmp.rs @@ -4,6 +4,7 @@ use super::{from_raw_parts, memchr}; use crate::ascii; use crate::cmp::{self, BytewiseEq, Ordering}; use crate::intrinsics::compare_bytes; +use crate::mem::SizedTypeProperties; use crate::num::NonZero; use crate::ops::ControlFlow; @@ -15,7 +16,14 @@ where { #[inline] fn eq(&self, other: &[U]) -> bool { - SlicePartialEq::equal(self, other) + let len = self.len(); + if len == other.len() { + // SAFETY: Just checked that they're the same length, and the pointers + // come from references-to-slices so they're guaranteed readable. + unsafe { SlicePartialEq::equal_same_length(self.as_ptr(), other.as_ptr(), len) } + } else { + false + } } } @@ -95,12 +103,14 @@ impl PartialOrd for [T] { // intermediate trait for specialization of slice's PartialEq #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] const trait SlicePartialEq { - fn equal(&self, other: &[B]) -> bool; + /// # Safety + /// `lhs` and `rhs` are both readable for `len` elements + unsafe fn equal_same_length(lhs: *const Self, rhs: *const B, len: usize) -> bool; } // Generic slice equality #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const SlicePartialEq for [A] +impl const SlicePartialEq for A where A: [const] PartialEq, { @@ -109,19 +119,15 @@ where // such as in `::eq`. // The codegen backend can still inline it later if needed. #[rustc_no_mir_inline] - default fn equal(&self, other: &[B]) -> bool { - if self.len() != other.len() { - return false; - } - + default unsafe fn equal_same_length(lhs: *const Self, rhs: *const B, len: usize) -> bool { // Implemented as explicit indexing rather // than zipped iterators for performance reasons. // See PR https://github.com/rust-lang/rust/pull/116846 - // FIXME(const_hack): make this a `for idx in 0..self.len()` loop. + // FIXME(const_hack): make this a `for idx in 0..len` loop. let mut idx = 0; - while idx < self.len() { - // bound checks are optimized away - if self[idx] != other[idx] { + while idx < len { + // SAFETY: idx < len, so both are in-bounds and readable + if unsafe { *lhs.add(idx) != *rhs.add(idx) } { return false; } idx += 1; @@ -134,30 +140,18 @@ where // When each element can be compared byte-wise, we can compare all the bytes // from the whole size in one call to the intrinsics. #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] -impl const SlicePartialEq for [A] +impl const SlicePartialEq for A where A: [const] BytewiseEq, { - // This is usually a pretty good backend inlining candidate because the - // intrinsic tends to just be `memcmp`. However, as of 2025-12 letting - // MIR inline this makes reuse worse because it means that, for example, - // `String::eq` doesn't inline, whereas by keeping this from inling all - // the wrappers until the call to this disappear. If the heuristics have - // changed and this is no longer fruitful, though, please do remove it. - // In the mean time, it's fine to not inline it in MIR because the backend - // will still inline it if it things it's important to do so. - #[rustc_no_mir_inline] #[inline] - fn equal(&self, other: &[B]) -> bool { - if self.len() != other.len() { - return false; - } - - // SAFETY: `self` and `other` are references and are thus guaranteed to be valid. - // The two slices have been checked to have the same size above. + unsafe fn equal_same_length(lhs: *const Self, rhs: *const B, len: usize) -> bool { + // SAFETY: by our precondition, `lhs` and `rhs` are guaranteed to be valid + // for reading `len` values, which also means the size is guaranteed + // not to overflow because it exists in memory; unsafe { - let size = size_of_val(self); - compare_bytes(self.as_ptr() as *const u8, other.as_ptr() as *const u8, size) == 0 + let size = crate::intrinsics::unchecked_mul(len, Self::SIZE); + compare_bytes(lhs as _, rhs as _, size) == 0 } } } diff --git a/library/core/src/slice/mod.rs b/library/core/src/slice/mod.rs index 139d2a4b4272..429f90acec34 100644 --- a/library/core/src/slice/mod.rs +++ b/library/core/src/slice/mod.rs @@ -4443,7 +4443,6 @@ impl [T] { where Simd: AsRef<[T; LANES]>, T: simd::SimdElement, - simd::LaneCount: simd::SupportedLaneCount, { // These are expected to always match, as vector types are laid out like // arrays per , but we @@ -4479,7 +4478,6 @@ impl [T] { where Simd: AsMut<[T; LANES]>, T: simd::SimdElement, - simd::LaneCount: simd::SupportedLaneCount, { // These are expected to always match, as vector types are laid out like // arrays per , but we diff --git a/library/coretests/tests/mem/type_info.rs b/library/coretests/tests/mem/type_info.rs index 0820e4f83993..87f2d5dd8289 100644 --- a/library/coretests/tests/mem/type_info.rs +++ b/library/coretests/tests/mem/type_info.rs @@ -163,3 +163,132 @@ fn test_pointers() { _ => unreachable!(), } } + +#[test] +fn test_dynamic_traits() { + use std::collections::HashSet; + use std::mem::type_info::DynTraitPredicate; + trait A {} + + trait B { + type Foo; + } + + trait FooTrait<'a, 'b, const CONST_NUM: i32> {} + + trait ProjectorTrait<'a, 'b> {} + + fn preds_of() -> &'static [DynTraitPredicate] { + match const { Type::of::() }.kind { + TypeKind::DynTrait(d) => d.predicates, + _ => unreachable!(), + } + } + + fn pred<'a>(preds: &'a [DynTraitPredicate], want: TypeId) -> &'a DynTraitPredicate { + preds + .iter() + .find(|p| p.trait_ty.ty == want) + .unwrap_or_else(|| panic!("missing predicate for {want:?}")) + } + + fn assert_typeid_set_eq(actual: &[TypeId], expected: &[TypeId]) { + let actual_set: HashSet = actual.iter().copied().collect(); + let expected_set: HashSet = expected.iter().copied().collect(); + assert_eq!(actual.len(), actual_set.len(), "duplicates present: {actual:?}"); + assert_eq!( + actual_set, expected_set, + "unexpected ids.\nactual: {actual:?}\nexpected: {expected:?}" + ); + } + + fn assert_predicates_exact(preds: &[DynTraitPredicate], expected_pred_ids: &[TypeId]) { + let actual_pred_ids: Vec = preds.iter().map(|p| p.trait_ty.ty).collect(); + assert_typeid_set_eq(&actual_pred_ids, expected_pred_ids); + } + + // dyn Send + { + let preds = preds_of::(); + assert_predicates_exact(preds, &[TypeId::of::()]); + + let p = pred(preds, TypeId::of::()); + assert!(p.trait_ty.is_auto); + } + + // dyn A + { + let preds = preds_of::>(); + assert_predicates_exact(preds, &[TypeId::of::>()]); + + let p = pred(preds, TypeId::of::>()); + assert!(!p.trait_ty.is_auto); + } + + // dyn B<5, Foo = i32> + { + let preds = preds_of::>(); + assert_predicates_exact(preds, &[TypeId::of::>()]); + + let e = pred(preds, TypeId::of::>()); + assert!(!e.trait_ty.is_auto); + } + + // dyn for<'a> FooTrait<'a, 'a, 7> + { + let preds = preds_of:: FooTrait<'a, 'a, 7>>(); + assert_predicates_exact(preds, &[TypeId::of:: FooTrait<'a, 'a, 7>>()]); + + let foo = pred(preds, TypeId::of:: FooTrait<'a, 'a, 7>>()); + assert!(!foo.trait_ty.is_auto); + } + + // dyn FooTrait<'static, 'static, 7> + { + let preds = preds_of::>(); + assert_predicates_exact(preds, &[TypeId::of::>()]); + + let foo = pred(preds, TypeId::of::>()); + assert!(!foo.trait_ty.is_auto); + } + + // dyn for<'a, 'b> FooTrait<'a, 'b, 7> + { + let preds = preds_of:: FooTrait<'a, 'b, 7>>(); + assert_predicates_exact(preds, &[TypeId::of:: FooTrait<'a, 'b, 7>>()]); + + let foo = pred(preds, TypeId::of:: FooTrait<'a, 'b, 7>>()); + assert!(!foo.trait_ty.is_auto); + } + + // dyn for<'a, 'b> ProjectorTrait<'a, 'b> + { + let preds = preds_of:: ProjectorTrait<'a, 'b>>(); + assert_predicates_exact(preds, &[TypeId::of:: ProjectorTrait<'a, 'b>>()]); + + let proj = pred(preds, TypeId::of:: ProjectorTrait<'a, 'b>>()); + assert!(!proj.trait_ty.is_auto); + } + + // dyn for<'a> FooTrait<'a, 'a, 7> + Send + Sync + { + let preds = preds_of:: FooTrait<'a, 'a, 7> + Send + Sync>(); + assert_predicates_exact( + preds, + &[ + TypeId::of:: FooTrait<'a, 'a, 7>>(), + TypeId::of::(), + TypeId::of::(), + ], + ); + + let foo = pred(preds, TypeId::of:: FooTrait<'a, 'a, 7>>()); + assert!(!foo.trait_ty.is_auto); + + let send = pred(preds, TypeId::of::()); + assert!(send.trait_ty.is_auto); + + let sync = pred(preds, TypeId::of::()); + assert!(sync.trait_ty.is_auto); + } +} diff --git a/library/portable-simd/.github/workflows/ci.yml b/library/portable-simd/.github/workflows/ci.yml index 3984d8f0d8d9..de7efa355283 100644 --- a/library/portable-simd/.github/workflows/ci.yml +++ b/library/portable-simd/.github/workflows/ci.yml @@ -59,7 +59,7 @@ jobs: strategy: fail-fast: false matrix: - target: [x86_64-pc-windows-msvc, i686-pc-windows-msvc, i586-pc-windows-msvc, x86_64-unknown-linux-gnu] + target: [x86_64-pc-windows-msvc, i686-pc-windows-msvc, x86_64-unknown-linux-gnu] # `default` means we use the default target config for the target, # `native` means we run with `-Ctarget-cpu=native`, and anything else is # an arg to `-Ctarget-feature` @@ -68,18 +68,12 @@ jobs: exclude: # -Ctarget-cpu=native sounds like bad-news if target != host - { target: i686-pc-windows-msvc, target_feature: native } - - { target: i586-pc-windows-msvc, target_feature: native } include: # Populate the `matrix.os` field - { target: x86_64-unknown-linux-gnu, os: ubuntu-latest } - { target: x86_64-pc-windows-msvc, os: windows-latest } - { target: i686-pc-windows-msvc, os: windows-latest } - - { target: i586-pc-windows-msvc, os: windows-latest } - - # These are globally available on all the other targets. - - { target: i586-pc-windows-msvc, target_feature: +sse, os: windows-latest } - - { target: i586-pc-windows-msvc, target_feature: +sse2, os: windows-latest } # Annoyingly, the x86_64-unknown-linux-gnu runner *almost* always has # avx512vl, but occasionally doesn't. Maybe one day we can enable it. @@ -129,7 +123,7 @@ jobs: run: cargo doc --verbose --target=${{ matrix.target }} env: RUSTDOCFLAGS: -Dwarnings - + macos-tests: name: ${{ matrix.target }} runs-on: macos-latest @@ -246,9 +240,18 @@ jobs: miri: runs-on: ubuntu-latest + strategy: + fail-fast: false + matrix: + shard: [1, 2, 3, 4] env: PROPTEST_CASES: 16 steps: - uses: actions/checkout@v4 - - name: Test (Miri) - run: cargo miri test + + - name: Install cargo-nextest + uses: taiki-e/install-action@nextest + + - name: Test (Miri) (partition ${{ matrix.shard }}/4) + run: | + cargo miri nextest run --partition count:${{ matrix.shard }}/4 diff --git a/library/portable-simd/Cargo.lock b/library/portable-simd/Cargo.lock index 1584c704fb22..5a5f0d8907ae 100644 --- a/library/portable-simd/Cargo.lock +++ b/library/portable-simd/Cargo.lock @@ -1,12 +1,12 @@ # This file is automatically @generated by Cargo. # It is not intended for manual editing. -version = 3 +version = 4 [[package]] name = "autocfg" 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It can also be used to describe "scalar operations" that use strictly scalar values, like addition. This term is mostly used to differentiate between vectorized operations that use SIMD instructions and scalar operations that don't. -* **Lane:** A single element position within a vector is called a lane. If you have `N` lanes available then they're numbered from `0` to `N-1` when referring to them, again like an array. The biggest difference between an array element and a vector lane is that in general is *relatively costly* to access an individual lane value. On most architectures, the vector has to be pushed out of the SIMD register onto the stack, then an individual lane is accessed while it's on the stack (and possibly the stack value is read back into a register). For this reason, when working with SIMD you should avoid reading or writing the value of an individual lane during hot loops. +* **Lane:** A single element position within a vector is called a lane. If you have `N` lanes available then they're numbered from `0` to `N-1` when referring to them, again like an array. The biggest difference between an array element and a vector lane is that in general it is *relatively costly* to access an individual lane value. On most architectures, the vector has to be pushed out of the SIMD register onto the stack, then an individual lane is accessed while it's on the stack (and possibly the stack value is read back into a register). For this reason, when working with SIMD you should avoid reading or writing the value of an individual lane during hot loops. * **Bit Widths:** When talking about SIMD, the bit widths used are the bit size of the vectors involved, *not* the individual elements. So "128-bit SIMD" has 128-bit vectors, and that might be `f32x4`, `i32x4`, `i16x8`, or other variations. While 128-bit SIMD is the most common, there's also 64-bit, 256-bit, and even 512-bit on the newest CPUs. diff --git a/library/portable-simd/crates/core_simd/examples/dot_product.rs b/library/portable-simd/crates/core_simd/examples/dot_product.rs index 75d152ae7f0e..4ef32bfa60b5 100644 --- a/library/portable-simd/crates/core_simd/examples/dot_product.rs +++ b/library/portable-simd/crates/core_simd/examples/dot_product.rs @@ -1,8 +1,6 @@ //! Code taken from the `packed_simd` crate. //! Run this code with `cargo test --example dot_product`. -#![feature(array_chunks)] -#![feature(slice_as_chunks)] // Add these imports to use the stdsimd library #![feature(portable_simd)] use core_simd::simd::prelude::*; @@ -33,7 +31,7 @@ pub fn dot_prod_scalar_1(a: &[f32], b: &[f32]) -> f32 { } // We now move on to the SIMD implementations: notice the following constructs: -// `array_chunks::<4>`: mapping this over the vector will let use construct SIMD vectors +// `as_chunks::<4>`: mapping this over the vector will let us construct SIMD vectors // `f32x4::from_array`: construct the SIMD vector from a slice // `(a * b).reduce_sum()`: Multiply both f32x4 vectors together, and then reduce them. // This approach essentially uses SIMD to produce a vector of length N/4 of all the products, @@ -42,9 +40,11 @@ pub fn dot_prod_scalar_1(a: &[f32], b: &[f32]) -> f32 { pub fn dot_prod_simd_0(a: &[f32], b: &[f32]) -> f32 { assert_eq!(a.len(), b.len()); // TODO handle remainder when a.len() % 4 != 0 - a.array_chunks::<4>() + a.as_chunks::<4>() + .0 + .iter() .map(|&a| f32x4::from_array(a)) - .zip(b.array_chunks::<4>().map(|&b| f32x4::from_array(b))) + .zip(b.as_chunks::<4>().0.iter().map(|&b| f32x4::from_array(b))) .map(|(a, b)| (a * b).reduce_sum()) .sum() } @@ -60,9 +60,11 @@ pub fn dot_prod_simd_0(a: &[f32], b: &[f32]) -> f32 { pub fn dot_prod_simd_1(a: &[f32], b: &[f32]) -> f32 { assert_eq!(a.len(), b.len()); // TODO handle remainder when a.len() % 4 != 0 - a.array_chunks::<4>() + a.as_chunks::<4>() + .0 + .iter() .map(|&a| f32x4::from_array(a)) - .zip(b.array_chunks::<4>().map(|&b| f32x4::from_array(b))) + .zip(b.as_chunks::<4>().0.iter().map(|&b| f32x4::from_array(b))) .fold(f32x4::splat(0.0), |acc, zipped| acc + zipped.0 * zipped.1) .reduce_sum() } @@ -74,9 +76,11 @@ pub fn dot_prod_simd_2(a: &[f32], b: &[f32]) -> f32 { assert_eq!(a.len(), b.len()); // TODO handle remainder when a.len() % 4 != 0 let mut res = f32x4::splat(0.0); - a.array_chunks::<4>() + a.as_chunks::<4>() + .0 + .iter() .map(|&a| f32x4::from_array(a)) - .zip(b.array_chunks::<4>().map(|&b| f32x4::from_array(b))) + .zip(b.as_chunks::<4>().0.iter().map(|&b| f32x4::from_array(b))) .for_each(|(a, b)| { res = a.mul_add(b, res); }); @@ -113,9 +117,11 @@ pub fn dot_prod_simd_3(a: &[f32], b: &[f32]) -> f32 { // next example. pub fn dot_prod_simd_4(a: &[f32], b: &[f32]) -> f32 { let mut sum = a - .array_chunks::<4>() + .as_chunks::<4>() + .0 + .iter() .map(|&a| f32x4::from_array(a)) - .zip(b.array_chunks::<4>().map(|&b| f32x4::from_array(b))) + .zip(b.as_chunks::<4>().0.iter().map(|&b| f32x4::from_array(b))) .map(|(a, b)| a * b) .fold(f32x4::splat(0.0), std::ops::Add::add) .reduce_sum(); @@ -131,9 +137,11 @@ pub fn dot_prod_simd_4(a: &[f32], b: &[f32]) -> f32 { // This version allocates a single `XMM` register for accumulation, and the folds don't allocate on top of that. // Notice the use of `mul_add`, which can do a multiply and an add operation ber iteration. pub fn dot_prod_simd_5(a: &[f32], b: &[f32]) -> f32 { - a.array_chunks::<4>() + a.as_chunks::<4>() + .0 + .iter() .map(|&a| f32x4::from_array(a)) - .zip(b.array_chunks::<4>().map(|&b| f32x4::from_array(b))) + .zip(b.as_chunks::<4>().0.iter().map(|&b| f32x4::from_array(b))) .fold(f32x4::splat(0.), |acc, (a, b)| a.mul_add(b, acc)) .reduce_sum() } diff --git a/library/portable-simd/crates/core_simd/examples/matrix_inversion.rs b/library/portable-simd/crates/core_simd/examples/matrix_inversion.rs index bad86414401d..ad2eea9153e0 100644 --- a/library/portable-simd/crates/core_simd/examples/matrix_inversion.rs +++ b/library/portable-simd/crates/core_simd/examples/matrix_inversion.rs @@ -1,7 +1,7 @@ //! 4x4 matrix inverse // Code ported from the `packed_simd` crate // Run this code with `cargo test --example matrix_inversion` -#![feature(array_chunks, portable_simd)] +#![feature(portable_simd)] use core_simd::simd::prelude::*; // Gotta define our own 4x4 matrix since Rust doesn't ship multidim arrays yet :^) diff --git a/library/portable-simd/crates/core_simd/src/fmt.rs b/library/portable-simd/crates/core_simd/src/fmt.rs index 3a540f5a0490..90c520e75bb3 100644 --- a/library/portable-simd/crates/core_simd/src/fmt.rs +++ b/library/portable-simd/crates/core_simd/src/fmt.rs @@ -1,9 +1,8 @@ -use crate::simd::{LaneCount, Simd, SimdElement, SupportedLaneCount}; +use crate::simd::{Simd, SimdElement}; use core::fmt; impl fmt::Debug for Simd where - LaneCount: SupportedLaneCount, T: SimdElement + fmt::Debug, { /// A `Simd` has a debug format like the one for `[T]`: diff --git a/library/portable-simd/crates/core_simd/src/iter.rs b/library/portable-simd/crates/core_simd/src/iter.rs index b3732fd74d5f..fdc458efeda4 100644 --- a/library/portable-simd/crates/core_simd/src/iter.rs +++ b/library/portable-simd/crates/core_simd/src/iter.rs @@ -1,4 +1,4 @@ -use crate::simd::{LaneCount, Simd, SupportedLaneCount}; +use crate::simd::Simd; use core::{ iter::{Product, Sum}, ops::{Add, Mul}, @@ -7,8 +7,6 @@ use core::{ macro_rules! impl_traits { { $type:ty } => { impl Sum for Simd<$type, N> - where - LaneCount: SupportedLaneCount, { #[inline] fn sum>(iter: I) -> Self { @@ -17,8 +15,6 @@ macro_rules! impl_traits { } impl Product for Simd<$type, N> - where - LaneCount: SupportedLaneCount, { #[inline] fn product>(iter: I) -> Self { @@ -27,8 +23,6 @@ macro_rules! impl_traits { } impl<'a, const N: usize> Sum<&'a Self> for Simd<$type, N> - where - LaneCount: SupportedLaneCount, { #[inline] fn sum>(iter: I) -> Self { @@ -37,8 +31,6 @@ macro_rules! impl_traits { } impl<'a, const N: usize> Product<&'a Self> for Simd<$type, N> - where - LaneCount: SupportedLaneCount, { #[inline] fn product>(iter: I) -> Self { diff --git a/library/portable-simd/crates/core_simd/src/lane_count.rs b/library/portable-simd/crates/core_simd/src/lane_count.rs deleted file mode 100644 index bbdfd5f5f3ed..000000000000 --- a/library/portable-simd/crates/core_simd/src/lane_count.rs +++ /dev/null @@ -1,40 +0,0 @@ -mod sealed { - pub trait Sealed {} -} -use sealed::Sealed; - -/// Specifies the number of lanes in a SIMD vector as a type. -pub struct LaneCount; - -impl LaneCount { - /// The number of bytes in a bitmask with this many lanes. - pub const BITMASK_LEN: usize = N.div_ceil(8); -} - -/// Statically guarantees that a lane count is marked as supported. -/// -/// This trait is *sealed*: the list of implementors below is total. -/// Users do not have the ability to mark additional `LaneCount` values as supported. -/// Only SIMD vectors with supported lane counts are constructable. -pub trait SupportedLaneCount: Sealed { - #[doc(hidden)] - type BitMask: Copy + Default + AsRef<[u8]> + AsMut<[u8]>; -} - -impl Sealed for LaneCount {} - -macro_rules! supported_lane_count { - ($($lanes:literal),+) => { - $( - impl SupportedLaneCount for LaneCount<$lanes> { - type BitMask = [u8; ($lanes + 7) / 8]; - } - )+ - }; -} - -supported_lane_count!( - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, - 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, - 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64 -); diff --git a/library/portable-simd/crates/core_simd/src/lib.rs b/library/portable-simd/crates/core_simd/src/lib.rs index 717b882b64ba..fe26d99b9194 100644 --- a/library/portable-simd/crates/core_simd/src/lib.rs +++ b/library/portable-simd/crates/core_simd/src/lib.rs @@ -9,7 +9,8 @@ simd_ffi, staged_api, prelude_import, - ptr_metadata + ptr_metadata, + rustc_attrs )] #![cfg_attr( all( @@ -30,10 +31,6 @@ any(target_arch = "powerpc", target_arch = "powerpc64"), feature(stdarch_powerpc) )] -#![cfg_attr( - all(target_arch = "x86_64", target_feature = "avx512f"), - feature(stdarch_x86_avx512) -)] #![warn(missing_docs, clippy::missing_inline_in_public_items)] // basically all items, really #![deny( unsafe_op_in_unsafe_fn, @@ -41,7 +38,7 @@ clippy::undocumented_unsafe_blocks )] #![doc(test(attr(deny(warnings))))] -#![allow(internal_features)] +#![allow(internal_features, clippy::repr_packed_without_abi)] #![unstable(feature = "portable_simd", issue = "86656")] //! Portable SIMD module. diff --git a/library/portable-simd/crates/core_simd/src/masks.rs b/library/portable-simd/crates/core_simd/src/masks.rs index 19d45f4d3b31..3e2209556b66 100644 --- a/library/portable-simd/crates/core_simd/src/masks.rs +++ b/library/portable-simd/crates/core_simd/src/masks.rs @@ -2,20 +2,33 @@ //! Types representing #![allow(non_camel_case_types)] -#[cfg_attr( - not(all(target_arch = "x86_64", target_feature = "avx512f")), - path = "masks/full_masks.rs" -)] -#[cfg_attr( - all(target_arch = "x86_64", target_feature = "avx512f"), - path = "masks/bitmask.rs" -)] -mod mask_impl; - -use crate::simd::{LaneCount, Simd, SimdCast, SimdElement, SupportedLaneCount}; +use crate::simd::{Select, Simd, SimdCast, SimdElement}; use core::cmp::Ordering; use core::{fmt, mem}; +pub(crate) trait FixEndianness { + fn fix_endianness(self) -> Self; +} + +macro_rules! impl_fix_endianness { + { $($int:ty),* } => { + $( + impl FixEndianness for $int { + #[inline(always)] + fn fix_endianness(self) -> Self { + if cfg!(target_endian = "big") { + <$int>::reverse_bits(self) + } else { + self + } + } + } + )* + } +} + +impl_fix_endianness! { u8, u16, u32, u64 } + mod sealed { use super::*; @@ -28,7 +41,6 @@ mod sealed { pub trait Sealed { fn valid(values: Simd) -> bool where - LaneCount: SupportedLaneCount, Self: SimdElement; fn eq(self, other: Self) -> bool; @@ -56,8 +68,6 @@ macro_rules! impl_element { impl Sealed for $ty { #[inline] fn valid(value: Simd) -> bool - where - LaneCount: SupportedLaneCount, { // We can't use `Simd` directly, because `Simd`'s functions call this function and // we will end up with an infinite loop. @@ -108,23 +118,19 @@ impl_element! { isize, usize } /// The layout of this type is unspecified, and may change between platforms /// and/or Rust versions, and code should not assume that it is equivalent to /// `[T; N]`. +/// +/// `N` cannot be 0 and may be at most 64. This limit may be increased in +/// the future. #[repr(transparent)] -pub struct Mask(mask_impl::Mask) +pub struct Mask(Simd) where - T: MaskElement, - LaneCount: SupportedLaneCount; + T: MaskElement; -impl Copy for Mask -where - T: MaskElement, - LaneCount: SupportedLaneCount, -{ -} +impl Copy for Mask where T: MaskElement {} impl Clone for Mask where T: MaskElement, - LaneCount: SupportedLaneCount, { #[inline] fn clone(&self) -> Self { @@ -135,12 +141,12 @@ where impl Mask where T: MaskElement, - LaneCount: SupportedLaneCount, { /// Constructs a mask by setting all elements to the given value. #[inline] - pub fn splat(value: bool) -> Self { - Self(mask_impl::Mask::splat(value)) + #[rustc_const_unstable(feature = "portable_simd", issue = "86656")] + pub const fn splat(value: bool) -> Self { + Self(Simd::splat(if value { T::TRUE } else { T::FALSE })) } /// Converts an array of bools to a SIMD mask. @@ -156,7 +162,7 @@ where let bytes: [u8; N] = mem::transmute_copy(&array); let bools: Simd = core::intrinsics::simd::simd_ne(Simd::from_array(bytes), Simd::splat(0u8)); - Mask::from_int_unchecked(core::intrinsics::simd::simd_cast(bools)) + Mask::from_simd_unchecked(core::intrinsics::simd::simd_cast(bools)) } } @@ -174,7 +180,7 @@ where // This would be hypothetically valid as an "in-place" transmute, // but these are "dependently-sized" types, so copy elision it is! unsafe { - let mut bytes: Simd = core::intrinsics::simd::simd_cast(self.to_int()); + let mut bytes: Simd = core::intrinsics::simd::simd_cast(self.to_simd()); bytes &= Simd::splat(1i8); mem::transmute_copy(&bytes) } @@ -187,12 +193,12 @@ where /// All elements must be either 0 or -1. #[inline] #[must_use = "method returns a new mask and does not mutate the original value"] - pub unsafe fn from_int_unchecked(value: Simd) -> Self { + pub unsafe fn from_simd_unchecked(value: Simd) -> Self { // Safety: the caller must confirm this invariant unsafe { core::intrinsics::assume(::valid(value)); - Self(mask_impl::Mask::from_int_unchecked(value)) } + Self(value) } /// Converts a vector of integers to a mask, where 0 represents `false` and -1 @@ -203,25 +209,26 @@ where #[inline] #[must_use = "method returns a new mask and does not mutate the original value"] #[track_caller] - pub fn from_int(value: Simd) -> Self { + pub fn from_simd(value: Simd) -> Self { assert!(T::valid(value), "all values must be either 0 or -1",); // Safety: the validity has been checked - unsafe { Self::from_int_unchecked(value) } + unsafe { Self::from_simd_unchecked(value) } } /// Converts the mask to a vector of integers, where 0 represents `false` and -1 /// represents `true`. #[inline] #[must_use = "method returns a new vector and does not mutate the original value"] - pub fn to_int(self) -> Simd { - self.0.to_int() + pub fn to_simd(self) -> Simd { + self.0 } /// Converts the mask to a mask of any other element size. #[inline] #[must_use = "method returns a new mask and does not mutate the original value"] pub fn cast(self) -> Mask { - Mask(self.0.convert()) + // Safety: mask elements are integers + unsafe { Mask(core::intrinsics::simd::simd_as(self.0)) } } /// Tests the value of the specified element. @@ -232,7 +239,7 @@ where #[must_use = "method returns a new bool and does not mutate the original value"] pub unsafe fn test_unchecked(&self, index: usize) -> bool { // Safety: the caller must confirm this invariant - unsafe { self.0.test_unchecked(index) } + unsafe { T::eq(*self.0.as_array().get_unchecked(index), T::TRUE) } } /// Tests the value of the specified element. @@ -243,9 +250,7 @@ where #[must_use = "method returns a new bool and does not mutate the original value"] #[track_caller] pub fn test(&self, index: usize) -> bool { - assert!(index < N, "element index out of range"); - // Safety: the element index has been checked - unsafe { self.test_unchecked(index) } + T::eq(self.0[index], T::TRUE) } /// Sets the value of the specified element. @@ -256,7 +261,7 @@ where pub unsafe fn set_unchecked(&mut self, index: usize, value: bool) { // Safety: the caller must confirm this invariant unsafe { - self.0.set_unchecked(index, value); + *self.0.as_mut_array().get_unchecked_mut(index) = if value { T::TRUE } else { T::FALSE } } } @@ -267,35 +272,65 @@ where #[inline] #[track_caller] pub fn set(&mut self, index: usize, value: bool) { - assert!(index < N, "element index out of range"); - // Safety: the element index has been checked - unsafe { - self.set_unchecked(index, value); - } + self.0[index] = if value { T::TRUE } else { T::FALSE } } /// Returns true if any element is set, or false otherwise. #[inline] #[must_use = "method returns a new bool and does not mutate the original value"] pub fn any(self) -> bool { - self.0.any() + // Safety: `self` is a mask vector + unsafe { core::intrinsics::simd::simd_reduce_any(self.0) } } /// Returns true if all elements are set, or false otherwise. #[inline] #[must_use = "method returns a new bool and does not mutate the original value"] pub fn all(self) -> bool { - self.0.all() + // Safety: `self` is a mask vector + unsafe { core::intrinsics::simd::simd_reduce_all(self.0) } } /// Creates a bitmask from a mask. /// /// Each bit is set if the corresponding element in the mask is `true`. - /// If the mask contains more than 64 elements, the bitmask is truncated to the first 64. #[inline] #[must_use = "method returns a new integer and does not mutate the original value"] pub fn to_bitmask(self) -> u64 { - self.0.to_bitmask_integer() + const { + assert!(N <= 64, "number of elements can't be greater than 64"); + } + + #[inline] + unsafe fn to_bitmask_impl( + mask: Mask, + ) -> U + where + T: MaskElement, + { + let resized = mask.resize::(false); + + // Safety: `resized` is an integer vector with length M, which must match T + let bitmask: U = unsafe { core::intrinsics::simd::simd_bitmask(resized.0) }; + + // LLVM assumes bit order should match endianness + bitmask.fix_endianness() + } + + // TODO modify simd_bitmask to zero-extend output, making this unnecessary + if N <= 8 { + // Safety: bitmask matches length + unsafe { to_bitmask_impl::(self) as u64 } + } else if N <= 16 { + // Safety: bitmask matches length + unsafe { to_bitmask_impl::(self) as u64 } + } else if N <= 32 { + // Safety: bitmask matches length + unsafe { to_bitmask_impl::(self) as u64 } + } else { + // Safety: bitmask matches length + unsafe { to_bitmask_impl::(self) } + } } /// Creates a mask from a bitmask. @@ -305,7 +340,7 @@ where #[inline] #[must_use = "method returns a new mask and does not mutate the original value"] pub fn from_bitmask(bitmask: u64) -> Self { - Self(mask_impl::Mask::from_bitmask_integer(bitmask)) + Self(bitmask.select(Simd::splat(T::TRUE), Simd::splat(T::FALSE))) } /// Finds the index of the first set element. @@ -351,7 +386,7 @@ where // Safety: the input and output are integer vectors let index: Simd = unsafe { core::intrinsics::simd::simd_cast(index) }; - let masked_index = self.select(index, Self::splat(true).to_int()); + let masked_index = self.select(index, Self::splat(true).to_simd()); // Safety: the input and output are integer vectors let masked_index: Simd = @@ -376,7 +411,6 @@ where impl From<[bool; N]> for Mask where T: MaskElement, - LaneCount: SupportedLaneCount, { #[inline] fn from(array: [bool; N]) -> Self { @@ -387,7 +421,6 @@ where impl From> for [bool; N] where T: MaskElement, - LaneCount: SupportedLaneCount, { #[inline] fn from(vector: Mask) -> Self { @@ -398,7 +431,6 @@ where impl Default for Mask where T: MaskElement, - LaneCount: SupportedLaneCount, { #[inline] fn default() -> Self { @@ -409,7 +441,6 @@ where impl PartialEq for Mask where T: MaskElement + PartialEq, - LaneCount: SupportedLaneCount, { #[inline] fn eq(&self, other: &Self) -> bool { @@ -420,7 +451,6 @@ where impl PartialOrd for Mask where T: MaskElement + PartialOrd, - LaneCount: SupportedLaneCount, { #[inline] fn partial_cmp(&self, other: &Self) -> Option { @@ -431,7 +461,6 @@ where impl fmt::Debug for Mask where T: MaskElement + fmt::Debug, - LaneCount: SupportedLaneCount, { #[inline] fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { @@ -444,19 +473,18 @@ where impl core::ops::BitAnd for Mask where T: MaskElement, - LaneCount: SupportedLaneCount, { type Output = Self; #[inline] fn bitand(self, rhs: Self) -> Self { - Self(self.0 & rhs.0) + // Safety: `self` is an integer vector + unsafe { Self(core::intrinsics::simd::simd_and(self.0, rhs.0)) } } } impl core::ops::BitAnd for Mask where T: MaskElement, - LaneCount: SupportedLaneCount, { type Output = Self; #[inline] @@ -468,7 +496,6 @@ where impl core::ops::BitAnd> for bool where T: MaskElement, - LaneCount: SupportedLaneCount, { type Output = Mask; #[inline] @@ -480,19 +507,18 @@ where impl core::ops::BitOr for Mask where T: MaskElement, - LaneCount: SupportedLaneCount, { type Output = Self; #[inline] fn bitor(self, rhs: Self) -> Self { - Self(self.0 | rhs.0) + // Safety: `self` is an integer vector + unsafe { Self(core::intrinsics::simd::simd_or(self.0, rhs.0)) } } } impl core::ops::BitOr for Mask where T: MaskElement, - LaneCount: SupportedLaneCount, { type Output = Self; #[inline] @@ -504,7 +530,6 @@ where impl core::ops::BitOr> for bool where T: MaskElement, - LaneCount: SupportedLaneCount, { type Output = Mask; #[inline] @@ -516,19 +541,18 @@ where impl core::ops::BitXor for Mask where T: MaskElement, - LaneCount: SupportedLaneCount, { type Output = Self; #[inline] fn bitxor(self, rhs: Self) -> Self::Output { - Self(self.0 ^ rhs.0) + // Safety: `self` is an integer vector + unsafe { Self(core::intrinsics::simd::simd_xor(self.0, rhs.0)) } } } impl core::ops::BitXor for Mask where T: MaskElement, - LaneCount: SupportedLaneCount, { type Output = Self; #[inline] @@ -540,7 +564,6 @@ where impl core::ops::BitXor> for bool where T: MaskElement, - LaneCount: SupportedLaneCount, { type Output = Mask; #[inline] @@ -552,30 +575,27 @@ where impl core::ops::Not for Mask where T: MaskElement, - LaneCount: SupportedLaneCount, { type Output = Mask; #[inline] fn not(self) -> Self::Output { - Self(!self.0) + Self::splat(true) ^ self } } impl core::ops::BitAndAssign for Mask where T: MaskElement, - LaneCount: SupportedLaneCount, { #[inline] fn bitand_assign(&mut self, rhs: Self) { - self.0 = self.0 & rhs.0; + *self = *self & rhs; } } impl core::ops::BitAndAssign for Mask where T: MaskElement, - LaneCount: SupportedLaneCount, { #[inline] fn bitand_assign(&mut self, rhs: bool) { @@ -586,18 +606,16 @@ where impl core::ops::BitOrAssign for Mask where T: MaskElement, - LaneCount: SupportedLaneCount, { #[inline] fn bitor_assign(&mut self, rhs: Self) { - self.0 = self.0 | rhs.0; + *self = *self | rhs; } } impl core::ops::BitOrAssign for Mask where T: MaskElement, - LaneCount: SupportedLaneCount, { #[inline] fn bitor_assign(&mut self, rhs: bool) { @@ -608,18 +626,16 @@ where impl core::ops::BitXorAssign for Mask where T: MaskElement, - LaneCount: SupportedLaneCount, { #[inline] fn bitxor_assign(&mut self, rhs: Self) { - self.0 = self.0 ^ rhs.0; + *self = *self ^ rhs; } } impl core::ops::BitXorAssign for Mask where T: MaskElement, - LaneCount: SupportedLaneCount, { #[inline] fn bitxor_assign(&mut self, rhs: bool) { @@ -631,8 +647,6 @@ macro_rules! impl_from { { $from:ty => $($to:ty),* } => { $( impl From> for Mask<$to, N> - where - LaneCount: SupportedLaneCount, { #[inline] fn from(value: Mask<$from, N>) -> Self { diff --git a/library/portable-simd/crates/core_simd/src/masks/bitmask.rs b/library/portable-simd/crates/core_simd/src/masks/bitmask.rs deleted file mode 100644 index 32d37b553392..000000000000 --- a/library/portable-simd/crates/core_simd/src/masks/bitmask.rs +++ /dev/null @@ -1,228 +0,0 @@ -#![allow(unused_imports)] -use super::MaskElement; -use crate::simd::{LaneCount, Simd, SupportedLaneCount}; -use core::marker::PhantomData; - -/// A mask where each lane is represented by a single bit. -#[repr(transparent)] -pub(crate) struct Mask( - as SupportedLaneCount>::BitMask, - PhantomData, -) -where - T: MaskElement, - LaneCount: SupportedLaneCount; - -impl Copy for Mask -where - T: MaskElement, - LaneCount: SupportedLaneCount, -{ -} - -impl Clone for Mask -where - T: MaskElement, - LaneCount: SupportedLaneCount, -{ - #[inline] - fn clone(&self) -> Self { - *self - } -} - -impl PartialEq for Mask -where - T: MaskElement, - LaneCount: SupportedLaneCount, -{ - #[inline] - fn eq(&self, other: &Self) -> bool { - self.0.as_ref() == other.0.as_ref() - } -} - -impl PartialOrd for Mask -where - T: MaskElement, - LaneCount: SupportedLaneCount, -{ - #[inline] - fn partial_cmp(&self, other: &Self) -> Option { - self.0.as_ref().partial_cmp(other.0.as_ref()) - } -} - -impl Eq for Mask -where - T: MaskElement, - LaneCount: SupportedLaneCount, -{ -} - -impl Ord for Mask -where - T: MaskElement, - LaneCount: SupportedLaneCount, -{ - #[inline] - fn cmp(&self, other: &Self) -> core::cmp::Ordering { - self.0.as_ref().cmp(other.0.as_ref()) - } -} - -impl Mask -where - T: MaskElement, - LaneCount: SupportedLaneCount, -{ - #[inline] - #[must_use = "method returns a new mask and does not mutate the original value"] - pub(crate) fn splat(value: bool) -> Self { - let mut mask = as SupportedLaneCount>::BitMask::default(); - if value { - mask.as_mut().fill(u8::MAX) - } else { - mask.as_mut().fill(u8::MIN) - } - if N % 8 > 0 { - *mask.as_mut().last_mut().unwrap() &= u8::MAX >> (8 - N % 8); - } - Self(mask, PhantomData) - } - - #[inline] - #[must_use = "method returns a new bool and does not mutate the original value"] - pub(crate) unsafe fn test_unchecked(&self, lane: usize) -> bool { - (self.0.as_ref()[lane / 8] >> (lane % 8)) & 0x1 > 0 - } - - #[inline] - pub(crate) unsafe fn set_unchecked(&mut self, lane: usize, value: bool) { - unsafe { - self.0.as_mut()[lane / 8] ^= ((value ^ self.test_unchecked(lane)) as u8) << (lane % 8) - } - } - - #[inline] - #[must_use = "method returns a new vector and does not mutate the original value"] - pub(crate) fn to_int(self) -> Simd { - unsafe { - core::intrinsics::simd::simd_select_bitmask( - self.0, - Simd::splat(T::TRUE), - Simd::splat(T::FALSE), - ) - } - } - - #[inline] - #[must_use = "method returns a new mask and does not mutate the original value"] - pub(crate) unsafe fn from_int_unchecked(value: Simd) -> Self { - unsafe { Self(core::intrinsics::simd::simd_bitmask(value), PhantomData) } - } - - #[inline] - pub(crate) fn to_bitmask_integer(self) -> u64 { - let mut bitmask = [0u8; 8]; - bitmask[..self.0.as_ref().len()].copy_from_slice(self.0.as_ref()); - u64::from_ne_bytes(bitmask) - } - - #[inline] - pub(crate) fn from_bitmask_integer(bitmask: u64) -> Self { - let mut bytes = as SupportedLaneCount>::BitMask::default(); - let len = bytes.as_mut().len(); - bytes - .as_mut() - .copy_from_slice(&bitmask.to_ne_bytes()[..len]); - Self(bytes, PhantomData) - } - - #[inline] - #[must_use = "method returns a new mask and does not mutate the original value"] - pub(crate) fn convert(self) -> Mask - where - U: MaskElement, - { - // Safety: bitmask layout does not depend on the element width - unsafe { core::mem::transmute_copy(&self) } - } - - #[inline] - #[must_use = "method returns a new bool and does not mutate the original value"] - pub(crate) fn any(self) -> bool { - self != Self::splat(false) - } - - #[inline] - #[must_use = "method returns a new bool and does not mutate the original value"] - pub(crate) fn all(self) -> bool { - self == Self::splat(true) - } -} - -impl core::ops::BitAnd for Mask -where - T: MaskElement, - LaneCount: SupportedLaneCount, - as SupportedLaneCount>::BitMask: AsRef<[u8]> + AsMut<[u8]>, -{ - type Output = Self; - #[inline] - fn bitand(mut self, rhs: Self) -> Self { - for (l, r) in self.0.as_mut().iter_mut().zip(rhs.0.as_ref().iter()) { - *l &= r; - } - self - } -} - -impl core::ops::BitOr for Mask -where - T: MaskElement, - LaneCount: SupportedLaneCount, - as SupportedLaneCount>::BitMask: AsRef<[u8]> + AsMut<[u8]>, -{ - type Output = Self; - #[inline] - fn bitor(mut self, rhs: Self) -> Self { - for (l, r) in self.0.as_mut().iter_mut().zip(rhs.0.as_ref().iter()) { - *l |= r; - } - self - } -} - -impl core::ops::BitXor for Mask -where - T: MaskElement, - LaneCount: SupportedLaneCount, -{ - type Output = Self; - #[inline] - fn bitxor(mut self, rhs: Self) -> Self::Output { - for (l, r) in self.0.as_mut().iter_mut().zip(rhs.0.as_ref().iter()) { - *l ^= r; - } - self - } -} - -impl core::ops::Not for Mask -where - T: MaskElement, - LaneCount: SupportedLaneCount, -{ - type Output = Self; - #[inline] - fn not(mut self) -> Self::Output { - for x in self.0.as_mut() { - *x = !*x; - } - if N % 8 > 0 { - *self.0.as_mut().last_mut().unwrap() &= u8::MAX >> (8 - N % 8); - } - self - } -} diff --git a/library/portable-simd/crates/core_simd/src/masks/full_masks.rs b/library/portable-simd/crates/core_simd/src/masks/full_masks.rs deleted file mode 100644 index 4e98db4070a9..000000000000 --- a/library/portable-simd/crates/core_simd/src/masks/full_masks.rs +++ /dev/null @@ -1,296 +0,0 @@ -//! Masks that take up full SIMD vector registers. - -use crate::simd::{LaneCount, MaskElement, Simd, SupportedLaneCount}; - -#[repr(transparent)] -pub(crate) struct Mask(Simd) -where - T: MaskElement, - LaneCount: SupportedLaneCount; - -impl Copy for Mask -where - T: MaskElement, - LaneCount: SupportedLaneCount, -{ -} - -impl Clone for Mask -where - T: MaskElement, - LaneCount: SupportedLaneCount, -{ - #[inline] - fn clone(&self) -> Self { - *self - } -} - -impl PartialEq for Mask -where - T: MaskElement + PartialEq, - LaneCount: SupportedLaneCount, -{ - #[inline] - fn eq(&self, other: &Self) -> bool { - self.0.eq(&other.0) - } -} - -impl PartialOrd for Mask -where - T: MaskElement + PartialOrd, - LaneCount: SupportedLaneCount, -{ - #[inline] - fn partial_cmp(&self, other: &Self) -> Option { - self.0.partial_cmp(&other.0) - } -} - -impl Eq for Mask -where - T: MaskElement + Eq, - LaneCount: SupportedLaneCount, -{ -} - -impl Ord for Mask -where - T: MaskElement + Ord, - LaneCount: SupportedLaneCount, -{ - #[inline] - fn cmp(&self, other: &Self) -> core::cmp::Ordering { - self.0.cmp(&other.0) - } -} - -// Used for bitmask bit order workaround -pub(crate) trait ReverseBits { - // Reverse the least significant `n` bits of `self`. - // (Remaining bits must be 0.) - fn reverse_bits(self, n: usize) -> Self; -} - -macro_rules! impl_reverse_bits { - { $($int:ty),* } => { - $( - impl ReverseBits for $int { - #[inline(always)] - fn reverse_bits(self, n: usize) -> Self { - let rev = <$int>::reverse_bits(self); - let bitsize = size_of::<$int>() * 8; - if n < bitsize { - // Shift things back to the right - rev >> (bitsize - n) - } else { - rev - } - } - } - )* - } -} - -impl_reverse_bits! { u8, u16, u32, u64 } - -impl Mask -where - T: MaskElement, - LaneCount: SupportedLaneCount, -{ - #[inline] - #[must_use = "method returns a new mask and does not mutate the original value"] - pub(crate) fn splat(value: bool) -> Self { - Self(Simd::splat(if value { T::TRUE } else { T::FALSE })) - } - - #[inline] - #[must_use = "method returns a new bool and does not mutate the original value"] - pub(crate) unsafe fn test_unchecked(&self, lane: usize) -> bool { - T::eq(self.0[lane], T::TRUE) - } - - #[inline] - pub(crate) unsafe fn set_unchecked(&mut self, lane: usize, value: bool) { - self.0[lane] = if value { T::TRUE } else { T::FALSE } - } - - #[inline] - #[must_use = "method returns a new vector and does not mutate the original value"] - pub(crate) fn to_int(self) -> Simd { - self.0 - } - - #[inline] - #[must_use = "method returns a new mask and does not mutate the original value"] - pub(crate) unsafe fn from_int_unchecked(value: Simd) -> Self { - Self(value) - } - - #[inline] - #[must_use = "method returns a new mask and does not mutate the original value"] - pub(crate) fn convert(self) -> Mask - where - U: MaskElement, - { - // Safety: masks are simply integer vectors of 0 and -1, and we can cast the element type. - unsafe { Mask(core::intrinsics::simd::simd_cast(self.0)) } - } - - #[inline] - unsafe fn to_bitmask_impl(self) -> U - where - LaneCount: SupportedLaneCount, - { - let resized = self.to_int().resize::(T::FALSE); - - // Safety: `resized` is an integer vector with length M, which must match T - let bitmask: U = unsafe { core::intrinsics::simd::simd_bitmask(resized) }; - - // LLVM assumes bit order should match endianness - if cfg!(target_endian = "big") { - bitmask.reverse_bits(M) - } else { - bitmask - } - } - - #[inline] - unsafe fn from_bitmask_impl(bitmask: U) -> Self - where - LaneCount: SupportedLaneCount, - { - // LLVM assumes bit order should match endianness - let bitmask = if cfg!(target_endian = "big") { - bitmask.reverse_bits(M) - } else { - bitmask - }; - - // SAFETY: `mask` is the correct bitmask type for a u64 bitmask - let mask: Simd = unsafe { - core::intrinsics::simd::simd_select_bitmask( - bitmask, - Simd::::splat(T::TRUE), - Simd::::splat(T::FALSE), - ) - }; - - // SAFETY: `mask` only contains `T::TRUE` or `T::FALSE` - unsafe { Self::from_int_unchecked(mask.resize::(T::FALSE)) } - } - - #[inline] - pub(crate) fn to_bitmask_integer(self) -> u64 { - // TODO modify simd_bitmask to zero-extend output, making this unnecessary - if N <= 8 { - // Safety: bitmask matches length - unsafe { self.to_bitmask_impl::() as u64 } - } else if N <= 16 { - // Safety: bitmask matches length - unsafe { self.to_bitmask_impl::() as u64 } - } else if N <= 32 { - // Safety: bitmask matches length - unsafe { self.to_bitmask_impl::() as u64 } - } else { - // Safety: bitmask matches length - unsafe { self.to_bitmask_impl::() } - } - } - - #[inline] - pub(crate) fn from_bitmask_integer(bitmask: u64) -> Self { - // TODO modify simd_bitmask_select to truncate input, making this unnecessary - if N <= 8 { - // Safety: bitmask matches length - unsafe { Self::from_bitmask_impl::(bitmask as u8) } - } else if N <= 16 { - // Safety: bitmask matches length - unsafe { Self::from_bitmask_impl::(bitmask as u16) } - } else if N <= 32 { - // Safety: bitmask matches length - unsafe { Self::from_bitmask_impl::(bitmask as u32) } - } else { - // Safety: bitmask matches length - unsafe { Self::from_bitmask_impl::(bitmask) } - } - } - - #[inline] - #[must_use = "method returns a new bool and does not mutate the original value"] - pub(crate) fn any(self) -> bool { - // Safety: use `self` as an integer vector - unsafe { core::intrinsics::simd::simd_reduce_any(self.to_int()) } - } - - #[inline] - #[must_use = "method returns a new bool and does not mutate the original value"] - pub(crate) fn all(self) -> bool { - // Safety: use `self` as an integer vector - unsafe { core::intrinsics::simd::simd_reduce_all(self.to_int()) } - } -} - -impl From> for Simd -where - T: MaskElement, - LaneCount: SupportedLaneCount, -{ - #[inline] - fn from(value: Mask) -> Self { - value.0 - } -} - -impl core::ops::BitAnd for Mask -where - T: MaskElement, - LaneCount: SupportedLaneCount, -{ - type Output = Self; - #[inline] - fn bitand(self, rhs: Self) -> Self { - // Safety: `self` is an integer vector - unsafe { Self(core::intrinsics::simd::simd_and(self.0, rhs.0)) } - } -} - -impl core::ops::BitOr for Mask -where - T: MaskElement, - LaneCount: SupportedLaneCount, -{ - type Output = Self; - #[inline] - fn bitor(self, rhs: Self) -> Self { - // Safety: `self` is an integer vector - unsafe { Self(core::intrinsics::simd::simd_or(self.0, rhs.0)) } - } -} - -impl core::ops::BitXor for Mask -where - T: MaskElement, - LaneCount: SupportedLaneCount, -{ - type Output = Self; - #[inline] - fn bitxor(self, rhs: Self) -> Self { - // Safety: `self` is an integer vector - unsafe { Self(core::intrinsics::simd::simd_xor(self.0, rhs.0)) } - } -} - -impl core::ops::Not for Mask -where - T: MaskElement, - LaneCount: SupportedLaneCount, -{ - type Output = Self; - #[inline] - fn not(self) -> Self::Output { - Self::splat(true) ^ self - } -} diff --git a/library/portable-simd/crates/core_simd/src/mod.rs b/library/portable-simd/crates/core_simd/src/mod.rs index 45b1a0f97514..5f635d80a178 100644 --- a/library/portable-simd/crates/core_simd/src/mod.rs +++ b/library/portable-simd/crates/core_simd/src/mod.rs @@ -5,7 +5,6 @@ mod alias; mod cast; mod fmt; mod iter; -mod lane_count; mod masks; mod ops; mod select; @@ -27,8 +26,8 @@ pub mod simd { pub use crate::core_simd::alias::*; pub use crate::core_simd::cast::*; - pub use crate::core_simd::lane_count::{LaneCount, SupportedLaneCount}; pub use crate::core_simd::masks::*; + pub use crate::core_simd::select::*; pub use crate::core_simd::swizzle::*; pub use crate::core_simd::to_bytes::ToBytes; pub use crate::core_simd::vector::*; diff --git a/library/portable-simd/crates/core_simd/src/ops.rs b/library/portable-simd/crates/core_simd/src/ops.rs index f36e8d01a73b..eb6601f73483 100644 --- a/library/portable-simd/crates/core_simd/src/ops.rs +++ b/library/portable-simd/crates/core_simd/src/ops.rs @@ -1,4 +1,4 @@ -use crate::simd::{LaneCount, Simd, SimdElement, SupportedLaneCount, cmp::SimdPartialEq}; +use crate::simd::{Select, Simd, SimdElement, cmp::SimdPartialEq}; use core::ops::{Add, Mul}; use core::ops::{BitAnd, BitOr, BitXor}; use core::ops::{Div, Rem, Sub}; @@ -12,7 +12,6 @@ mod unary; impl core::ops::Index for Simd where T: SimdElement, - LaneCount: SupportedLaneCount, I: core::slice::SliceIndex<[T]>, { type Output = I::Output; @@ -25,7 +24,6 @@ where impl core::ops::IndexMut for Simd where T: SimdElement, - LaneCount: SupportedLaneCount, I: core::slice::SliceIndex<[T]>, { #[inline] @@ -130,7 +128,6 @@ macro_rules! for_base_types { impl $op for Simd<$scalar, N> where $scalar: SimdElement, - LaneCount: SupportedLaneCount, { type Output = $out; diff --git a/library/portable-simd/crates/core_simd/src/ops/assign.rs b/library/portable-simd/crates/core_simd/src/ops/assign.rs index d21d867de26d..c1830c35df77 100644 --- a/library/portable-simd/crates/core_simd/src/ops/assign.rs +++ b/library/portable-simd/crates/core_simd/src/ops/assign.rs @@ -21,7 +21,6 @@ macro_rules! assign_ops { where Self: $trait, T: SimdElement, - LaneCount: SupportedLaneCount, { #[inline] fn $assign_call(&mut self, rhs: U) { diff --git a/library/portable-simd/crates/core_simd/src/ops/deref.rs b/library/portable-simd/crates/core_simd/src/ops/deref.rs index 913cbbe977c4..360b83c40346 100644 --- a/library/portable-simd/crates/core_simd/src/ops/deref.rs +++ b/library/portable-simd/crates/core_simd/src/ops/deref.rs @@ -13,7 +13,6 @@ macro_rules! deref_lhs { where T: SimdElement, $simd: $trait<$simd, Output = $simd>, - LaneCount: SupportedLaneCount, { type Output = Simd; @@ -33,7 +32,6 @@ macro_rules! deref_rhs { where T: SimdElement, $simd: $trait<$simd, Output = $simd>, - LaneCount: SupportedLaneCount, { type Output = Simd; @@ -64,7 +62,6 @@ macro_rules! deref_ops { where T: SimdElement, $simd: $trait<$simd, Output = $simd>, - LaneCount: SupportedLaneCount, { type Output = $simd; diff --git a/library/portable-simd/crates/core_simd/src/ops/shift_scalar.rs b/library/portable-simd/crates/core_simd/src/ops/shift_scalar.rs index f5115a5a5e93..7ca83dc40f61 100644 --- a/library/portable-simd/crates/core_simd/src/ops/shift_scalar.rs +++ b/library/portable-simd/crates/core_simd/src/ops/shift_scalar.rs @@ -1,13 +1,11 @@ // Shift operations uniquely typically only have a scalar on the right-hand side. // Here, we implement shifts for scalar RHS arguments. -use crate::simd::{LaneCount, Simd, SupportedLaneCount}; +use crate::simd::Simd; macro_rules! impl_splatted_shifts { { impl $trait:ident :: $trait_fn:ident for $ty:ty } => { impl core::ops::$trait<$ty> for Simd<$ty, N> - where - LaneCount: SupportedLaneCount, { type Output = Self; #[inline] @@ -17,8 +15,6 @@ macro_rules! impl_splatted_shifts { } impl core::ops::$trait<&$ty> for Simd<$ty, N> - where - LaneCount: SupportedLaneCount, { type Output = Self; #[inline] @@ -28,8 +24,6 @@ macro_rules! impl_splatted_shifts { } impl<'lhs, const N: usize> core::ops::$trait<$ty> for &'lhs Simd<$ty, N> - where - LaneCount: SupportedLaneCount, { type Output = Simd<$ty, N>; #[inline] @@ -39,8 +33,6 @@ macro_rules! impl_splatted_shifts { } impl<'lhs, const N: usize> core::ops::$trait<&$ty> for &'lhs Simd<$ty, N> - where - LaneCount: SupportedLaneCount, { type Output = Simd<$ty, N>; #[inline] diff --git a/library/portable-simd/crates/core_simd/src/ops/unary.rs b/library/portable-simd/crates/core_simd/src/ops/unary.rs index 412a5b801171..e1c06167f979 100644 --- a/library/portable-simd/crates/core_simd/src/ops/unary.rs +++ b/library/portable-simd/crates/core_simd/src/ops/unary.rs @@ -1,4 +1,4 @@ -use crate::simd::{LaneCount, Simd, SimdElement, SupportedLaneCount}; +use crate::simd::{Simd, SimdElement}; use core::ops::{Neg, Not}; // unary ops macro_rules! neg { @@ -6,7 +6,6 @@ macro_rules! neg { $(impl Neg for Simd<$scalar, N> where $scalar: SimdElement, - LaneCount: SupportedLaneCount, { type Output = Self; @@ -40,7 +39,6 @@ macro_rules! not { $(impl Not for Simd<$scalar, N> where $scalar: SimdElement, - LaneCount: SupportedLaneCount, { type Output = Self; diff --git a/library/portable-simd/crates/core_simd/src/select.rs b/library/portable-simd/crates/core_simd/src/select.rs index f33aa261a928..404f54d8f382 100644 --- a/library/portable-simd/crates/core_simd/src/select.rs +++ b/library/portable-simd/crates/core_simd/src/select.rs @@ -1,54 +1,155 @@ -use crate::simd::{LaneCount, Mask, MaskElement, Simd, SimdElement, SupportedLaneCount}; +use crate::simd::{FixEndianness, Mask, MaskElement, Simd, SimdElement}; -impl Mask +/// Choose elements from two vectors using a mask. +/// +/// For each element in the mask, choose the corresponding element from `true_values` if +/// that element mask is true, and `false_values` if that element mask is false. +/// +/// If the mask is `u64`, it's treated as a bitmask with the least significant bit +/// corresponding to the first element. +/// +/// # Examples +/// +/// ## Selecting values from `Simd` +/// ``` +/// # #![feature(portable_simd)] +/// # #[cfg(feature = "as_crate")] use core_simd::simd; +/// # #[cfg(not(feature = "as_crate"))] use core::simd; +/// # use simd::{Simd, Mask, Select}; +/// let a = Simd::from_array([0, 1, 2, 3]); +/// let b = Simd::from_array([4, 5, 6, 7]); +/// let mask = Mask::::from_array([true, false, false, true]); +/// let c = mask.select(a, b); +/// assert_eq!(c.to_array(), [0, 5, 6, 3]); +/// ``` +/// +/// ## Selecting values from `Mask` +/// ``` +/// # #![feature(portable_simd)] +/// # #[cfg(feature = "as_crate")] use core_simd::simd; +/// # #[cfg(not(feature = "as_crate"))] use core::simd; +/// # use simd::{Mask, Select}; +/// let a = Mask::::from_array([true, true, false, false]); +/// let b = Mask::::from_array([false, false, true, true]); +/// let mask = Mask::::from_array([true, false, false, true]); +/// let c = mask.select(a, b); +/// assert_eq!(c.to_array(), [true, false, true, false]); +/// ``` +/// +/// ## Selecting with a bitmask +/// ``` +/// # #![feature(portable_simd)] +/// # #[cfg(feature = "as_crate")] use core_simd::simd; +/// # #[cfg(not(feature = "as_crate"))] use core::simd; +/// # use simd::{Mask, Select}; +/// let a = Mask::::from_array([true, true, false, false]); +/// let b = Mask::::from_array([false, false, true, true]); +/// let mask = 0b1001; +/// let c = mask.select(a, b); +/// assert_eq!(c.to_array(), [true, false, true, false]); +/// ``` +pub trait Select { + /// Choose elements + fn select(self, true_values: T, false_values: T) -> T; +} + +impl Select> for Mask where - T: MaskElement, - LaneCount: SupportedLaneCount, + T: SimdElement, + U: MaskElement, { - /// Choose elements from two vectors. - /// - /// For each element in the mask, choose the corresponding element from `true_values` if - /// that element mask is true, and `false_values` if that element mask is false. - /// - /// # Examples - /// ``` - /// # #![feature(portable_simd)] - /// # use core::simd::{Simd, Mask}; - /// let a = Simd::from_array([0, 1, 2, 3]); - /// let b = Simd::from_array([4, 5, 6, 7]); - /// let mask = Mask::from_array([true, false, false, true]); - /// let c = mask.select(a, b); - /// assert_eq!(c.to_array(), [0, 5, 6, 3]); - /// ``` #[inline] - #[must_use = "method returns a new vector and does not mutate the original inputs"] - pub fn select(self, true_values: Simd, false_values: Simd) -> Simd - where - U: SimdElement, - { - // Safety: The mask has been cast to a vector of integers, - // and the operands to select between are vectors of the same type and length. - unsafe { core::intrinsics::simd::simd_select(self.to_int(), true_values, false_values) } - } - - /// Choose elements from two masks. - /// - /// For each element in the mask, choose the corresponding element from `true_values` if - /// that element mask is true, and `false_values` if that element mask is false. - /// - /// # Examples - /// ``` - /// # #![feature(portable_simd)] - /// # use core::simd::Mask; - /// let a = Mask::::from_array([true, true, false, false]); - /// let b = Mask::::from_array([false, false, true, true]); - /// let mask = Mask::::from_array([true, false, false, true]); - /// let c = mask.select_mask(a, b); - /// assert_eq!(c.to_array(), [true, false, true, false]); - /// ``` - #[inline] - #[must_use = "method returns a new mask and does not mutate the original inputs"] - pub fn select_mask(self, true_values: Self, false_values: Self) -> Self { - self & true_values | !self & false_values + fn select(self, true_values: Simd, false_values: Simd) -> Simd { + // Safety: + // simd_as between masks is always safe (they're vectors of ints). + // simd_select uses a mask that matches the width and number of elements + unsafe { + let mask: Simd = core::intrinsics::simd::simd_as(self.to_simd()); + core::intrinsics::simd::simd_select(mask, true_values, false_values) + } + } +} + +impl Select> for u64 +where + T: SimdElement, +{ + #[inline] + fn select(self, true_values: Simd, false_values: Simd) -> Simd { + const { + assert!(N <= 64, "number of elements can't be greater than 64"); + } + + #[inline] + unsafe fn select_impl( + bitmask: U, + true_values: Simd, + false_values: Simd, + ) -> Simd + where + T: SimdElement, + { + let default = true_values[0]; + let true_values = true_values.resize::(default); + let false_values = false_values.resize::(default); + + // LLVM assumes bit order should match endianness + let bitmask = bitmask.fix_endianness(); + + // Safety: the caller guarantees that the size of U matches M + let selected = unsafe { + core::intrinsics::simd::simd_select_bitmask(bitmask, true_values, false_values) + }; + + selected.resize::(default) + } + + // TODO modify simd_bitmask_select to truncate input, making this unnecessary + if N <= 8 { + let bitmask = self as u8; + // Safety: bitmask matches length + unsafe { select_impl::(bitmask, true_values, false_values) } + } else if N <= 16 { + let bitmask = self as u16; + // Safety: bitmask matches length + unsafe { select_impl::(bitmask, true_values, false_values) } + } else if N <= 32 { + let bitmask = self as u32; + // Safety: bitmask matches length + unsafe { select_impl::(bitmask, true_values, false_values) } + } else { + let bitmask = self; + // Safety: bitmask matches length + unsafe { select_impl::(bitmask, true_values, false_values) } + } + } +} + +impl Select> for Mask +where + T: MaskElement, + U: MaskElement, +{ + #[inline] + fn select(self, true_values: Mask, false_values: Mask) -> Mask { + let selected: Simd = + Select::select(self, true_values.to_simd(), false_values.to_simd()); + + // Safety: all values come from masks + unsafe { Mask::from_simd_unchecked(selected) } + } +} + +impl Select> for u64 +where + T: MaskElement, +{ + #[inline] + fn select(self, true_values: Mask, false_values: Mask) -> Mask { + let selected: Simd = + Select::select(self, true_values.to_simd(), false_values.to_simd()); + + // Safety: all values come from masks + unsafe { Mask::from_simd_unchecked(selected) } } } diff --git a/library/portable-simd/crates/core_simd/src/simd/cmp/eq.rs b/library/portable-simd/crates/core_simd/src/simd/cmp/eq.rs index 2312ba401fa7..d553d6c040c9 100644 --- a/library/portable-simd/crates/core_simd/src/simd/cmp/eq.rs +++ b/library/portable-simd/crates/core_simd/src/simd/cmp/eq.rs @@ -1,5 +1,5 @@ use crate::simd::{ - LaneCount, Mask, Simd, SimdElement, SupportedLaneCount, + Mask, Simd, SimdElement, ptr::{SimdConstPtr, SimdMutPtr}, }; @@ -21,8 +21,6 @@ macro_rules! impl_number { { $($number:ty),* } => { $( impl SimdPartialEq for Simd<$number, N> - where - LaneCount: SupportedLaneCount, { type Mask = Mask<<$number as SimdElement>::Mask, N>; @@ -30,14 +28,14 @@ macro_rules! impl_number { fn simd_eq(self, other: Self) -> Self::Mask { // Safety: `self` is a vector, and the result of the comparison // is always a valid mask. - unsafe { Mask::from_int_unchecked(core::intrinsics::simd::simd_eq(self, other)) } + unsafe { Mask::from_simd_unchecked(core::intrinsics::simd::simd_eq(self, other)) } } #[inline] fn simd_ne(self, other: Self) -> Self::Mask { // Safety: `self` is a vector, and the result of the comparison // is always a valid mask. - unsafe { Mask::from_int_unchecked(core::intrinsics::simd::simd_ne(self, other)) } + unsafe { Mask::from_simd_unchecked(core::intrinsics::simd::simd_ne(self, other)) } } } )* @@ -50,8 +48,6 @@ macro_rules! impl_mask { { $($integer:ty),* } => { $( impl SimdPartialEq for Mask<$integer, N> - where - LaneCount: SupportedLaneCount, { type Mask = Self; @@ -59,14 +55,14 @@ macro_rules! impl_mask { fn simd_eq(self, other: Self) -> Self::Mask { // Safety: `self` is a vector, and the result of the comparison // is always a valid mask. - unsafe { Self::from_int_unchecked(core::intrinsics::simd::simd_eq(self.to_int(), other.to_int())) } + unsafe { Self::from_simd_unchecked(core::intrinsics::simd::simd_eq(self.to_simd(), other.to_simd())) } } #[inline] fn simd_ne(self, other: Self) -> Self::Mask { // Safety: `self` is a vector, and the result of the comparison // is always a valid mask. - unsafe { Self::from_int_unchecked(core::intrinsics::simd::simd_ne(self.to_int(), other.to_int())) } + unsafe { Self::from_simd_unchecked(core::intrinsics::simd::simd_ne(self.to_simd(), other.to_simd())) } } } )* @@ -75,10 +71,7 @@ macro_rules! impl_mask { impl_mask! { i8, i16, i32, i64, isize } -impl SimdPartialEq for Simd<*const T, N> -where - LaneCount: SupportedLaneCount, -{ +impl SimdPartialEq for Simd<*const T, N> { type Mask = Mask; #[inline] @@ -92,10 +85,7 @@ where } } -impl SimdPartialEq for Simd<*mut T, N> -where - LaneCount: SupportedLaneCount, -{ +impl SimdPartialEq for Simd<*mut T, N> { type Mask = Mask; #[inline] diff --git a/library/portable-simd/crates/core_simd/src/simd/cmp/ord.rs b/library/portable-simd/crates/core_simd/src/simd/cmp/ord.rs index e813e7613032..5672fbbf54ca 100644 --- a/library/portable-simd/crates/core_simd/src/simd/cmp/ord.rs +++ b/library/portable-simd/crates/core_simd/src/simd/cmp/ord.rs @@ -1,5 +1,5 @@ use crate::simd::{ - LaneCount, Mask, Simd, SupportedLaneCount, + Mask, Select, Simd, cmp::SimdPartialEq, ptr::{SimdConstPtr, SimdMutPtr}, }; @@ -49,41 +49,37 @@ macro_rules! impl_integer { { $($integer:ty),* } => { $( impl SimdPartialOrd for Simd<$integer, N> - where - LaneCount: SupportedLaneCount, { #[inline] fn simd_lt(self, other: Self) -> Self::Mask { // Safety: `self` is a vector, and the result of the comparison // is always a valid mask. - unsafe { Mask::from_int_unchecked(core::intrinsics::simd::simd_lt(self, other)) } + unsafe { Mask::from_simd_unchecked(core::intrinsics::simd::simd_lt(self, other)) } } #[inline] fn simd_le(self, other: Self) -> Self::Mask { // Safety: `self` is a vector, and the result of the comparison // is always a valid mask. - unsafe { Mask::from_int_unchecked(core::intrinsics::simd::simd_le(self, other)) } + unsafe { Mask::from_simd_unchecked(core::intrinsics::simd::simd_le(self, other)) } } #[inline] fn simd_gt(self, other: Self) -> Self::Mask { // Safety: `self` is a vector, and the result of the comparison // is always a valid mask. - unsafe { Mask::from_int_unchecked(core::intrinsics::simd::simd_gt(self, other)) } + unsafe { Mask::from_simd_unchecked(core::intrinsics::simd::simd_gt(self, other)) } } #[inline] fn simd_ge(self, other: Self) -> Self::Mask { // Safety: `self` is a vector, and the result of the comparison // is always a valid mask. - unsafe { Mask::from_int_unchecked(core::intrinsics::simd::simd_ge(self, other)) } + unsafe { Mask::from_simd_unchecked(core::intrinsics::simd::simd_ge(self, other)) } } } impl SimdOrd for Simd<$integer, N> - where - LaneCount: SupportedLaneCount, { #[inline] fn simd_max(self, other: Self) -> Self { @@ -115,35 +111,33 @@ macro_rules! impl_float { { $($float:ty),* } => { $( impl SimdPartialOrd for Simd<$float, N> - where - LaneCount: SupportedLaneCount, { #[inline] fn simd_lt(self, other: Self) -> Self::Mask { // Safety: `self` is a vector, and the result of the comparison // is always a valid mask. - unsafe { Mask::from_int_unchecked(core::intrinsics::simd::simd_lt(self, other)) } + unsafe { Mask::from_simd_unchecked(core::intrinsics::simd::simd_lt(self, other)) } } #[inline] fn simd_le(self, other: Self) -> Self::Mask { // Safety: `self` is a vector, and the result of the comparison // is always a valid mask. - unsafe { Mask::from_int_unchecked(core::intrinsics::simd::simd_le(self, other)) } + unsafe { Mask::from_simd_unchecked(core::intrinsics::simd::simd_le(self, other)) } } #[inline] fn simd_gt(self, other: Self) -> Self::Mask { // Safety: `self` is a vector, and the result of the comparison // is always a valid mask. - unsafe { Mask::from_int_unchecked(core::intrinsics::simd::simd_gt(self, other)) } + unsafe { Mask::from_simd_unchecked(core::intrinsics::simd::simd_gt(self, other)) } } #[inline] fn simd_ge(self, other: Self) -> Self::Mask { // Safety: `self` is a vector, and the result of the comparison // is always a valid mask. - unsafe { Mask::from_int_unchecked(core::intrinsics::simd::simd_ge(self, other)) } + unsafe { Mask::from_simd_unchecked(core::intrinsics::simd::simd_ge(self, other)) } } } )* @@ -156,50 +150,46 @@ macro_rules! impl_mask { { $($integer:ty),* } => { $( impl SimdPartialOrd for Mask<$integer, N> - where - LaneCount: SupportedLaneCount, { #[inline] fn simd_lt(self, other: Self) -> Self::Mask { // Safety: `self` is a vector, and the result of the comparison // is always a valid mask. - unsafe { Self::from_int_unchecked(core::intrinsics::simd::simd_lt(self.to_int(), other.to_int())) } + unsafe { Self::from_simd_unchecked(core::intrinsics::simd::simd_lt(self.to_simd(), other.to_simd())) } } #[inline] fn simd_le(self, other: Self) -> Self::Mask { // Safety: `self` is a vector, and the result of the comparison // is always a valid mask. - unsafe { Self::from_int_unchecked(core::intrinsics::simd::simd_le(self.to_int(), other.to_int())) } + unsafe { Self::from_simd_unchecked(core::intrinsics::simd::simd_le(self.to_simd(), other.to_simd())) } } #[inline] fn simd_gt(self, other: Self) -> Self::Mask { // Safety: `self` is a vector, and the result of the comparison // is always a valid mask. - unsafe { Self::from_int_unchecked(core::intrinsics::simd::simd_gt(self.to_int(), other.to_int())) } + unsafe { Self::from_simd_unchecked(core::intrinsics::simd::simd_gt(self.to_simd(), other.to_simd())) } } #[inline] fn simd_ge(self, other: Self) -> Self::Mask { // Safety: `self` is a vector, and the result of the comparison // is always a valid mask. - unsafe { Self::from_int_unchecked(core::intrinsics::simd::simd_ge(self.to_int(), other.to_int())) } + unsafe { Self::from_simd_unchecked(core::intrinsics::simd::simd_ge(self.to_simd(), other.to_simd())) } } } impl SimdOrd for Mask<$integer, N> - where - LaneCount: SupportedLaneCount, { #[inline] fn simd_max(self, other: Self) -> Self { - self.simd_gt(other).select_mask(other, self) + self.simd_gt(other).select(other, self) } #[inline] fn simd_min(self, other: Self) -> Self { - self.simd_lt(other).select_mask(other, self) + self.simd_lt(other).select(other, self) } #[inline] @@ -218,10 +208,7 @@ macro_rules! impl_mask { impl_mask! { i8, i16, i32, i64, isize } -impl SimdPartialOrd for Simd<*const T, N> -where - LaneCount: SupportedLaneCount, -{ +impl SimdPartialOrd for Simd<*const T, N> { #[inline] fn simd_lt(self, other: Self) -> Self::Mask { self.addr().simd_lt(other.addr()) @@ -243,10 +230,7 @@ where } } -impl SimdOrd for Simd<*const T, N> -where - LaneCount: SupportedLaneCount, -{ +impl SimdOrd for Simd<*const T, N> { #[inline] fn simd_max(self, other: Self) -> Self { self.simd_lt(other).select(other, self) @@ -268,10 +252,7 @@ where } } -impl SimdPartialOrd for Simd<*mut T, N> -where - LaneCount: SupportedLaneCount, -{ +impl SimdPartialOrd for Simd<*mut T, N> { #[inline] fn simd_lt(self, other: Self) -> Self::Mask { self.addr().simd_lt(other.addr()) @@ -293,10 +274,7 @@ where } } -impl SimdOrd for Simd<*mut T, N> -where - LaneCount: SupportedLaneCount, -{ +impl SimdOrd for Simd<*mut T, N> { #[inline] fn simd_max(self, other: Self) -> Self { self.simd_lt(other).select(other, self) diff --git a/library/portable-simd/crates/core_simd/src/simd/num/float.rs b/library/portable-simd/crates/core_simd/src/simd/num/float.rs index b5972c47373b..efd7c2469512 100644 --- a/library/portable-simd/crates/core_simd/src/simd/num/float.rs +++ b/library/portable-simd/crates/core_simd/src/simd/num/float.rs @@ -1,6 +1,6 @@ use super::sealed::Sealed; use crate::simd::{ - LaneCount, Mask, Simd, SimdCast, SimdElement, SupportedLaneCount, + Mask, Select, Simd, SimdCast, SimdElement, cmp::{SimdPartialEq, SimdPartialOrd}, }; @@ -240,15 +240,9 @@ pub trait SimdFloat: Copy + Sealed { macro_rules! impl_trait { { $($ty:ty { bits: $bits_ty:ty, mask: $mask_ty:ty }),* } => { $( - impl Sealed for Simd<$ty, N> - where - LaneCount: SupportedLaneCount, - { - } + impl Sealed for Simd<$ty, N> {} impl SimdFloat for Simd<$ty, N> - where - LaneCount: SupportedLaneCount, { type Mask = Mask<<$mask_ty as SimdElement>::Mask, N>; type Scalar = $ty; diff --git a/library/portable-simd/crates/core_simd/src/simd/num/int.rs b/library/portable-simd/crates/core_simd/src/simd/num/int.rs index e7253313f036..eee54d396880 100644 --- a/library/portable-simd/crates/core_simd/src/simd/num/int.rs +++ b/library/portable-simd/crates/core_simd/src/simd/num/int.rs @@ -1,7 +1,6 @@ use super::sealed::Sealed; use crate::simd::{ - LaneCount, Mask, Simd, SimdCast, SimdElement, SupportedLaneCount, cmp::SimdOrd, - cmp::SimdPartialOrd, num::SimdUint, + Mask, Select, Simd, SimdCast, SimdElement, cmp::SimdOrd, cmp::SimdPartialOrd, num::SimdUint, }; /// Operations on SIMD vectors of signed integers. @@ -242,16 +241,9 @@ pub trait SimdInt: Copy + Sealed { macro_rules! impl_trait { { $($ty:ident ($unsigned:ident)),* } => { $( - impl Sealed for Simd<$ty, N> - where - LaneCount: SupportedLaneCount, - { - } + impl Sealed for Simd<$ty, N> {} - impl SimdInt for Simd<$ty, N> - where - LaneCount: SupportedLaneCount, - { + impl SimdInt for Simd<$ty, N> { type Mask = Mask<<$ty as SimdElement>::Mask, N>; type Scalar = $ty; type Unsigned = Simd<$unsigned, N>; diff --git a/library/portable-simd/crates/core_simd/src/simd/num/uint.rs b/library/portable-simd/crates/core_simd/src/simd/num/uint.rs index e3ba8658bd80..606107a1f06f 100644 --- a/library/portable-simd/crates/core_simd/src/simd/num/uint.rs +++ b/library/portable-simd/crates/core_simd/src/simd/num/uint.rs @@ -1,5 +1,5 @@ use super::sealed::Sealed; -use crate::simd::{LaneCount, Simd, SimdCast, SimdElement, SupportedLaneCount, cmp::SimdOrd}; +use crate::simd::{Simd, SimdCast, SimdElement, cmp::SimdOrd}; /// Operations on SIMD vectors of unsigned integers. pub trait SimdUint: Copy + Sealed { @@ -124,15 +124,9 @@ pub trait SimdUint: Copy + Sealed { macro_rules! impl_trait { { $($ty:ident ($signed:ident)),* } => { $( - impl Sealed for Simd<$ty, N> - where - LaneCount: SupportedLaneCount, - { - } + impl Sealed for Simd<$ty, N> {} impl SimdUint for Simd<$ty, N> - where - LaneCount: SupportedLaneCount, { type Scalar = $ty; type Cast = Simd; diff --git a/library/portable-simd/crates/core_simd/src/simd/ptr/const_ptr.rs b/library/portable-simd/crates/core_simd/src/simd/ptr/const_ptr.rs index 36452e7ae920..7ef9dc21373e 100644 --- a/library/portable-simd/crates/core_simd/src/simd/ptr/const_ptr.rs +++ b/library/portable-simd/crates/core_simd/src/simd/ptr/const_ptr.rs @@ -1,5 +1,5 @@ use super::sealed::Sealed; -use crate::simd::{LaneCount, Mask, Simd, SupportedLaneCount, cmp::SimdPartialEq, num::SimdUint}; +use crate::simd::{Mask, Simd, cmp::SimdPartialEq, num::SimdUint}; /// Operations on SIMD vectors of constant pointers. pub trait SimdConstPtr: Copy + Sealed { @@ -88,12 +88,9 @@ pub trait SimdConstPtr: Copy + Sealed { fn wrapping_sub(self, count: Self::Usize) -> Self; } -impl Sealed for Simd<*const T, N> where LaneCount: SupportedLaneCount {} +impl Sealed for Simd<*const T, N> {} -impl SimdConstPtr for Simd<*const T, N> -where - LaneCount: SupportedLaneCount, -{ +impl SimdConstPtr for Simd<*const T, N> { type Usize = Simd; type Isize = Simd; type CastPtr = Simd<*const U, N>; diff --git a/library/portable-simd/crates/core_simd/src/simd/ptr/mut_ptr.rs b/library/portable-simd/crates/core_simd/src/simd/ptr/mut_ptr.rs index c644f390c20a..3b9b75ddf566 100644 --- a/library/portable-simd/crates/core_simd/src/simd/ptr/mut_ptr.rs +++ b/library/portable-simd/crates/core_simd/src/simd/ptr/mut_ptr.rs @@ -1,5 +1,5 @@ use super::sealed::Sealed; -use crate::simd::{LaneCount, Mask, Simd, SupportedLaneCount, cmp::SimdPartialEq, num::SimdUint}; +use crate::simd::{Mask, Simd, cmp::SimdPartialEq, num::SimdUint}; /// Operations on SIMD vectors of mutable pointers. pub trait SimdMutPtr: Copy + Sealed { @@ -85,12 +85,9 @@ pub trait SimdMutPtr: Copy + Sealed { fn wrapping_sub(self, count: Self::Usize) -> Self; } -impl Sealed for Simd<*mut T, N> where LaneCount: SupportedLaneCount {} +impl Sealed for Simd<*mut T, N> {} -impl SimdMutPtr for Simd<*mut T, N> -where - LaneCount: SupportedLaneCount, -{ +impl SimdMutPtr for Simd<*mut T, N> { type Usize = Simd; type Isize = Simd; type CastPtr = Simd<*mut U, N>; diff --git a/library/portable-simd/crates/core_simd/src/swizzle.rs b/library/portable-simd/crates/core_simd/src/swizzle.rs index dbdd6ef40eba..02dcd71356dd 100644 --- a/library/portable-simd/crates/core_simd/src/swizzle.rs +++ b/library/portable-simd/crates/core_simd/src/swizzle.rs @@ -1,4 +1,4 @@ -use crate::simd::{LaneCount, Mask, MaskElement, Simd, SimdElement, SupportedLaneCount}; +use crate::simd::{Mask, MaskElement, Simd, SimdElement}; /// Constructs a new SIMD vector by copying elements from selected elements in other vectors. /// @@ -82,8 +82,6 @@ pub trait Swizzle { fn swizzle(vector: Simd) -> Simd where T: SimdElement, - LaneCount: SupportedLaneCount, - LaneCount: SupportedLaneCount, { // Safety: `vector` is a vector, and the index is a const vector of u32. unsafe { @@ -122,8 +120,6 @@ pub trait Swizzle { fn concat_swizzle(first: Simd, second: Simd) -> Simd where T: SimdElement, - LaneCount: SupportedLaneCount, - LaneCount: SupportedLaneCount, { // Safety: `first` and `second` are vectors, and the index is a const vector of u32. unsafe { @@ -161,11 +157,9 @@ pub trait Swizzle { fn swizzle_mask(mask: Mask) -> Mask where T: MaskElement, - LaneCount: SupportedLaneCount, - LaneCount: SupportedLaneCount, { // SAFETY: all elements of this mask come from another mask - unsafe { Mask::from_int_unchecked(Self::swizzle(mask.to_int())) } + unsafe { Mask::from_simd_unchecked(Self::swizzle(mask.to_simd())) } } /// Creates a new mask from the elements of `first` and `second`. @@ -177,18 +171,17 @@ pub trait Swizzle { fn concat_swizzle_mask(first: Mask, second: Mask) -> Mask where T: MaskElement, - LaneCount: SupportedLaneCount, - LaneCount: SupportedLaneCount, { // SAFETY: all elements of this mask come from another mask - unsafe { Mask::from_int_unchecked(Self::concat_swizzle(first.to_int(), second.to_int())) } + unsafe { + Mask::from_simd_unchecked(Self::concat_swizzle(first.to_simd(), second.to_simd())) + } } } impl Simd where T: SimdElement, - LaneCount: SupportedLaneCount, { /// Reverse the order of the elements in the vector. #[inline] @@ -462,10 +455,7 @@ where /// ``` #[inline] #[must_use = "method returns a new vector and does not mutate the original inputs"] - pub fn resize(self, value: T) -> Simd - where - LaneCount: SupportedLaneCount, - { + pub fn resize(self, value: T) -> Simd { struct Resize; impl Swizzle for Resize { const INDEX: [usize; M] = const { @@ -493,10 +483,7 @@ where /// ``` #[inline] #[must_use = "method returns a new vector and does not mutate the original inputs"] - pub fn extract(self) -> Simd - where - LaneCount: SupportedLaneCount, - { + pub fn extract(self) -> Simd { struct Extract; impl Swizzle for Extract { const INDEX: [usize; LEN] = const { @@ -517,14 +504,13 @@ where impl Mask where T: MaskElement, - LaneCount: SupportedLaneCount, { /// Reverse the order of the elements in the mask. #[inline] #[must_use = "method returns a new vector and does not mutate the original inputs"] pub fn reverse(self) -> Self { // Safety: swizzles are safe for masks - unsafe { Self::from_int_unchecked(self.to_int().reverse()) } + unsafe { Self::from_simd_unchecked(self.to_simd().reverse()) } } /// Rotates the mask such that the first `OFFSET` elements of the slice move to the end @@ -534,7 +520,7 @@ where #[must_use = "method returns a new vector and does not mutate the original inputs"] pub fn rotate_elements_left(self) -> Self { // Safety: swizzles are safe for masks - unsafe { Self::from_int_unchecked(self.to_int().rotate_elements_left::()) } + unsafe { Self::from_simd_unchecked(self.to_simd().rotate_elements_left::()) } } /// Rotates the mask such that the first `self.len() - OFFSET` elements of the mask move to @@ -544,7 +530,7 @@ where #[must_use = "method returns a new vector and does not mutate the original inputs"] pub fn rotate_elements_right(self) -> Self { // Safety: swizzles are safe for masks - unsafe { Self::from_int_unchecked(self.to_int().rotate_elements_right::()) } + unsafe { Self::from_simd_unchecked(self.to_simd().rotate_elements_right::()) } } /// Shifts the mask elements to the left by `OFFSET`, filling in with @@ -554,7 +540,7 @@ where pub fn shift_elements_left(self, padding: bool) -> Self { // Safety: swizzles are safe for masks unsafe { - Self::from_int_unchecked(self.to_int().shift_elements_left::(if padding { + Self::from_simd_unchecked(self.to_simd().shift_elements_left::(if padding { T::TRUE } else { T::FALSE @@ -569,7 +555,7 @@ where pub fn shift_elements_right(self, padding: bool) -> Self { // Safety: swizzles are safe for masks unsafe { - Self::from_int_unchecked(self.to_int().shift_elements_right::(if padding { + Self::from_simd_unchecked(self.to_simd().shift_elements_right::(if padding { T::TRUE } else { T::FALSE @@ -598,9 +584,9 @@ where #[inline] #[must_use = "method returns a new vector and does not mutate the original inputs"] pub fn interleave(self, other: Self) -> (Self, Self) { - let (lo, hi) = self.to_int().interleave(other.to_int()); + let (lo, hi) = self.to_simd().interleave(other.to_simd()); // Safety: swizzles are safe for masks - unsafe { (Self::from_int_unchecked(lo), Self::from_int_unchecked(hi)) } + unsafe { (Self::from_simd_unchecked(lo), Self::from_simd_unchecked(hi)) } } /// Deinterleave two masks. @@ -627,12 +613,12 @@ where #[inline] #[must_use = "method returns a new vector and does not mutate the original inputs"] pub fn deinterleave(self, other: Self) -> (Self, Self) { - let (even, odd) = self.to_int().deinterleave(other.to_int()); + let (even, odd) = self.to_simd().deinterleave(other.to_simd()); // Safety: swizzles are safe for masks unsafe { ( - Self::from_int_unchecked(even), - Self::from_int_unchecked(odd), + Self::from_simd_unchecked(even), + Self::from_simd_unchecked(odd), ) } } @@ -653,13 +639,10 @@ where /// ``` #[inline] #[must_use = "method returns a new vector and does not mutate the original inputs"] - pub fn resize(self, value: bool) -> Mask - where - LaneCount: SupportedLaneCount, - { + pub fn resize(self, value: bool) -> Mask { // Safety: swizzles are safe for masks unsafe { - Mask::::from_int_unchecked(self.to_int().resize::(if value { + Mask::::from_simd_unchecked(self.to_simd().resize::(if value { T::TRUE } else { T::FALSE @@ -679,11 +662,8 @@ where /// ``` #[inline] #[must_use = "method returns a new vector and does not mutate the original inputs"] - pub fn extract(self) -> Mask - where - LaneCount: SupportedLaneCount, - { + pub fn extract(self) -> Mask { // Safety: swizzles are safe for masks - unsafe { Mask::::from_int_unchecked(self.to_int().extract::()) } + unsafe { Mask::::from_simd_unchecked(self.to_simd().extract::()) } } } diff --git a/library/portable-simd/crates/core_simd/src/swizzle_dyn.rs b/library/portable-simd/crates/core_simd/src/swizzle_dyn.rs index 773bd028bae0..ae0b174973da 100644 --- a/library/portable-simd/crates/core_simd/src/swizzle_dyn.rs +++ b/library/portable-simd/crates/core_simd/src/swizzle_dyn.rs @@ -1,10 +1,7 @@ -use crate::simd::{LaneCount, Simd, SupportedLaneCount}; +use crate::simd::Simd; use core::mem; -impl Simd -where - LaneCount: SupportedLaneCount, -{ +impl Simd { /// Swizzle a vector of bytes according to the index vector. /// Indices within range select the appropriate byte. /// Indices "out of bounds" instead select 0. @@ -139,7 +136,7 @@ unsafe fn armv7_neon_swizzle_u8x16(bytes: Simd, idxs: Simd) -> S #[inline] #[allow(clippy::let_and_return)] unsafe fn avx2_pshufb(bytes: Simd, idxs: Simd) -> Simd { - use crate::simd::cmp::SimdPartialOrd; + use crate::simd::{Select, cmp::SimdPartialOrd}; #[cfg(target_arch = "x86")] use core::arch::x86; #[cfg(target_arch = "x86_64")] @@ -184,10 +181,7 @@ unsafe fn transize( f: unsafe fn(T, T) -> T, a: Simd, b: Simd, -) -> Simd -where - LaneCount: SupportedLaneCount, -{ +) -> Simd { // SAFETY: Same obligation to use this function as to use mem::transmute_copy. unsafe { mem::transmute_copy(&f(mem::transmute_copy(&a), mem::transmute_copy(&b))) } } @@ -196,11 +190,8 @@ where #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] #[allow(unused)] #[inline(always)] -fn zeroing_idxs(idxs: Simd) -> Simd -where - LaneCount: SupportedLaneCount, -{ - use crate::simd::cmp::SimdPartialOrd; +fn zeroing_idxs(idxs: Simd) -> Simd { + use crate::simd::{Select, cmp::SimdPartialOrd}; idxs.simd_lt(Simd::splat(N as u8)) .select(idxs, Simd::splat(u8::MAX)) } diff --git a/library/portable-simd/crates/core_simd/src/to_bytes.rs b/library/portable-simd/crates/core_simd/src/to_bytes.rs index fee2cc06c5b0..1fd285e457db 100644 --- a/library/portable-simd/crates/core_simd/src/to_bytes.rs +++ b/library/portable-simd/crates/core_simd/src/to_bytes.rs @@ -1,12 +1,12 @@ use crate::simd::{ - LaneCount, Simd, SimdElement, SupportedLaneCount, + Simd, SimdElement, num::{SimdFloat, SimdInt, SimdUint}, }; mod sealed { use super::*; pub trait Sealed {} - impl Sealed for Simd where LaneCount: SupportedLaneCount {} + impl Sealed for Simd {} } use sealed::Sealed; diff --git a/library/portable-simd/crates/core_simd/src/vector.rs b/library/portable-simd/crates/core_simd/src/vector.rs index f40031f8c4da..5b3a689f3611 100644 --- a/library/portable-simd/crates/core_simd/src/vector.rs +++ b/library/portable-simd/crates/core_simd/src/vector.rs @@ -1,5 +1,7 @@ +use core::intrinsics::simd::SimdAlign; + use crate::simd::{ - LaneCount, Mask, MaskElement, SupportedLaneCount, Swizzle, + Mask, MaskElement, cmp::SimdPartialOrd, num::SimdUint, ptr::{SimdConstPtr, SimdMutPtr}, @@ -51,6 +53,8 @@ use crate::simd::{ /// Thus it is sound to [`transmute`] `Simd` to `[T; N]` and should optimize to "zero cost", /// but the reverse transmutation may require a copy the compiler cannot simply elide. /// +/// `N` cannot be 0 and may be at most 64. This limit may be increased in the future. +/// /// # ABI "Features" /// Due to Rust's safety guarantees, `Simd` is currently passed and returned via memory, /// not SIMD registers, except as an optimization. Using `#[inline]` on functions that accept @@ -100,14 +104,13 @@ use crate::simd::{ // avoided, as it will likely become illegal on `#[repr(simd)]` structs in the future. It also // causes rustc to emit illegal LLVM IR in some cases. #[repr(simd, packed)] +#[rustc_simd_monomorphize_lane_limit = "64"] pub struct Simd([T; N]) where - LaneCount: SupportedLaneCount, T: SimdElement; impl Simd where - LaneCount: SupportedLaneCount, T: SimdElement, { /// Number of elements in this vector. @@ -146,30 +149,8 @@ where #[inline] #[rustc_const_unstable(feature = "portable_simd", issue = "86656")] pub const fn splat(value: T) -> Self { - const fn splat_const(value: T) -> Simd - where - T: SimdElement, - LaneCount: SupportedLaneCount, - { - Simd::from_array([value; N]) - } - - fn splat_rt(value: T) -> Simd - where - T: SimdElement, - LaneCount: SupportedLaneCount, - { - // This is preferred over `[value; N]`, since it's explicitly a splat: - // https://github.com/rust-lang/rust/issues/97804 - struct Splat; - impl Swizzle for Splat { - const INDEX: [usize; N] = [0; N]; - } - - Splat::swizzle::(Simd::::from([value])) - } - - core::intrinsics::const_eval_select((value,), splat_const, splat_rt) + // SAFETY: T is a SimdElement, and the item type of Self. + unsafe { core::intrinsics::simd::simd_splat(value) } } /// Returns an array reference containing the entire SIMD vector. @@ -195,7 +176,7 @@ where /// Returns a mutable array reference containing the entire SIMD vector. #[inline] - pub fn as_mut_array(&mut self) -> &mut [T; N] { + pub const fn as_mut_array(&mut self) -> &mut [T; N] { // SAFETY: `Simd` is just an overaligned `[T; N]` with // potential padding at the end, so pointer casting to a // `&mut [T; N]` is safe. @@ -324,7 +305,7 @@ where /// ``` #[inline] #[track_caller] - pub fn copy_to_slice(self, slice: &mut [T]) { + pub const fn copy_to_slice(self, slice: &mut [T]) { assert!( slice.len() >= Self::LEN, "slice length must be at least the number of elements" @@ -465,7 +446,7 @@ where /// value from `or` is passed through. /// /// # Safety - /// Enabled `ptr` elements must be safe to read as if by `std::ptr::read`. + /// Enabled `ptr` elements must be safe to read as if by `core::ptr::read`. #[must_use] #[inline] pub unsafe fn load_select_ptr( @@ -475,12 +456,11 @@ where ) -> Self { // SAFETY: The safety of reading elements through `ptr` is ensured by the caller. unsafe { - core::intrinsics::simd::simd_masked_load::< - _, - _, - _, - { core::intrinsics::simd::SimdAlign::Element }, - >(enable.to_int(), ptr, or) + core::intrinsics::simd::simd_masked_load::<_, _, _, { SimdAlign::Element }>( + enable.to_simd(), + ptr, + or, + ) } } @@ -659,7 +639,7 @@ where or: Self, ) -> Self { // Safety: The caller is responsible for upholding all invariants - unsafe { core::intrinsics::simd::simd_gather(or, source, enable.to_int()) } + unsafe { core::intrinsics::simd::simd_gather(or, source, enable.to_simd()) } } /// Conditionally write contiguous elements to `slice`. The `enable` mask controls @@ -731,12 +711,11 @@ where pub unsafe fn store_select_ptr(self, ptr: *mut T, enable: Mask<::Mask, N>) { // SAFETY: The safety of writing elements through `ptr` is ensured by the caller. unsafe { - core::intrinsics::simd::simd_masked_store::< - _, - _, - _, - { core::intrinsics::simd::SimdAlign::Element }, - >(enable.to_int(), ptr, self) + core::intrinsics::simd::simd_masked_store::<_, _, _, { SimdAlign::Element }>( + enable.to_simd(), + ptr, + self, + ) } } @@ -896,20 +875,14 @@ where #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces pub unsafe fn scatter_select_ptr(self, dest: Simd<*mut T, N>, enable: Mask) { // Safety: The caller is responsible for upholding all invariants - unsafe { core::intrinsics::simd::simd_scatter(self, dest, enable.to_int()) } + unsafe { core::intrinsics::simd::simd_scatter(self, dest, enable.to_simd()) } } } -impl Copy for Simd -where - LaneCount: SupportedLaneCount, - T: SimdElement, -{ -} +impl Copy for Simd where T: SimdElement {} impl Clone for Simd where - LaneCount: SupportedLaneCount, T: SimdElement, { #[inline] @@ -920,7 +893,6 @@ where impl Default for Simd where - LaneCount: SupportedLaneCount, T: SimdElement + Default, { #[inline] @@ -931,7 +903,6 @@ where impl PartialEq for Simd where - LaneCount: SupportedLaneCount, T: SimdElement + PartialEq, { #[inline] @@ -940,7 +911,7 @@ where let mask = unsafe { let tfvec: Simd<::Mask, N> = core::intrinsics::simd::simd_eq(*self, *other); - Mask::from_int_unchecked(tfvec) + Mask::from_simd_unchecked(tfvec) }; // Two vectors are equal if all elements are equal when compared elementwise @@ -954,7 +925,7 @@ where let mask = unsafe { let tfvec: Simd<::Mask, N> = core::intrinsics::simd::simd_ne(*self, *other); - Mask::from_int_unchecked(tfvec) + Mask::from_simd_unchecked(tfvec) }; // Two vectors are non-equal if any elements are non-equal when compared elementwise @@ -965,7 +936,6 @@ where /// Lexicographic order. For the SIMD elementwise minimum and maximum, use simd_min and simd_max instead. impl PartialOrd for Simd where - LaneCount: SupportedLaneCount, T: SimdElement + PartialOrd, { #[inline] @@ -975,17 +945,11 @@ where } } -impl Eq for Simd -where - LaneCount: SupportedLaneCount, - T: SimdElement + Eq, -{ -} +impl Eq for Simd where T: SimdElement + Eq {} /// Lexicographic order. For the SIMD elementwise minimum and maximum, use simd_min and simd_max instead. impl Ord for Simd where - LaneCount: SupportedLaneCount, T: SimdElement + Ord, { #[inline] @@ -997,7 +961,6 @@ where impl core::hash::Hash for Simd where - LaneCount: SupportedLaneCount, T: SimdElement + core::hash::Hash, { #[inline] @@ -1012,7 +975,6 @@ where // array references impl AsRef<[T; N]> for Simd where - LaneCount: SupportedLaneCount, T: SimdElement, { #[inline] @@ -1023,7 +985,6 @@ where impl AsMut<[T; N]> for Simd where - LaneCount: SupportedLaneCount, T: SimdElement, { #[inline] @@ -1035,7 +996,6 @@ where // slice references impl AsRef<[T]> for Simd where - LaneCount: SupportedLaneCount, T: SimdElement, { #[inline] @@ -1046,7 +1006,6 @@ where impl AsMut<[T]> for Simd where - LaneCount: SupportedLaneCount, T: SimdElement, { #[inline] @@ -1058,7 +1017,6 @@ where // vector/array conversion impl From<[T; N]> for Simd where - LaneCount: SupportedLaneCount, T: SimdElement, { #[inline] @@ -1069,7 +1027,6 @@ where impl From> for [T; N] where - LaneCount: SupportedLaneCount, T: SimdElement, { #[inline] @@ -1080,7 +1037,6 @@ where impl TryFrom<&[T]> for Simd where - LaneCount: SupportedLaneCount, T: SimdElement, { type Error = core::array::TryFromSliceError; @@ -1093,7 +1049,6 @@ where impl TryFrom<&mut [T]> for Simd where - LaneCount: SupportedLaneCount, T: SimdElement, { type Error = core::array::TryFromSliceError; @@ -1231,10 +1186,7 @@ where } #[inline] -fn lane_indices() -> Simd -where - LaneCount: SupportedLaneCount, -{ +fn lane_indices() -> Simd { #![allow(clippy::needless_range_loop)] let mut index = [0; N]; for i in 0..N { @@ -1246,7 +1198,6 @@ where #[inline] fn mask_up_to(len: usize) -> Mask where - LaneCount: SupportedLaneCount, M: MaskElement, { let index = lane_indices::(); diff --git a/library/portable-simd/crates/core_simd/src/vendor/loongarch64.rs b/library/portable-simd/crates/core_simd/src/vendor/loongarch64.rs index 1290bc166b2b..1f84cdb971ec 100644 --- a/library/portable-simd/crates/core_simd/src/vendor/loongarch64.rs +++ b/library/portable-simd/crates/core_simd/src/vendor/loongarch64.rs @@ -1,31 +1,26 @@ use crate::simd::*; use core::arch::loongarch64::*; -from_transmute! { unsafe u8x16 => v16u8 } -from_transmute! { unsafe u8x32 => v32u8 } -from_transmute! { unsafe i8x16 => v16i8 } -from_transmute! { unsafe i8x32 => v32i8 } +from_transmute! { unsafe u8x16 => m128i } +from_transmute! { unsafe u8x32 => m256i } +from_transmute! { unsafe i8x16 => m128i } +from_transmute! { unsafe i8x32 => m256i } -from_transmute! { unsafe u16x8 => v8u16 } -from_transmute! { unsafe u16x16 => v16u16 } -from_transmute! { unsafe i16x8 => v8i16 } -from_transmute! { unsafe i16x16 => v16i16 } +from_transmute! { unsafe u16x8 => m128i } +from_transmute! { unsafe u16x16 => m256i } +from_transmute! { unsafe i16x8 => m128i } +from_transmute! { unsafe i16x16 => m256i } -from_transmute! { unsafe u32x4 => v4u32 } -from_transmute! { unsafe u32x8 => v8u32 } -from_transmute! { unsafe i32x4 => v4i32 } -from_transmute! { unsafe i32x8 => v8i32 } -from_transmute! { unsafe f32x4 => v4f32 } -from_transmute! { unsafe f32x8 => v8f32 } +from_transmute! { unsafe u32x4 => m128i } +from_transmute! { unsafe u32x8 => m256i } +from_transmute! { unsafe i32x4 => m128i } +from_transmute! { unsafe i32x8 => m256i } +from_transmute! { unsafe f32x4 => m128 } +from_transmute! { unsafe f32x8 => m256 } -from_transmute! { unsafe u64x2 => v2u64 } -from_transmute! { unsafe u64x4 => v4u64 } -from_transmute! { unsafe i64x2 => v2i64 } -from_transmute! { unsafe i64x4 => v4i64 } -from_transmute! { unsafe f64x2 => v2f64 } -from_transmute! { unsafe f64x4 => v4f64 } - -from_transmute! { unsafe usizex2 => v2u64 } -from_transmute! { unsafe usizex4 => v4u64 } -from_transmute! { unsafe isizex2 => v2i64 } -from_transmute! { unsafe isizex4 => v4i64 } +from_transmute! { unsafe u64x2 => m128i } +from_transmute! { unsafe u64x4 => m256i } +from_transmute! { unsafe i64x2 => m128i } +from_transmute! { unsafe i64x4 => m256i } +from_transmute! { unsafe f64x2 => m128d } +from_transmute! { unsafe f64x4 => m256d } diff --git a/library/portable-simd/crates/core_simd/src/vendor/wasm32.rs b/library/portable-simd/crates/core_simd/src/vendor/wasm32.rs index ef3baf885b0f..1fdb2bc86d34 100644 --- a/library/portable-simd/crates/core_simd/src/vendor/wasm32.rs +++ b/library/portable-simd/crates/core_simd/src/vendor/wasm32.rs @@ -14,17 +14,3 @@ from_transmute! { unsafe f32x4 => v128 } from_transmute! { unsafe u64x2 => v128 } from_transmute! { unsafe i64x2 => v128 } from_transmute! { unsafe f64x2 => v128 } - -#[cfg(target_pointer_width = "32")] -mod p32 { - use super::*; - from_transmute! { unsafe usizex4 => v128 } - from_transmute! { unsafe isizex4 => v128 } -} - -#[cfg(target_pointer_width = "64")] -mod p64 { - use super::*; - from_transmute! { unsafe usizex2 => v128 } - from_transmute! { unsafe isizex2 => v128 } -} diff --git a/library/portable-simd/crates/core_simd/src/vendor/x86.rs b/library/portable-simd/crates/core_simd/src/vendor/x86.rs index 66aaf90eef59..eae42e6fd0d0 100644 --- a/library/portable-simd/crates/core_simd/src/vendor/x86.rs +++ b/library/portable-simd/crates/core_simd/src/vendor/x86.rs @@ -39,25 +39,3 @@ from_transmute! { unsafe i64x8 => __m512i } from_transmute! { unsafe f64x2 => __m128d } from_transmute! { unsafe f64x4 => __m256d } from_transmute! { unsafe f64x8 => __m512d } - -#[cfg(target_pointer_width = "32")] -mod p32 { - use super::*; - from_transmute! { unsafe usizex4 => __m128i } - from_transmute! { unsafe usizex8 => __m256i } - from_transmute! { unsafe Simd => __m512i } - from_transmute! { unsafe isizex4 => __m128i } - from_transmute! { unsafe isizex8 => __m256i } - from_transmute! { unsafe Simd => __m512i } -} - -#[cfg(target_pointer_width = "64")] -mod p64 { - use super::*; - from_transmute! { unsafe usizex2 => __m128i } - from_transmute! { unsafe usizex4 => __m256i } - from_transmute! { unsafe usizex8 => __m512i } - from_transmute! { unsafe isizex2 => __m128i } - from_transmute! { unsafe isizex4 => __m256i } - from_transmute! { unsafe isizex8 => __m512i } -} diff --git a/library/portable-simd/crates/core_simd/tests/masks.rs b/library/portable-simd/crates/core_simd/tests/masks.rs index 48786d02440b..53fb2367b605 100644 --- a/library/portable-simd/crates/core_simd/tests/masks.rs +++ b/library/portable-simd/crates/core_simd/tests/masks.rs @@ -65,9 +65,9 @@ macro_rules! test_mask_api { fn roundtrip_int_conversion() { let values = [true, false, false, true, false, false, true, false]; let mask = Mask::<$type, 8>::from_array(values); - let int = mask.to_int(); + let int = mask.to_simd(); assert_eq!(int.to_array(), [-1, 0, 0, -1, 0, 0, -1, 0]); - assert_eq!(Mask::<$type, 8>::from_int(int), mask); + assert_eq!(Mask::<$type, 8>::from_simd(int), mask); } #[test] diff --git a/library/portable-simd/crates/std_float/src/lib.rs b/library/portable-simd/crates/std_float/src/lib.rs index 148aa5f9f177..b269efc9b1d7 100644 --- a/library/portable-simd/crates/std_float/src/lib.rs +++ b/library/portable-simd/crates/std_float/src/lib.rs @@ -11,7 +11,7 @@ use core_simd::simd; use core::intrinsics::simd as intrinsics; -use simd::{LaneCount, Simd, SupportedLaneCount}; +use simd::Simd; #[cfg(feature = "as_crate")] mod experimental { @@ -66,28 +66,43 @@ pub trait StdFloat: Sealed + Sized { /// Produces a vector where every element has the sine of the value /// in the equivalently-indexed element in `self`. + #[inline] #[must_use = "method returns a new vector and does not mutate the original value"] - fn sin(self) -> Self; + fn sin(self) -> Self { + unsafe { intrinsics::simd_fsin(self) } + } /// Produces a vector where every element has the cosine of the value /// in the equivalently-indexed element in `self`. + #[inline] #[must_use = "method returns a new vector and does not mutate the original value"] - fn cos(self) -> Self; + fn cos(self) -> Self { + unsafe { intrinsics::simd_fcos(self) } + } /// Produces a vector where every element has the exponential (base e) of the value /// in the equivalently-indexed element in `self`. + #[inline] #[must_use = "method returns a new vector and does not mutate the original value"] - fn exp(self) -> Self; + fn exp(self) -> Self { + unsafe { intrinsics::simd_fexp(self) } + } /// Produces a vector where every element has the exponential (base 2) of the value /// in the equivalently-indexed element in `self`. + #[inline] #[must_use = "method returns a new vector and does not mutate the original value"] - fn exp2(self) -> Self; + fn exp2(self) -> Self { + unsafe { intrinsics::simd_fexp2(self) } + } /// Produces a vector where every element has the natural logarithm of the value /// in the equivalently-indexed element in `self`. + #[inline] #[must_use = "method returns a new vector and does not mutate the original value"] - fn ln(self) -> Self; + fn ln(self) -> Self { + unsafe { intrinsics::simd_flog(self) } + } /// Produces a vector where every element has the logarithm with respect to an arbitrary /// in the equivalently-indexed elements in `self` and `base`. @@ -99,13 +114,19 @@ pub trait StdFloat: Sealed + Sized { /// Produces a vector where every element has the base-2 logarithm of the value /// in the equivalently-indexed element in `self`. + #[inline] #[must_use = "method returns a new vector and does not mutate the original value"] - fn log2(self) -> Self; + fn log2(self) -> Self { + unsafe { intrinsics::simd_flog2(self) } + } /// Produces a vector where every element has the base-10 logarithm of the value /// in the equivalently-indexed element in `self`. + #[inline] #[must_use = "method returns a new vector and does not mutate the original value"] - fn log10(self) -> Self; + fn log10(self) -> Self { + unsafe { intrinsics::simd_flog10(self) } + } /// Returns the smallest integer greater than or equal to each element. #[must_use = "method returns a new vector and does not mutate the original value"] @@ -140,68 +161,19 @@ pub trait StdFloat: Sealed + Sized { fn fract(self) -> Self; } -impl Sealed for Simd where LaneCount: SupportedLaneCount {} -impl Sealed for Simd where LaneCount: SupportedLaneCount {} +impl Sealed for Simd {} +impl Sealed for Simd {} -macro_rules! impl_float { - { - $($fn:ident: $intrinsic:ident,)* - } => { - impl StdFloat for Simd - where - LaneCount: SupportedLaneCount, - { - #[inline] - fn fract(self) -> Self { - self - self.trunc() - } - - $( - #[inline] - fn $fn(self) -> Self { - unsafe { intrinsics::$intrinsic(self) } - } - )* - } - - impl StdFloat for Simd - where - LaneCount: SupportedLaneCount, - { - #[inline] - fn fract(self) -> Self { - self - self.trunc() - } - - $( - #[inline] - fn $fn(self) -> Self { - // https://github.com/llvm/llvm-project/issues/83729 - #[cfg(target_arch = "aarch64")] - { - let mut ln = Self::splat(0f64); - for i in 0..N { - ln[i] = self[i].$fn() - } - ln - } - - #[cfg(not(target_arch = "aarch64"))] - { - unsafe { intrinsics::$intrinsic(self) } - } - } - )* - } +impl StdFloat for Simd { + #[inline] + fn fract(self) -> Self { + self - self.trunc() } } -impl_float! { - sin: simd_fsin, - cos: simd_fcos, - exp: simd_fexp, - exp2: simd_fexp2, - ln: simd_flog, - log2: simd_flog2, - log10: simd_flog10, +impl StdFloat for Simd { + #[inline] + fn fract(self) -> Self { + self - self.trunc() + } } diff --git a/library/portable-simd/crates/std_float/tests/float.rs b/library/portable-simd/crates/std_float/tests/float.rs index c66c968f8c66..c608ba49564e 100644 --- a/library/portable-simd/crates/std_float/tests/float.rs +++ b/library/portable-simd/crates/std_float/tests/float.rs @@ -16,15 +16,33 @@ macro_rules! unary_test { } } -macro_rules! binary_test { +macro_rules! unary_approx_test { { $scalar:tt, $($func:tt),+ } => { test_helpers::test_lanes! { $( fn $func() { - test_helpers::test_binary_elementwise( + test_helpers::test_unary_elementwise_approx( + &core_simd::simd::Simd::<$scalar, LANES>::$func, + &$scalar::$func, + &|_| true, + 8, + ) + } + )* + } + } +} + +macro_rules! binary_approx_test { + { $scalar:tt, $($func:tt),+ } => { + test_helpers::test_lanes! { + $( + fn $func() { + test_helpers::test_binary_elementwise_approx( &core_simd::simd::Simd::<$scalar, LANES>::$func, &$scalar::$func, &|_, _| true, + 16, ) } )* @@ -53,10 +71,13 @@ macro_rules! impl_tests { mod $scalar { use std_float::StdFloat; - unary_test! { $scalar, sqrt, sin, cos, exp, exp2, ln, log2, log10, ceil, floor, round, trunc } - binary_test! { $scalar, log } + unary_test! { $scalar, sqrt, ceil, floor, round, trunc } ternary_test! { $scalar, mul_add } + // https://github.com/rust-lang/miri/issues/3555 + unary_approx_test! { $scalar, sin, cos, exp, exp2, ln, log2, log10 } + binary_approx_test! { $scalar, log } + test_helpers::test_lanes! { fn fract() { test_helpers::test_unary_elementwise_flush_subnormals( diff --git a/library/portable-simd/crates/test_helpers/Cargo.toml b/library/portable-simd/crates/test_helpers/Cargo.toml index a5359b9abc84..408bb04c7aa4 100644 --- a/library/portable-simd/crates/test_helpers/Cargo.toml +++ b/library/portable-simd/crates/test_helpers/Cargo.toml @@ -6,3 +6,4 @@ publish = false [dependencies] proptest = { version = "0.10", default-features = false, features = ["alloc"] } +float-cmp = "0.10" diff --git a/library/portable-simd/crates/test_helpers/src/approxeq.rs b/library/portable-simd/crates/test_helpers/src/approxeq.rs new file mode 100644 index 000000000000..57b43a16bc6f --- /dev/null +++ b/library/portable-simd/crates/test_helpers/src/approxeq.rs @@ -0,0 +1,110 @@ +//! Compare numeric types approximately. + +use float_cmp::Ulps; + +pub trait ApproxEq { + fn approxeq(&self, other: &Self, _ulps: i64) -> bool; + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result; +} + +impl ApproxEq for bool { + fn approxeq(&self, other: &Self, _ulps: i64) -> bool { + self == other + } + + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{:?}", self) + } +} + +macro_rules! impl_integer_approxeq { + { $($type:ty),* } => { + $( + impl ApproxEq for $type { + fn approxeq(&self, other: &Self, _ulps: i64) -> bool { + self == other + } + + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{:?} ({:x})", self, self) + } + } + )* + }; +} + +impl_integer_approxeq! { u8, u16, u32, u64, u128, usize, i8, i16, i32, i64, i128, isize } + +macro_rules! impl_float_approxeq { + { $($type:ty),* } => { + $( + impl ApproxEq for $type { + fn approxeq(&self, other: &Self, ulps: i64) -> bool { + if self.is_nan() && other.is_nan() { + true + } else { + (self.ulps(other) as i64).abs() <= ulps + } + } + + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{:?} ({:x})", self, self.to_bits()) + } + } + )* + }; +} + +impl_float_approxeq! { f32, f64 } + +impl ApproxEq for [T; N] { + fn approxeq(&self, other: &Self, ulps: i64) -> bool { + self.iter() + .zip(other.iter()) + .fold(true, |value, (left, right)| { + value && left.approxeq(right, ulps) + }) + } + + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + #[repr(transparent)] + struct Wrapper<'a, T: ApproxEq>(&'a T); + + impl core::fmt::Debug for Wrapper<'_, T> { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + self.0.fmt(f) + } + } + + f.debug_list() + .entries(self.iter().map(|x| Wrapper(x))) + .finish() + } +} + +#[doc(hidden)] +pub struct ApproxEqWrapper<'a, T>(pub &'a T, pub i64); + +impl PartialEq for ApproxEqWrapper<'_, T> { + fn eq(&self, other: &T) -> bool { + self.0.approxeq(other, self.1) + } +} + +impl core::fmt::Debug for ApproxEqWrapper<'_, T> { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + self.0.fmt(f) + } +} + +#[macro_export] +macro_rules! prop_assert_approxeq { + { $a:expr, $b:expr, $ulps:expr $(,)? } => { + { + use $crate::approxeq::ApproxEqWrapper; + let a = $a; + let b = $b; + proptest::prop_assert_eq!(ApproxEqWrapper(&a, $ulps), b); + } + }; +} diff --git a/library/portable-simd/crates/test_helpers/src/lib.rs b/library/portable-simd/crates/test_helpers/src/lib.rs index 197c920e11ea..eb3d3f68bc2e 100644 --- a/library/portable-simd/crates/test_helpers/src/lib.rs +++ b/library/portable-simd/crates/test_helpers/src/lib.rs @@ -12,6 +12,9 @@ pub mod wasm; #[macro_use] pub mod biteq; +#[macro_use] +pub mod approxeq; + pub mod subnormals; use subnormals::FlushSubnormals; @@ -185,6 +188,41 @@ pub fn test_unary_elementwise( + fv: &dyn Fn(Vector) -> VectorResult, + fs: &dyn Fn(Scalar) -> ScalarResult, + check: &dyn Fn([Scalar; LANES]) -> bool, + ulps: i64, +) where + Scalar: Copy + core::fmt::Debug + DefaultStrategy, + ScalarResult: Copy + approxeq::ApproxEq + core::fmt::Debug + DefaultStrategy, + Vector: Into<[Scalar; LANES]> + From<[Scalar; LANES]> + Copy, + VectorResult: Into<[ScalarResult; LANES]> + From<[ScalarResult; LANES]> + Copy, +{ + test_1(&|x: [Scalar; LANES]| { + proptest::prop_assume!(check(x)); + let result_1: [ScalarResult; LANES] = fv(x.into()).into(); + let result_2: [ScalarResult; LANES] = x + .iter() + .copied() + .map(fs) + .collect::>() + .try_into() + .unwrap(); + crate::prop_assert_approxeq!(result_1, result_2, ulps); + Ok(()) + }); +} + /// Test a unary vector function against a unary scalar function, applied elementwise. /// /// Where subnormals are flushed, use approximate equality. @@ -290,6 +328,44 @@ pub fn test_binary_elementwise< }); } +/// Test a binary vector function against a binary scalar function, applied elementwise. +pub fn test_binary_elementwise_approx< + Scalar1, + Scalar2, + ScalarResult, + Vector1, + Vector2, + VectorResult, + const LANES: usize, +>( + fv: &dyn Fn(Vector1, Vector2) -> VectorResult, + fs: &dyn Fn(Scalar1, Scalar2) -> ScalarResult, + check: &dyn Fn([Scalar1; LANES], [Scalar2; LANES]) -> bool, + ulps: i64, +) where + Scalar1: Copy + core::fmt::Debug + DefaultStrategy, + Scalar2: Copy + core::fmt::Debug + DefaultStrategy, + ScalarResult: Copy + approxeq::ApproxEq + core::fmt::Debug + DefaultStrategy, + Vector1: Into<[Scalar1; LANES]> + From<[Scalar1; LANES]> + Copy, + Vector2: Into<[Scalar2; LANES]> + From<[Scalar2; LANES]> + Copy, + VectorResult: Into<[ScalarResult; LANES]> + From<[ScalarResult; LANES]> + Copy, +{ + test_2(&|x: [Scalar1; LANES], y: [Scalar2; LANES]| { + proptest::prop_assume!(check(x, y)); + let result_1: [ScalarResult; LANES] = fv(x.into(), y.into()).into(); + let result_2: [ScalarResult; LANES] = x + .iter() + .copied() + .zip(y.iter().copied()) + .map(|(x, y)| fs(x, y)) + .collect::>() + .try_into() + .unwrap(); + crate::prop_assert_approxeq!(result_1, result_2, ulps); + Ok(()) + }); +} + /// Test a binary vector function against a binary scalar function, applied elementwise. /// /// Where subnormals are flushed, use approximate equality. @@ -528,8 +604,6 @@ macro_rules! test_lanes { use super::*; fn implementation() - where - core_simd::simd::LaneCount<$lanes>: core_simd::simd::SupportedLaneCount, $body #[cfg(target_arch = "wasm32")] @@ -628,8 +702,6 @@ macro_rules! test_lanes_panic { use super::*; fn implementation() - where - core_simd::simd::LaneCount<$lanes>: core_simd::simd::SupportedLaneCount, $body // test some odd and even non-power-of-2 lengths on miri diff --git a/library/portable-simd/rust-toolchain.toml b/library/portable-simd/rust-toolchain.toml index d17c6d2e8894..639d07df7337 100644 --- a/library/portable-simd/rust-toolchain.toml +++ b/library/portable-simd/rust-toolchain.toml @@ -1,3 +1,3 @@ [toolchain] -channel = "nightly-2025-01-16" +channel = "nightly-2026-01-26" components = ["rustfmt", "clippy", "miri", "rust-src"] diff --git a/library/std/Cargo.toml b/library/std/Cargo.toml index 87887f113b79..f4cc8edc0c1d 100644 --- a/library/std/Cargo.toml +++ b/library/std/Cargo.toml @@ -26,7 +26,7 @@ hashbrown = { version = "0.16.1", default-features = false, features = [ std_detect = { path = "../std_detect", public = true } # Dependencies of the `backtrace` crate -rustc-demangle = { version = "0.1.24", features = ['rustc-dep-of-std'] } +rustc-demangle = { version = "0.1.27", features = ['rustc-dep-of-std'] } [target.'cfg(not(all(windows, target_env = "msvc", not(target_vendor = "uwp"))))'.dependencies] miniz_oxide = { version = "0.8.0", optional = true, default-features = false } @@ -115,7 +115,6 @@ backtrace-trace-only = [] panic-unwind = ["dep:panic_unwind"] compiler-builtins-c = ["alloc/compiler-builtins-c"] compiler-builtins-mem = ["alloc/compiler-builtins-mem"] -compiler-builtins-no-f16-f128 = ["alloc/compiler-builtins-no-f16-f128"] llvm-libunwind = ["unwind/llvm-libunwind"] system-llvm-libunwind = ["unwind/system-llvm-libunwind"] diff --git a/library/std/src/env.rs b/library/std/src/env.rs index 5c068ad2471a..615b767a4ea5 100644 --- a/library/std/src/env.rs +++ b/library/std/src/env.rs @@ -728,7 +728,7 @@ pub fn temp_dir() -> PathBuf { /// /// You expected to safely execute the current executable, but you're /// instead executing something completely different. The code you -/// just executed run with your privileges. +/// just executed runs with your privileges. /// /// This sort of behavior has been known to [lead to privilege escalation] when /// used incorrectly. diff --git a/library/std/src/sys/thread/mod.rs b/library/std/src/sys/thread/mod.rs index 5010774dafde..9816981c7fc8 100644 --- a/library/std/src/sys/thread/mod.rs +++ b/library/std/src/sys/thread/mod.rs @@ -70,7 +70,6 @@ cfg_select! { target_os = "illumos", target_os = "dragonfly", target_os = "hurd", - target_os = "fuchsia", target_os = "vxworks", target_os = "wasi", target_vendor = "apple", @@ -131,7 +130,6 @@ cfg_select! { target_os = "illumos", target_os = "dragonfly", target_os = "hurd", - target_os = "fuchsia", target_os = "vxworks", target_os = "wasi", target_vendor = "apple", diff --git a/library/std/src/sys/thread/unix.rs b/library/std/src/sys/thread/unix.rs index e708c9a3f1ba..b758737d00c6 100644 --- a/library/std/src/sys/thread/unix.rs +++ b/library/std/src/sys/thread/unix.rs @@ -542,7 +542,6 @@ pub fn sleep(dur: Duration) { target_os = "illumos", target_os = "dragonfly", target_os = "hurd", - target_os = "fuchsia", target_os = "vxworks", target_os = "wasi", ) => { @@ -640,7 +639,6 @@ pub fn sleep(dur: Duration) { target_os = "illumos", target_os = "dragonfly", target_os = "hurd", - target_os = "fuchsia", target_os = "vxworks", target_os = "wasi", ))] diff --git a/library/std/src/thread/functions.rs b/library/std/src/thread/functions.rs index 73d727878570..95d7aaf51840 100644 --- a/library/std/src/thread/functions.rs +++ b/library/std/src/thread/functions.rs @@ -316,7 +316,6 @@ pub fn sleep(dur: Duration) { /// | Illumos | [clock_nanosleep] (Monotonic Clock)] | /// | Dragonfly | [clock_nanosleep] (Monotonic Clock)] | /// | Hurd | [clock_nanosleep] (Monotonic Clock)] | -/// | Fuchsia | [clock_nanosleep] (Monotonic Clock)] | /// | Vxworks | [clock_nanosleep] (Monotonic Clock)] | /// | Apple | `mach_wait_until` | /// | Other | `sleep_until` uses [`sleep`] and does not issue a syscall itself | diff --git a/library/std/src/thread/join_handle.rs b/library/std/src/thread/join_handle.rs index 7112fe44f907..93dcc634d2df 100644 --- a/library/std/src/thread/join_handle.rs +++ b/library/std/src/thread/join_handle.rs @@ -101,6 +101,8 @@ impl JoinHandle { /// Waits for the associated thread to finish. /// /// This function will return immediately if the associated thread has already finished. + /// Otherwise, it fully waits for the thread to finish, including all destructors + /// for thread-local variables that might be running after the main function of the thread. /// /// In terms of [atomic memory orderings], the completion of the associated /// thread synchronizes with this function returning. In other words, all diff --git a/library/std/src/thread/scoped.rs b/library/std/src/thread/scoped.rs index 3ac9956336d7..929f7fdc6dca 100644 --- a/library/std/src/thread/scoped.rs +++ b/library/std/src/thread/scoped.rs @@ -80,6 +80,9 @@ impl ScopeData { /// /// All threads spawned within the scope that haven't been manually joined /// will be automatically joined before this function returns. +/// However, note that joining will only wait for the main function of these threads to finish; even +/// when this function returns, destructors of thread-local variables in these threads might still +/// be running. /// /// # Panics /// @@ -290,6 +293,8 @@ impl<'scope, T> ScopedJoinHandle<'scope, T> { /// Waits for the associated thread to finish. /// /// This function will return immediately if the associated thread has already finished. + /// Otherwise, it fully waits for the thread to finish, including all destructors + /// for thread-local variables that might be running after the main function of the thread. /// /// In terms of [atomic memory orderings], the completion of the associated /// thread synchronizes with this function returning. diff --git a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs index b042bd0c3c72..9507b71106dd 100644 --- a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs +++ b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs @@ -733,10 +733,42 @@ pub fn vaddvq_u64(a: uint64x2_t) -> u64 { unsafe { simd_reduce_add_ordered(a, 0) } } #[doc = "Multi-vector floating-point absolute maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f16)"] +#[inline(always)] +#[target_feature(enable = "neon,faminmax")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))] +#[unstable(feature = "faminmax", issue = "137933")] +pub fn vamax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.famax.v4f16" + )] + fn _vamax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { _vamax_f16(a, b) } +} +#[doc = "Multi-vector floating-point absolute maximum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f16)"] +#[inline(always)] +#[target_feature(enable = "neon,faminmax")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))] +#[unstable(feature = "faminmax", issue = "137933")] +pub fn vamaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.famax.v8f16" + )] + fn _vamaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { _vamaxq_f16(a, b) } +} +#[doc = "Multi-vector floating-point absolute maximum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f32)"] #[inline(always)] #[target_feature(enable = "neon,faminmax")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] pub fn vamax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { @@ -752,7 +784,7 @@ pub fn vamax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f32)"] #[inline(always)] #[target_feature(enable = "neon,faminmax")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] pub fn vamaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { @@ -768,7 +800,7 @@ pub fn vamaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f64)"] #[inline(always)] #[target_feature(enable = "neon,faminmax")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))] #[unstable(feature = "faminmax", issue = "137933")] pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { @@ -781,10 +813,42 @@ pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe { _vamaxq_f64(a, b) } } #[doc = "Multi-vector floating-point absolute minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f16)"] +#[inline(always)] +#[target_feature(enable = "neon,faminmax")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))] +#[unstable(feature = "faminmax", issue = "137933")] +pub fn vamin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.famin.v4f16" + )] + fn _vamin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { _vamin_f16(a, b) } +} +#[doc = "Multi-vector floating-point absolute minimum"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f16)"] +#[inline(always)] +#[target_feature(enable = "neon,faminmax")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))] +#[unstable(feature = "faminmax", issue = "137933")] +pub fn vaminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.famin.v8f16" + )] + fn _vaminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { _vaminq_f16(a, b) } +} +#[doc = "Multi-vector floating-point absolute minimum"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f32)"] #[inline(always)] #[target_feature(enable = "neon,faminmax")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] pub fn vamin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { @@ -800,7 +864,7 @@ pub fn vamin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f32)"] #[inline(always)] #[target_feature(enable = "neon,faminmax")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] pub fn vaminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { @@ -816,7 +880,7 @@ pub fn vaminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f64)"] #[inline(always)] #[target_feature(enable = "neon,faminmax")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))] #[unstable(feature = "faminmax", issue = "137933")] pub fn vaminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { @@ -9491,68 +9555,6 @@ pub fn vdivq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { pub fn vdivh_f16(a: f16, b: f16) -> f16 { a / b } -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(test, assert_instr(sdot, LANE = 0))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub fn vdot_laneq_s32(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - let c: int32x4_t = vreinterpretq_s32_s8(c); - unsafe { - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vdot_s32(a, b, vreinterpret_s8_s32(c)) - } -} -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(test, assert_instr(sdot, LANE = 0))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub fn vdotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - let c: int32x4_t = vreinterpretq_s32_s8(c); - unsafe { - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vdotq_s32(a, b, vreinterpretq_s8_s32(c)) - } -} -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(test, assert_instr(udot, LANE = 0))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub fn vdot_laneq_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 2); - let c: uint32x4_t = vreinterpretq_u32_u8(c); - unsafe { - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vdot_u32(a, b, vreinterpret_u8_u32(c)) - } -} -#[doc = "Dot product arithmetic (indexed)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"] -#[inline(always)] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(test, assert_instr(udot, LANE = 0))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub fn vdotq_laneq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); - let c: uint32x4_t = vreinterpretq_u32_u8(c); - unsafe { - let c: uint32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vdotq_u32(a, b, vreinterpretq_u8_u32(c)) - } -} #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f64)"] #[inline(always)] @@ -11172,7 +11174,7 @@ pub fn vfmsd_laneq_f64(a: f64, b: f64, c: float64x2_t) -> f64 { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(test, assert_instr(ldr))] @@ -11184,7 +11186,7 @@ pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(test, assert_instr(ldr))] @@ -11196,7 +11198,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11207,7 +11209,7 @@ pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11218,7 +11220,7 @@ pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11229,7 +11231,7 @@ pub unsafe fn vld1_f64(ptr: *const f64) -> float64x1_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11240,7 +11242,7 @@ pub unsafe fn vld1q_f64(ptr: *const f64) -> float64x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11251,7 +11253,7 @@ pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11262,7 +11264,7 @@ pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11273,7 +11275,7 @@ pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11284,7 +11286,7 @@ pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11295,7 +11297,7 @@ pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11306,7 +11308,7 @@ pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11317,7 +11319,7 @@ pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11328,7 +11330,7 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11339,7 +11341,7 @@ pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11350,7 +11352,7 @@ pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11361,7 +11363,7 @@ pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11372,7 +11374,7 @@ pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11383,7 +11385,7 @@ pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11394,7 +11396,7 @@ pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11405,7 +11407,7 @@ pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11416,7 +11418,7 @@ pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11427,7 +11429,7 @@ pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11438,7 +11440,7 @@ pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11449,7 +11451,7 @@ pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] @@ -11460,7 +11462,7 @@ pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ldr))] @@ -11471,7 +11473,7 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ldr))] @@ -11482,7 +11484,7 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11500,7 +11502,7 @@ pub unsafe fn vld1_f64_x2(a: *const f64) -> float64x1x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11518,7 +11520,7 @@ pub unsafe fn vld1_f64_x3(a: *const f64) -> float64x1x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11536,7 +11538,7 @@ pub unsafe fn vld1_f64_x4(a: *const f64) -> float64x1x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11554,7 +11556,7 @@ pub unsafe fn vld1q_f64_x2(a: *const f64) -> float64x2x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11572,7 +11574,7 @@ pub unsafe fn vld1q_f64_x3(a: *const f64) -> float64x2x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11590,7 +11592,7 @@ pub unsafe fn vld1q_f64_x4(a: *const f64) -> float64x2x4_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11608,7 +11610,7 @@ pub unsafe fn vld2_dup_f64(a: *const f64) -> float64x1x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11626,7 +11628,7 @@ pub unsafe fn vld2q_dup_f64(a: *const f64) -> float64x2x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11644,7 +11646,7 @@ pub unsafe fn vld2q_dup_s64(a: *const i64) -> int64x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11662,7 +11664,7 @@ pub unsafe fn vld2_f64(a: *const f64) -> float64x1x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] @@ -11682,7 +11684,7 @@ pub unsafe fn vld2_lane_f64(a: *const f64, b: float64x1x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] @@ -11702,7 +11704,7 @@ pub unsafe fn vld2_lane_s64(a: *const i64, b: int64x1x2_t) -> i #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] @@ -11715,7 +11717,7 @@ pub unsafe fn vld2_lane_p64(a: *const p64, b: poly64x1x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] @@ -11728,7 +11730,7 @@ pub unsafe fn vld2_lane_u64(a: *const u64, b: uint64x1x2_t) -> #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -11740,7 +11742,7 @@ pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -11755,7 +11757,7 @@ pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -11767,7 +11769,7 @@ pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -11782,7 +11784,7 @@ pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11800,7 +11802,7 @@ pub unsafe fn vld2q_f64(a: *const f64) -> float64x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11818,7 +11820,7 @@ pub unsafe fn vld2q_s64(a: *const i64) -> int64x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] @@ -11839,7 +11841,7 @@ pub unsafe fn vld2q_lane_f64(a: *const f64, b: float64x2x2_t) - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] @@ -11859,7 +11861,7 @@ pub unsafe fn vld2q_lane_s8(a: *const i8, b: int8x16x2_t) -> in #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] @@ -11879,7 +11881,7 @@ pub unsafe fn vld2q_lane_s64(a: *const i64, b: int64x2x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] @@ -11892,7 +11894,7 @@ pub unsafe fn vld2q_lane_p64(a: *const p64, b: poly64x2x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] @@ -11905,7 +11907,7 @@ pub unsafe fn vld2q_lane_u8(a: *const u8, b: uint8x16x2_t) -> u #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] @@ -11918,7 +11920,7 @@ pub unsafe fn vld2q_lane_u64(a: *const u64, b: uint64x2x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] @@ -11931,7 +11933,7 @@ pub unsafe fn vld2q_lane_p8(a: *const p8, b: poly8x16x2_t) -> p #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -11943,7 +11945,7 @@ pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -11958,7 +11960,7 @@ pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -11970,7 +11972,7 @@ pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -11985,7 +11987,7 @@ pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12003,7 +12005,7 @@ pub unsafe fn vld3_dup_f64(a: *const f64) -> float64x1x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12021,7 +12023,7 @@ pub unsafe fn vld3q_dup_f64(a: *const f64) -> float64x2x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12039,7 +12041,7 @@ pub unsafe fn vld3q_dup_s64(a: *const i64) -> int64x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12057,7 +12059,7 @@ pub unsafe fn vld3_f64(a: *const f64) -> float64x1x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] @@ -12083,7 +12085,7 @@ pub unsafe fn vld3_lane_f64(a: *const f64, b: float64x1x3_t) -> #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] @@ -12096,7 +12098,7 @@ pub unsafe fn vld3_lane_p64(a: *const p64, b: poly64x1x3_t) -> #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] @@ -12122,7 +12124,7 @@ pub unsafe fn vld3_lane_s64(a: *const i64, b: int64x1x3_t) -> i #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] @@ -12135,7 +12137,7 @@ pub unsafe fn vld3_lane_u64(a: *const u64, b: uint64x1x3_t) -> #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -12147,7 +12149,7 @@ pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -12163,7 +12165,7 @@ pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -12175,7 +12177,7 @@ pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -12191,7 +12193,7 @@ pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12209,7 +12211,7 @@ pub unsafe fn vld3q_f64(a: *const f64) -> float64x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12227,7 +12229,7 @@ pub unsafe fn vld3q_s64(a: *const i64) -> int64x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] @@ -12253,7 +12255,7 @@ pub unsafe fn vld3q_lane_f64(a: *const f64, b: float64x2x3_t) - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] @@ -12266,7 +12268,7 @@ pub unsafe fn vld3q_lane_p64(a: *const p64, b: poly64x2x3_t) -> #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] @@ -12292,7 +12294,7 @@ pub unsafe fn vld3q_lane_s8(a: *const i8, b: int8x16x3_t) -> in #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] @@ -12318,7 +12320,7 @@ pub unsafe fn vld3q_lane_s64(a: *const i64, b: int64x2x3_t) -> #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] @@ -12331,7 +12333,7 @@ pub unsafe fn vld3q_lane_u8(a: *const u8, b: uint8x16x3_t) -> u #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] @@ -12344,7 +12346,7 @@ pub unsafe fn vld3q_lane_u64(a: *const u64, b: uint64x2x3_t) -> #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] @@ -12357,7 +12359,7 @@ pub unsafe fn vld3q_lane_p8(a: *const p8, b: poly8x16x3_t) -> p #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -12369,7 +12371,7 @@ pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -12385,7 +12387,7 @@ pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -12397,7 +12399,7 @@ pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -12413,7 +12415,7 @@ pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4r))] @@ -12431,7 +12433,7 @@ pub unsafe fn vld4_dup_f64(a: *const f64) -> float64x1x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4r))] @@ -12449,7 +12451,7 @@ pub unsafe fn vld4q_dup_f64(a: *const f64) -> float64x2x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4r))] @@ -12467,7 +12469,7 @@ pub unsafe fn vld4q_dup_s64(a: *const i64) -> int64x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12485,7 +12487,7 @@ pub unsafe fn vld4_f64(a: *const f64) -> float64x1x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] @@ -12512,7 +12514,7 @@ pub unsafe fn vld4_lane_f64(a: *const f64, b: float64x1x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] @@ -12539,7 +12541,7 @@ pub unsafe fn vld4_lane_s64(a: *const i64, b: int64x1x4_t) -> i #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] @@ -12552,7 +12554,7 @@ pub unsafe fn vld4_lane_p64(a: *const p64, b: poly64x1x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] @@ -12565,7 +12567,7 @@ pub unsafe fn vld4_lane_u64(a: *const u64, b: uint64x1x4_t) -> #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -12577,7 +12579,7 @@ pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -12594,7 +12596,7 @@ pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -12606,7 +12608,7 @@ pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -12623,7 +12625,7 @@ pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12641,7 +12643,7 @@ pub unsafe fn vld4q_f64(a: *const f64) -> float64x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12659,7 +12661,7 @@ pub unsafe fn vld4q_s64(a: *const i64) -> int64x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] @@ -12686,7 +12688,7 @@ pub unsafe fn vld4q_lane_f64(a: *const f64, b: float64x2x4_t) - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] @@ -12713,7 +12715,7 @@ pub unsafe fn vld4q_lane_s8(a: *const i8, b: int8x16x4_t) -> in #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] @@ -12740,7 +12742,7 @@ pub unsafe fn vld4q_lane_s64(a: *const i64, b: int64x2x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] @@ -12753,7 +12755,7 @@ pub unsafe fn vld4q_lane_p64(a: *const p64, b: poly64x2x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] @@ -12766,7 +12768,7 @@ pub unsafe fn vld4q_lane_u8(a: *const u8, b: uint8x16x4_t) -> u #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] @@ -12779,7 +12781,7 @@ pub unsafe fn vld4q_lane_u64(a: *const u64, b: uint64x2x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] @@ -12792,7 +12794,7 @@ pub unsafe fn vld4q_lane_p8(a: *const p8, b: poly8x16x4_t) -> p #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12804,7 +12806,7 @@ pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -12821,7 +12823,7 @@ pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -12833,7 +12835,7 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -12847,10 +12849,241 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t { ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; ret_val } +#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub unsafe fn vldap1_lane_s64(ptr: *const i64, src: int64x1_t) -> int64x1_t { + static_assert!(LANE == 0); + let atomic_src = crate::sync::atomic::AtomicI64::from_ptr(ptr as *mut i64); + simd_insert!( + src, + LANE as u32, + atomic_src.load(crate::sync::atomic::Ordering::Acquire) + ) +} +#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub unsafe fn vldap1q_lane_s64(ptr: *const i64, src: int64x2_t) -> int64x2_t { + static_assert_uimm_bits!(LANE, 1); + let atomic_src = crate::sync::atomic::AtomicI64::from_ptr(ptr as *mut i64); + simd_insert!( + src, + LANE as u32, + atomic_src.load(crate::sync::atomic::Ordering::Acquire) + ) +} +#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub unsafe fn vldap1q_lane_f64(ptr: *const f64, src: float64x2_t) -> float64x2_t { + static_assert_uimm_bits!(LANE, 1); + transmute(vldap1q_lane_s64::(ptr as *mut i64, transmute(src))) +} +#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub unsafe fn vldap1_lane_u64(ptr: *const u64, src: uint64x1_t) -> uint64x1_t { + static_assert!(LANE == 0); + transmute(vldap1_lane_s64::(ptr as *mut i64, transmute(src))) +} +#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub unsafe fn vldap1q_lane_u64(ptr: *const u64, src: uint64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 1); + transmute(vldap1q_lane_s64::(ptr as *mut i64, transmute(src))) +} +#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub unsafe fn vldap1_lane_p64(ptr: *const p64, src: poly64x1_t) -> poly64x1_t { + static_assert!(LANE == 0); + transmute(vldap1_lane_s64::(ptr as *mut i64, transmute(src))) +} +#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub unsafe fn vldap1q_lane_p64(ptr: *const p64, src: poly64x2_t) -> poly64x2_t { + static_assert_uimm_bits!(LANE, 1); + transmute(vldap1q_lane_s64::(ptr as *mut i64, transmute(src))) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2_lane_f16(a: float16x4_t, b: uint8x8_t) -> float16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + transmute(vluti2_lane_s16::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_f16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2q_lane_f16(a: float16x8_t, b: uint8x8_t) -> float16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + transmute(vluti2q_lane_s16::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2_lane_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t { + static_assert!(INDEX >= 0 && INDEX <= 1); + transmute(vluti2_lane_s8::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2q_lane_u8(a: uint8x16_t, b: uint8x8_t) -> uint8x16_t { + static_assert!(INDEX >= 0 && INDEX <= 1); + transmute(vluti2q_lane_s8::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2_lane_u16(a: uint16x4_t, b: uint8x8_t) -> uint16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + transmute(vluti2_lane_s16::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2q_lane_u16(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + transmute(vluti2q_lane_s16::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2_lane_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x16_t { + static_assert!(INDEX >= 0 && INDEX <= 1); + transmute(vluti2_lane_s8::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2q_lane_p8(a: poly8x16_t, b: uint8x8_t) -> poly8x16_t { + static_assert!(INDEX >= 0 && INDEX <= 1); + transmute(vluti2q_lane_s8::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2_lane_p16(a: poly16x4_t, b: uint8x8_t) -> poly16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + transmute(vluti2_lane_s16::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2q_lane_p16(a: poly16x8_t, b: uint8x8_t) -> poly16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + transmute(vluti2q_lane_s16::(transmute(a), b)) +} #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 1))] @@ -12870,7 +13103,7 @@ pub unsafe fn vluti2_lane_s8(a: int8x8_t, b: uint8x8_t) -> int8 #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 1))] @@ -12890,7 +13123,7 @@ pub unsafe fn vluti2q_lane_s8(a: int8x16_t, b: uint8x8_t) -> in #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 1))] @@ -12910,7 +13143,7 @@ pub unsafe fn vluti2_lane_s16(a: int16x4_t, b: uint8x8_t) -> in #[doc = "Lookup table read with 2-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 1))] @@ -12928,113 +13161,219 @@ pub unsafe fn vluti2q_lane_s16(a: int16x8_t, b: uint8x8_t) -> i _vluti2q_lane_s16(a, b, LANE) } #[doc = "Lookup table read with 2-bit indices"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] -#[cfg_attr(test, assert_instr(nop, LANE = 1))] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] #[rustc_legacy_const_generics(2)] -pub unsafe fn vluti2_lane_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t { - static_assert!(LANE >= 0 && LANE <= 1); - transmute(vluti2_lane_s8::(transmute(a), b)) +pub unsafe fn vluti2_laneq_f16(a: float16x4_t, b: uint8x16_t) -> float16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 7); + transmute(vluti2_laneq_s16::(transmute(a), b)) } #[doc = "Lookup table read with 2-bit indices"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] -#[cfg_attr(test, assert_instr(nop, LANE = 1))] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] #[rustc_legacy_const_generics(2)] -pub unsafe fn vluti2q_lane_u8(a: uint8x16_t, b: uint8x8_t) -> uint8x16_t { - static_assert!(LANE >= 0 && LANE <= 1); - transmute(vluti2q_lane_s8::(transmute(a), b)) +pub unsafe fn vluti2q_laneq_f16(a: float16x8_t, b: uint8x16_t) -> float16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 7); + transmute(vluti2q_laneq_s16::(transmute(a), b)) } #[doc = "Lookup table read with 2-bit indices"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] -#[cfg_attr(test, assert_instr(nop, LANE = 1))] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] #[rustc_legacy_const_generics(2)] -pub unsafe fn vluti2_lane_u16(a: uint16x4_t, b: uint8x8_t) -> uint16x8_t { - static_assert!(LANE >= 0 && LANE <= 3); - transmute(vluti2_lane_s16::(transmute(a), b)) +pub unsafe fn vluti2_laneq_u8(a: uint8x8_t, b: uint8x16_t) -> uint8x16_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + transmute(vluti2_laneq_s8::(transmute(a), b)) } #[doc = "Lookup table read with 2-bit indices"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] -#[cfg_attr(test, assert_instr(nop, LANE = 1))] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] #[rustc_legacy_const_generics(2)] -pub unsafe fn vluti2q_lane_u16(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t { - static_assert!(LANE >= 0 && LANE <= 3); - transmute(vluti2q_lane_s16::(transmute(a), b)) +pub unsafe fn vluti2q_laneq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + transmute(vluti2q_laneq_s8::(transmute(a), b)) } #[doc = "Lookup table read with 2-bit indices"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] -#[cfg_attr(test, assert_instr(nop, LANE = 1))] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] #[rustc_legacy_const_generics(2)] -pub unsafe fn vluti2_lane_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x16_t { - static_assert!(LANE >= 0 && LANE <= 1); - transmute(vluti2_lane_s8::(transmute(a), b)) +pub unsafe fn vluti2_laneq_u16(a: uint16x4_t, b: uint8x16_t) -> uint16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 7); + transmute(vluti2_laneq_s16::(transmute(a), b)) } #[doc = "Lookup table read with 2-bit indices"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] -#[cfg_attr(test, assert_instr(nop, LANE = 1))] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] #[rustc_legacy_const_generics(2)] -pub unsafe fn vluti2q_lane_p8(a: poly8x16_t, b: uint8x8_t) -> poly8x16_t { - static_assert!(LANE >= 0 && LANE <= 1); - transmute(vluti2q_lane_s8::(transmute(a), b)) +pub unsafe fn vluti2q_laneq_u16(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 7); + transmute(vluti2q_laneq_s16::(transmute(a), b)) } #[doc = "Lookup table read with 2-bit indices"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] -#[cfg_attr(test, assert_instr(nop, LANE = 1))] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] #[rustc_legacy_const_generics(2)] -pub unsafe fn vluti2_lane_p16(a: poly16x4_t, b: uint8x8_t) -> poly16x8_t { - static_assert!(LANE >= 0 && LANE <= 3); - transmute(vluti2_lane_s16::(transmute(a), b)) +pub unsafe fn vluti2_laneq_p8(a: poly8x8_t, b: uint8x16_t) -> poly8x16_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + transmute(vluti2_laneq_s8::(transmute(a), b)) } #[doc = "Lookup table read with 2-bit indices"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] -#[cfg_attr(test, assert_instr(nop, LANE = 1))] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] #[rustc_legacy_const_generics(2)] -pub unsafe fn vluti2q_lane_p16(a: poly16x8_t, b: uint8x8_t) -> poly16x8_t { - static_assert!(LANE >= 0 && LANE <= 3); - transmute(vluti2q_lane_s16::(transmute(a), b)) +pub unsafe fn vluti2q_laneq_p8(a: poly8x16_t, b: uint8x16_t) -> poly8x16_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + transmute(vluti2q_laneq_s8::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2_laneq_p16(a: poly16x4_t, b: uint8x16_t) -> poly16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 7); + transmute(vluti2_laneq_s16::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2q_laneq_p16(a: poly16x8_t, b: uint8x16_t) -> poly16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 7); + transmute(vluti2q_laneq_s16::(transmute(a), b)) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2_laneq_s8(a: int8x8_t, b: uint8x16_t) -> int8x16_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vluti2.laneq.v16i8.v8i8" + )] + fn _vluti2_laneq_s8(a: int8x8_t, b: uint8x16_t, n: i32) -> int8x16_t; + } + _vluti2_laneq_s8(a, b, INDEX) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2q_laneq_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t { + static_assert!(INDEX >= 0 && INDEX <= 3); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vluti2.laneq.v16i8.v16i8" + )] + fn _vluti2q_laneq_s8(a: int8x16_t, b: uint8x16_t, n: i32) -> int8x16_t; + } + _vluti2q_laneq_s8(a, b, INDEX) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2_laneq_s16(a: int16x4_t, b: uint8x16_t) -> int16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 7); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vluti2.laneq.v8i16.v4i16" + )] + fn _vluti2_laneq_s16(a: int16x4_t, b: uint8x16_t, n: i32) -> int16x8_t; + } + _vluti2_laneq_s16(a, b, INDEX) +} +#[doc = "Lookup table read with 2-bit indices"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[target_feature(enable = "neon,lut")] +#[cfg_attr(test, assert_instr(nop, INDEX = 1))] +#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vluti2q_laneq_s16(a: int16x8_t, b: uint8x16_t) -> int16x8_t { + static_assert!(INDEX >= 0 && INDEX <= 7); + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vluti2.laneq.v8i16.v8i16" + )] + fn _vluti2q_laneq_s16(a: int16x8_t, b: uint8x16_t, n: i32) -> int16x8_t; + } + _vluti2q_laneq_s16(a, b, INDEX) } #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_f16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut,fp16")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -13047,7 +13386,7 @@ pub unsafe fn vluti4q_lane_f16_x2(a: float16x8x2_t, b: uint8x8_ #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_u16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -13060,7 +13399,7 @@ pub unsafe fn vluti4q_lane_u16_x2(a: uint16x8x2_t, b: uint8x8_t #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_p16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -13073,7 +13412,7 @@ pub unsafe fn vluti4q_lane_p16_x2(a: poly16x8x2_t, b: uint8x8_t #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_s16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -13093,7 +13432,7 @@ pub unsafe fn vluti4q_lane_s16_x2(a: int16x8x2_t, b: uint8x8_t) #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -13113,7 +13452,7 @@ pub unsafe fn vluti4q_lane_s8(a: int8x16_t, b: uint8x8_t) -> in #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -13126,7 +13465,7 @@ pub unsafe fn vluti4q_lane_u8(a: uint8x16_t, b: uint8x8_t) -> u #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -13139,7 +13478,7 @@ pub unsafe fn vluti4q_lane_p8(a: poly8x16_t, b: uint8x8_t) -> p #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_f16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut,fp16")] #[cfg_attr(test, assert_instr(nop, LANE = 3))] @@ -13155,7 +13494,7 @@ pub unsafe fn vluti4q_laneq_f16_x2( #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_u16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 3))] @@ -13168,7 +13507,7 @@ pub unsafe fn vluti4q_laneq_u16_x2(a: uint16x8x2_t, b: uint8x16 #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_p16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 3))] @@ -13181,7 +13520,7 @@ pub unsafe fn vluti4q_laneq_p16_x2(a: poly16x8x2_t, b: uint8x16 #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_s16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 3))] @@ -13201,7 +13540,7 @@ pub unsafe fn vluti4q_laneq_s16_x2(a: int16x8x2_t, b: uint8x16_ #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -13221,7 +13560,7 @@ pub unsafe fn vluti4q_laneq_s8(a: int8x16_t, b: uint8x16_t) -> #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -13234,7 +13573,7 @@ pub unsafe fn vluti4q_laneq_u8(a: uint8x16_t, b: uint8x16_t) -> #[doc = "Lookup table read with 4-bit indices"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,lut")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -24113,6 +24452,86 @@ pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4 let x: uint32x2_t = vrsubhn_u64(b, c); unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) } } +#[doc = "Multi-vector floating-point adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f16)"] +#[inline(always)] +#[unstable(feature = "stdarch_neon_fp8", issue = "none")] +#[target_feature(enable = "neon,fp8")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))] +pub fn vscale_f16(vn: float16x4_t, vm: int16x4_t) -> float16x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fp8.fscale.v4f16" + )] + fn _vscale_f16(vn: float16x4_t, vm: int16x4_t) -> float16x4_t; + } + unsafe { _vscale_f16(vn, vm) } +} +#[doc = "Multi-vector floating-point adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f16)"] +#[inline(always)] +#[unstable(feature = "stdarch_neon_fp8", issue = "none")] +#[target_feature(enable = "neon,fp8")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))] +pub fn vscaleq_f16(vn: float16x8_t, vm: int16x8_t) -> float16x8_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fp8.fscale.v8f16" + )] + fn _vscaleq_f16(vn: float16x8_t, vm: int16x8_t) -> float16x8_t; + } + unsafe { _vscaleq_f16(vn, vm) } +} +#[doc = "Multi-vector floating-point adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f32)"] +#[inline(always)] +#[unstable(feature = "stdarch_neon_fp8", issue = "none")] +#[target_feature(enable = "neon,fp8")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))] +pub fn vscale_f32(vn: float32x2_t, vm: int32x2_t) -> float32x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fp8.fscale.v2f32" + )] + fn _vscale_f32(vn: float32x2_t, vm: int32x2_t) -> float32x2_t; + } + unsafe { _vscale_f32(vn, vm) } +} +#[doc = "Multi-vector floating-point adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f32)"] +#[inline(always)] +#[unstable(feature = "stdarch_neon_fp8", issue = "none")] +#[target_feature(enable = "neon,fp8")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))] +pub fn vscaleq_f32(vn: float32x4_t, vm: int32x4_t) -> float32x4_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fp8.fscale.v4f32" + )] + fn _vscaleq_f32(vn: float32x4_t, vm: int32x4_t) -> float32x4_t; + } + unsafe { _vscaleq_f32(vn, vm) } +} +#[doc = "Multi-vector floating-point adjust exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f64)"] +#[inline(always)] +#[unstable(feature = "stdarch_neon_fp8", issue = "none")] +#[target_feature(enable = "neon,fp8")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))] +pub fn vscaleq_f64(vn: float64x2_t, vm: int64x2_t) -> float64x2_t { + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fp8.fscale.v2f64" + )] + fn _vscaleq_f64(vn: float64x2_t, vm: int64x2_t) -> float64x2_t; + } + unsafe { _vscaleq_f64(vn, vm) } +} #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f64)"] #[inline(always)] @@ -25418,7 +25837,7 @@ pub fn vsrid_n_u64(a: u64, b: u64) -> u64 { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(test, assert_instr(str))] @@ -25431,7 +25850,7 @@ pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(test, assert_instr(str))] @@ -25444,7 +25863,7 @@ pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25456,7 +25875,7 @@ pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25468,7 +25887,7 @@ pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25480,7 +25899,7 @@ pub unsafe fn vst1_f64(ptr: *mut f64, a: float64x1_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25492,7 +25911,7 @@ pub unsafe fn vst1q_f64(ptr: *mut f64, a: float64x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25504,7 +25923,7 @@ pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25516,7 +25935,7 @@ pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25528,7 +25947,7 @@ pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25540,7 +25959,7 @@ pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25552,7 +25971,7 @@ pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25564,7 +25983,7 @@ pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25576,7 +25995,7 @@ pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25588,7 +26007,7 @@ pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25600,7 +26019,7 @@ pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25612,7 +26031,7 @@ pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25624,7 +26043,7 @@ pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25636,7 +26055,7 @@ pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25648,7 +26067,7 @@ pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25660,7 +26079,7 @@ pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25672,7 +26091,7 @@ pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25684,7 +26103,7 @@ pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25696,7 +26115,7 @@ pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25708,7 +26127,7 @@ pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25720,7 +26139,7 @@ pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] @@ -25732,7 +26151,7 @@ pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(str))] @@ -25744,7 +26163,7 @@ pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(str))] @@ -25756,7 +26175,7 @@ pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] @@ -25774,7 +26193,7 @@ pub unsafe fn vst1_f64_x2(a: *mut f64, b: float64x1x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] @@ -25792,7 +26211,7 @@ pub unsafe fn vst1q_f64_x2(a: *mut f64, b: float64x2x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] @@ -25810,7 +26229,7 @@ pub unsafe fn vst1_f64_x3(a: *mut f64, b: float64x1x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] @@ -25828,7 +26247,7 @@ pub unsafe fn vst1q_f64_x3(a: *mut f64, b: float64x2x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] @@ -25852,7 +26271,7 @@ pub unsafe fn vst1_f64_x4(a: *mut f64, b: float64x1x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st1))] @@ -25876,7 +26295,7 @@ pub unsafe fn vst1q_f64_x4(a: *mut f64, b: float64x2x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -25889,7 +26308,7 @@ pub unsafe fn vst1_lane_f64(a: *mut f64, b: float64x1_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] @@ -25902,7 +26321,7 @@ pub unsafe fn vst1q_lane_f64(a: *mut f64, b: float64x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -25920,7 +26339,7 @@ pub unsafe fn vst2_f64(a: *mut f64, b: float64x1x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] @@ -25940,7 +26359,7 @@ pub unsafe fn vst2_lane_f64(a: *mut f64, b: float64x1x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] @@ -25960,7 +26379,7 @@ pub unsafe fn vst2_lane_s64(a: *mut i64, b: int64x1x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] @@ -25973,7 +26392,7 @@ pub unsafe fn vst2_lane_p64(a: *mut p64, b: poly64x1x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] @@ -25986,7 +26405,7 @@ pub unsafe fn vst2_lane_u64(a: *mut u64, b: uint64x1x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26004,7 +26423,7 @@ pub unsafe fn vst2q_f64(a: *mut f64, b: float64x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26022,7 +26441,7 @@ pub unsafe fn vst2q_s64(a: *mut i64, b: int64x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] @@ -26042,7 +26461,7 @@ pub unsafe fn vst2q_lane_f64(a: *mut f64, b: float64x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] @@ -26062,7 +26481,7 @@ pub unsafe fn vst2q_lane_s8(a: *mut i8, b: int8x16x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] @@ -26082,7 +26501,7 @@ pub unsafe fn vst2q_lane_s64(a: *mut i64, b: int64x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] @@ -26095,7 +26514,7 @@ pub unsafe fn vst2q_lane_p64(a: *mut p64, b: poly64x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] @@ -26108,7 +26527,7 @@ pub unsafe fn vst2q_lane_u8(a: *mut u8, b: uint8x16x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] @@ -26121,7 +26540,7 @@ pub unsafe fn vst2q_lane_u64(a: *mut u64, b: uint64x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] @@ -26134,7 +26553,7 @@ pub unsafe fn vst2q_lane_p8(a: *mut p8, b: poly8x16x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st2))] @@ -26145,7 +26564,7 @@ pub unsafe fn vst2q_p64(a: *mut p64, b: poly64x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26156,7 +26575,7 @@ pub unsafe fn vst2q_u64(a: *mut u64, b: uint64x2x2_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26174,7 +26593,7 @@ pub unsafe fn vst3_f64(a: *mut f64, b: float64x1x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] @@ -26194,7 +26613,7 @@ pub unsafe fn vst3_lane_f64(a: *mut f64, b: float64x1x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] @@ -26214,7 +26633,7 @@ pub unsafe fn vst3_lane_s64(a: *mut i64, b: int64x1x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] @@ -26227,7 +26646,7 @@ pub unsafe fn vst3_lane_p64(a: *mut p64, b: poly64x1x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26240,7 +26659,7 @@ pub unsafe fn vst3_lane_u64(a: *mut u64, b: uint64x1x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26258,7 +26677,7 @@ pub unsafe fn vst3q_f64(a: *mut f64, b: float64x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26276,7 +26695,7 @@ pub unsafe fn vst3q_s64(a: *mut i64, b: int64x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] @@ -26296,7 +26715,7 @@ pub unsafe fn vst3q_lane_f64(a: *mut f64, b: float64x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] @@ -26316,7 +26735,7 @@ pub unsafe fn vst3q_lane_s8(a: *mut i8, b: int8x16x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] @@ -26336,7 +26755,7 @@ pub unsafe fn vst3q_lane_s64(a: *mut i64, b: int64x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] @@ -26349,7 +26768,7 @@ pub unsafe fn vst3q_lane_p64(a: *mut p64, b: poly64x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26362,7 +26781,7 @@ pub unsafe fn vst3q_lane_u8(a: *mut u8, b: uint8x16x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26375,7 +26794,7 @@ pub unsafe fn vst3q_lane_u64(a: *mut u64, b: uint64x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26388,7 +26807,7 @@ pub unsafe fn vst3q_lane_p8(a: *mut p8, b: poly8x16x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] @@ -26399,7 +26818,7 @@ pub unsafe fn vst3q_p64(a: *mut p64, b: poly64x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26410,7 +26829,7 @@ pub unsafe fn vst3q_u64(a: *mut u64, b: uint64x2x3_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26428,7 +26847,7 @@ pub unsafe fn vst4_f64(a: *mut f64, b: float64x1x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] @@ -26455,7 +26874,7 @@ pub unsafe fn vst4_lane_f64(a: *mut f64, b: float64x1x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] @@ -26482,7 +26901,7 @@ pub unsafe fn vst4_lane_s64(a: *mut i64, b: int64x1x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] @@ -26495,7 +26914,7 @@ pub unsafe fn vst4_lane_p64(a: *mut p64, b: poly64x1x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26508,7 +26927,7 @@ pub unsafe fn vst4_lane_u64(a: *mut u64, b: uint64x1x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26526,7 +26945,7 @@ pub unsafe fn vst4q_f64(a: *mut f64, b: float64x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26544,7 +26963,7 @@ pub unsafe fn vst4q_s64(a: *mut i64, b: int64x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] @@ -26571,7 +26990,7 @@ pub unsafe fn vst4q_lane_f64(a: *mut f64, b: float64x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] @@ -26598,7 +27017,7 @@ pub unsafe fn vst4q_lane_s8(a: *mut i8, b: int8x16x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] @@ -26625,7 +27044,7 @@ pub unsafe fn vst4q_lane_s64(a: *mut i64, b: int64x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] @@ -26638,7 +27057,7 @@ pub unsafe fn vst4q_lane_p64(a: *mut p64, b: poly64x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26651,7 +27070,7 @@ pub unsafe fn vst4q_lane_u8(a: *mut u8, b: uint8x16x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26664,7 +27083,7 @@ pub unsafe fn vst4q_lane_u64(a: *mut u64, b: uint64x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26677,7 +27096,7 @@ pub unsafe fn vst4q_lane_p8(a: *mut p8, b: poly8x16x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[target_feature(enable = "neon,aes")] @@ -26688,7 +27107,7 @@ pub unsafe fn vst4q_p64(a: *mut p64, b: poly64x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -26696,6 +27115,102 @@ pub unsafe fn vst4q_p64(a: *mut p64, b: poly64x2x4_t) { pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) { vst4q_s64(transmute(a), transmute(b)) } +#[doc = "Store-Release a single-element structure from one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_f64)"] +#[inline(always)] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub fn vstl1_lane_f64(ptr: *mut f64, val: float64x1_t) { + static_assert!(LANE == 0); + unsafe { vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } +} +#[doc = "Store-Release a single-element structure from one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_f64)"] +#[inline(always)] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub fn vstl1q_lane_f64(ptr: *mut f64, val: float64x2_t) { + static_assert_uimm_bits!(LANE, 1); + unsafe { vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } +} +#[doc = "Store-Release a single-element structure from one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_u64)"] +#[inline(always)] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub fn vstl1_lane_u64(ptr: *mut u64, val: uint64x1_t) { + static_assert!(LANE == 0); + unsafe { vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } +} +#[doc = "Store-Release a single-element structure from one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_u64)"] +#[inline(always)] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub fn vstl1q_lane_u64(ptr: *mut u64, val: uint64x2_t) { + static_assert_uimm_bits!(LANE, 1); + unsafe { vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } +} +#[doc = "Store-Release a single-element structure from one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_p64)"] +#[inline(always)] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub fn vstl1_lane_p64(ptr: *mut p64, val: poly64x1_t) { + static_assert!(LANE == 0); + unsafe { vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } +} +#[doc = "Store-Release a single-element structure from one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_p64)"] +#[inline(always)] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub fn vstl1q_lane_p64(ptr: *mut p64, val: poly64x2_t) { + static_assert_uimm_bits!(LANE, 1); + unsafe { vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } +} +#[doc = "Store-Release a single-element structure from one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_s64)"] +#[inline(always)] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub fn vstl1_lane_s64(ptr: *mut i64, val: int64x1_t) { + static_assert!(LANE == 0); + let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64; + unsafe { + let lane: i64 = simd_extract!(val, LANE as u32); + (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release) + } +} +#[doc = "Store-Release a single-element structure from one lane of one register."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_s64)"] +#[inline(always)] +#[target_feature(enable = "neon,rcpc3")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +pub fn vstl1q_lane_s64(ptr: *mut i64, val: int64x2_t) { + static_assert_uimm_bits!(LANE, 1); + let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64; + unsafe { + let lane: i64 = simd_extract!(val, LANE as u32); + (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release) + } +} #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f64)"] #[inline(always)] @@ -26904,37 +27419,6 @@ pub fn vsubw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { simd_sub(a, simd_cast(c)) } } -#[doc = "Dot product index form with signed and unsigned integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_laneq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(test, assert_instr(sudot, LANE = 3))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub fn vsudot_laneq_s32(a: int32x2_t, b: int8x8_t, c: uint8x16_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: uint32x4_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vusdot_s32(a, transmute(c), b) - } -} -#[doc = "Dot product index form with signed and unsigned integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_laneq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(test, assert_instr(sudot, LANE = 3))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub fn vsudotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: uint8x16_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - unsafe { - let c: uint32x4_t = transmute(c); - let c: uint32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vusdotq_s32(a, transmute(c), b) - } -} #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"] #[inline(always)] @@ -28274,37 +28758,6 @@ pub fn vuqadds_s32(a: i32, b: u32) -> i32 { } unsafe { _vuqadds_s32(a, b) } } -#[doc = "Dot product index form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(test, assert_instr(usdot, LANE = 3))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub fn vusdot_laneq_s32(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - let c: int32x4_t = vreinterpretq_s32_s8(c); - unsafe { - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vusdot_s32(a, b, vreinterpret_s8_s32(c)) - } -} -#[doc = "Dot product index form with unsigned and signed integers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"] -#[inline(always)] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(test, assert_instr(usdot, LANE = 3))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub fn vusdotq_laneq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - let c: int32x4_t = vreinterpretq_s32_s8(c); - unsafe { - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vusdotq_s32(a, b, vreinterpretq_s8_s32(c)) - } -} #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f16)"] #[inline(always)] diff --git a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs index 324ff73f62a1..3b67208182cb 100644 --- a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs +++ b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs @@ -9816,6 +9816,200 @@ pub fn vdotq_lane_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x8_ simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"] +#[inline(always)] +#[cfg(target_endian = "little")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sdot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] +pub fn vdot_laneq_s32(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let c: int32x4_t = transmute(c); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vdot_s32(a, b, transmute(c)) + } +} +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"] +#[inline(always)] +#[cfg(target_endian = "big")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sdot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] +pub fn vdot_laneq_s32(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; + let b: int8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; + let c: int8x16_t = + unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; + unsafe { + let c: int32x4_t = transmute(c); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + let ret_val: int32x2_t = vdot_s32(a, b, transmute(c)); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"] +#[inline(always)] +#[cfg(target_endian = "little")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sdot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] +pub fn vdotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let c: int32x4_t = transmute(c); + let c: int32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vdotq_s32(a, b, transmute(c)) + } +} +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"] +#[inline(always)] +#[cfg(target_endian = "big")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sdot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] +pub fn vdotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; + let b: int8x16_t = + unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; + let c: int8x16_t = + unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; + unsafe { + let c: int32x4_t = transmute(c); + let c: int32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + let ret_val: int32x4_t = vdotq_s32(a, b, transmute(c)); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"] +#[inline(always)] +#[cfg(target_endian = "little")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(udot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] +pub fn vdot_laneq_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let c: uint32x4_t = transmute(c); + let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vdot_u32(a, b, transmute(c)) + } +} +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"] +#[inline(always)] +#[cfg(target_endian = "big")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(udot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] +pub fn vdot_laneq_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 2); + let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; + let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; + let c: uint8x16_t = + unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; + unsafe { + let c: uint32x4_t = transmute(c); + let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + let ret_val: uint32x2_t = vdot_u32(a, b, transmute(c)); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"] +#[inline(always)] +#[cfg(target_endian = "little")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(udot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] +pub fn vdotq_laneq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let c: uint32x4_t = transmute(c); + let c: uint32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vdotq_u32(a, b, transmute(c)) + } +} +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"] +#[inline(always)] +#[cfg(target_endian = "big")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(udot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] +pub fn vdotq_laneq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; + let b: uint8x16_t = + unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; + let c: uint8x16_t = + unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; + unsafe { + let c: uint32x4_t = transmute(c); + let c: uint32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + let ret_val: uint32x4_t = vdotq_u32(a, b, transmute(c)); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "Dot product arithmetic (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_s32)"] #[inline(always)] @@ -12176,7 +12370,7 @@ pub fn vext_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -12201,7 +12395,7 @@ pub unsafe fn vext_s64(a: int64x1_t, _b: int64x1_t) -> int64x1_t { #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -14939,7 +15133,7 @@ pub fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[doc = "Load one single-element structure and replicate to all lanes of one register"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -14958,7 +15152,7 @@ pub unsafe fn vld1_dup_f16(ptr: *const f16) -> float16x4_t { #[doc = "Load one single-element structure and replicate to all lanes of one register"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -14977,7 +15171,7 @@ pub unsafe fn vld1q_dup_f16(ptr: *const f16) -> float16x8_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15000,7 +15194,7 @@ pub unsafe fn vld1_dup_f32(ptr: *const f32) -> float32x2_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15023,7 +15217,7 @@ pub unsafe fn vld1_dup_p16(ptr: *const p16) -> poly16x4_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15046,7 +15240,7 @@ pub unsafe fn vld1_dup_p8(ptr: *const p8) -> poly8x8_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15069,7 +15263,7 @@ pub unsafe fn vld1_dup_s16(ptr: *const i16) -> int16x4_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15092,7 +15286,7 @@ pub unsafe fn vld1_dup_s32(ptr: *const i32) -> int32x2_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15115,7 +15309,7 @@ pub unsafe fn vld1_dup_s8(ptr: *const i8) -> int8x8_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15138,7 +15332,7 @@ pub unsafe fn vld1_dup_u16(ptr: *const u16) -> uint16x4_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15161,7 +15355,7 @@ pub unsafe fn vld1_dup_u32(ptr: *const u32) -> uint32x2_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15184,7 +15378,7 @@ pub unsafe fn vld1_dup_u8(ptr: *const u8) -> uint8x8_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15207,7 +15401,7 @@ pub unsafe fn vld1q_dup_f32(ptr: *const f32) -> float32x4_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15230,7 +15424,7 @@ pub unsafe fn vld1q_dup_p16(ptr: *const p16) -> poly16x8_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15253,7 +15447,7 @@ pub unsafe fn vld1q_dup_p8(ptr: *const p8) -> poly8x16_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15276,7 +15470,7 @@ pub unsafe fn vld1q_dup_s16(ptr: *const i16) -> int16x8_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15299,7 +15493,7 @@ pub unsafe fn vld1q_dup_s32(ptr: *const i32) -> int32x4_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15322,7 +15516,7 @@ pub unsafe fn vld1q_dup_s64(ptr: *const i64) -> int64x2_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15345,7 +15539,7 @@ pub unsafe fn vld1q_dup_s8(ptr: *const i8) -> int8x16_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15368,7 +15562,7 @@ pub unsafe fn vld1q_dup_u16(ptr: *const u16) -> uint16x8_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15391,7 +15585,7 @@ pub unsafe fn vld1q_dup_u32(ptr: *const u32) -> uint32x4_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15414,7 +15608,7 @@ pub unsafe fn vld1q_dup_u64(ptr: *const u64) -> uint64x2_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15437,7 +15631,7 @@ pub unsafe fn vld1q_dup_u8(ptr: *const u8) -> uint8x16_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15469,7 +15663,7 @@ pub unsafe fn vld1_dup_p64(ptr: *const p64) -> poly64x1_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15501,7 +15695,7 @@ pub unsafe fn vld1_dup_s64(ptr: *const i64) -> int64x1_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15533,7 +15727,7 @@ pub unsafe fn vld1_dup_u64(ptr: *const u64) -> uint64x1_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[cfg(target_arch = "arm")] @@ -15551,7 +15745,7 @@ pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[cfg(target_arch = "arm")] @@ -15570,7 +15764,7 @@ pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[cfg(target_arch = "arm")] @@ -15588,7 +15782,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[cfg(target_arch = "arm")] @@ -15607,7 +15801,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15633,7 +15827,7 @@ pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15659,7 +15853,7 @@ pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15685,7 +15879,7 @@ pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15711,7 +15905,7 @@ pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15737,7 +15931,7 @@ pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15763,7 +15957,7 @@ pub unsafe fn vld1q_f16_x4(a: *const f16) -> float16x8x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -15776,7 +15970,7 @@ pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -15789,7 +15983,7 @@ pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -15802,7 +15996,7 @@ pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -15815,7 +16009,7 @@ pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -15828,7 +16022,7 @@ pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -15841,7 +16035,7 @@ pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -15854,7 +16048,7 @@ pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -15867,7 +16061,7 @@ pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -15880,7 +16074,7 @@ pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -15893,7 +16087,7 @@ pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -15906,7 +16100,7 @@ pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -15919,7 +16113,7 @@ pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -15932,7 +16126,7 @@ pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -15945,7 +16139,7 @@ pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,aes")] @@ -15958,7 +16152,7 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -15989,7 +16183,7 @@ pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16020,7 +16214,7 @@ pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16051,7 +16245,7 @@ pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16082,7 +16276,7 @@ pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16113,7 +16307,7 @@ pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16144,7 +16338,7 @@ pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t { #[doc = "Load one single-element structure to one lane of one register"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16164,7 +16358,7 @@ pub unsafe fn vld1_lane_f16(ptr: *const f16, src: float16x4_t) #[doc = "Load one single-element structure to one lane of one register"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16184,7 +16378,7 @@ pub unsafe fn vld1q_lane_f16(ptr: *const f16, src: float16x8_t) #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16209,7 +16403,7 @@ pub unsafe fn vld1_lane_f32(ptr: *const f32, src: float32x2_t) #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16234,7 +16428,7 @@ pub unsafe fn vld1_lane_p16(ptr: *const p16, src: poly16x4_t) - #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16259,7 +16453,7 @@ pub unsafe fn vld1_lane_p8(ptr: *const p8, src: poly8x8_t) -> p #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16284,7 +16478,7 @@ pub unsafe fn vld1_lane_s16(ptr: *const i16, src: int16x4_t) -> #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16309,7 +16503,7 @@ pub unsafe fn vld1_lane_s32(ptr: *const i32, src: int32x2_t) -> #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16334,7 +16528,7 @@ pub unsafe fn vld1_lane_s64(ptr: *const i64, src: int64x1_t) -> #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16359,7 +16553,7 @@ pub unsafe fn vld1_lane_s8(ptr: *const i8, src: int8x8_t) -> in #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16384,7 +16578,7 @@ pub unsafe fn vld1_lane_u16(ptr: *const u16, src: uint16x4_t) - #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16409,7 +16603,7 @@ pub unsafe fn vld1_lane_u32(ptr: *const u32, src: uint32x2_t) - #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16434,7 +16628,7 @@ pub unsafe fn vld1_lane_u64(ptr: *const u64, src: uint64x1_t) - #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16459,7 +16653,7 @@ pub unsafe fn vld1_lane_u8(ptr: *const u8, src: uint8x8_t) -> u #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16484,7 +16678,7 @@ pub unsafe fn vld1q_lane_f32(ptr: *const f32, src: float32x4_t) #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16509,7 +16703,7 @@ pub unsafe fn vld1q_lane_p16(ptr: *const p16, src: poly16x8_t) #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16534,7 +16728,7 @@ pub unsafe fn vld1q_lane_p8(ptr: *const p8, src: poly8x16_t) -> #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16559,7 +16753,7 @@ pub unsafe fn vld1q_lane_s16(ptr: *const i16, src: int16x8_t) - #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16584,7 +16778,7 @@ pub unsafe fn vld1q_lane_s32(ptr: *const i32, src: int32x4_t) - #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16609,7 +16803,7 @@ pub unsafe fn vld1q_lane_s64(ptr: *const i64, src: int64x2_t) - #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16634,7 +16828,7 @@ pub unsafe fn vld1q_lane_s8(ptr: *const i8, src: int8x16_t) -> #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16659,7 +16853,7 @@ pub unsafe fn vld1q_lane_u16(ptr: *const u16, src: uint16x8_t) #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16684,7 +16878,7 @@ pub unsafe fn vld1q_lane_u32(ptr: *const u32, src: uint32x4_t) #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16709,7 +16903,7 @@ pub unsafe fn vld1q_lane_u64(ptr: *const u64, src: uint64x2_t) #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16734,7 +16928,7 @@ pub unsafe fn vld1q_lane_u8(ptr: *const u8, src: uint8x16_t) -> #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16759,7 +16953,7 @@ pub unsafe fn vld1_lane_p64(ptr: *const p64, src: poly64x1_t) - #[doc = "Load one single-element structure to one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -16784,7 +16978,7 @@ pub unsafe fn vld1q_lane_p64(ptr: *const p64, src: poly64x2_t) #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,aes")] @@ -16802,7 +16996,7 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -16825,7 +17019,7 @@ pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -16848,7 +17042,7 @@ pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -16871,7 +17065,7 @@ pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -16895,7 +17089,7 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -16922,7 +17116,7 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -16946,7 +17140,7 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -16974,7 +17168,7 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -16998,7 +17192,7 @@ pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -17027,7 +17221,7 @@ pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -17040,7 +17234,7 @@ pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -17053,7 +17247,7 @@ pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -17066,7 +17260,7 @@ pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -17079,7 +17273,7 @@ pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -17092,7 +17286,7 @@ pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -17105,7 +17299,7 @@ pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -17118,7 +17312,7 @@ pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -17131,7 +17325,7 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17162,7 +17356,7 @@ pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17193,7 +17387,7 @@ pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17224,7 +17418,7 @@ pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17255,7 +17449,7 @@ pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17286,7 +17480,7 @@ pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17317,7 +17511,7 @@ pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17348,7 +17542,7 @@ pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17379,7 +17573,7 @@ pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17410,7 +17604,7 @@ pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17441,7 +17635,7 @@ pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17472,7 +17666,7 @@ pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17503,7 +17697,7 @@ pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17534,7 +17728,7 @@ pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17565,7 +17759,7 @@ pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17596,7 +17790,7 @@ pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17627,7 +17821,7 @@ pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17658,7 +17852,7 @@ pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17689,7 +17883,7 @@ pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17720,7 +17914,7 @@ pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17751,7 +17945,7 @@ pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17782,7 +17976,7 @@ pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17813,7 +18007,7 @@ pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17844,7 +18038,7 @@ pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -17875,7 +18069,7 @@ pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -17899,7 +18093,7 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -17926,7 +18120,7 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -17950,7 +18144,7 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -17978,7 +18172,7 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18002,7 +18196,7 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18031,7 +18225,7 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18055,7 +18249,7 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18094,7 +18288,7 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18118,7 +18312,7 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18164,7 +18358,7 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18188,7 +18382,7 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18241,7 +18435,7 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18265,7 +18459,7 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18292,7 +18486,7 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18316,7 +18510,7 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18344,7 +18538,7 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18368,7 +18562,7 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18397,7 +18591,7 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18421,7 +18615,7 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18448,7 +18642,7 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18472,7 +18666,7 @@ pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18500,7 +18694,7 @@ pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18524,7 +18718,7 @@ pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18553,7 +18747,7 @@ pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18577,7 +18771,7 @@ pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18604,7 +18798,7 @@ pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18628,7 +18822,7 @@ pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18656,7 +18850,7 @@ pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18680,7 +18874,7 @@ pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18709,7 +18903,7 @@ pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18733,7 +18927,7 @@ pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18760,7 +18954,7 @@ pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18784,7 +18978,7 @@ pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18812,7 +19006,7 @@ pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18836,7 +19030,7 @@ pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18865,7 +19059,7 @@ pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -18888,7 +19082,7 @@ pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -18911,7 +19105,7 @@ pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -18934,7 +19128,7 @@ pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -18958,7 +19152,7 @@ pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -18985,7 +19179,7 @@ pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19009,7 +19203,7 @@ pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19037,7 +19231,7 @@ pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19061,7 +19255,7 @@ pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19090,7 +19284,7 @@ pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19114,7 +19308,7 @@ pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19141,7 +19335,7 @@ pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19165,7 +19359,7 @@ pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19193,7 +19387,7 @@ pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19217,7 +19411,7 @@ pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19246,7 +19440,7 @@ pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19270,7 +19464,7 @@ pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19309,7 +19503,7 @@ pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19333,7 +19527,7 @@ pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19379,7 +19573,7 @@ pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19403,7 +19597,7 @@ pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19456,7 +19650,7 @@ pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19480,7 +19674,7 @@ pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19507,7 +19701,7 @@ pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19531,7 +19725,7 @@ pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19559,7 +19753,7 @@ pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19583,7 +19777,7 @@ pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19612,7 +19806,7 @@ pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19636,7 +19830,7 @@ pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19663,7 +19857,7 @@ pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19687,7 +19881,7 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19715,7 +19909,7 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -19739,7 +19933,7 @@ pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t { #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -19926,7 +20120,7 @@ unsafe fn vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t { #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -19950,7 +20144,7 @@ pub unsafe fn vld1q_dup_p64(ptr: *const p64) -> poly64x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -19969,7 +20163,7 @@ pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -19988,7 +20182,7 @@ pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20012,7 +20206,7 @@ pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20036,7 +20230,7 @@ pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -20052,7 +20246,7 @@ pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -20068,7 +20262,7 @@ pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -20084,7 +20278,7 @@ pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -20100,7 +20294,7 @@ pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -20116,7 +20310,7 @@ pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -20132,7 +20326,7 @@ pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -20148,7 +20342,7 @@ pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -20164,7 +20358,7 @@ pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20183,7 +20377,7 @@ pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20202,7 +20396,7 @@ pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20221,7 +20415,7 @@ pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20240,7 +20434,7 @@ pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20259,7 +20453,7 @@ pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20278,7 +20472,7 @@ pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20297,7 +20491,7 @@ pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20316,7 +20510,7 @@ pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -20339,7 +20533,7 @@ pub unsafe fn vld2_dup_p64(a: *const p64) -> poly64x1x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -20355,7 +20549,7 @@ pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20374,7 +20568,7 @@ pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -20397,7 +20591,7 @@ pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -20421,7 +20615,7 @@ pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -20448,7 +20642,7 @@ pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -20472,7 +20666,7 @@ pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -20511,7 +20705,7 @@ pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -20535,7 +20729,7 @@ pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -20562,7 +20756,7 @@ pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -20586,7 +20780,7 @@ pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -20613,7 +20807,7 @@ pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -20637,7 +20831,7 @@ pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -20664,7 +20858,7 @@ pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -20688,7 +20882,7 @@ pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -20715,7 +20909,7 @@ pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -20739,7 +20933,7 @@ pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -20766,7 +20960,7 @@ pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -20790,7 +20984,7 @@ pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -20829,7 +21023,7 @@ pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -20853,7 +21047,7 @@ pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -20880,7 +21074,7 @@ pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -20904,7 +21098,7 @@ pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -20931,7 +21125,7 @@ pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -20950,7 +21144,7 @@ pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -20969,7 +21163,7 @@ pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -20993,7 +21187,7 @@ pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t { #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21017,7 +21211,7 @@ pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21033,7 +21227,7 @@ pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21049,7 +21243,7 @@ pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21065,7 +21259,7 @@ pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21081,7 +21275,7 @@ pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21097,7 +21291,7 @@ pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21113,7 +21307,7 @@ pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21129,7 +21323,7 @@ pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21145,7 +21339,7 @@ pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21164,7 +21358,7 @@ pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21183,7 +21377,7 @@ pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21202,7 +21396,7 @@ pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21221,7 +21415,7 @@ pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21240,7 +21434,7 @@ pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21259,7 +21453,7 @@ pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21278,7 +21472,7 @@ pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21297,7 +21491,7 @@ pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21323,7 +21517,7 @@ pub unsafe fn vld2_lane_f16(a: *const f16, b: float16x4x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21349,7 +21543,7 @@ pub unsafe fn vld2q_lane_f16(a: *const f16, b: float16x8x2_t) - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21376,7 +21570,7 @@ pub unsafe fn vld2_lane_f16(a: *const f16, b: float16x4x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21407,7 +21601,7 @@ pub unsafe fn vld2q_lane_f16(a: *const f16, b: float16x8x2_t) - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21428,7 +21622,7 @@ pub unsafe fn vld2_lane_f32(a: *const f32, b: float32x2x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21450,7 +21644,7 @@ pub unsafe fn vld2q_lane_f32(a: *const f32, b: float32x4x2_t) - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21471,7 +21665,7 @@ pub unsafe fn vld2_lane_s8(a: *const i8, b: int8x8x2_t) -> int8 #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21492,7 +21686,7 @@ pub unsafe fn vld2_lane_s16(a: *const i16, b: int16x4x2_t) -> i #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21513,7 +21707,7 @@ pub unsafe fn vld2q_lane_s16(a: *const i16, b: int16x8x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21534,7 +21728,7 @@ pub unsafe fn vld2_lane_s32(a: *const i32, b: int32x2x2_t) -> i #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21555,7 +21749,7 @@ pub unsafe fn vld2q_lane_s32(a: *const i32, b: int32x4x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21579,7 +21773,7 @@ pub unsafe fn vld2_lane_f32(a: *const f32, b: float32x2x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21603,7 +21797,7 @@ pub unsafe fn vld2q_lane_f32(a: *const f32, b: float32x4x2_t) - #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21627,7 +21821,7 @@ pub unsafe fn vld2q_lane_s16(a: *const i16, b: int16x8x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21651,7 +21845,7 @@ pub unsafe fn vld2q_lane_s32(a: *const i32, b: int32x4x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21670,7 +21864,7 @@ pub unsafe fn vld2_lane_s8(a: *const i8, b: int8x8x2_t) -> int8 #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21694,7 +21888,7 @@ pub unsafe fn vld2_lane_s16(a: *const i16, b: int16x4x2_t) -> i #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21718,7 +21912,7 @@ pub unsafe fn vld2_lane_s32(a: *const i32, b: int32x2x2_t) -> i #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -21743,7 +21937,7 @@ pub unsafe fn vld2_lane_u8(a: *const u8, b: uint8x8x2_t) -> uin #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -21768,7 +21962,7 @@ pub unsafe fn vld2_lane_u16(a: *const u16, b: uint16x4x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -21793,7 +21987,7 @@ pub unsafe fn vld2q_lane_u16(a: *const u16, b: uint16x8x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -21818,7 +22012,7 @@ pub unsafe fn vld2_lane_u32(a: *const u32, b: uint32x2x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -21843,7 +22037,7 @@ pub unsafe fn vld2q_lane_u32(a: *const u32, b: uint32x4x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -21868,7 +22062,7 @@ pub unsafe fn vld2_lane_p8(a: *const p8, b: poly8x8x2_t) -> pol #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -21893,7 +22087,7 @@ pub unsafe fn vld2_lane_p16(a: *const p16, b: poly16x4x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -21918,7 +22112,7 @@ pub unsafe fn vld2q_lane_p16(a: *const p16, b: poly16x8x2_t) -> #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -21941,7 +22135,7 @@ pub unsafe fn vld2_p64(a: *const p64) -> poly64x1x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -21957,7 +22151,7 @@ pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -21976,7 +22170,7 @@ pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -21999,7 +22193,7 @@ pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -22023,7 +22217,7 @@ pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -22050,7 +22244,7 @@ pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -22074,7 +22268,7 @@ pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -22113,7 +22307,7 @@ pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -22137,7 +22331,7 @@ pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -22164,7 +22358,7 @@ pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -22188,7 +22382,7 @@ pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -22215,7 +22409,7 @@ pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -22239,7 +22433,7 @@ pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -22266,7 +22460,7 @@ pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -22290,7 +22484,7 @@ pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -22317,7 +22511,7 @@ pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -22341,7 +22535,7 @@ pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -22368,7 +22562,7 @@ pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -22392,7 +22586,7 @@ pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -22431,7 +22625,7 @@ pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -22455,7 +22649,7 @@ pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -22482,7 +22676,7 @@ pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -22506,7 +22700,7 @@ pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t { #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -22533,7 +22727,7 @@ pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t { #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -22552,7 +22746,7 @@ pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -22571,7 +22765,7 @@ pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22595,7 +22789,7 @@ pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22619,7 +22813,7 @@ pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22638,7 +22832,7 @@ pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22657,7 +22851,7 @@ pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22676,7 +22870,7 @@ pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22695,7 +22889,7 @@ pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22714,7 +22908,7 @@ pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22733,7 +22927,7 @@ pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22752,7 +22946,7 @@ pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22771,7 +22965,7 @@ pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -22790,7 +22984,7 @@ pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -22806,7 +23000,7 @@ pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -22822,7 +23016,7 @@ pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -22838,7 +23032,7 @@ pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -22854,7 +23048,7 @@ pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -22870,7 +23064,7 @@ pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -22886,7 +23080,7 @@ pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -22902,7 +23096,7 @@ pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -22918,7 +23112,7 @@ pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -22941,7 +23135,7 @@ pub unsafe fn vld3_dup_p64(a: *const p64) -> poly64x1x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -22957,7 +23151,7 @@ pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -22980,7 +23174,7 @@ pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -23004,7 +23198,7 @@ pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -23032,7 +23226,7 @@ pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -23056,7 +23250,7 @@ pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -23102,7 +23296,7 @@ pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -23126,7 +23320,7 @@ pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -23154,7 +23348,7 @@ pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -23178,7 +23372,7 @@ pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -23206,7 +23400,7 @@ pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -23230,7 +23424,7 @@ pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -23258,7 +23452,7 @@ pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -23282,7 +23476,7 @@ pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -23310,7 +23504,7 @@ pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -23334,7 +23528,7 @@ pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -23362,7 +23556,7 @@ pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -23386,7 +23580,7 @@ pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -23432,7 +23626,7 @@ pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -23456,7 +23650,7 @@ pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -23484,7 +23678,7 @@ pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -23508,7 +23702,7 @@ pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -23536,7 +23730,7 @@ pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23555,7 +23749,7 @@ pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23574,7 +23768,7 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -23598,7 +23792,7 @@ pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t { #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -23622,7 +23816,7 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23641,7 +23835,7 @@ pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23660,7 +23854,7 @@ pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23679,7 +23873,7 @@ pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23698,7 +23892,7 @@ pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23717,7 +23911,7 @@ pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23736,7 +23930,7 @@ pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23755,7 +23949,7 @@ pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23774,7 +23968,7 @@ pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -23790,7 +23984,7 @@ pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -23806,7 +24000,7 @@ pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -23822,7 +24016,7 @@ pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -23838,7 +24032,7 @@ pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -23854,7 +24048,7 @@ pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -23870,7 +24064,7 @@ pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -23886,7 +24080,7 @@ pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -23902,7 +24096,7 @@ pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t { #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -23929,7 +24123,7 @@ pub unsafe fn vld3_lane_f16(a: *const f16, b: float16x4x3_t) -> #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -23956,7 +24150,7 @@ pub unsafe fn vld3q_lane_f16(a: *const f16, b: float16x8x3_t) - #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -23988,7 +24182,7 @@ pub unsafe fn vld3_lane_f16(a: *const f16, b: float16x4x3_t) -> #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -24020,7 +24214,7 @@ pub unsafe fn vld3q_lane_f16(a: *const f16, b: float16x8x3_t) - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -24047,7 +24241,7 @@ pub unsafe fn vld3_lane_f32(a: *const f32, b: float32x2x3_t) -> #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -24074,7 +24268,7 @@ pub unsafe fn vld3q_lane_f32(a: *const f32, b: float32x4x3_t) - #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -24099,7 +24293,7 @@ pub unsafe fn vld3_lane_f32(a: *const f32, b: float32x2x3_t) -> #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -24126,7 +24320,7 @@ pub unsafe fn vld3_lane_s8(a: *const i8, b: int8x8x3_t) -> int8 #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -24153,7 +24347,7 @@ pub unsafe fn vld3_lane_s16(a: *const i16, b: int16x4x3_t) -> i #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -24180,7 +24374,7 @@ pub unsafe fn vld3q_lane_s16(a: *const i16, b: int16x8x3_t) -> #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -24207,7 +24401,7 @@ pub unsafe fn vld3_lane_s32(a: *const i32, b: int32x2x3_t) -> i #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -24234,7 +24428,7 @@ pub unsafe fn vld3q_lane_s32(a: *const i32, b: int32x4x3_t) -> #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -24259,7 +24453,7 @@ pub unsafe fn vld3_lane_s8(a: *const i8, b: int8x8x3_t) -> int8 #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -24284,7 +24478,7 @@ pub unsafe fn vld3_lane_s16(a: *const i16, b: int16x4x3_t) -> i #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -24309,7 +24503,7 @@ pub unsafe fn vld3q_lane_s16(a: *const i16, b: int16x8x3_t) -> #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -24334,7 +24528,7 @@ pub unsafe fn vld3_lane_s32(a: *const i32, b: int32x2x3_t) -> i #[doc = "Load multiple 3-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -24359,7 +24553,7 @@ pub unsafe fn vld3q_lane_s32(a: *const i32, b: int32x4x3_t) -> #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24384,7 +24578,7 @@ pub unsafe fn vld3_lane_u8(a: *const u8, b: uint8x8x3_t) -> uin #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24409,7 +24603,7 @@ pub unsafe fn vld3_lane_u16(a: *const u16, b: uint16x4x3_t) -> #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24434,7 +24628,7 @@ pub unsafe fn vld3q_lane_u16(a: *const u16, b: uint16x8x3_t) -> #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24459,7 +24653,7 @@ pub unsafe fn vld3_lane_u32(a: *const u32, b: uint32x2x3_t) -> #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24484,7 +24678,7 @@ pub unsafe fn vld3q_lane_u32(a: *const u32, b: uint32x4x3_t) -> #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24509,7 +24703,7 @@ pub unsafe fn vld3_lane_p8(a: *const p8, b: poly8x8x3_t) -> pol #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24534,7 +24728,7 @@ pub unsafe fn vld3_lane_p16(a: *const p16, b: poly16x4x3_t) -> #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24559,7 +24753,7 @@ pub unsafe fn vld3q_lane_p16(a: *const p16, b: poly16x8x3_t) -> #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -24582,7 +24776,7 @@ pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24601,7 +24795,7 @@ pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -24617,7 +24811,7 @@ pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24640,7 +24834,7 @@ pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -24664,7 +24858,7 @@ pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -24692,7 +24886,7 @@ pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -24716,7 +24910,7 @@ pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -24762,7 +24956,7 @@ pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -24786,7 +24980,7 @@ pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -24814,7 +25008,7 @@ pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -24838,7 +25032,7 @@ pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -24866,7 +25060,7 @@ pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -24890,7 +25084,7 @@ pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -24918,7 +25112,7 @@ pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -24942,7 +25136,7 @@ pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -24970,7 +25164,7 @@ pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -24994,7 +25188,7 @@ pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -25022,7 +25216,7 @@ pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -25046,7 +25240,7 @@ pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -25092,7 +25286,7 @@ pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -25116,7 +25310,7 @@ pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -25144,7 +25338,7 @@ pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -25168,7 +25362,7 @@ pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -25196,7 +25390,7 @@ pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t { #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -25221,7 +25415,7 @@ pub unsafe fn vld3q_lane_f32(a: *const f32, b: float32x4x3_t) - #[doc = "Load single 4-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg(target_arch = "arm")] @@ -25239,7 +25433,7 @@ pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg(target_arch = "arm")] @@ -25257,7 +25451,7 @@ pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr( @@ -25280,7 +25474,7 @@ pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr( @@ -25303,7 +25497,7 @@ pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -25319,7 +25513,7 @@ pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -25335,7 +25529,7 @@ pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -25351,7 +25545,7 @@ pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -25367,7 +25561,7 @@ pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -25383,7 +25577,7 @@ pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -25399,7 +25593,7 @@ pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -25415,7 +25609,7 @@ pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -25431,7 +25625,7 @@ pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -25450,7 +25644,7 @@ pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -25469,7 +25663,7 @@ pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -25488,7 +25682,7 @@ pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -25507,7 +25701,7 @@ pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -25526,7 +25720,7 @@ pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -25545,7 +25739,7 @@ pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -25564,7 +25758,7 @@ pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -25583,7 +25777,7 @@ pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -25602,7 +25796,7 @@ pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -25625,7 +25819,7 @@ pub unsafe fn vld4_dup_p64(a: *const p64) -> poly64x1x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -25641,7 +25835,7 @@ pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25664,7 +25858,7 @@ pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -25688,7 +25882,7 @@ pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -25717,7 +25911,7 @@ pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -25741,7 +25935,7 @@ pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -25794,7 +25988,7 @@ pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -25818,7 +26012,7 @@ pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -25847,7 +26041,7 @@ pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -25871,7 +26065,7 @@ pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -25900,7 +26094,7 @@ pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -25924,7 +26118,7 @@ pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -25953,7 +26147,7 @@ pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -25977,7 +26171,7 @@ pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -26006,7 +26200,7 @@ pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -26030,7 +26224,7 @@ pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -26059,7 +26253,7 @@ pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -26083,7 +26277,7 @@ pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -26136,7 +26330,7 @@ pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -26160,7 +26354,7 @@ pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -26189,7 +26383,7 @@ pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -26213,7 +26407,7 @@ pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -26242,7 +26436,7 @@ pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg(target_arch = "arm")] @@ -26260,7 +26454,7 @@ pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg(target_arch = "arm")] @@ -26278,7 +26472,7 @@ pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr( @@ -26301,7 +26495,7 @@ pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t { #[doc = "Load single 4-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr( @@ -26324,7 +26518,7 @@ pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26343,7 +26537,7 @@ pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26362,7 +26556,7 @@ pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26381,7 +26575,7 @@ pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26400,7 +26594,7 @@ pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26419,7 +26613,7 @@ pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26438,7 +26632,7 @@ pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26457,7 +26651,7 @@ pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26476,7 +26670,7 @@ pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26492,7 +26686,7 @@ pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26508,7 +26702,7 @@ pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26524,7 +26718,7 @@ pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26540,7 +26734,7 @@ pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26556,7 +26750,7 @@ pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26572,7 +26766,7 @@ pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26588,7 +26782,7 @@ pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26604,7 +26798,7 @@ pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t { #[doc = "Load multiple 4-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26632,7 +26826,7 @@ pub unsafe fn vld4_lane_f16(a: *const f16, b: float16x4x4_t) -> #[doc = "Load multiple 4-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26660,7 +26854,7 @@ pub unsafe fn vld4q_lane_f16(a: *const f16, b: float16x8x4_t) - #[doc = "Load multiple 4-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr( @@ -26692,7 +26886,7 @@ pub unsafe fn vld4_lane_f16(a: *const f16, b: float16x4x4_t) -> #[doc = "Load multiple 4-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr( @@ -26724,7 +26918,7 @@ pub unsafe fn vld4q_lane_f16(a: *const f16, b: float16x8x4_t) - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26752,7 +26946,7 @@ pub unsafe fn vld4_lane_f32(a: *const f32, b: float32x2x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26780,7 +26974,7 @@ pub unsafe fn vld4q_lane_f32(a: *const f32, b: float32x4x4_t) - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26808,7 +27002,7 @@ pub unsafe fn vld4_lane_s8(a: *const i8, b: int8x8x4_t) -> int8 #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26836,7 +27030,7 @@ pub unsafe fn vld4_lane_s16(a: *const i16, b: int16x4x4_t) -> i #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26864,7 +27058,7 @@ pub unsafe fn vld4q_lane_s16(a: *const i16, b: int16x8x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26892,7 +27086,7 @@ pub unsafe fn vld4_lane_s32(a: *const i32, b: int32x2x4_t) -> i #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -26920,7 +27114,7 @@ pub unsafe fn vld4q_lane_s32(a: *const i32, b: int32x4x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26946,7 +27140,7 @@ pub unsafe fn vld4_lane_f32(a: *const f32, b: float32x2x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26972,7 +27166,7 @@ pub unsafe fn vld4q_lane_f32(a: *const f32, b: float32x4x4_t) - #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -26998,7 +27192,7 @@ pub unsafe fn vld4_lane_s8(a: *const i8, b: int8x8x4_t) -> int8 #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -27024,7 +27218,7 @@ pub unsafe fn vld4_lane_s16(a: *const i16, b: int16x4x4_t) -> i #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -27050,7 +27244,7 @@ pub unsafe fn vld4q_lane_s16(a: *const i16, b: int16x8x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -27076,7 +27270,7 @@ pub unsafe fn vld4_lane_s32(a: *const i32, b: int32x2x4_t) -> i #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -27102,7 +27296,7 @@ pub unsafe fn vld4q_lane_s32(a: *const i32, b: int32x4x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27127,7 +27321,7 @@ pub unsafe fn vld4_lane_u8(a: *const u8, b: uint8x8x4_t) -> uin #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27152,7 +27346,7 @@ pub unsafe fn vld4_lane_u16(a: *const u16, b: uint16x4x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27177,7 +27371,7 @@ pub unsafe fn vld4q_lane_u16(a: *const u16, b: uint16x8x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27202,7 +27396,7 @@ pub unsafe fn vld4_lane_u32(a: *const u32, b: uint32x2x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27227,7 +27421,7 @@ pub unsafe fn vld4q_lane_u32(a: *const u32, b: uint32x4x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27252,7 +27446,7 @@ pub unsafe fn vld4_lane_p8(a: *const p8, b: poly8x8x4_t) -> pol #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27277,7 +27471,7 @@ pub unsafe fn vld4_lane_p16(a: *const p16, b: poly16x4x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27302,7 +27496,7 @@ pub unsafe fn vld4q_lane_p16(a: *const p16, b: poly16x8x4_t) -> #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,aes")] @@ -27325,7 +27519,7 @@ pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -27344,7 +27538,7 @@ pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -27360,7 +27554,7 @@ pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27383,7 +27577,7 @@ pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -27407,7 +27601,7 @@ pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -27436,7 +27630,7 @@ pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -27460,7 +27654,7 @@ pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -27513,7 +27707,7 @@ pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -27537,7 +27731,7 @@ pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -27566,7 +27760,7 @@ pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -27590,7 +27784,7 @@ pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -27619,7 +27813,7 @@ pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -27643,7 +27837,7 @@ pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -27672,7 +27866,7 @@ pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -27696,7 +27890,7 @@ pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -27725,7 +27919,7 @@ pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -27749,7 +27943,7 @@ pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -27778,7 +27972,7 @@ pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -27802,7 +27996,7 @@ pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -27855,7 +28049,7 @@ pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -27879,7 +28073,7 @@ pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -27908,7 +28102,7 @@ pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -27932,7 +28126,7 @@ pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t { #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -27961,7 +28155,7 @@ pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t { #[doc = "Store SIMD&FP register (immediate offset)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldrq_p128)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -42565,13 +42759,13 @@ pub fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42588,13 +42782,13 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42615,13 +42809,13 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42638,13 +42832,13 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42665,13 +42859,13 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42688,13 +42882,13 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42715,13 +42909,13 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42738,13 +42932,13 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42765,13 +42959,13 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42788,13 +42982,13 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42812,13 +43006,13 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42835,13 +43029,13 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42862,13 +43056,13 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42885,13 +43079,13 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42912,13 +43106,13 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42935,13 +43129,13 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42962,13 +43156,13 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -42985,13 +43179,13 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43009,13 +43203,13 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43032,13 +43226,13 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43059,13 +43253,13 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43082,13 +43276,13 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43109,13 +43303,13 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43132,13 +43326,13 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43159,13 +43353,13 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43182,13 +43376,13 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43213,13 +43407,13 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43236,13 +43430,13 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43263,13 +43457,13 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43286,13 +43480,13 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43313,13 +43507,13 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43336,13 +43530,13 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43363,13 +43557,13 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43386,13 +43580,13 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43417,13 +43611,13 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43440,13 +43634,13 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43467,13 +43661,13 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43490,13 +43684,13 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43517,13 +43711,13 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43540,13 +43734,13 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43567,13 +43761,13 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43590,13 +43784,13 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43621,13 +43815,13 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43644,13 +43838,13 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43671,13 +43865,13 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43694,13 +43888,13 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43721,13 +43915,13 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43744,13 +43938,13 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43771,13 +43965,13 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43794,13 +43988,13 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43821,13 +44015,13 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43844,13 +44038,13 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43872,13 +44066,13 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43895,13 +44089,13 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43922,13 +44116,13 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43945,13 +44139,13 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43972,13 +44166,13 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -43995,13 +44189,13 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44022,13 +44216,13 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44045,13 +44239,13 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44072,13 +44266,13 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44095,13 +44289,13 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44121,13 +44315,13 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44144,13 +44338,13 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44171,13 +44365,13 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44194,13 +44388,13 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44221,13 +44415,13 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44244,13 +44438,13 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44272,13 +44466,13 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44295,13 +44489,13 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44322,13 +44516,13 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44345,13 +44539,13 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44372,13 +44566,13 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44395,13 +44589,13 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44422,13 +44616,13 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44445,13 +44639,13 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44472,13 +44666,13 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44495,13 +44689,13 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44521,13 +44715,13 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44544,13 +44738,13 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44571,13 +44765,13 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44594,13 +44788,13 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44621,13 +44815,13 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44644,13 +44838,13 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44672,13 +44866,13 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44695,13 +44889,13 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44722,13 +44916,13 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44745,13 +44939,13 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44772,13 +44966,13 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44795,13 +44989,13 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44821,13 +45015,13 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44844,13 +45038,13 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44868,13 +45062,13 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44891,13 +45085,13 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44915,13 +45109,13 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44938,13 +45132,13 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44965,13 +45159,13 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -44988,13 +45182,13 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -45014,13 +45208,13 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"] #[inline(always)] #[cfg(target_endian = "little")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -45037,13 +45231,13 @@ pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"] #[inline(always)] #[cfg(target_endian = "big")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop) )] -#[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") @@ -64890,7 +65084,7 @@ pub fn vsriq_n_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -64908,7 +65102,7 @@ pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -64926,7 +65120,7 @@ pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -64944,7 +65138,7 @@ pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -64962,7 +65156,7 @@ pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -64982,7 +65176,7 @@ pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -65002,7 +65196,7 @@ pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65020,7 +65214,7 @@ pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65038,7 +65232,7 @@ pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -65058,7 +65252,7 @@ pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -65078,7 +65272,7 @@ pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65103,7 +65297,7 @@ pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65128,7 +65322,7 @@ pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -65154,7 +65348,7 @@ pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(st1))] @@ -65180,7 +65374,7 @@ pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65194,7 +65388,7 @@ pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65208,7 +65402,7 @@ pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65222,7 +65416,7 @@ pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65236,7 +65430,7 @@ pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65250,7 +65444,7 @@ pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65264,7 +65458,7 @@ pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65278,7 +65472,7 @@ pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65292,7 +65486,7 @@ pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65306,7 +65500,7 @@ pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65320,7 +65514,7 @@ pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65334,7 +65528,7 @@ pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65348,7 +65542,7 @@ pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65362,7 +65556,7 @@ pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65376,7 +65570,7 @@ pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65390,7 +65584,7 @@ pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65404,7 +65598,7 @@ pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65418,7 +65612,7 @@ pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65432,7 +65626,7 @@ pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65446,7 +65640,7 @@ pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65460,7 +65654,7 @@ pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65474,7 +65668,7 @@ pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65488,7 +65682,7 @@ pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65502,7 +65696,7 @@ pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -65516,7 +65710,7 @@ pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -65532,7 +65726,7 @@ pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -65548,7 +65742,7 @@ pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -65567,7 +65761,7 @@ pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -65586,7 +65780,7 @@ pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -65605,7 +65799,7 @@ pub unsafe fn vst1_f32_x3(a: *mut f32, b: float32x2x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -65624,7 +65818,7 @@ pub unsafe fn vst1q_f32_x3(a: *mut f32, b: float32x4x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -65646,7 +65840,7 @@ pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -65668,7 +65862,7 @@ pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -65693,7 +65887,7 @@ pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -65718,7 +65912,7 @@ pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65738,7 +65932,7 @@ pub unsafe fn vst1_lane_f16(a: *mut f16, b: float16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65758,7 +65952,7 @@ pub unsafe fn vst1q_lane_f16(a: *mut f16, b: float16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65783,7 +65977,7 @@ pub unsafe fn vst1_lane_f32(a: *mut f32, b: float32x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65808,7 +66002,7 @@ pub unsafe fn vst1q_lane_f32(a: *mut f32, b: float32x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65833,7 +66027,7 @@ pub unsafe fn vst1_lane_s8(a: *mut i8, b: int8x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65858,7 +66052,7 @@ pub unsafe fn vst1q_lane_s8(a: *mut i8, b: int8x16_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65883,7 +66077,7 @@ pub unsafe fn vst1_lane_s16(a: *mut i16, b: int16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65908,7 +66102,7 @@ pub unsafe fn vst1q_lane_s16(a: *mut i16, b: int16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65933,7 +66127,7 @@ pub unsafe fn vst1_lane_s32(a: *mut i32, b: int32x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65958,7 +66152,7 @@ pub unsafe fn vst1q_lane_s32(a: *mut i32, b: int32x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -65983,7 +66177,7 @@ pub unsafe fn vst1q_lane_s64(a: *mut i64, b: int64x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66008,7 +66202,7 @@ pub unsafe fn vst1_lane_u8(a: *mut u8, b: uint8x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66033,7 +66227,7 @@ pub unsafe fn vst1q_lane_u8(a: *mut u8, b: uint8x16_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66058,7 +66252,7 @@ pub unsafe fn vst1_lane_u16(a: *mut u16, b: uint16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66083,7 +66277,7 @@ pub unsafe fn vst1q_lane_u16(a: *mut u16, b: uint16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66108,7 +66302,7 @@ pub unsafe fn vst1_lane_u32(a: *mut u32, b: uint32x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66133,7 +66327,7 @@ pub unsafe fn vst1q_lane_u32(a: *mut u32, b: uint32x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66158,7 +66352,7 @@ pub unsafe fn vst1q_lane_u64(a: *mut u64, b: uint64x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66183,7 +66377,7 @@ pub unsafe fn vst1_lane_p8(a: *mut p8, b: poly8x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66208,7 +66402,7 @@ pub unsafe fn vst1q_lane_p8(a: *mut p8, b: poly8x16_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66233,7 +66427,7 @@ pub unsafe fn vst1_lane_p16(a: *mut p16, b: poly16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66258,7 +66452,7 @@ pub unsafe fn vst1q_lane_p16(a: *mut p16, b: poly16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,aes")] @@ -66283,7 +66477,7 @@ pub unsafe fn vst1_lane_p64(a: *mut p64, b: poly64x1_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66308,7 +66502,7 @@ pub unsafe fn vst1_lane_s64(a: *mut i64, b: int64x1_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -66333,7 +66527,7 @@ pub unsafe fn vst1_lane_u64(a: *mut u64, b: uint64x1_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -66356,7 +66550,7 @@ pub unsafe fn vst1_p64_x2(a: *mut p64, b: poly64x1x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -66379,7 +66573,7 @@ pub unsafe fn vst1_p64_x3(a: *mut p64, b: poly64x1x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -66402,7 +66596,7 @@ pub unsafe fn vst1_p64_x4(a: *mut p64, b: poly64x1x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -66425,7 +66619,7 @@ pub unsafe fn vst1q_p64_x2(a: *mut p64, b: poly64x2x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -66448,7 +66642,7 @@ pub unsafe fn vst1q_p64_x3(a: *mut p64, b: poly64x2x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -66471,7 +66665,7 @@ pub unsafe fn vst1q_p64_x4(a: *mut p64, b: poly64x2x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66490,7 +66684,7 @@ pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66509,7 +66703,7 @@ pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66528,7 +66722,7 @@ pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66547,7 +66741,7 @@ pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66566,7 +66760,7 @@ pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66585,7 +66779,7 @@ pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66604,7 +66798,7 @@ pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66623,7 +66817,7 @@ pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -66639,7 +66833,7 @@ pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -66655,7 +66849,7 @@ pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -66671,7 +66865,7 @@ pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -66687,7 +66881,7 @@ pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -66703,7 +66897,7 @@ pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -66719,7 +66913,7 @@ pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -66735,7 +66929,7 @@ pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -66751,7 +66945,7 @@ pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66770,7 +66964,7 @@ pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66789,7 +66983,7 @@ pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66808,7 +67002,7 @@ pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66827,7 +67021,7 @@ pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66846,7 +67040,7 @@ pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66865,7 +67059,7 @@ pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66884,7 +67078,7 @@ pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -66903,7 +67097,7 @@ pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -66919,7 +67113,7 @@ pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -66935,7 +67129,7 @@ pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -66951,7 +67145,7 @@ pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -66967,7 +67161,7 @@ pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -66983,7 +67177,7 @@ pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -66999,7 +67193,7 @@ pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -67015,7 +67209,7 @@ pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] @@ -67031,7 +67225,7 @@ pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -67050,7 +67244,7 @@ pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -67069,7 +67263,7 @@ pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -67088,7 +67282,7 @@ pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -67107,7 +67301,7 @@ pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -67126,7 +67320,7 @@ pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -67145,7 +67339,7 @@ pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -67164,7 +67358,7 @@ pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -67183,7 +67377,7 @@ pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -67199,7 +67393,7 @@ pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -67215,7 +67409,7 @@ pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -67231,7 +67425,7 @@ pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -67247,7 +67441,7 @@ pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -67263,7 +67457,7 @@ pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -67279,7 +67473,7 @@ pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -67295,7 +67489,7 @@ pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -67311,7 +67505,7 @@ pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67334,7 +67528,7 @@ pub unsafe fn vst1_u8_x2(a: *mut u8, b: uint8x8x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67357,7 +67551,7 @@ pub unsafe fn vst1_u8_x3(a: *mut u8, b: uint8x8x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67380,7 +67574,7 @@ pub unsafe fn vst1_u8_x4(a: *mut u8, b: uint8x8x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67403,7 +67597,7 @@ pub unsafe fn vst1q_u8_x2(a: *mut u8, b: uint8x16x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67426,7 +67620,7 @@ pub unsafe fn vst1q_u8_x3(a: *mut u8, b: uint8x16x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67449,7 +67643,7 @@ pub unsafe fn vst1q_u8_x4(a: *mut u8, b: uint8x16x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67472,7 +67666,7 @@ pub unsafe fn vst1_u16_x2(a: *mut u16, b: uint16x4x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67495,7 +67689,7 @@ pub unsafe fn vst1_u16_x3(a: *mut u16, b: uint16x4x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67518,7 +67712,7 @@ pub unsafe fn vst1_u16_x4(a: *mut u16, b: uint16x4x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67541,7 +67735,7 @@ pub unsafe fn vst1q_u16_x2(a: *mut u16, b: uint16x8x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67564,7 +67758,7 @@ pub unsafe fn vst1q_u16_x3(a: *mut u16, b: uint16x8x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67587,7 +67781,7 @@ pub unsafe fn vst1q_u16_x4(a: *mut u16, b: uint16x8x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67610,7 +67804,7 @@ pub unsafe fn vst1_u32_x2(a: *mut u32, b: uint32x2x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67633,7 +67827,7 @@ pub unsafe fn vst1_u32_x3(a: *mut u32, b: uint32x2x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67656,7 +67850,7 @@ pub unsafe fn vst1_u32_x4(a: *mut u32, b: uint32x2x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67679,7 +67873,7 @@ pub unsafe fn vst1q_u32_x2(a: *mut u32, b: uint32x4x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67702,7 +67896,7 @@ pub unsafe fn vst1q_u32_x3(a: *mut u32, b: uint32x4x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67725,7 +67919,7 @@ pub unsafe fn vst1q_u32_x4(a: *mut u32, b: uint32x4x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67748,7 +67942,7 @@ pub unsafe fn vst1_u64_x2(a: *mut u64, b: uint64x1x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67771,7 +67965,7 @@ pub unsafe fn vst1_u64_x3(a: *mut u64, b: uint64x1x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67794,7 +67988,7 @@ pub unsafe fn vst1_u64_x4(a: *mut u64, b: uint64x1x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67817,7 +68011,7 @@ pub unsafe fn vst1q_u64_x2(a: *mut u64, b: uint64x2x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67840,7 +68034,7 @@ pub unsafe fn vst1q_u64_x3(a: *mut u64, b: uint64x2x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67863,7 +68057,7 @@ pub unsafe fn vst1q_u64_x4(a: *mut u64, b: uint64x2x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67886,7 +68080,7 @@ pub unsafe fn vst1_p8_x2(a: *mut p8, b: poly8x8x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67909,7 +68103,7 @@ pub unsafe fn vst1_p8_x3(a: *mut p8, b: poly8x8x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67932,7 +68126,7 @@ pub unsafe fn vst1_p8_x4(a: *mut p8, b: poly8x8x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67955,7 +68149,7 @@ pub unsafe fn vst1q_p8_x2(a: *mut p8, b: poly8x16x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67978,7 +68172,7 @@ pub unsafe fn vst1q_p8_x3(a: *mut p8, b: poly8x16x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68001,7 +68195,7 @@ pub unsafe fn vst1q_p8_x4(a: *mut p8, b: poly8x16x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68024,7 +68218,7 @@ pub unsafe fn vst1_p16_x2(a: *mut p16, b: poly16x4x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68047,7 +68241,7 @@ pub unsafe fn vst1_p16_x3(a: *mut p16, b: poly16x4x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68070,7 +68264,7 @@ pub unsafe fn vst1_p16_x4(a: *mut p16, b: poly16x4x4_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x2)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68093,7 +68287,7 @@ pub unsafe fn vst1q_p16_x2(a: *mut p16, b: poly16x8x2_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x3)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68116,7 +68310,7 @@ pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) { #[doc = "Store multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x4)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68279,7 +68473,7 @@ unsafe fn vst1q_v8i16(addr: *const i8, val: int16x8_t) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v4f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68297,7 +68491,7 @@ unsafe fn vst1_v4f16(addr: *const i8, val: float16x4_t, align: i32) { #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v8f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68315,7 +68509,7 @@ unsafe fn vst1q_v8f16(addr: *const i8, val: float16x8_t, align: i32) { #[doc = "Store multiple single-element structures from one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,aes")] @@ -68340,7 +68534,7 @@ pub unsafe fn vst1q_lane_p64(a: *mut p64, b: poly64x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68361,7 +68555,7 @@ pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68382,7 +68576,7 @@ pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -68401,7 +68595,7 @@ pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -68420,7 +68614,7 @@ pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68439,7 +68633,7 @@ pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68458,7 +68652,7 @@ pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68477,7 +68671,7 @@ pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68496,7 +68690,7 @@ pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68515,7 +68709,7 @@ pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68534,7 +68728,7 @@ pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68553,7 +68747,7 @@ pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68572,7 +68766,7 @@ pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -68588,7 +68782,7 @@ pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -68604,7 +68798,7 @@ pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -68620,7 +68814,7 @@ pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -68636,7 +68830,7 @@ pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -68652,7 +68846,7 @@ pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -68668,7 +68862,7 @@ pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -68684,7 +68878,7 @@ pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -68700,7 +68894,7 @@ pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68723,7 +68917,7 @@ pub unsafe fn vst2_lane_f16(a: *mut f16, b: float16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68746,7 +68940,7 @@ pub unsafe fn vst2q_lane_f16(a: *mut f16, b: float16x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -68767,7 +68961,7 @@ pub unsafe fn vst2_lane_f16(a: *mut f16, b: float16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -68788,7 +68982,7 @@ pub unsafe fn vst2q_lane_f16(a: *mut f16, b: float16x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68809,7 +69003,7 @@ pub unsafe fn vst2_lane_f32(a: *mut f32, b: float32x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68830,7 +69024,7 @@ pub unsafe fn vst2q_lane_f32(a: *mut f32, b: float32x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68851,7 +69045,7 @@ pub unsafe fn vst2_lane_s8(a: *mut i8, b: int8x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68872,7 +69066,7 @@ pub unsafe fn vst2_lane_s16(a: *mut i16, b: int16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68893,7 +69087,7 @@ pub unsafe fn vst2q_lane_s16(a: *mut i16, b: int16x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68914,7 +69108,7 @@ pub unsafe fn vst2_lane_s32(a: *mut i32, b: int32x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -68935,7 +69129,7 @@ pub unsafe fn vst2q_lane_s32(a: *mut i32, b: int32x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -68953,7 +69147,7 @@ pub unsafe fn vst2_lane_f32(a: *mut f32, b: float32x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -68971,7 +69165,7 @@ pub unsafe fn vst2q_lane_f32(a: *mut f32, b: float32x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -68989,7 +69183,7 @@ pub unsafe fn vst2_lane_s8(a: *mut i8, b: int8x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69007,7 +69201,7 @@ pub unsafe fn vst2_lane_s16(a: *mut i16, b: int16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69025,7 +69219,7 @@ pub unsafe fn vst2q_lane_s16(a: *mut i16, b: int16x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69043,7 +69237,7 @@ pub unsafe fn vst2_lane_s32(a: *mut i32, b: int32x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69061,7 +69255,7 @@ pub unsafe fn vst2q_lane_s32(a: *mut i32, b: int32x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69086,7 +69280,7 @@ pub unsafe fn vst2_lane_u8(a: *mut u8, b: uint8x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69111,7 +69305,7 @@ pub unsafe fn vst2_lane_u16(a: *mut u16, b: uint16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69136,7 +69330,7 @@ pub unsafe fn vst2q_lane_u16(a: *mut u16, b: uint16x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69161,7 +69355,7 @@ pub unsafe fn vst2_lane_u32(a: *mut u32, b: uint32x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69186,7 +69380,7 @@ pub unsafe fn vst2q_lane_u32(a: *mut u32, b: uint32x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69211,7 +69405,7 @@ pub unsafe fn vst2_lane_p8(a: *mut p8, b: poly8x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69236,7 +69430,7 @@ pub unsafe fn vst2_lane_p16(a: *mut p16, b: poly16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69261,7 +69455,7 @@ pub unsafe fn vst2q_lane_p16(a: *mut p16, b: poly16x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,aes")] @@ -69284,7 +69478,7 @@ pub unsafe fn vst2_p64(a: *mut p64, b: poly64x1x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69300,7 +69494,7 @@ pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -69319,7 +69513,7 @@ pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69342,7 +69536,7 @@ pub unsafe fn vst2_u64(a: *mut u64, b: uint64x1x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69365,7 +69559,7 @@ pub unsafe fn vst2_u8(a: *mut u8, b: uint8x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69388,7 +69582,7 @@ pub unsafe fn vst2q_u8(a: *mut u8, b: uint8x16x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69411,7 +69605,7 @@ pub unsafe fn vst2_u16(a: *mut u16, b: uint16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69434,7 +69628,7 @@ pub unsafe fn vst2q_u16(a: *mut u16, b: uint16x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69457,7 +69651,7 @@ pub unsafe fn vst2_u32(a: *mut u32, b: uint32x2x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69480,7 +69674,7 @@ pub unsafe fn vst2q_u32(a: *mut u32, b: uint32x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69503,7 +69697,7 @@ pub unsafe fn vst2_p8(a: *mut p8, b: poly8x8x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69526,7 +69720,7 @@ pub unsafe fn vst2q_p8(a: *mut p8, b: poly8x16x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69549,7 +69743,7 @@ pub unsafe fn vst2_p16(a: *mut p16, b: poly16x4x2_t) { #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69572,7 +69766,7 @@ pub unsafe fn vst2q_p16(a: *mut p16, b: poly16x8x2_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -69591,7 +69785,7 @@ pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -69610,7 +69804,7 @@ pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -69631,7 +69825,7 @@ pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -69652,7 +69846,7 @@ pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69668,7 +69862,7 @@ pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69684,7 +69878,7 @@ pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69700,7 +69894,7 @@ pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69716,7 +69910,7 @@ pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69732,7 +69926,7 @@ pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69748,7 +69942,7 @@ pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69764,7 +69958,7 @@ pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -69780,7 +69974,7 @@ pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -69799,7 +69993,7 @@ pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -69818,7 +70012,7 @@ pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -69837,7 +70031,7 @@ pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -69856,7 +70050,7 @@ pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -69875,7 +70069,7 @@ pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -69894,7 +70088,7 @@ pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -69913,7 +70107,7 @@ pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -69932,7 +70126,7 @@ pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -69960,7 +70154,7 @@ pub unsafe fn vst3_lane_f16(a: *mut f16, b: float16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -69988,7 +70182,7 @@ pub unsafe fn vst3q_lane_f16(a: *mut f16, b: float16x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70011,7 +70205,7 @@ pub unsafe fn vst3_lane_f16(a: *mut f16, b: float16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70034,7 +70228,7 @@ pub unsafe fn vst3q_lane_f16(a: *mut f16, b: float16x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -70059,7 +70253,7 @@ pub unsafe fn vst3_lane_f32(a: *mut f32, b: float32x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -70084,7 +70278,7 @@ pub unsafe fn vst3q_lane_f32(a: *mut f32, b: float32x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -70102,7 +70296,7 @@ pub unsafe fn vst3_lane_s8(a: *mut i8, b: int8x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -70127,7 +70321,7 @@ pub unsafe fn vst3_lane_s16(a: *mut i16, b: int16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -70152,7 +70346,7 @@ pub unsafe fn vst3q_lane_s16(a: *mut i16, b: int16x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -70177,7 +70371,7 @@ pub unsafe fn vst3_lane_s32(a: *mut i32, b: int32x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -70202,7 +70396,7 @@ pub unsafe fn vst3q_lane_s32(a: *mut i32, b: int32x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70223,7 +70417,7 @@ pub unsafe fn vst3_lane_f32(a: *mut f32, b: float32x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70244,7 +70438,7 @@ pub unsafe fn vst3q_lane_f32(a: *mut f32, b: float32x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70265,7 +70459,7 @@ pub unsafe fn vst3_lane_s8(a: *mut i8, b: int8x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70286,7 +70480,7 @@ pub unsafe fn vst3_lane_s16(a: *mut i16, b: int16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70307,7 +70501,7 @@ pub unsafe fn vst3q_lane_s16(a: *mut i16, b: int16x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70328,7 +70522,7 @@ pub unsafe fn vst3_lane_s32(a: *mut i32, b: int32x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70349,7 +70543,7 @@ pub unsafe fn vst3q_lane_s32(a: *mut i32, b: int32x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70374,7 +70568,7 @@ pub unsafe fn vst3_lane_u8(a: *mut u8, b: uint8x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70399,7 +70593,7 @@ pub unsafe fn vst3_lane_u16(a: *mut u16, b: uint16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70424,7 +70618,7 @@ pub unsafe fn vst3q_lane_u16(a: *mut u16, b: uint16x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70449,7 +70643,7 @@ pub unsafe fn vst3_lane_u32(a: *mut u32, b: uint32x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70474,7 +70668,7 @@ pub unsafe fn vst3q_lane_u32(a: *mut u32, b: uint32x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70499,7 +70693,7 @@ pub unsafe fn vst3_lane_p8(a: *mut p8, b: poly8x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70524,7 +70718,7 @@ pub unsafe fn vst3_lane_p16(a: *mut p16, b: poly16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70549,7 +70743,7 @@ pub unsafe fn vst3q_lane_p16(a: *mut p16, b: poly16x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,aes")] @@ -70572,7 +70766,7 @@ pub unsafe fn vst3_p64(a: *mut p64, b: poly64x1x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70591,7 +70785,7 @@ pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -70607,7 +70801,7 @@ pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70630,7 +70824,7 @@ pub unsafe fn vst3_u64(a: *mut u64, b: uint64x1x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70653,7 +70847,7 @@ pub unsafe fn vst3_u8(a: *mut u8, b: uint8x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70676,7 +70870,7 @@ pub unsafe fn vst3q_u8(a: *mut u8, b: uint8x16x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70699,7 +70893,7 @@ pub unsafe fn vst3_u16(a: *mut u16, b: uint16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70722,7 +70916,7 @@ pub unsafe fn vst3q_u16(a: *mut u16, b: uint16x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70745,7 +70939,7 @@ pub unsafe fn vst3_u32(a: *mut u32, b: uint32x2x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70768,7 +70962,7 @@ pub unsafe fn vst3q_u32(a: *mut u32, b: uint32x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70791,7 +70985,7 @@ pub unsafe fn vst3_p8(a: *mut p8, b: poly8x8x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70814,7 +71008,7 @@ pub unsafe fn vst3q_p8(a: *mut p8, b: poly8x16x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70837,7 +71031,7 @@ pub unsafe fn vst3_p16(a: *mut p16, b: poly16x4x3_t) { #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70860,7 +71054,7 @@ pub unsafe fn vst3q_p16(a: *mut p16, b: poly16x8x3_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -70886,7 +71080,7 @@ pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -70912,7 +71106,7 @@ pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70933,7 +71127,7 @@ pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -70954,7 +71148,7 @@ pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -70977,7 +71171,7 @@ pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71000,7 +71194,7 @@ pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71016,7 +71210,7 @@ pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71039,7 +71233,7 @@ pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71062,7 +71256,7 @@ pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71085,7 +71279,7 @@ pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71108,7 +71302,7 @@ pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71131,7 +71325,7 @@ pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71150,7 +71344,7 @@ pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71169,7 +71363,7 @@ pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71188,7 +71382,7 @@ pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71207,7 +71401,7 @@ pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71226,7 +71420,7 @@ pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71245,7 +71439,7 @@ pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71264,7 +71458,7 @@ pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71283,7 +71477,7 @@ pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -71312,7 +71506,7 @@ pub unsafe fn vst4_lane_f16(a: *mut f16, b: float16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] @@ -71341,7 +71535,7 @@ pub unsafe fn vst4q_lane_f16(a: *mut f16, b: float16x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71371,7 +71565,7 @@ pub unsafe fn vst4_lane_f16(a: *mut f16, b: float16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71401,7 +71595,7 @@ pub unsafe fn vst4q_lane_f16(a: *mut f16, b: float16x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71427,7 +71621,7 @@ pub unsafe fn vst4_lane_f32(a: *mut f32, b: float32x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71453,7 +71647,7 @@ pub unsafe fn vst4q_lane_f32(a: *mut f32, b: float32x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71479,7 +71673,7 @@ pub unsafe fn vst4_lane_s8(a: *mut i8, b: int8x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71505,7 +71699,7 @@ pub unsafe fn vst4_lane_s16(a: *mut i16, b: int16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71531,7 +71725,7 @@ pub unsafe fn vst4q_lane_s16(a: *mut i16, b: int16x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71557,7 +71751,7 @@ pub unsafe fn vst4_lane_s32(a: *mut i32, b: int32x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -71583,7 +71777,7 @@ pub unsafe fn vst4q_lane_s32(a: *mut i32, b: int32x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71611,7 +71805,7 @@ pub unsafe fn vst4_lane_f32(a: *mut f32, b: float32x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71639,7 +71833,7 @@ pub unsafe fn vst4q_lane_f32(a: *mut f32, b: float32x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71660,7 +71854,7 @@ pub unsafe fn vst4_lane_s8(a: *mut i8, b: int8x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71688,7 +71882,7 @@ pub unsafe fn vst4_lane_s16(a: *mut i16, b: int16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71716,7 +71910,7 @@ pub unsafe fn vst4q_lane_s16(a: *mut i16, b: int16x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71744,7 +71938,7 @@ pub unsafe fn vst4_lane_s32(a: *mut i32, b: int32x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -71772,7 +71966,7 @@ pub unsafe fn vst4q_lane_s32(a: *mut i32, b: int32x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71797,7 +71991,7 @@ pub unsafe fn vst4_lane_u8(a: *mut u8, b: uint8x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71822,7 +72016,7 @@ pub unsafe fn vst4_lane_u16(a: *mut u16, b: uint16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71847,7 +72041,7 @@ pub unsafe fn vst4q_lane_u16(a: *mut u16, b: uint16x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71872,7 +72066,7 @@ pub unsafe fn vst4_lane_u32(a: *mut u32, b: uint32x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71897,7 +72091,7 @@ pub unsafe fn vst4q_lane_u32(a: *mut u32, b: uint32x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71922,7 +72116,7 @@ pub unsafe fn vst4_lane_p8(a: *mut p8, b: poly8x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71947,7 +72141,7 @@ pub unsafe fn vst4_lane_p16(a: *mut p16, b: poly16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71972,7 +72166,7 @@ pub unsafe fn vst4q_lane_p16(a: *mut p16, b: poly16x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,aes")] @@ -71995,7 +72189,7 @@ pub unsafe fn vst4_p64(a: *mut p64, b: poly64x1x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -72018,7 +72212,7 @@ pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] @@ -72037,7 +72231,7 @@ pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u64)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72060,7 +72254,7 @@ pub unsafe fn vst4_u64(a: *mut u64, b: uint64x1x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72083,7 +72277,7 @@ pub unsafe fn vst4_u8(a: *mut u8, b: uint8x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72106,7 +72300,7 @@ pub unsafe fn vst4q_u8(a: *mut u8, b: uint8x16x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72129,7 +72323,7 @@ pub unsafe fn vst4_u16(a: *mut u16, b: uint16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72152,7 +72346,7 @@ pub unsafe fn vst4q_u16(a: *mut u16, b: uint16x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72175,7 +72369,7 @@ pub unsafe fn vst4_u32(a: *mut u32, b: uint32x2x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u32)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72198,7 +72392,7 @@ pub unsafe fn vst4q_u32(a: *mut u32, b: uint32x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72221,7 +72415,7 @@ pub unsafe fn vst4_p8(a: *mut p8, b: poly8x8x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p8)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72244,7 +72438,7 @@ pub unsafe fn vst4q_p8(a: *mut p8, b: poly8x16x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72267,7 +72461,7 @@ pub unsafe fn vst4_p16(a: *mut p16, b: poly16x4x4_t) { #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p16)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -72290,7 +72484,7 @@ pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) { #[doc = "Store SIMD&FP register (immediate offset)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstrq_p128)"] #[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -73395,6 +73589,47 @@ pub fn vsudotq_lane_s32(a: int32x4_t, b: int8x16_t, c: uint8x8_ simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } +#[doc = "Dot product index form with signed and unsigned integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_laneq_s32)"] +#[inline(always)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sudot, LANE = 3) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub fn vsudot_laneq_s32(a: int32x2_t, b: int8x8_t, c: uint8x16_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let c: uint32x4_t = transmute(c); + let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vusdot_s32(a, transmute(c), b) + } +} +#[doc = "Dot product index form with signed and unsigned integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_laneq_s32)"] +#[inline(always)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sudot, LANE = 3) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub fn vsudotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: uint8x16_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let c: uint32x4_t = transmute(c); + let c: uint32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vusdotq_s32(a, transmute(c), b) + } +} #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1)"] #[inline(always)] @@ -75397,6 +75632,103 @@ pub fn vusdotq_lane_s32(a: int32x4_t, b: uint8x16_t, c: int8x8_ simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) } } +#[doc = "Dot product index form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"] +#[inline(always)] +#[cfg(target_endian = "little")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usdot, LANE = 3) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub fn vusdot_laneq_s32(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let c: int32x4_t = transmute(c); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vusdot_s32(a, b, transmute(c)) + } +} +#[doc = "Dot product index form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"] +#[inline(always)] +#[cfg(target_endian = "big")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usdot, LANE = 3) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub fn vusdot_laneq_s32(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; + let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; + let c: int8x16_t = + unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; + unsafe { + let c: int32x4_t = transmute(c); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + let ret_val: int32x2_t = vusdot_s32(a, b, transmute(c)); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } +} +#[doc = "Dot product index form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"] +#[inline(always)] +#[cfg(target_endian = "little")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usdot, LANE = 3) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub fn vusdotq_laneq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + unsafe { + let c: int32x4_t = transmute(c); + let c: int32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vusdotq_s32(a, b, transmute(c)) + } +} +#[doc = "Dot product index form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"] +#[inline(always)] +#[cfg(target_endian = "big")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usdot, LANE = 3) +)] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub fn vusdotq_laneq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; + let b: uint8x16_t = + unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; + let c: int8x16_t = + unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; + unsafe { + let c: int32x4_t = transmute(c); + let c: int32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + let ret_val: int32x4_t = vusdotq_s32(a, b, transmute(c)); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } +} #[doc = "Dot product vector form with unsigned and signed integers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32)"] #[inline(always)] diff --git a/library/stdarch/crates/core_arch/src/x86/avx.rs b/library/stdarch/crates/core_arch/src/x86/avx.rs index c8cddad2efa6..7b4b210bacf4 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx.rs @@ -3363,6 +3363,7 @@ unsafe extern "C" { #[cfg(test)] mod tests { use crate::core_arch::assert_eq_const as assert_eq; + use crate::core_arch::simd::*; use crate::hint::black_box; use crate::ptr; use stdarch_test::simd_test; @@ -3458,7 +3459,7 @@ mod tests { } #[simd_test(enable = "avx")] - unsafe fn test_mm256_max_pd() { + fn test_mm256_max_pd() { let a = _mm256_setr_pd(1., 4., 5., 8.); let b = _mm256_setr_pd(2., 3., 6., 7.); let r = _mm256_max_pd(a, b); @@ -3468,23 +3469,22 @@ mod tests { // > value in the second operand (source operand) is returned. let w = _mm256_max_pd(_mm256_set1_pd(0.0), _mm256_set1_pd(-0.0)); let x = _mm256_max_pd(_mm256_set1_pd(-0.0), _mm256_set1_pd(0.0)); - let wu: [u64; 4] = transmute(w); - let xu: [u64; 4] = transmute(x); - assert_eq!(wu, [0x8000_0000_0000_0000u64; 4]); - assert_eq!(xu, [0u64; 4]); + let wu = _mm256_castpd_si256(w).as_u64x4(); + let xu = _mm256_castpd_si256(x).as_u64x4(); + assert_eq!(wu, u64x4::splat(0x8000_0000_0000_0000u64)); + assert_eq!(xu, u64x4::splat(0u64)); // > If only one value is a NaN (SNaN or QNaN) for this instruction, the // > second operand (source operand), either a NaN or a valid // > floating-point value, is written to the result. let y = _mm256_max_pd(_mm256_set1_pd(f64::NAN), _mm256_set1_pd(0.0)); let z = _mm256_max_pd(_mm256_set1_pd(0.0), _mm256_set1_pd(f64::NAN)); - let yf: [f64; 4] = transmute(y); - let zf: [f64; 4] = transmute(z); - assert_eq!(yf, [0.0; 4]); + assert_eq_m256d(y, _mm256_set1_pd(0.0)); + let zf = *z.as_f64x4().as_array(); assert!(zf.iter().all(|f| f.is_nan()), "{:?}", zf); } #[simd_test(enable = "avx")] - unsafe fn test_mm256_max_ps() { + fn test_mm256_max_ps() { let a = _mm256_setr_ps(1., 4., 5., 8., 9., 12., 13., 16.); let b = _mm256_setr_ps(2., 3., 6., 7., 10., 11., 14., 15.); let r = _mm256_max_ps(a, b); @@ -3494,23 +3494,22 @@ mod tests { // > value in the second operand (source operand) is returned. let w = _mm256_max_ps(_mm256_set1_ps(0.0), _mm256_set1_ps(-0.0)); let x = _mm256_max_ps(_mm256_set1_ps(-0.0), _mm256_set1_ps(0.0)); - let wu: [u32; 8] = transmute(w); - let xu: [u32; 8] = transmute(x); - assert_eq!(wu, [0x8000_0000u32; 8]); - assert_eq!(xu, [0u32; 8]); + let wu = _mm256_castps_si256(w).as_u32x8(); + let xu = _mm256_castps_si256(x).as_u32x8(); + assert_eq!(wu, u32x8::splat(0x8000_0000u32)); + assert_eq!(xu, u32x8::splat(0u32)); // > If only one value is a NaN (SNaN or QNaN) for this instruction, the // > second operand (source operand), either a NaN or a valid // > floating-point value, is written to the result. let y = _mm256_max_ps(_mm256_set1_ps(f32::NAN), _mm256_set1_ps(0.0)); let z = _mm256_max_ps(_mm256_set1_ps(0.0), _mm256_set1_ps(f32::NAN)); - let yf: [f32; 8] = transmute(y); - let zf: [f32; 8] = transmute(z); - assert_eq!(yf, [0.0; 8]); + assert_eq_m256(y, _mm256_set1_ps(0.0)); + let zf = *z.as_f32x8().as_array(); assert!(zf.iter().all(|f| f.is_nan()), "{:?}", zf); } #[simd_test(enable = "avx")] - unsafe fn test_mm256_min_pd() { + fn test_mm256_min_pd() { let a = _mm256_setr_pd(1., 4., 5., 8.); let b = _mm256_setr_pd(2., 3., 6., 7.); let r = _mm256_min_pd(a, b); @@ -3520,23 +3519,22 @@ mod tests { // > value in the second operand (source operand) is returned. let w = _mm256_min_pd(_mm256_set1_pd(0.0), _mm256_set1_pd(-0.0)); let x = _mm256_min_pd(_mm256_set1_pd(-0.0), _mm256_set1_pd(0.0)); - let wu: [u64; 4] = transmute(w); - let xu: [u64; 4] = transmute(x); - assert_eq!(wu, [0x8000_0000_0000_0000u64; 4]); - assert_eq!(xu, [0u64; 4]); + let wu = _mm256_castpd_si256(w).as_u64x4(); + let xu = _mm256_castpd_si256(x).as_u64x4(); + assert_eq!(wu, u64x4::splat(0x8000_0000_0000_0000u64)); + assert_eq!(xu, u64x4::splat(0u64)); // > If only one value is a NaN (SNaN or QNaN) for this instruction, the // > second operand (source operand), either a NaN or a valid // > floating-point value, is written to the result. let y = _mm256_min_pd(_mm256_set1_pd(f64::NAN), _mm256_set1_pd(0.0)); let z = _mm256_min_pd(_mm256_set1_pd(0.0), _mm256_set1_pd(f64::NAN)); - let yf: [f64; 4] = transmute(y); - let zf: [f64; 4] = transmute(z); - assert_eq!(yf, [0.0; 4]); + assert_eq_m256d(y, _mm256_set1_pd(0.0)); + let zf = *z.as_f64x4().as_array(); assert!(zf.iter().all(|f| f.is_nan()), "{:?}", zf); } #[simd_test(enable = "avx")] - unsafe fn test_mm256_min_ps() { + fn test_mm256_min_ps() { let a = _mm256_setr_ps(1., 4., 5., 8., 9., 12., 13., 16.); let b = _mm256_setr_ps(2., 3., 6., 7., 10., 11., 14., 15.); let r = _mm256_min_ps(a, b); @@ -3546,18 +3544,17 @@ mod tests { // > value in the second operand (source operand) is returned. let w = _mm256_min_ps(_mm256_set1_ps(0.0), _mm256_set1_ps(-0.0)); let x = _mm256_min_ps(_mm256_set1_ps(-0.0), _mm256_set1_ps(0.0)); - let wu: [u32; 8] = transmute(w); - let xu: [u32; 8] = transmute(x); - assert_eq!(wu, [0x8000_0000u32; 8]); - assert_eq!(xu, [0u32; 8]); + let wu = _mm256_castps_si256(w).as_u32x8(); + let xu = _mm256_castps_si256(x).as_u32x8(); + assert_eq!(wu, u32x8::splat(0x8000_0000u32)); + assert_eq!(xu, u32x8::splat(0u32)); // > If only one value is a NaN (SNaN or QNaN) for this instruction, the // > second operand (source operand), either a NaN or a valid // > floating-point value, is written to the result. let y = _mm256_min_ps(_mm256_set1_ps(f32::NAN), _mm256_set1_ps(0.0)); let z = _mm256_min_ps(_mm256_set1_ps(0.0), _mm256_set1_ps(f32::NAN)); - let yf: [f32; 8] = transmute(y); - let zf: [f32; 8] = transmute(z); - assert_eq!(yf, [0.0; 8]); + assert_eq_m256(y, _mm256_set1_ps(0.0)); + let zf = *z.as_f32x8().as_array(); assert!(zf.iter().all(|f| f.is_nan()), "{:?}", zf); } @@ -4241,183 +4238,203 @@ mod tests { } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_load_pd() { + const fn test_mm256_load_pd() { let a = _mm256_setr_pd(1., 2., 3., 4.); let p = ptr::addr_of!(a) as *const f64; - let r = _mm256_load_pd(p); + let r = unsafe { _mm256_load_pd(p) }; let e = _mm256_setr_pd(1., 2., 3., 4.); assert_eq_m256d(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_store_pd() { + const fn test_mm256_store_pd() { let a = _mm256_setr_pd(1., 2., 3., 4.); let mut r = _mm256_undefined_pd(); - _mm256_store_pd(ptr::addr_of_mut!(r) as *mut f64, a); + unsafe { + _mm256_store_pd(ptr::addr_of_mut!(r) as *mut f64, a); + } assert_eq_m256d(r, a); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_load_ps() { + const fn test_mm256_load_ps() { let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.); let p = ptr::addr_of!(a) as *const f32; - let r = _mm256_load_ps(p); + let r = unsafe { _mm256_load_ps(p) }; let e = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.); assert_eq_m256(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_store_ps() { + const fn test_mm256_store_ps() { let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.); let mut r = _mm256_undefined_ps(); - _mm256_store_ps(ptr::addr_of_mut!(r) as *mut f32, a); + unsafe { + _mm256_store_ps(ptr::addr_of_mut!(r) as *mut f32, a); + } assert_eq_m256(r, a); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_loadu_pd() { + const fn test_mm256_loadu_pd() { let a = &[1.0f64, 2., 3., 4.]; let p = a.as_ptr(); - let r = _mm256_loadu_pd(black_box(p)); + let r = unsafe { _mm256_loadu_pd(black_box(p)) }; let e = _mm256_setr_pd(1., 2., 3., 4.); assert_eq_m256d(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_storeu_pd() { + const fn test_mm256_storeu_pd() { let a = _mm256_set1_pd(9.); let mut r = _mm256_undefined_pd(); - _mm256_storeu_pd(ptr::addr_of_mut!(r) as *mut f64, a); + unsafe { + _mm256_storeu_pd(ptr::addr_of_mut!(r) as *mut f64, a); + } assert_eq_m256d(r, a); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_loadu_ps() { + const fn test_mm256_loadu_ps() { let a = &[4., 3., 2., 5., 8., 9., 64., 50.]; let p = a.as_ptr(); - let r = _mm256_loadu_ps(black_box(p)); + let r = unsafe { _mm256_loadu_ps(black_box(p)) }; let e = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.); assert_eq_m256(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_storeu_ps() { + const fn test_mm256_storeu_ps() { let a = _mm256_set1_ps(9.); let mut r = _mm256_undefined_ps(); - _mm256_storeu_ps(ptr::addr_of_mut!(r) as *mut f32, a); + unsafe { + _mm256_storeu_ps(ptr::addr_of_mut!(r) as *mut f32, a); + } assert_eq_m256(r, a); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_load_si256() { + const fn test_mm256_load_si256() { let a = _mm256_setr_epi64x(1, 2, 3, 4); let p = ptr::addr_of!(a); - let r = _mm256_load_si256(p); + let r = unsafe { _mm256_load_si256(p) }; let e = _mm256_setr_epi64x(1, 2, 3, 4); assert_eq_m256i(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_store_si256() { + const fn test_mm256_store_si256() { let a = _mm256_setr_epi64x(1, 2, 3, 4); let mut r = _mm256_undefined_si256(); - _mm256_store_si256(ptr::addr_of_mut!(r), a); + unsafe { + _mm256_store_si256(ptr::addr_of_mut!(r), a); + } assert_eq_m256i(r, a); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_loadu_si256() { + const fn test_mm256_loadu_si256() { let a = _mm256_setr_epi64x(1, 2, 3, 4); let p = ptr::addr_of!(a); - let r = _mm256_loadu_si256(black_box(p)); + let r = unsafe { _mm256_loadu_si256(black_box(p)) }; let e = _mm256_setr_epi64x(1, 2, 3, 4); assert_eq_m256i(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_storeu_si256() { + const fn test_mm256_storeu_si256() { let a = _mm256_set1_epi8(9); let mut r = _mm256_undefined_si256(); - _mm256_storeu_si256(ptr::addr_of_mut!(r), a); + unsafe { + _mm256_storeu_si256(ptr::addr_of_mut!(r), a); + } assert_eq_m256i(r, a); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_maskload_pd() { + const fn test_mm256_maskload_pd() { let a = &[1.0f64, 2., 3., 4.]; let p = a.as_ptr(); let mask = _mm256_setr_epi64x(0, !0, 0, !0); - let r = _mm256_maskload_pd(black_box(p), mask); + let r = unsafe { _mm256_maskload_pd(black_box(p), mask) }; let e = _mm256_setr_pd(0., 2., 0., 4.); assert_eq_m256d(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_maskstore_pd() { + const fn test_mm256_maskstore_pd() { let mut r = _mm256_set1_pd(0.); let mask = _mm256_setr_epi64x(0, !0, 0, !0); let a = _mm256_setr_pd(1., 2., 3., 4.); - _mm256_maskstore_pd(ptr::addr_of_mut!(r) as *mut f64, mask, a); + unsafe { + _mm256_maskstore_pd(ptr::addr_of_mut!(r) as *mut f64, mask, a); + } let e = _mm256_setr_pd(0., 2., 0., 4.); assert_eq_m256d(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm_maskload_pd() { + const fn test_mm_maskload_pd() { let a = &[1.0f64, 2.]; let p = a.as_ptr(); let mask = _mm_setr_epi64x(0, !0); - let r = _mm_maskload_pd(black_box(p), mask); + let r = unsafe { _mm_maskload_pd(black_box(p), mask) }; let e = _mm_setr_pd(0., 2.); assert_eq_m128d(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm_maskstore_pd() { + const fn test_mm_maskstore_pd() { let mut r = _mm_set1_pd(0.); let mask = _mm_setr_epi64x(0, !0); let a = _mm_setr_pd(1., 2.); - _mm_maskstore_pd(ptr::addr_of_mut!(r) as *mut f64, mask, a); + unsafe { + _mm_maskstore_pd(ptr::addr_of_mut!(r) as *mut f64, mask, a); + } let e = _mm_setr_pd(0., 2.); assert_eq_m128d(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_maskload_ps() { + const fn test_mm256_maskload_ps() { let a = &[1.0f32, 2., 3., 4., 5., 6., 7., 8.]; let p = a.as_ptr(); let mask = _mm256_setr_epi32(0, !0, 0, !0, 0, !0, 0, !0); - let r = _mm256_maskload_ps(black_box(p), mask); + let r = unsafe { _mm256_maskload_ps(black_box(p), mask) }; let e = _mm256_setr_ps(0., 2., 0., 4., 0., 6., 0., 8.); assert_eq_m256(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_maskstore_ps() { + const fn test_mm256_maskstore_ps() { let mut r = _mm256_set1_ps(0.); let mask = _mm256_setr_epi32(0, !0, 0, !0, 0, !0, 0, !0); let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.); - _mm256_maskstore_ps(ptr::addr_of_mut!(r) as *mut f32, mask, a); + unsafe { + _mm256_maskstore_ps(ptr::addr_of_mut!(r) as *mut f32, mask, a); + } let e = _mm256_setr_ps(0., 2., 0., 4., 0., 6., 0., 8.); assert_eq_m256(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm_maskload_ps() { + const fn test_mm_maskload_ps() { let a = &[1.0f32, 2., 3., 4.]; let p = a.as_ptr(); let mask = _mm_setr_epi32(0, !0, 0, !0); - let r = _mm_maskload_ps(black_box(p), mask); + let r = unsafe { _mm_maskload_ps(black_box(p), mask) }; let e = _mm_setr_ps(0., 2., 0., 4.); assert_eq_m128(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm_maskstore_ps() { + const fn test_mm_maskstore_ps() { let mut r = _mm_set1_ps(0.); let mask = _mm_setr_epi32(0, !0, 0, !0); let a = _mm_setr_ps(1., 2., 3., 4.); - _mm_maskstore_ps(ptr::addr_of_mut!(r) as *mut f32, mask, a); + unsafe { + _mm_maskstore_ps(ptr::addr_of_mut!(r) as *mut f32, mask, a); + } let e = _mm_setr_ps(0., 2., 0., 4.); assert_eq_m128(r, e); } @@ -4447,7 +4464,7 @@ mod tests { } #[simd_test(enable = "avx")] - unsafe fn test_mm256_lddqu_si256() { + fn test_mm256_lddqu_si256() { #[rustfmt::skip] let a = _mm256_setr_epi8( 1, 2, 3, 4, 5, 6, 7, 8, @@ -4456,7 +4473,7 @@ mod tests { 25, 26, 27, 28, 29, 30, 31, 32, ); let p = ptr::addr_of!(a); - let r = _mm256_lddqu_si256(black_box(p)); + let r = unsafe { _mm256_lddqu_si256(black_box(p)) }; #[rustfmt::skip] let e = _mm256_setr_epi8( 1, 2, 3, 4, 5, 6, 7, 8, @@ -4469,17 +4486,19 @@ mod tests { #[simd_test(enable = "avx")] #[cfg_attr(miri, ignore)] // Non-temporal store, which is not supported by Miri - unsafe fn test_mm256_stream_si256() { + fn test_mm256_stream_si256() { let a = _mm256_setr_epi64x(1, 2, 3, 4); let mut r = _mm256_undefined_si256(); - _mm256_stream_si256(ptr::addr_of_mut!(r), a); + unsafe { + _mm256_stream_si256(ptr::addr_of_mut!(r), a); + } _mm_sfence(); assert_eq_m256i(r, a); } #[simd_test(enable = "avx")] #[cfg_attr(miri, ignore)] // Non-temporal store, which is not supported by Miri - unsafe fn test_mm256_stream_pd() { + fn test_mm256_stream_pd() { #[repr(align(32))] struct Memory { pub data: [f64; 4], @@ -4487,7 +4506,9 @@ mod tests { let a = _mm256_set1_pd(7.0); let mut mem = Memory { data: [-1.0; 4] }; - _mm256_stream_pd(ptr::addr_of_mut!(mem.data[0]), a); + unsafe { + _mm256_stream_pd(ptr::addr_of_mut!(mem.data[0]), a); + } _mm_sfence(); for i in 0..4 { assert_eq!(mem.data[i], get_m256d(a, i)); @@ -4496,7 +4517,7 @@ mod tests { #[simd_test(enable = "avx")] #[cfg_attr(miri, ignore)] // Non-temporal store, which is not supported by Miri - unsafe fn test_mm256_stream_ps() { + fn test_mm256_stream_ps() { #[repr(align(32))] struct Memory { pub data: [f32; 8], @@ -4504,7 +4525,9 @@ mod tests { let a = _mm256_set1_ps(7.0); let mut mem = Memory { data: [-1.0; 8] }; - _mm256_stream_ps(ptr::addr_of_mut!(mem.data[0]), a); + unsafe { + _mm256_stream_ps(ptr::addr_of_mut!(mem.data[0]), a); + } _mm_sfence(); for i in 0..8 { assert_eq!(mem.data[i], get_m256(a, i)); @@ -5141,29 +5164,29 @@ mod tests { } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_loadu2_m128() { + const fn test_mm256_loadu2_m128() { let hi = &[5., 6., 7., 8.]; let hiaddr = hi.as_ptr(); let lo = &[1., 2., 3., 4.]; let loaddr = lo.as_ptr(); - let r = _mm256_loadu2_m128(hiaddr, loaddr); + let r = unsafe { _mm256_loadu2_m128(hiaddr, loaddr) }; let e = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.); assert_eq_m256(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_loadu2_m128d() { + const fn test_mm256_loadu2_m128d() { let hi = &[3., 4.]; let hiaddr = hi.as_ptr(); let lo = &[1., 2.]; let loaddr = lo.as_ptr(); - let r = _mm256_loadu2_m128d(hiaddr, loaddr); + let r = unsafe { _mm256_loadu2_m128d(hiaddr, loaddr) }; let e = _mm256_setr_pd(1., 2., 3., 4.); assert_eq_m256d(r, e); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_loadu2_m128i() { + const fn test_mm256_loadu2_m128i() { #[rustfmt::skip] let hi = _mm_setr_epi8( 17, 18, 19, 20, 21, 22, 23, 24, @@ -5174,7 +5197,9 @@ mod tests { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, ); - let r = _mm256_loadu2_m128i(ptr::addr_of!(hi) as *const _, ptr::addr_of!(lo) as *const _); + let r = unsafe { + _mm256_loadu2_m128i(ptr::addr_of!(hi) as *const _, ptr::addr_of!(lo) as *const _) + }; #[rustfmt::skip] let e = _mm256_setr_epi8( 1, 2, 3, 4, 5, 6, 7, 8, @@ -5186,35 +5211,39 @@ mod tests { } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_storeu2_m128() { + const fn test_mm256_storeu2_m128() { let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.); let mut hi = _mm_undefined_ps(); let mut lo = _mm_undefined_ps(); - _mm256_storeu2_m128( - ptr::addr_of_mut!(hi) as *mut f32, - ptr::addr_of_mut!(lo) as *mut f32, - a, - ); + unsafe { + _mm256_storeu2_m128( + ptr::addr_of_mut!(hi) as *mut f32, + ptr::addr_of_mut!(lo) as *mut f32, + a, + ); + } assert_eq_m128(hi, _mm_setr_ps(5., 6., 7., 8.)); assert_eq_m128(lo, _mm_setr_ps(1., 2., 3., 4.)); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_storeu2_m128d() { + const fn test_mm256_storeu2_m128d() { let a = _mm256_setr_pd(1., 2., 3., 4.); let mut hi = _mm_undefined_pd(); let mut lo = _mm_undefined_pd(); - _mm256_storeu2_m128d( - ptr::addr_of_mut!(hi) as *mut f64, - ptr::addr_of_mut!(lo) as *mut f64, - a, - ); + unsafe { + _mm256_storeu2_m128d( + ptr::addr_of_mut!(hi) as *mut f64, + ptr::addr_of_mut!(lo) as *mut f64, + a, + ); + } assert_eq_m128d(hi, _mm_setr_pd(3., 4.)); assert_eq_m128d(lo, _mm_setr_pd(1., 2.)); } #[simd_test(enable = "avx")] - const unsafe fn test_mm256_storeu2_m128i() { + const fn test_mm256_storeu2_m128i() { #[rustfmt::skip] let a = _mm256_setr_epi8( 1, 2, 3, 4, 5, 6, 7, 8, @@ -5224,7 +5253,9 @@ mod tests { ); let mut hi = _mm_undefined_si128(); let mut lo = _mm_undefined_si128(); - _mm256_storeu2_m128i(ptr::addr_of_mut!(hi), ptr::addr_of_mut!(lo), a); + unsafe { + _mm256_storeu2_m128i(ptr::addr_of_mut!(hi), ptr::addr_of_mut!(lo), a); + } #[rustfmt::skip] let e_hi = _mm_setr_epi8( 17, 18, 19, 20, 21, 22, 23, 24, diff --git a/library/stdarch/crates/core_arch/src/x86/avx2.rs b/library/stdarch/crates/core_arch/src/x86/avx2.rs index 6f56e937c6db..6a39a0aaf8fe 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx2.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx2.rs @@ -4672,81 +4672,89 @@ mod tests { } #[simd_test(enable = "avx2")] - const unsafe fn test_mm_maskload_epi32() { + const fn test_mm_maskload_epi32() { let nums = [1, 2, 3, 4]; let a = &nums as *const i32; let mask = _mm_setr_epi32(-1, 0, 0, -1); - let r = _mm_maskload_epi32(a, mask); + let r = unsafe { _mm_maskload_epi32(a, mask) }; let e = _mm_setr_epi32(1, 0, 0, 4); assert_eq_m128i(r, e); } #[simd_test(enable = "avx2")] - const unsafe fn test_mm256_maskload_epi32() { + const fn test_mm256_maskload_epi32() { let nums = [1, 2, 3, 4, 5, 6, 7, 8]; let a = &nums as *const i32; let mask = _mm256_setr_epi32(-1, 0, 0, -1, 0, -1, -1, 0); - let r = _mm256_maskload_epi32(a, mask); + let r = unsafe { _mm256_maskload_epi32(a, mask) }; let e = _mm256_setr_epi32(1, 0, 0, 4, 0, 6, 7, 0); assert_eq_m256i(r, e); } #[simd_test(enable = "avx2")] - const unsafe fn test_mm_maskload_epi64() { + const fn test_mm_maskload_epi64() { let nums = [1_i64, 2_i64]; let a = &nums as *const i64; let mask = _mm_setr_epi64x(0, -1); - let r = _mm_maskload_epi64(a, mask); + let r = unsafe { _mm_maskload_epi64(a, mask) }; let e = _mm_setr_epi64x(0, 2); assert_eq_m128i(r, e); } #[simd_test(enable = "avx2")] - const unsafe fn test_mm256_maskload_epi64() { + const fn test_mm256_maskload_epi64() { let nums = [1_i64, 2_i64, 3_i64, 4_i64]; let a = &nums as *const i64; let mask = _mm256_setr_epi64x(0, -1, -1, 0); - let r = _mm256_maskload_epi64(a, mask); + let r = unsafe { _mm256_maskload_epi64(a, mask) }; let e = _mm256_setr_epi64x(0, 2, 3, 0); assert_eq_m256i(r, e); } #[simd_test(enable = "avx2")] - const unsafe fn test_mm_maskstore_epi32() { + const fn test_mm_maskstore_epi32() { let a = _mm_setr_epi32(1, 2, 3, 4); let mut arr = [-1, -1, -1, -1]; let mask = _mm_setr_epi32(-1, 0, 0, -1); - _mm_maskstore_epi32(arr.as_mut_ptr(), mask, a); + unsafe { + _mm_maskstore_epi32(arr.as_mut_ptr(), mask, a); + } let e = [1, -1, -1, 4]; assert_eq!(arr, e); } #[simd_test(enable = "avx2")] - const unsafe fn test_mm256_maskstore_epi32() { + const fn test_mm256_maskstore_epi32() { let a = _mm256_setr_epi32(1, 0x6d726f, 3, 42, 0x777161, 6, 7, 8); let mut arr = [-1, -1, -1, 0x776173, -1, 0x68657265, -1, -1]; let mask = _mm256_setr_epi32(-1, 0, 0, -1, 0, -1, -1, 0); - _mm256_maskstore_epi32(arr.as_mut_ptr(), mask, a); + unsafe { + _mm256_maskstore_epi32(arr.as_mut_ptr(), mask, a); + } let e = [1, -1, -1, 42, -1, 6, 7, -1]; assert_eq!(arr, e); } #[simd_test(enable = "avx2")] - const unsafe fn test_mm_maskstore_epi64() { + const fn test_mm_maskstore_epi64() { let a = _mm_setr_epi64x(1_i64, 2_i64); let mut arr = [-1_i64, -1_i64]; let mask = _mm_setr_epi64x(0, -1); - _mm_maskstore_epi64(arr.as_mut_ptr(), mask, a); + unsafe { + _mm_maskstore_epi64(arr.as_mut_ptr(), mask, a); + } let e = [-1, 2]; assert_eq!(arr, e); } #[simd_test(enable = "avx2")] - const unsafe fn test_mm256_maskstore_epi64() { + const fn test_mm256_maskstore_epi64() { let a = _mm256_setr_epi64x(1_i64, 2_i64, 3_i64, 4_i64); let mut arr = [-1_i64, -1_i64, -1_i64, -1_i64]; let mask = _mm256_setr_epi64x(0, -1, -1, 0); - _mm256_maskstore_epi64(arr.as_mut_ptr(), mask, a); + unsafe { + _mm256_maskstore_epi64(arr.as_mut_ptr(), mask, a); + } let e = [-1, 2, 3, -1]; assert_eq!(arr, e); } @@ -5301,9 +5309,9 @@ mod tests { } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_stream_load_si256() { + fn test_mm256_stream_load_si256() { let a = _mm256_set_epi64x(5, 6, 7, 8); - let r = _mm256_stream_load_si256(core::ptr::addr_of!(a) as *const _); + let r = unsafe { _mm256_stream_load_si256(core::ptr::addr_of!(a) as *const _) }; assert_eq_m256i(a, r); } @@ -5506,88 +5514,98 @@ mod tests { } #[simd_test(enable = "avx2")] - unsafe fn test_mm_i32gather_epi32() { + fn test_mm_i32gather_epi32() { let arr: [i32; 128] = core::array::from_fn(|i| i as i32); // A multiplier of 4 is word-addressing - let r = _mm_i32gather_epi32::<4>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)); + let r = unsafe { _mm_i32gather_epi32::<4>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)) }; assert_eq_m128i(r, _mm_setr_epi32(0, 16, 32, 48)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_mask_i32gather_epi32() { + fn test_mm_mask_i32gather_epi32() { let arr: [i32; 128] = core::array::from_fn(|i| i as i32); // A multiplier of 4 is word-addressing - let r = _mm_mask_i32gather_epi32::<4>( - _mm_set1_epi32(256), - arr.as_ptr(), - _mm_setr_epi32(0, 16, 64, 96), - _mm_setr_epi32(-1, -1, -1, 0), - ); + let r = unsafe { + _mm_mask_i32gather_epi32::<4>( + _mm_set1_epi32(256), + arr.as_ptr(), + _mm_setr_epi32(0, 16, 64, 96), + _mm_setr_epi32(-1, -1, -1, 0), + ) + }; assert_eq_m128i(r, _mm_setr_epi32(0, 16, 64, 256)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_i32gather_epi32() { + fn test_mm256_i32gather_epi32() { let arr: [i32; 128] = core::array::from_fn(|i| i as i32); // A multiplier of 4 is word-addressing - let r = - _mm256_i32gather_epi32::<4>(arr.as_ptr(), _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4)); + let r = unsafe { + _mm256_i32gather_epi32::<4>(arr.as_ptr(), _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4)) + }; assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_mask_i32gather_epi32() { + fn test_mm256_mask_i32gather_epi32() { let arr: [i32; 128] = core::array::from_fn(|i| i as i32); // A multiplier of 4 is word-addressing - let r = _mm256_mask_i32gather_epi32::<4>( - _mm256_set1_epi32(256), - arr.as_ptr(), - _mm256_setr_epi32(0, 16, 64, 96, 0, 0, 0, 0), - _mm256_setr_epi32(-1, -1, -1, 0, 0, 0, 0, 0), - ); + let r = unsafe { + _mm256_mask_i32gather_epi32::<4>( + _mm256_set1_epi32(256), + arr.as_ptr(), + _mm256_setr_epi32(0, 16, 64, 96, 0, 0, 0, 0), + _mm256_setr_epi32(-1, -1, -1, 0, 0, 0, 0, 0), + ) + }; assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 64, 256, 256, 256, 256, 256)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_i32gather_ps() { + fn test_mm_i32gather_ps() { let arr: [f32; 128] = core::array::from_fn(|i| i as f32); // A multiplier of 4 is word-addressing for f32s - let r = _mm_i32gather_ps::<4>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)); + let r = unsafe { _mm_i32gather_ps::<4>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)) }; assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 32.0, 48.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_mask_i32gather_ps() { + fn test_mm_mask_i32gather_ps() { let arr: [f32; 128] = core::array::from_fn(|i| i as f32); // A multiplier of 4 is word-addressing for f32s - let r = _mm_mask_i32gather_ps::<4>( - _mm_set1_ps(256.0), - arr.as_ptr(), - _mm_setr_epi32(0, 16, 64, 96), - _mm_setr_ps(-1.0, -1.0, -1.0, 0.0), - ); + let r = unsafe { + _mm_mask_i32gather_ps::<4>( + _mm_set1_ps(256.0), + arr.as_ptr(), + _mm_setr_epi32(0, 16, 64, 96), + _mm_setr_ps(-1.0, -1.0, -1.0, 0.0), + ) + }; assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 64.0, 256.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_i32gather_ps() { + fn test_mm256_i32gather_ps() { let arr: [f32; 128] = core::array::from_fn(|i| i as f32); // A multiplier of 4 is word-addressing for f32s - let r = - _mm256_i32gather_ps::<4>(arr.as_ptr(), _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4)); + let r = unsafe { + _mm256_i32gather_ps::<4>(arr.as_ptr(), _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4)) + }; assert_eq_m256(r, _mm256_setr_ps(0.0, 16.0, 32.0, 48.0, 1.0, 2.0, 3.0, 4.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_mask_i32gather_ps() { + fn test_mm256_mask_i32gather_ps() { let arr: [f32; 128] = core::array::from_fn(|i| i as f32); // A multiplier of 4 is word-addressing for f32s - let r = _mm256_mask_i32gather_ps::<4>( - _mm256_set1_ps(256.0), - arr.as_ptr(), - _mm256_setr_epi32(0, 16, 64, 96, 0, 0, 0, 0), - _mm256_setr_ps(-1.0, -1.0, -1.0, 0.0, 0.0, 0.0, 0.0, 0.0), - ); + let r = unsafe { + _mm256_mask_i32gather_ps::<4>( + _mm256_set1_ps(256.0), + arr.as_ptr(), + _mm256_setr_epi32(0, 16, 64, 96, 0, 0, 0, 0), + _mm256_setr_ps(-1.0, -1.0, -1.0, 0.0, 0.0, 0.0, 0.0, 0.0), + ) + }; assert_eq_m256( r, _mm256_setr_ps(0.0, 16.0, 64.0, 256.0, 256.0, 256.0, 256.0, 256.0), @@ -5595,254 +5613,282 @@ mod tests { } #[simd_test(enable = "avx2")] - unsafe fn test_mm_i32gather_epi64() { + fn test_mm_i32gather_epi64() { let arr: [i64; 128] = core::array::from_fn(|i| i as i64); // A multiplier of 8 is word-addressing for i64s - let r = _mm_i32gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 0, 0)); + let r = unsafe { _mm_i32gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 0, 0)) }; assert_eq_m128i(r, _mm_setr_epi64x(0, 16)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_mask_i32gather_epi64() { + fn test_mm_mask_i32gather_epi64() { let arr: [i64; 128] = core::array::from_fn(|i| i as i64); // A multiplier of 8 is word-addressing for i64s - let r = _mm_mask_i32gather_epi64::<8>( - _mm_set1_epi64x(256), - arr.as_ptr(), - _mm_setr_epi32(16, 16, 16, 16), - _mm_setr_epi64x(-1, 0), - ); + let r = unsafe { + _mm_mask_i32gather_epi64::<8>( + _mm_set1_epi64x(256), + arr.as_ptr(), + _mm_setr_epi32(16, 16, 16, 16), + _mm_setr_epi64x(-1, 0), + ) + }; assert_eq_m128i(r, _mm_setr_epi64x(16, 256)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_i32gather_epi64() { + fn test_mm256_i32gather_epi64() { let arr: [i64; 128] = core::array::from_fn(|i| i as i64); // A multiplier of 8 is word-addressing for i64s - let r = _mm256_i32gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)); + let r = unsafe { _mm256_i32gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)) }; assert_eq_m256i(r, _mm256_setr_epi64x(0, 16, 32, 48)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_mask_i32gather_epi64() { + fn test_mm256_mask_i32gather_epi64() { let arr: [i64; 128] = core::array::from_fn(|i| i as i64); // A multiplier of 8 is word-addressing for i64s - let r = _mm256_mask_i32gather_epi64::<8>( - _mm256_set1_epi64x(256), - arr.as_ptr(), - _mm_setr_epi32(0, 16, 64, 96), - _mm256_setr_epi64x(-1, -1, -1, 0), - ); + let r = unsafe { + _mm256_mask_i32gather_epi64::<8>( + _mm256_set1_epi64x(256), + arr.as_ptr(), + _mm_setr_epi32(0, 16, 64, 96), + _mm256_setr_epi64x(-1, -1, -1, 0), + ) + }; assert_eq_m256i(r, _mm256_setr_epi64x(0, 16, 64, 256)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_i32gather_pd() { + fn test_mm_i32gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); // A multiplier of 8 is word-addressing for f64s - let r = _mm_i32gather_pd::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 0, 0)); + let r = unsafe { _mm_i32gather_pd::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 0, 0)) }; assert_eq_m128d(r, _mm_setr_pd(0.0, 16.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_mask_i32gather_pd() { + fn test_mm_mask_i32gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); // A multiplier of 8 is word-addressing for f64s - let r = _mm_mask_i32gather_pd::<8>( - _mm_set1_pd(256.0), - arr.as_ptr(), - _mm_setr_epi32(16, 16, 16, 16), - _mm_setr_pd(-1.0, 0.0), - ); + let r = unsafe { + _mm_mask_i32gather_pd::<8>( + _mm_set1_pd(256.0), + arr.as_ptr(), + _mm_setr_epi32(16, 16, 16, 16), + _mm_setr_pd(-1.0, 0.0), + ) + }; assert_eq_m128d(r, _mm_setr_pd(16.0, 256.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_i32gather_pd() { + fn test_mm256_i32gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); // A multiplier of 8 is word-addressing for f64s - let r = _mm256_i32gather_pd::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)); + let r = unsafe { _mm256_i32gather_pd::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)) }; assert_eq_m256d(r, _mm256_setr_pd(0.0, 16.0, 32.0, 48.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_mask_i32gather_pd() { + fn test_mm256_mask_i32gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); // A multiplier of 8 is word-addressing for f64s - let r = _mm256_mask_i32gather_pd::<8>( - _mm256_set1_pd(256.0), - arr.as_ptr(), - _mm_setr_epi32(0, 16, 64, 96), - _mm256_setr_pd(-1.0, -1.0, -1.0, 0.0), - ); + let r = unsafe { + _mm256_mask_i32gather_pd::<8>( + _mm256_set1_pd(256.0), + arr.as_ptr(), + _mm_setr_epi32(0, 16, 64, 96), + _mm256_setr_pd(-1.0, -1.0, -1.0, 0.0), + ) + }; assert_eq_m256d(r, _mm256_setr_pd(0.0, 16.0, 64.0, 256.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_i64gather_epi32() { + fn test_mm_i64gather_epi32() { let arr: [i32; 128] = core::array::from_fn(|i| i as i32); // A multiplier of 4 is word-addressing - let r = _mm_i64gather_epi32::<4>(arr.as_ptr(), _mm_setr_epi64x(0, 16)); + let r = unsafe { _mm_i64gather_epi32::<4>(arr.as_ptr(), _mm_setr_epi64x(0, 16)) }; assert_eq_m128i(r, _mm_setr_epi32(0, 16, 0, 0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_mask_i64gather_epi32() { + fn test_mm_mask_i64gather_epi32() { let arr: [i32; 128] = core::array::from_fn(|i| i as i32); // A multiplier of 4 is word-addressing - let r = _mm_mask_i64gather_epi32::<4>( - _mm_set1_epi32(256), - arr.as_ptr(), - _mm_setr_epi64x(0, 16), - _mm_setr_epi32(-1, 0, -1, 0), - ); + let r = unsafe { + _mm_mask_i64gather_epi32::<4>( + _mm_set1_epi32(256), + arr.as_ptr(), + _mm_setr_epi64x(0, 16), + _mm_setr_epi32(-1, 0, -1, 0), + ) + }; assert_eq_m128i(r, _mm_setr_epi32(0, 256, 0, 0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_i64gather_epi32() { + fn test_mm256_i64gather_epi32() { let arr: [i32; 128] = core::array::from_fn(|i| i as i32); // A multiplier of 4 is word-addressing - let r = _mm256_i64gather_epi32::<4>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)); + let r = + unsafe { _mm256_i64gather_epi32::<4>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)) }; assert_eq_m128i(r, _mm_setr_epi32(0, 16, 32, 48)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_mask_i64gather_epi32() { + fn test_mm256_mask_i64gather_epi32() { let arr: [i32; 128] = core::array::from_fn(|i| i as i32); // A multiplier of 4 is word-addressing - let r = _mm256_mask_i64gather_epi32::<4>( - _mm_set1_epi32(256), - arr.as_ptr(), - _mm256_setr_epi64x(0, 16, 64, 96), - _mm_setr_epi32(-1, -1, -1, 0), - ); + let r = unsafe { + _mm256_mask_i64gather_epi32::<4>( + _mm_set1_epi32(256), + arr.as_ptr(), + _mm256_setr_epi64x(0, 16, 64, 96), + _mm_setr_epi32(-1, -1, -1, 0), + ) + }; assert_eq_m128i(r, _mm_setr_epi32(0, 16, 64, 256)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_i64gather_ps() { + fn test_mm_i64gather_ps() { let arr: [f32; 128] = core::array::from_fn(|i| i as f32); // A multiplier of 4 is word-addressing for f32s - let r = _mm_i64gather_ps::<4>(arr.as_ptr(), _mm_setr_epi64x(0, 16)); + let r = unsafe { _mm_i64gather_ps::<4>(arr.as_ptr(), _mm_setr_epi64x(0, 16)) }; assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 0.0, 0.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_mask_i64gather_ps() { + fn test_mm_mask_i64gather_ps() { let arr: [f32; 128] = core::array::from_fn(|i| i as f32); // A multiplier of 4 is word-addressing for f32s - let r = _mm_mask_i64gather_ps::<4>( - _mm_set1_ps(256.0), - arr.as_ptr(), - _mm_setr_epi64x(0, 16), - _mm_setr_ps(-1.0, 0.0, -1.0, 0.0), - ); + let r = unsafe { + _mm_mask_i64gather_ps::<4>( + _mm_set1_ps(256.0), + arr.as_ptr(), + _mm_setr_epi64x(0, 16), + _mm_setr_ps(-1.0, 0.0, -1.0, 0.0), + ) + }; assert_eq_m128(r, _mm_setr_ps(0.0, 256.0, 0.0, 0.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_i64gather_ps() { + fn test_mm256_i64gather_ps() { let arr: [f32; 128] = core::array::from_fn(|i| i as f32); // A multiplier of 4 is word-addressing for f32s - let r = _mm256_i64gather_ps::<4>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)); + let r = + unsafe { _mm256_i64gather_ps::<4>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)) }; assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 32.0, 48.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_mask_i64gather_ps() { + fn test_mm256_mask_i64gather_ps() { let arr: [f32; 128] = core::array::from_fn(|i| i as f32); // A multiplier of 4 is word-addressing for f32s - let r = _mm256_mask_i64gather_ps::<4>( - _mm_set1_ps(256.0), - arr.as_ptr(), - _mm256_setr_epi64x(0, 16, 64, 96), - _mm_setr_ps(-1.0, -1.0, -1.0, 0.0), - ); + let r = unsafe { + _mm256_mask_i64gather_ps::<4>( + _mm_set1_ps(256.0), + arr.as_ptr(), + _mm256_setr_epi64x(0, 16, 64, 96), + _mm_setr_ps(-1.0, -1.0, -1.0, 0.0), + ) + }; assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 64.0, 256.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_i64gather_epi64() { + fn test_mm_i64gather_epi64() { let arr: [i64; 128] = core::array::from_fn(|i| i as i64); // A multiplier of 8 is word-addressing for i64s - let r = _mm_i64gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi64x(0, 16)); + let r = unsafe { _mm_i64gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi64x(0, 16)) }; assert_eq_m128i(r, _mm_setr_epi64x(0, 16)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_mask_i64gather_epi64() { + fn test_mm_mask_i64gather_epi64() { let arr: [i64; 128] = core::array::from_fn(|i| i as i64); // A multiplier of 8 is word-addressing for i64s - let r = _mm_mask_i64gather_epi64::<8>( - _mm_set1_epi64x(256), - arr.as_ptr(), - _mm_setr_epi64x(16, 16), - _mm_setr_epi64x(-1, 0), - ); + let r = unsafe { + _mm_mask_i64gather_epi64::<8>( + _mm_set1_epi64x(256), + arr.as_ptr(), + _mm_setr_epi64x(16, 16), + _mm_setr_epi64x(-1, 0), + ) + }; assert_eq_m128i(r, _mm_setr_epi64x(16, 256)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_i64gather_epi64() { + fn test_mm256_i64gather_epi64() { let arr: [i64; 128] = core::array::from_fn(|i| i as i64); // A multiplier of 8 is word-addressing for i64s - let r = _mm256_i64gather_epi64::<8>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)); + let r = + unsafe { _mm256_i64gather_epi64::<8>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)) }; assert_eq_m256i(r, _mm256_setr_epi64x(0, 16, 32, 48)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_mask_i64gather_epi64() { + fn test_mm256_mask_i64gather_epi64() { let arr: [i64; 128] = core::array::from_fn(|i| i as i64); // A multiplier of 8 is word-addressing for i64s - let r = _mm256_mask_i64gather_epi64::<8>( - _mm256_set1_epi64x(256), - arr.as_ptr(), - _mm256_setr_epi64x(0, 16, 64, 96), - _mm256_setr_epi64x(-1, -1, -1, 0), - ); + let r = unsafe { + _mm256_mask_i64gather_epi64::<8>( + _mm256_set1_epi64x(256), + arr.as_ptr(), + _mm256_setr_epi64x(0, 16, 64, 96), + _mm256_setr_epi64x(-1, -1, -1, 0), + ) + }; assert_eq_m256i(r, _mm256_setr_epi64x(0, 16, 64, 256)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_i64gather_pd() { + fn test_mm_i64gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); // A multiplier of 8 is word-addressing for f64s - let r = _mm_i64gather_pd::<8>(arr.as_ptr(), _mm_setr_epi64x(0, 16)); + let r = unsafe { _mm_i64gather_pd::<8>(arr.as_ptr(), _mm_setr_epi64x(0, 16)) }; assert_eq_m128d(r, _mm_setr_pd(0.0, 16.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm_mask_i64gather_pd() { + fn test_mm_mask_i64gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); // A multiplier of 8 is word-addressing for f64s - let r = _mm_mask_i64gather_pd::<8>( - _mm_set1_pd(256.0), - arr.as_ptr(), - _mm_setr_epi64x(16, 16), - _mm_setr_pd(-1.0, 0.0), - ); + let r = unsafe { + _mm_mask_i64gather_pd::<8>( + _mm_set1_pd(256.0), + arr.as_ptr(), + _mm_setr_epi64x(16, 16), + _mm_setr_pd(-1.0, 0.0), + ) + }; assert_eq_m128d(r, _mm_setr_pd(16.0, 256.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_i64gather_pd() { + fn test_mm256_i64gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); // A multiplier of 8 is word-addressing for f64s - let r = _mm256_i64gather_pd::<8>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)); + let r = + unsafe { _mm256_i64gather_pd::<8>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)) }; assert_eq_m256d(r, _mm256_setr_pd(0.0, 16.0, 32.0, 48.0)); } #[simd_test(enable = "avx2")] - unsafe fn test_mm256_mask_i64gather_pd() { + fn test_mm256_mask_i64gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); // A multiplier of 8 is word-addressing for f64s - let r = _mm256_mask_i64gather_pd::<8>( - _mm256_set1_pd(256.0), - arr.as_ptr(), - _mm256_setr_epi64x(0, 16, 64, 96), - _mm256_setr_pd(-1.0, -1.0, -1.0, 0.0), - ); + let r = unsafe { + _mm256_mask_i64gather_pd::<8>( + _mm256_set1_pd(256.0), + arr.as_ptr(), + _mm256_setr_epi64x(0, 16, 64, 96), + _mm256_setr_pd(-1.0, -1.0, -1.0, 0.0), + ) + }; assert_eq_m256d(r, _mm256_setr_pd(0.0, 16.0, 64.0, 256.0)); } diff --git a/library/stdarch/crates/core_arch/src/x86/avx512bf16.rs b/library/stdarch/crates/core_arch/src/x86/avx512bf16.rs index 83dbc540a0c8..66eef063eed8 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512bf16.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512bf16.rs @@ -593,7 +593,7 @@ pub fn _mm_cvtness_sbh(a: f32) -> bf16 { #[cfg(test)] mod tests { - use crate::core_arch::simd::u16x4; + use crate::core_arch::simd::{f32x4, f32x8, f32x16, u16x4, u16x8, u16x16, u16x32}; use crate::{ core_arch::x86::*, mem::{transmute, transmute_copy}, @@ -601,13 +601,13 @@ mod tests { use stdarch_test::simd_test; #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm_cvtne2ps_pbh() { + fn test_mm_cvtne2ps_pbh() { let a_array = [178.125_f32, 10.5_f32, 3.75_f32, 50.25_f32]; let b_array = [-178.125_f32, -10.5_f32, -3.75_f32, -50.25_f32]; - let a: __m128 = transmute(a_array); - let b: __m128 = transmute(b_array); + let a = f32x4::from_array(a_array).as_m128(); + let b = f32x4::from_array(b_array).as_m128(); let c: __m128bh = _mm_cvtne2ps_pbh(a, b); - let result: [u16; 8] = transmute(c.as_u16x8()); + let result = *c.as_u16x8().as_array(); #[rustfmt::skip] let expected_result: [u16; 8] = [ 0b1_10000110_0110010, @@ -623,7 +623,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm_mask_cvtne2ps_pbh() { + fn test_mm_mask_cvtne2ps_pbh() { let a_array = [178.125_f32, 10.5_f32, 3.75_f32, 50.25_f32]; let b_array = [-178.125_f32, -10.5_f32, -3.75_f32, -50.25_f32]; #[rustfmt::skip] @@ -637,12 +637,12 @@ mod tests { 0b0_10000000_1110000, 0b0_10000100_1001001, ]; - let src: __m128bh = transmute(src_array); - let a: __m128 = transmute(a_array); - let b: __m128 = transmute(b_array); + let src = u16x8::from_array(src_array).as_m128bh(); + let a = f32x4::from_array(a_array).as_m128(); + let b = f32x4::from_array(b_array).as_m128(); let k: __mmask8 = 0b1111_1111; let c: __m128bh = _mm_mask_cvtne2ps_pbh(src, k, a, b); - let result: [u16; 8] = transmute(c.as_u16x8()); + let result = *c.as_u16x8().as_array(); #[rustfmt::skip] let expected_result: [u16; 8] = [ 0b1_10000110_0110010, @@ -657,20 +657,20 @@ mod tests { assert_eq!(result, expected_result); let k = 0b0000_0000; let c = _mm_mask_cvtne2ps_pbh(src, k, a, b); - let result: [u16; 8] = transmute(c.as_u16x8()); + let result = *c.as_u16x8().as_array(); let expected_result = src_array; assert_eq!(result, expected_result); } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm_maskz_cvtne2ps_pbh() { + fn test_mm_maskz_cvtne2ps_pbh() { let a_array = [178.125_f32, 10.5_f32, 3.75_f32, 50.25_f32]; let b_array = [-178.125_f32, -10.5_f32, -3.75_f32, -50.25_f32]; - let a: __m128 = transmute(a_array); - let b: __m128 = transmute(b_array); + let a = f32x4::from_array(a_array).as_m128(); + let b = f32x4::from_array(b_array).as_m128(); let k: __mmask8 = 0b1111_1111; let c: __m128bh = _mm_maskz_cvtne2ps_pbh(k, a, b); - let result: [u16; 8] = transmute(c.as_u16x8()); + let result = *c.as_u16x8().as_array(); #[rustfmt::skip] let expected_result: [u16; 8] = [ 0b1_10000110_0110010, @@ -685,7 +685,7 @@ mod tests { assert_eq!(result, expected_result); let k = 0b0011_1100; let c = _mm_maskz_cvtne2ps_pbh(k, a, b); - let result: [u16; 8] = transmute(c.as_u16x8()); + let result = *c.as_u16x8().as_array(); #[rustfmt::skip] let expected_result: [u16; 8] = [ 0, @@ -701,7 +701,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm256_cvtne2ps_pbh() { + fn test_mm256_cvtne2ps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -723,10 +723,10 @@ mod tests { -1000.158_f32, -575.575_f32, ]; - let a: __m256 = transmute(a_array); - let b: __m256 = transmute(b_array); + let a = f32x8::from_array(a_array).as_m256(); + let b = f32x8::from_array(b_array).as_m256(); let c: __m256bh = _mm256_cvtne2ps_pbh(a, b); - let result: [u16; 16] = transmute(c.as_u16x16()); + let result = *c.as_u16x16().as_array(); #[rustfmt::skip] let expected_result: [u16; 16] = [ 0b1_10000110_0110010, @@ -750,7 +750,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm256_mask_cvtne2ps_pbh() { + fn test_mm256_mask_cvtne2ps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -790,12 +790,12 @@ mod tests { 0b0_10000000_1110000, 0b0_10000100_1001001, ]; - let src: __m256bh = transmute(src_array); - let a: __m256 = transmute(a_array); - let b: __m256 = transmute(b_array); + let src = u16x16::from_array(src_array).as_m256bh(); + let a = f32x8::from_array(a_array).as_m256(); + let b = f32x8::from_array(b_array).as_m256(); let k: __mmask16 = 0xffff; let c: __m256bh = _mm256_mask_cvtne2ps_pbh(src, k, a, b); - let result: [u16; 16] = transmute(c.as_u16x16()); + let result = *c.as_u16x16().as_array(); #[rustfmt::skip] let expected_result: [u16; 16] = [ 0b1_10000110_0110010, @@ -818,13 +818,13 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask16 = 0; let c: __m256bh = _mm256_mask_cvtne2ps_pbh(src, k, a, b); - let result: [u16; 16] = transmute(c.as_u16x16()); + let result = *c.as_u16x16().as_array(); let expected_result = src_array; assert_eq!(result, expected_result); } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm256_maskz_cvtne2ps_pbh() { + fn test_mm256_maskz_cvtne2ps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -846,11 +846,11 @@ mod tests { -1000.158_f32, -575.575_f32, ]; - let a: __m256 = transmute(a_array); - let b: __m256 = transmute(b_array); + let a = f32x8::from_array(a_array).as_m256(); + let b = f32x8::from_array(b_array).as_m256(); let k: __mmask16 = 0xffff; let c: __m256bh = _mm256_maskz_cvtne2ps_pbh(k, a, b); - let result: [u16; 16] = transmute(c.as_u16x16()); + let result = *c.as_u16x16().as_array(); #[rustfmt::skip] let expected_result: [u16; 16] = [ 0b1_10000110_0110010, @@ -873,7 +873,7 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask16 = 0b0110_1100_0011_0110; let c: __m256bh = _mm256_maskz_cvtne2ps_pbh(k, a, b); - let result: [u16; 16] = transmute(c.as_u16x16()); + let result = *c.as_u16x16().as_array(); #[rustfmt::skip] let expected_result: [u16; 16] = [ 0, @@ -897,7 +897,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512f")] - unsafe fn test_mm512_cvtne2ps_pbh() { + fn test_mm512_cvtne2ps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -935,10 +935,10 @@ mod tests { -1000.158_f32, -575.575_f32, ]; - let a: __m512 = transmute(a_array); - let b: __m512 = transmute(b_array); + let a = f32x16::from_array(a_array).as_m512(); + let b = f32x16::from_array(b_array).as_m512(); let c: __m512bh = _mm512_cvtne2ps_pbh(a, b); - let result: [u16; 32] = transmute(c.as_u16x32()); + let result = *c.as_u16x32().as_array(); #[rustfmt::skip] let expected_result: [u16; 32] = [ 0b1_10000110_0110010, @@ -978,7 +978,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512f")] - unsafe fn test_mm512_mask_cvtne2ps_pbh() { + fn test_mm512_mask_cvtne2ps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -1050,12 +1050,12 @@ mod tests { 0b0_10000000_1110000, 0b0_10000100_1001001, ]; - let src: __m512bh = transmute(src_array); - let a: __m512 = transmute(a_array); - let b: __m512 = transmute(b_array); + let src = u16x32::from_array(src_array).as_m512bh(); + let a = f32x16::from_array(a_array).as_m512(); + let b = f32x16::from_array(b_array).as_m512(); let k: __mmask32 = 0xffffffff; let c: __m512bh = _mm512_mask_cvtne2ps_pbh(src, k, a, b); - let result: [u16; 32] = transmute(c.as_u16x32()); + let result = *c.as_u16x32().as_array(); #[rustfmt::skip] let expected_result: [u16; 32] = [ 0b1_10000110_0110010, @@ -1094,13 +1094,13 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask32 = 0; let c: __m512bh = _mm512_mask_cvtne2ps_pbh(src, k, a, b); - let result: [u16; 32] = transmute(c.as_u16x32()); + let result = *c.as_u16x32().as_array(); let expected_result = src_array; assert_eq!(result, expected_result); } #[simd_test(enable = "avx512bf16,avx512f")] - unsafe fn test_mm512_maskz_cvtne2ps_pbh() { + fn test_mm512_maskz_cvtne2ps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -1138,11 +1138,11 @@ mod tests { -1000.158_f32, -575.575_f32, ]; - let a: __m512 = transmute(a_array); - let b: __m512 = transmute(b_array); + let a = f32x16::from_array(a_array).as_m512(); + let b = f32x16::from_array(b_array).as_m512(); let k: __mmask32 = 0xffffffff; let c: __m512bh = _mm512_maskz_cvtne2ps_pbh(k, a, b); - let result: [u16; 32] = transmute(c.as_u16x32()); + let result = *c.as_u16x32().as_array(); #[rustfmt::skip] let expected_result: [u16; 32] = [ 0b1_10000110_0110010, @@ -1181,7 +1181,7 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask32 = 0b1100_1010_1001_0110_1010_0011_0101_0110; let c: __m512bh = _mm512_maskz_cvtne2ps_pbh(k, a, b); - let result: [u16; 32] = transmute(c.as_u16x32()); + let result = *c.as_u16x32().as_array(); #[rustfmt::skip] let expected_result: [u16; 32] = [ 0, @@ -1221,7 +1221,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm256_cvtneps_pbh() { + fn test_mm256_cvtneps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -1233,9 +1233,9 @@ mod tests { 1000.158_f32, 575.575_f32, ]; - let a: __m256 = transmute(a_array); + let a = f32x8::from_array(a_array).as_m256(); let c: __m128bh = _mm256_cvtneps_pbh(a); - let result: [u16; 8] = transmute(c.as_u16x8()); + let result = *c.as_u16x8().as_array(); #[rustfmt::skip] let expected_result: [u16; 8] = [ 0b0_10000110_0110010, @@ -1251,7 +1251,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm256_mask_cvtneps_pbh() { + fn test_mm256_mask_cvtneps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -1273,11 +1273,11 @@ mod tests { 0b1_10001000_1111010, 0b1_10001000_0010000, ]; - let src: __m128bh = transmute(src_array); - let a: __m256 = transmute(a_array); + let src = u16x8::from_array(src_array).as_m128bh(); + let a = f32x8::from_array(a_array).as_m256(); let k: __mmask8 = 0xff; let b = _mm256_mask_cvtneps_pbh(src, k, a); - let result: [u16; 8] = transmute(b.as_u16x8()); + let result = *b.as_u16x8().as_array(); #[rustfmt::skip] let expected_result: [u16; 8] = [ 0b0_10000110_0110010, @@ -1292,13 +1292,13 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask8 = 0x0; let b: __m128bh = _mm256_mask_cvtneps_pbh(src, k, a); - let result: [u16; 8] = transmute(b.as_u16x8()); + let result = *b.as_u16x8().as_array(); let expected_result: [u16; 8] = src_array; assert_eq!(result, expected_result); } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm256_maskz_cvtneps_pbh() { + fn test_mm256_maskz_cvtneps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -1310,10 +1310,10 @@ mod tests { 1000.158_f32, 575.575_f32, ]; - let a: __m256 = transmute(a_array); + let a = f32x8::from_array(a_array).as_m256(); let k: __mmask8 = 0xff; let b = _mm256_maskz_cvtneps_pbh(k, a); - let result: [u16; 8] = transmute(b.as_u16x8()); + let result = *b.as_u16x8().as_array(); #[rustfmt::skip] let expected_result: [u16; 8] = [ 0b0_10000110_0110010, @@ -1328,14 +1328,14 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask8 = 0x6; let b: __m128bh = _mm256_maskz_cvtneps_pbh(k, a); - let result: [u16; 8] = transmute(b.as_u16x8()); + let result = *b.as_u16x8().as_array(); let expected_result: [u16; 8] = [0, 0b0_10000010_0101000, 0b0_10000000_1110000, 0, 0, 0, 0, 0]; assert_eq!(result, expected_result); } #[simd_test(enable = "avx512bf16,avx512f")] - unsafe fn test_mm512_cvtneps_pbh() { + fn test_mm512_cvtneps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -1355,9 +1355,9 @@ mod tests { 1000.158_f32, 575.575_f32, ]; - let a: __m512 = transmute(a_array); + let a = f32x16::from_array(a_array).as_m512(); let c: __m256bh = _mm512_cvtneps_pbh(a); - let result: [u16; 16] = transmute(c.as_u16x16()); + let result = *c.as_u16x16().as_array(); #[rustfmt::skip] let expected_result: [u16; 16] = [ 0b0_10000110_0110010, @@ -1381,7 +1381,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512f")] - unsafe fn test_mm512_mask_cvtneps_pbh() { + fn test_mm512_mask_cvtneps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -1419,11 +1419,11 @@ mod tests { 0b1_10001000_1111010, 0b1_10001000_0010000, ]; - let src: __m256bh = transmute(src_array); - let a: __m512 = transmute(a_array); + let src = u16x16::from_array(src_array).as_m256bh(); + let a = f32x16::from_array(a_array).as_m512(); let k: __mmask16 = 0xffff; let c: __m256bh = _mm512_mask_cvtneps_pbh(src, k, a); - let result: [u16; 16] = transmute(c.as_u16x16()); + let result = *c.as_u16x16().as_array(); #[rustfmt::skip] let expected_result: [u16; 16] = [ 0b0_10000110_0110010, @@ -1446,13 +1446,13 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask16 = 0; let c: __m256bh = _mm512_mask_cvtneps_pbh(src, k, a); - let result: [u16; 16] = transmute(c.as_u16x16()); + let result = *c.as_u16x16().as_array(); let expected_result = src_array; assert_eq!(result, expected_result); } #[simd_test(enable = "avx512bf16,avx512f")] - unsafe fn test_mm512_maskz_cvtneps_pbh() { + fn test_mm512_maskz_cvtneps_pbh() { #[rustfmt::skip] let a_array = [ 178.125_f32, @@ -1472,10 +1472,10 @@ mod tests { 1000.158_f32, 575.575_f32, ]; - let a: __m512 = transmute(a_array); + let a = f32x16::from_array(a_array).as_m512(); let k: __mmask16 = 0xffff; let c: __m256bh = _mm512_maskz_cvtneps_pbh(k, a); - let result: [u16; 16] = transmute(c.as_u16x16()); + let result = *c.as_u16x16().as_array(); #[rustfmt::skip] let expected_result: [u16; 16] = [ 0b0_10000110_0110010, @@ -1498,7 +1498,7 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask16 = 0x653a; let c: __m256bh = _mm512_maskz_cvtneps_pbh(k, a); - let result: [u16; 16] = transmute(c.as_u16x16()); + let result = *c.as_u16x16().as_array(); #[rustfmt::skip] let expected_result: [u16; 16] = [ 0, @@ -1522,74 +1522,74 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm_dpbf16_ps() { + fn test_mm_dpbf16_ps() { let a_array = [8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32]; let b_array = [-1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32]; - let a1: __m128 = transmute(a_array); - let b1: __m128 = transmute(b_array); - let src: __m128 = transmute([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]); + let a1 = f32x4::from_array(a_array).as_m128(); + let b1 = f32x4::from_array(b_array).as_m128(); + let src = f32x4::from_array([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]).as_m128(); let a: __m128bh = _mm_cvtne2ps_pbh(a1, a1); let b: __m128bh = _mm_cvtne2ps_pbh(b1, b1); let c: __m128 = _mm_dpbf16_ps(src, a, b); - let result: [f32; 4] = transmute(c.as_f32x4()); + let result = *c.as_f32x4().as_array(); let expected_result: [f32; 4] = [-18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32]; assert_eq!(result, expected_result); } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm_mask_dpbf16_ps() { + fn test_mm_mask_dpbf16_ps() { let a_array = [8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32]; let b_array = [-1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32]; - let a1: __m128 = transmute(a_array); - let b1: __m128 = transmute(b_array); + let a1 = f32x4::from_array(a_array).as_m128(); + let b1 = f32x4::from_array(b_array).as_m128(); let k: __mmask8 = 0xf3; - let src: __m128 = transmute([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]); + let src = f32x4::from_array([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]).as_m128(); let a: __m128bh = _mm_cvtne2ps_pbh(a1, a1); let b: __m128bh = _mm_cvtne2ps_pbh(b1, b1); let c: __m128 = _mm_mask_dpbf16_ps(src, k, a, b); - let result: [f32; 4] = transmute(c.as_f32x4()); + let result = *c.as_f32x4().as_array(); let expected_result: [f32; 4] = [-18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32]; assert_eq!(result, expected_result); let k: __mmask8 = 0xff; let c: __m128 = _mm_mask_dpbf16_ps(src, k, a, b); - let result: [f32; 4] = transmute(c.as_f32x4()); + let result = *c.as_f32x4().as_array(); let expected_result: [f32; 4] = [-18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32]; assert_eq!(result, expected_result); let k: __mmask8 = 0; let c: __m128 = _mm_mask_dpbf16_ps(src, k, a, b); - let result: [f32; 4] = transmute(c.as_f32x4()); + let result = *c.as_f32x4().as_array(); let expected_result: [f32; 4] = [1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]; assert_eq!(result, expected_result); } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm_maskz_dpbf16_ps() { + fn test_mm_maskz_dpbf16_ps() { let a_array = [8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32]; let b_array = [-1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32]; - let a1: __m128 = transmute(a_array); - let b1: __m128 = transmute(b_array); + let a1 = f32x4::from_array(a_array).as_m128(); + let b1 = f32x4::from_array(b_array).as_m128(); let k: __mmask8 = 0xf3; - let src: __m128 = transmute([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]); + let src = f32x4::from_array([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]).as_m128(); let a: __m128bh = _mm_cvtne2ps_pbh(a1, a1); let b: __m128bh = _mm_cvtne2ps_pbh(b1, b1); let c: __m128 = _mm_maskz_dpbf16_ps(k, src, a, b); - let result: [f32; 4] = transmute(c.as_f32x4()); + let result = *c.as_f32x4().as_array(); let expected_result: [f32; 4] = [-18.0_f32, -52.0_f32, 0.0, 0.0]; assert_eq!(result, expected_result); let k: __mmask8 = 0xff; let c: __m128 = _mm_maskz_dpbf16_ps(k, src, a, b); - let result: [f32; 4] = transmute(c.as_f32x4()); + let result = *c.as_f32x4().as_array(); let expected_result: [f32; 4] = [-18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32]; assert_eq!(result, expected_result); let k: __mmask8 = 0; let c: __m128 = _mm_maskz_dpbf16_ps(k, src, a, b); - let result: [f32; 4] = transmute(c.as_f32x4()); + let result = *c.as_f32x4().as_array(); let expected_result: [f32; 4] = [0.0, 0.0, 0.0, 0.0]; assert_eq!(result, expected_result); } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm256_dpbf16_ps() { + fn test_mm256_dpbf16_ps() { #[rustfmt::skip] let a_array = [ 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, @@ -1597,16 +1597,16 @@ mod tests { let b_array = [ -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, ]; - let a1: __m256 = transmute(a_array); - let b1: __m256 = transmute(b_array); + let a1 = f32x8::from_array(a_array).as_m256(); + let b1 = f32x8::from_array(b_array).as_m256(); #[rustfmt::skip] - let src: __m256 = transmute([ + let src = f32x8::from_array([ 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, - ]); + ]).as_m256(); let a: __m256bh = _mm256_cvtne2ps_pbh(a1, a1); let b: __m256bh = _mm256_cvtne2ps_pbh(b1, b1); let c: __m256 = _mm256_dpbf16_ps(src, a, b); - let result: [f32; 8] = transmute(c.as_f32x8()); + let result = *c.as_f32x8().as_array(); #[rustfmt::skip] let expected_result: [f32; 8] = [ -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, @@ -1615,7 +1615,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm256_mask_dpbf16_ps() { + fn test_mm256_mask_dpbf16_ps() { #[rustfmt::skip] let a_array = [ 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, @@ -1623,17 +1623,17 @@ mod tests { let b_array = [ -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, ]; - let a1: __m256 = transmute(a_array); - let b1: __m256 = transmute(b_array); + let a1 = f32x8::from_array(a_array).as_m256(); + let b1 = f32x8::from_array(b_array).as_m256(); let k: __mmask8 = 0x33; #[rustfmt::skip] - let src: __m256 = transmute([ + let src = f32x8::from_array([ 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, - ]); + ]).as_m256(); let a: __m256bh = _mm256_cvtne2ps_pbh(a1, a1); let b: __m256bh = _mm256_cvtne2ps_pbh(b1, b1); let c: __m256 = _mm256_mask_dpbf16_ps(src, k, a, b); - let result: [f32; 8] = transmute(c.as_f32x8()); + let result = *c.as_f32x8().as_array(); #[rustfmt::skip] let expected_result: [f32; 8] = [ -18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32, -18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32, @@ -1641,7 +1641,7 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask8 = 0xff; let c: __m256 = _mm256_mask_dpbf16_ps(src, k, a, b); - let result: [f32; 8] = transmute(c.as_f32x8()); + let result = *c.as_f32x8().as_array(); #[rustfmt::skip] let expected_result: [f32; 8] = [ -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, @@ -1649,7 +1649,7 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask8 = 0; let c: __m256 = _mm256_mask_dpbf16_ps(src, k, a, b); - let result: [f32; 8] = transmute(c.as_f32x8()); + let result = *c.as_f32x8().as_array(); #[rustfmt::skip] let expected_result: [f32; 8] = [ 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, @@ -1658,7 +1658,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm256_maskz_dpbf16_ps() { + fn test_mm256_maskz_dpbf16_ps() { #[rustfmt::skip] let a_array = [ 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, @@ -1666,17 +1666,17 @@ mod tests { let b_array = [ -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, ]; - let a1: __m256 = transmute(a_array); - let b1: __m256 = transmute(b_array); + let a1 = f32x8::from_array(a_array).as_m256(); + let b1 = f32x8::from_array(b_array).as_m256(); let k: __mmask8 = 0x33; #[rustfmt::skip] - let src: __m256 = transmute([ + let src = f32x8::from_array([ 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, - ]); + ]).as_m256(); let a: __m256bh = _mm256_cvtne2ps_pbh(a1, a1); let b: __m256bh = _mm256_cvtne2ps_pbh(b1, b1); let c: __m256 = _mm256_maskz_dpbf16_ps(k, src, a, b); - let result: [f32; 8] = transmute(c.as_f32x8()); + let result = *c.as_f32x8().as_array(); #[rustfmt::skip] let expected_result: [f32; 8] = [ -18.0_f32, -52.0_f32, 0.0, 0.0, -18.0_f32, -52.0_f32, 0.0, 0.0, @@ -1684,7 +1684,7 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask8 = 0xff; let c: __m256 = _mm256_maskz_dpbf16_ps(k, src, a, b); - let result: [f32; 8] = transmute(c.as_f32x8()); + let result = *c.as_f32x8().as_array(); #[rustfmt::skip] let expected_result: [f32; 8] = [ -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, @@ -1692,13 +1692,13 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask8 = 0; let c: __m256 = _mm256_maskz_dpbf16_ps(k, src, a, b); - let result: [f32; 8] = transmute(c.as_f32x8()); + let result = *c.as_f32x8().as_array(); let expected_result: [f32; 8] = [0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0]; assert_eq!(result, expected_result); } #[simd_test(enable = "avx512bf16,avx512f")] - unsafe fn test_mm512_dpbf16_ps() { + fn test_mm512_dpbf16_ps() { #[rustfmt::skip] let a_array = [ 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, @@ -1708,16 +1708,17 @@ mod tests { -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, ]; - let a1: __m512 = transmute(a_array); - let b1: __m512 = transmute(b_array); - let src: __m512 = transmute([ + let a1 = f32x16::from_array(a_array).as_m512(); + let b1 = f32x16::from_array(b_array).as_m512(); + let src = f32x16::from_array([ 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, - ]); + ]) + .as_m512(); let a: __m512bh = _mm512_cvtne2ps_pbh(a1, a1); let b: __m512bh = _mm512_cvtne2ps_pbh(b1, b1); let c: __m512 = _mm512_dpbf16_ps(src, a, b); - let result: [f32; 16] = transmute(c.as_f32x16()); + let result = *c.as_f32x16().as_array(); #[rustfmt::skip] let expected_result: [f32; 16] = [ -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, @@ -1727,7 +1728,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512f")] - unsafe fn test_mm512_mask_dpbf16_ps() { + fn test_mm512_mask_dpbf16_ps() { #[rustfmt::skip] let a_array = [ 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, @@ -1737,18 +1738,18 @@ mod tests { -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, ]; - let a1: __m512 = transmute(a_array); - let b1: __m512 = transmute(b_array); + let a1 = f32x16::from_array(a_array).as_m512(); + let b1 = f32x16::from_array(b_array).as_m512(); let k: __mmask16 = 0x3333; #[rustfmt::skip] - let src: __m512 = transmute([ + let src = f32x16::from_array([ 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, - ]); + ]).as_m512(); let a: __m512bh = _mm512_cvtne2ps_pbh(a1, a1); let b: __m512bh = _mm512_cvtne2ps_pbh(b1, b1); let c: __m512 = _mm512_mask_dpbf16_ps(src, k, a, b); - let result: [f32; 16] = transmute(c.as_f32x16()); + let result = *c.as_f32x16().as_array(); #[rustfmt::skip] let expected_result: [f32; 16] = [ -18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32, -18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32, @@ -1757,7 +1758,7 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask16 = 0xffff; let c: __m512 = _mm512_mask_dpbf16_ps(src, k, a, b); - let result: [f32; 16] = transmute(c.as_f32x16()); + let result = *c.as_f32x16().as_array(); #[rustfmt::skip] let expected_result: [f32; 16] = [ -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, @@ -1766,7 +1767,7 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask16 = 0; let c: __m512 = _mm512_mask_dpbf16_ps(src, k, a, b); - let result: [f32; 16] = transmute(c.as_f32x16()); + let result = *c.as_f32x16().as_array(); #[rustfmt::skip] let expected_result: [f32; 16] = [ 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, @@ -1776,7 +1777,7 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512f")] - unsafe fn test_mm512_maskz_dpbf16_ps() { + fn test_mm512_maskz_dpbf16_ps() { #[rustfmt::skip] let a_array = [ 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, @@ -1786,18 +1787,18 @@ mod tests { -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, ]; - let a1: __m512 = transmute(a_array); - let b1: __m512 = transmute(b_array); + let a1 = f32x16::from_array(a_array).as_m512(); + let b1 = f32x16::from_array(b_array).as_m512(); let k: __mmask16 = 0x3333; #[rustfmt::skip] - let src: __m512 = transmute([ + let src = f32x16::from_array([ 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, - ]); + ]).as_m512(); let a: __m512bh = _mm512_cvtne2ps_pbh(a1, a1); let b: __m512bh = _mm512_cvtne2ps_pbh(b1, b1); let c: __m512 = _mm512_maskz_dpbf16_ps(k, src, a, b); - let result: [f32; 16] = transmute(c.as_f32x16()); + let result = *c.as_f32x16().as_array(); #[rustfmt::skip] let expected_result: [f32; 16] = [ -18.0_f32, -52.0_f32, 0.0, 0.0, -18.0_f32, -52.0_f32, 0.0, 0.0, -18.0_f32, -52.0_f32, @@ -1806,7 +1807,7 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask16 = 0xffff; let c: __m512 = _mm512_maskz_dpbf16_ps(k, src, a, b); - let result: [f32; 16] = transmute(c.as_f32x16()); + let result = *c.as_f32x16().as_array(); #[rustfmt::skip] let expected_result: [f32; 16] = [ -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, @@ -1815,7 +1816,7 @@ mod tests { assert_eq!(result, expected_result); let k: __mmask16 = 0; let c: __m512 = _mm512_maskz_dpbf16_ps(k, src, a, b); - let result: [f32; 16] = transmute(c.as_f32x16()); + let result = *c.as_f32x16().as_array(); #[rustfmt::skip] let expected_result: [f32; 16] = [ 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, @@ -1943,28 +1944,28 @@ mod tests { } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm_cvtneps_pbh() { + fn test_mm_cvtneps_pbh() { let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); - let r: u16x4 = transmute_copy(&_mm_cvtneps_pbh(a)); + let r: u16x4 = unsafe { transmute_copy(&_mm_cvtneps_pbh(a)) }; let e = u16x4::new(BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR); assert_eq!(r, e); } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm_mask_cvtneps_pbh() { + fn test_mm_mask_cvtneps_pbh() { let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); let src = __m128bh([5, 6, 7, 8, !0, !0, !0, !0]); let k = 0b1010; - let r: u16x4 = transmute_copy(&_mm_mask_cvtneps_pbh(src, k, a)); + let r: u16x4 = unsafe { transmute_copy(&_mm_mask_cvtneps_pbh(src, k, a)) }; let e = u16x4::new(5, BF16_TWO, 7, BF16_FOUR); assert_eq!(r, e); } #[simd_test(enable = "avx512bf16,avx512vl")] - unsafe fn test_mm_maskz_cvtneps_pbh() { + fn test_mm_maskz_cvtneps_pbh() { let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); let k = 0b1010; - let r: u16x4 = transmute_copy(&_mm_maskz_cvtneps_pbh(k, a)); + let r: u16x4 = unsafe { transmute_copy(&_mm_maskz_cvtneps_pbh(k, a)) }; let e = u16x4::new(0, BF16_TWO, 0, BF16_FOUR); assert_eq!(r, e); } diff --git a/library/stdarch/crates/core_arch/src/x86/avx512bw.rs b/library/stdarch/crates/core_arch/src/x86/avx512bw.rs index 6b4b88621efd..8e074fdcfa48 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512bw.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512bw.rs @@ -17098,37 +17098,37 @@ mod tests { } #[simd_test(enable = "avx512bw")] - const unsafe fn test_mm512_loadu_epi16() { + const fn test_mm512_loadu_epi16() { #[rustfmt::skip] let a: [i16; 32] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let r = _mm512_loadu_epi16(&a[0]); + let r = unsafe { _mm512_loadu_epi16(&a[0]) }; #[rustfmt::skip] let e = _mm512_set_epi16(32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm256_loadu_epi16() { + const fn test_mm256_loadu_epi16() { let a: [i16; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let r = _mm256_loadu_epi16(&a[0]); + let r = unsafe { _mm256_loadu_epi16(&a[0]) }; let e = _mm256_set_epi16(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm_loadu_epi16() { + const fn test_mm_loadu_epi16() { let a: [i16; 8] = [1, 2, 3, 4, 5, 6, 7, 8]; - let r = _mm_loadu_epi16(&a[0]); + let r = unsafe { _mm_loadu_epi16(&a[0]) }; let e = _mm_set_epi16(8, 7, 6, 5, 4, 3, 2, 1); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_mm512_loadu_epi8() { + const fn test_mm512_loadu_epi8() { #[rustfmt::skip] let a: [i8; 64] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let r = _mm512_loadu_epi8(&a[0]); + let r = unsafe { _mm512_loadu_epi8(&a[0]) }; #[rustfmt::skip] let e = _mm512_set_epi8(32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1); @@ -17136,73 +17136,85 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm256_loadu_epi8() { + const fn test_mm256_loadu_epi8() { #[rustfmt::skip] let a: [i8; 32] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let r = _mm256_loadu_epi8(&a[0]); + let r = unsafe { _mm256_loadu_epi8(&a[0]) }; #[rustfmt::skip] let e = _mm256_set_epi8(32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm_loadu_epi8() { + const fn test_mm_loadu_epi8() { let a: [i8; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let r = _mm_loadu_epi8(&a[0]); + let r = unsafe { _mm_loadu_epi8(&a[0]) }; let e = _mm_set_epi8(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_mm512_storeu_epi16() { + const fn test_mm512_storeu_epi16() { let a = _mm512_set1_epi16(9); let mut r = _mm512_undefined_epi32(); - _mm512_storeu_epi16(&mut r as *mut _ as *mut i16, a); + unsafe { + _mm512_storeu_epi16(&mut r as *mut _ as *mut i16, a); + } assert_eq_m512i(r, a); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm256_storeu_epi16() { + const fn test_mm256_storeu_epi16() { let a = _mm256_set1_epi16(9); let mut r = _mm256_set1_epi32(0); - _mm256_storeu_epi16(&mut r as *mut _ as *mut i16, a); + unsafe { + _mm256_storeu_epi16(&mut r as *mut _ as *mut i16, a); + } assert_eq_m256i(r, a); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm_storeu_epi16() { + const fn test_mm_storeu_epi16() { let a = _mm_set1_epi16(9); let mut r = _mm_set1_epi32(0); - _mm_storeu_epi16(&mut r as *mut _ as *mut i16, a); + unsafe { + _mm_storeu_epi16(&mut r as *mut _ as *mut i16, a); + } assert_eq_m128i(r, a); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_mm512_storeu_epi8() { + const fn test_mm512_storeu_epi8() { let a = _mm512_set1_epi8(9); let mut r = _mm512_undefined_epi32(); - _mm512_storeu_epi8(&mut r as *mut _ as *mut i8, a); + unsafe { + _mm512_storeu_epi8(&mut r as *mut _ as *mut i8, a); + } assert_eq_m512i(r, a); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm256_storeu_epi8() { + const fn test_mm256_storeu_epi8() { let a = _mm256_set1_epi8(9); let mut r = _mm256_set1_epi32(0); - _mm256_storeu_epi8(&mut r as *mut _ as *mut i8, a); + unsafe { + _mm256_storeu_epi8(&mut r as *mut _ as *mut i8, a); + } assert_eq_m256i(r, a); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm_storeu_epi8() { + const fn test_mm_storeu_epi8() { let a = _mm_set1_epi8(9); let mut r = _mm_set1_epi32(0); - _mm_storeu_epi8(&mut r as *mut _ as *mut i8, a); + unsafe { + _mm_storeu_epi8(&mut r as *mut _ as *mut i8, a); + } assert_eq_m128i(r, a); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_mm512_mask_loadu_epi16() { + const fn test_mm512_mask_loadu_epi16() { let src = _mm512_set1_epi16(42); let a = &[ 1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, @@ -17210,52 +17222,54 @@ mod tests { ]; let p = a.as_ptr(); let m = 0b10101010_11001100_11101000_11001010; - let r = _mm512_mask_loadu_epi16(src, m, black_box(p)); + let r = unsafe { _mm512_mask_loadu_epi16(src, m, black_box(p)) }; let e = &[ 42_i16, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42, 23, 24, 42, 26, 42, 28, 42, 30, 42, 32, ]; - let e = _mm512_loadu_epi16(e.as_ptr()); + let e = unsafe { _mm512_loadu_epi16(e.as_ptr()) }; assert_eq_m512i(r, e); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_mm512_maskz_loadu_epi16() { + const fn test_mm512_maskz_loadu_epi16() { let a = &[ 1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, ]; let p = a.as_ptr(); let m = 0b10101010_11001100_11101000_11001010; - let r = _mm512_maskz_loadu_epi16(m, black_box(p)); + let r = unsafe { _mm512_maskz_loadu_epi16(m, black_box(p)) }; let e = &[ 0_i16, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16, 0, 0, 19, 20, 0, 0, 23, 24, 0, 26, 0, 28, 0, 30, 0, 32, ]; - let e = _mm512_loadu_epi16(e.as_ptr()); + let e = unsafe { _mm512_loadu_epi16(e.as_ptr()) }; assert_eq_m512i(r, e); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_mm512_mask_storeu_epi16() { + const fn test_mm512_mask_storeu_epi16() { let mut r = [42_i16; 32]; let a = &[ 1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, ]; - let a = _mm512_loadu_epi16(a.as_ptr()); + let a = unsafe { _mm512_loadu_epi16(a.as_ptr()) }; let m = 0b10101010_11001100_11101000_11001010; - _mm512_mask_storeu_epi16(r.as_mut_ptr(), m, a); + unsafe { + _mm512_mask_storeu_epi16(r.as_mut_ptr(), m, a); + } let e = &[ 42_i16, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42, 23, 24, 42, 26, 42, 28, 42, 30, 42, 32, ]; - let e = _mm512_loadu_epi16(e.as_ptr()); - assert_eq_m512i(_mm512_loadu_epi16(r.as_ptr()), e); + let e = unsafe { _mm512_loadu_epi16(e.as_ptr()) }; + assert_eq_m512i(unsafe { _mm512_loadu_epi16(r.as_ptr()) }, e); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_mm512_mask_loadu_epi8() { + const fn test_mm512_mask_loadu_epi8() { let src = _mm512_set1_epi8(42); let a = &[ 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, @@ -17264,18 +17278,18 @@ mod tests { ]; let p = a.as_ptr(); let m = 0b00000000_11111111_11111111_00000000_10101010_11001100_11101000_11001010; - let r = _mm512_mask_loadu_epi8(src, m, black_box(p)); + let r = unsafe { _mm512_mask_loadu_epi8(src, m, black_box(p)) }; let e = &[ 42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42, 23, 24, 42, 26, 42, 28, 42, 30, 42, 32, 42, 42, 42, 42, 42, 42, 42, 42, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 42, 42, 42, 42, 42, 42, 42, 42, ]; - let e = _mm512_loadu_epi8(e.as_ptr()); + let e = unsafe { _mm512_loadu_epi8(e.as_ptr()) }; assert_eq_m512i(r, e); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_mm512_maskz_loadu_epi8() { + const fn test_mm512_maskz_loadu_epi8() { let a = &[ 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, @@ -17283,77 +17297,81 @@ mod tests { ]; let p = a.as_ptr(); let m = 0b00000000_11111111_11111111_00000000_10101010_11001100_11101000_11001010; - let r = _mm512_maskz_loadu_epi8(m, black_box(p)); + let r = unsafe { _mm512_maskz_loadu_epi8(m, black_box(p)) }; let e = &[ 0_i8, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16, 0, 0, 19, 20, 0, 0, 23, 24, 0, 26, 0, 28, 0, 30, 0, 32, 0, 0, 0, 0, 0, 0, 0, 0, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 0, 0, 0, 0, 0, 0, 0, 0, ]; - let e = _mm512_loadu_epi8(e.as_ptr()); + let e = unsafe { _mm512_loadu_epi8(e.as_ptr()) }; assert_eq_m512i(r, e); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_mm512_mask_storeu_epi8() { + const fn test_mm512_mask_storeu_epi8() { let mut r = [42_i8; 64]; let a = &[ 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, ]; - let a = _mm512_loadu_epi8(a.as_ptr()); + let a = unsafe { _mm512_loadu_epi8(a.as_ptr()) }; let m = 0b00000000_11111111_11111111_00000000_10101010_11001100_11101000_11001010; - _mm512_mask_storeu_epi8(r.as_mut_ptr(), m, a); + unsafe { + _mm512_mask_storeu_epi8(r.as_mut_ptr(), m, a); + } let e = &[ 42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42, 23, 24, 42, 26, 42, 28, 42, 30, 42, 32, 42, 42, 42, 42, 42, 42, 42, 42, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 42, 42, 42, 42, 42, 42, 42, 42, ]; - let e = _mm512_loadu_epi8(e.as_ptr()); - assert_eq_m512i(_mm512_loadu_epi8(r.as_ptr()), e); + let e = unsafe { _mm512_loadu_epi8(e.as_ptr()) }; + assert_eq_m512i(unsafe { _mm512_loadu_epi8(r.as_ptr()) }, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm256_mask_loadu_epi16() { + const fn test_mm256_mask_loadu_epi16() { let src = _mm256_set1_epi16(42); let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm256_mask_loadu_epi16(src, m, black_box(p)); + let r = unsafe { _mm256_mask_loadu_epi16(src, m, black_box(p)) }; let e = &[ 42_i16, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, ]; - let e = _mm256_loadu_epi16(e.as_ptr()); + let e = unsafe { _mm256_loadu_epi16(e.as_ptr()) }; assert_eq_m256i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm256_maskz_loadu_epi16() { + const fn test_mm256_maskz_loadu_epi16() { let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm256_maskz_loadu_epi16(m, black_box(p)); + let r = unsafe { _mm256_maskz_loadu_epi16(m, black_box(p)) }; let e = &[0_i16, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16]; - let e = _mm256_loadu_epi16(e.as_ptr()); + let e = unsafe { _mm256_loadu_epi16(e.as_ptr()) }; assert_eq_m256i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm256_mask_storeu_epi16() { + const fn test_mm256_mask_storeu_epi16() { let mut r = [42_i16; 16]; let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let a = _mm256_loadu_epi16(a.as_ptr()); + let a = unsafe { _mm256_loadu_epi16(a.as_ptr()) }; let m = 0b11101000_11001010; - _mm256_mask_storeu_epi16(r.as_mut_ptr(), m, a); + unsafe { + _mm256_mask_storeu_epi16(r.as_mut_ptr(), m, a); + } let e = &[ 42_i16, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, ]; - let e = _mm256_loadu_epi16(e.as_ptr()); - assert_eq_m256i(_mm256_loadu_epi16(r.as_ptr()), e); + let e = unsafe { _mm256_loadu_epi16(e.as_ptr()) }; + assert_eq_m256i(unsafe { _mm256_loadu_epi16(r.as_ptr()) }, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm256_mask_loadu_epi8() { + const fn test_mm256_mask_loadu_epi8() { let src = _mm256_set1_epi8(42); let a = &[ 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, @@ -17361,122 +17379,124 @@ mod tests { ]; let p = a.as_ptr(); let m = 0b10101010_11001100_11101000_11001010; - let r = _mm256_mask_loadu_epi8(src, m, black_box(p)); + let r = unsafe { _mm256_mask_loadu_epi8(src, m, black_box(p)) }; let e = &[ 42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42, 23, 24, 42, 26, 42, 28, 42, 30, 42, 32, ]; - let e = _mm256_loadu_epi8(e.as_ptr()); + let e = unsafe { _mm256_loadu_epi8(e.as_ptr()) }; assert_eq_m256i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm256_maskz_loadu_epi8() { + const fn test_mm256_maskz_loadu_epi8() { let a = &[ 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, ]; let p = a.as_ptr(); let m = 0b10101010_11001100_11101000_11001010; - let r = _mm256_maskz_loadu_epi8(m, black_box(p)); + let r = unsafe { _mm256_maskz_loadu_epi8(m, black_box(p)) }; let e = &[ 0_i8, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16, 0, 0, 19, 20, 0, 0, 23, 24, 0, 26, 0, 28, 0, 30, 0, 32, ]; - let e = _mm256_loadu_epi8(e.as_ptr()); + let e = unsafe { _mm256_loadu_epi8(e.as_ptr()) }; assert_eq_m256i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm256_mask_storeu_epi8() { + const fn test_mm256_mask_storeu_epi8() { let mut r = [42_i8; 32]; let a = &[ 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, ]; - let a = _mm256_loadu_epi8(a.as_ptr()); + let a = unsafe { _mm256_loadu_epi8(a.as_ptr()) }; let m = 0b10101010_11001100_11101000_11001010; - _mm256_mask_storeu_epi8(r.as_mut_ptr(), m, a); + unsafe { + _mm256_mask_storeu_epi8(r.as_mut_ptr(), m, a); + } let e = &[ 42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42, 23, 24, 42, 26, 42, 28, 42, 30, 42, 32, ]; - let e = _mm256_loadu_epi8(e.as_ptr()); - assert_eq_m256i(_mm256_loadu_epi8(r.as_ptr()), e); + let e = unsafe { _mm256_loadu_epi8(e.as_ptr()) }; + assert_eq_m256i(unsafe { _mm256_loadu_epi8(r.as_ptr()) }, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm_mask_loadu_epi16() { + const fn test_mm_mask_loadu_epi16() { let src = _mm_set1_epi16(42); let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11001010; - let r = _mm_mask_loadu_epi16(src, m, black_box(p)); + let r = unsafe { _mm_mask_loadu_epi16(src, m, black_box(p)) }; let e = &[42_i16, 2, 42, 4, 42, 42, 7, 8]; - let e = _mm_loadu_epi16(e.as_ptr()); + let e = unsafe { _mm_loadu_epi16(e.as_ptr()) }; assert_eq_m128i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm_maskz_loadu_epi16() { + const fn test_mm_maskz_loadu_epi16() { let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11001010; - let r = _mm_maskz_loadu_epi16(m, black_box(p)); + let r = unsafe { _mm_maskz_loadu_epi16(m, black_box(p)) }; let e = &[0_i16, 2, 0, 4, 0, 0, 7, 8]; - let e = _mm_loadu_epi16(e.as_ptr()); + let e = unsafe { _mm_loadu_epi16(e.as_ptr()) }; assert_eq_m128i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm_mask_storeu_epi16() { + const fn test_mm_mask_storeu_epi16() { let mut r = [42_i16; 8]; let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8]; - let a = _mm_loadu_epi16(a.as_ptr()); + let a = unsafe { _mm_loadu_epi16(a.as_ptr()) }; let m = 0b11001010; - _mm_mask_storeu_epi16(r.as_mut_ptr(), m, a); + unsafe { _mm_mask_storeu_epi16(r.as_mut_ptr(), m, a) }; let e = &[42_i16, 2, 42, 4, 42, 42, 7, 8]; - let e = _mm_loadu_epi16(e.as_ptr()); - assert_eq_m128i(_mm_loadu_epi16(r.as_ptr()), e); + let e = unsafe { _mm_loadu_epi16(e.as_ptr()) }; + assert_eq_m128i(unsafe { _mm_loadu_epi16(r.as_ptr()) }, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm_mask_loadu_epi8() { + const fn test_mm_mask_loadu_epi8() { let src = _mm_set1_epi8(42); let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm_mask_loadu_epi8(src, m, black_box(p)); + let r = unsafe { _mm_mask_loadu_epi8(src, m, black_box(p)) }; let e = &[ 42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, ]; - let e = _mm_loadu_epi8(e.as_ptr()); + let e = unsafe { _mm_loadu_epi8(e.as_ptr()) }; assert_eq_m128i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm_maskz_loadu_epi8() { + const fn test_mm_maskz_loadu_epi8() { let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm_maskz_loadu_epi8(m, black_box(p)); + let r = unsafe { _mm_maskz_loadu_epi8(m, black_box(p)) }; let e = &[0_i8, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16]; - let e = _mm_loadu_epi8(e.as_ptr()); + let e = unsafe { _mm_loadu_epi8(e.as_ptr()) }; assert_eq_m128i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - const unsafe fn test_mm_mask_storeu_epi8() { + const fn test_mm_mask_storeu_epi8() { let mut r = [42_i8; 16]; let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let a = _mm_loadu_epi8(a.as_ptr()); + let a = unsafe { _mm_loadu_epi8(a.as_ptr()) }; let m = 0b11101000_11001010; - _mm_mask_storeu_epi8(r.as_mut_ptr(), m, a); + unsafe { _mm_mask_storeu_epi8(r.as_mut_ptr(), m, a) }; let e = &[ 42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, ]; - let e = _mm_loadu_epi8(e.as_ptr()); - assert_eq_m128i(_mm_loadu_epi8(r.as_ptr()), e); + let e = unsafe { _mm_loadu_epi8(e.as_ptr()) }; + assert_eq_m128i(unsafe { _mm_loadu_epi8(r.as_ptr()) }, e); } #[simd_test(enable = "avx512bw")] @@ -20714,36 +20734,40 @@ mod tests { } #[simd_test(enable = "avx512bw")] - const unsafe fn test_store_mask64() { + const fn test_store_mask64() { let a: __mmask64 = 0b11111111_00000000_11111111_00000000_11111111_00000000_11111111_00000000; let mut r = 0; - _store_mask64(&mut r, a); + unsafe { + _store_mask64(&mut r, a); + } assert_eq!(r, a); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_store_mask32() { + const fn test_store_mask32() { let a: __mmask32 = 0b11111111_00000000_11111111_00000000; let mut r = 0; - _store_mask32(&mut r, a); + unsafe { + _store_mask32(&mut r, a); + } assert_eq!(r, a); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_load_mask64() { + const fn test_load_mask64() { let p: __mmask64 = 0b11111111_00000000_11111111_00000000_11111111_00000000_11111111_00000000; - let r = _load_mask64(&p); + let r = unsafe { _load_mask64(&p) }; let e: __mmask64 = 0b11111111_00000000_11111111_00000000_11111111_00000000_11111111_00000000; assert_eq!(r, e); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_load_mask32() { + const fn test_load_mask32() { let p: __mmask32 = 0b11111111_00000000_11111111_00000000; - let r = _load_mask32(&p); + let r = unsafe { _load_mask32(&p) }; let e: __mmask32 = 0b11111111_00000000_11111111_00000000; assert_eq!(r, e); } @@ -21163,21 +21187,21 @@ mod tests { } #[simd_test(enable = "avx512bw")] - const unsafe fn test_kortest_mask32_u8() { + const fn test_kortest_mask32_u8() { let a: __mmask32 = 0b0110100101101001_0110100101101001; let b: __mmask32 = 0b1011011010110110_1011011010110110; let mut all_ones: u8 = 0; - let r = _kortest_mask32_u8(a, b, &mut all_ones); + let r = unsafe { _kortest_mask32_u8(a, b, &mut all_ones) }; assert_eq!(r, 0); assert_eq!(all_ones, 1); } #[simd_test(enable = "avx512bw")] - const unsafe fn test_kortest_mask64_u8() { + const fn test_kortest_mask64_u8() { let a: __mmask64 = 0b0110100101101001_0110100101101001; let b: __mmask64 = 0b1011011010110110_1011011010110110; let mut all_ones: u8 = 0; - let r = _kortest_mask64_u8(a, b, &mut all_ones); + let r = unsafe { _kortest_mask64_u8(a, b, &mut all_ones) }; assert_eq!(r, 0); assert_eq!(all_ones, 0); } @@ -21299,11 +21323,11 @@ mod tests { } #[simd_test(enable = "avx512bw")] - const unsafe fn test_ktest_mask32_u8() { + const fn test_ktest_mask32_u8() { let a: __mmask32 = 0b0110100100111100_0110100100111100; let b: __mmask32 = 0b1001011011000011_1001011011000011; let mut and_not: u8 = 0; - let r = _ktest_mask32_u8(a, b, &mut and_not); + let r = unsafe { _ktest_mask32_u8(a, b, &mut and_not) }; assert_eq!(r, 1); assert_eq!(and_not, 0); } @@ -21325,11 +21349,11 @@ mod tests { } #[simd_test(enable = "avx512bw")] - const unsafe fn test_ktest_mask64_u8() { + const fn test_ktest_mask64_u8() { let a: __mmask64 = 0b0110100100111100_0110100100111100; let b: __mmask64 = 0b1001011011000011_1001011011000011; let mut and_not: u8 = 0; - let r = _ktest_mask64_u8(a, b, &mut and_not); + let r = unsafe { _ktest_mask64_u8(a, b, &mut and_not) }; assert_eq!(r, 1); assert_eq!(and_not, 0); } @@ -21951,32 +21975,38 @@ mod tests { } #[simd_test(enable = "avx512bw")] - unsafe fn test_mm512_mask_cvtsepi16_storeu_epi8() { + fn test_mm512_mask_cvtsepi16_storeu_epi8() { let a = _mm512_set1_epi16(i16::MAX); let mut r = _mm256_undefined_si256(); - _mm512_mask_cvtsepi16_storeu_epi8( - &mut r as *mut _ as *mut i8, - 0b11111111_11111111_11111111_11111111, - a, - ); + unsafe { + _mm512_mask_cvtsepi16_storeu_epi8( + &mut r as *mut _ as *mut i8, + 0b11111111_11111111_11111111_11111111, + a, + ); + } let e = _mm256_set1_epi8(i8::MAX); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - unsafe fn test_mm256_mask_cvtsepi16_storeu_epi8() { + fn test_mm256_mask_cvtsepi16_storeu_epi8() { let a = _mm256_set1_epi16(i16::MAX); let mut r = _mm_undefined_si128(); - _mm256_mask_cvtsepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + unsafe { + _mm256_mask_cvtsepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + } let e = _mm_set1_epi8(i8::MAX); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - unsafe fn test_mm_mask_cvtsepi16_storeu_epi8() { + fn test_mm_mask_cvtsepi16_storeu_epi8() { let a = _mm_set1_epi16(i16::MAX); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtsepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm_mask_cvtsepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } #[rustfmt::skip] let e = _mm_set_epi8( 0, 0, 0, 0, 0, 0, 0, 0, @@ -21986,63 +22016,75 @@ mod tests { } #[simd_test(enable = "avx512bw")] - unsafe fn test_mm512_mask_cvtepi16_storeu_epi8() { + fn test_mm512_mask_cvtepi16_storeu_epi8() { let a = _mm512_set1_epi16(8); let mut r = _mm256_undefined_si256(); - _mm512_mask_cvtepi16_storeu_epi8( - &mut r as *mut _ as *mut i8, - 0b11111111_11111111_11111111_11111111, - a, - ); + unsafe { + _mm512_mask_cvtepi16_storeu_epi8( + &mut r as *mut _ as *mut i8, + 0b11111111_11111111_11111111_11111111, + a, + ); + } let e = _mm256_set1_epi8(8); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - unsafe fn test_mm256_mask_cvtepi16_storeu_epi8() { + fn test_mm256_mask_cvtepi16_storeu_epi8() { let a = _mm256_set1_epi16(8); let mut r = _mm_undefined_si128(); - _mm256_mask_cvtepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + unsafe { + _mm256_mask_cvtepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + } let e = _mm_set1_epi8(8); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - unsafe fn test_mm_mask_cvtepi16_storeu_epi8() { + fn test_mm_mask_cvtepi16_storeu_epi8() { let a = _mm_set1_epi16(8); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm_mask_cvtepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512bw")] - unsafe fn test_mm512_mask_cvtusepi16_storeu_epi8() { + fn test_mm512_mask_cvtusepi16_storeu_epi8() { let a = _mm512_set1_epi16(i16::MAX); let mut r = _mm256_undefined_si256(); - _mm512_mask_cvtusepi16_storeu_epi8( - &mut r as *mut _ as *mut i8, - 0b11111111_11111111_11111111_11111111, - a, - ); + unsafe { + _mm512_mask_cvtusepi16_storeu_epi8( + &mut r as *mut _ as *mut i8, + 0b11111111_11111111_11111111_11111111, + a, + ); + } let e = _mm256_set1_epi8(u8::MAX as i8); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - unsafe fn test_mm256_mask_cvtusepi16_storeu_epi8() { + fn test_mm256_mask_cvtusepi16_storeu_epi8() { let a = _mm256_set1_epi16(i16::MAX); let mut r = _mm_undefined_si128(); - _mm256_mask_cvtusepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + unsafe { + _mm256_mask_cvtusepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + } let e = _mm_set1_epi8(u8::MAX as i8); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512bw,avx512vl")] - unsafe fn test_mm_mask_cvtusepi16_storeu_epi8() { + fn test_mm_mask_cvtusepi16_storeu_epi8() { let a = _mm_set1_epi16(i16::MAX); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtusepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm_mask_cvtusepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } #[rustfmt::skip] let e = _mm_set_epi8( 0, 0, 0, 0, diff --git a/library/stdarch/crates/core_arch/src/x86/avx512dq.rs b/library/stdarch/crates/core_arch/src/x86/avx512dq.rs index ebe75cd22d8e..9e1a4c0b2955 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512dq.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512dq.rs @@ -7401,27 +7401,25 @@ unsafe extern "C" { mod tests { use super::*; use crate::core_arch::assert_eq_const as assert_eq; + use crate::core_arch::x86::*; use stdarch_test::simd_test; - use crate::core_arch::x86::*; - use crate::mem::transmute; + const OPRND1_64: f64 = f64::from_bits(0x3333333333333333); + const OPRND2_64: f64 = f64::from_bits(0x5555555555555555); - const OPRND1_64: f64 = unsafe { transmute(0x3333333333333333_u64) }; - const OPRND2_64: f64 = unsafe { transmute(0x5555555555555555_u64) }; + const AND_64: f64 = f64::from_bits(0x1111111111111111); + const ANDN_64: f64 = f64::from_bits(0x4444444444444444); + const OR_64: f64 = f64::from_bits(0x7777777777777777); + const XOR_64: f64 = f64::from_bits(0x6666666666666666); - const AND_64: f64 = unsafe { transmute(0x1111111111111111_u64) }; - const ANDN_64: f64 = unsafe { transmute(0x4444444444444444_u64) }; - const OR_64: f64 = unsafe { transmute(0x7777777777777777_u64) }; - const XOR_64: f64 = unsafe { transmute(0x6666666666666666_u64) }; + const OPRND1_32: f32 = f32::from_bits(0x33333333); + const OPRND2_32: f32 = f32::from_bits(0x55555555); - const OPRND1_32: f32 = unsafe { transmute(0x33333333_u32) }; - const OPRND2_32: f32 = unsafe { transmute(0x55555555_u32) }; - - const AND_32: f32 = unsafe { transmute(0x11111111_u32) }; - const ANDN_32: f32 = unsafe { transmute(0x44444444_u32) }; - const OR_32: f32 = unsafe { transmute(0x77777777_u32) }; - const XOR_32: f32 = unsafe { transmute(0x66666666_u32) }; + const AND_32: f32 = f32::from_bits(0x11111111); + const ANDN_32: f32 = f32::from_bits(0x44444444); + const OR_32: f32 = f32::from_bits(0x77777777); + const XOR_32: f32 = f32::from_bits(0x66666666); #[simd_test(enable = "avx512dq,avx512vl")] const fn test_mm_mask_and_pd() { @@ -10023,11 +10021,11 @@ mod tests { } #[simd_test(enable = "avx512dq")] - const unsafe fn test_kortest_mask8_u8() { + const fn test_kortest_mask8_u8() { let a: __mmask8 = 0b01101001; let b: __mmask8 = 0b10110110; let mut all_ones: u8 = 0; - let r = _kortest_mask8_u8(a, b, &mut all_ones); + let r = unsafe { _kortest_mask8_u8(a, b, &mut all_ones) }; assert_eq!(r, 0); assert_eq!(all_ones, 1); } @@ -10049,7 +10047,7 @@ mod tests { } #[simd_test(enable = "avx512dq")] - const unsafe fn test_kshiftli_mask8() { + const fn test_kshiftli_mask8() { let a: __mmask8 = 0b01101001; let r = _kshiftli_mask8::<3>(a); let e: __mmask8 = 0b01001000; @@ -10089,11 +10087,11 @@ mod tests { } #[simd_test(enable = "avx512dq")] - const unsafe fn test_ktest_mask8_u8() { + const fn test_ktest_mask8_u8() { let a: __mmask8 = 0b01101001; let b: __mmask8 = 0b10010110; let mut and_not: u8 = 0; - let r = _ktest_mask8_u8(a, b, &mut and_not); + let r = unsafe { _ktest_mask8_u8(a, b, &mut and_not) }; assert_eq!(r, 1); assert_eq!(and_not, 0); } @@ -10115,11 +10113,11 @@ mod tests { } #[simd_test(enable = "avx512dq")] - const unsafe fn test_ktest_mask16_u8() { + const fn test_ktest_mask16_u8() { let a: __mmask16 = 0b0110100100111100; let b: __mmask16 = 0b1001011011000011; let mut and_not: u8 = 0; - let r = _ktest_mask16_u8(a, b, &mut and_not); + let r = unsafe { _ktest_mask16_u8(a, b, &mut and_not) }; assert_eq!(r, 1); assert_eq!(and_not, 0); } @@ -10141,18 +10139,20 @@ mod tests { } #[simd_test(enable = "avx512dq")] - const unsafe fn test_load_mask8() { + const fn test_load_mask8() { let a: __mmask8 = 0b01101001; - let r = _load_mask8(&a); + let r = unsafe { _load_mask8(&a) }; let e: __mmask8 = 0b01101001; assert_eq!(r, e); } #[simd_test(enable = "avx512dq")] - const unsafe fn test_store_mask8() { + const fn test_store_mask8() { let a: __mmask8 = 0b01101001; let mut r = 0; - _store_mask8(&mut r, a); + unsafe { + _store_mask8(&mut r, a); + } let e: __mmask8 = 0b01101001; assert_eq!(r, e); } diff --git a/library/stdarch/crates/core_arch/src/x86/avx512f.rs b/library/stdarch/crates/core_arch/src/x86/avx512f.rs index 76b753938383..3730496e1ec3 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512f.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512f.rs @@ -48062,9 +48062,7 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_ternarylogic_epi32() { - use core::intrinsics::simd::simd_xor; - + fn test_mm512_ternarylogic_epi32() { let a = _mm512_set4_epi32(0b100, 0b110, 0b001, 0b101); let b = _mm512_set4_epi32(0b010, 0b011, 0b001, 0b110); let c = _mm512_set4_epi32(0b001, 0b000, 0b001, 0b111); @@ -48077,7 +48075,7 @@ mod tests { let r = _mm512_ternarylogic_epi32::<0b10010110>(a, b, c); let e = _mm512_set4_epi32(0b111, 0b101, 0b001, 0b100); assert_eq_m512i(r, e); - assert_eq_m512i(r, simd_xor(simd_xor(a, b), c)); + assert_eq_m512i(r, _mm512_xor_si512(_mm512_xor_si512(a, b), c)); // Majority (2 or more bits set). let r = _mm512_ternarylogic_epi32::<0b1110_1000>(a, b, c); @@ -48110,9 +48108,7 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_ternarylogic_epi32() { - use core::intrinsics::simd::simd_xor; - + fn test_mm256_ternarylogic_epi32() { let _mm256_set4_epi32 = |a, b, c, d| _mm256_setr_epi32(a, b, c, d, a, b, c, d); let a = _mm256_set4_epi32(0b100, 0b110, 0b001, 0b101); @@ -48127,7 +48123,7 @@ mod tests { let r = _mm256_ternarylogic_epi32::<0b10010110>(a, b, c); let e = _mm256_set4_epi32(0b111, 0b101, 0b001, 0b100); assert_eq_m256i(r, e); - assert_eq_m256i(r, simd_xor(simd_xor(a, b), c)); + assert_eq_m256i(r, _mm256_xor_si256(_mm256_xor_si256(a, b), c)); // Majority (2 or more bits set). let r = _mm256_ternarylogic_epi32::<0b1110_1000>(a, b, c); @@ -48160,9 +48156,7 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_ternarylogic_epi32() { - use core::intrinsics::simd::simd_xor; - + fn test_mm_ternarylogic_epi32() { let a = _mm_setr_epi32(0b100, 0b110, 0b001, 0b101); let b = _mm_setr_epi32(0b010, 0b011, 0b001, 0b110); let c = _mm_setr_epi32(0b001, 0b000, 0b001, 0b111); @@ -48175,7 +48169,7 @@ mod tests { let r = _mm_ternarylogic_epi32::<0b10010110>(a, b, c); let e = _mm_setr_epi32(0b111, 0b101, 0b001, 0b100); assert_eq_m128i(r, e); - assert_eq_m128i(r, simd_xor(simd_xor(a, b), c)); + assert_eq_m128i(r, _mm_xor_si128(_mm_xor_si128(a, b), c)); // Majority (2 or more bits set). let r = _mm_ternarylogic_epi32::<0b1110_1000>(a, b, c); @@ -51447,20 +51441,20 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32gather_ps() { + fn test_mm512_i32gather_ps() { let arr: [f32; 256] = core::array::from_fn(|i| i as f32); // A multiplier of 4 is word-addressing #[rustfmt::skip] let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112, 120, 128, 136, 144, 152, 160, 168, 176); - let r = _mm512_i32gather_ps::<4>(index, arr.as_ptr()); + let r = unsafe { _mm512_i32gather_ps::<4>(index, arr.as_ptr()) }; #[rustfmt::skip] assert_eq_m512(r, _mm512_setr_ps(0., 16., 32., 48., 64., 80., 96., 112., 120., 128., 136., 144., 152., 160., 168., 176.)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32gather_ps() { + fn test_mm512_mask_i32gather_ps() { let arr: [f32; 256] = core::array::from_fn(|i| i as f32); let src = _mm512_set1_ps(2.); let mask = 0b10101010_10101010; @@ -51468,27 +51462,27 @@ mod tests { let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112, 120, 128, 136, 144, 152, 160, 168, 176); // A multiplier of 4 is word-addressing - let r = _mm512_mask_i32gather_ps::<4>(src, mask, index, arr.as_ptr()); + let r = unsafe { _mm512_mask_i32gather_ps::<4>(src, mask, index, arr.as_ptr()) }; #[rustfmt::skip] assert_eq_m512(r, _mm512_setr_ps(2., 16., 2., 48., 2., 80., 2., 112., 2., 128., 2., 144., 2., 160., 2., 176.)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32gather_epi32() { + fn test_mm512_i32gather_epi32() { let arr: [i32; 256] = core::array::from_fn(|i| i as i32); // A multiplier of 4 is word-addressing #[rustfmt::skip] let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112, 120, 128, 136, 144, 152, 160, 168, 176); - let r = _mm512_i32gather_epi32::<4>(index, arr.as_ptr()); + let r = unsafe { _mm512_i32gather_epi32::<4>(index, arr.as_ptr()) }; #[rustfmt::skip] assert_eq_m512i(r, _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112, 120, 128, 136, 144, 152, 160, 168, 176)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32gather_epi32() { + fn test_mm512_mask_i32gather_epi32() { let arr: [i32; 256] = core::array::from_fn(|i| i as i32); let src = _mm512_set1_epi32(2); let mask = 0b10101010_10101010; @@ -51496,7 +51490,7 @@ mod tests { 0, 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240, ); // A multiplier of 4 is word-addressing - let r = _mm512_mask_i32gather_epi32::<4>(src, mask, index, arr.as_ptr()); + let r = unsafe { _mm512_mask_i32gather_epi32::<4>(src, mask, index, arr.as_ptr()) }; assert_eq_m512i( r, _mm512_setr_epi32(2, 16, 2, 48, 2, 80, 2, 112, 2, 144, 2, 176, 2, 208, 2, 240), @@ -51504,7 +51498,7 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32scatter_ps() { + fn test_mm512_i32scatter_ps() { let mut arr = [0f32; 256]; #[rustfmt::skip] let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112, @@ -51513,7 +51507,9 @@ mod tests { 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16., ); // A multiplier of 4 is word-addressing - _mm512_i32scatter_ps::<4>(arr.as_mut_ptr(), index, src); + unsafe { + _mm512_i32scatter_ps::<4>(arr.as_mut_ptr(), index, src); + } let mut expected = [0f32; 256]; for i in 0..16 { expected[i * 16] = (i + 1) as f32; @@ -51522,7 +51518,7 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32scatter_ps() { + fn test_mm512_mask_i32scatter_ps() { let mut arr = [0f32; 256]; let mask = 0b10101010_10101010; #[rustfmt::skip] @@ -51532,7 +51528,9 @@ mod tests { 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16., ); // A multiplier of 4 is word-addressing - _mm512_mask_i32scatter_ps::<4>(arr.as_mut_ptr(), mask, index, src); + unsafe { + _mm512_mask_i32scatter_ps::<4>(arr.as_mut_ptr(), mask, index, src); + } let mut expected = [0f32; 256]; for i in 0..8 { expected[i * 32 + 16] = 2. * (i + 1) as f32; @@ -51541,7 +51539,7 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32scatter_epi32() { + fn test_mm512_i32scatter_epi32() { let mut arr = [0i32; 256]; #[rustfmt::skip] @@ -51549,7 +51547,9 @@ mod tests { 128, 144, 160, 176, 192, 208, 224, 240); let src = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); // A multiplier of 4 is word-addressing - _mm512_i32scatter_epi32::<4>(arr.as_mut_ptr(), index, src); + unsafe { + _mm512_i32scatter_epi32::<4>(arr.as_mut_ptr(), index, src); + } let mut expected = [0i32; 256]; for i in 0..16 { expected[i * 16] = (i + 1) as i32; @@ -51558,7 +51558,7 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32scatter_epi32() { + fn test_mm512_mask_i32scatter_epi32() { let mut arr = [0i32; 256]; let mask = 0b10101010_10101010; #[rustfmt::skip] @@ -51566,7 +51566,9 @@ mod tests { 128, 144, 160, 176, 192, 208, 224, 240); let src = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); // A multiplier of 4 is word-addressing - _mm512_mask_i32scatter_epi32::<4>(arr.as_mut_ptr(), mask, index, src); + unsafe { + _mm512_mask_i32scatter_epi32::<4>(arr.as_mut_ptr(), mask, index, src); + } let mut expected = [0i32; 256]; for i in 0..8 { expected[i * 32 + 16] = 2 * (i + 1) as i32; @@ -52850,29 +52852,31 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_loadu_pd() { + const fn test_mm512_loadu_pd() { let a = &[4., 3., 2., 5., 8., 9., 64., 50.]; let p = a.as_ptr(); - let r = _mm512_loadu_pd(black_box(p)); + let r = unsafe { _mm512_loadu_pd(black_box(p)) }; let e = _mm512_setr_pd(4., 3., 2., 5., 8., 9., 64., 50.); assert_eq_m512d(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_storeu_pd() { + const fn test_mm512_storeu_pd() { let a = _mm512_set1_pd(9.); let mut r = _mm512_undefined_pd(); - _mm512_storeu_pd(&mut r as *mut _ as *mut f64, a); + unsafe { + _mm512_storeu_pd(&mut r as *mut _ as *mut f64, a); + } assert_eq_m512d(r, a); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_loadu_ps() { + const fn test_mm512_loadu_ps() { let a = &[ 4., 3., 2., 5., 8., 9., 64., 50., -4., -3., -2., -5., -8., -9., -64., -50., ]; let p = a.as_ptr(); - let r = _mm512_loadu_ps(black_box(p)); + let r = unsafe { _mm512_loadu_ps(black_box(p)) }; let e = _mm512_setr_ps( 4., 3., 2., 5., 8., 9., 64., 50., -4., -3., -2., -5., -8., -9., -64., -50., ); @@ -52880,36 +52884,38 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_storeu_ps() { + const fn test_mm512_storeu_ps() { let a = _mm512_set1_ps(9.); let mut r = _mm512_undefined_ps(); - _mm512_storeu_ps(&mut r as *mut _ as *mut f32, a); + unsafe { + _mm512_storeu_ps(&mut r as *mut _ as *mut f32, a); + } assert_eq_m512(r, a); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_loadu_epi32() { + const fn test_mm512_mask_loadu_epi32() { let src = _mm512_set1_epi32(42); let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_mask_loadu_epi32(src, m, black_box(p)); + let r = unsafe { _mm512_mask_loadu_epi32(src, m, black_box(p)) }; let e = _mm512_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_maskz_loadu_epi32() { + const fn test_mm512_maskz_loadu_epi32() { let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_maskz_loadu_epi32(m, black_box(p)); + let r = unsafe { _mm512_maskz_loadu_epi32(m, black_box(p)) }; let e = _mm512_setr_epi32(0, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_load_epi32() { + const fn test_mm512_mask_load_epi32() { #[repr(align(64))] struct Align { data: [i32; 16], // 64 bytes @@ -52920,13 +52926,13 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_mask_load_epi32(src, m, black_box(p)); + let r = unsafe { _mm512_mask_load_epi32(src, m, black_box(p)) }; let e = _mm512_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_maskz_load_epi32() { + const fn test_mm512_maskz_load_epi32() { #[repr(align(64))] struct Align { data: [i32; 16], // 64 bytes @@ -52936,23 +52942,25 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_maskz_load_epi32(m, black_box(p)); + let r = unsafe { _mm512_maskz_load_epi32(m, black_box(p)) }; let e = _mm512_setr_epi32(0, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_storeu_epi32() { + const fn test_mm512_mask_storeu_epi32() { let mut r = [42_i32; 16]; let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); let m = 0b11101000_11001010; - _mm512_mask_storeu_epi32(r.as_mut_ptr(), m, a); + unsafe { + _mm512_mask_storeu_epi32(r.as_mut_ptr(), m, a); + } let e = _mm512_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16); - assert_eq_m512i(_mm512_loadu_epi32(r.as_ptr()), e); + assert_eq_m512i(unsafe { _mm512_loadu_epi32(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_store_epi32() { + const fn test_mm512_mask_store_epi32() { #[repr(align(64))] struct Align { data: [i32; 16], @@ -52960,34 +52968,36 @@ mod tests { let mut r = Align { data: [42; 16] }; let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); let m = 0b11101000_11001010; - _mm512_mask_store_epi32(r.data.as_mut_ptr(), m, a); + unsafe { + _mm512_mask_store_epi32(r.data.as_mut_ptr(), m, a); + } let e = _mm512_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16); - assert_eq_m512i(_mm512_load_epi32(r.data.as_ptr()), e); + assert_eq_m512i(unsafe { _mm512_load_epi32(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_loadu_epi64() { + const fn test_mm512_mask_loadu_epi64() { let src = _mm512_set1_epi64(42); let a = &[1_i64, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11001010; - let r = _mm512_mask_loadu_epi64(src, m, black_box(p)); + let r = unsafe { _mm512_mask_loadu_epi64(src, m, black_box(p)) }; let e = _mm512_setr_epi64(42, 2, 42, 4, 42, 42, 7, 8); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_maskz_loadu_epi64() { + const fn test_mm512_maskz_loadu_epi64() { let a = &[1_i64, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11001010; - let r = _mm512_maskz_loadu_epi64(m, black_box(p)); + let r = unsafe { _mm512_maskz_loadu_epi64(m, black_box(p)) }; let e = _mm512_setr_epi64(0, 2, 0, 4, 0, 0, 7, 8); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_load_epi64() { + const fn test_mm512_mask_load_epi64() { #[repr(align(64))] struct Align { data: [i64; 8], // 64 bytes @@ -52998,13 +53008,13 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11001010; - let r = _mm512_mask_load_epi64(src, m, black_box(p)); + let r = unsafe { _mm512_mask_load_epi64(src, m, black_box(p)) }; let e = _mm512_setr_epi64(42, 2, 42, 4, 42, 42, 7, 8); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_maskz_load_epi64() { + const fn test_mm512_maskz_load_epi64() { #[repr(align(64))] struct Align { data: [i64; 8], // 64 bytes @@ -53014,23 +53024,25 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11001010; - let r = _mm512_maskz_load_epi64(m, black_box(p)); + let r = unsafe { _mm512_maskz_load_epi64(m, black_box(p)) }; let e = _mm512_setr_epi64(0, 2, 0, 4, 0, 0, 7, 8); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_storeu_epi64() { + const fn test_mm512_mask_storeu_epi64() { let mut r = [42_i64; 8]; let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8); let m = 0b11001010; - _mm512_mask_storeu_epi64(r.as_mut_ptr(), m, a); + unsafe { + _mm512_mask_storeu_epi64(r.as_mut_ptr(), m, a); + } let e = _mm512_setr_epi64(42, 2, 42, 4, 42, 42, 7, 8); - assert_eq_m512i(_mm512_loadu_epi64(r.as_ptr()), e); + assert_eq_m512i(unsafe { _mm512_loadu_epi64(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_store_epi64() { + const fn test_mm512_mask_store_epi64() { #[repr(align(64))] struct Align { data: [i64; 8], @@ -53039,13 +53051,15 @@ mod tests { let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8); let m = 0b11001010; let p = r.data.as_mut_ptr(); - _mm512_mask_store_epi64(p, m, a); + unsafe { + _mm512_mask_store_epi64(p, m, a); + } let e = _mm512_setr_epi64(42, 2, 42, 4, 42, 42, 7, 8); - assert_eq_m512i(_mm512_load_epi64(r.data.as_ptr()), e); + assert_eq_m512i(unsafe { _mm512_load_epi64(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_loadu_ps() { + const fn test_mm512_mask_loadu_ps() { let src = _mm512_set1_ps(42.0); let a = &[ 1.0_f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, @@ -53053,7 +53067,7 @@ mod tests { ]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_mask_loadu_ps(src, m, black_box(p)); + let r = unsafe { _mm512_mask_loadu_ps(src, m, black_box(p)) }; let e = _mm512_setr_ps( 42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0, 42.0, 42.0, 42.0, 12.0, 42.0, 14.0, 15.0, 16.0, @@ -53062,14 +53076,14 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_maskz_loadu_ps() { + const fn test_mm512_maskz_loadu_ps() { let a = &[ 1.0_f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, ]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_maskz_loadu_ps(m, black_box(p)); + let r = unsafe { _mm512_maskz_loadu_ps(m, black_box(p)) }; let e = _mm512_setr_ps( 0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0, 0.0, 0.0, 0.0, 12.0, 0.0, 14.0, 15.0, 16.0, ); @@ -53077,7 +53091,7 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_load_ps() { + const fn test_mm512_mask_load_ps() { #[repr(align(64))] struct Align { data: [f32; 16], // 64 bytes @@ -53091,7 +53105,7 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_mask_load_ps(src, m, black_box(p)); + let r = unsafe { _mm512_mask_load_ps(src, m, black_box(p)) }; let e = _mm512_setr_ps( 42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0, 42.0, 42.0, 42.0, 12.0, 42.0, 14.0, 15.0, 16.0, @@ -53100,7 +53114,7 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_maskz_load_ps() { + const fn test_mm512_maskz_load_ps() { #[repr(align(64))] struct Align { data: [f32; 16], // 64 bytes @@ -53113,7 +53127,7 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_maskz_load_ps(m, black_box(p)); + let r = unsafe { _mm512_maskz_load_ps(m, black_box(p)) }; let e = _mm512_setr_ps( 0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0, 0.0, 0.0, 0.0, 12.0, 0.0, 14.0, 15.0, 16.0, ); @@ -53121,22 +53135,24 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_storeu_ps() { + const fn test_mm512_mask_storeu_ps() { let mut r = [42_f32; 16]; let a = _mm512_setr_ps( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, ); let m = 0b11101000_11001010; - _mm512_mask_storeu_ps(r.as_mut_ptr(), m, a); + unsafe { + _mm512_mask_storeu_ps(r.as_mut_ptr(), m, a); + } let e = _mm512_setr_ps( 42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0, 42.0, 42.0, 42.0, 12.0, 42.0, 14.0, 15.0, 16.0, ); - assert_eq_m512(_mm512_loadu_ps(r.as_ptr()), e); + assert_eq_m512(unsafe { _mm512_loadu_ps(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_store_ps() { + const fn test_mm512_mask_store_ps() { #[repr(align(64))] struct Align { data: [f32; 16], @@ -53146,37 +53162,39 @@ mod tests { 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, ); let m = 0b11101000_11001010; - _mm512_mask_store_ps(r.data.as_mut_ptr(), m, a); + unsafe { + _mm512_mask_store_ps(r.data.as_mut_ptr(), m, a); + } let e = _mm512_setr_ps( 42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0, 42.0, 42.0, 42.0, 12.0, 42.0, 14.0, 15.0, 16.0, ); - assert_eq_m512(_mm512_load_ps(r.data.as_ptr()), e); + assert_eq_m512(unsafe { _mm512_load_ps(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_loadu_pd() { + const fn test_mm512_mask_loadu_pd() { let src = _mm512_set1_pd(42.0); let a = &[1.0_f64, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0]; let p = a.as_ptr(); let m = 0b11001010; - let r = _mm512_mask_loadu_pd(src, m, black_box(p)); + let r = unsafe { _mm512_mask_loadu_pd(src, m, black_box(p)) }; let e = _mm512_setr_pd(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0); assert_eq_m512d(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_maskz_loadu_pd() { + const fn test_mm512_maskz_loadu_pd() { let a = &[1.0_f64, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0]; let p = a.as_ptr(); let m = 0b11001010; - let r = _mm512_maskz_loadu_pd(m, black_box(p)); + let r = unsafe { _mm512_maskz_loadu_pd(m, black_box(p)) }; let e = _mm512_setr_pd(0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0); assert_eq_m512d(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_load_pd() { + const fn test_mm512_mask_load_pd() { #[repr(align(64))] struct Align { data: [f64; 8], // 64 bytes @@ -53187,13 +53205,13 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11001010; - let r = _mm512_mask_load_pd(src, m, black_box(p)); + let r = unsafe { _mm512_mask_load_pd(src, m, black_box(p)) }; let e = _mm512_setr_pd(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0); assert_eq_m512d(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_maskz_load_pd() { + const fn test_mm512_maskz_load_pd() { #[repr(align(64))] struct Align { data: [f64; 8], // 64 bytes @@ -53203,23 +53221,25 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11001010; - let r = _mm512_maskz_load_pd(m, black_box(p)); + let r = unsafe { _mm512_maskz_load_pd(m, black_box(p)) }; let e = _mm512_setr_pd(0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0); assert_eq_m512d(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_storeu_pd() { + const fn test_mm512_mask_storeu_pd() { let mut r = [42_f64; 8]; let a = _mm512_setr_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0); let m = 0b11001010; - _mm512_mask_storeu_pd(r.as_mut_ptr(), m, a); + unsafe { + _mm512_mask_storeu_pd(r.as_mut_ptr(), m, a); + } let e = _mm512_setr_pd(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0); - assert_eq_m512d(_mm512_loadu_pd(r.as_ptr()), e); + assert_eq_m512d(unsafe { _mm512_loadu_pd(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_mask_store_pd() { + const fn test_mm512_mask_store_pd() { #[repr(align(64))] struct Align { data: [f64; 8], @@ -53227,34 +53247,36 @@ mod tests { let mut r = Align { data: [42.0; 8] }; let a = _mm512_setr_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0); let m = 0b11001010; - _mm512_mask_store_pd(r.data.as_mut_ptr(), m, a); + unsafe { + _mm512_mask_store_pd(r.data.as_mut_ptr(), m, a); + } let e = _mm512_setr_pd(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0); - assert_eq_m512d(_mm512_load_pd(r.data.as_ptr()), e); + assert_eq_m512d(unsafe { _mm512_load_pd(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_loadu_epi32() { + const fn test_mm256_mask_loadu_epi32() { let src = _mm256_set1_epi32(42); let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11001010; - let r = _mm256_mask_loadu_epi32(src, m, black_box(p)); + let r = unsafe { _mm256_mask_loadu_epi32(src, m, black_box(p)) }; let e = _mm256_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_maskz_loadu_epi32() { + const fn test_mm256_maskz_loadu_epi32() { let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11001010; - let r = _mm256_maskz_loadu_epi32(m, black_box(p)); + let r = unsafe { _mm256_maskz_loadu_epi32(m, black_box(p)) }; let e = _mm256_setr_epi32(0, 2, 0, 4, 0, 0, 7, 8); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_load_epi32() { + const fn test_mm256_mask_load_epi32() { #[repr(align(32))] struct Align { data: [i32; 8], // 32 bytes @@ -53265,13 +53287,13 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11001010; - let r = _mm256_mask_load_epi32(src, m, black_box(p)); + let r = unsafe { _mm256_mask_load_epi32(src, m, black_box(p)) }; let e = _mm256_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_maskz_load_epi32() { + const fn test_mm256_maskz_load_epi32() { #[repr(align(32))] struct Align { data: [i32; 8], // 32 bytes @@ -53281,23 +53303,25 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11001010; - let r = _mm256_maskz_load_epi32(m, black_box(p)); + let r = unsafe { _mm256_maskz_load_epi32(m, black_box(p)) }; let e = _mm256_setr_epi32(0, 2, 0, 4, 0, 0, 7, 8); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_storeu_epi32() { + const fn test_mm256_mask_storeu_epi32() { let mut r = [42_i32; 8]; let a = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8); let m = 0b11001010; - _mm256_mask_storeu_epi32(r.as_mut_ptr(), m, a); + unsafe { + _mm256_mask_storeu_epi32(r.as_mut_ptr(), m, a); + } let e = _mm256_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8); - assert_eq_m256i(_mm256_loadu_epi32(r.as_ptr()), e); + assert_eq_m256i(unsafe { _mm256_loadu_epi32(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_store_epi32() { + const fn test_mm256_mask_store_epi32() { #[repr(align(64))] struct Align { data: [i32; 8], @@ -53305,34 +53329,36 @@ mod tests { let mut r = Align { data: [42; 8] }; let a = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8); let m = 0b11001010; - _mm256_mask_store_epi32(r.data.as_mut_ptr(), m, a); + unsafe { + _mm256_mask_store_epi32(r.data.as_mut_ptr(), m, a); + } let e = _mm256_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8); - assert_eq_m256i(_mm256_load_epi32(r.data.as_ptr()), e); + assert_eq_m256i(unsafe { _mm256_load_epi32(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_loadu_epi64() { + const fn test_mm256_mask_loadu_epi64() { let src = _mm256_set1_epi64x(42); let a = &[1_i64, 2, 3, 4]; let p = a.as_ptr(); let m = 0b1010; - let r = _mm256_mask_loadu_epi64(src, m, black_box(p)); + let r = unsafe { _mm256_mask_loadu_epi64(src, m, black_box(p)) }; let e = _mm256_setr_epi64x(42, 2, 42, 4); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_maskz_loadu_epi64() { + const fn test_mm256_maskz_loadu_epi64() { let a = &[1_i64, 2, 3, 4]; let p = a.as_ptr(); let m = 0b1010; - let r = _mm256_maskz_loadu_epi64(m, black_box(p)); + let r = unsafe { _mm256_maskz_loadu_epi64(m, black_box(p)) }; let e = _mm256_setr_epi64x(0, 2, 0, 4); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_load_epi64() { + const fn test_mm256_mask_load_epi64() { #[repr(align(32))] struct Align { data: [i64; 4], // 32 bytes @@ -53343,13 +53369,13 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b1010; - let r = _mm256_mask_load_epi64(src, m, black_box(p)); + let r = unsafe { _mm256_mask_load_epi64(src, m, black_box(p)) }; let e = _mm256_setr_epi64x(42, 2, 42, 4); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_maskz_load_epi64() { + const fn test_mm256_maskz_load_epi64() { #[repr(align(32))] struct Align { data: [i64; 4], // 32 bytes @@ -53359,23 +53385,25 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b1010; - let r = _mm256_maskz_load_epi64(m, black_box(p)); + let r = unsafe { _mm256_maskz_load_epi64(m, black_box(p)) }; let e = _mm256_setr_epi64x(0, 2, 0, 4); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_storeu_epi64() { + const fn test_mm256_mask_storeu_epi64() { let mut r = [42_i64; 4]; let a = _mm256_setr_epi64x(1, 2, 3, 4); let m = 0b1010; - _mm256_mask_storeu_epi64(r.as_mut_ptr(), m, a); + unsafe { + _mm256_mask_storeu_epi64(r.as_mut_ptr(), m, a); + } let e = _mm256_setr_epi64x(42, 2, 42, 4); - assert_eq_m256i(_mm256_loadu_epi64(r.as_ptr()), e); + assert_eq_m256i(unsafe { _mm256_loadu_epi64(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_store_epi64() { + const fn test_mm256_mask_store_epi64() { #[repr(align(32))] struct Align { data: [i64; 4], @@ -53383,34 +53411,36 @@ mod tests { let mut r = Align { data: [42; 4] }; let a = _mm256_setr_epi64x(1, 2, 3, 4); let m = 0b1010; - _mm256_mask_store_epi64(r.data.as_mut_ptr(), m, a); + unsafe { + _mm256_mask_store_epi64(r.data.as_mut_ptr(), m, a); + } let e = _mm256_setr_epi64x(42, 2, 42, 4); - assert_eq_m256i(_mm256_load_epi64(r.data.as_ptr()), e); + assert_eq_m256i(unsafe { _mm256_load_epi64(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_loadu_ps() { + const fn test_mm256_mask_loadu_ps() { let src = _mm256_set1_ps(42.0); let a = &[1.0_f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0]; let p = a.as_ptr(); let m = 0b11001010; - let r = _mm256_mask_loadu_ps(src, m, black_box(p)); + let r = unsafe { _mm256_mask_loadu_ps(src, m, black_box(p)) }; let e = _mm256_setr_ps(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0); assert_eq_m256(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_maskz_loadu_ps() { + const fn test_mm256_maskz_loadu_ps() { let a = &[1.0_f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0]; let p = a.as_ptr(); let m = 0b11001010; - let r = _mm256_maskz_loadu_ps(m, black_box(p)); + let r = unsafe { _mm256_maskz_loadu_ps(m, black_box(p)) }; let e = _mm256_setr_ps(0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0); assert_eq_m256(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_load_ps() { + const fn test_mm256_mask_load_ps() { #[repr(align(32))] struct Align { data: [f32; 8], // 32 bytes @@ -53421,13 +53451,13 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11001010; - let r = _mm256_mask_load_ps(src, m, black_box(p)); + let r = unsafe { _mm256_mask_load_ps(src, m, black_box(p)) }; let e = _mm256_setr_ps(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0); assert_eq_m256(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_maskz_load_ps() { + const fn test_mm256_maskz_load_ps() { #[repr(align(32))] struct Align { data: [f32; 8], // 32 bytes @@ -53437,23 +53467,25 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b11001010; - let r = _mm256_maskz_load_ps(m, black_box(p)); + let r = unsafe { _mm256_maskz_load_ps(m, black_box(p)) }; let e = _mm256_setr_ps(0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0); assert_eq_m256(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_storeu_ps() { + const fn test_mm256_mask_storeu_ps() { let mut r = [42_f32; 8]; let a = _mm256_setr_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0); let m = 0b11001010; - _mm256_mask_storeu_ps(r.as_mut_ptr(), m, a); + unsafe { + _mm256_mask_storeu_ps(r.as_mut_ptr(), m, a); + } let e = _mm256_setr_ps(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0); - assert_eq_m256(_mm256_loadu_ps(r.as_ptr()), e); + assert_eq_m256(unsafe { _mm256_loadu_ps(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_store_ps() { + const fn test_mm256_mask_store_ps() { #[repr(align(32))] struct Align { data: [f32; 8], @@ -53461,34 +53493,36 @@ mod tests { let mut r = Align { data: [42.0; 8] }; let a = _mm256_setr_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0); let m = 0b11001010; - _mm256_mask_store_ps(r.data.as_mut_ptr(), m, a); + unsafe { + _mm256_mask_store_ps(r.data.as_mut_ptr(), m, a); + } let e = _mm256_setr_ps(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0); - assert_eq_m256(_mm256_load_ps(r.data.as_ptr()), e); + assert_eq_m256(unsafe { _mm256_load_ps(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_loadu_pd() { + const fn test_mm256_mask_loadu_pd() { let src = _mm256_set1_pd(42.0); let a = &[1.0_f64, 2.0, 3.0, 4.0]; let p = a.as_ptr(); let m = 0b1010; - let r = _mm256_mask_loadu_pd(src, m, black_box(p)); + let r = unsafe { _mm256_mask_loadu_pd(src, m, black_box(p)) }; let e = _mm256_setr_pd(42.0, 2.0, 42.0, 4.0); assert_eq_m256d(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_maskz_loadu_pd() { + const fn test_mm256_maskz_loadu_pd() { let a = &[1.0_f64, 2.0, 3.0, 4.0]; let p = a.as_ptr(); let m = 0b1010; - let r = _mm256_maskz_loadu_pd(m, black_box(p)); + let r = unsafe { _mm256_maskz_loadu_pd(m, black_box(p)) }; let e = _mm256_setr_pd(0.0, 2.0, 0.0, 4.0); assert_eq_m256d(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_load_pd() { + const fn test_mm256_mask_load_pd() { #[repr(align(32))] struct Align { data: [f64; 4], // 32 bytes @@ -53499,13 +53533,13 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b1010; - let r = _mm256_mask_load_pd(src, m, black_box(p)); + let r = unsafe { _mm256_mask_load_pd(src, m, black_box(p)) }; let e = _mm256_setr_pd(42.0, 2.0, 42.0, 4.0); assert_eq_m256d(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_maskz_load_pd() { + const fn test_mm256_maskz_load_pd() { #[repr(align(32))] struct Align { data: [f64; 4], // 32 bytes @@ -53515,23 +53549,25 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b1010; - let r = _mm256_maskz_load_pd(m, black_box(p)); + let r = unsafe { _mm256_maskz_load_pd(m, black_box(p)) }; let e = _mm256_setr_pd(0.0, 2.0, 0.0, 4.0); assert_eq_m256d(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_storeu_pd() { + const fn test_mm256_mask_storeu_pd() { let mut r = [42_f64; 4]; let a = _mm256_setr_pd(1.0, 2.0, 3.0, 4.0); let m = 0b1010; - _mm256_mask_storeu_pd(r.as_mut_ptr(), m, a); + unsafe { + _mm256_mask_storeu_pd(r.as_mut_ptr(), m, a); + } let e = _mm256_setr_pd(42.0, 2.0, 42.0, 4.0); - assert_eq_m256d(_mm256_loadu_pd(r.as_ptr()), e); + assert_eq_m256d(unsafe { _mm256_loadu_pd(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_mask_store_pd() { + const fn test_mm256_mask_store_pd() { #[repr(align(32))] struct Align { data: [f64; 4], @@ -53539,34 +53575,36 @@ mod tests { let mut r = Align { data: [42.0; 4] }; let a = _mm256_setr_pd(1.0, 2.0, 3.0, 4.0); let m = 0b1010; - _mm256_mask_store_pd(r.data.as_mut_ptr(), m, a); + unsafe { + _mm256_mask_store_pd(r.data.as_mut_ptr(), m, a); + } let e = _mm256_setr_pd(42.0, 2.0, 42.0, 4.0); - assert_eq_m256d(_mm256_load_pd(r.data.as_ptr()), e); + assert_eq_m256d(unsafe { _mm256_load_pd(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_loadu_epi32() { + const fn test_mm_mask_loadu_epi32() { let src = _mm_set1_epi32(42); let a = &[1_i32, 2, 3, 4]; let p = a.as_ptr(); let m = 0b1010; - let r = _mm_mask_loadu_epi32(src, m, black_box(p)); + let r = unsafe { _mm_mask_loadu_epi32(src, m, black_box(p)) }; let e = _mm_setr_epi32(42, 2, 42, 4); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_maskz_loadu_epi32() { + const fn test_mm_maskz_loadu_epi32() { let a = &[1_i32, 2, 3, 4]; let p = a.as_ptr(); let m = 0b1010; - let r = _mm_maskz_loadu_epi32(m, black_box(p)); + let r = unsafe { _mm_maskz_loadu_epi32(m, black_box(p)) }; let e = _mm_setr_epi32(0, 2, 0, 4); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_load_epi32() { + const fn test_mm_mask_load_epi32() { #[repr(align(16))] struct Align { data: [i32; 4], // 32 bytes @@ -53577,13 +53615,13 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b1010; - let r = _mm_mask_load_epi32(src, m, black_box(p)); + let r = unsafe { _mm_mask_load_epi32(src, m, black_box(p)) }; let e = _mm_setr_epi32(42, 2, 42, 4); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_maskz_load_epi32() { + const fn test_mm_maskz_load_epi32() { #[repr(align(16))] struct Align { data: [i32; 4], // 16 bytes @@ -53593,23 +53631,25 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b1010; - let r = _mm_maskz_load_epi32(m, black_box(p)); + let r = unsafe { _mm_maskz_load_epi32(m, black_box(p)) }; let e = _mm_setr_epi32(0, 2, 0, 4); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_storeu_epi32() { + const fn test_mm_mask_storeu_epi32() { let mut r = [42_i32; 4]; let a = _mm_setr_epi32(1, 2, 3, 4); let m = 0b1010; - _mm_mask_storeu_epi32(r.as_mut_ptr(), m, a); + unsafe { + _mm_mask_storeu_epi32(r.as_mut_ptr(), m, a); + } let e = _mm_setr_epi32(42, 2, 42, 4); - assert_eq_m128i(_mm_loadu_epi32(r.as_ptr()), e); + assert_eq_m128i(unsafe { _mm_loadu_epi32(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_store_epi32() { + const fn test_mm_mask_store_epi32() { #[repr(align(16))] struct Align { data: [i32; 4], // 16 bytes @@ -53617,34 +53657,36 @@ mod tests { let mut r = Align { data: [42; 4] }; let a = _mm_setr_epi32(1, 2, 3, 4); let m = 0b1010; - _mm_mask_store_epi32(r.data.as_mut_ptr(), m, a); + unsafe { + _mm_mask_store_epi32(r.data.as_mut_ptr(), m, a); + } let e = _mm_setr_epi32(42, 2, 42, 4); - assert_eq_m128i(_mm_load_epi32(r.data.as_ptr()), e); + assert_eq_m128i(unsafe { _mm_load_epi32(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_loadu_epi64() { + const fn test_mm_mask_loadu_epi64() { let src = _mm_set1_epi64x(42); let a = &[1_i64, 2]; let p = a.as_ptr(); let m = 0b10; - let r = _mm_mask_loadu_epi64(src, m, black_box(p)); + let r = unsafe { _mm_mask_loadu_epi64(src, m, black_box(p)) }; let e = _mm_setr_epi64x(42, 2); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_maskz_loadu_epi64() { + const fn test_mm_maskz_loadu_epi64() { let a = &[1_i64, 2]; let p = a.as_ptr(); let m = 0b10; - let r = _mm_maskz_loadu_epi64(m, black_box(p)); + let r = unsafe { _mm_maskz_loadu_epi64(m, black_box(p)) }; let e = _mm_setr_epi64x(0, 2); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_load_epi64() { + const fn test_mm_mask_load_epi64() { #[repr(align(16))] struct Align { data: [i64; 2], // 16 bytes @@ -53653,13 +53695,13 @@ mod tests { let a = Align { data: [1_i64, 2] }; let p = a.data.as_ptr(); let m = 0b10; - let r = _mm_mask_load_epi64(src, m, black_box(p)); + let r = unsafe { _mm_mask_load_epi64(src, m, black_box(p)) }; let e = _mm_setr_epi64x(42, 2); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_maskz_load_epi64() { + const fn test_mm_maskz_load_epi64() { #[repr(align(16))] struct Align { data: [i64; 2], // 16 bytes @@ -53667,23 +53709,25 @@ mod tests { let a = Align { data: [1_i64, 2] }; let p = a.data.as_ptr(); let m = 0b10; - let r = _mm_maskz_load_epi64(m, black_box(p)); + let r = unsafe { _mm_maskz_load_epi64(m, black_box(p)) }; let e = _mm_setr_epi64x(0, 2); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_storeu_epi64() { + const fn test_mm_mask_storeu_epi64() { let mut r = [42_i64; 2]; let a = _mm_setr_epi64x(1, 2); let m = 0b10; - _mm_mask_storeu_epi64(r.as_mut_ptr(), m, a); + unsafe { + _mm_mask_storeu_epi64(r.as_mut_ptr(), m, a); + } let e = _mm_setr_epi64x(42, 2); - assert_eq_m128i(_mm_loadu_epi64(r.as_ptr()), e); + assert_eq_m128i(unsafe { _mm_loadu_epi64(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_store_epi64() { + const fn test_mm_mask_store_epi64() { #[repr(align(16))] struct Align { data: [i64; 2], // 16 bytes @@ -53691,34 +53735,36 @@ mod tests { let mut r = Align { data: [42; 2] }; let a = _mm_setr_epi64x(1, 2); let m = 0b10; - _mm_mask_store_epi64(r.data.as_mut_ptr(), m, a); + unsafe { + _mm_mask_store_epi64(r.data.as_mut_ptr(), m, a); + } let e = _mm_setr_epi64x(42, 2); - assert_eq_m128i(_mm_load_epi64(r.data.as_ptr()), e); + assert_eq_m128i(unsafe { _mm_load_epi64(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_loadu_ps() { + const fn test_mm_mask_loadu_ps() { let src = _mm_set1_ps(42.0); let a = &[1.0_f32, 2.0, 3.0, 4.0]; let p = a.as_ptr(); let m = 0b1010; - let r = _mm_mask_loadu_ps(src, m, black_box(p)); + let r = unsafe { _mm_mask_loadu_ps(src, m, black_box(p)) }; let e = _mm_setr_ps(42.0, 2.0, 42.0, 4.0); assert_eq_m128(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_maskz_loadu_ps() { + const fn test_mm_maskz_loadu_ps() { let a = &[1.0_f32, 2.0, 3.0, 4.0]; let p = a.as_ptr(); let m = 0b1010; - let r = _mm_maskz_loadu_ps(m, black_box(p)); + let r = unsafe { _mm_maskz_loadu_ps(m, black_box(p)) }; let e = _mm_setr_ps(0.0, 2.0, 0.0, 4.0); assert_eq_m128(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_load_ps() { + const fn test_mm_mask_load_ps() { #[repr(align(16))] struct Align { data: [f32; 4], // 16 bytes @@ -53729,13 +53775,13 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b1010; - let r = _mm_mask_load_ps(src, m, black_box(p)); + let r = unsafe { _mm_mask_load_ps(src, m, black_box(p)) }; let e = _mm_setr_ps(42.0, 2.0, 42.0, 4.0); assert_eq_m128(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_maskz_load_ps() { + const fn test_mm_maskz_load_ps() { #[repr(align(16))] struct Align { data: [f32; 4], // 16 bytes @@ -53745,23 +53791,25 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b1010; - let r = _mm_maskz_load_ps(m, black_box(p)); + let r = unsafe { _mm_maskz_load_ps(m, black_box(p)) }; let e = _mm_setr_ps(0.0, 2.0, 0.0, 4.0); assert_eq_m128(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_storeu_ps() { + const fn test_mm_mask_storeu_ps() { let mut r = [42_f32; 4]; let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); let m = 0b1010; - _mm_mask_storeu_ps(r.as_mut_ptr(), m, a); + unsafe { + _mm_mask_storeu_ps(r.as_mut_ptr(), m, a); + } let e = _mm_setr_ps(42.0, 2.0, 42.0, 4.0); - assert_eq_m128(_mm_loadu_ps(r.as_ptr()), e); + assert_eq_m128(unsafe { _mm_loadu_ps(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_store_ps() { + const fn test_mm_mask_store_ps() { #[repr(align(16))] struct Align { data: [f32; 4], // 16 bytes @@ -53769,34 +53817,36 @@ mod tests { let mut r = Align { data: [42.0; 4] }; let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); let m = 0b1010; - _mm_mask_store_ps(r.data.as_mut_ptr(), m, a); + unsafe { + _mm_mask_store_ps(r.data.as_mut_ptr(), m, a); + } let e = _mm_setr_ps(42.0, 2.0, 42.0, 4.0); - assert_eq_m128(_mm_load_ps(r.data.as_ptr()), e); + assert_eq_m128(unsafe { _mm_load_ps(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_loadu_pd() { + const fn test_mm_mask_loadu_pd() { let src = _mm_set1_pd(42.0); let a = &[1.0_f64, 2.0]; let p = a.as_ptr(); let m = 0b10; - let r = _mm_mask_loadu_pd(src, m, black_box(p)); + let r = unsafe { _mm_mask_loadu_pd(src, m, black_box(p)) }; let e = _mm_setr_pd(42.0, 2.0); assert_eq_m128d(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_maskz_loadu_pd() { + const fn test_mm_maskz_loadu_pd() { let a = &[1.0_f64, 2.0]; let p = a.as_ptr(); let m = 0b10; - let r = _mm_maskz_loadu_pd(m, black_box(p)); + let r = unsafe { _mm_maskz_loadu_pd(m, black_box(p)) }; let e = _mm_setr_pd(0.0, 2.0); assert_eq_m128d(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_load_pd() { + const fn test_mm_mask_load_pd() { #[repr(align(16))] struct Align { data: [f64; 2], // 16 bytes @@ -53807,13 +53857,13 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b10; - let r = _mm_mask_load_pd(src, m, black_box(p)); + let r = unsafe { _mm_mask_load_pd(src, m, black_box(p)) }; let e = _mm_setr_pd(42.0, 2.0); assert_eq_m128d(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_maskz_load_pd() { + const fn test_mm_maskz_load_pd() { #[repr(align(16))] struct Align { data: [f64; 2], // 16 bytes @@ -53823,77 +53873,79 @@ mod tests { }; let p = a.data.as_ptr(); let m = 0b10; - let r = _mm_maskz_load_pd(m, black_box(p)); + let r = unsafe { _mm_maskz_load_pd(m, black_box(p)) }; let e = _mm_setr_pd(0.0, 2.0); assert_eq_m128d(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm_mask_load_ss() { + fn test_mm_mask_load_ss() { #[repr(align(16))] struct Align { data: f32, } let src = _mm_set_ss(2.0); let mem = Align { data: 1.0 }; - let r = _mm_mask_load_ss(src, 0b1, &mem.data); + let r = unsafe { _mm_mask_load_ss(src, 0b1, &mem.data) }; assert_eq_m128(r, _mm_set_ss(1.0)); - let r = _mm_mask_load_ss(src, 0b0, &mem.data); + let r = unsafe { _mm_mask_load_ss(src, 0b0, &mem.data) }; assert_eq_m128(r, _mm_set_ss(2.0)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm_maskz_load_ss() { + fn test_mm_maskz_load_ss() { #[repr(align(16))] struct Align { data: f32, } let mem = Align { data: 1.0 }; - let r = _mm_maskz_load_ss(0b1, &mem.data); + let r = unsafe { _mm_maskz_load_ss(0b1, &mem.data) }; assert_eq_m128(r, _mm_set_ss(1.0)); - let r = _mm_maskz_load_ss(0b0, &mem.data); + let r = unsafe { _mm_maskz_load_ss(0b0, &mem.data) }; assert_eq_m128(r, _mm_set_ss(0.0)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm_mask_load_sd() { + fn test_mm_mask_load_sd() { #[repr(align(16))] struct Align { data: f64, } let src = _mm_set_sd(2.0); let mem = Align { data: 1.0 }; - let r = _mm_mask_load_sd(src, 0b1, &mem.data); + let r = unsafe { _mm_mask_load_sd(src, 0b1, &mem.data) }; assert_eq_m128d(r, _mm_set_sd(1.0)); - let r = _mm_mask_load_sd(src, 0b0, &mem.data); + let r = unsafe { _mm_mask_load_sd(src, 0b0, &mem.data) }; assert_eq_m128d(r, _mm_set_sd(2.0)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm_maskz_load_sd() { + fn test_mm_maskz_load_sd() { #[repr(align(16))] struct Align { data: f64, } let mem = Align { data: 1.0 }; - let r = _mm_maskz_load_sd(0b1, &mem.data); + let r = unsafe { _mm_maskz_load_sd(0b1, &mem.data) }; assert_eq_m128d(r, _mm_set_sd(1.0)); - let r = _mm_maskz_load_sd(0b0, &mem.data); + let r = unsafe { _mm_maskz_load_sd(0b0, &mem.data) }; assert_eq_m128d(r, _mm_set_sd(0.0)); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_storeu_pd() { + const fn test_mm_mask_storeu_pd() { let mut r = [42_f64; 2]; let a = _mm_setr_pd(1.0, 2.0); let m = 0b10; - _mm_mask_storeu_pd(r.as_mut_ptr(), m, a); + unsafe { + _mm_mask_storeu_pd(r.as_mut_ptr(), m, a); + } let e = _mm_setr_pd(42.0, 2.0); - assert_eq_m128d(_mm_loadu_pd(r.as_ptr()), e); + assert_eq_m128d(unsafe { _mm_loadu_pd(r.as_ptr()) }, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_mask_store_pd() { + const fn test_mm_mask_store_pd() { #[repr(align(16))] struct Align { data: [f64; 2], // 16 bytes @@ -53901,36 +53953,46 @@ mod tests { let mut r = Align { data: [42.0; 2] }; let a = _mm_setr_pd(1.0, 2.0); let m = 0b10; - _mm_mask_store_pd(r.data.as_mut_ptr(), m, a); + unsafe { + _mm_mask_store_pd(r.data.as_mut_ptr(), m, a); + } let e = _mm_setr_pd(42.0, 2.0); - assert_eq_m128d(_mm_load_pd(r.data.as_ptr()), e); + assert_eq_m128d(unsafe { _mm_load_pd(r.data.as_ptr()) }, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm_mask_store_ss() { + fn test_mm_mask_store_ss() { #[repr(align(16))] struct Align { data: f32, } let a = _mm_set_ss(2.0); let mut mem = Align { data: 1.0 }; - _mm_mask_store_ss(&mut mem.data, 0b1, a); + unsafe { + _mm_mask_store_ss(&mut mem.data, 0b1, a); + } assert_eq!(mem.data, 2.0); - _mm_mask_store_ss(&mut mem.data, 0b0, a); + unsafe { + _mm_mask_store_ss(&mut mem.data, 0b0, a); + } assert_eq!(mem.data, 2.0); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm_mask_store_sd() { + fn test_mm_mask_store_sd() { #[repr(align(16))] struct Align { data: f64, } let a = _mm_set_sd(2.0); let mut mem = Align { data: 1.0 }; - _mm_mask_store_sd(&mut mem.data, 0b1, a); + unsafe { + _mm_mask_store_sd(&mut mem.data, 0b1, a); + } assert_eq!(mem.data, 2.0); - _mm_mask_store_sd(&mut mem.data, 0b0, a); + unsafe { + _mm_mask_store_sd(&mut mem.data, 0b0, a); + } assert_eq!(mem.data, 2.0); } @@ -57931,11 +57993,11 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_kortest_mask16_u8() { + const fn test_kortest_mask16_u8() { let a: __mmask16 = 0b0110100101101001; let b: __mmask16 = 0b1011011010110110; let mut all_ones: u8 = 0; - let r = _kortest_mask16_u8(a, b, &mut all_ones); + let r = unsafe { _kortest_mask16_u8(a, b, &mut all_ones) }; assert_eq!(r, 0); assert_eq!(all_ones, 1); } @@ -57997,18 +58059,20 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_load_mask16() { + const fn test_load_mask16() { let a: __mmask16 = 0b1001011011000011; - let r = _load_mask16(&a); + let r = unsafe { _load_mask16(&a) }; let e: __mmask16 = 0b1001011011000011; assert_eq!(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_store_mask16() { + const fn test_store_mask16() { let a: __mmask16 = 0b0110100100111100; let mut r = 0; - _store_mask16(&mut r, a); + unsafe { + _store_mask16(&mut r, a); + } let e: __mmask16 = 0b0110100100111100; assert_eq!(r, e); } @@ -58189,7 +58253,7 @@ mod tests { #[simd_test(enable = "avx512f")] #[cfg_attr(miri, ignore)] - unsafe fn test_mm512_stream_ps() { + fn test_mm512_stream_ps() { #[repr(align(64))] struct Memory { pub data: [f32; 16], // 64 bytes @@ -58197,7 +58261,9 @@ mod tests { let a = _mm512_set1_ps(7.0); let mut mem = Memory { data: [-1.0; 16] }; - _mm512_stream_ps(&mut mem.data[0] as *mut f32, a); + unsafe { + _mm512_stream_ps(&mut mem.data[0] as *mut f32, a); + } _mm_sfence(); for i in 0..16 { assert_eq!(mem.data[i], get_m512(a, i)); @@ -58206,7 +58272,7 @@ mod tests { #[simd_test(enable = "avx512f")] #[cfg_attr(miri, ignore)] - unsafe fn test_mm512_stream_pd() { + fn test_mm512_stream_pd() { #[repr(align(64))] struct Memory { pub data: [f64; 8], @@ -58214,7 +58280,9 @@ mod tests { let a = _mm512_set1_pd(7.0); let mut mem = Memory { data: [-1.0; 8] }; - _mm512_stream_pd(&mut mem.data[0] as *mut f64, a); + unsafe { + _mm512_stream_pd(&mut mem.data[0] as *mut f64, a); + } _mm_sfence(); for i in 0..8 { assert_eq!(mem.data[i], get_m512d(a, i)); @@ -58223,7 +58291,7 @@ mod tests { #[simd_test(enable = "avx512f")] #[cfg_attr(miri, ignore)] - unsafe fn test_mm512_stream_si512() { + fn test_mm512_stream_si512() { #[repr(align(64))] struct Memory { pub data: [i64; 8], @@ -58231,7 +58299,9 @@ mod tests { let a = _mm512_set1_epi32(7); let mut mem = Memory { data: [-1; 8] }; - _mm512_stream_si512(mem.data.as_mut_ptr().cast(), a); + unsafe { + _mm512_stream_si512(mem.data.as_mut_ptr().cast(), a); + } _mm_sfence(); for i in 0..8 { assert_eq!(mem.data[i], get_m512i(a, i)); @@ -58239,9 +58309,9 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_stream_load_si512() { + fn test_mm512_stream_load_si512() { let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8); - let r = _mm512_stream_load_si512(core::ptr::addr_of!(a) as *const _); + let r = unsafe { _mm512_stream_load_si512(core::ptr::addr_of!(a) as *const _) }; assert_eq_m512i(a, r); } @@ -58558,75 +58628,103 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_compressstoreu_epi32() { + fn test_mm512_mask_compressstoreu_epi32() { let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); let mut r = [0_i32; 16]; - _mm512_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a); + unsafe { + _mm512_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i32; 16]); - _mm512_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b1111000011001010, a); + unsafe { + _mm512_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b1111000011001010, a); + } assert_eq!(&r, &[2, 4, 7, 8, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0]); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_compressstoreu_epi32() { + fn test_mm256_mask_compressstoreu_epi32() { let a = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8); let mut r = [0_i32; 8]; - _mm256_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a); + unsafe { + _mm256_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i32; 8]); - _mm256_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b11001010, a); + unsafe { + _mm256_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b11001010, a); + } assert_eq!(&r, &[2, 4, 7, 8, 0, 0, 0, 0]); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_compressstoreu_epi32() { + fn test_mm_mask_compressstoreu_epi32() { let a = _mm_setr_epi32(1, 2, 3, 4); let mut r = [0_i32; 4]; - _mm_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a); + unsafe { + _mm_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i32; 4]); - _mm_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b1011, a); + unsafe { + _mm_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b1011, a); + } assert_eq!(&r, &[1, 2, 4, 0]); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_compressstoreu_epi64() { + fn test_mm512_mask_compressstoreu_epi64() { let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8); let mut r = [0_i64; 8]; - _mm512_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a); + unsafe { + _mm512_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i64; 8]); - _mm512_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b11001010, a); + unsafe { + _mm512_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b11001010, a); + } assert_eq!(&r, &[2, 4, 7, 8, 0, 0, 0, 0]); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_compressstoreu_epi64() { + fn test_mm256_mask_compressstoreu_epi64() { let a = _mm256_setr_epi64x(1, 2, 3, 4); let mut r = [0_i64; 4]; - _mm256_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a); + unsafe { + _mm256_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i64; 4]); - _mm256_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b1011, a); + unsafe { + _mm256_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b1011, a); + } assert_eq!(&r, &[1, 2, 4, 0]); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_compressstoreu_epi64() { + fn test_mm_mask_compressstoreu_epi64() { let a = _mm_setr_epi64x(1, 2); let mut r = [0_i64; 2]; - _mm_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a); + unsafe { + _mm_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i64; 2]); - _mm_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b10, a); + unsafe { + _mm_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b10, a); + } assert_eq!(&r, &[2, 0]); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_compressstoreu_ps() { + fn test_mm512_mask_compressstoreu_ps() { let a = _mm512_setr_ps( 1_f32, 2_f32, 3_f32, 4_f32, 5_f32, 6_f32, 7_f32, 8_f32, 9_f32, 10_f32, 11_f32, 12_f32, 13_f32, 14_f32, 15_f32, 16_f32, ); let mut r = [0_f32; 16]; - _mm512_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a); + unsafe { + _mm512_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_f32; 16]); - _mm512_mask_compressstoreu_ps(r.as_mut_ptr(), 0b1111000011001010, a); + unsafe { + _mm512_mask_compressstoreu_ps(r.as_mut_ptr(), 0b1111000011001010, a); + } assert_eq!( &r, &[ @@ -58637,12 +58735,16 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_compressstoreu_ps() { + fn test_mm256_mask_compressstoreu_ps() { let a = _mm256_setr_ps(1_f32, 2_f32, 3_f32, 4_f32, 5_f32, 6_f32, 7_f32, 8_f32); let mut r = [0_f32; 8]; - _mm256_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a); + unsafe { + _mm256_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_f32; 8]); - _mm256_mask_compressstoreu_ps(r.as_mut_ptr(), 0b11001010, a); + unsafe { + _mm256_mask_compressstoreu_ps(r.as_mut_ptr(), 0b11001010, a); + } assert_eq!( &r, &[2_f32, 4_f32, 7_f32, 8_f32, 0_f32, 0_f32, 0_f32, 0_f32] @@ -58650,47 +58752,63 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_compressstoreu_ps() { + fn test_mm_mask_compressstoreu_ps() { let a = _mm_setr_ps(1_f32, 2_f32, 3_f32, 4_f32); let mut r = [0.; 4]; - _mm_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a); + unsafe { + _mm_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0.; 4]); - _mm_mask_compressstoreu_ps(r.as_mut_ptr(), 0b1011, a); + unsafe { + _mm_mask_compressstoreu_ps(r.as_mut_ptr(), 0b1011, a); + } assert_eq!(&r, &[1_f32, 2_f32, 4_f32, 0_f32]); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_compressstoreu_pd() { + fn test_mm512_mask_compressstoreu_pd() { let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.); let mut r = [0.; 8]; - _mm512_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a); + unsafe { + _mm512_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0.; 8]); - _mm512_mask_compressstoreu_pd(r.as_mut_ptr(), 0b11001010, a); + unsafe { + _mm512_mask_compressstoreu_pd(r.as_mut_ptr(), 0b11001010, a); + } assert_eq!(&r, &[2., 4., 7., 8., 0., 0., 0., 0.]); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_compressstoreu_pd() { + fn test_mm256_mask_compressstoreu_pd() { let a = _mm256_setr_pd(1., 2., 3., 4.); let mut r = [0.; 4]; - _mm256_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a); + unsafe { + _mm256_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0.; 4]); - _mm256_mask_compressstoreu_pd(r.as_mut_ptr(), 0b1011, a); + unsafe { + _mm256_mask_compressstoreu_pd(r.as_mut_ptr(), 0b1011, a); + } assert_eq!(&r, &[1., 2., 4., 0.]); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_compressstoreu_pd() { + fn test_mm_mask_compressstoreu_pd() { let a = _mm_setr_pd(1., 2.); let mut r = [0.; 2]; - _mm_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a); + unsafe { + _mm_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0.; 2]); - _mm_mask_compressstoreu_pd(r.as_mut_ptr(), 0b10, a); + unsafe { + _mm_mask_compressstoreu_pd(r.as_mut_ptr(), 0b10, a); + } assert_eq!(&r, &[2., 0.]); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_expand_epi32() { + fn test_mm512_mask_expand_epi32() { let src = _mm512_set1_epi32(200); let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); let r = _mm512_mask_expand_epi32(src, 0, a); @@ -58826,109 +58944,135 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_loadu_epi32() { + const fn test_mm512_loadu_epi32() { let a = &[4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50]; let p = a.as_ptr(); - let r = _mm512_loadu_epi32(black_box(p)); + let r = unsafe { _mm512_loadu_epi32(black_box(p)) }; let e = _mm512_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_loadu_epi32() { + const fn test_mm256_loadu_epi32() { let a = &[4, 3, 2, 5, 8, 9, 64, 50]; let p = a.as_ptr(); - let r = _mm256_loadu_epi32(black_box(p)); + let r = unsafe { _mm256_loadu_epi32(black_box(p)) }; let e = _mm256_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_loadu_epi32() { + const fn test_mm_loadu_epi32() { let a = &[4, 3, 2, 5]; let p = a.as_ptr(); - let r = _mm_loadu_epi32(black_box(p)); + let r = unsafe { _mm_loadu_epi32(black_box(p)) }; let e = _mm_setr_epi32(4, 3, 2, 5); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtepi32_storeu_epi16() { + fn test_mm512_mask_cvtepi32_storeu_epi16() { let a = _mm512_set1_epi32(9); let mut r = _mm256_undefined_si256(); - _mm512_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111_11111111, a); + unsafe { + _mm512_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111_11111111, a); + } let e = _mm256_set1_epi16(9); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtepi32_storeu_epi16() { + fn test_mm256_mask_cvtepi32_storeu_epi16() { let a = _mm256_set1_epi32(9); let mut r = _mm_undefined_si128(); - _mm256_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm256_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set1_epi16(9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtepi32_storeu_epi16() { + fn test_mm_mask_cvtepi32_storeu_epi16() { let a = _mm_set1_epi32(9); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set_epi16(0, 0, 0, 0, 9, 9, 9, 9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtsepi32_storeu_epi16() { + fn test_mm512_mask_cvtsepi32_storeu_epi16() { let a = _mm512_set1_epi32(i32::MAX); let mut r = _mm256_undefined_si256(); - _mm512_mask_cvtsepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111_11111111, a); + unsafe { + _mm512_mask_cvtsepi32_storeu_epi16( + &mut r as *mut _ as *mut i16, + 0b11111111_11111111, + a, + ); + } let e = _mm256_set1_epi16(i16::MAX); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtsepi32_storeu_epi16() { + fn test_mm256_mask_cvtsepi32_storeu_epi16() { let a = _mm256_set1_epi32(i32::MAX); let mut r = _mm_undefined_si128(); - _mm256_mask_cvtsepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm256_mask_cvtsepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set1_epi16(i16::MAX); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtsepi32_storeu_epi16() { + fn test_mm_mask_cvtsepi32_storeu_epi16() { let a = _mm_set1_epi32(i32::MAX); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtsepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm_mask_cvtsepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set_epi16(0, 0, 0, 0, i16::MAX, i16::MAX, i16::MAX, i16::MAX); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtusepi32_storeu_epi16() { + fn test_mm512_mask_cvtusepi32_storeu_epi16() { let a = _mm512_set1_epi32(i32::MAX); let mut r = _mm256_undefined_si256(); - _mm512_mask_cvtusepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111_11111111, a); + unsafe { + _mm512_mask_cvtusepi32_storeu_epi16( + &mut r as *mut _ as *mut i16, + 0b11111111_11111111, + a, + ); + } let e = _mm256_set1_epi16(u16::MAX as i16); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtusepi32_storeu_epi16() { + fn test_mm256_mask_cvtusepi32_storeu_epi16() { let a = _mm256_set1_epi32(i32::MAX); let mut r = _mm_undefined_si128(); - _mm256_mask_cvtusepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm256_mask_cvtusepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set1_epi16(u16::MAX as i16); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtusepi32_storeu_epi16() { + fn test_mm_mask_cvtusepi32_storeu_epi16() { let a = _mm_set1_epi32(i32::MAX); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtusepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm_mask_cvtusepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set_epi16( 0, 0, @@ -58943,46 +59087,56 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtepi32_storeu_epi8() { + fn test_mm512_mask_cvtepi32_storeu_epi8() { let a = _mm512_set1_epi32(9); let mut r = _mm_undefined_si128(); - _mm512_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + unsafe { + _mm512_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + } let e = _mm_set1_epi8(9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtepi32_storeu_epi8() { + fn test_mm256_mask_cvtepi32_storeu_epi8() { let a = _mm256_set1_epi32(9); let mut r = _mm_set1_epi8(0); - _mm256_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm256_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 9, 9, 9, 9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtepi32_storeu_epi8() { + fn test_mm_mask_cvtepi32_storeu_epi8() { let a = _mm_set1_epi32(9); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtsepi32_storeu_epi8() { + fn test_mm512_mask_cvtsepi32_storeu_epi8() { let a = _mm512_set1_epi32(i32::MAX); let mut r = _mm_undefined_si128(); - _mm512_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + unsafe { + _mm512_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + } let e = _mm_set1_epi8(i8::MAX); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtsepi32_storeu_epi8() { + fn test_mm256_mask_cvtsepi32_storeu_epi8() { let a = _mm256_set1_epi32(i32::MAX); let mut r = _mm_set1_epi8(0); - _mm256_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm256_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } #[rustfmt::skip] let e = _mm_set_epi8( 0, 0, 0, 0, @@ -58994,10 +59148,12 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtsepi32_storeu_epi8() { + fn test_mm_mask_cvtsepi32_storeu_epi8() { let a = _mm_set1_epi32(i32::MAX); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } #[rustfmt::skip] let e = _mm_set_epi8( 0, 0, 0, 0, @@ -59009,19 +59165,23 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtusepi32_storeu_epi8() { + fn test_mm512_mask_cvtusepi32_storeu_epi8() { let a = _mm512_set1_epi32(i32::MAX); let mut r = _mm_undefined_si128(); - _mm512_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + unsafe { + _mm512_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a); + } let e = _mm_set1_epi8(u8::MAX as i8); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtusepi32_storeu_epi8() { + fn test_mm256_mask_cvtusepi32_storeu_epi8() { let a = _mm256_set1_epi32(i32::MAX); let mut r = _mm_set1_epi8(0); - _mm256_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm256_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } #[rustfmt::skip] let e = _mm_set_epi8( 0, 0, 0, 0, @@ -59033,10 +59193,12 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtusepi32_storeu_epi8() { + fn test_mm_mask_cvtusepi32_storeu_epi8() { let a = _mm_set1_epi32(i32::MAX); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } #[rustfmt::skip] let e = _mm_set_epi8( 0, 0, 0, 0, @@ -59048,48 +59210,56 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_storeu_epi32() { + const fn test_mm512_storeu_epi32() { let a = _mm512_set1_epi32(9); let mut r = _mm512_undefined_epi32(); - _mm512_storeu_epi32(&mut r as *mut _ as *mut i32, a); + unsafe { + _mm512_storeu_epi32(&mut r as *mut _ as *mut i32, a); + } assert_eq_m512i(r, a); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_storeu_epi32() { + const fn test_mm256_storeu_epi32() { let a = _mm256_set1_epi32(9); let mut r = _mm256_undefined_si256(); - _mm256_storeu_epi32(&mut r as *mut _ as *mut i32, a); + unsafe { + _mm256_storeu_epi32(&mut r as *mut _ as *mut i32, a); + } assert_eq_m256i(r, a); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_storeu_epi32() { + const fn test_mm_storeu_epi32() { let a = _mm_set1_epi32(9); let mut r = _mm_undefined_si128(); - _mm_storeu_epi32(&mut r as *mut _ as *mut i32, a); + unsafe { + _mm_storeu_epi32(&mut r as *mut _ as *mut i32, a); + } assert_eq_m128i(r, a); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_loadu_si512() { + const fn test_mm512_loadu_si512() { let a = &[4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50]; let p = a.as_ptr().cast(); - let r = _mm512_loadu_si512(black_box(p)); + let r = unsafe { _mm512_loadu_si512(black_box(p)) }; let e = _mm512_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_storeu_si512() { + const fn test_mm512_storeu_si512() { let a = _mm512_set1_epi32(9); let mut r = _mm512_undefined_epi32(); - _mm512_storeu_si512(&mut r as *mut _, a); + unsafe { + _mm512_storeu_si512(&mut r as *mut _, a); + } assert_eq_m512i(r, a); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_load_si512() { + const fn test_mm512_load_si512() { #[repr(align(64))] struct Align { data: [i32; 16], // 64 bytes @@ -59098,21 +59268,23 @@ mod tests { data: [4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50], }; let p = (a.data).as_ptr().cast(); - let r = _mm512_load_si512(black_box(p)); + let r = unsafe { _mm512_load_si512(black_box(p)) }; let e = _mm512_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_store_si512() { + const fn test_mm512_store_si512() { let a = _mm512_set1_epi32(9); let mut r = _mm512_undefined_epi32(); - _mm512_store_si512(&mut r as *mut _, a); + unsafe { + _mm512_store_si512(&mut r as *mut _, a); + } assert_eq_m512i(r, a); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_load_epi32() { + const fn test_mm512_load_epi32() { #[repr(align(64))] struct Align { data: [i32; 16], // 64 bytes @@ -59121,13 +59293,13 @@ mod tests { data: [4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50], }; let p = (a.data).as_ptr(); - let r = _mm512_load_epi32(black_box(p)); + let r = unsafe { _mm512_load_epi32(black_box(p)) }; let e = _mm512_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_load_epi32() { + const fn test_mm256_load_epi32() { #[repr(align(64))] struct Align { data: [i32; 8], @@ -59136,50 +59308,56 @@ mod tests { data: [4, 3, 2, 5, 8, 9, 64, 50], }; let p = (a.data).as_ptr(); - let r = _mm256_load_epi32(black_box(p)); + let r = unsafe { _mm256_load_epi32(black_box(p)) }; let e = _mm256_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_load_epi32() { + const fn test_mm_load_epi32() { #[repr(align(64))] struct Align { data: [i32; 4], } let a = Align { data: [4, 3, 2, 5] }; let p = (a.data).as_ptr(); - let r = _mm_load_epi32(black_box(p)); + let r = unsafe { _mm_load_epi32(black_box(p)) }; let e = _mm_setr_epi32(4, 3, 2, 5); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_store_epi32() { + const fn test_mm512_store_epi32() { let a = _mm512_set1_epi32(9); let mut r = _mm512_undefined_epi32(); - _mm512_store_epi32(&mut r as *mut _ as *mut i32, a); + unsafe { + _mm512_store_epi32(&mut r as *mut _ as *mut i32, a); + } assert_eq_m512i(r, a); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_store_epi32() { + const fn test_mm256_store_epi32() { let a = _mm256_set1_epi32(9); let mut r = _mm256_undefined_si256(); - _mm256_store_epi32(&mut r as *mut _ as *mut i32, a); + unsafe { + _mm256_store_epi32(&mut r as *mut _ as *mut i32, a); + } assert_eq_m256i(r, a); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_store_epi32() { + const fn test_mm_store_epi32() { let a = _mm_set1_epi32(9); let mut r = _mm_undefined_si128(); - _mm_store_epi32(&mut r as *mut _ as *mut i32, a); + unsafe { + _mm_store_epi32(&mut r as *mut _ as *mut i32, a); + } assert_eq_m128i(r, a); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_load_ps() { + const fn test_mm512_load_ps() { #[repr(align(64))] struct Align { data: [f32; 16], // 64 bytes @@ -59190,7 +59368,7 @@ mod tests { ], }; let p = (a.data).as_ptr(); - let r = _mm512_load_ps(black_box(p)); + let r = unsafe { _mm512_load_ps(black_box(p)) }; let e = _mm512_setr_ps( 4., 3., 2., 5., 8., 9., 64., 50., -4., -3., -2., -5., -8., -9., -64., -50., ); @@ -59198,10 +59376,12 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_store_ps() { + const fn test_mm512_store_ps() { let a = _mm512_set1_ps(9.); let mut r = _mm512_undefined_ps(); - _mm512_store_ps(&mut r as *mut _ as *mut f32, a); + unsafe { + _mm512_store_ps(&mut r as *mut _ as *mut f32, a); + } assert_eq_m512(r, a); } @@ -62191,140 +62371,140 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_expandloadu_epi32() { + fn test_mm512_mask_expandloadu_epi32() { let src = _mm512_set1_epi32(42); let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_mask_expandloadu_epi32(src, m, black_box(p)); + let r = unsafe { _mm512_mask_expandloadu_epi32(src, m, black_box(p)) }; let e = _mm512_set_epi32(8, 7, 6, 42, 5, 42, 42, 42, 4, 3, 42, 42, 2, 42, 1, 42); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_maskz_expandloadu_epi32() { + fn test_mm512_maskz_expandloadu_epi32() { let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_maskz_expandloadu_epi32(m, black_box(p)); + let r = unsafe { _mm512_maskz_expandloadu_epi32(m, black_box(p)) }; let e = _mm512_set_epi32(8, 7, 6, 0, 5, 0, 0, 0, 4, 3, 0, 0, 2, 0, 1, 0); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_expandloadu_epi32() { + fn test_mm256_mask_expandloadu_epi32() { let src = _mm256_set1_epi32(42); let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm256_mask_expandloadu_epi32(src, m, black_box(p)); + let r = unsafe { _mm256_mask_expandloadu_epi32(src, m, black_box(p)) }; let e = _mm256_set_epi32(4, 3, 2, 42, 1, 42, 42, 42); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_maskz_expandloadu_epi32() { + fn test_mm256_maskz_expandloadu_epi32() { let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm256_maskz_expandloadu_epi32(m, black_box(p)); + let r = unsafe { _mm256_maskz_expandloadu_epi32(m, black_box(p)) }; let e = _mm256_set_epi32(4, 3, 2, 0, 1, 0, 0, 0); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_expandloadu_epi32() { + fn test_mm_mask_expandloadu_epi32() { let src = _mm_set1_epi32(42); let a = &[1_i32, 2, 3, 4]; let p = a.as_ptr(); let m = 0b11111000; - let r = _mm_mask_expandloadu_epi32(src, m, black_box(p)); + let r = unsafe { _mm_mask_expandloadu_epi32(src, m, black_box(p)) }; let e = _mm_set_epi32(1, 42, 42, 42); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_maskz_expandloadu_epi32() { + fn test_mm_maskz_expandloadu_epi32() { let a = &[1_i32, 2, 3, 4]; let p = a.as_ptr(); let m = 0b11111000; - let r = _mm_maskz_expandloadu_epi32(m, black_box(p)); + let r = unsafe { _mm_maskz_expandloadu_epi32(m, black_box(p)) }; let e = _mm_set_epi32(1, 0, 0, 0); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_expandloadu_epi64() { + fn test_mm512_mask_expandloadu_epi64() { let src = _mm512_set1_epi64(42); let a = &[1_i64, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm512_mask_expandloadu_epi64(src, m, black_box(p)); + let r = unsafe { _mm512_mask_expandloadu_epi64(src, m, black_box(p)) }; let e = _mm512_set_epi64(4, 3, 2, 42, 1, 42, 42, 42); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_maskz_expandloadu_epi64() { + fn test_mm512_maskz_expandloadu_epi64() { let a = &[1_i64, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm512_maskz_expandloadu_epi64(m, black_box(p)); + let r = unsafe { _mm512_maskz_expandloadu_epi64(m, black_box(p)) }; let e = _mm512_set_epi64(4, 3, 2, 0, 1, 0, 0, 0); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_expandloadu_epi64() { + fn test_mm256_mask_expandloadu_epi64() { let src = _mm256_set1_epi64x(42); let a = &[1_i64, 2, 3, 4]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm256_mask_expandloadu_epi64(src, m, black_box(p)); + let r = unsafe { _mm256_mask_expandloadu_epi64(src, m, black_box(p)) }; let e = _mm256_set_epi64x(1, 42, 42, 42); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_maskz_expandloadu_epi64() { + fn test_mm256_maskz_expandloadu_epi64() { let a = &[1_i64, 2, 3, 4]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm256_maskz_expandloadu_epi64(m, black_box(p)); + let r = unsafe { _mm256_maskz_expandloadu_epi64(m, black_box(p)) }; let e = _mm256_set_epi64x(1, 0, 0, 0); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_expandloadu_epi64() { + fn test_mm_mask_expandloadu_epi64() { let src = _mm_set1_epi64x(42); let a = &[1_i64, 2]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm_mask_expandloadu_epi64(src, m, black_box(p)); + let r = unsafe { _mm_mask_expandloadu_epi64(src, m, black_box(p)) }; let e = _mm_set_epi64x(42, 42); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_maskz_expandloadu_epi64() { + fn test_mm_maskz_expandloadu_epi64() { let a = &[1_i64, 2]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm_maskz_expandloadu_epi64(m, black_box(p)); + let r = unsafe { _mm_maskz_expandloadu_epi64(m, black_box(p)) }; let e = _mm_set_epi64x(0, 0); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_expandloadu_ps() { + fn test_mm512_mask_expandloadu_ps() { let src = _mm512_set1_ps(42.); let a = &[ 1.0f32, 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16., ]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_mask_expandloadu_ps(src, m, black_box(p)); + let r = unsafe { _mm512_mask_expandloadu_ps(src, m, black_box(p)) }; let e = _mm512_set_ps( 8., 7., 6., 42., 5., 42., 42., 42., 4., 3., 42., 42., 2., 42., 1., 42., ); @@ -62332,13 +62512,13 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_maskz_expandloadu_ps() { + fn test_mm512_maskz_expandloadu_ps() { let a = &[ 1.0f32, 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16., ]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm512_maskz_expandloadu_ps(m, black_box(p)); + let r = unsafe { _mm512_maskz_expandloadu_ps(m, black_box(p)) }; let e = _mm512_set_ps( 8., 7., 6., 0., 5., 0., 0., 0., 4., 3., 0., 0., 2., 0., 1., 0., ); @@ -62346,106 +62526,106 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_expandloadu_ps() { + fn test_mm256_mask_expandloadu_ps() { let src = _mm256_set1_ps(42.); let a = &[1.0f32, 2., 3., 4., 5., 6., 7., 8.]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm256_mask_expandloadu_ps(src, m, black_box(p)); + let r = unsafe { _mm256_mask_expandloadu_ps(src, m, black_box(p)) }; let e = _mm256_set_ps(4., 3., 2., 42., 1., 42., 42., 42.); assert_eq_m256(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_maskz_expandloadu_ps() { + fn test_mm256_maskz_expandloadu_ps() { let a = &[1.0f32, 2., 3., 4., 5., 6., 7., 8.]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm256_maskz_expandloadu_ps(m, black_box(p)); + let r = unsafe { _mm256_maskz_expandloadu_ps(m, black_box(p)) }; let e = _mm256_set_ps(4., 3., 2., 0., 1., 0., 0., 0.); assert_eq_m256(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_expandloadu_ps() { + fn test_mm_mask_expandloadu_ps() { let src = _mm_set1_ps(42.); let a = &[1.0f32, 2., 3., 4.]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm_mask_expandloadu_ps(src, m, black_box(p)); + let r = unsafe { _mm_mask_expandloadu_ps(src, m, black_box(p)) }; let e = _mm_set_ps(1., 42., 42., 42.); assert_eq_m128(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_maskz_expandloadu_ps() { + fn test_mm_maskz_expandloadu_ps() { let a = &[1.0f32, 2., 3., 4.]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm_maskz_expandloadu_ps(m, black_box(p)); + let r = unsafe { _mm_maskz_expandloadu_ps(m, black_box(p)) }; let e = _mm_set_ps(1., 0., 0., 0.); assert_eq_m128(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_expandloadu_pd() { + fn test_mm512_mask_expandloadu_pd() { let src = _mm512_set1_pd(42.); let a = &[1.0f64, 2., 3., 4., 5., 6., 7., 8.]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm512_mask_expandloadu_pd(src, m, black_box(p)); + let r = unsafe { _mm512_mask_expandloadu_pd(src, m, black_box(p)) }; let e = _mm512_set_pd(4., 3., 2., 42., 1., 42., 42., 42.); assert_eq_m512d(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_maskz_expandloadu_pd() { + fn test_mm512_maskz_expandloadu_pd() { let a = &[1.0f64, 2., 3., 4., 5., 6., 7., 8.]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm512_maskz_expandloadu_pd(m, black_box(p)); + let r = unsafe { _mm512_maskz_expandloadu_pd(m, black_box(p)) }; let e = _mm512_set_pd(4., 3., 2., 0., 1., 0., 0., 0.); assert_eq_m512d(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_expandloadu_pd() { + fn test_mm256_mask_expandloadu_pd() { let src = _mm256_set1_pd(42.); let a = &[1.0f64, 2., 3., 4.]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm256_mask_expandloadu_pd(src, m, black_box(p)); + let r = unsafe { _mm256_mask_expandloadu_pd(src, m, black_box(p)) }; let e = _mm256_set_pd(1., 42., 42., 42.); assert_eq_m256d(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_maskz_expandloadu_pd() { + fn test_mm256_maskz_expandloadu_pd() { let a = &[1.0f64, 2., 3., 4.]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm256_maskz_expandloadu_pd(m, black_box(p)); + let r = unsafe { _mm256_maskz_expandloadu_pd(m, black_box(p)) }; let e = _mm256_set_pd(1., 0., 0., 0.); assert_eq_m256d(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_expandloadu_pd() { + fn test_mm_mask_expandloadu_pd() { let src = _mm_set1_pd(42.); let a = &[1.0f64, 2.]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm_mask_expandloadu_pd(src, m, black_box(p)); + let r = unsafe { _mm_mask_expandloadu_pd(src, m, black_box(p)) }; let e = _mm_set_pd(42., 42.); assert_eq_m128d(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_maskz_expandloadu_pd() { + fn test_mm_maskz_expandloadu_pd() { let a = &[1.0f64, 2.]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm_maskz_expandloadu_pd(m, black_box(p)); + let r = unsafe { _mm_maskz_expandloadu_pd(m, black_box(p)) }; let e = _mm_set_pd(0., 0.); assert_eq_m128d(r, e); } diff --git a/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs b/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs index 57d47c0bb010..27f06691c550 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs @@ -16932,7 +16932,6 @@ unsafe extern "C" { mod tests { use crate::core_arch::assert_eq_const as assert_eq; use crate::core_arch::x86::*; - use crate::mem::transmute; use crate::ptr::{addr_of, addr_of_mut}; use stdarch_test::simd_test; @@ -17569,72 +17568,72 @@ mod tests { } #[simd_test(enable = "avx512fp16,avx512vl")] - const unsafe fn test_mm_load_ph() { + const fn test_mm_load_ph() { let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0); - let b = _mm_load_ph(addr_of!(a).cast()); + let b = unsafe { _mm_load_ph(addr_of!(a).cast()) }; assert_eq_m128h(a, b); } #[simd_test(enable = "avx512fp16,avx512vl")] - const unsafe fn test_mm256_load_ph() { + const fn test_mm256_load_ph() { let a = _mm256_set_ph( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, ); - let b = _mm256_load_ph(addr_of!(a).cast()); + let b = unsafe { _mm256_load_ph(addr_of!(a).cast()) }; assert_eq_m256h(a, b); } #[simd_test(enable = "avx512fp16")] - const unsafe fn test_mm512_load_ph() { + const fn test_mm512_load_ph() { let a = _mm512_set_ph( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0, 31.0, 32.0, ); - let b = _mm512_load_ph(addr_of!(a).cast()); + let b = unsafe { _mm512_load_ph(addr_of!(a).cast()) }; assert_eq_m512h(a, b); } #[simd_test(enable = "avx512fp16,avx512vl")] - const unsafe fn test_mm_load_sh() { + const fn test_mm_load_sh() { let a = _mm_set_sh(1.0); - let b = _mm_load_sh(addr_of!(a).cast()); + let b = unsafe { _mm_load_sh(addr_of!(a).cast()) }; assert_eq_m128h(a, b); } #[simd_test(enable = "avx512fp16,avx512vl")] - unsafe fn test_mm_mask_load_sh() { + fn test_mm_mask_load_sh() { let a = _mm_set_sh(1.0); let src = _mm_set_sh(2.); - let b = _mm_mask_load_sh(src, 1, addr_of!(a).cast()); + let b = unsafe { _mm_mask_load_sh(src, 1, addr_of!(a).cast()) }; assert_eq_m128h(a, b); - let b = _mm_mask_load_sh(src, 0, addr_of!(a).cast()); + let b = unsafe { _mm_mask_load_sh(src, 0, addr_of!(a).cast()) }; assert_eq_m128h(src, b); } #[simd_test(enable = "avx512fp16,avx512vl")] - unsafe fn test_mm_maskz_load_sh() { + fn test_mm_maskz_load_sh() { let a = _mm_set_sh(1.0); - let b = _mm_maskz_load_sh(1, addr_of!(a).cast()); + let b = unsafe { _mm_maskz_load_sh(1, addr_of!(a).cast()) }; assert_eq_m128h(a, b); - let b = _mm_maskz_load_sh(0, addr_of!(a).cast()); + let b = unsafe { _mm_maskz_load_sh(0, addr_of!(a).cast()) }; assert_eq_m128h(_mm_setzero_ph(), b); } #[simd_test(enable = "avx512fp16,avx512vl")] - const unsafe fn test_mm_loadu_ph() { + const fn test_mm_loadu_ph() { let array = [1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0]; - let r = _mm_loadu_ph(array.as_ptr()); + let r = unsafe { _mm_loadu_ph(array.as_ptr()) }; let e = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0); assert_eq_m128h(r, e); } #[simd_test(enable = "avx512fp16,avx512vl")] - const unsafe fn test_mm256_loadu_ph() { + const fn test_mm256_loadu_ph() { let array = [ 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, ]; - let r = _mm256_loadu_ph(array.as_ptr()); + let r = unsafe { _mm256_loadu_ph(array.as_ptr()) }; let e = _mm256_setr_ph( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, ); @@ -17642,13 +17641,13 @@ mod tests { } #[simd_test(enable = "avx512fp16")] - const unsafe fn test_mm512_loadu_ph() { + const fn test_mm512_loadu_ph() { let array = [ 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0, 31.0, 32.0, ]; - let r = _mm512_loadu_ph(array.as_ptr()); + let r = unsafe { _mm512_loadu_ph(array.as_ptr()) }; let e = _mm512_setr_ph( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0, @@ -17686,81 +17685,99 @@ mod tests { } #[simd_test(enable = "avx512fp16,avx512vl")] - const unsafe fn test_mm_store_ph() { + const fn test_mm_store_ph() { let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0); let mut b = _mm_setzero_ph(); - _mm_store_ph(addr_of_mut!(b).cast(), a); + unsafe { + _mm_store_ph(addr_of_mut!(b).cast(), a); + } assert_eq_m128h(a, b); } #[simd_test(enable = "avx512fp16,avx512vl")] - const unsafe fn test_mm256_store_ph() { + const fn test_mm256_store_ph() { let a = _mm256_set_ph( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, ); let mut b = _mm256_setzero_ph(); - _mm256_store_ph(addr_of_mut!(b).cast(), a); + unsafe { + _mm256_store_ph(addr_of_mut!(b).cast(), a); + } assert_eq_m256h(a, b); } #[simd_test(enable = "avx512fp16")] - const unsafe fn test_mm512_store_ph() { + const fn test_mm512_store_ph() { let a = _mm512_set_ph( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0, 31.0, 32.0, ); let mut b = _mm512_setzero_ph(); - _mm512_store_ph(addr_of_mut!(b).cast(), a); + unsafe { + _mm512_store_ph(addr_of_mut!(b).cast(), a); + } assert_eq_m512h(a, b); } #[simd_test(enable = "avx512fp16,avx512vl")] - const unsafe fn test_mm_store_sh() { + const fn test_mm_store_sh() { let a = _mm_set_sh(1.0); let mut b = _mm_setzero_ph(); - _mm_store_sh(addr_of_mut!(b).cast(), a); + unsafe { + _mm_store_sh(addr_of_mut!(b).cast(), a); + } assert_eq_m128h(a, b); } #[simd_test(enable = "avx512fp16,avx512vl")] - unsafe fn test_mm_mask_store_sh() { + fn test_mm_mask_store_sh() { let a = _mm_set_sh(1.0); let mut b = _mm_setzero_ph(); - _mm_mask_store_sh(addr_of_mut!(b).cast(), 0, a); + unsafe { + _mm_mask_store_sh(addr_of_mut!(b).cast(), 0, a); + } assert_eq_m128h(_mm_setzero_ph(), b); - _mm_mask_store_sh(addr_of_mut!(b).cast(), 1, a); + unsafe { + _mm_mask_store_sh(addr_of_mut!(b).cast(), 1, a); + } assert_eq_m128h(a, b); } #[simd_test(enable = "avx512fp16,avx512vl")] - const unsafe fn test_mm_storeu_ph() { + const fn test_mm_storeu_ph() { let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0); let mut array = [0.0; 8]; - _mm_storeu_ph(array.as_mut_ptr(), a); - assert_eq_m128h(a, _mm_loadu_ph(array.as_ptr())); + unsafe { + _mm_storeu_ph(array.as_mut_ptr(), a); + } + assert_eq_m128h(a, unsafe { _mm_loadu_ph(array.as_ptr()) }); } #[simd_test(enable = "avx512fp16,avx512vl")] - const unsafe fn test_mm256_storeu_ph() { + const fn test_mm256_storeu_ph() { let a = _mm256_set_ph( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, ); let mut array = [0.0; 16]; - _mm256_storeu_ph(array.as_mut_ptr(), a); - assert_eq_m256h(a, _mm256_loadu_ph(array.as_ptr())); + unsafe { + _mm256_storeu_ph(array.as_mut_ptr(), a); + } + assert_eq_m256h(a, unsafe { _mm256_loadu_ph(array.as_ptr()) }); } #[simd_test(enable = "avx512fp16")] - const unsafe fn test_mm512_storeu_ph() { + const fn test_mm512_storeu_ph() { let a = _mm512_set_ph( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0, 31.0, 32.0, ); let mut array = [0.0; 32]; - _mm512_storeu_ph(array.as_mut_ptr(), a); - assert_eq_m512h(a, _mm512_loadu_ph(array.as_ptr())); + unsafe { + _mm512_storeu_ph(array.as_mut_ptr(), a); + } + assert_eq_m512h(a, unsafe { _mm512_loadu_ph(array.as_ptr()) }); } #[simd_test(enable = "avx512fp16,avx512vl")] @@ -23993,16 +24010,16 @@ mod tests { #[simd_test(enable = "avx512fp16,avx512vl")] const fn test_mm256_reduce_mul_ph() { - let a = _mm256_set1_ph(2.0); + let a = _mm256_set1_ph(1.2); let r = _mm256_reduce_mul_ph(a); - assert_eq!(r, 65536.0); + assert_eq!(r, 18.5); } #[simd_test(enable = "avx512fp16")] const fn test_mm512_reduce_mul_ph() { - let a = _mm512_set1_ph(2.0); + let a = _mm512_set1_ph(1.2); let r = _mm512_reduce_mul_ph(a); - assert_eq!(r, 16777216.0); + assert_eq!(r, 342.3); } #[simd_test(enable = "avx512fp16,avx512vl")] diff --git a/library/stdarch/crates/core_arch/src/x86/avx512vbmi2.rs b/library/stdarch/crates/core_arch/src/x86/avx512vbmi2.rs index 26cef5814e9c..78a50b90c861 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512vbmi2.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512vbmi2.rs @@ -3932,7 +3932,7 @@ mod tests { } #[simd_test(enable = "avx512vbmi2")] - unsafe fn test_mm512_mask_expandloadu_epi16() { + fn test_mm512_mask_expandloadu_epi16() { let src = _mm512_set1_epi16(42); let a = &[ 1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, @@ -3940,7 +3940,7 @@ mod tests { ]; let p = a.as_ptr(); let m = 0b11101000_11001010_11110000_00001111; - let r = _mm512_mask_expandloadu_epi16(src, m, black_box(p)); + let r = unsafe { _mm512_mask_expandloadu_epi16(src, m, black_box(p)) }; let e = _mm512_set_epi16( 16, 15, 14, 42, 13, 42, 42, 42, 12, 11, 42, 42, 10, 42, 9, 42, 8, 7, 6, 5, 42, 42, 42, 42, 42, 42, 42, 42, 4, 3, 2, 1, @@ -3949,14 +3949,14 @@ mod tests { } #[simd_test(enable = "avx512vbmi2")] - unsafe fn test_mm512_maskz_expandloadu_epi16() { + fn test_mm512_maskz_expandloadu_epi16() { let a = &[ 1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, ]; let p = a.as_ptr(); let m = 0b11101000_11001010_11110000_00001111; - let r = _mm512_maskz_expandloadu_epi16(m, black_box(p)); + let r = unsafe { _mm512_maskz_expandloadu_epi16(m, black_box(p)) }; let e = _mm512_set_epi16( 16, 15, 14, 0, 13, 0, 0, 0, 12, 11, 0, 0, 10, 0, 9, 0, 8, 7, 6, 5, 0, 0, 0, 0, 0, 0, 0, 0, 4, 3, 2, 1, @@ -3965,49 +3965,49 @@ mod tests { } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm256_mask_expandloadu_epi16() { + fn test_mm256_mask_expandloadu_epi16() { let src = _mm256_set1_epi16(42); let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm256_mask_expandloadu_epi16(src, m, black_box(p)); + let r = unsafe { _mm256_mask_expandloadu_epi16(src, m, black_box(p)) }; let e = _mm256_set_epi16(8, 7, 6, 42, 5, 42, 42, 42, 4, 3, 42, 42, 2, 42, 1, 42); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm256_maskz_expandloadu_epi16() { + fn test_mm256_maskz_expandloadu_epi16() { let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm256_maskz_expandloadu_epi16(m, black_box(p)); + let r = unsafe { _mm256_maskz_expandloadu_epi16(m, black_box(p)) }; let e = _mm256_set_epi16(8, 7, 6, 0, 5, 0, 0, 0, 4, 3, 0, 0, 2, 0, 1, 0); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm_mask_expandloadu_epi16() { + fn test_mm_mask_expandloadu_epi16() { let src = _mm_set1_epi16(42); let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm_mask_expandloadu_epi16(src, m, black_box(p)); + let r = unsafe { _mm_mask_expandloadu_epi16(src, m, black_box(p)) }; let e = _mm_set_epi16(4, 3, 2, 42, 1, 42, 42, 42); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm_maskz_expandloadu_epi16() { + fn test_mm_maskz_expandloadu_epi16() { let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8]; let p = a.as_ptr(); let m = 0b11101000; - let r = _mm_maskz_expandloadu_epi16(m, black_box(p)); + let r = unsafe { _mm_maskz_expandloadu_epi16(m, black_box(p)) }; let e = _mm_set_epi16(4, 3, 2, 0, 1, 0, 0, 0); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512vbmi2")] - unsafe fn test_mm512_mask_expandloadu_epi8() { + fn test_mm512_mask_expandloadu_epi8() { let src = _mm512_set1_epi8(42); let a = &[ 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, @@ -4016,7 +4016,7 @@ mod tests { ]; let p = a.as_ptr(); let m = 0b11101000_11001010_11110000_00001111_11111111_00000000_10101010_01010101; - let r = _mm512_mask_expandloadu_epi8(src, m, black_box(p)); + let r = unsafe { _mm512_mask_expandloadu_epi8(src, m, black_box(p)) }; let e = _mm512_set_epi8( 32, 31, 30, 42, 29, 42, 42, 42, 28, 27, 42, 42, 26, 42, 25, 42, 24, 23, 22, 21, 42, 42, 42, 42, 42, 42, 42, 42, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 42, 42, 42, 42, @@ -4026,7 +4026,7 @@ mod tests { } #[simd_test(enable = "avx512vbmi2")] - unsafe fn test_mm512_maskz_expandloadu_epi8() { + fn test_mm512_maskz_expandloadu_epi8() { let a = &[ 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, @@ -4034,7 +4034,7 @@ mod tests { ]; let p = a.as_ptr(); let m = 0b11101000_11001010_11110000_00001111_11111111_00000000_10101010_01010101; - let r = _mm512_maskz_expandloadu_epi8(m, black_box(p)); + let r = unsafe { _mm512_maskz_expandloadu_epi8(m, black_box(p)) }; let e = _mm512_set_epi8( 32, 31, 30, 0, 29, 0, 0, 0, 28, 27, 0, 0, 26, 0, 25, 0, 24, 23, 22, 21, 0, 0, 0, 0, 0, 0, 0, 0, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, @@ -4044,7 +4044,7 @@ mod tests { } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm256_mask_expandloadu_epi8() { + fn test_mm256_mask_expandloadu_epi8() { let src = _mm256_set1_epi8(42); let a = &[ 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, @@ -4052,7 +4052,7 @@ mod tests { ]; let p = a.as_ptr(); let m = 0b11101000_11001010_11110000_00001111; - let r = _mm256_mask_expandloadu_epi8(src, m, black_box(p)); + let r = unsafe { _mm256_mask_expandloadu_epi8(src, m, black_box(p)) }; let e = _mm256_set_epi8( 16, 15, 14, 42, 13, 42, 42, 42, 12, 11, 42, 42, 10, 42, 9, 42, 8, 7, 6, 5, 42, 42, 42, 42, 42, 42, 42, 42, 4, 3, 2, 1, @@ -4061,14 +4061,14 @@ mod tests { } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm256_maskz_expandloadu_epi8() { + fn test_mm256_maskz_expandloadu_epi8() { let a = &[ 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, ]; let p = a.as_ptr(); let m = 0b11101000_11001010_11110000_00001111; - let r = _mm256_maskz_expandloadu_epi8(m, black_box(p)); + let r = unsafe { _mm256_maskz_expandloadu_epi8(m, black_box(p)) }; let e = _mm256_set_epi8( 16, 15, 14, 0, 13, 0, 0, 0, 12, 11, 0, 0, 10, 0, 9, 0, 8, 7, 6, 5, 0, 0, 0, 0, 0, 0, 0, 0, 4, 3, 2, 1, @@ -4077,36 +4077,44 @@ mod tests { } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm_mask_expandloadu_epi8() { + fn test_mm_mask_expandloadu_epi8() { let src = _mm_set1_epi8(42); let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm_mask_expandloadu_epi8(src, m, black_box(p)); + let r = unsafe { _mm_mask_expandloadu_epi8(src, m, black_box(p)) }; let e = _mm_set_epi8(8, 7, 6, 42, 5, 42, 42, 42, 4, 3, 42, 42, 2, 42, 1, 42); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm_maskz_expandloadu_epi8() { + fn test_mm_maskz_expandloadu_epi8() { let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; let p = a.as_ptr(); let m = 0b11101000_11001010; - let r = _mm_maskz_expandloadu_epi8(m, black_box(p)); + let r = unsafe { _mm_maskz_expandloadu_epi8(m, black_box(p)) }; let e = _mm_set_epi8(8, 7, 6, 0, 5, 0, 0, 0, 4, 3, 0, 0, 2, 0, 1, 0); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512vbmi2")] - unsafe fn test_mm512_mask_compressstoreu_epi16() { + fn test_mm512_mask_compressstoreu_epi16() { let a = _mm512_set_epi16( 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, ); let mut r = [0_i16; 32]; - _mm512_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a); + unsafe { + _mm512_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i16; 32]); - _mm512_mask_compressstoreu_epi16(r.as_mut_ptr(), 0b11110000_11001010_11111111_00000000, a); + unsafe { + _mm512_mask_compressstoreu_epi16( + r.as_mut_ptr(), + 0b11110000_11001010_11111111_00000000, + a, + ); + } assert_eq!( &r, &[ @@ -4117,40 +4125,52 @@ mod tests { } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm256_mask_compressstoreu_epi16() { + fn test_mm256_mask_compressstoreu_epi16() { let a = _mm256_set_epi16(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1); let mut r = [0_i16; 16]; - _mm256_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a); + unsafe { + _mm256_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i16; 16]); - _mm256_mask_compressstoreu_epi16(r.as_mut_ptr(), 0b11110000_11001010, a); + unsafe { + _mm256_mask_compressstoreu_epi16(r.as_mut_ptr(), 0b11110000_11001010, a); + } assert_eq!(&r, &[2, 4, 7, 8, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0]); } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm_mask_compressstoreu_epi16() { + fn test_mm_mask_compressstoreu_epi16() { let a = _mm_set_epi16(8, 7, 6, 5, 4, 3, 2, 1); let mut r = [0_i16; 8]; - _mm_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a); + unsafe { + _mm_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i16; 8]); - _mm_mask_compressstoreu_epi16(r.as_mut_ptr(), 0b11110000, a); + unsafe { + _mm_mask_compressstoreu_epi16(r.as_mut_ptr(), 0b11110000, a); + } assert_eq!(&r, &[5, 6, 7, 8, 0, 0, 0, 0]); } #[simd_test(enable = "avx512vbmi2")] - unsafe fn test_mm512_mask_compressstoreu_epi8() { + fn test_mm512_mask_compressstoreu_epi8() { let a = _mm512_set_epi8( 64, 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, 50, 49, 48, 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, ); let mut r = [0_i8; 64]; - _mm512_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a); + unsafe { + _mm512_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i8; 64]); - _mm512_mask_compressstoreu_epi8( - r.as_mut_ptr(), - 0b11110000_11001010_11111111_00000000_10101010_01010101_11110000_00001111, - a, - ); + unsafe { + _mm512_mask_compressstoreu_epi8( + r.as_mut_ptr(), + 0b11110000_11001010_11111111_00000000_10101010_01010101_11110000_00001111, + a, + ); + } assert_eq!( &r, &[ @@ -4162,15 +4182,23 @@ mod tests { } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm256_mask_compressstoreu_epi8() { + fn test_mm256_mask_compressstoreu_epi8() { let a = _mm256_set_epi8( 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, ); let mut r = [0_i8; 32]; - _mm256_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a); + unsafe { + _mm256_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i8; 32]); - _mm256_mask_compressstoreu_epi8(r.as_mut_ptr(), 0b11110000_11001010_11111111_00000000, a); + unsafe { + _mm256_mask_compressstoreu_epi8( + r.as_mut_ptr(), + 0b11110000_11001010_11111111_00000000, + a, + ); + } assert_eq!( &r, &[ @@ -4181,12 +4209,16 @@ mod tests { } #[simd_test(enable = "avx512vbmi2,avx512vl")] - unsafe fn test_mm_mask_compressstoreu_epi8() { + fn test_mm_mask_compressstoreu_epi8() { let a = _mm_set_epi8(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1); let mut r = [0_i8; 16]; - _mm_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a); + unsafe { + _mm_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a); + } assert_eq!(&r, &[0_i8; 16]); - _mm_mask_compressstoreu_epi8(r.as_mut_ptr(), 0b11110000_11001010, a); + unsafe { + _mm_mask_compressstoreu_epi8(r.as_mut_ptr(), 0b11110000_11001010, a); + } assert_eq!(&r, &[2, 4, 7, 8, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0]); } } diff --git a/library/stdarch/crates/core_arch/src/x86/avxneconvert.rs b/library/stdarch/crates/core_arch/src/x86/avxneconvert.rs index a53d6d97e8a0..91b6be2b09d7 100644 --- a/library/stdarch/crates/core_arch/src/x86/avxneconvert.rs +++ b/library/stdarch/crates/core_arch/src/x86/avxneconvert.rs @@ -242,127 +242,127 @@ mod tests { const BF16_EIGHT: u16 = 0b0_10000010_0000000; #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm_bcstnebf16_ps() { + fn test_mm_bcstnebf16_ps() { let a = bf16::from_bits(BF16_ONE); - let r = _mm_bcstnebf16_ps(addr_of!(a)); + let r = unsafe { _mm_bcstnebf16_ps(addr_of!(a)) }; let e = _mm_set_ps(1., 1., 1., 1.); assert_eq_m128(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm256_bcstnebf16_ps() { + fn test_mm256_bcstnebf16_ps() { let a = bf16::from_bits(BF16_ONE); - let r = _mm256_bcstnebf16_ps(addr_of!(a)); + let r = unsafe { _mm256_bcstnebf16_ps(addr_of!(a)) }; let e = _mm256_set_ps(1., 1., 1., 1., 1., 1., 1., 1.); assert_eq_m256(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm_bcstnesh_ps() { + fn test_mm_bcstnesh_ps() { let a = 1.0_f16; - let r = _mm_bcstnesh_ps(addr_of!(a)); + let r = unsafe { _mm_bcstnesh_ps(addr_of!(a)) }; let e = _mm_set_ps(1., 1., 1., 1.); assert_eq_m128(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm256_bcstnesh_ps() { + fn test_mm256_bcstnesh_ps() { let a = 1.0_f16; - let r = _mm256_bcstnesh_ps(addr_of!(a)); + let r = unsafe { _mm256_bcstnesh_ps(addr_of!(a)) }; let e = _mm256_set_ps(1., 1., 1., 1., 1., 1., 1., 1.); assert_eq_m256(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm_cvtneebf16_ps() { + fn test_mm_cvtneebf16_ps() { let a = __m128bh([ BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT, ]); - let r = _mm_cvtneebf16_ps(addr_of!(a)); + let r = unsafe { _mm_cvtneebf16_ps(addr_of!(a)) }; let e = _mm_setr_ps(1., 3., 5., 7.); assert_eq_m128(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm256_cvtneebf16_ps() { + fn test_mm256_cvtneebf16_ps() { let a = __m256bh([ BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT, BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT, ]); - let r = _mm256_cvtneebf16_ps(addr_of!(a)); + let r = unsafe { _mm256_cvtneebf16_ps(addr_of!(a)) }; let e = _mm256_setr_ps(1., 3., 5., 7., 1., 3., 5., 7.); assert_eq_m256(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm_cvtneeph_ps() { + fn test_mm_cvtneeph_ps() { let a = __m128h([1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0]); - let r = _mm_cvtneeph_ps(addr_of!(a)); + let r = unsafe { _mm_cvtneeph_ps(addr_of!(a)) }; let e = _mm_setr_ps(1., 3., 5., 7.); assert_eq_m128(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm256_cvtneeph_ps() { + fn test_mm256_cvtneeph_ps() { let a = __m256h([ 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, ]); - let r = _mm256_cvtneeph_ps(addr_of!(a)); + let r = unsafe { _mm256_cvtneeph_ps(addr_of!(a)) }; let e = _mm256_setr_ps(1., 3., 5., 7., 9., 11., 13., 15.); assert_eq_m256(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm_cvtneobf16_ps() { + fn test_mm_cvtneobf16_ps() { let a = __m128bh([ BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT, ]); - let r = _mm_cvtneobf16_ps(addr_of!(a)); + let r = unsafe { _mm_cvtneobf16_ps(addr_of!(a)) }; let e = _mm_setr_ps(2., 4., 6., 8.); assert_eq_m128(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm256_cvtneobf16_ps() { + fn test_mm256_cvtneobf16_ps() { let a = __m256bh([ BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT, BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT, ]); - let r = _mm256_cvtneobf16_ps(addr_of!(a)); + let r = unsafe { _mm256_cvtneobf16_ps(addr_of!(a)) }; let e = _mm256_setr_ps(2., 4., 6., 8., 2., 4., 6., 8.); assert_eq_m256(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm_cvtneoph_ps() { + fn test_mm_cvtneoph_ps() { let a = __m128h([1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0]); - let r = _mm_cvtneoph_ps(addr_of!(a)); + let r = unsafe { _mm_cvtneoph_ps(addr_of!(a)) }; let e = _mm_setr_ps(2., 4., 6., 8.); assert_eq_m128(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm256_cvtneoph_ps() { + fn test_mm256_cvtneoph_ps() { let a = __m256h([ 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, ]); - let r = _mm256_cvtneoph_ps(addr_of!(a)); + let r = unsafe { _mm256_cvtneoph_ps(addr_of!(a)) }; let e = _mm256_setr_ps(2., 4., 6., 8., 10., 12., 14., 16.); assert_eq_m256(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm_cvtneps_avx_pbh() { + fn test_mm_cvtneps_avx_pbh() { let a = _mm_setr_ps(1., 2., 3., 4.); - let r: u16x4 = transmute_copy(&_mm_cvtneps_avx_pbh(a)); + let r: u16x4 = unsafe { transmute_copy(&_mm_cvtneps_avx_pbh(a)) }; let e = u16x4::new(BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR); assert_eq!(r, e); } #[simd_test(enable = "avxneconvert")] - unsafe fn test_mm256_cvtneps_avx_pbh() { + fn test_mm256_cvtneps_avx_pbh() { let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.); - let r: u16x8 = transmute(_mm256_cvtneps_avx_pbh(a)); + let r: u16x8 = _mm256_cvtneps_avx_pbh(a).as_u16x8(); let e = u16x8::new( BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT, ); diff --git a/library/stdarch/crates/core_arch/src/x86/f16c.rs b/library/stdarch/crates/core_arch/src/x86/f16c.rs index 0a26a9ff8d25..a0bb992bb9d4 100644 --- a/library/stdarch/crates/core_arch/src/x86/f16c.rs +++ b/library/stdarch/crates/core_arch/src/x86/f16c.rs @@ -106,7 +106,7 @@ pub fn _mm256_cvtps_ph(a: __m256) -> __m128i { #[cfg(test)] mod tests { use crate::core_arch::assert_eq_const as assert_eq; - use crate::{core_arch::x86::*, mem::transmute}; + use crate::core_arch::x86::*; use stdarch_test::simd_test; const F16_ONE: i16 = 0x3c00; diff --git a/library/stdarch/crates/core_arch/src/x86/fxsr.rs b/library/stdarch/crates/core_arch/src/x86/fxsr.rs index 71fd52ca1496..08619efe7c9e 100644 --- a/library/stdarch/crates/core_arch/src/x86/fxsr.rs +++ b/library/stdarch/crates/core_arch/src/x86/fxsr.rs @@ -77,12 +77,14 @@ mod tests { #[simd_test(enable = "fxsr")] #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri - unsafe fn test_fxsave() { + fn test_fxsave() { let mut a = FxsaveArea::new(); let mut b = FxsaveArea::new(); - fxsr::_fxsave(a.ptr()); - fxsr::_fxrstor(a.ptr()); - fxsr::_fxsave(b.ptr()); + unsafe { + fxsr::_fxsave(a.ptr()); + fxsr::_fxrstor(a.ptr()); + fxsr::_fxsave(b.ptr()); + } } } diff --git a/library/stdarch/crates/core_arch/src/x86/gfni.rs b/library/stdarch/crates/core_arch/src/x86/gfni.rs index 681b8ae330d4..e9ee27a7b823 100644 --- a/library/stdarch/crates/core_arch/src/x86/gfni.rs +++ b/library/stdarch/crates/core_arch/src/x86/gfni.rs @@ -898,25 +898,25 @@ mod tests { } #[simd_test(enable = "gfni,avx512f")] - unsafe fn test_mm512_gf2p8mul_epi8() { + fn test_mm512_gf2p8mul_epi8() { let (left, right, expected) = generate_byte_mul_test_data(); for i in 0..NUM_TEST_WORDS_512 { - let left = load_m512i_word(&left, i); - let right = load_m512i_word(&right, i); - let expected = load_m512i_word(&expected, i); + let left = unsafe { load_m512i_word(&left, i) }; + let right = unsafe { load_m512i_word(&right, i) }; + let expected = unsafe { load_m512i_word(&expected, i) }; let result = _mm512_gf2p8mul_epi8(left, right); assert_eq_m512i(result, expected); } } #[simd_test(enable = "gfni,avx512bw")] - unsafe fn test_mm512_maskz_gf2p8mul_epi8() { + fn test_mm512_maskz_gf2p8mul_epi8() { let (left, right, _expected) = generate_byte_mul_test_data(); for i in 0..NUM_TEST_WORDS_512 { - let left = load_m512i_word(&left, i); - let right = load_m512i_word(&right, i); + let left = unsafe { load_m512i_word(&left, i) }; + let right = unsafe { load_m512i_word(&right, i) }; let result_zero = _mm512_maskz_gf2p8mul_epi8(0, left, right); assert_eq_m512i(result_zero, _mm512_setzero_si512()); let mask_bytes: __mmask64 = 0x0F_0F_0F_0F_FF_FF_00_00; @@ -930,12 +930,12 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw")] - unsafe fn test_mm512_mask_gf2p8mul_epi8() { + fn test_mm512_mask_gf2p8mul_epi8() { let (left, right, _expected) = generate_byte_mul_test_data(); for i in 0..NUM_TEST_WORDS_512 { - let left = load_m512i_word(&left, i); - let right = load_m512i_word(&right, i); + let left = unsafe { load_m512i_word(&left, i) }; + let right = unsafe { load_m512i_word(&right, i) }; let result_left = _mm512_mask_gf2p8mul_epi8(left, 0, left, right); assert_eq_m512i(result_left, left); let mask_bytes: __mmask64 = 0x0F_0F_0F_0F_FF_FF_00_00; @@ -948,25 +948,25 @@ mod tests { } #[simd_test(enable = "gfni,avx")] - unsafe fn test_mm256_gf2p8mul_epi8() { + fn test_mm256_gf2p8mul_epi8() { let (left, right, expected) = generate_byte_mul_test_data(); for i in 0..NUM_TEST_WORDS_256 { - let left = load_m256i_word(&left, i); - let right = load_m256i_word(&right, i); - let expected = load_m256i_word(&expected, i); + let left = unsafe { load_m256i_word(&left, i) }; + let right = unsafe { load_m256i_word(&right, i) }; + let expected = unsafe { load_m256i_word(&expected, i) }; let result = _mm256_gf2p8mul_epi8(left, right); assert_eq_m256i(result, expected); } } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm256_maskz_gf2p8mul_epi8() { + fn test_mm256_maskz_gf2p8mul_epi8() { let (left, right, _expected) = generate_byte_mul_test_data(); for i in 0..NUM_TEST_WORDS_256 { - let left = load_m256i_word(&left, i); - let right = load_m256i_word(&right, i); + let left = unsafe { load_m256i_word(&left, i) }; + let right = unsafe { load_m256i_word(&right, i) }; let result_zero = _mm256_maskz_gf2p8mul_epi8(0, left, right); assert_eq_m256i(result_zero, _mm256_setzero_si256()); let mask_bytes: __mmask32 = 0x0F_F0_FF_00; @@ -980,12 +980,12 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm256_mask_gf2p8mul_epi8() { + fn test_mm256_mask_gf2p8mul_epi8() { let (left, right, _expected) = generate_byte_mul_test_data(); for i in 0..NUM_TEST_WORDS_256 { - let left = load_m256i_word(&left, i); - let right = load_m256i_word(&right, i); + let left = unsafe { load_m256i_word(&left, i) }; + let right = unsafe { load_m256i_word(&right, i) }; let result_left = _mm256_mask_gf2p8mul_epi8(left, 0, left, right); assert_eq_m256i(result_left, left); let mask_bytes: __mmask32 = 0x0F_F0_FF_00; @@ -998,25 +998,25 @@ mod tests { } #[simd_test(enable = "gfni")] - unsafe fn test_mm_gf2p8mul_epi8() { + fn test_mm_gf2p8mul_epi8() { let (left, right, expected) = generate_byte_mul_test_data(); for i in 0..NUM_TEST_WORDS_128 { - let left = load_m128i_word(&left, i); - let right = load_m128i_word(&right, i); - let expected = load_m128i_word(&expected, i); + let left = unsafe { load_m128i_word(&left, i) }; + let right = unsafe { load_m128i_word(&right, i) }; + let expected = unsafe { load_m128i_word(&expected, i) }; let result = _mm_gf2p8mul_epi8(left, right); assert_eq_m128i(result, expected); } } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm_maskz_gf2p8mul_epi8() { + fn test_mm_maskz_gf2p8mul_epi8() { let (left, right, _expected) = generate_byte_mul_test_data(); for i in 0..NUM_TEST_WORDS_128 { - let left = load_m128i_word(&left, i); - let right = load_m128i_word(&right, i); + let left = unsafe { load_m128i_word(&left, i) }; + let right = unsafe { load_m128i_word(&right, i) }; let result_zero = _mm_maskz_gf2p8mul_epi8(0, left, right); assert_eq_m128i(result_zero, _mm_setzero_si128()); let mask_bytes: __mmask16 = 0x0F_F0; @@ -1030,12 +1030,12 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm_mask_gf2p8mul_epi8() { + fn test_mm_mask_gf2p8mul_epi8() { let (left, right, _expected) = generate_byte_mul_test_data(); for i in 0..NUM_TEST_WORDS_128 { - let left = load_m128i_word(&left, i); - let right = load_m128i_word(&right, i); + let left = unsafe { load_m128i_word(&left, i) }; + let right = unsafe { load_m128i_word(&right, i) }; let result_left = _mm_mask_gf2p8mul_epi8(left, 0, left, right); assert_eq_m128i(result_left, left); let mask_bytes: __mmask16 = 0x0F_F0; @@ -1048,7 +1048,7 @@ mod tests { } #[simd_test(enable = "gfni,avx512f")] - unsafe fn test_mm512_gf2p8affine_epi64_epi8() { + fn test_mm512_gf2p8affine_epi64_epi8() { let identity: i64 = 0x01_02_04_08_10_20_40_80; const IDENTITY_BYTE: i32 = 0; let constant: i64 = 0; @@ -1061,20 +1061,20 @@ mod tests { let (matrices, vectors, references) = generate_affine_mul_test_data(IDENTITY_BYTE as u8); for i in 0..NUM_TEST_WORDS_512 { - let data = load_m512i_word(&bytes, i); + let data = unsafe { load_m512i_word(&bytes, i) }; let result = _mm512_gf2p8affine_epi64_epi8::(data, identity); assert_eq_m512i(result, data); let result = _mm512_gf2p8affine_epi64_epi8::(data, constant); assert_eq_m512i(result, constant_reference); - let data = load_m512i_word(&more_bytes, i); + let data = unsafe { load_m512i_word(&more_bytes, i) }; let result = _mm512_gf2p8affine_epi64_epi8::(data, identity); assert_eq_m512i(result, data); let result = _mm512_gf2p8affine_epi64_epi8::(data, constant); assert_eq_m512i(result, constant_reference); - let matrix = load_m512i_word(&matrices, i); - let vector = load_m512i_word(&vectors, i); - let reference = load_m512i_word(&references, i); + let matrix = unsafe { load_m512i_word(&matrices, i) }; + let vector = unsafe { load_m512i_word(&vectors, i) }; + let reference = unsafe { load_m512i_word(&references, i) }; let result = _mm512_gf2p8affine_epi64_epi8::(vector, matrix); assert_eq_m512i(result, reference); @@ -1082,13 +1082,13 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw")] - unsafe fn test_mm512_maskz_gf2p8affine_epi64_epi8() { + fn test_mm512_maskz_gf2p8affine_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_512 { - let matrix = load_m512i_word(&matrices, i); - let vector = load_m512i_word(&vectors, i); + let matrix = unsafe { load_m512i_word(&matrices, i) }; + let vector = unsafe { load_m512i_word(&vectors, i) }; let result_zero = _mm512_maskz_gf2p8affine_epi64_epi8::(0, vector, matrix); assert_eq_m512i(result_zero, _mm512_setzero_si512()); @@ -1104,13 +1104,13 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw")] - unsafe fn test_mm512_mask_gf2p8affine_epi64_epi8() { + fn test_mm512_mask_gf2p8affine_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_512 { - let left = load_m512i_word(&vectors, i); - let right = load_m512i_word(&matrices, i); + let left = unsafe { load_m512i_word(&vectors, i) }; + let right = unsafe { load_m512i_word(&matrices, i) }; let result_left = _mm512_mask_gf2p8affine_epi64_epi8::(left, 0, left, right); assert_eq_m512i(result_left, left); @@ -1125,7 +1125,7 @@ mod tests { } #[simd_test(enable = "gfni,avx")] - unsafe fn test_mm256_gf2p8affine_epi64_epi8() { + fn test_mm256_gf2p8affine_epi64_epi8() { let identity: i64 = 0x01_02_04_08_10_20_40_80; const IDENTITY_BYTE: i32 = 0; let constant: i64 = 0; @@ -1138,20 +1138,20 @@ mod tests { let (matrices, vectors, references) = generate_affine_mul_test_data(IDENTITY_BYTE as u8); for i in 0..NUM_TEST_WORDS_256 { - let data = load_m256i_word(&bytes, i); + let data = unsafe { load_m256i_word(&bytes, i) }; let result = _mm256_gf2p8affine_epi64_epi8::(data, identity); assert_eq_m256i(result, data); let result = _mm256_gf2p8affine_epi64_epi8::(data, constant); assert_eq_m256i(result, constant_reference); - let data = load_m256i_word(&more_bytes, i); + let data = unsafe { load_m256i_word(&more_bytes, i) }; let result = _mm256_gf2p8affine_epi64_epi8::(data, identity); assert_eq_m256i(result, data); let result = _mm256_gf2p8affine_epi64_epi8::(data, constant); assert_eq_m256i(result, constant_reference); - let matrix = load_m256i_word(&matrices, i); - let vector = load_m256i_word(&vectors, i); - let reference = load_m256i_word(&references, i); + let matrix = unsafe { load_m256i_word(&matrices, i) }; + let vector = unsafe { load_m256i_word(&vectors, i) }; + let reference = unsafe { load_m256i_word(&references, i) }; let result = _mm256_gf2p8affine_epi64_epi8::(vector, matrix); assert_eq_m256i(result, reference); @@ -1159,13 +1159,13 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm256_maskz_gf2p8affine_epi64_epi8() { + fn test_mm256_maskz_gf2p8affine_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_256 { - let matrix = load_m256i_word(&matrices, i); - let vector = load_m256i_word(&vectors, i); + let matrix = unsafe { load_m256i_word(&matrices, i) }; + let vector = unsafe { load_m256i_word(&vectors, i) }; let result_zero = _mm256_maskz_gf2p8affine_epi64_epi8::(0, vector, matrix); assert_eq_m256i(result_zero, _mm256_setzero_si256()); @@ -1181,13 +1181,13 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm256_mask_gf2p8affine_epi64_epi8() { + fn test_mm256_mask_gf2p8affine_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_256 { - let left = load_m256i_word(&vectors, i); - let right = load_m256i_word(&matrices, i); + let left = unsafe { load_m256i_word(&vectors, i) }; + let right = unsafe { load_m256i_word(&matrices, i) }; let result_left = _mm256_mask_gf2p8affine_epi64_epi8::(left, 0, left, right); assert_eq_m256i(result_left, left); @@ -1202,7 +1202,7 @@ mod tests { } #[simd_test(enable = "gfni")] - unsafe fn test_mm_gf2p8affine_epi64_epi8() { + fn test_mm_gf2p8affine_epi64_epi8() { let identity: i64 = 0x01_02_04_08_10_20_40_80; const IDENTITY_BYTE: i32 = 0; let constant: i64 = 0; @@ -1215,20 +1215,20 @@ mod tests { let (matrices, vectors, references) = generate_affine_mul_test_data(IDENTITY_BYTE as u8); for i in 0..NUM_TEST_WORDS_128 { - let data = load_m128i_word(&bytes, i); + let data = unsafe { load_m128i_word(&bytes, i) }; let result = _mm_gf2p8affine_epi64_epi8::(data, identity); assert_eq_m128i(result, data); let result = _mm_gf2p8affine_epi64_epi8::(data, constant); assert_eq_m128i(result, constant_reference); - let data = load_m128i_word(&more_bytes, i); + let data = unsafe { load_m128i_word(&more_bytes, i) }; let result = _mm_gf2p8affine_epi64_epi8::(data, identity); assert_eq_m128i(result, data); let result = _mm_gf2p8affine_epi64_epi8::(data, constant); assert_eq_m128i(result, constant_reference); - let matrix = load_m128i_word(&matrices, i); - let vector = load_m128i_word(&vectors, i); - let reference = load_m128i_word(&references, i); + let matrix = unsafe { load_m128i_word(&matrices, i) }; + let vector = unsafe { load_m128i_word(&vectors, i) }; + let reference = unsafe { load_m128i_word(&references, i) }; let result = _mm_gf2p8affine_epi64_epi8::(vector, matrix); assert_eq_m128i(result, reference); @@ -1236,13 +1236,13 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm_maskz_gf2p8affine_epi64_epi8() { + fn test_mm_maskz_gf2p8affine_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_128 { - let matrix = load_m128i_word(&matrices, i); - let vector = load_m128i_word(&vectors, i); + let matrix = unsafe { load_m128i_word(&matrices, i) }; + let vector = unsafe { load_m128i_word(&vectors, i) }; let result_zero = _mm_maskz_gf2p8affine_epi64_epi8::(0, vector, matrix); assert_eq_m128i(result_zero, _mm_setzero_si128()); let mask_bytes: __mmask16 = 0x0F_F0; @@ -1257,13 +1257,13 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm_mask_gf2p8affine_epi64_epi8() { + fn test_mm_mask_gf2p8affine_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_128 { - let left = load_m128i_word(&vectors, i); - let right = load_m128i_word(&matrices, i); + let left = unsafe { load_m128i_word(&vectors, i) }; + let right = unsafe { load_m128i_word(&matrices, i) }; let result_left = _mm_mask_gf2p8affine_epi64_epi8::(left, 0, left, right); assert_eq_m128i(result_left, left); @@ -1278,7 +1278,7 @@ mod tests { } #[simd_test(enable = "gfni,avx512f")] - unsafe fn test_mm512_gf2p8affineinv_epi64_epi8() { + fn test_mm512_gf2p8affineinv_epi64_epi8() { let identity: i64 = 0x01_02_04_08_10_20_40_80; const IDENTITY_BYTE: i32 = 0; const CONSTANT_BYTE: i32 = 0x63; @@ -1288,8 +1288,8 @@ mod tests { let (inputs, results) = generate_inv_tests_data(); for i in 0..NUM_BYTES_WORDS_512 { - let input = load_m512i_word(&inputs, i); - let reference = load_m512i_word(&results, i); + let input = unsafe { load_m512i_word(&inputs, i) }; + let reference = unsafe { load_m512i_word(&results, i) }; let result = _mm512_gf2p8affineinv_epi64_epi8::(input, identity); let remultiplied = _mm512_gf2p8mul_epi8(result, input); assert_eq_m512i(remultiplied, reference); @@ -1300,8 +1300,8 @@ mod tests { generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_512 { - let vector = load_m512i_word(&vectors, i); - let matrix = load_m512i_word(&matrices, i); + let vector = unsafe { load_m512i_word(&vectors, i) }; + let matrix = unsafe { load_m512i_word(&matrices, i) }; let inv_vec = _mm512_gf2p8affineinv_epi64_epi8::(vector, identity); let reference = _mm512_gf2p8affine_epi64_epi8::(inv_vec, matrix); @@ -1314,21 +1314,21 @@ mod tests { let sbox_matrix = _mm512_set1_epi64(AES_S_BOX_MATRIX); for i in 0..NUM_BYTES_WORDS_512 { - let reference = load_m512i_word(&AES_S_BOX, i); - let input = load_m512i_word(&inputs, i); + let reference = unsafe { load_m512i_word(&AES_S_BOX, i) }; + let input = unsafe { load_m512i_word(&inputs, i) }; let result = _mm512_gf2p8affineinv_epi64_epi8::(input, sbox_matrix); assert_eq_m512i(result, reference); } } #[simd_test(enable = "gfni,avx512bw")] - unsafe fn test_mm512_maskz_gf2p8affineinv_epi64_epi8() { + fn test_mm512_maskz_gf2p8affineinv_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_512 { - let matrix = load_m512i_word(&matrices, i); - let vector = load_m512i_word(&vectors, i); + let matrix = unsafe { load_m512i_word(&matrices, i) }; + let vector = unsafe { load_m512i_word(&vectors, i) }; let result_zero = _mm512_maskz_gf2p8affineinv_epi64_epi8::(0, vector, matrix); assert_eq_m512i(result_zero, _mm512_setzero_si512()); @@ -1344,13 +1344,13 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw")] - unsafe fn test_mm512_mask_gf2p8affineinv_epi64_epi8() { + fn test_mm512_mask_gf2p8affineinv_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_512 { - let left = load_m512i_word(&vectors, i); - let right = load_m512i_word(&matrices, i); + let left = unsafe { load_m512i_word(&vectors, i) }; + let right = unsafe { load_m512i_word(&matrices, i) }; let result_left = _mm512_mask_gf2p8affineinv_epi64_epi8::(left, 0, left, right); assert_eq_m512i(result_left, left); @@ -1366,7 +1366,7 @@ mod tests { } #[simd_test(enable = "gfni,avx")] - unsafe fn test_mm256_gf2p8affineinv_epi64_epi8() { + fn test_mm256_gf2p8affineinv_epi64_epi8() { let identity: i64 = 0x01_02_04_08_10_20_40_80; const IDENTITY_BYTE: i32 = 0; const CONSTANT_BYTE: i32 = 0x63; @@ -1376,8 +1376,8 @@ mod tests { let (inputs, results) = generate_inv_tests_data(); for i in 0..NUM_BYTES_WORDS_256 { - let input = load_m256i_word(&inputs, i); - let reference = load_m256i_word(&results, i); + let input = unsafe { load_m256i_word(&inputs, i) }; + let reference = unsafe { load_m256i_word(&results, i) }; let result = _mm256_gf2p8affineinv_epi64_epi8::(input, identity); let remultiplied = _mm256_gf2p8mul_epi8(result, input); assert_eq_m256i(remultiplied, reference); @@ -1388,8 +1388,8 @@ mod tests { generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_256 { - let vector = load_m256i_word(&vectors, i); - let matrix = load_m256i_word(&matrices, i); + let vector = unsafe { load_m256i_word(&vectors, i) }; + let matrix = unsafe { load_m256i_word(&matrices, i) }; let inv_vec = _mm256_gf2p8affineinv_epi64_epi8::(vector, identity); let reference = _mm256_gf2p8affine_epi64_epi8::(inv_vec, matrix); @@ -1402,21 +1402,21 @@ mod tests { let sbox_matrix = _mm256_set1_epi64x(AES_S_BOX_MATRIX); for i in 0..NUM_BYTES_WORDS_256 { - let reference = load_m256i_word(&AES_S_BOX, i); - let input = load_m256i_word(&inputs, i); + let reference = unsafe { load_m256i_word(&AES_S_BOX, i) }; + let input = unsafe { load_m256i_word(&inputs, i) }; let result = _mm256_gf2p8affineinv_epi64_epi8::(input, sbox_matrix); assert_eq_m256i(result, reference); } } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm256_maskz_gf2p8affineinv_epi64_epi8() { + fn test_mm256_maskz_gf2p8affineinv_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_256 { - let matrix = load_m256i_word(&matrices, i); - let vector = load_m256i_word(&vectors, i); + let matrix = unsafe { load_m256i_word(&matrices, i) }; + let vector = unsafe { load_m256i_word(&vectors, i) }; let result_zero = _mm256_maskz_gf2p8affineinv_epi64_epi8::(0, vector, matrix); assert_eq_m256i(result_zero, _mm256_setzero_si256()); @@ -1432,13 +1432,13 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm256_mask_gf2p8affineinv_epi64_epi8() { + fn test_mm256_mask_gf2p8affineinv_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_256 { - let left = load_m256i_word(&vectors, i); - let right = load_m256i_word(&matrices, i); + let left = unsafe { load_m256i_word(&vectors, i) }; + let right = unsafe { load_m256i_word(&matrices, i) }; let result_left = _mm256_mask_gf2p8affineinv_epi64_epi8::(left, 0, left, right); assert_eq_m256i(result_left, left); @@ -1454,7 +1454,7 @@ mod tests { } #[simd_test(enable = "gfni")] - unsafe fn test_mm_gf2p8affineinv_epi64_epi8() { + fn test_mm_gf2p8affineinv_epi64_epi8() { let identity: i64 = 0x01_02_04_08_10_20_40_80; const IDENTITY_BYTE: i32 = 0; const CONSTANT_BYTE: i32 = 0x63; @@ -1464,8 +1464,8 @@ mod tests { let (inputs, results) = generate_inv_tests_data(); for i in 0..NUM_BYTES_WORDS_128 { - let input = load_m128i_word(&inputs, i); - let reference = load_m128i_word(&results, i); + let input = unsafe { load_m128i_word(&inputs, i) }; + let reference = unsafe { load_m128i_word(&results, i) }; let result = _mm_gf2p8affineinv_epi64_epi8::(input, identity); let remultiplied = _mm_gf2p8mul_epi8(result, input); assert_eq_m128i(remultiplied, reference); @@ -1476,8 +1476,8 @@ mod tests { generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_128 { - let vector = load_m128i_word(&vectors, i); - let matrix = load_m128i_word(&matrices, i); + let vector = unsafe { load_m128i_word(&vectors, i) }; + let matrix = unsafe { load_m128i_word(&matrices, i) }; let inv_vec = _mm_gf2p8affineinv_epi64_epi8::(vector, identity); let reference = _mm_gf2p8affine_epi64_epi8::(inv_vec, matrix); @@ -1490,21 +1490,21 @@ mod tests { let sbox_matrix = _mm_set1_epi64x(AES_S_BOX_MATRIX); for i in 0..NUM_BYTES_WORDS_128 { - let reference = load_m128i_word(&AES_S_BOX, i); - let input = load_m128i_word(&inputs, i); + let reference = unsafe { load_m128i_word(&AES_S_BOX, i) }; + let input = unsafe { load_m128i_word(&inputs, i) }; let result = _mm_gf2p8affineinv_epi64_epi8::(input, sbox_matrix); assert_eq_m128i(result, reference); } } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm_maskz_gf2p8affineinv_epi64_epi8() { + fn test_mm_maskz_gf2p8affineinv_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_128 { - let matrix = load_m128i_word(&matrices, i); - let vector = load_m128i_word(&vectors, i); + let matrix = unsafe { load_m128i_word(&matrices, i) }; + let vector = unsafe { load_m128i_word(&vectors, i) }; let result_zero = _mm_maskz_gf2p8affineinv_epi64_epi8::(0, vector, matrix); assert_eq_m128i(result_zero, _mm_setzero_si128()); @@ -1520,13 +1520,13 @@ mod tests { } #[simd_test(enable = "gfni,avx512bw,avx512vl")] - unsafe fn test_mm_mask_gf2p8affineinv_epi64_epi8() { + fn test_mm_mask_gf2p8affineinv_epi64_epi8() { const CONSTANT_BYTE: i32 = 0x63; let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8); for i in 0..NUM_TEST_WORDS_128 { - let left = load_m128i_word(&vectors, i); - let right = load_m128i_word(&matrices, i); + let left = unsafe { load_m128i_word(&vectors, i) }; + let right = unsafe { load_m128i_word(&matrices, i) }; let result_left = _mm_mask_gf2p8affineinv_epi64_epi8::(left, 0, left, right); assert_eq_m128i(result_left, left); diff --git a/library/stdarch/crates/core_arch/src/x86/kl.rs b/library/stdarch/crates/core_arch/src/x86/kl.rs index 26e5a46c6293..7cb52847f50d 100644 --- a/library/stdarch/crates/core_arch/src/x86/kl.rs +++ b/library/stdarch/crates/core_arch/src/x86/kl.rs @@ -352,45 +352,47 @@ mod tests { use stdarch_test::simd_test; #[target_feature(enable = "kl")] - unsafe fn encodekey128() -> [u8; 48] { + fn encodekey128() -> [u8; 48] { let mut handle = [0; 48]; - let _ = _mm_encodekey128_u32(0, _mm_setzero_si128(), handle.as_mut_ptr()); + let _ = unsafe { _mm_encodekey128_u32(0, _mm_setzero_si128(), handle.as_mut_ptr()) }; handle } #[target_feature(enable = "kl")] - unsafe fn encodekey256() -> [u8; 64] { + fn encodekey256() -> [u8; 64] { let mut handle = [0; 64]; - let _ = _mm_encodekey256_u32( - 0, - _mm_setzero_si128(), - _mm_setzero_si128(), - handle.as_mut_ptr(), - ); + let _ = unsafe { + _mm_encodekey256_u32( + 0, + _mm_setzero_si128(), + _mm_setzero_si128(), + handle.as_mut_ptr(), + ) + }; handle } #[simd_test(enable = "kl")] - unsafe fn test_mm_encodekey128_u32() { + fn test_mm_encodekey128_u32() { encodekey128(); } #[simd_test(enable = "kl")] - unsafe fn test_mm_encodekey256_u32() { + fn test_mm_encodekey256_u32() { encodekey256(); } #[simd_test(enable = "kl")] - unsafe fn test_mm_aesenc128kl_u8() { + fn test_mm_aesenc128kl_u8() { let mut buffer = _mm_setzero_si128(); let key = encodekey128(); for _ in 0..100 { - let status = _mm_aesenc128kl_u8(&mut buffer, buffer, key.as_ptr()); + let status = unsafe { _mm_aesenc128kl_u8(&mut buffer, buffer, key.as_ptr()) }; assert_eq!(status, 0); } for _ in 0..100 { - let status = _mm_aesdec128kl_u8(&mut buffer, buffer, key.as_ptr()); + let status = unsafe { _mm_aesdec128kl_u8(&mut buffer, buffer, key.as_ptr()) }; assert_eq!(status, 0); } @@ -398,16 +400,16 @@ mod tests { } #[simd_test(enable = "kl")] - unsafe fn test_mm_aesdec128kl_u8() { + fn test_mm_aesdec128kl_u8() { let mut buffer = _mm_setzero_si128(); let key = encodekey128(); for _ in 0..100 { - let status = _mm_aesdec128kl_u8(&mut buffer, buffer, key.as_ptr()); + let status = unsafe { _mm_aesdec128kl_u8(&mut buffer, buffer, key.as_ptr()) }; assert_eq!(status, 0); } for _ in 0..100 { - let status = _mm_aesenc128kl_u8(&mut buffer, buffer, key.as_ptr()); + let status = unsafe { _mm_aesenc128kl_u8(&mut buffer, buffer, key.as_ptr()) }; assert_eq!(status, 0); } @@ -415,16 +417,16 @@ mod tests { } #[simd_test(enable = "kl")] - unsafe fn test_mm_aesenc256kl_u8() { + fn test_mm_aesenc256kl_u8() { let mut buffer = _mm_setzero_si128(); let key = encodekey256(); for _ in 0..100 { - let status = _mm_aesenc256kl_u8(&mut buffer, buffer, key.as_ptr()); + let status = unsafe { _mm_aesenc256kl_u8(&mut buffer, buffer, key.as_ptr()) }; assert_eq!(status, 0); } for _ in 0..100 { - let status = _mm_aesdec256kl_u8(&mut buffer, buffer, key.as_ptr()); + let status = unsafe { _mm_aesdec256kl_u8(&mut buffer, buffer, key.as_ptr()) }; assert_eq!(status, 0); } @@ -432,16 +434,16 @@ mod tests { } #[simd_test(enable = "kl")] - unsafe fn test_mm_aesdec256kl_u8() { + fn test_mm_aesdec256kl_u8() { let mut buffer = _mm_setzero_si128(); let key = encodekey256(); for _ in 0..100 { - let status = _mm_aesdec256kl_u8(&mut buffer, buffer, key.as_ptr()); + let status = unsafe { _mm_aesdec256kl_u8(&mut buffer, buffer, key.as_ptr()) }; assert_eq!(status, 0); } for _ in 0..100 { - let status = _mm_aesenc256kl_u8(&mut buffer, buffer, key.as_ptr()); + let status = unsafe { _mm_aesenc256kl_u8(&mut buffer, buffer, key.as_ptr()) }; assert_eq!(status, 0); } @@ -449,16 +451,20 @@ mod tests { } #[simd_test(enable = "widekl")] - unsafe fn test_mm_aesencwide128kl_u8() { + fn test_mm_aesencwide128kl_u8() { let mut buffer = [_mm_setzero_si128(); 8]; let key = encodekey128(); for _ in 0..100 { - let status = _mm_aesencwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()); + let status = unsafe { + _mm_aesencwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()) + }; assert_eq!(status, 0); } for _ in 0..100 { - let status = _mm_aesdecwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()); + let status = unsafe { + _mm_aesdecwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()) + }; assert_eq!(status, 0); } @@ -468,16 +474,20 @@ mod tests { } #[simd_test(enable = "widekl")] - unsafe fn test_mm_aesdecwide128kl_u8() { + fn test_mm_aesdecwide128kl_u8() { let mut buffer = [_mm_setzero_si128(); 8]; let key = encodekey128(); for _ in 0..100 { - let status = _mm_aesdecwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()); + let status = unsafe { + _mm_aesdecwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()) + }; assert_eq!(status, 0); } for _ in 0..100 { - let status = _mm_aesencwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()); + let status = unsafe { + _mm_aesencwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()) + }; assert_eq!(status, 0); } @@ -487,16 +497,20 @@ mod tests { } #[simd_test(enable = "widekl")] - unsafe fn test_mm_aesencwide256kl_u8() { + fn test_mm_aesencwide256kl_u8() { let mut buffer = [_mm_setzero_si128(); 8]; let key = encodekey256(); for _ in 0..100 { - let status = _mm_aesencwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()); + let status = unsafe { + _mm_aesencwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()) + }; assert_eq!(status, 0); } for _ in 0..100 { - let status = _mm_aesdecwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()); + let status = unsafe { + _mm_aesdecwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()) + }; assert_eq!(status, 0); } @@ -506,16 +520,20 @@ mod tests { } #[simd_test(enable = "widekl")] - unsafe fn test_mm_aesdecwide256kl_u8() { + fn test_mm_aesdecwide256kl_u8() { let mut buffer = [_mm_setzero_si128(); 8]; let key = encodekey256(); for _ in 0..100 { - let status = _mm_aesdecwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()); + let status = unsafe { + _mm_aesdecwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()) + }; assert_eq!(status, 0); } for _ in 0..100 { - let status = _mm_aesencwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()); + let status = unsafe { + _mm_aesencwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr()) + }; assert_eq!(status, 0); } diff --git a/library/stdarch/crates/core_arch/src/x86/rtm.rs b/library/stdarch/crates/core_arch/src/x86/rtm.rs index b37e7571eb8f..c88bd6592d78 100644 --- a/library/stdarch/crates/core_arch/src/x86/rtm.rs +++ b/library/stdarch/crates/core_arch/src/x86/rtm.rs @@ -120,13 +120,15 @@ mod tests { use crate::core_arch::x86::*; #[simd_test(enable = "rtm")] - unsafe fn test_xbegin() { + fn test_xbegin() { let mut x = 0; for _ in 0..10 { - let code = _xbegin(); + let code = unsafe { _xbegin() }; if code == _XBEGIN_STARTED { x += 1; - _xend(); + unsafe { + _xend(); + } assert_eq!(x, 1); break; } @@ -135,19 +137,23 @@ mod tests { } #[simd_test(enable = "rtm")] - unsafe fn test_xabort() { + fn test_xabort() { const ABORT_CODE: u32 = 42; // aborting outside a transactional region does nothing - _xabort::(); + unsafe { + _xabort::(); + } for _ in 0..10 { let mut x = 0; - let code = rtm::_xbegin(); + let code = unsafe { _xbegin() }; if code == _XBEGIN_STARTED { x += 1; - rtm::_xabort::(); + unsafe { + _xabort::(); + } } else if code & _XABORT_EXPLICIT != 0 { - let test_abort_code = rtm::_xabort_code(code); + let test_abort_code = _xabort_code(code); assert_eq!(test_abort_code, ABORT_CODE); } assert_eq!(x, 0); @@ -155,14 +161,16 @@ mod tests { } #[simd_test(enable = "rtm")] - unsafe fn test_xtest() { - assert_eq!(_xtest(), 0); + fn test_xtest() { + assert_eq!(unsafe { _xtest() }, 0); for _ in 0..10 { - let code = rtm::_xbegin(); + let code = unsafe { _xbegin() }; if code == _XBEGIN_STARTED { - let in_tx = _xtest(); - rtm::_xend(); + let in_tx = unsafe { _xtest() }; + unsafe { + _xend(); + } // putting the assert inside the transaction would abort the transaction on fail // without any output/panic/etc diff --git a/library/stdarch/crates/core_arch/src/x86/sse.rs b/library/stdarch/crates/core_arch/src/x86/sse.rs index 38b309c1cb79..b83274e60e72 100644 --- a/library/stdarch/crates/core_arch/src/x86/sse.rs +++ b/library/stdarch/crates/core_arch/src/x86/sse.rs @@ -3147,21 +3147,21 @@ mod tests { } #[simd_test(enable = "sse")] - const unsafe fn test_mm_load_ss() { + const fn test_mm_load_ss() { let a = 42.0f32; - let r = _mm_load_ss(ptr::addr_of!(a)); + let r = unsafe { _mm_load_ss(ptr::addr_of!(a)) }; assert_eq_m128(r, _mm_setr_ps(42.0, 0.0, 0.0, 0.0)); } #[simd_test(enable = "sse")] - const unsafe fn test_mm_load1_ps() { + const fn test_mm_load1_ps() { let a = 42.0f32; - let r = _mm_load1_ps(ptr::addr_of!(a)); + let r = unsafe { _mm_load1_ps(ptr::addr_of!(a)) }; assert_eq_m128(r, _mm_setr_ps(42.0, 42.0, 42.0, 42.0)); } #[simd_test(enable = "sse")] - const unsafe fn test_mm_load_ps() { + const fn test_mm_load_ps() { let vals = Memory { data: [1.0f32, 2.0, 3.0, 4.0], }; @@ -3169,21 +3169,21 @@ mod tests { // guaranteed to be aligned to 16 bytes let p = vals.data.as_ptr(); - let r = _mm_load_ps(p); + let r = unsafe { _mm_load_ps(p) }; let e = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); assert_eq_m128(r, e); } #[simd_test(enable = "sse")] - const unsafe fn test_mm_loadu_ps() { + const fn test_mm_loadu_ps() { let vals = &[1.0f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0]; - let p = vals.as_ptr().add(3); - let r = _mm_loadu_ps(black_box(p)); + let p = unsafe { vals.as_ptr().add(3) }; + let r = unsafe { _mm_loadu_ps(black_box(p)) }; assert_eq_m128(r, _mm_setr_ps(4.0, 5.0, 6.0, 7.0)); } #[simd_test(enable = "sse")] - const unsafe fn test_mm_loadr_ps() { + const fn test_mm_loadr_ps() { let vals = Memory { data: [1.0f32, 2.0, 3.0, 4.0], }; @@ -3191,16 +3191,18 @@ mod tests { // guaranteed to be aligned to 16 bytes let p = vals.data.as_ptr(); - let r = _mm_loadr_ps(p); + let r = unsafe { _mm_loadr_ps(p) }; let e = _mm_setr_ps(4.0, 3.0, 2.0, 1.0); assert_eq_m128(r, e); } #[simd_test(enable = "sse")] - const unsafe fn test_mm_store_ss() { + const fn test_mm_store_ss() { let mut vals = [0.0f32; 8]; let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); - _mm_store_ss(vals.as_mut_ptr().add(1), a); + unsafe { + _mm_store_ss(vals.as_mut_ptr().add(1), a); + } assert_eq!(vals[0], 0.0); assert_eq!(vals[1], 1.0); @@ -3208,46 +3210,52 @@ mod tests { } #[simd_test(enable = "sse")] - const unsafe fn test_mm_store1_ps() { + const fn test_mm_store1_ps() { let mut vals = Memory { data: [0.0f32; 4] }; let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); // guaranteed to be aligned to 16 bytes let p = vals.data.as_mut_ptr(); - _mm_store1_ps(p, *black_box(&a)); + unsafe { + _mm_store1_ps(p, *black_box(&a)); + } assert_eq!(vals.data, [1.0, 1.0, 1.0, 1.0]); } #[simd_test(enable = "sse")] - const unsafe fn test_mm_store_ps() { + const fn test_mm_store_ps() { let mut vals = Memory { data: [0.0f32; 4] }; let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); // guaranteed to be aligned to 16 bytes let p = vals.data.as_mut_ptr(); - _mm_store_ps(p, *black_box(&a)); + unsafe { + _mm_store_ps(p, *black_box(&a)); + } assert_eq!(vals.data, [1.0, 2.0, 3.0, 4.0]); } #[simd_test(enable = "sse")] - const unsafe fn test_mm_storer_ps() { + const fn test_mm_storer_ps() { let mut vals = Memory { data: [0.0f32; 4] }; let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); // guaranteed to be aligned to 16 bytes let p = vals.data.as_mut_ptr(); - _mm_storer_ps(p, *black_box(&a)); + unsafe { + _mm_storer_ps(p, *black_box(&a)); + } assert_eq!(vals.data, [4.0, 3.0, 2.0, 1.0]); } #[simd_test(enable = "sse")] - const unsafe fn test_mm_storeu_ps() { + const fn test_mm_storeu_ps() { #[repr(align(16))] struct Memory8 { data: [f32; 8], @@ -3258,9 +3266,11 @@ mod tests { let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); // guaranteed to be *not* aligned to 16 bytes - let p = vals.data.as_mut_ptr().offset(1); + let p = unsafe { vals.data.as_mut_ptr().offset(1) }; - _mm_storeu_ps(p, *black_box(&a)); + unsafe { + _mm_storeu_ps(p, *black_box(&a)); + } assert_eq!(vals.data, [0.0, 1.0, 2.0, 3.0, 4.0, 0.0, 0.0, 0.0]); } @@ -3315,11 +3325,13 @@ mod tests { // Miri cannot support this until it is clear how it fits in the Rust memory model // (non-temporal store) #[cfg_attr(miri, ignore)] - unsafe fn test_mm_stream_ps() { + fn test_mm_stream_ps() { let a = _mm_set1_ps(7.0); let mut mem = Memory { data: [-1.0; 4] }; - _mm_stream_ps(ptr::addr_of_mut!(mem.data[0]), a); + unsafe { + _mm_stream_ps(ptr::addr_of_mut!(mem.data[0]), a); + } _mm_sfence(); for i in 0..4 { assert_eq!(mem.data[i], get_m128(a, i)); diff --git a/library/stdarch/crates/core_arch/src/x86/sse2.rs b/library/stdarch/crates/core_arch/src/x86/sse2.rs index d712c4f4c5d7..f339a003df4d 100644 --- a/library/stdarch/crates/core_arch/src/x86/sse2.rs +++ b/library/stdarch/crates/core_arch/src/x86/sse2.rs @@ -3291,9 +3291,11 @@ mod tests { } #[simd_test(enable = "sse2")] - unsafe fn test_mm_clflush() { + fn test_mm_clflush() { let x = 0_u8; - _mm_clflush(ptr::addr_of!(x)); + unsafe { + _mm_clflush(ptr::addr_of!(x)); + } } #[simd_test(enable = "sse2")] @@ -3725,7 +3727,7 @@ mod tests { } #[simd_test(enable = "sse2")] - unsafe fn test_mm_sll_epi16() { + fn test_mm_sll_epi16() { let a = _mm_setr_epi16(0xCC, -0xCC, 0xDD, -0xDD, 0xEE, -0xEE, 0xFF, -0xFF); let r = _mm_sll_epi16(a, _mm_set_epi64x(0, 4)); assert_eq_m128i( @@ -4071,7 +4073,7 @@ mod tests { } #[simd_test(enable = "sse2")] - unsafe fn test_mm_cvtps_epi32() { + fn test_mm_cvtps_epi32() { let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); let r = _mm_cvtps_epi32(a); assert_eq_m128i(r, _mm_setr_epi32(1, 2, 3, 4)); @@ -4178,23 +4180,23 @@ mod tests { } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_loadl_epi64() { + const fn test_mm_loadl_epi64() { let a = _mm_setr_epi64x(6, 5); - let r = _mm_loadl_epi64(ptr::addr_of!(a)); + let r = unsafe { _mm_loadl_epi64(ptr::addr_of!(a)) }; assert_eq_m128i(r, _mm_setr_epi64x(6, 0)); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_load_si128() { + const fn test_mm_load_si128() { let a = _mm_set_epi64x(5, 6); - let r = _mm_load_si128(ptr::addr_of!(a) as *const _); + let r = unsafe { _mm_load_si128(ptr::addr_of!(a) as *const _) }; assert_eq_m128i(a, r); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_loadu_si128() { + const fn test_mm_loadu_si128() { let a = _mm_set_epi64x(5, 6); - let r = _mm_loadu_si128(ptr::addr_of!(a) as *const _); + let r = unsafe { _mm_loadu_si128(ptr::addr_of!(a) as *const _) }; assert_eq_m128i(a, r); } @@ -4202,7 +4204,7 @@ mod tests { // Miri cannot support this until it is clear how it fits in the Rust memory model // (non-temporal store) #[cfg_attr(miri, ignore)] - unsafe fn test_mm_maskmoveu_si128() { + fn test_mm_maskmoveu_si128() { let a = _mm_set1_epi8(9); #[rustfmt::skip] let mask = _mm_set_epi8( @@ -4210,33 +4212,41 @@ mod tests { 0, 0, 0, 0, 0, 0, 0, 0, ); let mut r = _mm_set1_epi8(0); - _mm_maskmoveu_si128(a, mask, ptr::addr_of_mut!(r) as *mut i8); + unsafe { + _mm_maskmoveu_si128(a, mask, ptr::addr_of_mut!(r) as *mut i8); + } _mm_sfence(); let e = _mm_set_epi8(0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); assert_eq_m128i(r, e); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_store_si128() { + const fn test_mm_store_si128() { let a = _mm_set1_epi8(9); let mut r = _mm_set1_epi8(0); - _mm_store_si128(&mut r, a); + unsafe { + _mm_store_si128(&mut r, a); + } assert_eq_m128i(r, a); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_storeu_si128() { + const fn test_mm_storeu_si128() { let a = _mm_set1_epi8(9); let mut r = _mm_set1_epi8(0); - _mm_storeu_si128(&mut r, a); + unsafe { + _mm_storeu_si128(&mut r, a); + } assert_eq_m128i(r, a); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_storel_epi64() { + const fn test_mm_storel_epi64() { let a = _mm_setr_epi64x(2, 9); let mut r = _mm_set1_epi8(0); - _mm_storel_epi64(&mut r, a); + unsafe { + _mm_storel_epi64(&mut r, a); + } assert_eq_m128i(r, _mm_setr_epi64x(2, 0)); } @@ -4244,10 +4254,12 @@ mod tests { // Miri cannot support this until it is clear how it fits in the Rust memory model // (non-temporal store) #[cfg_attr(miri, ignore)] - unsafe fn test_mm_stream_si128() { + fn test_mm_stream_si128() { let a = _mm_setr_epi32(1, 2, 3, 4); let mut r = _mm_undefined_si128(); - _mm_stream_si128(ptr::addr_of_mut!(r), a); + unsafe { + _mm_stream_si128(ptr::addr_of_mut!(r), a); + } _mm_sfence(); assert_eq_m128i(r, a); } @@ -4256,10 +4268,12 @@ mod tests { // Miri cannot support this until it is clear how it fits in the Rust memory model // (non-temporal store) #[cfg_attr(miri, ignore)] - unsafe fn test_mm_stream_si32() { + fn test_mm_stream_si32() { let a: i32 = 7; let mut mem = boxed::Box::::new(-1); - _mm_stream_si32(ptr::addr_of_mut!(*mem), a); + unsafe { + _mm_stream_si32(ptr::addr_of_mut!(*mem), a); + } _mm_sfence(); assert_eq!(a, *mem); } @@ -4909,40 +4923,40 @@ mod tests { } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_load_pd() { + const fn test_mm_load_pd() { let mem = Memory { data: [1.0f64, 2.0, 3.0, 4.0], }; let vals = &mem.data; let d = vals.as_ptr(); - let r = _mm_load_pd(d); + let r = unsafe { _mm_load_pd(d) }; assert_eq_m128d(r, _mm_setr_pd(1.0, 2.0)); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_load_sd() { + const fn test_mm_load_sd() { let a = 1.; let expected = _mm_setr_pd(a, 0.); - let r = _mm_load_sd(&a); + let r = unsafe { _mm_load_sd(&a) }; assert_eq_m128d(r, expected); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_loadh_pd() { + const fn test_mm_loadh_pd() { let a = _mm_setr_pd(1., 2.); let b = 3.; let expected = _mm_setr_pd(_mm_cvtsd_f64(a), 3.); - let r = _mm_loadh_pd(a, &b); + let r = unsafe { _mm_loadh_pd(a, &b) }; assert_eq_m128d(r, expected); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_loadl_pd() { + const fn test_mm_loadl_pd() { let a = _mm_setr_pd(1., 2.); let b = 3.; let expected = _mm_setr_pd(3., get_m128d(a, 1)); - let r = _mm_loadl_pd(a, &b); + let r = unsafe { _mm_loadl_pd(a, &b) }; assert_eq_m128d(r, expected); } @@ -4950,7 +4964,7 @@ mod tests { // Miri cannot support this until it is clear how it fits in the Rust memory model // (non-temporal store) #[cfg_attr(miri, ignore)] - unsafe fn test_mm_stream_pd() { + fn test_mm_stream_pd() { #[repr(align(128))] struct Memory { pub data: [f64; 2], @@ -4958,7 +4972,9 @@ mod tests { let a = _mm_set1_pd(7.0); let mut mem = Memory { data: [-1.0; 2] }; - _mm_stream_pd(ptr::addr_of_mut!(mem.data[0]), a); + unsafe { + _mm_stream_pd(ptr::addr_of_mut!(mem.data[0]), a); + } _mm_sfence(); for i in 0..2 { assert_eq!(mem.data[i], get_m128d(a, i)); @@ -4966,132 +4982,154 @@ mod tests { } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_store_sd() { + const fn test_mm_store_sd() { let mut dest = 0.; let a = _mm_setr_pd(1., 2.); - _mm_store_sd(&mut dest, a); + unsafe { + _mm_store_sd(&mut dest, a); + } assert_eq!(dest, _mm_cvtsd_f64(a)); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_store_pd() { + const fn test_mm_store_pd() { let mut mem = Memory { data: [0.0f64; 4] }; let vals = &mut mem.data; let a = _mm_setr_pd(1.0, 2.0); let d = vals.as_mut_ptr(); - _mm_store_pd(d, *black_box(&a)); + unsafe { + _mm_store_pd(d, *black_box(&a)); + } assert_eq!(vals[0], 1.0); assert_eq!(vals[1], 2.0); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_storeu_pd() { + const fn test_mm_storeu_pd() { // guaranteed to be aligned to 16 bytes let mut mem = Memory { data: [0.0f64; 4] }; let vals = &mut mem.data; let a = _mm_setr_pd(1.0, 2.0); // so p is *not* aligned to 16 bytes - let p = vals.as_mut_ptr().offset(1); - _mm_storeu_pd(p, *black_box(&a)); + unsafe { + let p = vals.as_mut_ptr().offset(1); + _mm_storeu_pd(p, *black_box(&a)); + } assert_eq!(*vals, [0.0, 1.0, 2.0, 0.0]); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_storeu_si16() { + const fn test_mm_storeu_si16() { let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8); let mut r = _mm_setr_epi16(9, 10, 11, 12, 13, 14, 15, 16); - _mm_storeu_si16(ptr::addr_of_mut!(r).cast(), a); + unsafe { + _mm_storeu_si16(ptr::addr_of_mut!(r).cast(), a); + } let e = _mm_setr_epi16(1, 10, 11, 12, 13, 14, 15, 16); assert_eq_m128i(r, e); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_storeu_si32() { + const fn test_mm_storeu_si32() { let a = _mm_setr_epi32(1, 2, 3, 4); let mut r = _mm_setr_epi32(5, 6, 7, 8); - _mm_storeu_si32(ptr::addr_of_mut!(r).cast(), a); + unsafe { + _mm_storeu_si32(ptr::addr_of_mut!(r).cast(), a); + } let e = _mm_setr_epi32(1, 6, 7, 8); assert_eq_m128i(r, e); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_storeu_si64() { + const fn test_mm_storeu_si64() { let a = _mm_setr_epi64x(1, 2); let mut r = _mm_setr_epi64x(3, 4); - _mm_storeu_si64(ptr::addr_of_mut!(r).cast(), a); + unsafe { + _mm_storeu_si64(ptr::addr_of_mut!(r).cast(), a); + } let e = _mm_setr_epi64x(1, 4); assert_eq_m128i(r, e); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_store1_pd() { + const fn test_mm_store1_pd() { let mut mem = Memory { data: [0.0f64; 4] }; let vals = &mut mem.data; let a = _mm_setr_pd(1.0, 2.0); let d = vals.as_mut_ptr(); - _mm_store1_pd(d, *black_box(&a)); + unsafe { + _mm_store1_pd(d, *black_box(&a)); + } assert_eq!(vals[0], 1.0); assert_eq!(vals[1], 1.0); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_store_pd1() { + const fn test_mm_store_pd1() { let mut mem = Memory { data: [0.0f64; 4] }; let vals = &mut mem.data; let a = _mm_setr_pd(1.0, 2.0); let d = vals.as_mut_ptr(); - _mm_store_pd1(d, *black_box(&a)); + unsafe { + _mm_store_pd1(d, *black_box(&a)); + } assert_eq!(vals[0], 1.0); assert_eq!(vals[1], 1.0); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_storer_pd() { + const fn test_mm_storer_pd() { let mut mem = Memory { data: [0.0f64; 4] }; let vals = &mut mem.data; let a = _mm_setr_pd(1.0, 2.0); let d = vals.as_mut_ptr(); - _mm_storer_pd(d, *black_box(&a)); + unsafe { + _mm_storer_pd(d, *black_box(&a)); + } assert_eq!(vals[0], 2.0); assert_eq!(vals[1], 1.0); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_storeh_pd() { + const fn test_mm_storeh_pd() { let mut dest = 0.; let a = _mm_setr_pd(1., 2.); - _mm_storeh_pd(&mut dest, a); + unsafe { + _mm_storeh_pd(&mut dest, a); + } assert_eq!(dest, get_m128d(a, 1)); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_storel_pd() { + const fn test_mm_storel_pd() { let mut dest = 0.; let a = _mm_setr_pd(1., 2.); - _mm_storel_pd(&mut dest, a); + unsafe { + _mm_storel_pd(&mut dest, a); + } assert_eq!(dest, _mm_cvtsd_f64(a)); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_loadr_pd() { + const fn test_mm_loadr_pd() { let mut mem = Memory { data: [1.0f64, 2.0, 3.0, 4.0], }; let vals = &mut mem.data; let d = vals.as_ptr(); - let r = _mm_loadr_pd(d); + let r = unsafe { _mm_loadr_pd(d) }; assert_eq_m128d(r, _mm_setr_pd(2.0, 1.0)); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_loadu_pd() { + const fn test_mm_loadu_pd() { // guaranteed to be aligned to 16 bytes let mut mem = Memory { data: [1.0f64, 2.0, 3.0, 4.0], @@ -5099,31 +5137,31 @@ mod tests { let vals = &mut mem.data; // so this will *not* be aligned to 16 bytes - let d = vals.as_ptr().offset(1); + let d = unsafe { vals.as_ptr().offset(1) }; - let r = _mm_loadu_pd(d); + let r = unsafe { _mm_loadu_pd(d) }; let e = _mm_setr_pd(2.0, 3.0); assert_eq_m128d(r, e); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_loadu_si16() { + const fn test_mm_loadu_si16() { let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8); - let r = _mm_loadu_si16(ptr::addr_of!(a) as *const _); + let r = unsafe { _mm_loadu_si16(ptr::addr_of!(a) as *const _) }; assert_eq_m128i(r, _mm_setr_epi16(1, 0, 0, 0, 0, 0, 0, 0)); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_loadu_si32() { + const fn test_mm_loadu_si32() { let a = _mm_setr_epi32(1, 2, 3, 4); - let r = _mm_loadu_si32(ptr::addr_of!(a) as *const _); + let r = unsafe { _mm_loadu_si32(ptr::addr_of!(a) as *const _) }; assert_eq_m128i(r, _mm_setr_epi32(1, 0, 0, 0)); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_loadu_si64() { + const fn test_mm_loadu_si64() { let a = _mm_setr_epi64x(5, 6); - let r = _mm_loadu_si64(ptr::addr_of!(a) as *const _); + let r = unsafe { _mm_loadu_si64(ptr::addr_of!(a) as *const _) }; assert_eq_m128i(r, _mm_setr_epi64x(5, 0)); } @@ -5302,16 +5340,16 @@ mod tests { } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_load1_pd() { + const fn test_mm_load1_pd() { let d = -5.0; - let r = _mm_load1_pd(&d); + let r = unsafe { _mm_load1_pd(&d) }; assert_eq_m128d(r, _mm_setr_pd(d, d)); } #[simd_test(enable = "sse2")] - const unsafe fn test_mm_load_pd1() { + const fn test_mm_load_pd1() { let d = -5.0; - let r = _mm_load_pd1(&d); + let r = unsafe { _mm_load_pd1(&d) }; assert_eq_m128d(r, _mm_setr_pd(d, d)); } diff --git a/library/stdarch/crates/core_arch/src/x86/sse3.rs b/library/stdarch/crates/core_arch/src/x86/sse3.rs index 68817856f44a..e4c75702544d 100644 --- a/library/stdarch/crates/core_arch/src/x86/sse3.rs +++ b/library/stdarch/crates/core_arch/src/x86/sse3.rs @@ -239,7 +239,7 @@ mod tests { } #[simd_test(enable = "sse3")] - unsafe fn test_mm_lddqu_si128() { + fn test_mm_lddqu_si128() { #[rustfmt::skip] let a = _mm_setr_epi8( 1, 2, 3, 4, @@ -247,7 +247,7 @@ mod tests { 9, 10, 11, 12, 13, 14, 15, 16, ); - let r = _mm_lddqu_si128(&a); + let r = unsafe { _mm_lddqu_si128(&a) }; assert_eq_m128i(a, r); } @@ -273,9 +273,9 @@ mod tests { } #[simd_test(enable = "sse3")] - const unsafe fn test_mm_loaddup_pd() { + const fn test_mm_loaddup_pd() { let d = -5.0; - let r = _mm_loaddup_pd(&d); + let r = unsafe { _mm_loaddup_pd(&d) }; assert_eq_m128d(r, _mm_setr_pd(d, d)); } } diff --git a/library/stdarch/crates/core_arch/src/x86/sse41.rs b/library/stdarch/crates/core_arch/src/x86/sse41.rs index a499bf898b80..7ad4306f36f2 100644 --- a/library/stdarch/crates/core_arch/src/x86/sse41.rs +++ b/library/stdarch/crates/core_arch/src/x86/sse41.rs @@ -1219,20 +1219,20 @@ mod tests { } #[simd_test(enable = "sse4.1")] - const unsafe fn test_mm_blendv_pd() { + const fn test_mm_blendv_pd() { let a = _mm_set1_pd(0.0); let b = _mm_set1_pd(1.0); - let mask = transmute(_mm_setr_epi64x(0, -1)); + let mask = _mm_castsi128_pd(_mm_setr_epi64x(0, -1)); let r = _mm_blendv_pd(a, b, mask); let e = _mm_setr_pd(0.0, 1.0); assert_eq_m128d(r, e); } #[simd_test(enable = "sse4.1")] - const unsafe fn test_mm_blendv_ps() { + const fn test_mm_blendv_ps() { let a = _mm_set1_ps(0.0); let b = _mm_set1_ps(1.0); - let mask = transmute(_mm_setr_epi32(0, -1, 0, -1)); + let mask = _mm_castsi128_ps(_mm_setr_epi32(0, -1, 0, -1)); let r = _mm_blendv_ps(a, b, mask); let e = _mm_setr_ps(0.0, 1.0, 0.0, 1.0); assert_eq_m128(r, e); @@ -1949,9 +1949,9 @@ mod tests { } #[simd_test(enable = "sse4.1")] - unsafe fn test_mm_stream_load_si128() { + fn test_mm_stream_load_si128() { let a = _mm_set_epi64x(5, 6); - let r = _mm_stream_load_si128(core::ptr::addr_of!(a) as *const _); + let r = unsafe { _mm_stream_load_si128(core::ptr::addr_of!(a) as *const _) }; assert_eq_m128i(a, r); } } diff --git a/library/stdarch/crates/core_arch/src/x86/sse42.rs b/library/stdarch/crates/core_arch/src/x86/sse42.rs index 65d1fe4d6233..55e22592637f 100644 --- a/library/stdarch/crates/core_arch/src/x86/sse42.rs +++ b/library/stdarch/crates/core_arch/src/x86/sse42.rs @@ -613,6 +613,7 @@ mod tests { use crate::core_arch::assert_eq_const as assert_eq; use stdarch_test::simd_test; + use crate::core_arch::simd::*; use crate::core_arch::x86::*; use std::ptr; @@ -625,7 +626,7 @@ mod tests { assert!(s.len() <= 16); let mut array = [0u8; 16]; array[..s.len()].copy_from_slice(s); - unsafe { transmute(array) } + u8x16::from_array(array).as_m128i() } #[simd_test(enable = "sse4.2")] diff --git a/library/stdarch/crates/core_arch/src/x86/sse4a.rs b/library/stdarch/crates/core_arch/src/x86/sse4a.rs index 020baeff152d..f36b879a030e 100644 --- a/library/stdarch/crates/core_arch/src/x86/sse4a.rs +++ b/library/stdarch/crates/core_arch/src/x86/sse4a.rs @@ -206,7 +206,7 @@ mod tests { // Miri cannot support this until it is clear how it fits in the Rust memory model // (non-temporal store) #[cfg_attr(miri, ignore)] - unsafe fn test_mm_stream_sd() { + fn test_mm_stream_sd() { let mut mem = MemoryF64 { data: [1.0_f64, 2.0], }; @@ -216,7 +216,9 @@ mod tests { let x = _mm_setr_pd(3.0, 4.0); - _mm_stream_sd(d, x); + unsafe { + _mm_stream_sd(d, x); + } _mm_sfence(); } assert_eq!(mem.data[0], 3.0); @@ -232,7 +234,7 @@ mod tests { // Miri cannot support this until it is clear how it fits in the Rust memory model // (non-temporal store) #[cfg_attr(miri, ignore)] - unsafe fn test_mm_stream_ss() { + fn test_mm_stream_ss() { let mut mem = MemoryF32 { data: [1.0_f32, 2.0, 3.0, 4.0], }; @@ -242,7 +244,9 @@ mod tests { let x = _mm_setr_ps(5.0, 6.0, 7.0, 8.0); - _mm_stream_ss(d, x); + unsafe { + _mm_stream_ss(d, x); + } _mm_sfence(); } assert_eq!(mem.data[0], 5.0); diff --git a/library/stdarch/crates/core_arch/src/x86/xsave.rs b/library/stdarch/crates/core_arch/src/x86/xsave.rs index 653eb28c4268..e22d3580ff46 100644 --- a/library/stdarch/crates/core_arch/src/x86/xsave.rs +++ b/library/stdarch/crates/core_arch/src/x86/xsave.rs @@ -197,47 +197,53 @@ mod tests { #[simd_test(enable = "xsave")] #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri - unsafe fn test_xsave() { + fn test_xsave() { let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers let mut a = XsaveArea::new(); let mut b = XsaveArea::new(); - _xsave(a.ptr(), m); - _xrstor(a.ptr(), m); - _xsave(b.ptr(), m); + unsafe { + _xsave(a.ptr(), m); + _xrstor(a.ptr(), m); + _xsave(b.ptr(), m); + } } #[simd_test(enable = "xsave")] #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri - unsafe fn test_xgetbv() { + fn test_xgetbv() { let xcr_n: u32 = _XCR_XFEATURE_ENABLED_MASK; - let xcr: u64 = _xgetbv(xcr_n); - let xcr_cpy: u64 = _xgetbv(xcr_n); + let xcr: u64 = unsafe { _xgetbv(xcr_n) }; + let xcr_cpy: u64 = unsafe { _xgetbv(xcr_n) }; assert_eq!(xcr, xcr_cpy); } #[simd_test(enable = "xsave,xsaveopt")] #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri - unsafe fn test_xsaveopt() { + fn test_xsaveopt() { let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers let mut a = XsaveArea::new(); let mut b = XsaveArea::new(); - _xsaveopt(a.ptr(), m); - _xrstor(a.ptr(), m); - _xsaveopt(b.ptr(), m); + unsafe { + _xsaveopt(a.ptr(), m); + _xrstor(a.ptr(), m); + _xsaveopt(b.ptr(), m); + } } #[simd_test(enable = "xsave,xsavec")] #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri - unsafe fn test_xsavec() { + fn test_xsavec() { let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers let mut a = XsaveArea::new(); let mut b = XsaveArea::new(); - _xsavec(a.ptr(), m); - _xrstor(a.ptr(), m); - _xsavec(b.ptr(), m); + unsafe { + _xsavec(a.ptr(), m); + _xrstor(a.ptr(), m); + _xsavec(b.ptr(), m); + } } } diff --git a/library/stdarch/crates/core_arch/src/x86_64/amx.rs b/library/stdarch/crates/core_arch/src/x86_64/amx.rs index f372f7066d51..4e20e014cf20 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/amx.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/amx.rs @@ -581,267 +581,297 @@ mod tests { } #[simd_test(enable = "amx-tile")] - unsafe fn test_tile_loadconfig() { - let config = __tilecfg::default(); - _tile_loadconfig(config.as_ptr()); - _tile_release(); + fn test_tile_loadconfig() { + unsafe { + let config = __tilecfg::default(); + _tile_loadconfig(config.as_ptr()); + _tile_release(); + } } #[simd_test(enable = "amx-tile")] - unsafe fn test_tile_storeconfig() { - let config = __tilecfg::new(1, 0, [32; 8], [8; 8]); - _tile_loadconfig(config.as_ptr()); - let mut _config = __tilecfg::default(); - _tile_storeconfig(_config.as_mut_ptr()); - _tile_release(); - assert_eq!(config, _config); + fn test_tile_storeconfig() { + unsafe { + let config = __tilecfg::new(1, 0, [32; 8], [8; 8]); + _tile_loadconfig(config.as_ptr()); + let mut _config = __tilecfg::default(); + _tile_storeconfig(_config.as_mut_ptr()); + _tile_release(); + assert_eq!(config, _config); + } } #[simd_test(enable = "amx-tile")] - unsafe fn test_tile_zero() { - _init_amx(); - let mut config = __tilecfg::default(); - config.palette = 1; - config.colsb[0] = 64; - config.rows[0] = 16; - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - let mut out = [[1_i8; 64]; 16]; - _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); - _tile_release(); - assert_eq!(out, [[0; 64]; 16]); + fn test_tile_zero() { + unsafe { + _init_amx(); + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + let mut out = [[1_i8; 64]; 16]; + _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); + _tile_release(); + assert_eq!(out, [[0; 64]; 16]); + } } #[simd_test(enable = "amx-tile")] - unsafe fn test_tile_stored() { - _init_amx(); - let mut config = __tilecfg::default(); - config.palette = 1; - config.colsb[0] = 64; - config.rows[0] = 16; - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - let mut out = [[1_i8; 64]; 16]; - _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); - _tile_release(); - assert_eq!(out, [[0; 64]; 16]); + fn test_tile_stored() { + unsafe { + _init_amx(); + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + let mut out = [[1_i8; 64]; 16]; + _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); + _tile_release(); + assert_eq!(out, [[0; 64]; 16]); + } } #[simd_test(enable = "amx-tile")] - unsafe fn test_tile_loadd() { - _init_amx(); - let mut config = __tilecfg::default(); - config.palette = 1; - config.colsb[0] = 64; - config.rows[0] = 16; - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - let mat = [1_i8; 1024]; - _tile_loadd::<0>(&mat as *const i8 as *const u8, 64); - let mut out = [[0_i8; 64]; 16]; - _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); - _tile_release(); - assert_eq!(out, [[1; 64]; 16]); + fn test_tile_loadd() { + unsafe { + _init_amx(); + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + let mat = [1_i8; 1024]; + _tile_loadd::<0>(&mat as *const i8 as *const u8, 64); + let mut out = [[0_i8; 64]; 16]; + _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); + _tile_release(); + assert_eq!(out, [[1; 64]; 16]); + } } #[simd_test(enable = "amx-tile")] - unsafe fn test_tile_stream_loadd() { - _init_amx(); - let mut config = __tilecfg::default(); - config.palette = 1; - config.colsb[0] = 64; - config.rows[0] = 16; - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - let mat = [1_i8; 1024]; - _tile_stream_loadd::<0>(&mat as *const i8 as *const u8, 64); - let mut out = [[0_i8; 64]; 16]; - _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); - _tile_release(); - assert_eq!(out, [[1; 64]; 16]); + fn test_tile_stream_loadd() { + unsafe { + _init_amx(); + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + let mat = [1_i8; 1024]; + _tile_stream_loadd::<0>(&mat as *const i8 as *const u8, 64); + let mut out = [[0_i8; 64]; 16]; + _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); + _tile_release(); + assert_eq!(out, [[1; 64]; 16]); + } } #[simd_test(enable = "amx-tile")] - unsafe fn test_tile_release() { - _tile_release(); + fn test_tile_release() { + unsafe { + _tile_release(); + } } #[simd_test(enable = "amx-bf16,avx512f")] - unsafe fn test_tile_dpbf16ps() { - _init_amx(); - let bf16_1: u16 = _mm_cvtness_sbh(1.0).to_bits(); - let bf16_2: u16 = _mm_cvtness_sbh(2.0).to_bits(); - let ones: [u8; 1024] = transmute([bf16_1; 512]); - let twos: [u8; 1024] = transmute([bf16_2; 512]); - let mut res = [[0f32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const u8, 64); - _tile_loadd::<2>(&twos as *const u8, 64); - _tile_dpbf16ps::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64); - _tile_release(); - assert_eq!(res, [[64f32; 16]; 16]); + fn test_tile_dpbf16ps() { + unsafe { + _init_amx(); + let bf16_1: u16 = _mm_cvtness_sbh(1.0).to_bits(); + let bf16_2: u16 = _mm_cvtness_sbh(2.0).to_bits(); + let ones: [u8; 1024] = transmute([bf16_1; 512]); + let twos: [u8; 1024] = transmute([bf16_2; 512]); + let mut res = [[0f32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const u8, 64); + _tile_loadd::<2>(&twos as *const u8, 64); + _tile_dpbf16ps::<0, 1, 2>(); + _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64); + _tile_release(); + assert_eq!(res, [[64f32; 16]; 16]); + } } #[simd_test(enable = "amx-int8")] - unsafe fn test_tile_dpbssd() { - _init_amx(); - let ones = [-1_i8; 1024]; - let twos = [-2_i8; 1024]; - let mut res = [[0_i32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const i8 as *const u8, 64); - _tile_loadd::<2>(&twos as *const i8 as *const u8, 64); - _tile_dpbssd::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64); - _tile_release(); - assert_eq!(res, [[128_i32; 16]; 16]); + fn test_tile_dpbssd() { + unsafe { + _init_amx(); + let ones = [-1_i8; 1024]; + let twos = [-2_i8; 1024]; + let mut res = [[0_i32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const i8 as *const u8, 64); + _tile_loadd::<2>(&twos as *const i8 as *const u8, 64); + _tile_dpbssd::<0, 1, 2>(); + _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64); + _tile_release(); + assert_eq!(res, [[128_i32; 16]; 16]); + } } #[simd_test(enable = "amx-int8")] - unsafe fn test_tile_dpbsud() { - _init_amx(); - let ones = [-1_i8; 1024]; - let twos = [2_u8; 1024]; - let mut res = [[0_i32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const i8 as *const u8, 64); - _tile_loadd::<2>(&twos as *const u8, 64); - _tile_dpbsud::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64); - _tile_release(); - assert_eq!(res, [[-128_i32; 16]; 16]); + fn test_tile_dpbsud() { + unsafe { + _init_amx(); + let ones = [-1_i8; 1024]; + let twos = [2_u8; 1024]; + let mut res = [[0_i32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const i8 as *const u8, 64); + _tile_loadd::<2>(&twos as *const u8, 64); + _tile_dpbsud::<0, 1, 2>(); + _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64); + _tile_release(); + assert_eq!(res, [[-128_i32; 16]; 16]); + } } #[simd_test(enable = "amx-int8")] - unsafe fn test_tile_dpbusd() { - _init_amx(); - let ones = [1_u8; 1024]; - let twos = [-2_i8; 1024]; - let mut res = [[0_i32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const u8, 64); - _tile_loadd::<2>(&twos as *const i8 as *const u8, 64); - _tile_dpbusd::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64); - _tile_release(); - assert_eq!(res, [[-128_i32; 16]; 16]); + fn test_tile_dpbusd() { + unsafe { + _init_amx(); + let ones = [1_u8; 1024]; + let twos = [-2_i8; 1024]; + let mut res = [[0_i32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const u8, 64); + _tile_loadd::<2>(&twos as *const i8 as *const u8, 64); + _tile_dpbusd::<0, 1, 2>(); + _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64); + _tile_release(); + assert_eq!(res, [[-128_i32; 16]; 16]); + } } #[simd_test(enable = "amx-int8")] - unsafe fn test_tile_dpbuud() { - _init_amx(); - let ones = [1_u8; 1024]; - let twos = [2_u8; 1024]; - let mut res = [[0_i32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const u8, 64); - _tile_loadd::<2>(&twos as *const u8, 64); - _tile_dpbuud::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64); - _tile_release(); - assert_eq!(res, [[128_i32; 16]; 16]); + fn test_tile_dpbuud() { + unsafe { + _init_amx(); + let ones = [1_u8; 1024]; + let twos = [2_u8; 1024]; + let mut res = [[0_i32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const u8, 64); + _tile_loadd::<2>(&twos as *const u8, 64); + _tile_dpbuud::<0, 1, 2>(); + _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64); + _tile_release(); + assert_eq!(res, [[128_i32; 16]; 16]); + } } #[simd_test(enable = "amx-fp16")] - unsafe fn test_tile_dpfp16ps() { - _init_amx(); - let ones = [1f16; 512]; - let twos = [2f16; 512]; - let mut res = [[0f32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const f16 as *const u8, 64); - _tile_loadd::<2>(&twos as *const f16 as *const u8, 64); - _tile_dpfp16ps::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64); - _tile_release(); - assert_eq!(res, [[64f32; 16]; 16]); + fn test_tile_dpfp16ps() { + unsafe { + _init_amx(); + let ones = [1f16; 512]; + let twos = [2f16; 512]; + let mut res = [[0f32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const f16 as *const u8, 64); + _tile_loadd::<2>(&twos as *const f16 as *const u8, 64); + _tile_dpfp16ps::<0, 1, 2>(); + _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64); + _tile_release(); + assert_eq!(res, [[64f32; 16]; 16]); + } } #[simd_test(enable = "amx-complex")] - unsafe fn test_tile_cmmimfp16ps() { - _init_amx(); - let ones = [1f16; 512]; - let twos = [2f16; 512]; - let mut res = [[0f32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const f16 as *const u8, 64); - _tile_loadd::<2>(&twos as *const f16 as *const u8, 64); - _tile_cmmimfp16ps::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64); - _tile_release(); - assert_eq!(res, [[64f32; 16]; 16]); + fn test_tile_cmmimfp16ps() { + unsafe { + _init_amx(); + let ones = [1f16; 512]; + let twos = [2f16; 512]; + let mut res = [[0f32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const f16 as *const u8, 64); + _tile_loadd::<2>(&twos as *const f16 as *const u8, 64); + _tile_cmmimfp16ps::<0, 1, 2>(); + _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64); + _tile_release(); + assert_eq!(res, [[64f32; 16]; 16]); + } } #[simd_test(enable = "amx-complex")] - unsafe fn test_tile_cmmrlfp16ps() { - _init_amx(); - let ones = [1f16; 512]; - let twos = [2f16; 512]; - let mut res = [[0f32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const f16 as *const u8, 64); - _tile_loadd::<2>(&twos as *const f16 as *const u8, 64); - _tile_cmmrlfp16ps::<0, 1, 2>(); - _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64); - _tile_release(); - assert_eq!(res, [[0f32; 16]; 16]); + fn test_tile_cmmrlfp16ps() { + unsafe { + _init_amx(); + let ones = [1f16; 512]; + let twos = [2f16; 512]; + let mut res = [[0f32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const f16 as *const u8, 64); + _tile_loadd::<2>(&twos as *const f16 as *const u8, 64); + _tile_cmmrlfp16ps::<0, 1, 2>(); + _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64); + _tile_release(); + assert_eq!(res, [[0f32; 16]; 16]); + } } const BF8_ONE: u8 = 0x3c; @@ -850,223 +880,245 @@ mod tests { const HF8_TWO: u8 = 0x40; #[simd_test(enable = "amx-fp8")] - unsafe fn test_tile_dpbf8ps() { - _init_amx(); - let ones = [BF8_ONE; 1024]; - let twos = [BF8_TWO; 1024]; - let mut res = [[0.0_f32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const u8, 64); - _tile_loadd::<2>(&twos as *const u8, 64); - _tile_dpbf8ps::<0, 1, 2>(); - _tile_stored::<0>(res.as_mut_ptr().cast(), 64); - _tile_release(); - assert_eq!(res, [[128.0_f32; 16]; 16]); + fn test_tile_dpbf8ps() { + unsafe { + _init_amx(); + let ones = [BF8_ONE; 1024]; + let twos = [BF8_TWO; 1024]; + let mut res = [[0.0_f32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const u8, 64); + _tile_loadd::<2>(&twos as *const u8, 64); + _tile_dpbf8ps::<0, 1, 2>(); + _tile_stored::<0>(res.as_mut_ptr().cast(), 64); + _tile_release(); + assert_eq!(res, [[128.0_f32; 16]; 16]); + } } #[simd_test(enable = "amx-fp8")] - unsafe fn test_tile_dpbhf8ps() { - _init_amx(); - let ones = [BF8_ONE; 1024]; - let twos = [HF8_TWO; 1024]; - let mut res = [[0.0_f32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const u8, 64); - _tile_loadd::<2>(&twos as *const u8, 64); - _tile_dpbhf8ps::<0, 1, 2>(); - _tile_stored::<0>(res.as_mut_ptr().cast(), 64); - _tile_release(); - assert_eq!(res, [[128.0_f32; 16]; 16]); + fn test_tile_dpbhf8ps() { + unsafe { + _init_amx(); + let ones = [BF8_ONE; 1024]; + let twos = [HF8_TWO; 1024]; + let mut res = [[0.0_f32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const u8, 64); + _tile_loadd::<2>(&twos as *const u8, 64); + _tile_dpbhf8ps::<0, 1, 2>(); + _tile_stored::<0>(res.as_mut_ptr().cast(), 64); + _tile_release(); + assert_eq!(res, [[128.0_f32; 16]; 16]); + } } #[simd_test(enable = "amx-fp8")] - unsafe fn test_tile_dphbf8ps() { - _init_amx(); - let ones = [HF8_ONE; 1024]; - let twos = [BF8_TWO; 1024]; - let mut res = [[0.0_f32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const u8, 64); - _tile_loadd::<2>(&twos as *const u8, 64); - _tile_dphbf8ps::<0, 1, 2>(); - _tile_stored::<0>(res.as_mut_ptr().cast(), 64); - _tile_release(); - assert_eq!(res, [[128.0_f32; 16]; 16]); + fn test_tile_dphbf8ps() { + unsafe { + _init_amx(); + let ones = [HF8_ONE; 1024]; + let twos = [BF8_TWO; 1024]; + let mut res = [[0.0_f32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const u8, 64); + _tile_loadd::<2>(&twos as *const u8, 64); + _tile_dphbf8ps::<0, 1, 2>(); + _tile_stored::<0>(res.as_mut_ptr().cast(), 64); + _tile_release(); + assert_eq!(res, [[128.0_f32; 16]; 16]); + } } #[simd_test(enable = "amx-fp8")] - unsafe fn test_tile_dphf8ps() { - _init_amx(); - let ones = [HF8_ONE; 1024]; - let twos = [HF8_TWO; 1024]; - let mut res = [[0.0_f32; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(&ones as *const u8, 64); - _tile_loadd::<2>(&twos as *const u8, 64); - _tile_dphf8ps::<0, 1, 2>(); - _tile_stored::<0>(res.as_mut_ptr().cast(), 64); - _tile_release(); - assert_eq!(res, [[128.0_f32; 16]; 16]); + fn test_tile_dphf8ps() { + unsafe { + _init_amx(); + let ones = [HF8_ONE; 1024]; + let twos = [HF8_TWO; 1024]; + let mut res = [[0.0_f32; 16]; 16]; + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(&ones as *const u8, 64); + _tile_loadd::<2>(&twos as *const u8, 64); + _tile_dphf8ps::<0, 1, 2>(); + _tile_stored::<0>(res.as_mut_ptr().cast(), 64); + _tile_release(); + assert_eq!(res, [[128.0_f32; 16]; 16]); + } } #[simd_test(enable = "amx-movrs")] - unsafe fn test_tile_loaddrs() { - _init_amx(); - let mut config = __tilecfg::default(); - config.palette = 1; - config.colsb[0] = 64; - config.rows[0] = 16; - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - let mat = [1_i8; 1024]; - _tile_loaddrs::<0>(&mat as *const i8 as *const u8, 64); - let mut out = [[0_i8; 64]; 16]; - _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); - _tile_release(); - assert_eq!(out, [[1; 64]; 16]); + fn test_tile_loaddrs() { + unsafe { + _init_amx(); + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + let mat = [1_i8; 1024]; + _tile_loaddrs::<0>(&mat as *const i8 as *const u8, 64); + let mut out = [[0_i8; 64]; 16]; + _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); + _tile_release(); + assert_eq!(out, [[1; 64]; 16]); + } } #[simd_test(enable = "amx-movrs")] - unsafe fn test_tile_stream_loaddrs() { - _init_amx(); - let mut config = __tilecfg::default(); - config.palette = 1; - config.colsb[0] = 64; - config.rows[0] = 16; - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - let mat = [1_i8; 1024]; - _tile_stream_loaddrs::<0>(&mat as *const i8 as *const u8, 64); - let mut out = [[0_i8; 64]; 16]; - _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); - _tile_release(); - assert_eq!(out, [[1; 64]; 16]); - } - - #[simd_test(enable = "amx-avx512,avx10.2")] - unsafe fn test_tile_movrow() { - _init_amx(); - let array: [[u8; 64]; 16] = array::from_fn(|i| [i as _; _]); - - let mut config = __tilecfg::default(); - config.palette = 1; - config.colsb[0] = 64; - config.rows[0] = 16; - _tile_loadconfig(config.as_ptr()); - _tile_loadd::<0>(array.as_ptr().cast(), 64); - for i in 0..16 { - let row = _tile_movrow::<0>(i); - assert_eq!(*row.as_u8x64().as_array(), [i as _; _]); + fn test_tile_stream_loaddrs() { + unsafe { + _init_amx(); + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + let mat = [1_i8; 1024]; + _tile_stream_loaddrs::<0>(&mat as *const i8 as *const u8, 64); + let mut out = [[0_i8; 64]; 16]; + _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64); + _tile_release(); + assert_eq!(out, [[1; 64]; 16]); } } #[simd_test(enable = "amx-avx512,avx10.2")] - unsafe fn test_tile_cvtrowd2ps() { - _init_amx(); - let array: [[u32; 16]; 16] = array::from_fn(|i| [i as _; _]); + fn test_tile_movrow() { + unsafe { + _init_amx(); + let array: [[u8; 64]; 16] = array::from_fn(|i| [i as _; _]); - let mut config = __tilecfg::default(); - config.palette = 1; - config.colsb[0] = 64; - config.rows[0] = 16; - _tile_loadconfig(config.as_ptr()); - _tile_loadd::<0>(array.as_ptr().cast(), 64); - for i in 0..16 { - let row = _tile_cvtrowd2ps::<0>(i); - assert_eq!(*row.as_f32x16().as_array(), [i as _; _]); + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + for i in 0..16 { + let row = _tile_movrow::<0>(i); + assert_eq!(*row.as_u8x64().as_array(), [i as _; _]); + } } } #[simd_test(enable = "amx-avx512,avx10.2")] - unsafe fn test_tile_cvtrowps2phh() { - _init_amx(); - let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); + fn test_tile_cvtrowd2ps() { + unsafe { + _init_amx(); + let array: [[u32; 16]; 16] = array::from_fn(|i| [i as _; _]); - let mut config = __tilecfg::default(); - config.palette = 1; - config.colsb[0] = 64; - config.rows[0] = 16; - _tile_loadconfig(config.as_ptr()); - _tile_loadd::<0>(array.as_ptr().cast(), 64); - for i in 0..16 { - let row = _tile_cvtrowps2phh::<0>(i); - assert_eq!( - *row.as_f16x32().as_array(), - array::from_fn(|j| if j & 1 == 0 { 0.0 } else { i as _ }) - ); + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + for i in 0..16 { + let row = _tile_cvtrowd2ps::<0>(i); + assert_eq!(*row.as_f32x16().as_array(), [i as _; _]); + } } } #[simd_test(enable = "amx-avx512,avx10.2")] - unsafe fn test_tile_cvtrowps2phl() { - _init_amx(); - let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); + fn test_tile_cvtrowps2phh() { + unsafe { + _init_amx(); + let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); - let mut config = __tilecfg::default(); - config.palette = 1; - config.colsb[0] = 64; - config.rows[0] = 16; - _tile_loadconfig(config.as_ptr()); - _tile_loadd::<0>(array.as_ptr().cast(), 64); - for i in 0..16 { - let row = _tile_cvtrowps2phl::<0>(i); - assert_eq!( - *row.as_f16x32().as_array(), - array::from_fn(|j| if j & 1 == 0 { i as _ } else { 0.0 }) - ); + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + for i in 0..16 { + let row = _tile_cvtrowps2phh::<0>(i); + assert_eq!( + *row.as_f16x32().as_array(), + array::from_fn(|j| if j & 1 == 0 { 0.0 } else { i as _ }) + ); + } + } + } + + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test_tile_cvtrowps2phl() { + unsafe { + _init_amx(); + let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); + + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + for i in 0..16 { + let row = _tile_cvtrowps2phl::<0>(i); + assert_eq!( + *row.as_f16x32().as_array(), + array::from_fn(|j| if j & 1 == 0 { i as _ } else { 0.0 }) + ); + } } } #[simd_test(enable = "amx-tf32")] - unsafe fn test_tile_mmultf32ps() { - _init_amx(); - let a: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); - let b: [[f32; 16]; 16] = [array::from_fn(|j| j as _); _]; - let mut res = [[0.0; 16]; 16]; + fn test_tile_mmultf32ps() { + unsafe { + _init_amx(); + let a: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); + let b: [[f32; 16]; 16] = [array::from_fn(|j| j as _); _]; + let mut res = [[0.0; 16]; 16]; - let mut config = __tilecfg::default(); - config.palette = 1; - (0..=2).for_each(|i| { - config.colsb[i] = 64; - config.rows[i] = 16; - }); - _tile_loadconfig(config.as_ptr()); - _tile_zero::<0>(); - _tile_loadd::<1>(a.as_ptr().cast(), 64); - _tile_loadd::<2>(b.as_ptr().cast(), 64); - _tile_mmultf32ps::<0, 1, 2>(); - _tile_stored::<0>(res.as_mut_ptr().cast(), 64); - _tile_release(); + let mut config = __tilecfg::default(); + config.palette = 1; + (0..=2).for_each(|i| { + config.colsb[i] = 64; + config.rows[i] = 16; + }); + _tile_loadconfig(config.as_ptr()); + _tile_zero::<0>(); + _tile_loadd::<1>(a.as_ptr().cast(), 64); + _tile_loadd::<2>(b.as_ptr().cast(), 64); + _tile_mmultf32ps::<0, 1, 2>(); + _tile_stored::<0>(res.as_mut_ptr().cast(), 64); + _tile_release(); - let expected = array::from_fn(|i| array::from_fn(|j| 16.0 * i as f32 * j as f32)); - assert_eq!(res, expected); + let expected = array::from_fn(|i| array::from_fn(|j| 16.0 * i as f32 * j as f32)); + assert_eq!(res, expected); + } } } diff --git a/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs b/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs index 368fb0c238e4..0fd9b09363d4 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs @@ -7446,81 +7446,81 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32gather_pd() { + fn test_mm512_i32gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); // A multiplier of 8 is word-addressing let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112); - let r = _mm512_i32gather_pd::<8>(index, arr.as_ptr()); + let r = unsafe { _mm512_i32gather_pd::<8>(index, arr.as_ptr()) }; assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32gather_pd() { + fn test_mm512_mask_i32gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); let src = _mm512_set1_pd(2.); let mask = 0b10101010; let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112); // A multiplier of 8 is word-addressing - let r = _mm512_mask_i32gather_pd::<8>(src, mask, index, arr.as_ptr()); + let r = unsafe { _mm512_mask_i32gather_pd::<8>(src, mask, index, arr.as_ptr()) }; assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i64gather_pd() { + fn test_mm512_i64gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); // A multiplier of 8 is word-addressing let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); - let r = _mm512_i64gather_pd::<8>(index, arr.as_ptr()); + let r = unsafe { _mm512_i64gather_pd::<8>(index, arr.as_ptr()) }; assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i64gather_pd() { + fn test_mm512_mask_i64gather_pd() { let arr: [f64; 128] = core::array::from_fn(|i| i as f64); let src = _mm512_set1_pd(2.); let mask = 0b10101010; let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); // A multiplier of 8 is word-addressing - let r = _mm512_mask_i64gather_pd::<8>(src, mask, index, arr.as_ptr()); + let r = unsafe { _mm512_mask_i64gather_pd::<8>(src, mask, index, arr.as_ptr()) }; assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i64gather_ps() { + fn test_mm512_i64gather_ps() { let arr: [f32; 128] = core::array::from_fn(|i| i as f32); // A multiplier of 4 is word-addressing #[rustfmt::skip] let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); - let r = _mm512_i64gather_ps::<4>(index, arr.as_ptr()); + let r = unsafe { _mm512_i64gather_ps::<4>(index, arr.as_ptr()) }; assert_eq_m256(r, _mm256_setr_ps(0., 16., 32., 48., 64., 80., 96., 112.)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i64gather_ps() { + fn test_mm512_mask_i64gather_ps() { let arr: [f32; 128] = core::array::from_fn(|i| i as f32); let src = _mm256_set1_ps(2.); let mask = 0b10101010; #[rustfmt::skip] let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); // A multiplier of 4 is word-addressing - let r = _mm512_mask_i64gather_ps::<4>(src, mask, index, arr.as_ptr()); + let r = unsafe { _mm512_mask_i64gather_ps::<4>(src, mask, index, arr.as_ptr()) }; assert_eq_m256(r, _mm256_setr_ps(2., 16., 2., 48., 2., 80., 2., 112.)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32gather_epi64() { + fn test_mm512_i32gather_epi64() { let mut arr = [0i64; 128]; for i in 0..128i64 { arr[i as usize] = i; } // A multiplier of 8 is word-addressing let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112); - let r = _mm512_i32gather_epi64::<8>(index, arr.as_ptr()); + let r = unsafe { _mm512_i32gather_epi64::<8>(index, arr.as_ptr()) }; assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32gather_epi64() { + fn test_mm512_mask_i32gather_epi64() { let mut arr = [0i64; 128]; for i in 0..128i64 { arr[i as usize] = i; @@ -7529,24 +7529,24 @@ mod tests { let mask = 0b10101010; let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112); // A multiplier of 8 is word-addressing - let r = _mm512_mask_i32gather_epi64::<8>(src, mask, index, arr.as_ptr()); + let r = unsafe { _mm512_mask_i32gather_epi64::<8>(src, mask, index, arr.as_ptr()) }; assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i64gather_epi64() { + fn test_mm512_i64gather_epi64() { let mut arr = [0i64; 128]; for i in 0..128i64 { arr[i as usize] = i; } // A multiplier of 8 is word-addressing let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); - let r = _mm512_i64gather_epi64::<8>(index, arr.as_ptr()); + let r = unsafe { _mm512_i64gather_epi64::<8>(index, arr.as_ptr()) }; assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i64gather_epi64() { + fn test_mm512_mask_i64gather_epi64() { let mut arr = [0i64; 128]; for i in 0..128i64 { arr[i as usize] = i; @@ -7555,24 +7555,24 @@ mod tests { let mask = 0b10101010; let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); // A multiplier of 8 is word-addressing - let r = _mm512_mask_i64gather_epi64::<8>(src, mask, index, arr.as_ptr()); + let r = unsafe { _mm512_mask_i64gather_epi64::<8>(src, mask, index, arr.as_ptr()) }; assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i64gather_epi32() { + fn test_mm512_i64gather_epi32() { let mut arr = [0i64; 128]; for i in 0..128i64 { arr[i as usize] = i; } // A multiplier of 8 is word-addressing let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); - let r = _mm512_i64gather_epi32::<8>(index, arr.as_ptr() as *const i32); + let r = unsafe { _mm512_i64gather_epi32::<8>(index, arr.as_ptr() as *const i32) }; assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i64gather_epi32() { + fn test_mm512_mask_i64gather_epi32() { let mut arr = [0i64; 128]; for i in 0..128i64 { arr[i as usize] = i; @@ -7581,17 +7581,21 @@ mod tests { let mask = 0b10101010; let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); // A multiplier of 8 is word-addressing - let r = _mm512_mask_i64gather_epi32::<8>(src, mask, index, arr.as_ptr() as *const i32); + let r = unsafe { + _mm512_mask_i64gather_epi32::<8>(src, mask, index, arr.as_ptr() as *const i32) + }; assert_eq_m256i(r, _mm256_setr_epi32(2, 16, 2, 48, 2, 80, 2, 112)); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32scatter_pd() { + fn test_mm512_i32scatter_pd() { let mut arr = [0f64; 128]; let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.); // A multiplier of 8 is word-addressing - _mm512_i32scatter_pd::<8>(arr.as_mut_ptr(), index, src); + unsafe { + _mm512_i32scatter_pd::<8>(arr.as_mut_ptr(), index, src); + } let mut expected = [0f64; 128]; for i in 0..8 { expected[i * 16] = (i + 1) as f64; @@ -7600,13 +7604,15 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32scatter_pd() { + fn test_mm512_mask_i32scatter_pd() { let mut arr = [0f64; 128]; let mask = 0b10101010; let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.); // A multiplier of 8 is word-addressing - _mm512_mask_i32scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src); + unsafe { + _mm512_mask_i32scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src); + } let mut expected = [0f64; 128]; for i in 0..4 { expected[i * 32 + 16] = 2. * (i + 1) as f64; @@ -7615,12 +7621,14 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i64scatter_pd() { + fn test_mm512_i64scatter_pd() { let mut arr = [0f64; 128]; let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.); // A multiplier of 8 is word-addressing - _mm512_i64scatter_pd::<8>(arr.as_mut_ptr(), index, src); + unsafe { + _mm512_i64scatter_pd::<8>(arr.as_mut_ptr(), index, src); + } let mut expected = [0f64; 128]; for i in 0..8 { expected[i * 16] = (i + 1) as f64; @@ -7629,13 +7637,15 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i64scatter_pd() { + fn test_mm512_mask_i64scatter_pd() { let mut arr = [0f64; 128]; let mask = 0b10101010; let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.); // A multiplier of 8 is word-addressing - _mm512_mask_i64scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src); + unsafe { + _mm512_mask_i64scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src); + } let mut expected = [0f64; 128]; for i in 0..4 { expected[i * 32 + 16] = 2. * (i + 1) as f64; @@ -7644,12 +7654,14 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i64scatter_ps() { + fn test_mm512_i64scatter_ps() { let mut arr = [0f32; 128]; let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.); // A multiplier of 4 is word-addressing - _mm512_i64scatter_ps::<4>(arr.as_mut_ptr(), index, src); + unsafe { + _mm512_i64scatter_ps::<4>(arr.as_mut_ptr(), index, src); + } let mut expected = [0f32; 128]; for i in 0..8 { expected[i * 16] = (i + 1) as f32; @@ -7658,13 +7670,15 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i64scatter_ps() { + fn test_mm512_mask_i64scatter_ps() { let mut arr = [0f32; 128]; let mask = 0b10101010; let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.); // A multiplier of 4 is word-addressing - _mm512_mask_i64scatter_ps::<4>(arr.as_mut_ptr(), mask, index, src); + unsafe { + _mm512_mask_i64scatter_ps::<4>(arr.as_mut_ptr(), mask, index, src); + } let mut expected = [0f32; 128]; for i in 0..4 { expected[i * 32 + 16] = 2. * (i + 1) as f32; @@ -7673,12 +7687,14 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32scatter_epi64() { + fn test_mm512_i32scatter_epi64() { let mut arr = [0i64; 128]; let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8); // A multiplier of 8 is word-addressing - _mm512_i32scatter_epi64::<8>(arr.as_mut_ptr(), index, src); + unsafe { + _mm512_i32scatter_epi64::<8>(arr.as_mut_ptr(), index, src); + } let mut expected = [0i64; 128]; for i in 0..8 { expected[i * 16] = (i + 1) as i64; @@ -7687,13 +7703,15 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32scatter_epi64() { + fn test_mm512_mask_i32scatter_epi64() { let mut arr = [0i64; 128]; let mask = 0b10101010; let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8); // A multiplier of 8 is word-addressing - _mm512_mask_i32scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src); + unsafe { + _mm512_mask_i32scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src); + } let mut expected = [0i64; 128]; for i in 0..4 { expected[i * 32 + 16] = 2 * (i + 1) as i64; @@ -7702,12 +7720,14 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i64scatter_epi64() { + fn test_mm512_i64scatter_epi64() { let mut arr = [0i64; 128]; let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8); // A multiplier of 8 is word-addressing - _mm512_i64scatter_epi64::<8>(arr.as_mut_ptr(), index, src); + unsafe { + _mm512_i64scatter_epi64::<8>(arr.as_mut_ptr(), index, src); + } let mut expected = [0i64; 128]; for i in 0..8 { expected[i * 16] = (i + 1) as i64; @@ -7716,13 +7736,15 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i64scatter_epi64() { + fn test_mm512_mask_i64scatter_epi64() { let mut arr = [0i64; 128]; let mask = 0b10101010; let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8); // A multiplier of 8 is word-addressing - _mm512_mask_i64scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src); + unsafe { + _mm512_mask_i64scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src); + } let mut expected = [0i64; 128]; for i in 0..4 { expected[i * 32 + 16] = 2 * (i + 1) as i64; @@ -7731,12 +7753,14 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i64scatter_epi32() { + fn test_mm512_i64scatter_epi32() { let mut arr = [0i32; 128]; let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8); // A multiplier of 4 is word-addressing - _mm512_i64scatter_epi32::<4>(arr.as_mut_ptr(), index, src); + unsafe { + _mm512_i64scatter_epi32::<4>(arr.as_mut_ptr(), index, src); + } let mut expected = [0i32; 128]; for i in 0..8 { expected[i * 16] = (i + 1) as i32; @@ -7745,13 +7769,15 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i64scatter_epi32() { + fn test_mm512_mask_i64scatter_epi32() { let mut arr = [0i32; 128]; let mask = 0b10101010; let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112); let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8); // A multiplier of 4 is word-addressing - _mm512_mask_i64scatter_epi32::<4>(arr.as_mut_ptr(), mask, index, src); + unsafe { + _mm512_mask_i64scatter_epi32::<4>(arr.as_mut_ptr(), mask, index, src); + } let mut expected = [0i32; 128]; for i in 0..4 { expected[i * 32 + 16] = 2 * (i + 1) as i32; @@ -7760,559 +7786,640 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32logather_epi64() { + fn test_mm512_i32logather_epi64() { let base_addr: [i64; 8] = [1, 2, 3, 4, 5, 6, 7, 8]; let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1); - let r = _mm512_i32logather_epi64::<8>(vindex, base_addr.as_ptr()); + let r = unsafe { _mm512_i32logather_epi64::<8>(vindex, base_addr.as_ptr()) }; let expected = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1); assert_eq_m512i(expected, r); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32logather_epi64() { + fn test_mm512_mask_i32logather_epi64() { let base_addr: [i64; 8] = [1, 2, 3, 4, 5, 6, 7, 8]; let src = _mm512_setr_epi64(9, 10, 11, 12, 13, 14, 15, 16); let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1); - let r = _mm512_mask_i32logather_epi64::<8>(src, 0b01010101, vindex, base_addr.as_ptr()); + let r = unsafe { + _mm512_mask_i32logather_epi64::<8>(src, 0b01010101, vindex, base_addr.as_ptr()) + }; let expected = _mm512_setr_epi64(2, 10, 4, 12, 6, 14, 8, 16); assert_eq_m512i(expected, r); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32logather_pd() { + fn test_mm512_i32logather_pd() { let base_addr: [f64; 8] = [1., 2., 3., 4., 5., 6., 7., 8.]; let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1); - let r = _mm512_i32logather_pd::<8>(vindex, base_addr.as_ptr()); + let r = unsafe { _mm512_i32logather_pd::<8>(vindex, base_addr.as_ptr()) }; let expected = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.); assert_eq_m512d(expected, r); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32logather_pd() { + fn test_mm512_mask_i32logather_pd() { let base_addr: [f64; 8] = [1., 2., 3., 4., 5., 6., 7., 8.]; let src = _mm512_setr_pd(9., 10., 11., 12., 13., 14., 15., 16.); let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1); - let r = _mm512_mask_i32logather_pd::<8>(src, 0b01010101, vindex, base_addr.as_ptr()); + let r = + unsafe { _mm512_mask_i32logather_pd::<8>(src, 0b01010101, vindex, base_addr.as_ptr()) }; let expected = _mm512_setr_pd(2., 10., 4., 12., 6., 14., 8., 16.); assert_eq_m512d(expected, r); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32loscatter_epi64() { + fn test_mm512_i32loscatter_epi64() { let mut base_addr: [i64; 8] = [0; 8]; let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1); let src = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1); - _mm512_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm512_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1, 2, 3, 4, 5, 6, 7, 8]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32loscatter_epi64() { + fn test_mm512_mask_i32loscatter_epi64() { let mut base_addr: [i64; 8] = [0; 8]; let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1); let src = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1); - _mm512_mask_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src); + unsafe { + _mm512_mask_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src); + } let expected = [0, 2, 0, 4, 0, 6, 0, 8]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_i32loscatter_pd() { + fn test_mm512_i32loscatter_pd() { let mut base_addr: [f64; 8] = [0.; 8]; let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1); let src = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.); - _mm512_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm512_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1., 2., 3., 4., 5., 6., 7., 8.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_i32loscatter_pd() { + fn test_mm512_mask_i32loscatter_pd() { let mut base_addr: [f64; 8] = [0.; 8]; let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1); let src = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.); - _mm512_mask_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src); + unsafe { + _mm512_mask_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src); + } let expected = [0., 2., 0., 4., 0., 6., 0., 8.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mmask_i32gather_epi32() { + fn test_mm_mmask_i32gather_epi32() { let base_addr: [i32; 4] = [1, 2, 3, 4]; let src = _mm_setr_epi32(5, 6, 7, 8); let vindex = _mm_setr_epi32(1, 2, 3, 0); - let r = _mm_mmask_i32gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr()); + let r = unsafe { _mm_mmask_i32gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr()) }; let expected = _mm_setr_epi32(2, 6, 4, 8); assert_eq_m128i(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mmask_i32gather_epi64() { + fn test_mm_mmask_i32gather_epi64() { let base_addr: [i64; 2] = [1, 2]; let src = _mm_setr_epi64x(5, 6); let vindex = _mm_setr_epi32(1, 0, -1, -1); - let r = _mm_mmask_i32gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr()); + let r = unsafe { _mm_mmask_i32gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr()) }; let expected = _mm_setr_epi64x(2, 6); assert_eq_m128i(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mmask_i32gather_pd() { + fn test_mm_mmask_i32gather_pd() { let base_addr: [f64; 2] = [1., 2.]; let src = _mm_setr_pd(5., 6.); let vindex = _mm_setr_epi32(1, 0, -1, -1); - let r = _mm_mmask_i32gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr()); + let r = unsafe { _mm_mmask_i32gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr()) }; let expected = _mm_setr_pd(2., 6.); assert_eq_m128d(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mmask_i32gather_ps() { + fn test_mm_mmask_i32gather_ps() { let base_addr: [f32; 4] = [1., 2., 3., 4.]; let src = _mm_setr_ps(5., 6., 7., 8.); let vindex = _mm_setr_epi32(1, 2, 3, 0); - let r = _mm_mmask_i32gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr()); + let r = unsafe { _mm_mmask_i32gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr()) }; let expected = _mm_setr_ps(2., 6., 4., 8.); assert_eq_m128(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mmask_i64gather_epi32() { + fn test_mm_mmask_i64gather_epi32() { let base_addr: [i32; 2] = [1, 2]; let src = _mm_setr_epi32(5, 6, 7, 8); let vindex = _mm_setr_epi64x(1, 0); - let r = _mm_mmask_i64gather_epi32::<4>(src, 0b01, vindex, base_addr.as_ptr()); + let r = unsafe { _mm_mmask_i64gather_epi32::<4>(src, 0b01, vindex, base_addr.as_ptr()) }; let expected = _mm_setr_epi32(2, 6, 0, 0); assert_eq_m128i(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mmask_i64gather_epi64() { + fn test_mm_mmask_i64gather_epi64() { let base_addr: [i64; 2] = [1, 2]; let src = _mm_setr_epi64x(5, 6); let vindex = _mm_setr_epi64x(1, 0); - let r = _mm_mmask_i64gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr()); + let r = unsafe { _mm_mmask_i64gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr()) }; let expected = _mm_setr_epi64x(2, 6); assert_eq_m128i(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mmask_i64gather_pd() { + fn test_mm_mmask_i64gather_pd() { let base_addr: [f64; 2] = [1., 2.]; let src = _mm_setr_pd(5., 6.); let vindex = _mm_setr_epi64x(1, 0); - let r = _mm_mmask_i64gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr()); + let r = unsafe { _mm_mmask_i64gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr()) }; let expected = _mm_setr_pd(2., 6.); assert_eq_m128d(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mmask_i64gather_ps() { + fn test_mm_mmask_i64gather_ps() { let base_addr: [f32; 2] = [1., 2.]; let src = _mm_setr_ps(5., 6., 7., 8.); let vindex = _mm_setr_epi64x(1, 0); - let r = _mm_mmask_i64gather_ps::<4>(src, 0b01, vindex, base_addr.as_ptr()); + let r = unsafe { _mm_mmask_i64gather_ps::<4>(src, 0b01, vindex, base_addr.as_ptr()) }; let expected = _mm_setr_ps(2., 6., 0., 0.); assert_eq_m128(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mmask_i32gather_epi32() { + fn test_mm256_mmask_i32gather_epi32() { let base_addr: [i32; 8] = [1, 2, 3, 4, 5, 6, 7, 8]; let src = _mm256_setr_epi32(9, 10, 11, 12, 13, 14, 15, 16); let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0); - let r = _mm256_mmask_i32gather_epi32::<4>(src, 0b01010101, vindex, base_addr.as_ptr()); + let r = unsafe { + _mm256_mmask_i32gather_epi32::<4>(src, 0b01010101, vindex, base_addr.as_ptr()) + }; let expected = _mm256_setr_epi32(2, 10, 4, 12, 6, 14, 8, 16); assert_eq_m256i(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mmask_i32gather_epi64() { + fn test_mm256_mmask_i32gather_epi64() { let base_addr: [i64; 4] = [1, 2, 3, 4]; let src = _mm256_setr_epi64x(9, 10, 11, 12); let vindex = _mm_setr_epi32(1, 2, 3, 4); - let r = _mm256_mmask_i32gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr()); + let r = + unsafe { _mm256_mmask_i32gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr()) }; let expected = _mm256_setr_epi64x(2, 10, 4, 12); assert_eq_m256i(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mmask_i32gather_pd() { + fn test_mm256_mmask_i32gather_pd() { let base_addr: [f64; 4] = [1., 2., 3., 4.]; let src = _mm256_setr_pd(9., 10., 11., 12.); let vindex = _mm_setr_epi32(1, 2, 3, 4); - let r = _mm256_mmask_i32gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr()); + let r = unsafe { _mm256_mmask_i32gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr()) }; let expected = _mm256_setr_pd(2., 10., 4., 12.); assert_eq_m256d(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mmask_i32gather_ps() { + fn test_mm256_mmask_i32gather_ps() { let base_addr: [f32; 8] = [1., 2., 3., 4., 5., 6., 7., 8.]; let src = _mm256_setr_ps(9., 10., 11., 12., 13., 14., 15., 16.); let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0); - let r = _mm256_mmask_i32gather_ps::<4>(src, 0b01010101, vindex, base_addr.as_ptr()); + let r = + unsafe { _mm256_mmask_i32gather_ps::<4>(src, 0b01010101, vindex, base_addr.as_ptr()) }; let expected = _mm256_setr_ps(2., 10., 4., 12., 6., 14., 8., 16.); assert_eq_m256(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mmask_i64gather_epi32() { + fn test_mm256_mmask_i64gather_epi32() { let base_addr: [i32; 4] = [1, 2, 3, 4]; let src = _mm_setr_epi32(9, 10, 11, 12); let vindex = _mm256_setr_epi64x(1, 2, 3, 0); - let r = _mm256_mmask_i64gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr()); + let r = + unsafe { _mm256_mmask_i64gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr()) }; let expected = _mm_setr_epi32(2, 10, 4, 12); assert_eq_m128i(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mmask_i64gather_epi64() { + fn test_mm256_mmask_i64gather_epi64() { let base_addr: [i64; 4] = [1, 2, 3, 4]; let src = _mm256_setr_epi64x(9, 10, 11, 12); let vindex = _mm256_setr_epi64x(1, 2, 3, 0); - let r = _mm256_mmask_i64gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr()); + let r = + unsafe { _mm256_mmask_i64gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr()) }; let expected = _mm256_setr_epi64x(2, 10, 4, 12); assert_eq_m256i(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mmask_i64gather_pd() { + fn test_mm256_mmask_i64gather_pd() { let base_addr: [f64; 4] = [1., 2., 3., 4.]; let src = _mm256_setr_pd(9., 10., 11., 12.); let vindex = _mm256_setr_epi64x(1, 2, 3, 0); - let r = _mm256_mmask_i64gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr()); + let r = unsafe { _mm256_mmask_i64gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr()) }; let expected = _mm256_setr_pd(2., 10., 4., 12.); assert_eq_m256d(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mmask_i64gather_ps() { + fn test_mm256_mmask_i64gather_ps() { let base_addr: [f32; 4] = [1., 2., 3., 4.]; let src = _mm_setr_ps(9., 10., 11., 12.); let vindex = _mm256_setr_epi64x(1, 2, 3, 0); - let r = _mm256_mmask_i64gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr()); + let r = unsafe { _mm256_mmask_i64gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr()) }; let expected = _mm_setr_ps(2., 10., 4., 12.); assert_eq_m128(expected, r); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_i32scatter_epi32() { + fn test_mm_i32scatter_epi32() { let mut base_addr: [i32; 4] = [0; 4]; let vindex = _mm_setr_epi32(1, 2, 3, 0); let src = _mm_setr_epi32(2, 3, 4, 1); - _mm_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1, 2, 3, 4]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_i32scatter_epi32() { + fn test_mm_mask_i32scatter_epi32() { let mut base_addr: [i32; 4] = [0; 4]; let vindex = _mm_setr_epi32(1, 2, 3, 0); let src = _mm_setr_epi32(2, 3, 4, 1); - _mm_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + unsafe { + _mm_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + } let expected = [0, 2, 0, 4]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_i32scatter_epi64() { + fn test_mm_i32scatter_epi64() { let mut base_addr: [i64; 2] = [0; 2]; let vindex = _mm_setr_epi32(1, 0, -1, -1); let src = _mm_setr_epi64x(2, 1); - _mm_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1, 2]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_i32scatter_epi64() { + fn test_mm_mask_i32scatter_epi64() { let mut base_addr: [i64; 2] = [0; 2]; let vindex = _mm_setr_epi32(1, 0, -1, -1); let src = _mm_setr_epi64x(2, 1); - _mm_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src); + unsafe { + _mm_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src); + } let expected = [0, 2]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_i32scatter_pd() { + fn test_mm_i32scatter_pd() { let mut base_addr: [f64; 2] = [0.; 2]; let vindex = _mm_setr_epi32(1, 0, -1, -1); let src = _mm_setr_pd(2., 1.); - _mm_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1., 2.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_i32scatter_pd() { + fn test_mm_mask_i32scatter_pd() { let mut base_addr: [f64; 2] = [0.; 2]; let vindex = _mm_setr_epi32(1, 0, -1, -1); let src = _mm_setr_pd(2., 1.); - _mm_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src); + unsafe { + _mm_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src); + } let expected = [0., 2.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_i32scatter_ps() { + fn test_mm_i32scatter_ps() { let mut base_addr: [f32; 4] = [0.; 4]; let vindex = _mm_setr_epi32(1, 2, 3, 0); let src = _mm_setr_ps(2., 3., 4., 1.); - _mm_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1., 2., 3., 4.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_i32scatter_ps() { + fn test_mm_mask_i32scatter_ps() { let mut base_addr: [f32; 4] = [0.; 4]; let vindex = _mm_setr_epi32(1, 2, 3, 0); let src = _mm_setr_ps(2., 3., 4., 1.); - _mm_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + unsafe { + _mm_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + } let expected = [0., 2., 0., 4.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_i64scatter_epi32() { + fn test_mm_i64scatter_epi32() { let mut base_addr: [i32; 2] = [0; 2]; let vindex = _mm_setr_epi64x(1, 0); let src = _mm_setr_epi32(2, 1, -1, -1); - _mm_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1, 2]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_i64scatter_epi32() { + fn test_mm_mask_i64scatter_epi32() { let mut base_addr: [i32; 2] = [0; 2]; let vindex = _mm_setr_epi64x(1, 0); let src = _mm_setr_epi32(2, 1, -1, -1); - _mm_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src); + unsafe { + _mm_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src); + } let expected = [0, 2]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_i64scatter_epi64() { + fn test_mm_i64scatter_epi64() { let mut base_addr: [i64; 2] = [0; 2]; let vindex = _mm_setr_epi64x(1, 0); let src = _mm_setr_epi64x(2, 1); - _mm_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1, 2]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_i64scatter_epi64() { + fn test_mm_mask_i64scatter_epi64() { let mut base_addr: [i64; 2] = [0; 2]; let vindex = _mm_setr_epi64x(1, 0); let src = _mm_setr_epi64x(2, 1); - _mm_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src); + unsafe { + _mm_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src); + } let expected = [0, 2]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_i64scatter_pd() { + fn test_mm_i64scatter_pd() { let mut base_addr: [f64; 2] = [0.; 2]; let vindex = _mm_setr_epi64x(1, 0); let src = _mm_setr_pd(2., 1.); - _mm_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1., 2.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_i64scatter_pd() { + fn test_mm_mask_i64scatter_pd() { let mut base_addr: [f64; 2] = [0.; 2]; let vindex = _mm_setr_epi64x(1, 0); let src = _mm_setr_pd(2., 1.); - _mm_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src); + unsafe { + _mm_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src); + } let expected = [0., 2.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_i64scatter_ps() { + fn test_mm_i64scatter_ps() { let mut base_addr: [f32; 2] = [0.; 2]; let vindex = _mm_setr_epi64x(1, 0); let src = _mm_setr_ps(2., 1., -1., -1.); - _mm_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1., 2.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_i64scatter_ps() { + fn test_mm_mask_i64scatter_ps() { let mut base_addr: [f32; 2] = [0.; 2]; let vindex = _mm_setr_epi64x(1, 0); let src = _mm_setr_ps(2., 1., -1., -1.); - _mm_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src); + unsafe { + _mm_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src); + } let expected = [0., 2.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_i32scatter_epi32() { + fn test_mm256_i32scatter_epi32() { let mut base_addr: [i32; 8] = [0; 8]; let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0); let src = _mm256_setr_epi32(2, 3, 4, 5, 6, 7, 8, 1); - _mm256_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm256_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1, 2, 3, 4, 5, 6, 7, 8]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_i32scatter_epi32() { + fn test_mm256_mask_i32scatter_epi32() { let mut base_addr: [i32; 8] = [0; 8]; let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0); let src = _mm256_setr_epi32(2, 3, 4, 5, 6, 7, 8, 1); - _mm256_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src); + unsafe { + _mm256_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src); + } let expected = [0, 2, 0, 4, 0, 6, 0, 8]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_i32scatter_epi64() { + fn test_mm256_i32scatter_epi64() { let mut base_addr: [i64; 4] = [0; 4]; let vindex = _mm_setr_epi32(1, 2, 3, 0); let src = _mm256_setr_epi64x(2, 3, 4, 1); - _mm256_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm256_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1, 2, 3, 4]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_i32scatter_epi64() { + fn test_mm256_mask_i32scatter_epi64() { let mut base_addr: [i64; 4] = [0; 4]; let vindex = _mm_setr_epi32(1, 2, 3, 0); let src = _mm256_setr_epi64x(2, 3, 4, 1); - _mm256_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + unsafe { + _mm256_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + } let expected = [0, 2, 0, 4]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_i32scatter_pd() { + fn test_mm256_i32scatter_pd() { let mut base_addr: [f64; 4] = [0.; 4]; let vindex = _mm_setr_epi32(1, 2, 3, 0); let src = _mm256_setr_pd(2., 3., 4., 1.); - _mm256_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm256_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1., 2., 3., 4.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_i32scatter_pd() { + fn test_mm256_mask_i32scatter_pd() { let mut base_addr: [f64; 4] = [0.; 4]; let vindex = _mm_setr_epi32(1, 2, 3, 0); let src = _mm256_setr_pd(2., 3., 4., 1.); - _mm256_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + unsafe { + _mm256_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + } let expected = [0., 2., 0., 4.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_i32scatter_ps() { + fn test_mm256_i32scatter_ps() { let mut base_addr: [f32; 8] = [0.; 8]; let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0); let src = _mm256_setr_ps(2., 3., 4., 5., 6., 7., 8., 1.); - _mm256_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm256_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1., 2., 3., 4., 5., 6., 7., 8.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_i32scatter_ps() { + fn test_mm256_mask_i32scatter_ps() { let mut base_addr: [f32; 8] = [0.; 8]; let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0); let src = _mm256_setr_ps(2., 3., 4., 5., 6., 7., 8., 1.); - _mm256_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src); + unsafe { + _mm256_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src); + } let expected = [0., 2., 0., 4., 0., 6., 0., 8.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_i64scatter_epi32() { + fn test_mm256_i64scatter_epi32() { let mut base_addr: [i32; 4] = [0; 4]; let vindex = _mm256_setr_epi64x(1, 2, 3, 0); let src = _mm_setr_epi32(2, 3, 4, 1); - _mm256_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm256_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1, 2, 3, 4]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_i64scatter_epi32() { + fn test_mm256_mask_i64scatter_epi32() { let mut base_addr: [i32; 4] = [0; 4]; let vindex = _mm256_setr_epi64x(1, 2, 3, 0); let src = _mm_setr_epi32(2, 3, 4, 1); - _mm256_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + unsafe { + _mm256_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + } let expected = [0, 2, 0, 4]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_i64scatter_epi64() { + fn test_mm256_i64scatter_epi64() { let mut base_addr: [i64; 4] = [0; 4]; let vindex = _mm256_setr_epi64x(1, 2, 3, 0); let src = _mm256_setr_epi64x(2, 3, 4, 1); - _mm256_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm256_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1, 2, 3, 4]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_i64scatter_epi64() { + fn test_mm256_mask_i64scatter_epi64() { let mut base_addr: [i64; 4] = [0; 4]; let vindex = _mm256_setr_epi64x(1, 2, 3, 0); let src = _mm256_setr_epi64x(2, 3, 4, 1); - _mm256_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + unsafe { + _mm256_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + } let expected = [0, 2, 0, 4]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_i64scatter_pd() { + fn test_mm256_i64scatter_pd() { let mut base_addr: [f64; 4] = [0.; 4]; let vindex = _mm256_setr_epi64x(1, 2, 3, 0); let src = _mm256_setr_pd(2., 3., 4., 1.); - _mm256_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm256_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1., 2., 3., 4.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_i64scatter_pd() { + fn test_mm256_mask_i64scatter_pd() { let mut base_addr: [f64; 4] = [0.; 4]; let vindex = _mm256_setr_epi64x(1, 2, 3, 0); let src = _mm256_setr_pd(2., 3., 4., 1.); - _mm256_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + unsafe { + _mm256_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + } let expected = [0., 2., 0., 4.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_i64scatter_ps() { + fn test_mm256_i64scatter_ps() { let mut base_addr: [f32; 4] = [0.; 4]; let vindex = _mm256_setr_epi64x(1, 2, 3, 0); let src = _mm_setr_ps(2., 3., 4., 1.); - _mm256_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src); + unsafe { + _mm256_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src); + } let expected = [1., 2., 3., 4.]; assert_eq!(expected, base_addr); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_i64scatter_ps() { + fn test_mm256_mask_i64scatter_ps() { let mut base_addr: [f32; 4] = [0.; 4]; let vindex = _mm256_setr_epi64x(1, 2, 3, 0); let src = _mm_setr_ps(2., 3., 4., 1.); - _mm256_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + unsafe { + _mm256_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src); + } let expected = [0., 2., 0., 4.]; assert_eq!(expected, base_addr); } @@ -12168,100 +12275,116 @@ mod tests { } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_loadu_epi64() { + const fn test_mm512_loadu_epi64() { let a = &[4, 3, 2, 5, -8, -9, -64, -50]; let p = a.as_ptr(); - let r = _mm512_loadu_epi64(black_box(p)); + let r = unsafe { _mm512_loadu_epi64(black_box(p)) }; let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_loadu_epi64() { + const fn test_mm256_loadu_epi64() { let a = &[4, 3, 2, 5]; let p = a.as_ptr(); - let r = _mm256_loadu_epi64(black_box(p)); + let r = unsafe { _mm256_loadu_epi64(black_box(p)) }; let e = _mm256_setr_epi64x(4, 3, 2, 5); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_loadu_epi64() { + const fn test_mm_loadu_epi64() { let a = &[4, 3]; let p = a.as_ptr(); - let r = _mm_loadu_epi64(black_box(p)); + let r = unsafe { _mm_loadu_epi64(black_box(p)) }; let e = _mm_setr_epi64x(4, 3); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtepi64_storeu_epi16() { + fn test_mm512_mask_cvtepi64_storeu_epi16() { let a = _mm512_set1_epi64(9); let mut r = _mm_undefined_si128(); - _mm512_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm512_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set1_epi16(9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtepi64_storeu_epi16() { + fn test_mm256_mask_cvtepi64_storeu_epi16() { let a = _mm256_set1_epi64x(9); let mut r = _mm_set1_epi16(0); - _mm256_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm256_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set_epi16(0, 0, 0, 0, 9, 9, 9, 9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtepi64_storeu_epi16() { + fn test_mm_mask_cvtepi64_storeu_epi16() { let a = _mm_set1_epi64x(9); let mut r = _mm_set1_epi16(0); - _mm_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 9, 9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtsepi64_storeu_epi16() { + fn test_mm512_mask_cvtsepi64_storeu_epi16() { let a = _mm512_set1_epi64(i64::MAX); let mut r = _mm_undefined_si128(); - _mm512_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm512_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set1_epi16(i16::MAX); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtsepi64_storeu_epi16() { + fn test_mm256_mask_cvtsepi64_storeu_epi16() { let a = _mm256_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi16(0); - _mm256_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm256_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set_epi16(0, 0, 0, 0, i16::MAX, i16::MAX, i16::MAX, i16::MAX); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtsepi64_storeu_epi16() { + fn test_mm_mask_cvtsepi64_storeu_epi16() { let a = _mm_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi16(0); - _mm_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MAX, i16::MAX); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtusepi64_storeu_epi16() { + fn test_mm512_mask_cvtusepi64_storeu_epi16() { let a = _mm512_set1_epi64(i64::MAX); let mut r = _mm_undefined_si128(); - _mm512_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm512_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set1_epi16(u16::MAX as i16); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtusepi64_storeu_epi16() { + fn test_mm256_mask_cvtusepi64_storeu_epi16() { let a = _mm256_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi16(0); - _mm256_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm256_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set_epi16( 0, 0, @@ -12276,46 +12399,56 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtusepi64_storeu_epi16() { + fn test_mm_mask_cvtusepi64_storeu_epi16() { let a = _mm_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi16(0); - _mm_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + unsafe { + _mm_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a); + } let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, u16::MAX as i16, u16::MAX as i16); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtepi64_storeu_epi8() { + fn test_mm512_mask_cvtepi64_storeu_epi8() { let a = _mm512_set1_epi64(9); let mut r = _mm_set1_epi8(0); - _mm512_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm512_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 9, 9, 9, 9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtepi64_storeu_epi8() { + fn test_mm256_mask_cvtepi64_storeu_epi8() { let a = _mm256_set1_epi64x(9); let mut r = _mm_set1_epi8(0); - _mm256_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm256_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtepi64_storeu_epi8() { + fn test_mm_mask_cvtepi64_storeu_epi8() { let a = _mm_set1_epi64x(9); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtsepi64_storeu_epi8() { + fn test_mm512_mask_cvtsepi64_storeu_epi8() { let a = _mm512_set1_epi64(i64::MAX); let mut r = _mm_set1_epi8(0); - _mm512_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm512_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } #[rustfmt::skip] let e = _mm_set_epi8( 0, 0, 0, 0, @@ -12327,10 +12460,12 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtsepi64_storeu_epi8() { + fn test_mm256_mask_cvtsepi64_storeu_epi8() { let a = _mm256_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi8(0); - _mm256_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm256_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } #[rustfmt::skip] let e = _mm_set_epi8( 0, 0, 0, 0, @@ -12342,19 +12477,23 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtsepi64_storeu_epi8() { + fn test_mm_mask_cvtsepi64_storeu_epi8() { let a = _mm_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MAX, i8::MAX); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtusepi64_storeu_epi8() { + fn test_mm512_mask_cvtusepi64_storeu_epi8() { let a = _mm512_set1_epi64(i64::MAX); let mut r = _mm_set1_epi8(0); - _mm512_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm512_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } #[rustfmt::skip] let e = _mm_set_epi8( 0, 0, 0, 0, @@ -12366,10 +12505,12 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtusepi64_storeu_epi8() { + fn test_mm256_mask_cvtusepi64_storeu_epi8() { let a = _mm256_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi8(0); - _mm256_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm256_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } #[rustfmt::skip] let e = _mm_set_epi8( 0, 0, 0, 0, @@ -12381,10 +12522,12 @@ mod tests { } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtusepi64_storeu_epi8() { + fn test_mm_mask_cvtusepi64_storeu_epi8() { let a = _mm_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi8(0); - _mm_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + unsafe { + _mm_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a); + } #[rustfmt::skip] let e = _mm_set_epi8( 0, 0, 0, 0, @@ -12396,112 +12539,136 @@ mod tests { } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtepi64_storeu_epi32() { + fn test_mm512_mask_cvtepi64_storeu_epi32() { let a = _mm512_set1_epi64(9); let mut r = _mm256_undefined_si256(); - _mm512_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a); + unsafe { + _mm512_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a); + } let e = _mm256_set1_epi32(9); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtepi64_storeu_epi32() { + fn test_mm256_mask_cvtepi64_storeu_epi32() { let a = _mm256_set1_epi64x(9); let mut r = _mm_set1_epi32(0); - _mm256_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a); + unsafe { + _mm256_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a); + } let e = _mm_set_epi32(9, 9, 9, 9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtepi64_storeu_epi32() { + fn test_mm_mask_cvtepi64_storeu_epi32() { let a = _mm_set1_epi64x(9); let mut r = _mm_set1_epi16(0); - _mm_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a); + unsafe { + _mm_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a); + } let e = _mm_set_epi32(0, 0, 9, 9); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtsepi64_storeu_epi32() { + fn test_mm512_mask_cvtsepi64_storeu_epi32() { let a = _mm512_set1_epi64(i64::MAX); let mut r = _mm256_undefined_si256(); - _mm512_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a); + unsafe { + _mm512_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a); + } let e = _mm256_set1_epi32(i32::MAX); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtsepi64_storeu_epi32() { + fn test_mm256_mask_cvtsepi64_storeu_epi32() { let a = _mm256_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi32(0); - _mm256_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a); + unsafe { + _mm256_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a); + } let e = _mm_set1_epi32(i32::MAX); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtsepi64_storeu_epi32() { + fn test_mm_mask_cvtsepi64_storeu_epi32() { let a = _mm_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi16(0); - _mm_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a); + unsafe { + _mm_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a); + } let e = _mm_set_epi32(0, 0, i32::MAX, i32::MAX); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - unsafe fn test_mm512_mask_cvtusepi64_storeu_epi32() { + fn test_mm512_mask_cvtusepi64_storeu_epi32() { let a = _mm512_set1_epi64(i64::MAX); let mut r = _mm256_undefined_si256(); - _mm512_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a); + unsafe { + _mm512_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a); + } let e = _mm256_set1_epi32(u32::MAX as i32); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm256_mask_cvtusepi64_storeu_epi32() { + fn test_mm256_mask_cvtusepi64_storeu_epi32() { let a = _mm256_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi32(0); - _mm256_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a); + unsafe { + _mm256_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a); + } let e = _mm_set1_epi32(u32::MAX as i32); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - unsafe fn test_mm_mask_cvtusepi64_storeu_epi32() { + fn test_mm_mask_cvtusepi64_storeu_epi32() { let a = _mm_set1_epi64x(i64::MAX); let mut r = _mm_set1_epi16(0); - _mm_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a); + unsafe { + _mm_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a); + } let e = _mm_set_epi32(0, 0, u32::MAX as i32, u32::MAX as i32); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_storeu_epi64() { + const fn test_mm512_storeu_epi64() { let a = _mm512_set1_epi64(9); let mut r = _mm512_set1_epi64(0); - _mm512_storeu_epi64(&mut r as *mut _ as *mut i64, a); + unsafe { + _mm512_storeu_epi64(&mut r as *mut _ as *mut i64, a); + } assert_eq_m512i(r, a); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_storeu_epi64() { + const fn test_mm256_storeu_epi64() { let a = _mm256_set1_epi64x(9); let mut r = _mm256_set1_epi64x(0); - _mm256_storeu_epi64(&mut r as *mut _ as *mut i64, a); + unsafe { + _mm256_storeu_epi64(&mut r as *mut _ as *mut i64, a); + } assert_eq_m256i(r, a); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_storeu_epi64() { + const fn test_mm_storeu_epi64() { let a = _mm_set1_epi64x(9); let mut r = _mm_set1_epi64x(0); - _mm_storeu_epi64(&mut r as *mut _ as *mut i64, a); + unsafe { + _mm_storeu_epi64(&mut r as *mut _ as *mut i64, a); + } assert_eq_m128i(r, a); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_load_epi64() { + const fn test_mm512_load_epi64() { #[repr(align(64))] struct Align { data: [i64; 8], // 64 bytes @@ -12510,63 +12677,69 @@ mod tests { data: [4, 3, 2, 5, -8, -9, -64, -50], }; let p = (a.data).as_ptr(); - let r = _mm512_load_epi64(black_box(p)); + let r = unsafe { _mm512_load_epi64(black_box(p)) }; let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50); assert_eq_m512i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_load_epi64() { + const fn test_mm256_load_epi64() { #[repr(align(64))] struct Align { data: [i64; 4], } let a = Align { data: [4, 3, 2, 5] }; let p = (a.data).as_ptr(); - let r = _mm256_load_epi64(black_box(p)); + let r = unsafe { _mm256_load_epi64(black_box(p)) }; let e = _mm256_set_epi64x(5, 2, 3, 4); assert_eq_m256i(r, e); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_load_epi64() { + const fn test_mm_load_epi64() { #[repr(align(64))] struct Align { data: [i64; 2], } let a = Align { data: [4, 3] }; let p = (a.data).as_ptr(); - let r = _mm_load_epi64(black_box(p)); + let r = unsafe { _mm_load_epi64(black_box(p)) }; let e = _mm_set_epi64x(3, 4); assert_eq_m128i(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_store_epi64() { + const fn test_mm512_store_epi64() { let a = _mm512_set1_epi64(9); let mut r = _mm512_set1_epi64(0); - _mm512_store_epi64(&mut r as *mut _ as *mut i64, a); + unsafe { + _mm512_store_epi64(&mut r as *mut _ as *mut i64, a); + } assert_eq_m512i(r, a); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm256_store_epi64() { + const fn test_mm256_store_epi64() { let a = _mm256_set1_epi64x(9); let mut r = _mm256_set1_epi64x(0); - _mm256_store_epi64(&mut r as *mut _ as *mut i64, a); + unsafe { + _mm256_store_epi64(&mut r as *mut _ as *mut i64, a); + } assert_eq_m256i(r, a); } #[simd_test(enable = "avx512f,avx512vl")] - const unsafe fn test_mm_store_epi64() { + const fn test_mm_store_epi64() { let a = _mm_set1_epi64x(9); let mut r = _mm_set1_epi64x(0); - _mm_store_epi64(&mut r as *mut _ as *mut i64, a); + unsafe { + _mm_store_epi64(&mut r as *mut _ as *mut i64, a); + } assert_eq_m128i(r, a); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_load_pd() { + const fn test_mm512_load_pd() { #[repr(align(64))] struct Align { data: [f64; 8], // 64 bytes @@ -12575,16 +12748,18 @@ mod tests { data: [4., 3., 2., 5., -8., -9., -64., -50.], }; let p = (a.data).as_ptr(); - let r = _mm512_load_pd(black_box(p)); + let r = unsafe { _mm512_load_pd(black_box(p)) }; let e = _mm512_setr_pd(4., 3., 2., 5., -8., -9., -64., -50.); assert_eq_m512d(r, e); } #[simd_test(enable = "avx512f")] - const unsafe fn test_mm512_store_pd() { + const fn test_mm512_store_pd() { let a = _mm512_set1_pd(9.); let mut r = _mm512_undefined_pd(); - _mm512_store_pd(&mut r as *mut _ as *mut f64, a); + unsafe { + _mm512_store_pd(&mut r as *mut _ as *mut f64, a); + } assert_eq_m512d(r, a); } diff --git a/library/stdarch/crates/core_arch/src/x86_64/fxsr.rs b/library/stdarch/crates/core_arch/src/x86_64/fxsr.rs index a24b44fb1f7e..28bf1951167a 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/fxsr.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/fxsr.rs @@ -77,12 +77,14 @@ mod tests { #[simd_test(enable = "fxsr")] #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri - unsafe fn test_fxsave64() { + fn test_fxsave64() { let mut a = FxsaveArea::new(); let mut b = FxsaveArea::new(); - fxsr::_fxsave64(a.ptr()); - fxsr::_fxrstor64(a.ptr()); - fxsr::_fxsave64(b.ptr()); + unsafe { + fxsr::_fxsave64(a.ptr()); + fxsr::_fxrstor64(a.ptr()); + fxsr::_fxsave64(b.ptr()); + } } } diff --git a/library/stdarch/crates/core_arch/src/x86_64/sse2.rs b/library/stdarch/crates/core_arch/src/x86_64/sse2.rs index b156af078a32..08dabf053d42 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/sse2.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/sse2.rs @@ -204,10 +204,12 @@ mod tests { // Miri cannot support this until it is clear how it fits in the Rust memory model // (non-temporal store) #[cfg_attr(miri, ignore)] - unsafe fn test_mm_stream_si64() { + fn test_mm_stream_si64() { let a: i64 = 7; let mut mem = boxed::Box::::new(-1); - _mm_stream_si64(ptr::addr_of_mut!(*mem), a); + unsafe { + _mm_stream_si64(ptr::addr_of_mut!(*mem), a); + } _mm_sfence(); assert_eq!(a, *mem); } diff --git a/library/stdarch/crates/core_arch/src/x86_64/xsave.rs b/library/stdarch/crates/core_arch/src/x86_64/xsave.rs index fa1454a822e3..30a7123315e5 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/xsave.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/xsave.rs @@ -132,37 +132,43 @@ mod tests { #[simd_test(enable = "xsave")] #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri - unsafe fn test_xsave64() { + fn test_xsave64() { let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers let mut a = XsaveArea::new(); let mut b = XsaveArea::new(); - _xsave64(a.ptr(), m); - _xrstor64(a.ptr(), m); - _xsave64(b.ptr(), m); + unsafe { + _xsave64(a.ptr(), m); + _xrstor64(a.ptr(), m); + _xsave64(b.ptr(), m); + } } #[simd_test(enable = "xsave,xsaveopt")] #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri - unsafe fn test_xsaveopt64() { + fn test_xsaveopt64() { let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers let mut a = XsaveArea::new(); let mut b = XsaveArea::new(); - _xsaveopt64(a.ptr(), m); - _xrstor64(a.ptr(), m); - _xsaveopt64(b.ptr(), m); + unsafe { + _xsaveopt64(a.ptr(), m); + _xrstor64(a.ptr(), m); + _xsaveopt64(b.ptr(), m); + } } #[simd_test(enable = "xsave,xsavec")] #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri - unsafe fn test_xsavec64() { + fn test_xsavec64() { let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers let mut a = XsaveArea::new(); let mut b = XsaveArea::new(); - _xsavec64(a.ptr(), m); - _xrstor64(a.ptr(), m); - _xsavec64(b.ptr(), m); + unsafe { + _xsavec64(a.ptr(), m); + _xrstor64(a.ptr(), m); + _xsavec64(b.ptr(), m); + } } } diff --git a/library/stdarch/crates/intrinsic-test/missing_aarch64.txt b/library/stdarch/crates/intrinsic-test/missing_aarch64.txt index 814756cefa40..3c1ac59e910e 100644 --- a/library/stdarch/crates/intrinsic-test/missing_aarch64.txt +++ b/library/stdarch/crates/intrinsic-test/missing_aarch64.txt @@ -1,3 +1,43 @@ +# Not supported by qemu (will throw illegal instruction) +vamax_f16 +vamaxq_f16 +vamin_f16 +vaminq_f16 +vscale_f16 +vscale_f32 +vscaleq_f16 +vscaleq_f32 +vscaleq_f64 +vluti2_lane_p16 +vluti2_lane_p8 +vluti2_lane_s16 +vluti2_lane_s8 +vluti2_lane_u16 +vluti2_lane_u8 +vluti2q_lane_p16 +vluti2q_lane_p8 +vluti2q_lane_s16 +vluti2q_lane_s8 +vluti2q_lane_u16 +vluti2_laneq_f16 +vluti2_lane_f16 +vluti2_laneq_f16 +vluti2_laneq_p16 +vluti2_laneq_p8 +vluti2_laneq_s16 +vluti2_laneq_s8 +vluti2_laneq_u16 +vluti2_laneq_u8 +vluti2q_lane_f16 +vluti2q_laneq_f16 +vluti2q_laneq_p16 +vluti2q_laneq_p8 +vluti2q_laneq_s16 +vluti2q_laneq_s8 +vluti2q_laneq_u16 +vluti2q_laneq_u8 +vluti2q_lane_u8 + # Not implemented in stdarch yet vbfdot_f32 vbfdot_lane_f32 @@ -30,18 +70,6 @@ vrnd32x_f64 vrnd32z_f64 vrnd64x_f64 vrnd64z_f64 -vluti2_lane_p16 -vluti2_lane_p8 -vluti2_lane_s16 -vluti2_lane_s8 -vluti2_lane_u16 -vluti2_lane_u8 -vluti2q_lane_p16 -vluti2q_lane_p8 -vluti2q_lane_s16 -vluti2q_lane_s8 -vluti2q_lane_u16 -vluti2q_lane_u8 vluti4q_lane_f16_x2 vluti4q_lane_p16_x2 vluti4q_lane_p8 diff --git a/library/stdarch/crates/intrinsic-test/missing_aarch64_be.txt b/library/stdarch/crates/intrinsic-test/missing_aarch64_be.txt index 1fa8fb7f1693..f3c4ffa3d064 100644 --- a/library/stdarch/crates/intrinsic-test/missing_aarch64_be.txt +++ b/library/stdarch/crates/intrinsic-test/missing_aarch64_be.txt @@ -38,6 +38,45 @@ vusdotq_lane_s32 vusdotq_laneq_s32 # Below are in common to missing_aarch64.txt +# Not supported by qemu (will throw illegal instruction) +vamax_f16 +vamaxq_f16 +vamin_f16 +vaminq_f16 +vscale_f16 +vscale_f32 +vscaleq_f16 +vscaleq_f32 +vscaleq_f64 +vluti2_lane_p16 +vluti2_lane_p8 +vluti2_lane_s16 +vluti2_lane_s8 +vluti2_lane_u16 +vluti2_lane_u8 +vluti2q_lane_p16 +vluti2q_lane_p8 +vluti2q_lane_s16 +vluti2q_lane_s8 +vluti2q_lane_u16 +vluti2_laneq_f16 +vluti2_lane_f16 +vluti2_laneq_f16 +vluti2_laneq_p16 +vluti2_laneq_p8 +vluti2_laneq_s16 +vluti2_laneq_s8 +vluti2_laneq_u16 +vluti2_laneq_u8 +vluti2q_lane_f16 +vluti2q_laneq_f16 +vluti2q_laneq_p16 +vluti2q_laneq_p8 +vluti2q_laneq_s16 +vluti2q_laneq_s8 +vluti2q_laneq_u16 +vluti2q_laneq_u8 +vluti2q_lane_u8 # Not implemented in stdarch yet vbfdot_f32 @@ -71,18 +110,6 @@ vrnd32x_f64 vrnd32z_f64 vrnd64x_f64 vrnd64z_f64 -vluti2_lane_p16 -vluti2_lane_p8 -vluti2_lane_s16 -vluti2_lane_s8 -vluti2_lane_u16 -vluti2_lane_u8 -vluti2q_lane_p16 -vluti2q_lane_p8 -vluti2q_lane_s16 -vluti2q_lane_s8 -vluti2q_lane_u16 -vluti2q_lane_u8 vluti4q_lane_f16_x2 vluti4q_lane_p16_x2 vluti4q_lane_p8 diff --git a/library/stdarch/crates/stdarch-gen-arm/README.md b/library/stdarch/crates/stdarch-gen-arm/README.md new file mode 100644 index 000000000000..4da14bcbb6c9 --- /dev/null +++ b/library/stdarch/crates/stdarch-gen-arm/README.md @@ -0,0 +1,300 @@ +# stdarch-gen-arm generator guide +## Running the generator +- Run: `cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec` +``` +$ cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec + Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.18s + Running `target/debug/stdarch-gen-arm crates/stdarch-gen-arm/spec` +``` +## Input/Output +### Input files (intrinsic YAML definitions) + - `crates/stdarch-gen-arm/spec//*.spec.yml` +### Output files + - Generated intrinsics: + - `crates/core_arch/src///generated.rs` + - Generated load/store tests: + - `crates/core_arch/src///ld_st_tests_.rs` + - Only generated when `test: { load: }` or `test: { store: }` is set for SVE/SVE2 intrinsics. +## `.spec.yml` file anatomy +``` +--- +Configs +--- +Variable definitions +--- + +Intrinsic definitions + +--- +``` +- If you're new to YAML syntax, consider [reviewing](https://quickref.me/yaml.html) some of the less obvious syntax and features. +- For example, mapping an attribute to a sequence can be done in two different ways: +```yaml +attribute: [item_a, item_b, item_c] +``` +or +```yaml +attribute: + - item_a + - item_b + - item_c +``` +## Configs +- Mappings defining top-level settings applied to all intrinsics: +- `arch_cfgs` + - Sequence of mappings specifying `arch_name`, `target_feature` (sequence), and `llvm_prefix`. +- `uses_neon_types`(_Optional_) + - A boolean specifying whether to emit NEON type imports in generated code. +- `auto_big_endian`(_Optional_) + - A boolean specifying whether to auto-generate big-endian shuffles when possible. +- `auto_llvm_sign_conversion`(_Optional_) + - A boolean specifying whether to auto-convert LLVM wrapper args to signed types. +## Variable definitions +- Defines YAML anchors/variables to avoid repetition. +- Commonly used for stability attributes, cfgs and target features. +## Intrinsic definitions +### Example +```yaml + - name: "vtst{neon_type[0].no}" + doc: "Signed compare bitwise Test bits nonzero" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmtst]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: safe + types: + - [int64x1_t, uint64x1_t, 'i64x1', 'i64x1::new(0)'] + - [int64x2_t, uint64x2_t, 'i64x2', 'i64x2::new(0, 0)'] + - [poly64x1_t, uint64x1_t, 'i64x1', 'i64x1::new(0)'] + - [poly64x2_t, uint64x2_t, 'i64x2', 'i64x2::new(0, 0)'] + compose: + - Let: [c, "{neon_type[0]}", {FnCall: [simd_and, [a, b]]}] + - Let: [d, "{type[2]}", "{type[3]}"] + - FnCall: [simd_ne, [c, {FnCall: [transmute, [d]]}]] +``` + +### Explanation of fields +- `name` + - The name of the intrinsic + - Often built from a base name followed by a type suffix +- `doc` (_Optional_) + - A string explaining the purpose of the intrinsic +- `static_defs` (_Optional_) + - A sequence of const generics of the format `"const : "` +- `arguments` + - A sequence of strings in the format `": "` +- `return_type` (_Optional_) + - A string specifying the return type. If omitted, the intrinsic returns `()`. +- `attr` (_Optional_) + - A sequence of items defining the attributes to be applied to the intrinsic. Often stability attributes, target features, or `assert_instr` tests. At least one of `attr` or `assert_instr` must be set. +- `target_features` (_Optional_) + - A sequence of target features to enable for this intrinsic (merged with any global `arch_cfgs` settings). +- `assert_instr` (_Optional_) + - A sequence of strings expected to be found in the assembly. Required if `attr` is not set. +- `safety` (_Optional_) + - Use `safe`, or map `unsafe:` to a sequence of unsafety comments: + - `custom: ""` + - `uninitialized` + - `pointer_offset`, `pointer_offset_vnum`, or `dereference` (optionally qualified with `predicated`, `predicated_non_faulting`, or `predicated_first_faulting`) + - `unpredictable_on_fault` + - `non_temporal` + - `neon` + - `no_provenance: ""` +- `substitutions` (_Optional_) + - Mappings of custom wildcard names to either `MatchSize` or `MatchKind` expressions +- `types` + - A sequence or sequence of sequences specifying the types to use when producing each intrinsic variant. These sequences can then be indexed by wildcards. +- `constraints` (_Optional_) + - A sequence of mappings. Each specifies a variable and a constraint. The available mappings are: + - Assert a variable's value exists in a sequence of i32's + - Usage: `{ variable: , any_values: [,...] }` + - Assert a variable's value exists in a range (inclusive) + - Usage: `{ variable: , range: [, ] }` + - Assert a variable's value exists in a range via a match (inclusive) + - Usage: `{ variable: , range: }` + - Assert a variable's value does not exceed the number of elements in a SVE type ``. + - Usage: `{ variable: , sve_max_elems_type: }` + - Assert a variable's value does not exceed the number of elements in a vector type ``. + - Usage: `{ variable: , vec_max_elems_type: }` +- `predication_methods` (_Optional_) + - Configuration for predicate-form variants. Only used when the intrinsic name includes an `_m*_` wildcard (e.g., `{_mx}`, `{_mxz}`). + - `zeroing_method`: Required when requesting `_z`; either `{ drop: }` to remove an argument and replace it with a zero initialiser, or `{ select: }` to select zeros into a predicate. + - `dont_care_method`: How `_x` should be implemented (`inferred`, `as_zeroing`, or `as_merging`). +- `compose` + - A sequence of expressions that make up the body of the intrinsic +- `big_endian_inverse` (_Optional_) + - A boolean, default false. If true, generates two implementations of each intrinsic variant, one for each endianness, and attempts to automatically generate the required bit swizzles +- `visibility` (_Optional_) + - Function visibility. One of `public` (default) or `private`. +- `n_variant_op` (_Optional_) + - Enables generation of an `_n` variant when the intrinsic name includes the `{_n}` wildcard. Set to the operand name that should be splattered for the `_n` form. +- `test` (_Optional_) + - When set, load/store tests are automatically generated. + - A mapping of either `load` or `store` to a number that indexes `types` to specify the type that the test should be addressing in memory. +### Expressions +#### Common +- `Let` + - Defines a variable + - Usage: `Let: [, , ]` +- `Const` + - Defines a const + - Usage: `Const: [, , ]` +- `Assign` + - Performs variable assignment + - Usage: `Assign: [, ]` +- `FnCall` + - Performs a function call + - Usage: `FnCall: [, [, ... ], [, ...](optional), ]` +- `MacroCall` + - Performs a macro call + - Usage: `MacroCall: [, ]` +- `MethodCall` + - Performs a method call + - Usage: `MethodCall: [, , [, ... ]]` +- `LLVMLink` + - Creates an LLVM link and stores the function's name in the wildcard `{llvm_link}` for later use in subsequent expressions. + - If left unset, the arguments and return type inherit from the intrinsic's signature by default. The links will also be set automatically if unset. + - Usage: +```yaml +LLVMLink: + name: + arguments: [, ... ](optional) + return_type: (optional) + links: (optional) + - link: + arch: + - ... +``` +- `Identifier` + - Emits a symbol. Prepend with a `$` to treat it as a scope variable, which engages variable tracking and enables inference. For example, `my_function_name` for a generic symbol or `$my_variable` for a variable. + - Usage `Identifier: [, ]` +- `CastAs` + - Casts an expression to an unchecked type + - Usage: `CastAs: [, ]` +- `MatchSize` + - Allows for conditional generation depending on the size of a specified type + - Usage: +```yaml +MatchSize: + - + - default: + byte(optional): + halfword(optional): + doubleword(optional): +``` +- `MatchKind` + - Allows for conditional generation depending on the kind of a specified type +```yaml +MatchKind: + - + - default: + float(optional): + unsigned(optional): +``` +#### Rarely Used +- `IntConstant` + - Constant signed integer expression + - Usage: `IntConstant: ` +- `FloatConstant` + - Constant floating-point expression + - Usage: `FloatConstant: ` +- `BoolConstant` + - Constant boolean expression + - Usage: `BoolConstant: ` +- `Array` + - An array of expressions + - Usage: `Array: [, ...]` +- `SvUndef` + - Returns the LLVM `undef` symbol + - Usage: `SvUndef` +- `Multiply` + - Simply `*` + - Usage: `Multiply: [, ]` +- `Xor` + - Simply `^` + - Usage: `Xor: [, ]` +- `ConvertConst` + - Converts the specified constant to the specified type's kind + - Usage: `ConvertConst: [, ]` +- `Type` + - Yields the given type in the Rust representation + - Usage: `Type: []` + +### Wildstrings +- Wildstrings let you take advantage of wildcards. +- For example, they are often used in intrinsic names `name: "vtst{neon_type[0].no}"` +- As shown above, wildcards are identified by the surrounding curly brackets. +- Double curly brackets can be used to escape wildcard functionality if you need literal curly brackets in the generated intrinsic. +### Wildcards +Wildcards are heavily used in the spec. They let you write generalised definitions for a group of intrinsics that generate multiple variants. The wildcard itself is replaced with the relevant string in each variant. +Ignoring endianness, for each row in the `types` field of an intrinsic in the spec, a variant of the intrinsic will be generated. That row's contents can be indexed by the wildcards. Below is the behaviour of each wildcard. +- `type[]` + - Replaced in each variant with the value in the indexed position in the relevant row of the `types` field. + - For unnested sequences of `types` (i.e., `types` is a sequence where each element is a single item, not another sequence), the square brackets can be omitted. Simply: `type` +- `neon_type[]` + - Extends the behaviour of `type` with some NEON-specific features and inference. + - Tuples: This wildcard can also be written as `neon_type_x` where `n` is in the set `{2,3,4}`. This generates the `n`-tuple variant of the (inferred) NEON type. + - Suffixes: These modify the behaviour of the wildcard from simple substitution. + - `no` - normal behaviour. Tries to do as much work as it can for you, inferring when to emit: + - Regular type-size suffixes: `_s8`, `_u16`, `_f32`, ... + - `q` variants for double-width (128b) vector types: `q_s8`, `q_u16`, `q_f32`, ... + - `_x` variants for tuple vector types: `_s8_x2`, `_u32_x3`, `_f64_x4`, ... + - As well as any combination of the above: `q_s16_x16` ... + - Most of the other suffixes modify the normal behaviour by disabling features or adding new ones. (See table below) +- `sve_type[]` + - Similar to `neon_type`, but without the suffixes. +- `size[]` + - The size (in bits) of the indexed type. +- `size_minus_one[]` + - Emits the size (in bits) of the indexed type minus one. +- `size_literal[]` + - The literal representation of the indexed type. + - `b`: byte, `h`: halfword, `w`: word, or `d`: double. +- `type_kind[]` + - The literal representation of the indexed type's kind. + - `f`: float, `s`: signed, `u`: unsigned, `p`: polynomial, `b`: boolean. +- `size_in_bytes_log2[]` + - Log2 of the size of the indexed type in *bytes*. +- `predicate[]` + - SVE predicate vector type inferred from the indexed type. +- `max_predicate` + - The same as predicate, but uses the largest type in the relevant `types` sequence/row. +- `_n` + - Emits the current N-variant suffix when `n_variant_op` is configured. +- ` as ` + - If `` evaluates to a vector, it produces a vector of the same shape, but with `` as the base type. +- `llvm_link` + - If the `LLVMLink` mapping has been set for an intrinsic, this will give the name of the link. +- `_m*` + - Predicate form masks. Use wildcards such as `{_mx}` or `{_mxz}` to expand merging/don't-care/zeroing variants according to the mask. +- `` + - You may simply call upon wildcards defined under `substitutions`. +### neon_type suffixes + +| suffix | implication | +| ----------------- | --------------------------------------------- | +| `.no` | Normal | +| `.noq` | Never include `q`s | +| `.nox` | Never include `_x`s | +| `.N` | Include `_n_`, e.g., `_n_s8` | +| `.noq_N` | Include `_n_`, but never `q`s | +| `.dup` | Include `_dup_`, e.g., `_dup_s8` | +| `.dup_nox` | Include `_dup_` but never `_x`s | +| `.lane` | Include `_lane_`, e.g., `_lane_s8` | +| `.lane_nox` | Include `_lane_`, but never `_x`s | +| `.rot90` | Include `_rot90_`, e.g., `_rot90_s8` | +| `.rot180` | Include `_rot180_`, e.g., `_rot180_s8` | +| `.rot270` | Include `_rot270_`, e.g., `_rot270_s8` | +| `.rot90_lane` | Include `_rot90_lane_` | +| `.rot180_lane` | Include `_rot180_lane_` | +| `.rot270_lane` | Include `_rot270_lane_` | +| `.rot90_laneq` | Include `_rot90_laneq_` | +| `.rot180_laneq` | Include `_rot180_laneq_` | +| `.rot270_laneq` | Include `_rot270_laneq_` | +| `.base` | Produce only the size, e.g., `8`, `16` | +| `.u` | Produce the type's unsigned equivalent | +| `.laneq_nox` | Include `_laneq_`, but never `_x`s | +| `.tuple` | Produce only the size of the tuple, e.g., `3` | +| `.base_byte_size` | Produce only the size in bytes. | + diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml index a951343e0183..a9bc377924dd 100644 --- a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml +++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml @@ -66,6 +66,14 @@ neon-unstable-feat-lut: &neon-unstable-feat-lut aarch64-stable-jscvt: &aarch64-stable-jscvt FnCall: [stable, ['feature = "stdarch_aarch64_jscvt"', 'since = "CURRENT_RUSTC_VERSION"']] +# #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +neon-unstable-feat-lrcpc3: &neon-unstable-feat-lrcpc3 + FnCall: [unstable, ['feature = "stdarch_neon_feat_lrcpc3"', 'issue = "none"']] + +# #[unstable(feature = "stdarch_neon_fp8", issue = "none")] +neon-unstable-fp8: &neon-unstable-fp8 + FnCall: [unstable, ['feature = "stdarch_neon_fp8"', 'issue = "none"']] + # #[cfg(target_endian = "little")] little-endian: &little-endian FnCall: [cfg, ['target_endian = "little"']] @@ -4398,6 +4406,116 @@ intrinsics: - - FnCall: [transmute, [a]] - FnCall: [transmute, [b]] + - name: "vldap1{neon_type[1].lane_nox}" + doc: "Load-acquire RCpc one single-element structure to one lane of one register" + arguments: ["ptr: {type[0]}", "src: {type[1]}"] + static_defs: ["const LANE: i32"] + return_type: "{type[1]}" + safety: + unsafe: [neon] + attr: + - FnCall: [target_feature, ['enable = "neon,rcpc3"']] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-unstable-feat-lrcpc3 + types: + - ['*const i64', int64x1_t, 'static_assert!', 'LANE == 0'] + - ['*const i64', int64x2_t,'static_assert_uimm_bits!', 'LANE, 1'] + compose: + - FnCall: ['{type[2]}', ['{type[3]}']] + - Let: + - "atomic_src" + - FnCall: ["crate::sync::atomic::AtomicI64::from_ptr", ['ptr as *mut i64']] + - Identifier: [';', Symbol] + - FnCall: + - simd_insert! + - - src + - "LANE as u32" + - MethodCall: + - "atomic_src" + - load + - ["crate::sync::atomic::Ordering::Acquire"] + + - name: "vldap1{neon_type[1].lane_nox}" + doc: "Load-acquire RCpc one single-element structure to one lane of one register" + arguments: ["ptr: {type[0]}","src: {type[1]}"] + static_defs: ["const LANE: i32"] + return_type: "{type[1]}" + safety: + unsafe: [neon] + attr: + - FnCall: [rustc_legacy_const_generics, ["2"]] + - FnCall: [target_feature, ['enable = "neon,rcpc3"']] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]] + - *neon-unstable-feat-lrcpc3 + types: + - ['*const u64', uint64x1_t,'static_assert!', 'LANE == 0',''] + #- ['*const f64', float64x1_t,'static_assert!', 'LANE == 0',''] # Fails due to bad IR gen from rust + - ['*const p64', poly64x1_t,'static_assert!', 'LANE == 0',''] + - ['*const u64', uint64x2_t,'static_assert_uimm_bits!', 'LANE, 1','q'] + - ['*const f64', float64x2_t,'static_assert_uimm_bits!', 'LANE, 1','q'] + - ['*const p64', poly64x2_t,'static_assert_uimm_bits!', 'LANE, 1','q'] + compose: + - FnCall: ['{type[2]}', ['{type[3]}']] + - FnCall: + - transmute + - - FnCall: + - 'vldap1{type[4]}_lane_s64::' + - - "ptr as *mut i64" + - FnCall: [transmute,[src]] + + - name: "vstl1{neon_type[1].lane_nox}" + doc: "Store-Release a single-element structure from one lane of one register." + arguments: ["ptr: {type[0]}", "val: {neon_type[1]}"] + static_defs: ["const LANE: i32"] + safety: safe + attr: + - FnCall: [target_feature, ['enable = "neon,rcpc3"']] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-unstable-feat-lrcpc3 + types: + - ['*mut i64', int64x1_t,'static_assert!', 'LANE == 0'] + - ['*mut i64', int64x2_t,'static_assert_uimm_bits!', 'LANE, 1'] + compose: + - FnCall: ['{type[2]}', ['{type[3]}']] + - Let: + - "atomic_dst" + - "ptr as *mut crate::sync::atomic::AtomicI64" + - Identifier: [';', Symbol] + - Let: + - "lane" + - i64 + - FnCall: [simd_extract!, [val, 'LANE as u32']] + - MethodCall: + - "(*atomic_dst)" + - store + - [FnCall: [transmute, [lane]],"crate::sync::atomic::Ordering::Release"] + + - name: "vstl1{neon_type[1].lane_nox}" + doc: "Store-Release a single-element structure from one lane of one register." + arguments: ["ptr: {type[0]}", "val: {neon_type[1]}"] + static_defs: ["const LANE: i32"] + safety: safe + attr: + - FnCall: [target_feature, ['enable = "neon,rcpc3"']] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-unstable-feat-lrcpc3 + types: + - ['*mut u64', uint64x1_t, 'static_assert!', 'LANE == 0',''] + - ['*mut f64', float64x1_t,'static_assert!', 'LANE == 0',''] + - ['*mut p64', poly64x1_t, 'static_assert!', 'LANE == 0',''] + - ['*mut u64', uint64x2_t ,'static_assert_uimm_bits!', 'LANE, 1','q'] + - ['*mut f64', float64x2_t,'static_assert_uimm_bits!', 'LANE, 1','q'] + - ['*mut p64', poly64x2_t ,'static_assert_uimm_bits!', 'LANE, 1','q'] + compose: + - FnCall: ['{type[2]}', ['{type[3]}']] + - FnCall: + - "vstl1{type[4]}_lane_s64::" + - - "ptr as *mut i64" + - FnCall: [transmute, [val]] + - name: "vst1{neon_type[1].lane_nox}" doc: "Store multiple single-element structures from one, two, three, or four registers" arguments: ["a: {type[0]}", "b: {neon_type[1]}"] @@ -5081,56 +5199,6 @@ intrinsics: arch: aarch64,arm64ec - FnCall: ['_vst4{neon_type[1].lane_nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'LANE as i64', 'a as _']] - - name: "vusdot{neon_type[0].laneq_nox}" - doc: "Dot product index form with unsigned and signed integers" - arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] - return_type: "{neon_type[0]}" - attr: - - *neon-i8mm - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [usdot, 'LANE = 3']]}]] - - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']] - static_defs: ["const LANE: i32"] - safety: safe - types: - - [int32x2_t, uint8x8_t, int8x16_t, '[LANE as u32, LANE as u32]',''] - - [int32x4_t, uint8x16_t, int8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] - compose: - - FnCall: [static_assert_uimm_bits!, [LANE, '2']] - - Let: [c, int32x4_t, {FnCall: ['vreinterpretq_s32_s8', [c]]}] - - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]}] - - FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: ['vreinterpret{type[4]}_s8_s32', [c]]}]] - - - name: "vsudot{neon_type[0].laneq_nox}" - doc: "Dot product index form with signed and unsigned integers" - arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] - return_type: "{neon_type[0]}" - attr: - - *neon-i8mm - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sudot, 'LANE = 3']]}]] - - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']] - static_defs: ["const LANE: i32"] - safety: safe - types: - - [int32x2_t, int8x8_t, uint8x16_t, '[LANE as u32, LANE as u32]', uint32x2_t] - - [int32x4_t, int8x16_t, uint8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]', uint32x4_t] - compose: - - FnCall: [static_assert_uimm_bits!, [LANE, 2]] - - Let: - - c - - uint32x4_t - - FnCall: [transmute, [c]] - - Let: - - c - - "{type[4]}" - - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]] - - FnCall: - - "vusdot{neon_type[0].no}" - - - a - - FnCall: [transmute, [c]] - - b - - name: "vmul{neon_type.no}" doc: Multiply arguments: ["a: {neon_type}", "b: {neon_type}"] @@ -6552,7 +6620,6 @@ intrinsics: - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]}] - FnCall: ["vcmla{neon_type[0].rot270}", [a, b, c]] - - name: "vcmla{neon_type[0].rot270_lane}" doc: Floating-point complex multiply accumulate arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] @@ -6574,66 +6641,6 @@ intrinsics: - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]}] - FnCall: ["vcmla{neon_type[0].rot270}", [a, b, c]] - - name: "vdot{neon_type[0].laneq_nox}" - doc: Dot product arithmetic (indexed) - arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] - return_type: "{neon_type[0]}" - static_defs: ["const LANE: i32"] - attr: - - FnCall: [target_feature, ['enable = "neon,dotprod"']] - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sdot, 'LANE = 0']]}]] - - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']] - safety: safe - types: - - [int32x2_t, int8x8_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32]', ''] - - [int32x4_t, int8x16_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] - compose: - - FnCall: [static_assert_uimm_bits!, [LANE, '2']] - - Let: - - c - - "{neon_type[3]}" - - FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] - - FnCall: - - "vdot{neon_type[0].no}" - - - a - - b - - FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]] - - - name: "vdot{neon_type[0].laneq_nox}" - doc: Dot product arithmetic (indexed) - arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] - return_type: "{neon_type[0]}" - static_defs: ["const LANE: i32"] - attr: - - FnCall: [target_feature, ['enable = "neon,dotprod"']] - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [udot, 'LANE = 0']]}]] - - FnCall: [rustc_legacy_const_generics, ['3']] - - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']] - safety: safe - types: - - [uint32x2_t, uint8x8_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32]',''] - - [uint32x4_t, uint8x16_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] - compose: - - FnCall: [static_assert_uimm_bits!, [LANE, '2']] - - Let: - - c - - "{neon_type[3]}" - - FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]] - - Let: - - c - - "{neon_type[0]}" - - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] - - FnCall: - - "vdot{neon_type[0].no}" - - - a - - b - - FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]] - - name: "vmax{neon_type.no}" doc: Maximum (vector) arguments: ["a: {neon_type}", "b: {neon_type}"] @@ -13966,10 +13973,12 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [target_feature, ['enable = "neon,faminmax"']] - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [famax]]}]] - FnCall: [unstable, ['feature = "faminmax"', 'issue = "137933"']] safety: safe types: + - float16x4_t + - float16x8_t - float32x2_t - float32x4_t - float64x2_t @@ -13986,10 +13995,12 @@ intrinsics: return_type: "{neon_type}" attr: - FnCall: [target_feature, ['enable = "neon,faminmax"']] - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [famin]]}]] - FnCall: [unstable, ['feature = "faminmax"', 'issue = "137933"']] safety: safe types: + - float16x4_t + - float16x8_t - float32x2_t - float32x4_t - float64x2_t @@ -14030,36 +14041,101 @@ intrinsics: arch: aarch64,arm64ec - FnCall: ['_vluti2{neon_type[0].lane_nox}', [a, b, LANE]] + - name: "vluti2{neon_type[0].laneq_nox}" + doc: "Lookup table read with 2-bit indices" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [target_feature, ['enable = {type[4]}']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'INDEX = 1']]}]] + - *neon-unstable-feat-lut + - FnCall: [rustc_legacy_const_generics, ['2']] + static_defs: ["const INDEX: i32"] + safety: + unsafe: [neon] + types: + - [int8x8_t, uint8x16_t, int8x16_t, 'INDEX >= 0 && INDEX <= 3', '"neon,lut"'] + - [int8x16_t, uint8x16_t, int8x16_t, 'INDEX >= 0 && INDEX <= 3', '"neon,lut"'] + - [int16x4_t, uint8x16_t, int16x8_t, 'INDEX >= 0 && INDEX <= 7', '"neon,lut"'] + - [int16x8_t, uint8x16_t, int16x8_t, 'INDEX >= 0 && INDEX <= 7', '"neon,lut"'] + compose: + - FnCall: ['static_assert!', ['{type[3]}']] + - LLVMLink: + name: "vluti2{neon_type[0].laneq_nox}" + arguments: + - 'a: {neon_type[0]}' + - 'b: {neon_type[1]}' + - 'n: i32' + links: + - link: "llvm.aarch64.neon.vluti2.laneq.{neon_type[2]}.{neon_type[0]}" + arch: aarch64,arm64ec + - FnCall: ['_vluti2{neon_type[0].laneq_nox}', [a, b, INDEX]] + - name: "vluti2{neon_type[0].lane_nox}" doc: "Lookup table read with 2-bit indices" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - FnCall: [target_feature, ['enable = "neon,lut"']] - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 1']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'INDEX = 1']]}]] - *neon-unstable-feat-lut - FnCall: [rustc_legacy_const_generics, ['2']] - static_defs: ["const LANE: i32"] + static_defs: ["const INDEX: i32"] safety: unsafe: [neon] types: - - [uint8x8_t, uint8x8_t, uint8x16_t, 'LANE >= 0 && LANE <= 1', 'int8x8_t'] - - [uint8x16_t, uint8x8_t, uint8x16_t, 'LANE >= 0 && LANE <= 1', 'int8x16_t'] - - [poly8x8_t, uint8x8_t, poly8x16_t, 'LANE >= 0 && LANE <= 1', 'int8x8_t'] - - [poly8x16_t, uint8x8_t, poly8x16_t, 'LANE >= 0 && LANE <= 1', 'int8x16_t'] - - [uint16x4_t, uint8x8_t, uint16x8_t, 'LANE >= 0 && LANE <= 3', 'int16x4_t'] - - [uint16x8_t, uint8x8_t, uint16x8_t, 'LANE >= 0 && LANE <= 3', 'int16x8_t'] - - [poly16x4_t, uint8x8_t, poly16x8_t, 'LANE >= 0 && LANE <= 3', 'int16x4_t'] - - [poly16x8_t, uint8x8_t, poly16x8_t, 'LANE >= 0 && LANE <= 3', 'int16x8_t'] + - [uint8x8_t, uint8x8_t, uint8x16_t, 'INDEX >= 0 && INDEX <= 1', 'int8x8_t'] + - [uint8x16_t, uint8x8_t, uint8x16_t, 'INDEX >= 0 && INDEX <= 1', 'int8x16_t'] + - [poly8x8_t, uint8x8_t, poly8x16_t, 'INDEX >= 0 && INDEX <= 1', 'int8x8_t'] + - [poly8x16_t, uint8x8_t, poly8x16_t, 'INDEX >= 0 && INDEX <= 1', 'int8x16_t'] + - [uint16x4_t, uint8x8_t, uint16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x4_t'] + - [uint16x8_t, uint8x8_t, uint16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x8_t'] + - [poly16x4_t, uint8x8_t, poly16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x4_t'] + - [poly16x8_t, uint8x8_t, poly16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x8_t'] + - [float16x4_t, uint8x8_t, float16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x4_t'] + - [float16x8_t, uint8x8_t, float16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x8_t'] compose: - FnCall: ['static_assert!', ['{type[3]}']] - FnCall: - transmute - - FnCall: - - 'vluti2{neon_type[4].lane_nox}::' + - 'vluti2{neon_type[4].lane_nox}::' - - FnCall: [transmute, [a]] - b + - name: "vluti2{neon_type[0].laneq_nox}" + doc: "Lookup table read with 2-bit indices" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [target_feature, ['enable = "neon,lut"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'INDEX = 1']]}]] + - *neon-unstable-feat-lut + - FnCall: [rustc_legacy_const_generics, ['2']] + static_defs: ["const INDEX: i32"] + safety: + unsafe: [neon] + types: + - [uint8x8_t, uint8x16_t, uint8x16_t, 'INDEX >= 0 && INDEX <= 3', 'int8x8_t'] + - [uint8x16_t, uint8x16_t, uint8x16_t, 'INDEX >= 0 && INDEX <= 3', 'int8x16_t'] + - [poly8x8_t, uint8x16_t, poly8x16_t, 'INDEX >= 0 && INDEX <= 3', 'int8x8_t'] + - [poly8x16_t, uint8x16_t, poly8x16_t, 'INDEX >= 0 && INDEX <= 3', 'int8x16_t'] + - [uint16x4_t, uint8x16_t, uint16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x4_t'] + - [uint16x8_t, uint8x16_t, uint16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x8_t'] + - [poly16x4_t, uint8x16_t, poly16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x4_t'] + - [poly16x8_t, uint8x16_t, poly16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x8_t'] + - [float16x4_t, uint8x16_t, float16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x4_t'] + - [float16x8_t, uint8x16_t, float16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x8_t'] + compose: + - FnCall: ['static_assert!', ['{type[3]}']] + - FnCall: + - transmute + - - FnCall: + - 'vluti2{neon_type[4].laneq_nox}::' + - - FnCall: [transmute, [a]] + - b + + - name: "vluti4{neon_type[0].lane_nox}" doc: "Lookup table read with 4-bit indices" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] @@ -14268,6 +14344,28 @@ intrinsics: - - FnCall: [transmute, [a]] - b + - name: "vscale{neon_type[0].no}" + doc: "Multi-vector floating-point adjust exponent" + arguments: ["vn: {type[0]}", "vm: {type[1]}"] + return_type: "{type[0]}" + attr: + - *neon-unstable-fp8 + - FnCall: [target_feature, ['enable = "neon,fp8"']] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [fscale]]}]] + safety: safe + types: + - [float16x4_t, int16x4_t] + - [float16x8_t, int16x8_t] + - [float32x2_t, int32x2_t] + - [float32x4_t, int32x4_t] + - [float64x2_t, int64x2_t] + compose: + - LLVMLink: + name: "vscale{neon_type[0].no}" + links: + - link: "llvm.aarch64.neon.fp8.fscale.{neon_type[0]}" + arch: aarch64,arm64ec + - name: "__jcvt" doc: "Floating-point JavaScript convert to signed fixed-point, rounding toward zero" arguments: ["a: {type}"] diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml index c7a333d7f75e..52748a4cc056 100644 --- a/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml +++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml @@ -7096,6 +7096,132 @@ intrinsics: - FnCall: [simd_cast, [b]] - FnCall: [simd_sub, [c, d]] + - name: "vusdot{neon_type[0].laneq_nox}" + doc: "Dot product index form with unsigned and signed integers" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure. + attr: + - *neon-v8 + - *neon-i8mm + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vusdot, 'LANE = 3']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [usdot, 'LANE = 3']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']] + static_defs: ["const LANE: i32"] + safety: safe + types: + - [int32x2_t, uint8x8_t, int8x16_t, '[LANE as u32, LANE as u32]',''] + - [int32x4_t, uint8x16_t, int8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '2']] + - Let: [c, int32x4_t, {FnCall: [transmute, [c]]}] + - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]}] + - FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: [transmute, [c]]}]] + #- FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: ['vreinterpret{type[4]}_s8_s32', [c]]}]] + + - name: "vsudot{neon_type[0].laneq_nox}" + doc: "Dot product index form with signed and unsigned integers" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-v8 + - *neon-i8mm + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsudot, 'LANE = 1']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sudot, 'LANE = 3']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']] + static_defs: ["const LANE: i32"] + safety: safe + types: + - [int32x2_t, int8x8_t, uint8x16_t, '[LANE as u32, LANE as u32]', uint32x2_t] + - [int32x4_t, int8x16_t, uint8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]', uint32x4_t] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, 2]] + - Let: + - c + - uint32x4_t + - FnCall: [transmute, [c]] + - Let: + - c + - "{type[4]}" + - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]] + - FnCall: + - "vusdot{neon_type[0].no}" + - - a + - FnCall: [transmute, [c]] + - b + + - name: "vdot{neon_type[0].laneq_nox}" + doc: Dot product arithmetic (indexed) + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + static_defs: ["const LANE: i32"] + big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure. + attr: + - *neon-v8 + - FnCall: [target_feature, ['enable = "neon,dotprod"']] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsdot, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sdot, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']] + safety: safe + types: + - [int32x2_t, int8x8_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32]', ''] + - [int32x4_t, int8x16_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '2']] + - Let: + - c + - "{neon_type[3]}" + - FnCall: [transmute, [c]] + #- FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]] + - Let: + - c + - "{neon_type[0]}" + - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] + - FnCall: + - "vdot{neon_type[0].no}" + - - a + - b + - FnCall: [transmute, [c]] + #- FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]] + + - name: "vdot{neon_type[0].laneq_nox}" + doc: Dot product arithmetic (indexed) + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + static_defs: ["const LANE: i32"] + big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure. + attr: + - *neon-v8 + - FnCall: [target_feature, ['enable = "neon,dotprod"']] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vudot, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [udot, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']] + safety: safe + types: + - [uint32x2_t, uint8x8_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32]',''] + - [uint32x4_t, uint8x16_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '2']] + - Let: + - c + - "{neon_type[3]}" + - FnCall: [transmute, [c]] + #- FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]] + - Let: + - c + - "{neon_type[0]}" + - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] + - FnCall: + - "vdot{neon_type[0].no}" + - - a + - b + - FnCall: [transmute, [c]] + #- FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]] + - name: "vdot{neon_type[0].no}" doc: Dot product arithmetic (vector) arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] @@ -8785,7 +8911,6 @@ intrinsics: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] - - *neon-fp16 - *neon-not-arm-stable-fp16 - *neon-cfg-arm-unstable - *target-not-arm64ec @@ -8849,7 +8974,6 @@ intrinsics: - *neon-v8 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] - - *neon-fp16 - *neon-not-arm-stable-fp16 - *neon-cfg-arm-unstable - *target-not-arm64ec diff --git a/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs b/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs index 71301c5ba6ce..ce427d54b355 100644 --- a/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs +++ b/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs @@ -840,7 +840,7 @@ impl fmt::Display for UnsafetyComment { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { match self { Self::Custom(s) => s.fmt(f), - Self::Neon => write!(f, "Neon instrinsic unsafe"), + Self::Neon => write!(f, "Neon intrinsic unsafe"), Self::Uninitialized => write!( f, "This creates an uninitialized value, and may be unsound (like \ diff --git a/library/stdarch/intrinsics_data/arm_intrinsics.json b/library/stdarch/intrinsics_data/arm_intrinsics.json index 19c655cd6d24..bce85d19a10f 100644 --- a/library/stdarch/intrinsics_data/arm_intrinsics.json +++ b/library/stdarch/intrinsics_data/arm_intrinsics.json @@ -223,6 +223,141 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vscale_f16", + "arguments": [ + "float16x4_t a", + "int16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vscaleq_f16", + "arguments": [ + "float16x8_t a", + "int16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vscale_f32", + "arguments": [ + "float32x2_t a", + "int32x2_t b" + ], + "return_type": { + "value": "float32x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vscaleq_f32", + "arguments": [ + "float32x4_t a", + "int32x4_t b" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vscaleq_f64", + "arguments": [ + "float64x2_t a", + "int64x2_t b" + ], + "return_type": { + "value": "float64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vaba_s16", @@ -34733,6 +34868,230 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vldap1_lane_u64", + "arguments": [ + "uint64_t const * ptr", + "uint64x1_t src", + "const int lane" + ], + "return_type": { + "value": "uint64x1_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1_lane_s64", + "arguments": [ + "int64_t const * ptr", + "int64x1_t src", + "const int lane" + ], + "return_type": { + "value": "int64x1_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1q_lane_u64", + "arguments": [ + "uint64_t const * ptr", + "uint64x2_t src", + "const int lane" + ], + "return_type": { + "value": "uint64x2_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1q_lane_s64", + "arguments": [ + "int64_t const * ptr", + "int64x2_t src", + "const int lane" + ], + "return_type": { + "value": "int64x2_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1_lane_p64", + "arguments": [ + "poly64_t const * ptr", + "poly64x1_t src", + "const int lane" + ], + "return_type": { + "value": "poly64x1_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1q_lane_p64", + "arguments": [ + "poly64_t const * ptr", + "poly64x2_t src", + "const int lane" + ], + "return_type": { + "value": "poly64x2_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1q_lane_f64", + "arguments": [ + "float64_t const * ptr", + "float64x2_t src", + "const int lane" + ], + "return_type": { + "value": "float64x2_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld1_dup_f16", @@ -109193,6 +109552,262 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vstl1_lane_f64", + "arguments": [ + "float64_t * ptr", + "float64x1_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STL1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vstl1q_lane_f64", + "arguments": [ + "float64_t * ptr", + "float64x2_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STL1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vstl1_lane_p64", + "arguments": [ + "poly64_t * ptr", + "poly64x1_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STL1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vstl1q_lane_p64", + "arguments": [ + "poly64_t * ptr", + "poly64x2_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STL1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vstl1_lane_u64", + "arguments": [ + "uint64_t * ptr", + "uint64x1_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STL1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vstl1q_lane_u64", + "arguments": [ + "uint64_t * ptr", + "uint64x2_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STL1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vstl1_lane_s64", + "arguments": [ + "int64_t * ptr", + "int64x1_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STL1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vstl1q_lane_s64", + "arguments": [ + "int64_t * ptr", + "int64x2_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STL1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vsub_f16", @@ -118682,6 +119297,60 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vamin_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMIN" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vaminq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMIN" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vamin_f32", @@ -118763,6 +119432,60 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vamax_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMAX" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vamaxq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMAX" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vamax_f32", @@ -118844,6 +119567,531 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_lane_f16", + "arguments": [ + "float16x4_t a", + "uint8x8_t b", + "const int index" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_lane_s16", + "arguments": [ + "int16x4_t a", + "uint8x8_t b", + "const int index" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_lane_u16", + "arguments": [ + "uint16x4_t a", + "uint8x8_t b", + "const int index" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_lane_p16", + "arguments": [ + "poly16x4_t a", + "uint8x8_t b", + "const int index" + ], + "return_type": { + "value": "poly16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_laneq_f16", + "arguments": [ + "float16x4_t a", + "uint8x16_t b", + "const int index" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_laneq_s16", + "arguments": [ + "int16x4_t a", + "uint8x16_t b", + "const int index" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_laneq_u16", + "arguments": [ + "uint16x4_t a", + "uint8x16_t b", + "const int index" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_laneq_p16", + "arguments": [ + "poly16x4_t a", + "uint8x16_t b", + "const int index" + ], + "return_type": { + "value": "poly16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_lane_f16", + "arguments": [ + "float16x8_t a", + "uint8x8_t b", + "const int index" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_lane_s16", + "arguments": [ + "int16x8_t a", + "uint8x8_t b", + "const int index" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_lane_u16", + "arguments": [ + "uint16x8_t a", + "uint8x8_t b", + "const int index" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_lane_p16", + "arguments": [ + "poly16x8_t a", + "uint8x8_t b", + "const int index" + ], + "return_type": { + "value": "poly16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_laneq_f16", + "arguments": [ + "float16x8_t a", + "uint8x16_t b", + "const int index" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_laneq_s16", + "arguments": [ + "int16x8_t a", + "uint8x16_t b", + "const int index" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_laneq_u16", + "arguments": [ + "uint16x8_t a", + "uint8x16_t b", + "const int index" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vluti2_lane_u8", @@ -118862,7 +120110,7 @@ "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, "maximum": 1 }, @@ -118897,7 +120145,7 @@ "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, "maximum": 1 }, @@ -118932,7 +120180,7 @@ "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, "maximum": 1 }, @@ -118967,7 +120215,7 @@ "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, "maximum": 1 }, @@ -119002,7 +120250,7 @@ "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, "maximum": 1 }, @@ -119037,7 +120285,7 @@ "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, "maximum": 1 }, @@ -119056,28 +120304,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vluti2_lane_u16", + "name": "vluti2_laneq_u8", "arguments": [ - "uint16x4_t a", - "uint8x8_t b", - "const int lane" + "uint8x8_t a", + "uint8x16_t b", + "const int index" ], "return_type": { - "value": "uint16x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, "maximum": 3 }, "r": { - "register": "Vd.8H" + "register": "Vd.16B" } }, "Architectures": [ @@ -119091,28 +120339,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vluti2q_lane_u16", + "name": "vluti2q_laneq_u8", "arguments": [ - "uint16x8_t a", - "uint8x8_t b", - "const int lane" + "uint8x16_t a", + "uint8x16_t b", + "const int index" ], "return_type": { - "value": "uint16x8_t" + "value": "uint8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, "maximum": 3 }, "r": { - "register": "Vd.8H" + "register": "Vd.16B" } }, "Architectures": [ @@ -119126,28 +120374,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vluti2_lane_s16", + "name": "vluti2_laneq_s8", "arguments": [ - "int16x4_t a", - "uint8x8_t b", - "const int lane" + "int8x8_t a", + "uint8x16_t b", + "const int index" ], "return_type": { - "value": "int16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, "maximum": 3 }, "r": { - "register": "Vd.8H" + "register": "Vd.16B" } }, "Architectures": [ @@ -119161,28 +120409,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vluti2q_lane_s16", + "name": "vluti2q_laneq_s8", "arguments": [ - "int16x8_t a", - "uint8x8_t b", - "const int lane" + "int8x16_t a", + "uint8x16_t b", + "const int index" ], "return_type": { - "value": "int16x8_t" + "value": "int8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, "maximum": 3 }, "r": { - "register": "Vd.8H" + "register": "Vd.16B" } }, "Architectures": [ @@ -119196,28 +120444,28 @@ }, { "SIMD_ISA": "Neon", - "name": "vluti2_lane_p16", + "name": "vluti2_laneq_p8", "arguments": [ - "poly16x4_t a", - "uint8x8_t b", - "const int lane" + "poly8x8_t a", + "uint8x16_t b", + "const int index" ], "return_type": { - "value": "poly16x8_t" + "value": "poly8x16_t" }, "Arguments_Preparation": { "a": { - "register": "Vn.8H" + "register": "Vn.16B" }, "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, "maximum": 3 }, "r": { - "register": "Vd.8H" + "register": "Vd.16B" } }, "Architectures": [ @@ -119231,11 +120479,46 @@ }, { "SIMD_ISA": "Neon", - "name": "vluti2q_lane_p16", + "name": "vluti2q_laneq_p8", + "arguments": [ + "poly8x16_t a", + "uint8x16_t b", + "const int index" + ], + "return_type": { + "value": "poly8x16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.16B" + }, + "b": { + "register": "Vm" + }, + "index": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_laneq_p16", "arguments": [ "poly16x8_t a", - "uint8x8_t b", - "const int lane" + "uint8x16_t b", + "const int index" ], "return_type": { "value": "poly16x8_t" @@ -119247,9 +120530,9 @@ "b": { "register": "Vm" }, - "lane": { + "index": { "minimum": 0, - "maximum": 3 + "maximum": 7 }, "r": { "register": "Vd.8H" diff --git a/library/sysroot/Cargo.toml b/library/sysroot/Cargo.toml index a18868082916..b2069ef6a613 100644 --- a/library/sysroot/Cargo.toml +++ b/library/sysroot/Cargo.toml @@ -25,7 +25,6 @@ backtrace = ["std/backtrace"] backtrace-trace-only = ["std/backtrace-trace-only"] compiler-builtins-c = ["std/compiler-builtins-c"] compiler-builtins-mem = ["std/compiler-builtins-mem"] -compiler-builtins-no-f16-f128 = ["std/compiler-builtins-no-f16-f128"] debug_refcell = ["std/debug_refcell"] llvm-libunwind = ["std/llvm-libunwind"] system-llvm-libunwind = ["std/system-llvm-libunwind"] diff --git a/package.json b/package.json index 1fe87b181669..66596cab4268 100644 --- a/package.json +++ b/package.json @@ -1,6 +1,6 @@ { "dependencies": { - "browser-ui-test": "^0.23.2", + "browser-ui-test": "^0.23.3", "es-check": "^9.4.4", "eslint": "^8.57.1", "typescript": "^5.8.3" diff --git a/src/bootstrap/src/core/build_steps/check.rs b/src/bootstrap/src/core/build_steps/check.rs index f983c59f9bf8..8bbd03ac3afa 100644 --- a/src/bootstrap/src/core/build_steps/check.rs +++ b/src/bootstrap/src/core/build_steps/check.rs @@ -87,7 +87,7 @@ impl Step for Std { Mode::Std, SourceType::InTree, target, - Kind::Check, + builder.config.cmd.kind(), ); std_cargo(builder, target, &mut cargo, &self.crates); @@ -97,7 +97,7 @@ impl Step for Std { } let _guard = builder.msg( - Kind::Check, + builder.config.cmd.kind(), format_args!("library artifacts{}", crate_description(&self.crates)), Mode::Std, build_compiler, diff --git a/src/ci/citool/Cargo.toml b/src/ci/citool/Cargo.toml index 539edf60033a..0b1f2fe79bf7 100644 --- a/src/ci/citool/Cargo.toml +++ b/src/ci/citool/Cargo.toml @@ -5,7 +5,7 @@ edition = "2024" [dependencies] anyhow = "1" -askama = "0.15.1" +askama = "0.15.4" clap = { version = "4.5", features = ["derive"] } csv = "1" diff = "0.1" diff --git a/src/ci/docker/scripts/build-clang.sh b/src/ci/docker/scripts/build-clang.sh index 905c40773042..b3b1dc47e2ef 100755 --- a/src/ci/docker/scripts/build-clang.sh +++ b/src/ci/docker/scripts/build-clang.sh @@ -5,7 +5,7 @@ set -ex source shared.sh # Try to keep the LLVM version here in sync with src/ci/scripts/install-clang.sh -LLVM=llvmorg-21.1.0-rc2 +LLVM=llvmorg-22.1.0-rc2 mkdir llvm-project cd llvm-project diff --git a/src/librustdoc/Cargo.toml b/src/librustdoc/Cargo.toml index 3c5d01c7201b..033d3ecdd03d 100644 --- a/src/librustdoc/Cargo.toml +++ b/src/librustdoc/Cargo.toml @@ -10,7 +10,7 @@ path = "lib.rs" [dependencies] # tidy-alphabetical-start arrayvec = { version = "0.7", default-features = false } -askama = { version = "0.15.1", default-features = false, features = ["alloc", "config", "derive"] } +askama = { version = "0.15.4", default-features = false, features = ["alloc", "config", "derive"] } base64 = "0.21.7" indexmap = { version = "2", features = ["serde"] } itertools = "0.12" diff --git a/src/librustdoc/clean/mod.rs b/src/librustdoc/clean/mod.rs index 9d6038367419..1c9154238657 100644 --- a/src/librustdoc/clean/mod.rs +++ b/src/librustdoc/clean/mod.rs @@ -3178,7 +3178,7 @@ fn clean_assoc_item_constraint<'tcx>( } fn clean_bound_vars<'tcx>( - bound_vars: &ty::List, + bound_vars: &ty::List>, cx: &mut DocContext<'tcx>, ) -> Vec { bound_vars diff --git a/src/librustdoc/html/static/css/noscript.css b/src/librustdoc/html/static/css/noscript.css index 6f44854b6914..363cec3116a9 100644 --- a/src/librustdoc/html/static/css/noscript.css +++ b/src/librustdoc/html/static/css/noscript.css @@ -163,7 +163,7 @@ nav.sub { --headings-border-bottom-color: #d2d2d2; --border-color: #e0e0e0; --button-background-color: #f0f0f0; - --right-side-color: grey; + --right-side-color: #d0d0d0; --code-attribute-color: #999; --toggles-color: #999; --toggle-filter: invert(100%); diff --git a/src/librustdoc/html/static/css/rustdoc.css b/src/librustdoc/html/static/css/rustdoc.css index 6c34d31cc918..9e47f80a7fe2 100644 --- a/src/librustdoc/html/static/css/rustdoc.css +++ b/src/librustdoc/html/static/css/rustdoc.css @@ -359,7 +359,8 @@ summary.hideme, .rustdoc-breadcrumbs, .search-switcher, /* This selector is for the items listed in the "all items" page. */ -ul.all-items { +ul.all-items, +.deprecated-count { font-family: "Fira Sans", Arial, NanumBarunGothic, sans-serif; } @@ -2671,6 +2672,18 @@ However, it's not needed with smaller screen width because the doc/code block is display: none; } +.deprecated-count { + display: none; +} +/* +The `:not(:empty)` is a little trick to not have to add conditions in JS to hide/show the marker. +It's entirely based on whether it has content and if the setting is enabled. +*/ +.hide-deprecated-items .deprecated-count:not(:empty) { + display: block; + margin: 10px 0; +} + /* WARNING: RUSTDOC_MOBILE_BREAKPOINT MEDIA QUERY If you update this line, then you also need to update the line with the same warning @@ -3286,7 +3299,7 @@ by default. --headings-border-bottom-color: #d2d2d2; --border-color: #e0e0e0; --button-background-color: #f0f0f0; - --right-side-color: grey; + --right-side-color: #d0d0d0; --code-attribute-color: #999; --toggles-color: #999; --toggle-filter: invert(100%); diff --git a/src/librustdoc/html/static/js/search.js b/src/librustdoc/html/static/js/search.js index 9961c1447ec2..55ff48846dcb 100644 --- a/src/librustdoc/html/static/js/search.js +++ b/src/librustdoc/html/static/js/search.js @@ -158,6 +158,7 @@ const REGEX_INVALID_TYPE_FILTER = /[^a-z]/ui; const MAX_RESULTS = 200; const NO_TYPE_FILTER = -1; +const DEPRECATED_COUNT_SELECTOR = "deprecated-count"; /** * The [edit distance] is a metric for measuring the difference between two strings. @@ -4904,7 +4905,12 @@ async function addTab(results, query, display, finishedCallback, isTypeSearch) { let output = document.createElement("ul"); output.className = "search-results " + extraClass; + const deprecatedCountElem = document.createElement("span"); + deprecatedCountElem.className = DEPRECATED_COUNT_SELECTOR; + output.appendChild(deprecatedCountElem); + let count = 0; + let deprecatedCount = 0; /** @type {Promise[]} */ const descList = []; @@ -4922,6 +4928,10 @@ async function addTab(results, query, display, finishedCallback, isTypeSearch) { link.className = "result-" + type; if (obj.item.deprecated) { link.className += " deprecated"; + deprecatedCount += 1; + const plural = deprecatedCount > 1 ? "s" : ""; + deprecatedCountElem.innerText = + `${deprecatedCount} deprecated item${plural} hidden by setting`; } link.href = obj.href; @@ -5411,7 +5421,7 @@ function registerSearchEvents() { const active = document.activeElement; if (active) { const previous = active.previousElementSibling; - if (previous) { + if (previous && previous.className !== DEPRECATED_COUNT_SELECTOR) { // @ts-expect-error previous.focus(); } else { diff --git a/src/llvm-project b/src/llvm-project index 00d23d10dc48..41256ab128f2 160000 --- a/src/llvm-project +++ b/src/llvm-project @@ -1 +1 @@ -Subproject commit 00d23d10dc48c6bb9d57ba96d4a748d85d77d0c7 +Subproject commit 41256ab128f2af613b4a16771cda6baa36b55f45 diff --git a/src/tools/clippy/clippy_utils/src/ty/mod.rs b/src/tools/clippy/clippy_utils/src/ty/mod.rs index 2926a329ce16..0f11df98fc17 100644 --- a/src/tools/clippy/clippy_utils/src/ty/mod.rs +++ b/src/tools/clippy/clippy_utils/src/ty/mod.rs @@ -782,15 +782,15 @@ pub fn is_c_void(cx: &LateContext<'_>, ty: Ty<'_>) -> bool { } } -pub fn for_each_top_level_late_bound_region( - ty: Ty<'_>, - f: impl FnMut(BoundRegion) -> ControlFlow, +pub fn for_each_top_level_late_bound_region<'cx, B>( + ty: Ty<'cx>, + f: impl FnMut(BoundRegion<'cx>) -> ControlFlow, ) -> ControlFlow { struct V { index: u32, f: F, } - impl<'tcx, B, F: FnMut(BoundRegion) -> ControlFlow> TypeVisitor> for V { + impl<'tcx, B, F: FnMut(BoundRegion<'tcx>) -> ControlFlow> TypeVisitor> for V { type Result = ControlFlow; fn visit_region(&mut self, r: Region<'tcx>) -> Self::Result { if let RegionKind::ReBound(BoundVarIndexKind::Bound(idx), bound) = r.kind() diff --git a/src/tools/generate-copyright/Cargo.toml b/src/tools/generate-copyright/Cargo.toml index 66b9f394409b..17b5c727964f 100644 --- a/src/tools/generate-copyright/Cargo.toml +++ b/src/tools/generate-copyright/Cargo.toml @@ -8,7 +8,7 @@ description = "Produces a manifest of all the copyrighted materials in the Rust [dependencies] anyhow = "1.0.65" -askama = "0.15.1" +askama = "0.15.4" cargo_metadata = "0.21" serde = { version = "1.0.147", features = ["derive"] } serde_json = "1.0.85" diff --git a/src/tools/miri/rust-version b/src/tools/miri/rust-version index cc1ff32815cd..3e8514346218 100644 --- a/src/tools/miri/rust-version +++ b/src/tools/miri/rust-version @@ -1 +1 @@ -e96bb7e44fbcc23c1e6009e8d0ee8ab208668fb4 +35a31ba763976907cd38ba88743a3aefbaf8ffff diff --git a/src/tools/miri/tests/pass/intrinsics/portable-simd.rs b/src/tools/miri/tests/pass/intrinsics/portable-simd.rs index 56c000633e58..6c5e06518f56 100644 --- a/src/tools/miri/tests/pass/intrinsics/portable-simd.rs +++ b/src/tools/miri/tests/pass/intrinsics/portable-simd.rs @@ -471,7 +471,7 @@ fn simd_ops_i32() { fn simd_mask() { use std::intrinsics::simd::*; - let intmask = Mask::from_int(i32x4::from_array([0, -1, 0, 0])); + let intmask = Mask::from_simd(i32x4::from_array([0, -1, 0, 0])); assert_eq!(intmask, Mask::from_array([false, true, false, false])); assert_eq!(intmask.to_array(), [false, true, false, false]); @@ -486,8 +486,8 @@ fn simd_mask() { // Also directly call intrinsic, to test both kinds of return types. unsafe { - let bitmask1: u16 = simd_bitmask(mask.to_int()); - let bitmask2: [u8; 2] = simd_bitmask(mask.to_int()); + let bitmask1: u16 = simd_bitmask(mask.to_simd()); + let bitmask2: [u8; 2] = simd_bitmask(mask.to_simd()); if cfg!(target_endian = "little") { assert_eq!(bitmask1, 0b1010001101001001); assert_eq!(bitmask2, [0b01001001, 0b10100011]); @@ -506,8 +506,8 @@ fn simd_mask() { assert_eq!(bitmask, 0b1000); assert_eq!(Mask::::from_bitmask(bitmask), mask); unsafe { - let bitmask1: u8 = simd_bitmask(mask.to_int()); - let bitmask2: [u8; 1] = simd_bitmask(mask.to_int()); + let bitmask1: u8 = simd_bitmask(mask.to_simd()); + let bitmask2: [u8; 1] = simd_bitmask(mask.to_simd()); if cfg!(target_endian = "little") { assert_eq!(bitmask1, 0b1000); assert_eq!(bitmask2, [0b1000]); diff --git a/src/tools/tidy/src/main.rs b/src/tools/tidy/src/main.rs index 94c24f11ed12..0d9a22556dfa 100644 --- a/src/tools/tidy/src/main.rs +++ b/src/tools/tidy/src/main.rs @@ -32,6 +32,7 @@ fn main() { let npm: PathBuf = env::args_os().nth(5).expect("need name/path of npm command").into(); let root_manifest = root_path.join("Cargo.toml"); + let typos_toml = root_path.join("typos.toml"); let src_path = root_path.join("src"); let tests_path = root_path.join("tests"); let library_path = root_path.join("library"); @@ -143,6 +144,7 @@ fn main() { check!(edition, &library_path); check!(alphabetical, &root_manifest); + check!(alphabetical, &typos_toml); check!(alphabetical, &src_path); check!(alphabetical, &tests_path); check!(alphabetical, &compiler_path); diff --git a/src/tools/tidy/src/ui_tests.rs b/src/tools/tidy/src/ui_tests.rs index bf51810810a6..b5643034d45c 100644 --- a/src/tools/tidy/src/ui_tests.rs +++ b/src/tools/tidy/src/ui_tests.rs @@ -73,6 +73,57 @@ pub fn check(root_path: &Path, tidy_ctx: TidyCtx) { )); } } + + // The list of subdirectories in ui tests. + // Compare previous subdirectory with current subdirectory + // to sync with `tests/ui/README.md`. + // See + let mut prev_line = String::new(); + let mut is_sorted = true; + let documented_subdirs: BTreeSet<_> = include_str!("../../../../tests/ui/README.md") + .lines() + .filter_map(|line| { + static_regex!(r"^##.*?`(?[^`]+)`").captures(line).map(|cap| { + let dir = &cap["dir"]; + // FIXME(reddevilmidzy) normalize subdirs title in tests/ui/README.md + if dir.ends_with('/') { + dir.strip_suffix('/').unwrap().to_string() + } else { + dir.to_string() + } + }) + }) + .inspect(|line| { + if prev_line.as_str() > line.as_str() { + is_sorted = false; + } + + prev_line = line.clone(); + }) + .collect(); + let filesystem_subdirs = collect_ui_tests_subdirs(&path); + let is_modified = !filesystem_subdirs.eq(&documented_subdirs); + + if !is_sorted { + check.error("`tests/ui/README.md` is not in order"); + } + if is_modified { + for directory in documented_subdirs.symmetric_difference(&filesystem_subdirs) { + if documented_subdirs.contains(directory) { + check.error(format!( + "ui subdirectory `{directory}` is listed in `tests/ui/README.md` but does not exist in the filesystem" + )); + } else { + check.error(format!( + "ui subdirectory `{directory}` exists in the filesystem but is not documented in `tests/ui/README.md`" + )); + } + } + check.error( + "`tests/ui/README.md` subdirectory listing is out of sync with the filesystem. \ + Please add or remove subdirectory entries (## headers with backtick-wrapped names) to match the actual directories in `tests/ui/`" + ); + } } fn deny_new_top_level_ui_tests(check: &mut RunningCheck, tests_path: &Path) { @@ -137,6 +188,24 @@ fn recursively_check_ui_tests<'issues>( remaining_issue_names } +fn collect_ui_tests_subdirs(path: &Path) -> BTreeSet { + let ui = path.join("ui"); + let entries = std::fs::read_dir(ui.as_path()).unwrap(); + + entries + .filter_map(|entry| entry.ok()) + .map(|entry| entry.path()) + .filter(|path| path.is_dir()) + .map(|dir_path| { + let dir_path = dir_path.strip_prefix(path).unwrap(); + format!( + "tests/{}", + dir_path.to_string_lossy().replace(std::path::MAIN_SEPARATOR_STR, "/") + ) + }) + .collect() +} + fn check_unexpected_extension(check: &mut RunningCheck, file_path: &Path, ext: &str) { const EXPECTED_TEST_FILE_EXTENSIONS: &[&str] = &[ "rs", // test source files diff --git a/tests/assembly-llvm/asm/loongarch-type.rs b/tests/assembly-llvm/asm/loongarch-type.rs index e0a7940f89a3..5efad583a39d 100644 --- a/tests/assembly-llvm/asm/loongarch-type.rs +++ b/tests/assembly-llvm/asm/loongarch-type.rs @@ -1,10 +1,14 @@ //@ add-minicore -//@ revisions: loongarch32 loongarch64 +//@ revisions: loongarch32s loongarch32r loongarch64 //@ assembly-output: emit-asm -//@[loongarch32] compile-flags: --target loongarch32-unknown-none -//@[loongarch32] needs-llvm-components: loongarch +//@[loongarch32s] compile-flags: --target loongarch32-unknown-none -Ctarget-feature=+32s +//@[loongarch32s] needs-llvm-components: loongarch + +//@[loongarch32r] compile-flags: --target loongarch32-unknown-none +//@[loongarch32r] needs-llvm-components: loongarch +//@[loongarch32r] min-llvm-version: 22 //@[loongarch64] compile-flags: --target loongarch64-unknown-none //@[loongarch64] needs-llvm-components: loongarch @@ -28,8 +32,12 @@ extern "C" { // CHECK-LABEL: sym_fn: // CHECK: #APP -// CHECK: pcalau12i $t0, %got_pc_hi20(extern_func) -// CHECK: ld.{{[wd]}} $t0, $t0, %got_pc_lo12(extern_func) +// loongarch64: pcalau12i $t0, %got_pc_hi20(extern_func) +// loongarch64: ld.d $t0, $t0, %got_pc_lo12(extern_func) +// loongarch32s: pcalau12i $t0, %got_pc_hi20(extern_func) +// loongarch32s: ld.w $t0, $t0, %got_pc_lo12(extern_func) +// loongarch32r: pcaddu12i $t0, %got_pcadd_hi20(extern_func) +// loongarch32r: ld.w $t0, $t0, %got_pcadd_lo12(.Lpcadd_hi0) // CHECK: #NO_APP #[no_mangle] pub unsafe fn sym_fn() { @@ -38,8 +46,13 @@ pub unsafe fn sym_fn() { // CHECK-LABEL: sym_static: // CHECK: #APP -// CHECK: pcalau12i $t0, %got_pc_hi20(extern_static) -// CHECK: ld.{{[wd]}} $t0, $t0, %got_pc_lo12(extern_static) +// loongarch64: pcalau12i $t0, %got_pc_hi20(extern_static) +// loongarch64: ld.d $t0, $t0, %got_pc_lo12(extern_static) +// loongarch32s: pcalau12i $t0, %got_pc_hi20(extern_static) +// loongarch32s: ld.w $t0, $t0, %got_pc_lo12(extern_static) +// loongarch32r: pcaddu12i $t0, %got_pcadd_hi20(extern_static) +// loongarch32r: ld.w $t0, $t0, %got_pcadd_lo12(.Lpcadd_hi1) + // CHECK: #NO_APP #[no_mangle] pub unsafe fn sym_static() { diff --git a/tests/codegen-llvm/gpu_offload/control_flow.rs b/tests/codegen-llvm/gpu_offload/control_flow.rs index 28ee9c85b0ed..1a3d3cd7a778 100644 --- a/tests/codegen-llvm/gpu_offload/control_flow.rs +++ b/tests/codegen-llvm/gpu_offload/control_flow.rs @@ -12,8 +12,7 @@ // CHECK: define{{( dso_local)?}} void @main() // CHECK-NOT: define -// CHECK: %EmptyDesc = alloca %struct.__tgt_bin_desc, align 8 -// CHECK-NEXT: %.offload_baseptrs = alloca [1 x ptr], align 8 +// CHECK: %.offload_baseptrs = alloca [1 x ptr], align 8 // CHECK-NEXT: %.offload_ptrs = alloca [1 x ptr], align 8 // CHECK-NEXT: %.offload_sizes = alloca [1 x i64], align 8 // CHECK-NEXT: %kernel_args = alloca %struct.__tgt_kernel_arguments, align 8 diff --git a/tests/codegen-llvm/gpu_offload/gpu_host.rs b/tests/codegen-llvm/gpu_offload/gpu_host.rs index 27ff6f325aa0..d0bc34ec66b2 100644 --- a/tests/codegen-llvm/gpu_offload/gpu_host.rs +++ b/tests/codegen-llvm/gpu_offload/gpu_host.rs @@ -2,9 +2,10 @@ //@ no-prefer-dynamic //@ needs-offload -// This test is verifying that we generate __tgt_target_data_*_mapper before and after a call to the -// kernel_1. Better documentation to what each global or variable means is available in the gpu -// offload code, or the LLVM offload documentation. +// This test is verifying that we generate __tgt_target_data_*_mapper before and after a call to +// __tgt_target_kernel, and initialize all needed variables. It also verifies some related globals. +// Better documentation to what each global or variable means is available in the gpu offload code, +// or the LLVM offload documentation. #![feature(rustc_attrs)] #![feature(core_intrinsics)] @@ -17,10 +18,8 @@ fn main() { core::hint::black_box(&x); } -#[unsafe(no_mangle)] -#[inline(never)] pub fn kernel_1(x: &mut [f32; 256]) { - core::intrinsics::offload(_kernel_1, [256, 1, 1], [32, 1, 1], (x,)) + core::intrinsics::offload(kernel_1, [256, 1, 1], [32, 1, 1], (x,)) } #[unsafe(no_mangle)] @@ -33,75 +32,75 @@ pub fn _kernel_1(x: &mut [f32; 256]) { // CHECK: %struct.ident_t = type { i32, i32, i32, i32, ptr } // CHECK: %struct.__tgt_offload_entry = type { i64, i16, i16, i32, ptr, ptr, i64, i64, ptr } -// CHECK: %struct.__tgt_bin_desc = type { i32, ptr, ptr, ptr } // CHECK: %struct.__tgt_kernel_arguments = type { i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, i64, i64, [3 x i32], [3 x i32], i32 } -// CHECK: @anon.{{.*}}.0 = private unnamed_addr constant [23 x i8] c";unknown;unknown;0;0;;\00", align 1 -// CHECK: @anon.{{.*}}.1 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 22, ptr @anon.{{.*}}.0 }, align 8 +// CHECK: @anon.[[ID:.*]].0 = private unnamed_addr constant [23 x i8] c";unknown;unknown;0;0;;\00", align 1 +// CHECK: @anon.{{.*}}.1 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 22, ptr @anon.[[ID]].0 }, align 8 -// CHECK: @.offload_sizes._kernel_1 = private unnamed_addr constant [1 x i64] [i64 1024] -// CHECK: @.offload_maptypes._kernel_1 = private unnamed_addr constant [1 x i64] [i64 35] -// CHECK: @._kernel_1.region_id = internal constant i8 0 -// CHECK: @.offloading.entry_name._kernel_1 = internal unnamed_addr constant [10 x i8] c"_kernel_1\00", section ".llvm.rodata.offloading", align 1 -// CHECK: @.offloading.entry._kernel_1 = internal constant %struct.__tgt_offload_entry { i64 0, i16 1, i16 1, i32 0, ptr @._kernel_1.region_id, ptr @.offloading.entry_name._kernel_1, i64 0, i64 0, ptr null }, section "llvm_offload_entries", align 8 +// CHECK-DAG: @.omp_offloading.descriptor = internal constant { i32, ptr, ptr, ptr } zeroinitializer +// CHECK-DAG: @llvm.global_ctors = appending constant [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 101, ptr @.omp_offloading.descriptor_reg, ptr null }] +// CHECK-DAG: @.offload_sizes.[[K:[^ ]*kernel_1]] = private unnamed_addr constant [1 x i64] [i64 1024] +// CHECK-DAG: @.offload_maptypes.[[K]] = private unnamed_addr constant [1 x i64] [i64 35] +// CHECK-DAG: @.[[K]].region_id = internal constant i8 0 +// CHECK-DAG: @.offloading.entry_name.[[K]] = internal unnamed_addr constant [{{[0-9]+}} x i8] c"[[K]]{{\\00}}", section ".llvm.rodata.offloading", align 1 +// CHECK-DAG: @.offloading.entry.[[K]] = internal constant %struct.__tgt_offload_entry { i64 0, i16 1, i16 1, i32 0, ptr @.[[K]].region_id, ptr @.offloading.entry_name.[[K]], i64 0, i64 0, ptr null }, section "llvm_offload_entries", align 8 // CHECK: declare i32 @__tgt_target_kernel(ptr, i64, i32, i32, ptr, ptr) -// CHECK: declare void @__tgt_register_lib(ptr) local_unnamed_addr -// CHECK: declare void @__tgt_unregister_lib(ptr) local_unnamed_addr -// CHECK: define{{( dso_local)?}} void @main() +// CHECK-LABEL: define{{( dso_local)?}} void @main() // CHECK-NEXT: start: -// CHECK-NEXT: %0 = alloca [8 x i8], align 8 -// CHECK-NEXT: %x = alloca [1024 x i8], align 16 -// CHECK: call void @kernel_1(ptr noalias noundef nonnull align 4 dereferenceable(1024) %x) -// CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %0) -// CHECK-NEXT: store ptr %x, ptr %0, align 8 -// CHECK-NEXT: call void asm sideeffect "", "r,~{memory}"(ptr nonnull %0) -// CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %0) -// CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1024, ptr nonnull %x) -// CHECK-NEXT: ret void -// CHECK-NEXT: } - -// CHECK: define{{( dso_local)?}} void @kernel_1(ptr noalias noundef align 4 dereferenceable(1024) %x) -// CHECK-NEXT: start: -// CHECK-NEXT: %EmptyDesc = alloca %struct.__tgt_bin_desc, align 8 +// CHECK-NEXT: %0 = alloca [8 x i8], align 8 +// CHECK-NEXT: %x = alloca [1024 x i8], align 16 // CHECK-NEXT: %.offload_baseptrs = alloca [1 x ptr], align 8 // CHECK-NEXT: %.offload_ptrs = alloca [1 x ptr], align 8 // CHECK-NEXT: %.offload_sizes = alloca [1 x i64], align 8 // CHECK-NEXT: %kernel_args = alloca %struct.__tgt_kernel_arguments, align 8 -// CHECK-NEXT: %dummy = load volatile ptr, ptr @.offload_sizes._kernel_1, align 8 -// CHECK-NEXT: %dummy1 = load volatile ptr, ptr @.offloading.entry._kernel_1, align 8 -// CHECK-NEXT: call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(32) %EmptyDesc, i8 0, i64 32, i1 false) -// CHECK-NEXT: call void @__tgt_register_lib(ptr nonnull %EmptyDesc) +// CHECK: %dummy = load volatile ptr, ptr @.offload_sizes.[[K]], align 8 +// CHECK-NEXT: %dummy1 = load volatile ptr, ptr @.offloading.entry.[[K]], align 8 // CHECK-NEXT: call void @__tgt_init_all_rtls() // CHECK-NEXT: store ptr %x, ptr %.offload_baseptrs, align 8 // CHECK-NEXT: store ptr %x, ptr %.offload_ptrs, align 8 // CHECK-NEXT: store i64 1024, ptr %.offload_sizes, align 8 -// CHECK-NEXT: call void @__tgt_target_data_begin_mapper(ptr nonnull @anon.{{.*}}.1, i64 -1, i32 1, ptr nonnull %.offload_baseptrs, ptr nonnull %.offload_ptrs, ptr nonnull %.offload_sizes, ptr nonnull @.offload_maptypes._kernel_1, ptr null, ptr null) +// CHECK-NEXT: call void @__tgt_target_data_begin_mapper(ptr nonnull @anon.{{.*}}.1, i64 -1, i32 1, ptr nonnull %.offload_baseptrs, ptr nonnull %.offload_ptrs, ptr nonnull %.offload_sizes, ptr nonnull @.offload_maptypes.[[K]], ptr null, ptr null) // CHECK-NEXT: store i32 3, ptr %kernel_args, align 8 -// CHECK-NEXT: %0 = getelementptr inbounds nuw i8, ptr %kernel_args, i64 4 -// CHECK-NEXT: store i32 1, ptr %0, align 4 -// CHECK-NEXT: %1 = getelementptr inbounds nuw i8, ptr %kernel_args, i64 8 -// CHECK-NEXT: store ptr %.offload_baseptrs, ptr %1, align 8 -// CHECK-NEXT: %2 = getelementptr inbounds nuw i8, ptr %kernel_args, i64 16 -// CHECK-NEXT: store ptr %.offload_ptrs, ptr %2, align 8 -// CHECK-NEXT: %3 = getelementptr inbounds nuw i8, ptr %kernel_args, i64 24 -// CHECK-NEXT: store ptr %.offload_sizes, ptr %3, align 8 -// CHECK-NEXT: %4 = getelementptr inbounds nuw i8, ptr %kernel_args, i64 32 -// CHECK-NEXT: store ptr @.offload_maptypes._kernel_1, ptr %4, align 8 -// CHECK-NEXT: %5 = getelementptr inbounds nuw i8, ptr %kernel_args, i64 40 -// CHECK-NEXT: %6 = getelementptr inbounds nuw i8, ptr %kernel_args, i64 72 -// CHECK-NEXT: call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(32) %5, i8 0, i64 32, i1 false) -// CHECK-NEXT: store <4 x i32> , ptr %6, align 8 -// CHECK-NEXT: %.fca.1.gep5 = getelementptr inbounds nuw i8, ptr %kernel_args, i64 88 -// CHECK-NEXT: store i32 1, ptr %.fca.1.gep5, align 8 -// CHECK-NEXT: %.fca.2.gep7 = getelementptr inbounds nuw i8, ptr %kernel_args, i64 92 -// CHECK-NEXT: store i32 1, ptr %.fca.2.gep7, align 4 -// CHECK-NEXT: %7 = getelementptr inbounds nuw i8, ptr %kernel_args, i64 96 -// CHECK-NEXT: store i32 0, ptr %7, align 8 -// CHECK-NEXT: %8 = call i32 @__tgt_target_kernel(ptr nonnull @anon.{{.*}}.1, i64 -1, i32 256, i32 32, ptr nonnull @._kernel_1.region_id, ptr nonnull %kernel_args) -// CHECK-NEXT: call void @__tgt_target_data_end_mapper(ptr nonnull @anon.{{.*}}.1, i64 -1, i32 1, ptr nonnull %.offload_baseptrs, ptr nonnull %.offload_ptrs, ptr nonnull %.offload_sizes, ptr nonnull @.offload_maptypes._kernel_1, ptr null, ptr null) -// CHECK-NEXT: call void @__tgt_unregister_lib(ptr nonnull %EmptyDesc) +// CHECK-NEXT: [[P4:%[^ ]+]] = getelementptr inbounds nuw i8, ptr %kernel_args, i64 4 +// CHECK-NEXT: store i32 1, ptr [[P4]], align 4 +// CHECK-NEXT: [[P8:%[^ ]+]] = getelementptr inbounds nuw i8, ptr %kernel_args, i64 8 +// CHECK-NEXT: store ptr %.offload_baseptrs, ptr [[P8]], align 8 +// CHECK-NEXT: [[P16:%[^ ]+]] = getelementptr inbounds nuw i8, ptr %kernel_args, i64 16 +// CHECK-NEXT: store ptr %.offload_ptrs, ptr [[P16]], align 8 +// CHECK-NEXT: [[P24:%[^ ]+]] = getelementptr inbounds nuw i8, ptr %kernel_args, i64 24 +// CHECK-NEXT: store ptr %.offload_sizes, ptr [[P24]], align 8 +// CHECK-NEXT: [[P32:%[^ ]+]] = getelementptr inbounds nuw i8, ptr %kernel_args, i64 32 +// CHECK-NEXT: store ptr @.offload_maptypes.[[K]], ptr [[P32]], align 8 +// CHECK-NEXT: [[P40:%[^ ]+]] = getelementptr inbounds nuw i8, ptr %kernel_args, i64 40 +// CHECK-NEXT: [[P72:%[^ ]+]] = getelementptr inbounds nuw i8, ptr %kernel_args, i64 72 +// CHECK-NEXT: call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(32) [[P40]], i8 0, i64 32, i1 false) +// CHECK-NEXT: store <4 x i32> , ptr [[P72]], align 8 +// CHECK-NEXT: [[P88:%[^ ]+]] = getelementptr inbounds nuw i8, ptr %kernel_args, i64 88 +// CHECK-NEXT: store i32 1, ptr [[P88]], align 8 +// CHECK-NEXT: [[P92:%[^ ]+]] = getelementptr inbounds nuw i8, ptr %kernel_args, i64 92 +// CHECK-NEXT: store i32 1, ptr [[P92]], align 4 +// CHECK-NEXT: [[P96:%[^ ]+]] = getelementptr inbounds nuw i8, ptr %kernel_args, i64 96 +// CHECK-NEXT: store i32 0, ptr [[P96]], align 8 +// CHECK-NEXT: {{%[^ ]+}} = call i32 @__tgt_target_kernel(ptr nonnull @anon.{{.*}}.1, i64 -1, i32 256, i32 32, ptr nonnull @.[[K]].region_id, ptr nonnull %kernel_args) +// CHECK-NEXT: call void @__tgt_target_data_end_mapper(ptr nonnull @anon.{{.*}}.1, i64 -1, i32 1, ptr nonnull %.offload_baseptrs, ptr nonnull %.offload_ptrs, ptr nonnull %.offload_sizes, ptr nonnull @.offload_maptypes.[[K]], ptr null, ptr null) +// CHECK: ret void +// CHECK-NEXT: } + +// CHECK: declare void @__tgt_register_lib(ptr) local_unnamed_addr +// CHECK: declare void @__tgt_unregister_lib(ptr) local_unnamed_addr + +// CHECK-LABEL: define internal void @.omp_offloading.descriptor_reg() section ".text.startup" { +// CHECK-NEXT: entry: +// CHECK-NEXT: call void @__tgt_register_lib(ptr nonnull @.omp_offloading.descriptor) +// CHECK-NEXT: %0 = {{tail }}call i32 @atexit(ptr nonnull @.omp_offloading.descriptor_unreg) +// CHECK-NEXT: ret void +// CHECK-NEXT: } + +// CHECK-LABEL: define internal void @.omp_offloading.descriptor_unreg() section ".text.startup" { +// CHECK-NEXT: entry: +// CHECK-NEXT: call void @__tgt_unregister_lib(ptr nonnull @.omp_offloading.descriptor) // CHECK-NEXT: ret void // CHECK-NEXT: } diff --git a/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-abort.diff b/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-abort.diff index 6c9cf0cf623b..a0aeb0a30f41 100644 --- a/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-abort.diff +++ b/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-abort.diff @@ -93,64 +93,100 @@ } scope 25 (inlined std::cmp::impls::::eq) { scope 26 (inlined core::slice::cmp::::eq) { + let _39: usize; + let mut _40: bool; + let mut _41: usize; + let mut _42: *const u8; + let mut _43: *const u8; + scope 27 { + scope 28 (inlined core::slice::::as_ptr) { + let mut _44: *const [u8]; + } + scope 29 (inlined core::slice::::as_ptr) { + let mut _45: *const [u8]; + } + scope 30 (inlined >::equal_same_length) { + let mut _46: i32; + scope 31 { + } + } + } } } } } } - scope 27 (inlined std::cmp::impls:: for &String>::eq) { - let mut _39: &std::string::String; - let mut _40: &str; - scope 28 (inlined >::eq) { - scope 29 (inlined #[track_caller] >::index) { - let _41: &str; - scope 30 (inlined String::as_str) { - let _42: &[u8]; - scope 31 (inlined Vec::::as_slice) { - let _43: *const [u8]; - let mut _44: *const u8; - let mut _45: usize; - scope 32 (inlined Vec::::as_ptr) { - scope 33 (inlined alloc::raw_vec::RawVec::::ptr) { - scope 34 (inlined alloc::raw_vec::RawVecInner::ptr::) { - scope 35 (inlined alloc::raw_vec::RawVecInner::non_null::) { - let mut _46: std::ptr::NonNull; - scope 36 (inlined std::ptr::Unique::::cast::) { - scope 37 (inlined NonNull::::cast::) { - scope 38 (inlined NonNull::::as_ptr) { + scope 32 (inlined std::cmp::impls:: for &String>::eq) { + let mut _47: &std::string::String; + let mut _48: &str; + scope 33 (inlined >::eq) { + scope 34 (inlined #[track_caller] >::index) { + let _49: &str; + scope 35 (inlined String::as_str) { + let _50: &[u8]; + scope 36 (inlined Vec::::as_slice) { + let _51: *const [u8]; + let mut _52: *const u8; + let mut _53: usize; + scope 37 (inlined Vec::::as_ptr) { + scope 38 (inlined alloc::raw_vec::RawVec::::ptr) { + scope 39 (inlined alloc::raw_vec::RawVecInner::ptr::) { + scope 40 (inlined alloc::raw_vec::RawVecInner::non_null::) { + let mut _54: std::ptr::NonNull; + scope 41 (inlined std::ptr::Unique::::cast::) { + scope 42 (inlined NonNull::::cast::) { + scope 43 (inlined NonNull::::as_ptr) { } } } - scope 39 (inlined std::ptr::Unique::::as_non_null_ptr) { + scope 44 (inlined std::ptr::Unique::::as_non_null_ptr) { } } - scope 40 (inlined NonNull::::as_ptr) { + scope 45 (inlined NonNull::::as_ptr) { } } } } } - scope 41 (inlined from_utf8_unchecked) { + scope 46 (inlined from_utf8_unchecked) { } } - scope 42 (inlined #[track_caller] core::str::traits:: for RangeFull>::index) { + scope 47 (inlined #[track_caller] core::str::traits:: for RangeFull>::index) { } } - scope 43 (inlined #[track_caller] core::str::traits:: for str>::index) { - scope 44 (inlined #[track_caller] core::str::traits:: for RangeFull>::index) { + scope 48 (inlined #[track_caller] core::str::traits:: for str>::index) { + scope 49 (inlined #[track_caller] core::str::traits:: for RangeFull>::index) { } } - scope 45 (inlined core::str::traits::::eq) { - let mut _47: &&[u8]; - let _48: &[u8]; - let mut _49: &&[u8]; - let _50: &[u8]; - scope 46 (inlined core::str::::as_bytes) { + scope 50 (inlined core::str::traits::::eq) { + let mut _55: &&[u8]; + let _56: &[u8]; + let mut _57: &&[u8]; + let _58: &[u8]; + scope 51 (inlined core::str::::as_bytes) { } - scope 47 (inlined core::str::::as_bytes) { + scope 52 (inlined core::str::::as_bytes) { } - scope 48 (inlined std::cmp::impls::::eq) { - scope 49 (inlined core::slice::cmp::::eq) { + scope 53 (inlined std::cmp::impls::::eq) { + scope 54 (inlined core::slice::cmp::::eq) { + let _59: usize; + let mut _60: bool; + let mut _61: usize; + let mut _62: *const u8; + let mut _63: *const u8; + scope 55 { + scope 56 (inlined core::slice::::as_ptr) { + let mut _64: *const [u8]; + } + scope 57 (inlined core::slice::::as_ptr) { + let mut _65: *const [u8]; + } + scope 58 (inlined >::equal_same_length) { + let mut _66: i32; + scope 59 { + } + } + } } } } @@ -179,7 +215,7 @@ bb3: { _1 = chained_conditions::BacktraceStyle::Off; - goto -> bb18; -+ goto -> bb23; ++ goto -> bb29; } bb4: { @@ -216,9 +252,17 @@ StorageDead(_30); StorageLive(_36); StorageLive(_38); + StorageLive(_39); + StorageLive(_42); + StorageLive(_43); _36 = copy _29 as &[u8] (Transmute); _38 = copy _28 as &[u8] (Transmute); - _7 = <[u8] as core::slice::cmp::SlicePartialEq>::equal(move _36, move _38) -> [return: bb19, unwind unreachable]; + _39 = PtrMetadata(copy _36); + StorageLive(_40); + StorageLive(_41); + _41 = PtrMetadata(copy _38); + _40 = Eq(copy _39, move _41); + switchInt(move _40) -> [0: bb20, otherwise: bb19]; } bb5: { @@ -249,39 +293,47 @@ StorageLive(_17); _20 = const chained_conditions::promoted[0]; _17 = &(*_20); - StorageLive(_39); - StorageLive(_40); - _39 = copy (*_15); - _40 = copy (*_17); - StorageLive(_41); - StorageLive(_42); - StorageLive(_43); - StorageLive(_44); - StorageLive(_46); - _46 = copy ((((((*_39).0: std::vec::Vec).0: alloc::raw_vec::RawVec).0: alloc::raw_vec::RawVecInner).0: std::ptr::Unique).0: std::ptr::NonNull); - _44 = copy _46 as *const u8 (Transmute); - StorageDead(_46); - StorageLive(_45); - _45 = copy (((*_39).0: std::vec::Vec).1: usize); - _43 = *const [u8] from (copy _44, move _45); - StorageDead(_45); - StorageDead(_44); - _42 = &(*_43); - StorageDead(_43); - _41 = copy _42 as &str (Transmute); - StorageDead(_42); + StorageLive(_47); StorageLive(_48); + _47 = copy (*_15); + _48 = copy (*_17); + StorageLive(_49); StorageLive(_50); - _48 = copy _41 as &[u8] (Transmute); - _50 = copy _40 as &[u8] (Transmute); - _14 = <[u8] as core::slice::cmp::SlicePartialEq>::equal(move _48, move _50) -> [return: bb20, unwind unreachable]; + StorageLive(_51); + StorageLive(_52); + StorageLive(_54); + _54 = copy ((((((*_47).0: std::vec::Vec).0: alloc::raw_vec::RawVec).0: alloc::raw_vec::RawVecInner).0: std::ptr::Unique).0: std::ptr::NonNull); + _52 = copy _54 as *const u8 (Transmute); + StorageDead(_54); + StorageLive(_53); + _53 = copy (((*_47).0: std::vec::Vec).1: usize); + _51 = *const [u8] from (copy _52, move _53); + StorageDead(_53); + StorageDead(_52); + _50 = &(*_51); + StorageDead(_51); + _49 = copy _50 as &str (Transmute); + StorageDead(_50); + StorageLive(_56); + StorageLive(_58); + StorageLive(_59); + StorageLive(_62); + StorageLive(_63); + _56 = copy _49 as &[u8] (Transmute); + _58 = copy _48 as &[u8] (Transmute); + _59 = PtrMetadata(copy _56); + StorageLive(_60); + StorageLive(_61); + _61 = PtrMetadata(copy _58); + _60 = Eq(copy _59, move _61); + switchInt(move _60) -> [0: bb24, otherwise: bb23]; } bb7: { StorageDead(_5); StorageDead(_6); - goto -> bb18; -+ goto -> bb21; ++ goto -> bb27; } bb8: { @@ -304,14 +356,14 @@ StorageDead(_13); _1 = chained_conditions::BacktraceStyle::Short; - goto -> bb18; -+ goto -> bb23; ++ goto -> bb29; } bb10: { StorageDead(_12); StorageDead(_13); - goto -> bb18; -+ goto -> bb21; ++ goto -> bb27; } bb11: { @@ -356,6 +408,31 @@ } bb19: { + StorageDead(_41); + StorageLive(_44); + _44 = &raw const (*_36); + _42 = copy _44 as *const u8 (PtrToPtr); + StorageDead(_44); + StorageLive(_45); + _45 = &raw const (*_38); + _43 = copy _45 as *const u8 (PtrToPtr); + StorageDead(_45); + StorageLive(_46); + _46 = compare_bytes(move _42, move _43, move _39) -> [return: bb22, unwind unreachable]; + } + + bb20: { + StorageDead(_41); + _7 = const false; +- goto -> bb21; ++ goto -> bb32; + } + + bb21: { + StorageDead(_40); + StorageDead(_43); + StorageDead(_42); + StorageDead(_39); StorageDead(_38); StorageDead(_36); StorageDead(_29); @@ -364,31 +441,94 @@ switchInt(move _7) -> [0: bb6, otherwise: bb5]; } - bb20: { - StorageDead(_50); + bb22: { + _7 = Eq(move _46, const 0_i32); + StorageDead(_46); + goto -> bb21; + } + + bb23: { + StorageDead(_61); + StorageLive(_64); + _64 = &raw const (*_56); + _62 = copy _64 as *const u8 (PtrToPtr); + StorageDead(_64); + StorageLive(_65); + _65 = &raw const (*_58); + _63 = copy _65 as *const u8 (PtrToPtr); + StorageDead(_65); + StorageLive(_66); + _66 = compare_bytes(move _62, move _63, move _59) -> [return: bb26, unwind unreachable]; + } + + bb24: { + StorageDead(_61); + _14 = const false; +- goto -> bb25; ++ goto -> bb31; + } + + bb25: { + StorageDead(_60); + StorageDead(_63); + StorageDead(_62); + StorageDead(_59); + StorageDead(_58); + StorageDead(_56); + StorageDead(_49); StorageDead(_48); - StorageDead(_41); - StorageDead(_40); - StorageDead(_39); + StorageDead(_47); switchInt(move _14) -> [0: bb9, otherwise: bb8]; + } + + bb26: { + _14 = Eq(move _66, const 0_i32); + StorageDead(_66); + goto -> bb25; + } + -+ bb21: { ++ bb27: { + _24 = discriminant(_2); -+ switchInt(move _24) -> [1: bb22, otherwise: bb15]; ++ switchInt(move _24) -> [1: bb28, otherwise: bb15]; + } + -+ bb22: { ++ bb28: { + goto -> bb15; + } + -+ bb23: { ++ bb29: { + _24 = discriminant(_2); -+ switchInt(move _24) -> [1: bb24, otherwise: bb15]; ++ switchInt(move _24) -> [1: bb30, otherwise: bb15]; + } + -+ bb24: { ++ bb30: { + goto -> bb17; ++ } ++ ++ bb31: { ++ StorageDead(_60); ++ StorageDead(_63); ++ StorageDead(_62); ++ StorageDead(_59); ++ StorageDead(_58); ++ StorageDead(_56); ++ StorageDead(_49); ++ StorageDead(_48); ++ StorageDead(_47); ++ goto -> bb9; ++ } ++ ++ bb32: { ++ StorageDead(_40); ++ StorageDead(_43); ++ StorageDead(_42); ++ StorageDead(_39); ++ StorageDead(_38); ++ StorageDead(_36); ++ StorageDead(_29); ++ StorageDead(_28); ++ StorageDead(_27); ++ goto -> bb6; } } diff --git a/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-unwind.diff b/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-unwind.diff index 49cd68577a12..71d91fed6307 100644 --- a/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-unwind.diff +++ b/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-unwind.diff @@ -93,64 +93,100 @@ } scope 25 (inlined std::cmp::impls::::eq) { scope 26 (inlined core::slice::cmp::::eq) { + let _39: usize; + let mut _40: bool; + let mut _41: usize; + let mut _42: *const u8; + let mut _43: *const u8; + scope 27 { + scope 28 (inlined core::slice::::as_ptr) { + let mut _44: *const [u8]; + } + scope 29 (inlined core::slice::::as_ptr) { + let mut _45: *const [u8]; + } + scope 30 (inlined >::equal_same_length) { + let mut _46: i32; + scope 31 { + } + } + } } } } } } - scope 27 (inlined std::cmp::impls:: for &String>::eq) { - let mut _39: &std::string::String; - let mut _40: &str; - scope 28 (inlined >::eq) { - scope 29 (inlined #[track_caller] >::index) { - let _41: &str; - scope 30 (inlined String::as_str) { - let _42: &[u8]; - scope 31 (inlined Vec::::as_slice) { - let _43: *const [u8]; - let mut _44: *const u8; - let mut _45: usize; - scope 32 (inlined Vec::::as_ptr) { - scope 33 (inlined alloc::raw_vec::RawVec::::ptr) { - scope 34 (inlined alloc::raw_vec::RawVecInner::ptr::) { - scope 35 (inlined alloc::raw_vec::RawVecInner::non_null::) { - let mut _46: std::ptr::NonNull; - scope 36 (inlined std::ptr::Unique::::cast::) { - scope 37 (inlined NonNull::::cast::) { - scope 38 (inlined NonNull::::as_ptr) { + scope 32 (inlined std::cmp::impls:: for &String>::eq) { + let mut _47: &std::string::String; + let mut _48: &str; + scope 33 (inlined >::eq) { + scope 34 (inlined #[track_caller] >::index) { + let _49: &str; + scope 35 (inlined String::as_str) { + let _50: &[u8]; + scope 36 (inlined Vec::::as_slice) { + let _51: *const [u8]; + let mut _52: *const u8; + let mut _53: usize; + scope 37 (inlined Vec::::as_ptr) { + scope 38 (inlined alloc::raw_vec::RawVec::::ptr) { + scope 39 (inlined alloc::raw_vec::RawVecInner::ptr::) { + scope 40 (inlined alloc::raw_vec::RawVecInner::non_null::) { + let mut _54: std::ptr::NonNull; + scope 41 (inlined std::ptr::Unique::::cast::) { + scope 42 (inlined NonNull::::cast::) { + scope 43 (inlined NonNull::::as_ptr) { } } } - scope 39 (inlined std::ptr::Unique::::as_non_null_ptr) { + scope 44 (inlined std::ptr::Unique::::as_non_null_ptr) { } } - scope 40 (inlined NonNull::::as_ptr) { + scope 45 (inlined NonNull::::as_ptr) { } } } } } - scope 41 (inlined from_utf8_unchecked) { + scope 46 (inlined from_utf8_unchecked) { } } - scope 42 (inlined #[track_caller] core::str::traits:: for RangeFull>::index) { + scope 47 (inlined #[track_caller] core::str::traits:: for RangeFull>::index) { } } - scope 43 (inlined #[track_caller] core::str::traits:: for str>::index) { - scope 44 (inlined #[track_caller] core::str::traits:: for RangeFull>::index) { + scope 48 (inlined #[track_caller] core::str::traits:: for str>::index) { + scope 49 (inlined #[track_caller] core::str::traits:: for RangeFull>::index) { } } - scope 45 (inlined core::str::traits::::eq) { - let mut _47: &&[u8]; - let _48: &[u8]; - let mut _49: &&[u8]; - let _50: &[u8]; - scope 46 (inlined core::str::::as_bytes) { + scope 50 (inlined core::str::traits::::eq) { + let mut _55: &&[u8]; + let _56: &[u8]; + let mut _57: &&[u8]; + let _58: &[u8]; + scope 51 (inlined core::str::::as_bytes) { } - scope 47 (inlined core::str::::as_bytes) { + scope 52 (inlined core::str::::as_bytes) { } - scope 48 (inlined std::cmp::impls::::eq) { - scope 49 (inlined core::slice::cmp::::eq) { + scope 53 (inlined std::cmp::impls::::eq) { + scope 54 (inlined core::slice::cmp::::eq) { + let _59: usize; + let mut _60: bool; + let mut _61: usize; + let mut _62: *const u8; + let mut _63: *const u8; + scope 55 { + scope 56 (inlined core::slice::::as_ptr) { + let mut _64: *const [u8]; + } + scope 57 (inlined core::slice::::as_ptr) { + let mut _65: *const [u8]; + } + scope 58 (inlined >::equal_same_length) { + let mut _66: i32; + scope 59 { + } + } + } } } } @@ -179,7 +215,7 @@ bb3: { _1 = chained_conditions::BacktraceStyle::Off; - goto -> bb19; -+ goto -> bb27; ++ goto -> bb33; } bb4: { @@ -216,9 +252,17 @@ StorageDead(_30); StorageLive(_36); StorageLive(_38); + StorageLive(_39); + StorageLive(_42); + StorageLive(_43); _36 = copy _29 as &[u8] (Transmute); _38 = copy _28 as &[u8] (Transmute); - _7 = <[u8] as core::slice::cmp::SlicePartialEq>::equal(move _36, move _38) -> [return: bb23, unwind: bb22]; + _39 = PtrMetadata(copy _36); + StorageLive(_40); + StorageLive(_41); + _41 = PtrMetadata(copy _38); + _40 = Eq(copy _39, move _41); + switchInt(move _40) -> [0: bb24, otherwise: bb23]; } bb5: { @@ -249,39 +293,47 @@ StorageLive(_17); _20 = const chained_conditions::promoted[0]; _17 = &(*_20); - StorageLive(_39); - StorageLive(_40); - _39 = copy (*_15); - _40 = copy (*_17); - StorageLive(_41); - StorageLive(_42); - StorageLive(_43); - StorageLive(_44); - StorageLive(_46); - _46 = copy ((((((*_39).0: std::vec::Vec).0: alloc::raw_vec::RawVec).0: alloc::raw_vec::RawVecInner).0: std::ptr::Unique).0: std::ptr::NonNull); - _44 = copy _46 as *const u8 (Transmute); - StorageDead(_46); - StorageLive(_45); - _45 = copy (((*_39).0: std::vec::Vec).1: usize); - _43 = *const [u8] from (copy _44, move _45); - StorageDead(_45); - StorageDead(_44); - _42 = &(*_43); - StorageDead(_43); - _41 = copy _42 as &str (Transmute); - StorageDead(_42); + StorageLive(_47); StorageLive(_48); + _47 = copy (*_15); + _48 = copy (*_17); + StorageLive(_49); StorageLive(_50); - _48 = copy _41 as &[u8] (Transmute); - _50 = copy _40 as &[u8] (Transmute); - _14 = <[u8] as core::slice::cmp::SlicePartialEq>::equal(move _48, move _50) -> [return: bb24, unwind: bb22]; + StorageLive(_51); + StorageLive(_52); + StorageLive(_54); + _54 = copy ((((((*_47).0: std::vec::Vec).0: alloc::raw_vec::RawVec).0: alloc::raw_vec::RawVecInner).0: std::ptr::Unique).0: std::ptr::NonNull); + _52 = copy _54 as *const u8 (Transmute); + StorageDead(_54); + StorageLive(_53); + _53 = copy (((*_47).0: std::vec::Vec).1: usize); + _51 = *const [u8] from (copy _52, move _53); + StorageDead(_53); + StorageDead(_52); + _50 = &(*_51); + StorageDead(_51); + _49 = copy _50 as &str (Transmute); + StorageDead(_50); + StorageLive(_56); + StorageLive(_58); + StorageLive(_59); + StorageLive(_62); + StorageLive(_63); + _56 = copy _49 as &[u8] (Transmute); + _58 = copy _48 as &[u8] (Transmute); + _59 = PtrMetadata(copy _56); + StorageLive(_60); + StorageLive(_61); + _61 = PtrMetadata(copy _58); + _60 = Eq(copy _59, move _61); + switchInt(move _60) -> [0: bb28, otherwise: bb27]; } bb7: { StorageDead(_5); StorageDead(_6); - goto -> bb19; -+ goto -> bb25; ++ goto -> bb31; } bb8: { @@ -304,14 +356,14 @@ StorageDead(_13); _1 = chained_conditions::BacktraceStyle::Short; - goto -> bb19; -+ goto -> bb27; ++ goto -> bb33; } bb10: { StorageDead(_12); StorageDead(_13); - goto -> bb19; -+ goto -> bb25; ++ goto -> bb31; } bb11: { @@ -373,6 +425,31 @@ } bb23: { + StorageDead(_41); + StorageLive(_44); + _44 = &raw const (*_36); + _42 = copy _44 as *const u8 (PtrToPtr); + StorageDead(_44); + StorageLive(_45); + _45 = &raw const (*_38); + _43 = copy _45 as *const u8 (PtrToPtr); + StorageDead(_45); + StorageLive(_46); + _46 = compare_bytes(move _42, move _43, move _39) -> [return: bb26, unwind unreachable]; + } + + bb24: { + StorageDead(_41); + _7 = const false; +- goto -> bb25; ++ goto -> bb36; + } + + bb25: { + StorageDead(_40); + StorageDead(_43); + StorageDead(_42); + StorageDead(_39); StorageDead(_38); StorageDead(_36); StorageDead(_29); @@ -381,31 +458,94 @@ switchInt(move _7) -> [0: bb6, otherwise: bb5]; } - bb24: { - StorageDead(_50); + bb26: { + _7 = Eq(move _46, const 0_i32); + StorageDead(_46); + goto -> bb25; + } + + bb27: { + StorageDead(_61); + StorageLive(_64); + _64 = &raw const (*_56); + _62 = copy _64 as *const u8 (PtrToPtr); + StorageDead(_64); + StorageLive(_65); + _65 = &raw const (*_58); + _63 = copy _65 as *const u8 (PtrToPtr); + StorageDead(_65); + StorageLive(_66); + _66 = compare_bytes(move _62, move _63, move _59) -> [return: bb30, unwind unreachable]; + } + + bb28: { + StorageDead(_61); + _14 = const false; +- goto -> bb29; ++ goto -> bb35; + } + + bb29: { + StorageDead(_60); + StorageDead(_63); + StorageDead(_62); + StorageDead(_59); + StorageDead(_58); + StorageDead(_56); + StorageDead(_49); StorageDead(_48); - StorageDead(_41); - StorageDead(_40); - StorageDead(_39); + StorageDead(_47); switchInt(move _14) -> [0: bb9, otherwise: bb8]; + } + + bb30: { + _14 = Eq(move _66, const 0_i32); + StorageDead(_66); + goto -> bb29; + } + -+ bb25: { ++ bb31: { + _24 = discriminant(_2); -+ switchInt(move _24) -> [1: bb26, otherwise: bb16]; ++ switchInt(move _24) -> [1: bb32, otherwise: bb16]; + } + -+ bb26: { ++ bb32: { + goto -> bb16; + } + -+ bb27: { ++ bb33: { + _24 = discriminant(_2); -+ switchInt(move _24) -> [1: bb28, otherwise: bb16]; ++ switchInt(move _24) -> [1: bb34, otherwise: bb16]; + } + -+ bb28: { ++ bb34: { + goto -> bb18; ++ } ++ ++ bb35: { ++ StorageDead(_60); ++ StorageDead(_63); ++ StorageDead(_62); ++ StorageDead(_59); ++ StorageDead(_58); ++ StorageDead(_56); ++ StorageDead(_49); ++ StorageDead(_48); ++ StorageDead(_47); ++ goto -> bb9; ++ } ++ ++ bb36: { ++ StorageDead(_40); ++ StorageDead(_43); ++ StorageDead(_42); ++ StorageDead(_39); ++ StorageDead(_38); ++ StorageDead(_36); ++ StorageDead(_29); ++ StorageDead(_28); ++ StorageDead(_27); ++ goto -> bb6; } } diff --git a/tests/mir-opt/simplify_match.rs b/tests/mir-opt/simplify_match.rs index b035b6339fae..ca9dac40aa91 100644 --- a/tests/mir-opt/simplify_match.rs +++ b/tests/mir-opt/simplify_match.rs @@ -1,9 +1,15 @@ -// skip-filecheck +//! Test that GVN propagates the constant `false` and eliminates the match. // EMIT_MIR_FOR_EACH_PANIC_STRATEGY + #[inline(never)] fn noop() {} // EMIT_MIR simplify_match.main.GVN.diff +// CHECK-LABEL: fn main( +// CHECK: debug x => const false; +// CHECK-NOT: switchInt +// CHECK: bb0: { +// CHECK-NEXT: return; fn main() { match { let x = false; diff --git a/tests/run-make/crate-loading/multiple-dep-versions.stderr b/tests/run-make/crate-loading/multiple-dep-versions.stderr index f8f8bfaaff6f..ef7fb7082266 100644 --- a/tests/run-make/crate-loading/multiple-dep-versions.stderr +++ b/tests/run-make/crate-loading/multiple-dep-versions.stderr @@ -1,8 +1,8 @@ -error[E0277]: the trait bound `dep_2_reexport::Type: Trait` is not satisfied +error[E0277]: the trait bound `dep_2_reexport::Type: dependency::Trait` is not satisfied --> replaced | LL | do_something(Type); - | ------------ ^^^^ the trait `Trait` is not implemented for `dep_2_reexport::Type` + | ------------ ^^^^ the trait `dependency::Trait` is not implemented for `dep_2_reexport::Type` | | | required by a bound introduced by this call | @@ -17,7 +17,7 @@ LL | pub trait Trait { LL | pub trait Trait { | --------------- this is the found trait = help: you can use `cargo tree` to explore your dependency tree -help: the trait `Trait` is implemented for `dependency::Type` +help: the trait `dependency::Trait` is implemented for `dependency::Type` --> replaced | LL | impl Trait for Type { @@ -64,11 +64,11 @@ LL | pub trait Trait { | --------------- this is the trait that was imported = help: you can use `cargo tree` to explore your dependency tree -error[E0277]: the trait bound `OtherType: Trait` is not satisfied +error[E0277]: the trait bound `OtherType: dependency::Trait` is not satisfied --> replaced | LL | do_something(OtherType); - | ------------ ^^^^^^^^^ the trait `Trait` is not implemented for `OtherType` + | ------------ ^^^^^^^^^ the trait `dependency::Trait` is not implemented for `OtherType` | | | required by a bound introduced by this call | @@ -83,7 +83,7 @@ LL | pub trait Trait { LL | pub trait Trait { | --------------- this is the found trait = help: you can use `cargo tree` to explore your dependency tree -help: the trait `Trait` is implemented for `dependency::Type` +help: the trait `dependency::Trait` is implemented for `dependency::Type` --> replaced | LL | impl Trait for Type { diff --git a/tests/rustdoc-gui/headings.goml b/tests/rustdoc-gui/headings.goml index 94d80a3e3df5..391234b78ebd 100644 --- a/tests/rustdoc-gui/headings.goml +++ b/tests/rustdoc-gui/headings.goml @@ -221,14 +221,14 @@ call-function: ( define-function: ( "check-since-color", - [theme], + [theme, color], block { call-function: ("switch-theme", {"theme": |theme|}) - assert-css: (".since", {"color": "#808080"}, ALL) + assert-css: (".since", {"color": |color|}, ALL) }, ) go-to: "file://" + |DOC_PATH| + "/staged_api/struct.Foo.html" -call-function: ("check-since-color", {"theme": "ayu"}) -call-function: ("check-since-color", {"theme": "dark"}) -call-function: ("check-since-color", {"theme": "light"}) +call-function: ("check-since-color", {"theme": "ayu", "color": "#808080"}) +call-function: ("check-since-color", {"theme": "dark", "color": "#d0d0d0"}) +call-function: ("check-since-color", {"theme": "light", "color": "#808080"}) diff --git a/tests/rustdoc-gui/setting-hide-deprecated.goml b/tests/rustdoc-gui/setting-hide-deprecated.goml index 6dc5a6bff175..0fefe00f9457 100644 --- a/tests/rustdoc-gui/setting-hide-deprecated.goml +++ b/tests/rustdoc-gui/setting-hide-deprecated.goml @@ -69,7 +69,7 @@ wait-for-css: ("details" + |deprecated_class|, {"display": "block"}, ALL) // And now we check with the search results. call-function: ("perform-search", {"query": "deprecated::depr"}) -// There should at least 7 results. +// There should be at least 7 results. store-count: ("#results ul.search-results.active > a", nb_search_results) assert: |nb_search_results| >= 7 // There should be at least 5 deprecated items. @@ -77,6 +77,12 @@ store-count: ("#results ul.search-results.active > a" + |deprecated_class|, nb_d assert: |nb_search_results| >= 5 // Deprecated items should all be displayed. assert-css: ("#results ul.search-results.active > a" + |deprecated_class|, {"display": "grid"}, ALL) +// The "X deprecated items hidden by setting" element should not be displayed. +assert-text: ( + "#results ul.search-results.active .deprecated-count", + "5 deprecated items hidden by setting", +) +assert-css: ("#results ul.search-results.active .deprecated-count", {"display": "none"}) // We enable the "hide deprecated items" setting. call-function: ("open-settings-menu", {}) click: "#hide-deprecated-items" @@ -86,11 +92,16 @@ wait-for-css: ( {"display": "none"}, ALL, ) +// The "X deprecated items hidden by setting" element should be displayed. +assert-css: ("#results ul.search-results.active .deprecated-count", {"display": "block"}) // Finally we check that the future deprecated item doesn't have the deprecated class in the search -// and therefore isn't impact by the setting. -call-function: ("perform-search", {"query": "deprecated::future_deprecated"}) +// and therefore isn't impacted by the setting. +call-function: ("perform-search", {"query": '"future_deprecated_fn"'}) assert-text: ( "#results ul.search-results.active > a:not(" + |deprecated_class| + ") .path", " lib2::deprecated::NonDeprecatedStruct::future_deprecated_fn", ) +// The "X deprecated items hidden by setting" element should now be empty, and therefore not displayed. +assert-text: ("#results ul.search-results.active .deprecated-count", "") +assert-css: ("#results ul.search-results.active .deprecated-count", {"display": "none"}) diff --git a/tests/rustdoc-html/glob-shadowing.rs b/tests/rustdoc-html/glob-shadowing.rs index d9e9ead3f9a9..c1eeb7e663e7 100644 --- a/tests/rustdoc-html/glob-shadowing.rs +++ b/tests/rustdoc-html/glob-shadowing.rs @@ -1,9 +1,9 @@ //@ has 'glob_shadowing/index.html' -//@ count - '//dt' 6 -//@ !has - '//dd' 'sub1::describe' +//@ count - '//dt' 7 +//@ !has - '//dd' 'sub1::describe1' //@ has - '//dd' 'sub2::describe' -//@ !has - '//dd' 'sub1::describe2' +//@ has - '//dd' 'sub1::describe2' //@ !has - '//dd' 'sub1::prelude' //@ has - '//dd' 'mod::prelude' @@ -18,7 +18,7 @@ mod sub1 { // this should be shadowed by sub2::describe - /// sub1::describe + /// sub1::describe1 pub fn describe() -> &'static str { "sub1::describe" } @@ -33,7 +33,9 @@ mod sub1 { pub struct Foo; // this should be shadowed, - // because both sub1::describe2 and sub3::describe2 are from glob reexport + // because both sub1::describe2 and sub3::describe2 are from glob reexport, + // but it is still usable from other crates under the `ambiguous_glob_imports` lint, + // so it is reachable and documented /// sub1::describe2 pub fn describe2() -> &'static str { "sub1::describe2" diff --git a/tests/rustdoc-json/reexport/glob_collision.rs b/tests/rustdoc-json/reexport/glob_collision.rs index 48de1b5e7721..dd6eab6517b0 100644 --- a/tests/rustdoc-json/reexport/glob_collision.rs +++ b/tests/rustdoc-json/reexport/glob_collision.rs @@ -1,7 +1,9 @@ // Regression test for https://github.com/rust-lang/rust/issues/100973 +// Update: the rules has changed after #147984, one of the colliding items is now available +// from other crates under a deprecation lint. //@ set m1 = "$.index[?(@.name == 'm1' && @.inner.module)].id" -//@ is "$.index[?(@.name == 'm1')].inner.module.items" [] +//@ is "$.index[?(@.name == 'm1')].inner.module.items" [0] //@ is "$.index[?(@.name == 'm1')].inner.module.is_stripped" true mod m1 { pub fn f() {} diff --git a/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.rs b/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.rs index 3d1e48a4c638..91447e5fa166 100644 --- a/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.rs +++ b/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.rs @@ -14,3 +14,20 @@ pub mod bar { //~| ERROR: unresolved link pub fn sql_function_proc() {} } + +// From here, this is a regression test for . +pub use fuzz_test_helpers::*; + +/// A type referenced in the deprecation note. +pub struct Env; + +impl Env { + pub fn try_invoke(&self) {} +} + +mod fuzz_test_helpers { + #[deprecated(note = "use [Env::try_invoke] instead")] + //~^ ERROR: unresolved link + //~| ERROR: unresolved link + pub fn fuzz_catch_panic() {} +} diff --git a/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.stderr b/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.stderr index 25f10b24d9fb..cb7a5f0c6e02 100644 --- a/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.stderr +++ b/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.stderr @@ -16,6 +16,18 @@ note: the lint level is defined here LL | #![deny(rustdoc::broken_intra_doc_links)] | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +error: unresolved link to `Env::try_invoke` + --> $DIR/deprecated-note-from-reexported.rs:29:25 + | +LL | #[deprecated(note = "use [Env::try_invoke] instead")] + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + | + = note: the link appears in this line: + + use [Env::try_invoke] instead + ^^^^^^^^^^^^^^^ + = note: no item named `Env` in scope + error: unresolved link to `define_sql_function` --> $DIR/deprecated-note-from-reexported.rs:12:25 | @@ -30,5 +42,18 @@ LL | #[deprecated(note = "Use [`define_sql_function`] instead")] = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]` = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` -error: aborting due to 2 previous errors +error: unresolved link to `Env::try_invoke` + --> $DIR/deprecated-note-from-reexported.rs:29:25 + | +LL | #[deprecated(note = "use [Env::try_invoke] instead")] + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + | + = note: the link appears in this line: + + use [Env::try_invoke] instead + ^^^^^^^^^^^^^^^ + = note: no item named `Env` in scope + = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` + +error: aborting due to 4 previous errors diff --git a/tests/ui-fulldeps/session-diagnostic/diagnostic-derive-doc-comment-field.rs b/tests/ui-fulldeps/session-diagnostic/diagnostic-derive-doc-comment-field.rs index 37f78a7777c4..4f08c5327c15 100644 --- a/tests/ui-fulldeps/session-diagnostic/diagnostic-derive-doc-comment-field.rs +++ b/tests/ui-fulldeps/session-diagnostic/diagnostic-derive-doc-comment-field.rs @@ -18,6 +18,7 @@ extern crate rustc_fluent_macro; extern crate rustc_macros; extern crate rustc_session; extern crate rustc_span; +extern crate core; use rustc_errors::{Applicability, DiagMessage, SubdiagMessage}; use rustc_macros::{Diagnostic, Subdiagnostic}; diff --git a/tests/ui-fulldeps/session-diagnostic/diagnostic-derive-doc-comment-field.stderr b/tests/ui-fulldeps/session-diagnostic/diagnostic-derive-doc-comment-field.stderr index 316f23888bc1..0b00e098f6d4 100644 --- a/tests/ui-fulldeps/session-diagnostic/diagnostic-derive-doc-comment-field.stderr +++ b/tests/ui-fulldeps/session-diagnostic/diagnostic-derive-doc-comment-field.stderr @@ -1,5 +1,5 @@ error[E0277]: the trait bound `NotIntoDiagArg: IntoDiagArg` is not satisfied - --> $DIR/diagnostic-derive-doc-comment-field.rs:36:10 + --> $DIR/diagnostic-derive-doc-comment-field.rs:37:10 | LL | #[derive(Diagnostic)] | ---------- required by a bound introduced by this call @@ -8,7 +8,7 @@ LL | arg: NotIntoDiagArg, | ^^^^^^^^^^^^^^ unsatisfied trait bound | help: the nightly-only, unstable trait `IntoDiagArg` is not implemented for `NotIntoDiagArg` - --> $DIR/diagnostic-derive-doc-comment-field.rs:28:1 + --> $DIR/diagnostic-derive-doc-comment-field.rs:29:1 | LL | struct NotIntoDiagArg; | ^^^^^^^^^^^^^^^^^^^^^ @@ -21,7 +21,7 @@ note: required by a bound in `Diag::<'a, G>::arg` = note: this error originates in the macro `with_fn` (in Nightly builds, run with -Z macro-backtrace for more info) error[E0277]: the trait bound `NotIntoDiagArg: IntoDiagArg` is not satisfied - --> $DIR/diagnostic-derive-doc-comment-field.rs:46:10 + --> $DIR/diagnostic-derive-doc-comment-field.rs:47:10 | LL | #[derive(Subdiagnostic)] | ------------- required by a bound introduced by this call @@ -30,7 +30,7 @@ LL | arg: NotIntoDiagArg, | ^^^^^^^^^^^^^^ unsatisfied trait bound | help: the nightly-only, unstable trait `IntoDiagArg` is not implemented for `NotIntoDiagArg` - --> $DIR/diagnostic-derive-doc-comment-field.rs:28:1 + --> $DIR/diagnostic-derive-doc-comment-field.rs:29:1 | LL | struct NotIntoDiagArg; | ^^^^^^^^^^^^^^^^^^^^^ diff --git a/tests/ui-fulldeps/session-diagnostic/diagnostic-derive.rs b/tests/ui-fulldeps/session-diagnostic/diagnostic-derive.rs index fa2d037064d2..798eca68b1c9 100644 --- a/tests/ui-fulldeps/session-diagnostic/diagnostic-derive.rs +++ b/tests/ui-fulldeps/session-diagnostic/diagnostic-derive.rs @@ -29,6 +29,8 @@ use rustc_errors::{Applicability, DiagMessage, ErrCode, MultiSpan, SubdiagMessag extern crate rustc_session; +extern crate core; + rustc_fluent_macro::fluent_messages! { "./example.ftl" } // E0123 and E0456 are no longer used, so we define our own constants here just for this test. @@ -56,7 +58,7 @@ enum DiagnosticOnEnum { #[derive(Diagnostic)] #[diag(no_crate_example, code = E0123)] #[diag = "E0123"] -//~^ ERROR failed to resolve: you might be missing crate `core` +//~^ ERROR expected parentheses: #[diag(...)] struct WrongStructAttrStyle {} #[derive(Diagnostic)] @@ -78,20 +80,17 @@ struct InvalidNestedStructAttr {} #[derive(Diagnostic)] #[diag(nonsense("foo"), code = E0123, slug = "foo")] -//~^ ERROR diagnostic slug must be the first argument -//~| ERROR diagnostic slug not specified +//~^ ERROR derive(Diagnostic): diagnostic slug not specified struct InvalidNestedStructAttr1 {} #[derive(Diagnostic)] #[diag(nonsense = "...", code = E0123, slug = "foo")] -//~^ ERROR unknown argument -//~| ERROR diagnostic slug not specified +//~^ ERROR diagnostic slug not specified struct InvalidNestedStructAttr2 {} #[derive(Diagnostic)] #[diag(nonsense = 4, code = E0123, slug = "foo")] -//~^ ERROR unknown argument -//~| ERROR diagnostic slug not specified +//~^ ERROR diagnostic slug not specified struct InvalidNestedStructAttr3 {} #[derive(Diagnostic)] @@ -111,7 +110,6 @@ struct WrongPlaceField { #[diag(no_crate_example, code = E0123)] #[diag(no_crate_example, code = E0456)] //~^ ERROR specified multiple times -//~^^ ERROR specified multiple times struct DiagSpecifiedTwice {} #[derive(Diagnostic)] @@ -541,7 +539,7 @@ struct LabelWithTrailingPath { #[diag(no_crate_example, code = E0123)] struct LabelWithTrailingNameValue { #[label(no_crate_label, foo = "...")] - //~^ ERROR only `no_span` is a valid nested attribute + //~^ ERROR no nested attribute expected here span: Span, } @@ -549,7 +547,7 @@ struct LabelWithTrailingNameValue { #[diag(no_crate_example, code = E0123)] struct LabelWithTrailingList { #[label(no_crate_label, foo("..."))] - //~^ ERROR only `no_span` is a valid nested attribute + //~^ ERROR no nested attribute expected here span: Span, } @@ -801,15 +799,15 @@ struct SuggestionsNoItem { struct SuggestionsInvalidItem { #[suggestion(code(foo))] //~^ ERROR `code(...)` must contain only string literals - //~| ERROR failed to resolve: you might be missing crate `core` + //~| ERROR unexpected token, expected `)` sub: Span, } -#[derive(Diagnostic)] //~ ERROR cannot find value `__code_34` in this scope +#[derive(Diagnostic)] #[diag(no_crate_example)] struct SuggestionsInvalidLiteral { #[suggestion(code = 3)] - //~^ ERROR failed to resolve: you might be missing crate `core` + //~^ ERROR expected string literal sub: Span, } diff --git a/tests/ui-fulldeps/session-diagnostic/diagnostic-derive.stderr b/tests/ui-fulldeps/session-diagnostic/diagnostic-derive.stderr index 77c48aceca8e..9ecb6c15767e 100644 --- a/tests/ui-fulldeps/session-diagnostic/diagnostic-derive.stderr +++ b/tests/ui-fulldeps/session-diagnostic/diagnostic-derive.stderr @@ -1,11 +1,11 @@ error: derive(Diagnostic): unsupported type attribute for diagnostic derive enum - --> $DIR/diagnostic-derive.rs:47:1 + --> $DIR/diagnostic-derive.rs:49:1 | LL | #[diag(no_crate_example, code = E0123)] | ^ error: derive(Diagnostic): diagnostic slug not specified - --> $DIR/diagnostic-derive.rs:50:5 + --> $DIR/diagnostic-derive.rs:52:5 | LL | Foo, | ^^^ @@ -13,21 +13,27 @@ LL | Foo, = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]` error: derive(Diagnostic): diagnostic slug not specified - --> $DIR/diagnostic-derive.rs:52:5 + --> $DIR/diagnostic-derive.rs:54:5 | LL | Bar, | ^^^ | = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]` +error: expected parentheses: #[diag(...)] + --> $DIR/diagnostic-derive.rs:60:8 + | +LL | #[diag = "E0123"] + | ^ + error: derive(Diagnostic): `#[nonsense(...)]` is not a valid attribute - --> $DIR/diagnostic-derive.rs:63:1 + --> $DIR/diagnostic-derive.rs:65:1 | LL | #[nonsense(no_crate_example, code = E0123)] | ^ error: derive(Diagnostic): diagnostic slug not specified - --> $DIR/diagnostic-derive.rs:63:1 + --> $DIR/diagnostic-derive.rs:65:1 | LL | #[nonsense(no_crate_example, code = E0123)] | ^ @@ -35,51 +41,29 @@ LL | #[nonsense(no_crate_example, code = E0123)] = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]` error: derive(Diagnostic): diagnostic slug not specified - --> $DIR/diagnostic-derive.rs:70:1 + --> $DIR/diagnostic-derive.rs:72:1 | LL | #[diag(code = E0123)] | ^ | = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]` -error: derive(Diagnostic): diagnostic slug must be the first argument - --> $DIR/diagnostic-derive.rs:80:16 - | -LL | #[diag(nonsense("foo"), code = E0123, slug = "foo")] - | ^ - error: derive(Diagnostic): diagnostic slug not specified - --> $DIR/diagnostic-derive.rs:80:1 + --> $DIR/diagnostic-derive.rs:82:1 | LL | #[diag(nonsense("foo"), code = E0123, slug = "foo")] | ^ | = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]` -error: derive(Diagnostic): unknown argument - --> $DIR/diagnostic-derive.rs:86:8 - | -LL | #[diag(nonsense = "...", code = E0123, slug = "foo")] - | ^^^^^^^^ - | - = note: only the `code` parameter is valid after the slug - error: derive(Diagnostic): diagnostic slug not specified - --> $DIR/diagnostic-derive.rs:86:1 + --> $DIR/diagnostic-derive.rs:87:1 | LL | #[diag(nonsense = "...", code = E0123, slug = "foo")] | ^ | = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]` -error: derive(Diagnostic): unknown argument - --> $DIR/diagnostic-derive.rs:92:8 - | -LL | #[diag(nonsense = 4, code = E0123, slug = "foo")] - | ^^^^^^^^ - | - = note: only the `code` parameter is valid after the slug - error: derive(Diagnostic): diagnostic slug not specified --> $DIR/diagnostic-derive.rs:92:1 | @@ -89,7 +73,7 @@ LL | #[diag(nonsense = 4, code = E0123, slug = "foo")] = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]` error: derive(Diagnostic): unknown argument - --> $DIR/diagnostic-derive.rs:98:40 + --> $DIR/diagnostic-derive.rs:97:40 | LL | #[diag(no_crate_example, code = E0123, slug = "foo")] | ^^^^ @@ -97,55 +81,43 @@ LL | #[diag(no_crate_example, code = E0123, slug = "foo")] = note: only the `code` parameter is valid after the slug error: derive(Diagnostic): `#[suggestion = ...]` is not a valid attribute - --> $DIR/diagnostic-derive.rs:105:5 + --> $DIR/diagnostic-derive.rs:104:5 | LL | #[suggestion = "bar"] | ^ error: derive(Diagnostic): attribute specified multiple times - --> $DIR/diagnostic-derive.rs:112:8 - | -LL | #[diag(no_crate_example, code = E0456)] - | ^^^^^^^^^^^^^^^^ - | -note: previously specified here - --> $DIR/diagnostic-derive.rs:111:8 - | -LL | #[diag(no_crate_example, code = E0123)] - | ^^^^^^^^^^^^^^^^ - -error: derive(Diagnostic): attribute specified multiple times - --> $DIR/diagnostic-derive.rs:112:26 - | -LL | #[diag(no_crate_example, code = E0456)] - | ^^^^ - | -note: previously specified here --> $DIR/diagnostic-derive.rs:111:26 | +LL | #[diag(no_crate_example, code = E0456)] + | ^^^^ + | +note: previously specified here + --> $DIR/diagnostic-derive.rs:110:26 + | LL | #[diag(no_crate_example, code = E0123)] | ^^^^ error: derive(Diagnostic): attribute specified multiple times - --> $DIR/diagnostic-derive.rs:118:40 + --> $DIR/diagnostic-derive.rs:116:40 | LL | #[diag(no_crate_example, code = E0123, code = E0456)] | ^^^^ | note: previously specified here - --> $DIR/diagnostic-derive.rs:118:26 + --> $DIR/diagnostic-derive.rs:116:26 | LL | #[diag(no_crate_example, code = E0123, code = E0456)] | ^^^^ error: derive(Diagnostic): diagnostic slug must be the first argument - --> $DIR/diagnostic-derive.rs:123:43 + --> $DIR/diagnostic-derive.rs:121:26 | LL | #[diag(no_crate_example, no_crate::example, code = E0123)] - | ^ + | ^^^^^^^^ error: derive(Diagnostic): diagnostic slug not specified - --> $DIR/diagnostic-derive.rs:128:1 + --> $DIR/diagnostic-derive.rs:126:1 | LL | struct KindNotProvided {} | ^^^^^^ @@ -153,7 +125,7 @@ LL | struct KindNotProvided {} = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]` error: derive(Diagnostic): diagnostic slug not specified - --> $DIR/diagnostic-derive.rs:131:1 + --> $DIR/diagnostic-derive.rs:129:1 | LL | #[diag(code = E0123)] | ^ @@ -161,31 +133,31 @@ LL | #[diag(code = E0123)] = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]` error: derive(Diagnostic): the `#[primary_span]` attribute can only be applied to fields of type `Span` or `MultiSpan` - --> $DIR/diagnostic-derive.rs:142:5 + --> $DIR/diagnostic-derive.rs:140:5 | LL | #[primary_span] | ^ error: derive(Diagnostic): `#[nonsense]` is not a valid attribute - --> $DIR/diagnostic-derive.rs:150:5 + --> $DIR/diagnostic-derive.rs:148:5 | LL | #[nonsense] | ^ error: derive(Diagnostic): the `#[label(...)]` attribute can only be applied to fields of type `Span` or `MultiSpan` - --> $DIR/diagnostic-derive.rs:167:5 + --> $DIR/diagnostic-derive.rs:165:5 | LL | #[label(no_crate_label)] | ^ error: derive(Diagnostic): `name` doesn't refer to a field on this type - --> $DIR/diagnostic-derive.rs:175:46 + --> $DIR/diagnostic-derive.rs:173:46 | LL | #[suggestion(no_crate_suggestion, code = "{name}")] | ^^^^^^^^ error: invalid format string: expected `}` but string was terminated - --> $DIR/diagnostic-derive.rs:180:10 + --> $DIR/diagnostic-derive.rs:178:10 | LL | #[derive(Diagnostic)] | ^^^^^^^^^^ expected `}` in format string @@ -194,7 +166,7 @@ LL | #[derive(Diagnostic)] = note: this error originates in the derive macro `Diagnostic` (in Nightly builds, run with -Z macro-backtrace for more info) error: invalid format string: unmatched `}` found - --> $DIR/diagnostic-derive.rs:190:10 + --> $DIR/diagnostic-derive.rs:188:10 | LL | #[derive(Diagnostic)] | ^^^^^^^^^^ unmatched `}` in format string @@ -203,47 +175,47 @@ LL | #[derive(Diagnostic)] = note: this error originates in the derive macro `Diagnostic` (in Nightly builds, run with -Z macro-backtrace for more info) error: derive(Diagnostic): the `#[label(...)]` attribute can only be applied to fields of type `Span` or `MultiSpan` - --> $DIR/diagnostic-derive.rs:210:5 + --> $DIR/diagnostic-derive.rs:208:5 | LL | #[label(no_crate_label)] | ^ error: derive(Diagnostic): suggestion without `code = "..."` - --> $DIR/diagnostic-derive.rs:229:5 + --> $DIR/diagnostic-derive.rs:227:5 | LL | #[suggestion(no_crate_suggestion)] | ^ error: derive(Diagnostic): invalid nested attribute - --> $DIR/diagnostic-derive.rs:237:18 + --> $DIR/diagnostic-derive.rs:235:18 | LL | #[suggestion(nonsense = "bar")] | ^^^^^^^^ | - = help: only `no_span`, `style`, `code` and `applicability` are valid nested attributes + = help: only `style`, `code` and `applicability` are valid nested attributes error: derive(Diagnostic): suggestion without `code = "..."` - --> $DIR/diagnostic-derive.rs:237:5 + --> $DIR/diagnostic-derive.rs:235:5 | LL | #[suggestion(nonsense = "bar")] | ^ error: derive(Diagnostic): invalid nested attribute - --> $DIR/diagnostic-derive.rs:246:18 + --> $DIR/diagnostic-derive.rs:244:18 | LL | #[suggestion(msg = "bar")] | ^^^ | - = help: only `no_span`, `style`, `code` and `applicability` are valid nested attributes + = help: only `style`, `code` and `applicability` are valid nested attributes error: derive(Diagnostic): suggestion without `code = "..."` - --> $DIR/diagnostic-derive.rs:246:5 + --> $DIR/diagnostic-derive.rs:244:5 | LL | #[suggestion(msg = "bar")] | ^ error: derive(Diagnostic): wrong field type for suggestion - --> $DIR/diagnostic-derive.rs:269:5 + --> $DIR/diagnostic-derive.rs:267:5 | LL | #[suggestion(no_crate_suggestion, code = "This is suggested code")] | ^ @@ -251,79 +223,79 @@ LL | #[suggestion(no_crate_suggestion, code = "This is suggested code")] = help: `#[suggestion(...)]` should be applied to fields of type `Span` or `(Span, Applicability)` error: derive(Diagnostic): attribute specified multiple times - --> $DIR/diagnostic-derive.rs:285:24 + --> $DIR/diagnostic-derive.rs:283:24 | LL | suggestion: (Span, Span, Applicability), | ^^^^ | note: previously specified here - --> $DIR/diagnostic-derive.rs:285:18 + --> $DIR/diagnostic-derive.rs:283:18 | LL | suggestion: (Span, Span, Applicability), | ^^^^ error: derive(Diagnostic): attribute specified multiple times - --> $DIR/diagnostic-derive.rs:293:33 + --> $DIR/diagnostic-derive.rs:291:33 | LL | suggestion: (Applicability, Applicability, Span), | ^^^^^^^^^^^^^ | note: previously specified here - --> $DIR/diagnostic-derive.rs:293:18 + --> $DIR/diagnostic-derive.rs:291:18 | LL | suggestion: (Applicability, Applicability, Span), | ^^^^^^^^^^^^^ error: derive(Diagnostic): `#[label = ...]` is not a valid attribute - --> $DIR/diagnostic-derive.rs:300:5 + --> $DIR/diagnostic-derive.rs:298:5 | LL | #[label = "bar"] | ^ error: derive(Diagnostic): attribute specified multiple times - --> $DIR/diagnostic-derive.rs:451:5 + --> $DIR/diagnostic-derive.rs:449:5 | LL | #[suggestion(no_crate_suggestion, code = "...", applicability = "maybe-incorrect")] | ^ | note: previously specified here - --> $DIR/diagnostic-derive.rs:453:24 + --> $DIR/diagnostic-derive.rs:451:24 | LL | suggestion: (Span, Applicability), | ^^^^^^^^^^^^^ error: derive(Diagnostic): invalid applicability - --> $DIR/diagnostic-derive.rs:459:69 + --> $DIR/diagnostic-derive.rs:457:69 | LL | #[suggestion(no_crate_suggestion, code = "...", applicability = "batman")] | ^^^^^^^^ error: derive(Diagnostic): the `#[help(...)]` attribute can only be applied to fields of type `Span`, `MultiSpan`, `bool` or `()` - --> $DIR/diagnostic-derive.rs:526:5 + --> $DIR/diagnostic-derive.rs:524:5 | LL | #[help(no_crate_help)] | ^ error: derive(Diagnostic): a diagnostic slug must be the first argument to the attribute - --> $DIR/diagnostic-derive.rs:535:32 + --> $DIR/diagnostic-derive.rs:533:29 | LL | #[label(no_crate_label, foo)] - | ^ + | ^^^ -error: derive(Diagnostic): only `no_span` is a valid nested attribute - --> $DIR/diagnostic-derive.rs:543:29 +error: derive(Diagnostic): no nested attribute expected here + --> $DIR/diagnostic-derive.rs:541:29 | LL | #[label(no_crate_label, foo = "...")] | ^^^ -error: derive(Diagnostic): only `no_span` is a valid nested attribute - --> $DIR/diagnostic-derive.rs:551:29 +error: derive(Diagnostic): no nested attribute expected here + --> $DIR/diagnostic-derive.rs:549:29 | LL | #[label(no_crate_label, foo("..."))] | ^^^ error: derive(Diagnostic): `#[primary_span]` is not a valid attribute - --> $DIR/diagnostic-derive.rs:563:5 + --> $DIR/diagnostic-derive.rs:561:5 | LL | #[primary_span] | ^ @@ -331,13 +303,13 @@ LL | #[primary_span] = help: the `primary_span` field attribute is not valid for lint diagnostics error: derive(Diagnostic): `#[error(...)]` is not a valid attribute - --> $DIR/diagnostic-derive.rs:583:1 + --> $DIR/diagnostic-derive.rs:581:1 | LL | #[error(no_crate_example, code = E0123)] | ^ error: derive(Diagnostic): diagnostic slug not specified - --> $DIR/diagnostic-derive.rs:583:1 + --> $DIR/diagnostic-derive.rs:581:1 | LL | #[error(no_crate_example, code = E0123)] | ^ @@ -345,13 +317,13 @@ LL | #[error(no_crate_example, code = E0123)] = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]` error: derive(Diagnostic): `#[warn_(...)]` is not a valid attribute - --> $DIR/diagnostic-derive.rs:590:1 + --> $DIR/diagnostic-derive.rs:588:1 | LL | #[warn_(no_crate_example, code = E0123)] | ^ error: derive(Diagnostic): diagnostic slug not specified - --> $DIR/diagnostic-derive.rs:590:1 + --> $DIR/diagnostic-derive.rs:588:1 | LL | #[warn_(no_crate_example, code = E0123)] | ^ @@ -359,13 +331,13 @@ LL | #[warn_(no_crate_example, code = E0123)] = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]` error: derive(Diagnostic): `#[lint(...)]` is not a valid attribute - --> $DIR/diagnostic-derive.rs:597:1 + --> $DIR/diagnostic-derive.rs:595:1 | LL | #[lint(no_crate_example, code = E0123)] | ^ error: derive(Diagnostic): diagnostic slug not specified - --> $DIR/diagnostic-derive.rs:597:1 + --> $DIR/diagnostic-derive.rs:595:1 | LL | #[lint(no_crate_example, code = E0123)] | ^ @@ -373,13 +345,13 @@ LL | #[lint(no_crate_example, code = E0123)] = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]` error: derive(Diagnostic): `#[lint(...)]` is not a valid attribute - --> $DIR/diagnostic-derive.rs:604:1 + --> $DIR/diagnostic-derive.rs:602:1 | LL | #[lint(no_crate_example, code = E0123)] | ^ error: derive(Diagnostic): diagnostic slug not specified - --> $DIR/diagnostic-derive.rs:604:1 + --> $DIR/diagnostic-derive.rs:602:1 | LL | #[lint(no_crate_example, code = E0123)] | ^ @@ -387,19 +359,19 @@ LL | #[lint(no_crate_example, code = E0123)] = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]` error: derive(Diagnostic): attribute specified multiple times - --> $DIR/diagnostic-derive.rs:613:53 + --> $DIR/diagnostic-derive.rs:611:53 | LL | #[suggestion(no_crate_suggestion, code = "...", code = ",,,")] | ^^^^ | note: previously specified here - --> $DIR/diagnostic-derive.rs:613:39 + --> $DIR/diagnostic-derive.rs:611:39 | LL | #[suggestion(no_crate_suggestion, code = "...", code = ",,,")] | ^^^^ error: derive(Diagnostic): wrong types for suggestion - --> $DIR/diagnostic-derive.rs:622:24 + --> $DIR/diagnostic-derive.rs:620:24 | LL | suggestion: (Span, usize), | ^^^^^ @@ -407,7 +379,7 @@ LL | suggestion: (Span, usize), = help: `#[suggestion(...)]` on a tuple field must be applied to fields of type `(Span, Applicability)` error: derive(Diagnostic): wrong types for suggestion - --> $DIR/diagnostic-derive.rs:630:17 + --> $DIR/diagnostic-derive.rs:628:17 | LL | suggestion: (Span,), | ^^^^^^^ @@ -415,13 +387,13 @@ LL | suggestion: (Span,), = help: `#[suggestion(...)]` on a tuple field must be applied to fields of type `(Span, Applicability)` error: derive(Diagnostic): suggestion without `code = "..."` - --> $DIR/diagnostic-derive.rs:637:5 + --> $DIR/diagnostic-derive.rs:635:5 | LL | #[suggestion(no_crate_suggestion)] | ^ error: derive(Diagnostic): `#[multipart_suggestion(...)]` is not a valid attribute - --> $DIR/diagnostic-derive.rs:644:1 + --> $DIR/diagnostic-derive.rs:642:1 | LL | #[multipart_suggestion(no_crate_suggestion)] | ^ @@ -429,7 +401,7 @@ LL | #[multipart_suggestion(no_crate_suggestion)] = help: consider creating a `Subdiagnostic` instead error: derive(Diagnostic): `#[multipart_suggestion(...)]` is not a valid attribute - --> $DIR/diagnostic-derive.rs:647:1 + --> $DIR/diagnostic-derive.rs:645:1 | LL | #[multipart_suggestion()] | ^ @@ -437,7 +409,7 @@ LL | #[multipart_suggestion()] = help: consider creating a `Subdiagnostic` instead error: derive(Diagnostic): `#[multipart_suggestion(...)]` is not a valid attribute - --> $DIR/diagnostic-derive.rs:651:5 + --> $DIR/diagnostic-derive.rs:649:5 | LL | #[multipart_suggestion(no_crate_suggestion)] | ^ @@ -445,7 +417,7 @@ LL | #[multipart_suggestion(no_crate_suggestion)] = help: consider creating a `Subdiagnostic` instead error: derive(Diagnostic): `#[suggestion(...)]` is not a valid attribute - --> $DIR/diagnostic-derive.rs:659:1 + --> $DIR/diagnostic-derive.rs:657:1 | LL | #[suggestion(no_crate_suggestion, code = "...")] | ^ @@ -453,7 +425,7 @@ LL | #[suggestion(no_crate_suggestion, code = "...")] = help: `#[label]` and `#[suggestion]` can only be applied to fields error: derive(Diagnostic): `#[label]` is not a valid attribute - --> $DIR/diagnostic-derive.rs:668:1 + --> $DIR/diagnostic-derive.rs:666:1 | LL | #[label] | ^ @@ -461,61 +433,73 @@ LL | #[label] = help: `#[label]` and `#[suggestion]` can only be applied to fields error: derive(Diagnostic): `#[subdiagnostic(...)]` is not a valid attribute - --> $DIR/diagnostic-derive.rs:702:5 + --> $DIR/diagnostic-derive.rs:700:5 | LL | #[subdiagnostic(bad)] | ^ error: derive(Diagnostic): `#[subdiagnostic = ...]` is not a valid attribute - --> $DIR/diagnostic-derive.rs:710:5 + --> $DIR/diagnostic-derive.rs:708:5 | LL | #[subdiagnostic = "bad"] | ^ error: derive(Diagnostic): `#[subdiagnostic(...)]` is not a valid attribute - --> $DIR/diagnostic-derive.rs:718:5 + --> $DIR/diagnostic-derive.rs:716:5 | LL | #[subdiagnostic(bad, bad)] | ^ error: derive(Diagnostic): `#[subdiagnostic(...)]` is not a valid attribute - --> $DIR/diagnostic-derive.rs:726:5 + --> $DIR/diagnostic-derive.rs:724:5 | LL | #[subdiagnostic("bad")] | ^ error: derive(Diagnostic): `#[subdiagnostic(...)]` is not a valid attribute - --> $DIR/diagnostic-derive.rs:734:5 + --> $DIR/diagnostic-derive.rs:732:5 | LL | #[subdiagnostic(eager)] | ^ error: derive(Diagnostic): `#[subdiagnostic(...)]` is not a valid attribute - --> $DIR/diagnostic-derive.rs:742:5 + --> $DIR/diagnostic-derive.rs:740:5 | LL | #[subdiagnostic(eager)] | ^ error: derive(Diagnostic): `#[subdiagnostic(...)]` is not a valid attribute - --> $DIR/diagnostic-derive.rs:763:5 + --> $DIR/diagnostic-derive.rs:761:5 | LL | #[subdiagnostic(eager)] | ^ error: derive(Diagnostic): expected at least one string literal for `code(...)` - --> $DIR/diagnostic-derive.rs:794:23 + --> $DIR/diagnostic-derive.rs:792:23 | LL | #[suggestion(code())] | ^ error: derive(Diagnostic): `code(...)` must contain only string literals - --> $DIR/diagnostic-derive.rs:802:23 + --> $DIR/diagnostic-derive.rs:800:23 | LL | #[suggestion(code(foo))] | ^^^ +error: unexpected token, expected `)` + --> $DIR/diagnostic-derive.rs:800:23 + | +LL | #[suggestion(code(foo))] + | ^^^ + +error: expected string literal + --> $DIR/diagnostic-derive.rs:809:25 + | +LL | #[suggestion(code = 3)] + | ^ + error: derive(Diagnostic): `#[suggestion(...)]` is not a valid attribute - --> $DIR/diagnostic-derive.rs:826:5 + --> $DIR/diagnostic-derive.rs:824:5 | LL | #[suggestion(no_crate_suggestion, code = "")] | ^ @@ -524,38 +508,20 @@ LL | #[suggestion(no_crate_suggestion, code = "")] = help: to show a suggestion consisting of multiple parts, use a `Subdiagnostic` annotated with `#[multipart_suggestion(...)]` = help: to show a variable set of suggestions, use a `Vec` of `Subdiagnostic`s annotated with `#[suggestion(...)]` -error[E0433]: failed to resolve: you might be missing crate `core` - --> $DIR/diagnostic-derive.rs:58:8 - | -LL | #[diag = "E0123"] - | ^ you might be missing crate `core` - -error[E0433]: failed to resolve: you might be missing crate `core` - --> $DIR/diagnostic-derive.rs:802:23 - | -LL | #[suggestion(code(foo))] - | ^^^ you might be missing crate `core` - -error[E0433]: failed to resolve: you might be missing crate `core` - --> $DIR/diagnostic-derive.rs:811:25 - | -LL | #[suggestion(code = 3)] - | ^ you might be missing crate `core` - error: cannot find attribute `nonsense` in this scope - --> $DIR/diagnostic-derive.rs:63:3 + --> $DIR/diagnostic-derive.rs:65:3 | LL | #[nonsense(no_crate_example, code = E0123)] | ^^^^^^^^ error: cannot find attribute `nonsense` in this scope - --> $DIR/diagnostic-derive.rs:150:7 + --> $DIR/diagnostic-derive.rs:148:7 | LL | #[nonsense] | ^^^^^^^^ error: cannot find attribute `error` in this scope - --> $DIR/diagnostic-derive.rs:583:3 + --> $DIR/diagnostic-derive.rs:581:3 | LL | #[error(no_crate_example, code = E0123)] | ^^^^^ @@ -567,7 +533,7 @@ LL | struct ErrorAttribute {} | error: cannot find attribute `warn_` in this scope - --> $DIR/diagnostic-derive.rs:590:3 + --> $DIR/diagnostic-derive.rs:588:3 | LL | #[warn_(no_crate_example, code = E0123)] | ^^^^^ @@ -579,7 +545,7 @@ LL + #[warn(no_crate_example, code = E0123)] | error: cannot find attribute `lint` in this scope - --> $DIR/diagnostic-derive.rs:597:3 + --> $DIR/diagnostic-derive.rs:595:3 | LL | #[lint(no_crate_example, code = E0123)] | ^^^^ @@ -591,7 +557,7 @@ LL + #[link(no_crate_example, code = E0123)] | error: cannot find attribute `lint` in this scope - --> $DIR/diagnostic-derive.rs:604:3 + --> $DIR/diagnostic-derive.rs:602:3 | LL | #[lint(no_crate_example, code = E0123)] | ^^^^ @@ -603,7 +569,7 @@ LL + #[link(no_crate_example, code = E0123)] | error: cannot find attribute `multipart_suggestion` in this scope - --> $DIR/diagnostic-derive.rs:644:3 + --> $DIR/diagnostic-derive.rs:642:3 | LL | #[multipart_suggestion(no_crate_suggestion)] | ^^^^^^^^^^^^^^^^^^^^ @@ -615,7 +581,7 @@ LL | struct MultipartSuggestion { | error: cannot find attribute `multipart_suggestion` in this scope - --> $DIR/diagnostic-derive.rs:647:3 + --> $DIR/diagnostic-derive.rs:645:3 | LL | #[multipart_suggestion()] | ^^^^^^^^^^^^^^^^^^^^ @@ -627,7 +593,7 @@ LL | struct MultipartSuggestion { | error: cannot find attribute `multipart_suggestion` in this scope - --> $DIR/diagnostic-derive.rs:651:7 + --> $DIR/diagnostic-derive.rs:649:7 | LL | #[multipart_suggestion(no_crate_suggestion)] | ^^^^^^^^^^^^^^^^^^^^ @@ -635,21 +601,13 @@ LL | #[multipart_suggestion(no_crate_suggestion)] = note: `multipart_suggestion` is an attribute that can be used by the derive macro `Subdiagnostic`, you might be missing a `derive` attribute error[E0425]: cannot find value `nonsense` in module `crate::fluent_generated` - --> $DIR/diagnostic-derive.rs:75:8 + --> $DIR/diagnostic-derive.rs:77:8 | LL | #[diag(nonsense, code = E0123)] | ^^^^^^^^ not found in `crate::fluent_generated` -error[E0425]: cannot find value `__code_34` in this scope - --> $DIR/diagnostic-derive.rs:808:10 - | -LL | #[derive(Diagnostic)] - | ^^^^^^^^^^ not found in this scope - | - = note: this error originates in the derive macro `Diagnostic` (in Nightly builds, run with -Z macro-backtrace for more info) - error[E0277]: the trait bound `Hello: IntoDiagArg` is not satisfied - --> $DIR/diagnostic-derive.rs:349:12 + --> $DIR/diagnostic-derive.rs:347:12 | LL | #[derive(Diagnostic)] | ---------- required by a bound introduced by this call @@ -658,7 +616,7 @@ LL | other: Hello, | ^^^^^ unsatisfied trait bound | help: the nightly-only, unstable trait `IntoDiagArg` is not implemented for `Hello` - --> $DIR/diagnostic-derive.rs:40:1 + --> $DIR/diagnostic-derive.rs:42:1 | LL | struct Hello {} | ^^^^^^^^^^^^ @@ -670,7 +628,7 @@ note: required by a bound in `Diag::<'a, G>::arg` = note: in this macro invocation = note: this error originates in the macro `with_fn` (in Nightly builds, run with -Z macro-backtrace for more info) -error: aborting due to 85 previous errors +error: aborting due to 80 previous errors -Some errors have detailed explanations: E0277, E0425, E0433. +Some errors have detailed explanations: E0277, E0425. For more information about an error, try `rustc --explain E0277`. diff --git a/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive-2.rs b/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive-2.rs new file mode 100644 index 000000000000..f42fe1689842 --- /dev/null +++ b/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive-2.rs @@ -0,0 +1,37 @@ +//@ check-fail +// Tests error conditions for specifying subdiagnostics using #[derive(Subdiagnostic)]. +// This test is split off from the main `subdiagnostic-derive`, +// because this error is generated post-expansion. + +// The proc_macro2 crate handles spans differently when on beta/stable release rather than nightly, +// changing the output of this test. Since Subdiagnostic is strictly internal to the compiler +// the test is just ignored on stable and beta: +//@ ignore-stage1 +//@ ignore-beta +//@ ignore-stable + +#![feature(rustc_private)] +#![crate_type = "lib"] + +extern crate rustc_errors; +extern crate rustc_fluent_macro; +extern crate rustc_macros; +extern crate rustc_session; +extern crate rustc_span; +extern crate core; + +use rustc_errors::{Applicability, DiagMessage, SubdiagMessage}; +use rustc_macros::Subdiagnostic; +use rustc_span::Span; + +rustc_fluent_macro::fluent_messages! { "./example.ftl" } + +#[derive(Subdiagnostic)] +#[label(slug)] +//~^ ERROR cannot find value `slug` in module `crate::fluent_generated` +//~^^ NOTE not found in `crate::fluent_generated` +struct L { + #[primary_span] + span: Span, + var: String, +} diff --git a/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive-2.stderr b/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive-2.stderr new file mode 100644 index 000000000000..37566e39fcd6 --- /dev/null +++ b/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive-2.stderr @@ -0,0 +1,9 @@ +error[E0425]: cannot find value `slug` in module `crate::fluent_generated` + --> $DIR/subdiagnostic-derive-2.rs:30:9 + | +LL | #[label(slug)] + | ^^^^ not found in `crate::fluent_generated` + +error: aborting due to 1 previous error + +For more information about this error, try `rustc --explain E0425`. diff --git a/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive.rs b/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive.rs index c837372a7a7a..b2e7b4c61daa 100644 --- a/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive.rs +++ b/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive.rs @@ -16,6 +16,7 @@ extern crate rustc_fluent_macro; extern crate rustc_macros; extern crate rustc_session; extern crate rustc_span; +extern crate core; use rustc_errors::{Applicability, DiagMessage, SubdiagMessage}; use rustc_macros::Subdiagnostic; @@ -84,7 +85,7 @@ struct F { #[derive(Subdiagnostic)] #[label(bug = "...")] -//~^ ERROR only `no_span` is a valid nested attribute +//~^ ERROR no nested attribute expected here //~| ERROR diagnostic slug must be first argument struct G { #[primary_span] @@ -94,8 +95,7 @@ struct G { #[derive(Subdiagnostic)] #[label("...")] -//~^ ERROR failed to resolve: you might be missing crate `core` -//~| NOTE you might be missing crate `core` +//~^ ERROR expected identifier struct H { #[primary_span] span: Span, @@ -104,7 +104,7 @@ struct H { #[derive(Subdiagnostic)] #[label(slug = 4)] -//~^ ERROR only `no_span` is a valid nested attribute +//~^ ERROR no nested attribute expected here //~| ERROR diagnostic slug must be first argument struct J { #[primary_span] @@ -114,7 +114,7 @@ struct J { #[derive(Subdiagnostic)] #[label(slug("..."))] -//~^ ERROR only `no_span` is a valid nested attribute +//~^ ERROR no nested attribute expected here //~| ERROR diagnostic slug must be first argument struct K { #[primary_span] @@ -122,16 +122,6 @@ struct K { var: String, } -#[derive(Subdiagnostic)] -#[label(slug)] -//~^ ERROR cannot find value `slug` in module `crate::fluent_generated` -//~^^ NOTE not found in `crate::fluent_generated` -struct L { - #[primary_span] - span: Span, - var: String, -} - #[derive(Subdiagnostic)] #[label()] //~^ ERROR diagnostic slug must be first argument of a `#[label(...)]` attribute @@ -143,7 +133,7 @@ struct M { #[derive(Subdiagnostic)] #[label(no_crate_example, code = "...")] -//~^ ERROR only `no_span` is a valid nested attribute +//~^ ERROR no nested attribute expected here struct N { #[primary_span] span: Span, @@ -152,7 +142,7 @@ struct N { #[derive(Subdiagnostic)] #[label(no_crate_example, applicability = "machine-applicable")] -//~^ ERROR only `no_span` is a valid nested attribute +//~^ ERROR no nested attribute expected here struct O { #[primary_span] span: Span, @@ -224,7 +214,7 @@ enum T { enum U { #[label(code = "...")] //~^ ERROR diagnostic slug must be first argument of a `#[label(...)]` attribute - //~| ERROR only `no_span` is a valid nested attribute + //~| ERROR no nested attribute expected here A { #[primary_span] span: Span, @@ -310,8 +300,7 @@ struct AB { #[derive(Subdiagnostic)] union AC { - //~^ ERROR failed to resolve: you might be missing crate `core` - //~| NOTE you might be missing crate `core` + //~^ ERROR unexpected unsupported untagged union span: u32, b: u64, } @@ -581,8 +570,7 @@ struct BD { span2: Span, #[suggestion_part(foo = "bar")] //~^ ERROR `code` is the only valid nested attribute - //~| ERROR failed to resolve: you might be missing crate `core` - //~| NOTE you might be missing crate `core` + //~| ERROR expected `,` span4: Span, #[suggestion_part(code = "...")] //~^ ERROR the `#[suggestion_part(...)]` attribute can only be applied to fields of type `Span` or `MultiSpan` @@ -674,8 +662,7 @@ enum BL { struct BM { #[suggestion_part(code("foo"))] //~^ ERROR expected exactly one string literal for `code = ...` - //~| ERROR failed to resolve: you might be missing crate `core` - //~| NOTE you might be missing crate `core` + //~| ERROR unexpected token, expected `)` span: Span, r#type: String, } @@ -685,8 +672,7 @@ struct BM { struct BN { #[suggestion_part(code("foo", "bar"))] //~^ ERROR expected exactly one string literal for `code = ...` - //~| ERROR failed to resolve: you might be missing crate `core` - //~| NOTE you might be missing crate `core` + //~| ERROR unexpected token, expected `)` span: Span, r#type: String, } @@ -696,8 +682,7 @@ struct BN { struct BO { #[suggestion_part(code(3))] //~^ ERROR expected exactly one string literal for `code = ...` - //~| ERROR failed to resolve: you might be missing crate `core` - //~| NOTE you might be missing crate `core` + //~| ERROR unexpected token, expected `)` span: Span, r#type: String, } @@ -712,14 +697,10 @@ struct BP { } #[derive(Subdiagnostic)] -//~^ ERROR cannot find value `__code_29` in this scope -//~| NOTE in this expansion -//~| NOTE not found in this scope #[multipart_suggestion(no_crate_example)] struct BQ { #[suggestion_part(code = 3)] - //~^ ERROR failed to resolve: you might be missing crate `core` - //~| NOTE you might be missing crate `core` + //~^ ERROR expected string literal span: Span, r#type: String, } @@ -794,7 +775,7 @@ struct SuggestionStyleInvalid1 { #[derive(Subdiagnostic)] #[suggestion(no_crate_example, code = "", style = 42)] -//~^ ERROR expected `= "xxx"` +//~^ ERROR expected string literal struct SuggestionStyleInvalid2 { #[primary_span] sub: Span, @@ -810,9 +791,7 @@ struct SuggestionStyleInvalid3 { #[derive(Subdiagnostic)] #[suggestion(no_crate_example, code = "", style("foo"))] -//~^ ERROR expected `= "xxx"` -//~| ERROR failed to resolve: you might be missing crate `core` -//~| NOTE you might be missing crate `core` +//~^ ERROR expected `=` struct SuggestionStyleInvalid4 { #[primary_span] sub: Span, diff --git a/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive.stderr b/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive.stderr index 0ae7ba4c4973..63634741e934 100644 --- a/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive.stderr +++ b/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive.stderr @@ -1,40 +1,46 @@ error: derive(Diagnostic): label without `#[primary_span]` field - --> $DIR/subdiagnostic-derive.rs:51:1 + --> $DIR/subdiagnostic-derive.rs:52:1 | LL | #[label(no_crate_example)] | ^ error: derive(Diagnostic): diagnostic slug must be first argument of a `#[label(...)]` attribute - --> $DIR/subdiagnostic-derive.rs:58:1 + --> $DIR/subdiagnostic-derive.rs:59:1 | LL | #[label] | ^ error: derive(Diagnostic): `#[foo]` is not a valid attribute - --> $DIR/subdiagnostic-derive.rs:67:1 + --> $DIR/subdiagnostic-derive.rs:68:1 | LL | #[foo] | ^ error: derive(Diagnostic): `#[label = ...]` is not a valid attribute - --> $DIR/subdiagnostic-derive.rs:77:1 + --> $DIR/subdiagnostic-derive.rs:78:1 | LL | #[label = "..."] | ^ -error: derive(Diagnostic): only `no_span` is a valid nested attribute - --> $DIR/subdiagnostic-derive.rs:86:9 +error: derive(Diagnostic): no nested attribute expected here + --> $DIR/subdiagnostic-derive.rs:87:9 | LL | #[label(bug = "...")] | ^^^ error: derive(Diagnostic): diagnostic slug must be first argument of a `#[label(...)]` attribute - --> $DIR/subdiagnostic-derive.rs:86:1 + --> $DIR/subdiagnostic-derive.rs:87:1 | LL | #[label(bug = "...")] | ^ -error: derive(Diagnostic): only `no_span` is a valid nested attribute +error: expected identifier + --> $DIR/subdiagnostic-derive.rs:97:9 + | +LL | #[label("...")] + | ^^^^^ + +error: derive(Diagnostic): no nested attribute expected here --> $DIR/subdiagnostic-derive.rs:106:9 | LL | #[label(slug = 4)] @@ -46,7 +52,7 @@ error: derive(Diagnostic): diagnostic slug must be first argument of a `#[label( LL | #[label(slug = 4)] | ^ -error: derive(Diagnostic): only `no_span` is a valid nested attribute +error: derive(Diagnostic): no nested attribute expected here --> $DIR/subdiagnostic-derive.rs:116:9 | LL | #[label(slug("..."))] @@ -59,85 +65,85 @@ LL | #[label(slug("..."))] | ^ error: derive(Diagnostic): diagnostic slug must be first argument of a `#[label(...)]` attribute - --> $DIR/subdiagnostic-derive.rs:136:1 + --> $DIR/subdiagnostic-derive.rs:126:1 | LL | #[label()] | ^ -error: derive(Diagnostic): only `no_span` is a valid nested attribute - --> $DIR/subdiagnostic-derive.rs:145:27 +error: derive(Diagnostic): no nested attribute expected here + --> $DIR/subdiagnostic-derive.rs:135:27 | LL | #[label(no_crate_example, code = "...")] | ^^^^ -error: derive(Diagnostic): only `no_span` is a valid nested attribute - --> $DIR/subdiagnostic-derive.rs:154:27 +error: derive(Diagnostic): no nested attribute expected here + --> $DIR/subdiagnostic-derive.rs:144:27 | LL | #[label(no_crate_example, applicability = "machine-applicable")] | ^^^^^^^^^^^^^ error: derive(Diagnostic): unsupported type attribute for subdiagnostic enum - --> $DIR/subdiagnostic-derive.rs:163:1 + --> $DIR/subdiagnostic-derive.rs:153:1 | LL | #[foo] | ^ error: derive(Diagnostic): `#[bar]` is not a valid attribute - --> $DIR/subdiagnostic-derive.rs:177:5 + --> $DIR/subdiagnostic-derive.rs:167:5 | LL | #[bar] | ^ error: derive(Diagnostic): `#[bar = ...]` is not a valid attribute - --> $DIR/subdiagnostic-derive.rs:189:5 + --> $DIR/subdiagnostic-derive.rs:179:5 | LL | #[bar = "..."] | ^ error: derive(Diagnostic): `#[bar = ...]` is not a valid attribute - --> $DIR/subdiagnostic-derive.rs:201:5 + --> $DIR/subdiagnostic-derive.rs:191:5 | LL | #[bar = 4] | ^ error: derive(Diagnostic): `#[bar(...)]` is not a valid attribute - --> $DIR/subdiagnostic-derive.rs:213:5 + --> $DIR/subdiagnostic-derive.rs:203:5 | LL | #[bar("...")] | ^ -error: derive(Diagnostic): only `no_span` is a valid nested attribute - --> $DIR/subdiagnostic-derive.rs:225:13 +error: derive(Diagnostic): no nested attribute expected here + --> $DIR/subdiagnostic-derive.rs:215:13 | LL | #[label(code = "...")] | ^^^^ error: derive(Diagnostic): diagnostic slug must be first argument of a `#[label(...)]` attribute - --> $DIR/subdiagnostic-derive.rs:225:5 + --> $DIR/subdiagnostic-derive.rs:215:5 | LL | #[label(code = "...")] | ^ error: derive(Diagnostic): the `#[primary_span]` attribute can only be applied to fields of type `Span` or `MultiSpan` - --> $DIR/subdiagnostic-derive.rs:254:5 + --> $DIR/subdiagnostic-derive.rs:244:5 | LL | #[primary_span] | ^ error: derive(Diagnostic): label without `#[primary_span]` field - --> $DIR/subdiagnostic-derive.rs:251:1 + --> $DIR/subdiagnostic-derive.rs:241:1 | LL | #[label(no_crate_example)] | ^ error: derive(Diagnostic): `#[applicability]` is only valid on suggestions - --> $DIR/subdiagnostic-derive.rs:264:5 + --> $DIR/subdiagnostic-derive.rs:254:5 | LL | #[applicability] | ^ error: derive(Diagnostic): `#[bar]` is not a valid attribute - --> $DIR/subdiagnostic-derive.rs:274:5 + --> $DIR/subdiagnostic-derive.rs:264:5 | LL | #[bar] | ^ @@ -145,111 +151,121 @@ LL | #[bar] = help: only `primary_span`, `applicability` and `skip_arg` are valid field attributes error: derive(Diagnostic): `#[bar = ...]` is not a valid attribute - --> $DIR/subdiagnostic-derive.rs:285:5 + --> $DIR/subdiagnostic-derive.rs:275:5 | LL | #[bar = "..."] | ^ error: derive(Diagnostic): `#[bar(...)]` is not a valid attribute - --> $DIR/subdiagnostic-derive.rs:296:5 + --> $DIR/subdiagnostic-derive.rs:286:5 | LL | #[bar("...")] | ^ | = help: only `primary_span`, `applicability` and `skip_arg` are valid field attributes +error: unexpected unsupported untagged union + --> $DIR/subdiagnostic-derive.rs:302:1 + | +LL | / union AC { +LL | | +LL | | span: u32, +LL | | b: u64, +LL | | } + | |_^ + error: derive(Diagnostic): a diagnostic slug must be the first argument to the attribute - --> $DIR/subdiagnostic-derive.rs:328:44 + --> $DIR/subdiagnostic-derive.rs:317:27 | LL | #[label(no_crate_example, no_crate::example)] - | ^ + | ^^^^^^^^ error: derive(Diagnostic): attribute specified multiple times - --> $DIR/subdiagnostic-derive.rs:341:5 + --> $DIR/subdiagnostic-derive.rs:330:5 | LL | #[primary_span] | ^ | note: previously specified here - --> $DIR/subdiagnostic-derive.rs:338:5 + --> $DIR/subdiagnostic-derive.rs:327:5 | LL | #[primary_span] | ^ error: derive(Diagnostic): subdiagnostic kind not specified - --> $DIR/subdiagnostic-derive.rs:347:8 + --> $DIR/subdiagnostic-derive.rs:336:8 | LL | struct AG { | ^^ error: derive(Diagnostic): attribute specified multiple times - --> $DIR/subdiagnostic-derive.rs:384:46 + --> $DIR/subdiagnostic-derive.rs:373:46 | LL | #[suggestion(no_crate_example, code = "...", code = "...")] | ^^^^ | note: previously specified here - --> $DIR/subdiagnostic-derive.rs:384:32 + --> $DIR/subdiagnostic-derive.rs:373:32 | LL | #[suggestion(no_crate_example, code = "...", code = "...")] | ^^^^ error: derive(Diagnostic): attribute specified multiple times - --> $DIR/subdiagnostic-derive.rs:402:5 + --> $DIR/subdiagnostic-derive.rs:391:5 | LL | #[applicability] | ^ | note: previously specified here - --> $DIR/subdiagnostic-derive.rs:399:5 + --> $DIR/subdiagnostic-derive.rs:388:5 | LL | #[applicability] | ^ error: derive(Diagnostic): the `#[applicability]` attribute can only be applied to fields of type `Applicability` - --> $DIR/subdiagnostic-derive.rs:412:5 + --> $DIR/subdiagnostic-derive.rs:401:5 | LL | #[applicability] | ^ error: derive(Diagnostic): suggestion without `code = "..."` - --> $DIR/subdiagnostic-derive.rs:425:1 + --> $DIR/subdiagnostic-derive.rs:414:1 | LL | #[suggestion(no_crate_example)] | ^ error: derive(Diagnostic): invalid applicability - --> $DIR/subdiagnostic-derive.rs:435:62 + --> $DIR/subdiagnostic-derive.rs:424:62 | LL | #[suggestion(no_crate_example, code = "...", applicability = "foo")] | ^^^^^ error: derive(Diagnostic): suggestion without `#[primary_span]` field - --> $DIR/subdiagnostic-derive.rs:453:1 + --> $DIR/subdiagnostic-derive.rs:442:1 | LL | #[suggestion(no_crate_example, code = "...")] | ^ error: derive(Diagnostic): unsupported type attribute for subdiagnostic enum - --> $DIR/subdiagnostic-derive.rs:467:1 + --> $DIR/subdiagnostic-derive.rs:456:1 | LL | #[label] | ^ error: derive(Diagnostic): `var` doesn't refer to a field on this type - --> $DIR/subdiagnostic-derive.rs:487:39 + --> $DIR/subdiagnostic-derive.rs:476:39 | LL | #[suggestion(no_crate_example, code = "{var}", applicability = "machine-applicable")] | ^^^^^^^ error: derive(Diagnostic): `var` doesn't refer to a field on this type - --> $DIR/subdiagnostic-derive.rs:506:43 + --> $DIR/subdiagnostic-derive.rs:495:43 | LL | #[suggestion(no_crate_example, code = "{var}", applicability = "machine-applicable")] | ^^^^^^^ error: derive(Diagnostic): `#[suggestion_part]` is not a valid attribute - --> $DIR/subdiagnostic-derive.rs:529:5 + --> $DIR/subdiagnostic-derive.rs:518:5 | LL | #[suggestion_part] | ^ @@ -257,7 +273,7 @@ LL | #[suggestion_part] = help: `#[suggestion_part(...)]` is only valid in multipart suggestions, use `#[primary_span]` instead error: derive(Diagnostic): `#[suggestion_part(...)]` is not a valid attribute - --> $DIR/subdiagnostic-derive.rs:532:5 + --> $DIR/subdiagnostic-derive.rs:521:5 | LL | #[suggestion_part(code = "...")] | ^ @@ -265,39 +281,39 @@ LL | #[suggestion_part(code = "...")] = help: `#[suggestion_part(...)]` is only valid in multipart suggestions error: derive(Diagnostic): suggestion without `#[primary_span]` field - --> $DIR/subdiagnostic-derive.rs:526:1 + --> $DIR/subdiagnostic-derive.rs:515:1 | LL | #[suggestion(no_crate_example, code = "...")] | ^ error: derive(Diagnostic): invalid nested attribute - --> $DIR/subdiagnostic-derive.rs:541:42 + --> $DIR/subdiagnostic-derive.rs:530:42 | LL | #[multipart_suggestion(no_crate_example, code = "...", applicability = "machine-applicable")] | ^^^^ | - = help: only `no_span`, `style` and `applicability` are valid nested attributes + = help: only `style` and `applicability` are valid nested attributes error: derive(Diagnostic): multipart suggestion without any `#[suggestion_part(...)]` fields - --> $DIR/subdiagnostic-derive.rs:541:1 + --> $DIR/subdiagnostic-derive.rs:530:1 | LL | #[multipart_suggestion(no_crate_example, code = "...", applicability = "machine-applicable")] | ^ error: derive(Diagnostic): `#[suggestion_part(...)]` attribute without `code = "..."` - --> $DIR/subdiagnostic-derive.rs:551:5 + --> $DIR/subdiagnostic-derive.rs:540:5 | LL | #[suggestion_part] | ^ error: derive(Diagnostic): `#[suggestion_part(...)]` attribute without `code = "..."` - --> $DIR/subdiagnostic-derive.rs:559:5 + --> $DIR/subdiagnostic-derive.rs:548:5 | LL | #[suggestion_part()] | ^ error: derive(Diagnostic): `#[primary_span]` is not a valid attribute - --> $DIR/subdiagnostic-derive.rs:568:5 + --> $DIR/subdiagnostic-derive.rs:557:5 | LL | #[primary_span] | ^ @@ -305,97 +321,127 @@ LL | #[primary_span] = help: multipart suggestions use one or more `#[suggestion_part]`s rather than one `#[primary_span]` error: derive(Diagnostic): multipart suggestion without any `#[suggestion_part(...)]` fields - --> $DIR/subdiagnostic-derive.rs:565:1 + --> $DIR/subdiagnostic-derive.rs:554:1 | LL | #[multipart_suggestion(no_crate_example)] | ^ error: derive(Diagnostic): `#[suggestion_part(...)]` attribute without `code = "..."` - --> $DIR/subdiagnostic-derive.rs:576:5 + --> $DIR/subdiagnostic-derive.rs:565:5 | LL | #[suggestion_part] | ^ error: derive(Diagnostic): `#[suggestion_part(...)]` attribute without `code = "..."` - --> $DIR/subdiagnostic-derive.rs:579:5 + --> $DIR/subdiagnostic-derive.rs:568:5 | LL | #[suggestion_part()] | ^ error: derive(Diagnostic): `code` is the only valid nested attribute - --> $DIR/subdiagnostic-derive.rs:582:23 + --> $DIR/subdiagnostic-derive.rs:571:23 | LL | #[suggestion_part(foo = "bar")] | ^^^ error: derive(Diagnostic): the `#[suggestion_part(...)]` attribute can only be applied to fields of type `Span` or `MultiSpan` - --> $DIR/subdiagnostic-derive.rs:587:5 + --> $DIR/subdiagnostic-derive.rs:575:5 | LL | #[suggestion_part(code = "...")] | ^ error: derive(Diagnostic): the `#[suggestion_part(...)]` attribute can only be applied to fields of type `Span` or `MultiSpan` - --> $DIR/subdiagnostic-derive.rs:590:5 + --> $DIR/subdiagnostic-derive.rs:578:5 | LL | #[suggestion_part()] | ^ +error: expected `,` + --> $DIR/subdiagnostic-derive.rs:571:27 + | +LL | #[suggestion_part(foo = "bar")] + | ^ + error: derive(Diagnostic): attribute specified multiple times - --> $DIR/subdiagnostic-derive.rs:598:37 + --> $DIR/subdiagnostic-derive.rs:586:37 | LL | #[suggestion_part(code = "...", code = ",,,")] | ^^^^ | note: previously specified here - --> $DIR/subdiagnostic-derive.rs:598:23 + --> $DIR/subdiagnostic-derive.rs:586:23 | LL | #[suggestion_part(code = "...", code = ",,,")] | ^^^^ error: derive(Diagnostic): `#[applicability]` has no effect if all `#[suggestion]`/`#[multipart_suggestion]` attributes have a static `applicability = "..."` - --> $DIR/subdiagnostic-derive.rs:627:5 + --> $DIR/subdiagnostic-derive.rs:615:5 | LL | #[applicability] | ^ error: derive(Diagnostic): expected exactly one string literal for `code = ...` - --> $DIR/subdiagnostic-derive.rs:675:34 + --> $DIR/subdiagnostic-derive.rs:663:28 | LL | #[suggestion_part(code("foo"))] - | ^ + | ^^^^^ + +error: unexpected token, expected `)` + --> $DIR/subdiagnostic-derive.rs:663:28 + | +LL | #[suggestion_part(code("foo"))] + | ^^^^^ error: derive(Diagnostic): expected exactly one string literal for `code = ...` - --> $DIR/subdiagnostic-derive.rs:686:41 + --> $DIR/subdiagnostic-derive.rs:673:28 | LL | #[suggestion_part(code("foo", "bar"))] - | ^ + | ^^^^^ + +error: unexpected token, expected `)` + --> $DIR/subdiagnostic-derive.rs:673:28 + | +LL | #[suggestion_part(code("foo", "bar"))] + | ^^^^^ error: derive(Diagnostic): expected exactly one string literal for `code = ...` - --> $DIR/subdiagnostic-derive.rs:697:30 + --> $DIR/subdiagnostic-derive.rs:683:28 | LL | #[suggestion_part(code(3))] - | ^ + | ^ + +error: unexpected token, expected `)` + --> $DIR/subdiagnostic-derive.rs:683:28 + | +LL | #[suggestion_part(code(3))] + | ^ error: derive(Diagnostic): expected exactly one string literal for `code = ...` - --> $DIR/subdiagnostic-derive.rs:708:29 + --> $DIR/subdiagnostic-derive.rs:693:28 | LL | #[suggestion_part(code())] - | ^ + | ^ + +error: expected string literal + --> $DIR/subdiagnostic-derive.rs:702:30 + | +LL | #[suggestion_part(code = 3)] + | ^ error: derive(Diagnostic): attribute specified multiple times - --> $DIR/subdiagnostic-derive.rs:763:1 + --> $DIR/subdiagnostic-derive.rs:744:1 | LL | #[suggestion(no_crate_example, code = "", style = "hidden", style = "normal")] | ^ | note: previously specified here - --> $DIR/subdiagnostic-derive.rs:763:1 + --> $DIR/subdiagnostic-derive.rs:744:1 | LL | #[suggestion(no_crate_example, code = "", style = "hidden", style = "normal")] | ^ error: derive(Diagnostic): `#[suggestion_hidden(...)]` is not a valid attribute - --> $DIR/subdiagnostic-derive.rs:772:1 + --> $DIR/subdiagnostic-derive.rs:753:1 | LL | #[suggestion_hidden(no_crate_example, code = "")] | ^ @@ -403,7 +449,7 @@ LL | #[suggestion_hidden(no_crate_example, code = "")] = help: Use `#[suggestion(..., style = "hidden")]` instead error: derive(Diagnostic): `#[suggestion_hidden(...)]` is not a valid attribute - --> $DIR/subdiagnostic-derive.rs:780:1 + --> $DIR/subdiagnostic-derive.rs:761:1 | LL | #[suggestion_hidden(no_crate_example, code = "", style = "normal")] | ^ @@ -411,33 +457,33 @@ LL | #[suggestion_hidden(no_crate_example, code = "", style = "normal")] = help: Use `#[suggestion(..., style = "hidden")]` instead error: derive(Diagnostic): invalid suggestion style - --> $DIR/subdiagnostic-derive.rs:788:51 + --> $DIR/subdiagnostic-derive.rs:769:51 | LL | #[suggestion(no_crate_example, code = "", style = "foo")] | ^^^^^ | = help: valid styles are `normal`, `short`, `hidden`, `verbose` and `tool-only` -error: derive(Diagnostic): expected `= "xxx"` - --> $DIR/subdiagnostic-derive.rs:796:49 +error: expected string literal + --> $DIR/subdiagnostic-derive.rs:777:51 | LL | #[suggestion(no_crate_example, code = "", style = 42)] - | ^ + | ^^ error: derive(Diagnostic): a diagnostic slug must be the first argument to the attribute - --> $DIR/subdiagnostic-derive.rs:804:48 + --> $DIR/subdiagnostic-derive.rs:785:43 | LL | #[suggestion(no_crate_example, code = "", style)] - | ^ + | ^^^^^ -error: derive(Diagnostic): expected `= "xxx"` - --> $DIR/subdiagnostic-derive.rs:812:48 +error: expected `=` + --> $DIR/subdiagnostic-derive.rs:793:48 | LL | #[suggestion(no_crate_example, code = "", style("foo"))] | ^ error: derive(Diagnostic): `#[primary_span]` is not a valid attribute - --> $DIR/subdiagnostic-derive.rs:825:5 + --> $DIR/subdiagnostic-derive.rs:804:5 | LL | #[primary_span] | ^ @@ -446,128 +492,64 @@ LL | #[primary_span] = help: to create a suggestion with multiple spans, use `#[multipart_suggestion]` instead error: derive(Diagnostic): suggestion without `#[primary_span]` field - --> $DIR/subdiagnostic-derive.rs:822:1 + --> $DIR/subdiagnostic-derive.rs:801:1 | LL | #[suggestion(no_crate_example, code = "")] | ^ -error[E0433]: failed to resolve: you might be missing crate `core` - --> $DIR/subdiagnostic-derive.rs:96:9 - | -LL | #[label("...")] - | ^^^^^ you might be missing crate `core` - -error[E0433]: failed to resolve: you might be missing crate `core` - --> $DIR/subdiagnostic-derive.rs:312:1 - | -LL | union AC { - | ^^^^^ you might be missing crate `core` - -error[E0433]: failed to resolve: you might be missing crate `core` - --> $DIR/subdiagnostic-derive.rs:582:27 - | -LL | #[suggestion_part(foo = "bar")] - | ^ you might be missing crate `core` - -error[E0433]: failed to resolve: you might be missing crate `core` - --> $DIR/subdiagnostic-derive.rs:675:28 - | -LL | #[suggestion_part(code("foo"))] - | ^^^^^ you might be missing crate `core` - -error[E0433]: failed to resolve: you might be missing crate `core` - --> $DIR/subdiagnostic-derive.rs:686:28 - | -LL | #[suggestion_part(code("foo", "bar"))] - | ^^^^^ you might be missing crate `core` - -error[E0433]: failed to resolve: you might be missing crate `core` - --> $DIR/subdiagnostic-derive.rs:697:28 - | -LL | #[suggestion_part(code(3))] - | ^ you might be missing crate `core` - -error[E0433]: failed to resolve: you might be missing crate `core` - --> $DIR/subdiagnostic-derive.rs:720:30 - | -LL | #[suggestion_part(code = 3)] - | ^ you might be missing crate `core` - -error[E0433]: failed to resolve: you might be missing crate `core` - --> $DIR/subdiagnostic-derive.rs:812:48 - | -LL | #[suggestion(no_crate_example, code = "", style("foo"))] - | ^ you might be missing crate `core` - error: cannot find attribute `foo` in this scope - --> $DIR/subdiagnostic-derive.rs:67:3 + --> $DIR/subdiagnostic-derive.rs:68:3 | LL | #[foo] | ^^^ error: cannot find attribute `foo` in this scope - --> $DIR/subdiagnostic-derive.rs:163:3 + --> $DIR/subdiagnostic-derive.rs:153:3 | LL | #[foo] | ^^^ error: cannot find attribute `bar` in this scope - --> $DIR/subdiagnostic-derive.rs:177:7 + --> $DIR/subdiagnostic-derive.rs:167:7 | LL | #[bar] | ^^^ error: cannot find attribute `bar` in this scope - --> $DIR/subdiagnostic-derive.rs:189:7 + --> $DIR/subdiagnostic-derive.rs:179:7 | LL | #[bar = "..."] | ^^^ error: cannot find attribute `bar` in this scope - --> $DIR/subdiagnostic-derive.rs:201:7 + --> $DIR/subdiagnostic-derive.rs:191:7 | LL | #[bar = 4] | ^^^ error: cannot find attribute `bar` in this scope - --> $DIR/subdiagnostic-derive.rs:213:7 + --> $DIR/subdiagnostic-derive.rs:203:7 | LL | #[bar("...")] | ^^^ error: cannot find attribute `bar` in this scope - --> $DIR/subdiagnostic-derive.rs:274:7 + --> $DIR/subdiagnostic-derive.rs:264:7 | LL | #[bar] | ^^^ error: cannot find attribute `bar` in this scope - --> $DIR/subdiagnostic-derive.rs:285:7 + --> $DIR/subdiagnostic-derive.rs:275:7 | LL | #[bar = "..."] | ^^^ error: cannot find attribute `bar` in this scope - --> $DIR/subdiagnostic-derive.rs:296:7 + --> $DIR/subdiagnostic-derive.rs:286:7 | LL | #[bar("...")] | ^^^ -error[E0425]: cannot find value `slug` in module `crate::fluent_generated` - --> $DIR/subdiagnostic-derive.rs:126:9 - | -LL | #[label(slug)] - | ^^^^ not found in `crate::fluent_generated` +error: aborting due to 83 previous errors -error[E0425]: cannot find value `__code_29` in this scope - --> $DIR/subdiagnostic-derive.rs:714:10 - | -LL | #[derive(Subdiagnostic)] - | ^^^^^^^^^^^^^ not found in this scope - | - = note: this error originates in the derive macro `Subdiagnostic` (in Nightly builds, run with -Z macro-backtrace for more info) - -error: aborting due to 86 previous errors - -Some errors have detailed explanations: E0425, E0433. -For more information about an error, try `rustc --explain E0425`. diff --git a/tests/ui/README.md b/tests/ui/README.md index 4c91f313a735..237cfb9c4f07 100644 --- a/tests/ui/README.md +++ b/tests/ui/README.md @@ -10,17 +10,23 @@ These tests deal with *Application Binary Interfaces* (ABI), mostly relating to Tests for unsupported ABIs can be made cross-platform by using the `extern "rust-invalid"` ABI, which is considered unsupported on every platform. +## `tests/ui/alloc-error` + +These tests exercise alloc error handling. + +See . + ## `tests/ui/allocator` These tests exercise `#![feature(allocator_api)]` and the `#[global_allocator]` attribute. See [Allocator traits and `std::heap` #32838](https://github.com/rust-lang/rust/issues/32838). -## `tests/ui/alloc-error` +## `tests/ui/annotate-moves` -These tests exercise alloc error handling. +These tests exercise the `annotate-moves` feature. -See . +See [`annotate-moves` | The Unstable book](https://doc.rust-lang.org/nightly/unstable-book/compiler-flags/annotate-moves.html) ## `tests/ui/annotate-snippet` @@ -34,20 +40,26 @@ These tests exercise the [`annotate-snippets`]-based emitter implementation. These tests deal with anonymous parameters (no name, only type), a deprecated feature that becomes a hard error in Edition 2018. +## `tests/ui/any` + +These tests exercise the `try_as_dyn` feature. + +See [`core::any::try_as_dyn`](https://doc.rust-lang.org/nightly/core/any/fn.try_as_dyn.html) + ## `tests/ui/argfile`: External files providing command line arguments These tests exercise rustc reading command line arguments from an externally provided argfile (`@argsfile`). See [Implement `@argsfile` to read arguments from command line #63576](https://github.com/rust-lang/rust/issues/63576). -## `tests/ui/array-slice-vec`: Arrays, slices and vectors - -Exercises various aspects surrounding basic collection types `[]`, `&[]` and `Vec`. E.g. type-checking, out-of-bounds indices, attempted instructions which are allowed in other programming languages, and more. - ## `tests/ui/argument-suggestions`: Argument suggestions Calling a function with the wrong number of arguments causes a compilation failure, but the compiler is able to, in some cases, provide suggestions on how to fix the error, such as which arguments to add or delete. These tests exercise the quality of such diagnostics. +## `tests/ui/array-slice-vec`: Arrays, slices and vectors + +Exercises various aspects surrounding basic collection types `[]`, `&[]` and `Vec`. E.g. type-checking, out-of-bounds indices, attempted instructions which are allowed in other programming languages, and more. + ## `tests/ui/asm`: `asm!` macro These tests exercise the `asm!` macro, which is used for adding inline assembly. @@ -172,6 +184,10 @@ See [RFC 3729: Hierarchy of Sized traits](https://github.com/rust-lang/rfcs/pull Defining custom auto traits with the `auto` keyword belongs to `tests/ui/auto-traits/` instead. +## `tests/ui/c-variadic`: C Variadic Function + +Tests for FFI with C varargs (`va_list`). + ## `tests/ui/cast/`: Type Casting Tests for type casting using the `as` operator. Includes tests for valid/invalid casts between primitive types, trait objects, and custom types. For example, check that trying to cast `i32` into `bool` results in a helpful error message. @@ -190,16 +206,16 @@ Tests for the `--check-cfg` compiler mechanism for checking cfg configurations, See [Checking conditional configurations | The rustc book](https://doc.rust-lang.org/rustc/check-cfg.html). -## `tests/ui/closure_context/`: Closure type inference in context - -Tests for closure type inference with respect to surrounding scopes, mostly quality of diagnostics. - ## `tests/ui/closure-expected-type/`: Closure type inference Tests targeted at how we deduce the types of closure arguments. This process is a result of some heuristics which take into account the *expected type* we have alongside the *actual types* that we get from inputs. **FIXME**: Appears to have significant overlap with `tests/ui/closure_context` and `tests/ui/functions-closures/closure-expected-type`. Needs further investigation. +## `tests/ui/closure_context`: Closure type inference in context + +Tests for closure type inference with respect to surrounding scopes, mostly quality of diagnostics. + ## `tests/ui/closures/`: General Closure Tests Any closure-focused tests that does not fit in the other more specific closure subdirectories belong here. E.g. syntax, `move`, lifetimes. @@ -244,6 +260,14 @@ See: This directory only contains one highly specific test. Other coinduction tests can be found down the deeply located `tests/ui/traits/next-solver/cycles/coinduction/` subdirectory. +## `tests/ui/collections` + +These tests exercise the `collections` library. + +See [`std::collections`](https://doc.rust-lang.org/std/collections/index.html) + +**FIXME**: consider merge with `tests/ui/btreemap` and `tests/ui/hashmap` + ## `tests/ui/command/`: `std::process::Command` This directory is actually for the standard library [`std::process::Command`](https://doc.rust-lang.org/std/process/struct.Command.html) type, where some tests are too difficult or inconvenient to write as unit tests or integration tests within the standard library itself. @@ -285,10 +309,6 @@ See: - [Tracking Issue for complex generic constants: `feature(generic_const_exprs)` #76560](https://github.com/rust-lang/rust/issues/76560) - [Const generics | Reference](https://doc.rust-lang.org/reference/items/generics.html#const-generics) -## `tests/ui/const_prop/`: Constant Propagation - -Tests exercising `ConstProp` mir-opt pass (mostly regression tests). See . - ## `tests/ui/const-ptr/`: Constant Pointers Tests exercise const raw pointers. E.g. pointer arithmetic, casting and dereferencing, always with a `const`. @@ -299,6 +319,10 @@ See: - [`std::ptr`](https://doc.rust-lang.org/std/ptr/index.html) - [Pointer types | Reference](https://doc.rust-lang.org/reference/types/pointer.html) +## `tests/ui/const_prop`: Constant Propagation + +Tests exercising `ConstProp` mir-opt pass (mostly regression tests). See . + ## `tests/ui/consts/`: General Constant Evaluation Anything to do with constants, which does not fit in the previous two `const` categories, goes here. This does not always imply use of the `const` keyword - other values considered constant, such as defining an enum variant as `enum Foo { Variant = 5 }` also counts. @@ -340,10 +364,6 @@ Tests for `#[bench]`, `#[test_case]` attributes and the `custom_test_frameworks` See [Tracking issue for eRFC 2318, Custom test frameworks #50297](https://github.com/rust-lang/rust/issues/50297). -## `tests/ui/c-variadic/`: C Variadic Function - -Tests for FFI with C varargs (`va_list`). - ## `tests/ui/cycle-trait/`: Trait Cycle Detection Tests for detection and handling of cyclic trait dependencies. @@ -380,6 +400,18 @@ These tests use the unstable command line option `query-dep-graph` to examine th Tests for `#[deprecated]` attribute and `deprecated_in_future` internal lint. +## `tests/ui/deref` + +Tests for `Deref` and `DerefMut` traits. + +## `tests/ui/deref-patterns`: `#![feature(deref_patterns)]` and `#![feature(string_deref_patterns)]` + +Tests for `#![feature(deref_patterns)]` and `#![feature(string_deref_patterns)]`. See [Deref patterns | The Unstable book](https://doc.rust-lang.org/nightly/unstable-book/language-features/deref-patterns.html). + +**FIXME**: May have some overlap with `tests/ui/pattern/deref-patterns`. + +See [`std::ops::Deref`](https://doc.rust-lang.org/std/ops/trait.Deref.html) and [`std::ops::DerefMut`](https://doc.rust-lang.org/std/ops/trait.DerefMut.html) + ## `tests/ui/derived-errors/`: Derived Error Messages Tests for quality of diagnostics involving suppression of cascading errors in some cases to avoid overwhelming the user. @@ -406,6 +438,10 @@ These tests revolve around command-line flags which change the way error/warning **FIXME**: Check redundancy with `annotate-snippet`, which is another emitter. +## `tests/ui/diagnostic-width`: `--diagnostic-width` + +Everything to do with `--diagnostic-width`. + ## `tests/ui/diagnostic_namespace/` Exercises `#[diagnostic::*]` namespaced attributes. See [RFC 3368 Diagnostic attribute namespace](https://github.com/rust-lang/rfcs/blob/master/text/3368-diagnostic-attribute-namespace.md). @@ -414,10 +450,6 @@ Exercises `#[diagnostic::*]` namespaced attributes. See [RFC 3368 Diagnostic att This directory contains tests and infrastructure related to the diagnostics system, including support for translatable diagnostics -## `tests/ui/diagnostic-width/`: `--diagnostic-width` - -Everything to do with `--diagnostic-width`. - ## `tests/ui/did_you_mean/` Tests for miscellaneous suggestions. @@ -430,6 +462,10 @@ Exercises diagnostics for when a code block attempts to gain ownership of a non- Exercises diagnostics for disallowed struct destructuring. +## `tests/ui/dist` + +Tests that require distribution artifacts. + ## `tests/ui/dollar-crate/`: `$crate` used with the `use` keyword There are a few rules - which are checked in this directory - to follow when using `$crate` - it must be used in the start of a `use` line and is a reserved identifier. @@ -461,10 +497,6 @@ Tests for dynamically-sized types (DSTs). See [Dynamically Sized Types | Referen Tests about duplicated symbol names and associated errors, such as using the `#[export_name]` attribute to rename a function with the same name as another function. -## `tests/ui/dynamically-sized-types/`: Dynamically Sized Types - -**FIXME**: should be coalesced with `tests/ui/dst`. - ## `tests/ui/dyn-compatibility/`: Dyn-compatibility Tests for dyn-compatibility of traits. @@ -486,12 +518,20 @@ The `dyn` keyword is used to highlight that calls to methods on the associated T See [`dyn` keyword](https://doc.rust-lang.org/std/keyword.dyn.html). +## `tests/ui/dynamically-sized-types`: Dynamically Sized Types + +**FIXME**: should be coalesced with `tests/ui/dst`. + ## `tests/ui/editions/`: Rust edition-specific peculiarities These tests run in specific Rust editions, such as Rust 2015 or Rust 2018, and check errors and functionality related to specific now-deprecated idioms and features. **FIXME**: Maybe regroup `rust-2018`, `rust-2021` and `rust-2024` under this umbrella? +## `tests/ui/eii`: Externally Implementable Items + +Exercises `eii` keyword. + ## `tests/ui/empty/`: Various tests related to the concept of "empty" **FIXME**: These tests need better homes, this is not very informative. @@ -571,6 +611,10 @@ See: - [`ffi_const` | The Unstable book](https://doc.rust-lang.org/unstable-book/language-features/ffi-const.html) - [`ffi_pure` | The Unstable book](https://doc.rust-lang.org/beta/unstable-book/language-features/ffi-pure.html) +## `tests/ui/float` + +See: [Tracking Issue for `f16` and `f128` float types #116909](https://github.com/rust-lang/rust/issues/116909) + ## `tests/ui/fmt/` Exercises the `format!` macro. @@ -579,6 +623,16 @@ Exercises the `format!` macro. A broad category of tests on functions. +## `tests/ui/fn_traits` + +Tests for `#![feature(fn_traits)]`. See [`fn_traits` | The Unstable book](https://doc.rust-lang.org/nightly/unstable-book/library-features/fn-traits.html). + +## `tests/ui/for-loop-while` + +Anything to do with loops and `for`, `loop` and `while` keywords to express them. + +**FIXME**: After `ui/for` is merged into this, also carry over its SUMMARY text. + ## `tests/ui/force-inlining/`: `#[rustc_force_inline]` Tests for `#[rustc_force_inline]`, which will force a function to always be labelled as inline by the compiler (it will be inserted at the point of its call instead of being used as a normal function call.) If the compiler is unable to inline the function, an error will be reported. See . @@ -589,12 +643,6 @@ Tests for `extern "C"` and `extern "Rust`. **FIXME**: Check for potential overlap/merge with `ui/c-variadic` and/or `ui/extern`. -## `tests/ui/for-loop-while/` - -Anything to do with loops and `for`, `loop` and `while` keywords to express them. - -**FIXME**: After `ui/for` is merged into this, also carry over its SUMMARY text. - ## `tests/ui/frontmatter/` Tests for `#![feature(frontmatter)]`. See [Tracking Issue for `frontmatter` #136889](https://github.com/rust-lang/rust/issues/136889). @@ -603,12 +651,6 @@ Tests for `#![feature(frontmatter)]`. See [Tracking Issue for `frontmatter` #136 Tests for diagnostics when there may be identically named types that need further qualifications to disambiguate. -## `tests/ui/functional-struct-update/` - -Functional Struct Update is the name for the idiom by which one can write `..` at the end of a struct literal expression to fill in all remaining fields of the struct literal by using `` as the source for them. - -See [RFC 0736 Privacy-respecting Functional Struct Update](https://github.com/rust-lang/rfcs/blob/master/text/0736-privacy-respecting-fru.md). - ## `tests/ui/function-pointer/` Tests on function pointers, such as testing their compatibility with higher-ranked trait bounds. @@ -618,6 +660,12 @@ See: - [Function pointer types | Reference](https://doc.rust-lang.org/reference/types/function-pointer.html) - [Higher-ranked trait bounds | Nomicon](https://doc.rust-lang.org/nomicon/hrtb.html) +## `tests/ui/functional-struct-update/` + +Functional Struct Update is the name for the idiom by which one can write `..` at the end of a struct literal expression to fill in all remaining fields of the struct literal by using `` as the source for them. + +See [RFC 0736 Privacy-respecting Functional Struct Update](https://github.com/rust-lang/rfcs/blob/master/text/0736-privacy-respecting-fru.md). + ## `tests/ui/functions-closures/` Tests on closures. See [Closure expressions | Reference](https://doc.rust-lang.org/reference/expressions/closure-expr.html). @@ -653,6 +701,10 @@ See: - [Higher-ranked trait bounds | rustc-dev-guide](https://rustc-dev-guide.rust-lang.org/traits/hrtb.html) - [Higher-ranked trait bounds | Nomicon](https://doc.rust-lang.org/nomicon/hrtb.html) +## `tests/ui/higher-ranked-trait-bounds` + +**FIXME**: move to `tests/ui/higher-ranked/trait-bounds` + ## `tests/ui/hygiene/` This seems to have been originally intended for "hygienic macros" - macros which work in all contexts, independent of what surrounds them. However, this category has grown into a mish-mash of many tests that may belong in the other directories. @@ -669,14 +721,14 @@ This test category revolves around trait objects with `Sized` having illegal ope Tests on lifetime elision in impl function signatures. See [Lifetime elision | Nomicon](https://doc.rust-lang.org/nomicon/lifetime-elision.html). -## `tests/ui/implied-bounds/` - -See [Implied bounds | Reference](https://doc.rust-lang.org/reference/trait-bounds.html#implied-bounds). - ## `tests/ui/impl-trait/` Tests for trait impls. +## `tests/ui/implied-bounds/` + +See [Implied bounds | Reference](https://doc.rust-lang.org/reference/trait-bounds.html#implied-bounds). + ## `tests/ui/imports/` Tests for module system and imports. @@ -802,6 +854,12 @@ Broad directory on lifetimes, including proper specifiers, lifetimes not living These tests exercises numerical limits, such as `[[u8; 1518599999]; 1518600000]`. +## `tests/ui/link-native-libs/` + +Tests for `#[link(name = "", kind = "")]` and `-l` command line flag. + +See [Tracking Issue for linking modifiers for native libraries #81490](https://github.com/rust-lang/rust/issues/81490). + ## `tests/ui/linkage-attr/` Tests for the linkage attribute `#[linkage]` of `#![feature(linkage)]`. @@ -814,12 +872,6 @@ Tests on code which fails during the linking stage, or which contain arguments a See [Linkage | Reference](https://doc.rust-lang.org/reference/linkage.html). -## `tests/ui/link-native-libs/` - -Tests for `#[link(name = "", kind = "")]` and `-l` command line flag. - -See [Tracking Issue for linking modifiers for native libraries #81490](https://github.com/rust-lang/rust/issues/81490). - ## `tests/ui/lint/` Tests for the lint infrastructure, lint levels, lint reasons, etc. @@ -835,6 +887,10 @@ Tests exercising analysis for unused variables, unreachable statements, function **FIXME**: This seems unrelated to "liveness" as defined in the rustc compiler guide. Is this misleadingly named? https://rustc-dev-guide.rust-lang.org/borrow_check/region_inference/lifetime_parameters.html#liveness-and-universal-regions +## `tests/ui/loop-match` + +Tests for `loop` with `match` expressions. + ## `tests/ui/loops/` Tests on the `loop` construct. @@ -941,6 +997,10 @@ See [RFC 3550 New Range](https://github.com/rust-lang/rfcs/blob/master/text/3550 Tests for Non-lexical lifetimes. See [RFC 2094 NLL](https://rust-lang.github.io/rfcs/2094-nll.html). +## `tests/ui/no_std/` + +Tests for where the standard library is disabled through `#![no_std]`. + ## `tests/ui/non_modrs_mods/` Despite the size of the directory, this is a single test, spawning a sprawling `mod` dependency tree and checking its successful build. @@ -953,10 +1013,6 @@ A very similar principle as `non_modrs_mods`, but with an added inline `mod` sta **FIXME**: Consider merge with `tests/ui/modules/`, keeping the directory structure. -## `tests/ui/no_std/` - -Tests for where the standard library is disabled through `#![no_std]`. - ## `tests/ui/not-panic/` Tests checking various types, such as `&RefCell`, and whether they are not `UnwindSafe` as expected. @@ -981,6 +1037,15 @@ Contains a single test. Check that we reject the ancient Rust syntax `x <- y` an **FIXME**: Definitely should be rehomed, maybe to `tests/ui/deprecation/`. +## `tests/ui/offload` + +Exercises the offload feature. + +See: + +- [`std::offload` | rustc-dev-guide](https://rustc-dev-guide.rust-lang.org/offload/internals.html) +- [Tracking Issue for GPU-offload #131513](https://github.com/rust-lang/rust/issues/131513) + ## `tests/ui/offset-of/` Exercises the [`std::mem::offset_of` macro](https://doc.rust-lang.org/beta/std/mem/macro.offset_of.html). @@ -1039,6 +1104,16 @@ Broad category of tests surrounding patterns. See [Patterns | Reference](https:/ **FIXME**: Some overlap with `tests/ui/match/`. +## `tests/ui/pin` + +**FIXME**: Consider merging with `tests/ui/pin-macro`. + +## `tests/ui/pin-ergonomics` + +Exercises the `#![feature(pin_ergonomics)]` feature. + +See [Tracking issue for pin ergonomics #130494](https://github.com/rust-lang/rust/issues/130494) + ## `tests/ui/pin-macro/` See [`std::pin`](https://doc.rust-lang.org/std/pin/). @@ -1059,6 +1134,10 @@ Exercises the `-Z print-type-sizes` flag. Exercises on name privacy. E.g. the meaning of `pub`, `pub(crate)`, etc. +## `tests/ui/proc-macro/` + +Broad category of tests on proc-macros. See [Procedural Macros | Reference](https://doc.rust-lang.org/reference/procedural-macros.html). + ## `tests/ui/process/` Some standard library process tests which are hard to write within standard library crate tests. @@ -1067,10 +1146,6 @@ Some standard library process tests which are hard to write within standard libr Some standard library process termination tests which are hard to write within standard library crate tests. -## `tests/ui/proc-macro/` - -Broad category of tests on proc-macros. See [Procedural Macros | Reference](https://doc.rust-lang.org/reference/procedural-macros.html). - ## `tests/ui/ptr_ops/`: Using operations on a pointer Contains only 2 tests, related to a single issue, which was about an error caused by using addition on a pointer to `i8`. @@ -1103,6 +1178,12 @@ Reachability tests, primarily unreachable code and coercions into the never type **FIXME**: Check for overlap with `ui/liveness`. +## `tests/ui/reborrow` + +Exercises the `#![feature(reborrow)]` feature. + +See [Tracking Issue for Reborrow trait lang experiment #145612](https://github.com/rust-lang/rust/issues/145612) + ## `tests/ui/recursion/` Broad category of tests exercising recursions (compile test and run time), in functions, macros, `type` definitions, and more. @@ -1115,6 +1196,12 @@ Sets a recursion limit on recursive code. **FIXME**: Should be merged with `tests/ui/recursion/`. +## `tests/ui/reflection/` + +Exercises the `#![feature(type_info)]` feature. + +See [Tracking Issue for type_info #146922](https://github.com/rust-lang/rust/issues/146922) + ## `tests/ui/regions/` **FIXME**: Maybe merge with `ui/lifetimes`. @@ -1157,22 +1244,44 @@ Exercises `.rmeta` crate metadata and the `--emit=metadata` cli flag. Tests for runtime environment on which Rust programs are executed. E.g. Unix `SIGPIPE`. -## `tests/ui/rust-{2018,2021,2024}/` +## `tests/ui/rust-2018` -Tests that exercise behaviors and features that are specific to editions. +Tests that exercise behaviors and features specific to the Rust 2018 edition. + +## `tests/ui/rust-2021` + +Tests that exercise behaviors and features specific to the Rust 2021 edition. + +## `tests/ui/rust-2024` + +Tests that exercise behaviors and features specific to the Rust 2024 edition. ## `tests/ui/rustc-env` Tests on environmental variables that affect `rustc`. +## `tests/ui/rustc_public-ir-print` + +Some tests for pretty printing of rustc_public's IR. + ## `tests/ui/rustdoc` Hybrid tests that exercises `rustdoc`, and also some joint `rustdoc`/`rustc` interactions. +## `tests/ui/sanitize-attr` + +Tests for the `#![feature(sanitize)]` attribute. + +See [Sanitize | The Unstable Book](https://doc.rust-lang.org/unstable-book/language-features/sanitize.html). + ## `tests/ui/sanitizer/` Exercises sanitizer support. See [Sanitizer | The rustc book](https://doc.rust-lang.org/unstable-book/compiler-flags/sanitizer.html). +## `tests/ui/scalable-vectors` + +See [Tracking Issue for Scalable Vectors #145052](https://github.com/rust-lang/rust/issues/145052) + ## `tests/ui/self/`: `self` keyword Tests with erroneous ways of using `self`, such as using `this.x` syntax as seen in other languages, having it not be the first argument, or using it in a non-associated function (no `impl` or `trait`). It also contains correct uses of `self` which have previously been observed to cause ICEs. @@ -1211,6 +1320,12 @@ This is a test directory for the specific error case where a lifetime never gets While many tests here involve the `Sized` trait directly, some instead test, for example the slight variations between returning a zero-sized `Vec` and a `Vec` with one item, where one has no known type and the other does. +## `tests/ui/sized-hierarchy` + +Tests for `#![feature(sized_hierarchy)]` attribute. + +See [Tracking Issue for Sized Hierarchy #144404](https://github.com/rust-lang/rust/issues/144404) + ## `tests/ui/span/` An assorted collection of tests that involves specific diagnostic spans. @@ -1225,9 +1340,9 @@ See [Tracking issue for specialization (RFC 1210) #31844](https://github.com/rus Stability attributes used internally by the standard library: `#[stable()]` and `#[unstable()]`. -## `tests/ui/rustc_public-ir-print/` +## `tests/ui/stack-probes` -Some tests for pretty printing of rustc_public's IR. +**FIXME**: Contains a single test, should likely be rehomed to `tests/ui/abi`. ## `tests/ui/stack-protector/`: `-Z stack-protector` command line flag @@ -1359,6 +1474,10 @@ Tests surrounding [`std::mem::transmute`](https://doc.rust-lang.org/std/mem/fn.t Exercises compiler development support flag `-Z treat-err-as-bug`. +## `tests/ui/trimmed-paths/` + +Tests for the `#[doc(hidden)]` items. + ## `tests/ui/trivial-bounds/` `#![feature(trivial_bounds)]`. See [RFC 2056 Allow trivial where clause constraints](https://github.com/rust-lang/rfcs/blob/master/text/2056-allow-trivial-where-clause-constraints.md). @@ -1393,17 +1512,13 @@ Tests for `type` aliases in the context of `enum` variants, such as that applied `#![feature(type_alias_impl_trait)]`. See [Type Alias Impl Trait | The Unstable book](https://doc.rust-lang.org/nightly/unstable-book/language-features/type-alias-impl-trait.html). -## `tests/ui/typeck/` - -General collection of type checking related tests. - ## `tests/ui/type-inference/` General collection of type inference related tests. -## `tests/ui/typeof/` +## `tests/ui/typeck` -`typeof` keyword, reserved but unimplemented. +General collection of type checking related tests. ## `tests/ui/ufcs/` @@ -1483,7 +1598,11 @@ See: **FIXME**: Seems to also contain more generic tests that fit in `tests/ui/unsized/`. -## `tests/ui/unused-crate-deps/` +## `tests/ui/unstable-feature-bound` + +Tests for gating and diagnostics when unstable features are used. + +## `tests/ui/unused-crate-deps` Exercises the `unused_crate_dependencies` lint. diff --git a/tests/ui/async-await/async-closures/move-from-async-fn-bound.rs b/tests/ui/async-await/async-closures/move-from-async-fn-bound.rs new file mode 100644 index 000000000000..fbd8aac2515b --- /dev/null +++ b/tests/ui/async-await/async-closures/move-from-async-fn-bound.rs @@ -0,0 +1,13 @@ +//@ edition:2021 +// Test that a by-ref `AsyncFn` closure gets an error when it tries to +// consume a value, with a helpful diagnostic pointing to the bound. + +fn call(_: F) where F: AsyncFn() {} + +fn main() { + let y = vec![format!("World")]; + call(async || { + //~^ ERROR cannot move out of `y`, a captured variable in an `AsyncFn` closure + y.into_iter(); + }); +} diff --git a/tests/ui/async-await/async-closures/move-from-async-fn-bound.stderr b/tests/ui/async-await/async-closures/move-from-async-fn-bound.stderr new file mode 100644 index 000000000000..1a881db2a37d --- /dev/null +++ b/tests/ui/async-await/async-closures/move-from-async-fn-bound.stderr @@ -0,0 +1,30 @@ +error[E0507]: cannot move out of `y`, a captured variable in an `AsyncFn` closure + --> $DIR/move-from-async-fn-bound.rs:9:10 + | +LL | let y = vec![format!("World")]; + | - captured outer variable +LL | call(async || { + | ^^^^^^^^ + | | + | captured by this `AsyncFn` closure + | `y` is moved here +LL | +LL | y.into_iter(); + | - + | | + | variable moved due to use in coroutine + | move occurs because `y` has type `Vec`, which does not implement the `Copy` trait + | +help: `AsyncFn` and `AsyncFnMut` closures require captured values to be able to be consumed multiple times, but `AsyncFnOnce` closures may consume them only once + --> $DIR/move-from-async-fn-bound.rs:5:27 + | +LL | fn call(_: F) where F: AsyncFn() {} + | ^^^^^^^^^ +help: consider cloning the value if the performance cost is acceptable + | +LL | y.clone().into_iter(); + | ++++++++ + +error: aborting due to 1 previous error + +For more information about this error, try `rustc --explain E0507`. diff --git a/tests/ui/attributes/attr-on-mac-call.stderr b/tests/ui/attributes/attr-on-mac-call.stderr index 1aeec463c71c..3bb50f2d6f65 100644 --- a/tests/ui/attributes/attr-on-mac-call.stderr +++ b/tests/ui/attributes/attr-on-mac-call.stderr @@ -55,7 +55,7 @@ LL | #[deprecated] | ^^^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[deprecated]` can be applied to associated consts, associated types, constants, crates, data types, enum variants, foreign statics, functions, inherent impl blocks, macro defs, modules, statics, struct fields, traits, type aliases, unions, and use statements + = help: `#[deprecated]` can be applied to associated consts, associated types, constants, crates, data types, enum variants, foreign statics, functions, inherent impl blocks, macro defs, modules, statics, struct fields, traits, type aliases, and use statements warning: `#[inline]` attribute cannot be used on macro calls --> $DIR/attr-on-mac-call.rs:24:5 @@ -136,7 +136,7 @@ LL | #[deprecated] | ^^^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[deprecated]` can be applied to associated consts, associated types, constants, crates, data types, enum variants, foreign statics, functions, inherent impl blocks, macro defs, modules, statics, struct fields, traits, type aliases, unions, and use statements + = help: `#[deprecated]` can be applied to associated consts, associated types, constants, crates, data types, enum variants, foreign statics, functions, inherent impl blocks, macro defs, modules, statics, struct fields, traits, type aliases, and use statements warning: `#[automatically_derived]` attribute cannot be used on macro calls --> $DIR/attr-on-mac-call.rs:51:5 @@ -163,7 +163,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits warning: `#[no_implicit_prelude]` attribute cannot be used on macro calls --> $DIR/attr-on-mac-call.rs:60:5 diff --git a/tests/ui/deprecation/deprecated-expr-precedence.stderr b/tests/ui/deprecation/deprecated-expr-precedence.stderr index c3124cf86ef4..bd575e6b6276 100644 --- a/tests/ui/deprecation/deprecated-expr-precedence.stderr +++ b/tests/ui/deprecation/deprecated-expr-precedence.stderr @@ -5,7 +5,7 @@ LL | #[deprecated] 0 | ^^^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[deprecated]` can be applied to associated consts, associated types, constants, crates, data types, enum variants, foreign statics, functions, inherent impl blocks, macro defs, modules, statics, struct fields, traits, type aliases, unions, and use statements + = help: `#[deprecated]` can be applied to associated consts, associated types, constants, crates, data types, enum variants, foreign statics, functions, inherent impl blocks, macro defs, modules, statics, struct fields, traits, type aliases, and use statements = note: requested on the command line with `-W unused-attributes` error[E0308]: mismatched types diff --git a/tests/ui/deprecation/deprecation-sanity.stderr b/tests/ui/deprecation/deprecation-sanity.stderr index a4dc9f23d3d2..427d14d89c19 100644 --- a/tests/ui/deprecation/deprecation-sanity.stderr +++ b/tests/ui/deprecation/deprecation-sanity.stderr @@ -83,7 +83,7 @@ LL | #[deprecated = "hello"] | ^^^^^^^^^^^^^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[deprecated]` can be applied to associated consts, associated types, constants, crates, data types, enum variants, foreign statics, functions, inherent impl blocks, macro defs, modules, statics, struct fields, traits, type aliases, unions, and use statements + = help: `#[deprecated]` can be applied to associated consts, associated types, constants, crates, data types, enum variants, foreign statics, functions, inherent impl blocks, macro defs, modules, statics, struct fields, traits, type aliases, and use statements = note: `#[deny(useless_deprecated)]` on by default error: aborting due to 10 previous errors diff --git a/tests/ui/errors/remap-path-prefix-diagnostics.not-diag-in-deps.stderr b/tests/ui/errors/remap-path-prefix-diagnostics.not-diag-in-deps.stderr index 234e251b2ad8..08c850cd8e24 100644 --- a/tests/ui/errors/remap-path-prefix-diagnostics.not-diag-in-deps.stderr +++ b/tests/ui/errors/remap-path-prefix-diagnostics.not-diag-in-deps.stderr @@ -9,7 +9,7 @@ help: the trait `std::fmt::Display` is not implemented for `A` | LL | struct A; | ^^^^^^^^ -note: required by a bound in `Trait` +note: required by a bound in `r#trait::Trait` --> $DIR/auxiliary/trait.rs:LL:COL | LL | pub trait Trait: std::fmt::Display {} diff --git a/tests/ui/errors/remap-path-prefix-diagnostics.only-debuginfo-in-deps.stderr b/tests/ui/errors/remap-path-prefix-diagnostics.only-debuginfo-in-deps.stderr index 3b0d66e75e86..ebd7606815d0 100644 --- a/tests/ui/errors/remap-path-prefix-diagnostics.only-debuginfo-in-deps.stderr +++ b/tests/ui/errors/remap-path-prefix-diagnostics.only-debuginfo-in-deps.stderr @@ -9,7 +9,7 @@ help: the trait `std::fmt::Display` is not implemented for `A` | LL | struct A; | ^^^^^^^^ -note: required by a bound in `Trait` +note: required by a bound in `r#trait::Trait` --> $DIR/auxiliary/trait-debuginfo.rs:LL:COL | LL | pub trait Trait: std::fmt::Display {} diff --git a/tests/ui/errors/remap-path-prefix-diagnostics.only-diag-in-deps.stderr b/tests/ui/errors/remap-path-prefix-diagnostics.only-diag-in-deps.stderr index 86c1140573e3..c21d49e325e2 100644 --- a/tests/ui/errors/remap-path-prefix-diagnostics.only-diag-in-deps.stderr +++ b/tests/ui/errors/remap-path-prefix-diagnostics.only-diag-in-deps.stderr @@ -9,7 +9,7 @@ help: the trait `std::fmt::Display` is not implemented for `A` | LL | struct A; | ^^^^^^^^ -note: required by a bound in `Trait` +note: required by a bound in `r#trait::Trait` --> remapped/errors/auxiliary/trait-diag.rs:LL:COL | LL | pub trait Trait: std::fmt::Display {} diff --git a/tests/ui/errors/remap-path-prefix-diagnostics.only-doc-in-deps.stderr b/tests/ui/errors/remap-path-prefix-diagnostics.only-doc-in-deps.stderr index e1b93a1042f5..6ea6c16c5149 100644 --- a/tests/ui/errors/remap-path-prefix-diagnostics.only-doc-in-deps.stderr +++ b/tests/ui/errors/remap-path-prefix-diagnostics.only-doc-in-deps.stderr @@ -9,7 +9,7 @@ help: the trait `std::fmt::Display` is not implemented for `A` | LL | struct A; | ^^^^^^^^ -note: required by a bound in `Trait` +note: required by a bound in `r#trait::Trait` --> $DIR/auxiliary/trait-doc.rs:LL:COL | LL | pub trait Trait: std::fmt::Display {} diff --git a/tests/ui/errors/remap-path-prefix-diagnostics.only-macro-in-deps.stderr b/tests/ui/errors/remap-path-prefix-diagnostics.only-macro-in-deps.stderr index 91c9cd90152b..9a0676ca0ea9 100644 --- a/tests/ui/errors/remap-path-prefix-diagnostics.only-macro-in-deps.stderr +++ b/tests/ui/errors/remap-path-prefix-diagnostics.only-macro-in-deps.stderr @@ -9,7 +9,7 @@ help: the trait `std::fmt::Display` is not implemented for `A` | LL | struct A; | ^^^^^^^^ -note: required by a bound in `Trait` +note: required by a bound in `r#trait::Trait` --> $DIR/auxiliary/trait-macro.rs:LL:COL | LL | pub trait Trait: std::fmt::Display {} diff --git a/tests/ui/errors/remap-path-prefix-diagnostics.with-debuginfo-in-deps.stderr b/tests/ui/errors/remap-path-prefix-diagnostics.with-debuginfo-in-deps.stderr index 3b0d66e75e86..ebd7606815d0 100644 --- a/tests/ui/errors/remap-path-prefix-diagnostics.with-debuginfo-in-deps.stderr +++ b/tests/ui/errors/remap-path-prefix-diagnostics.with-debuginfo-in-deps.stderr @@ -9,7 +9,7 @@ help: the trait `std::fmt::Display` is not implemented for `A` | LL | struct A; | ^^^^^^^^ -note: required by a bound in `Trait` +note: required by a bound in `r#trait::Trait` --> $DIR/auxiliary/trait-debuginfo.rs:LL:COL | LL | pub trait Trait: std::fmt::Display {} diff --git a/tests/ui/errors/remap-path-prefix-diagnostics.with-diag-in-deps.stderr b/tests/ui/errors/remap-path-prefix-diagnostics.with-diag-in-deps.stderr index 00a647df61f9..688db94a9753 100644 --- a/tests/ui/errors/remap-path-prefix-diagnostics.with-diag-in-deps.stderr +++ b/tests/ui/errors/remap-path-prefix-diagnostics.with-diag-in-deps.stderr @@ -9,7 +9,7 @@ help: the trait `std::fmt::Display` is not implemented for `A` | LL | struct A; | ^^^^^^^^ -note: required by a bound in `Trait` +note: required by a bound in `r#trait::Trait` --> remapped/errors/auxiliary/trait-diag.rs:LL:COL | LL | pub trait Trait: std::fmt::Display {} diff --git a/tests/ui/errors/remap-path-prefix-diagnostics.with-doc-in-deps.stderr b/tests/ui/errors/remap-path-prefix-diagnostics.with-doc-in-deps.stderr index e1b93a1042f5..6ea6c16c5149 100644 --- a/tests/ui/errors/remap-path-prefix-diagnostics.with-doc-in-deps.stderr +++ b/tests/ui/errors/remap-path-prefix-diagnostics.with-doc-in-deps.stderr @@ -9,7 +9,7 @@ help: the trait `std::fmt::Display` is not implemented for `A` | LL | struct A; | ^^^^^^^^ -note: required by a bound in `Trait` +note: required by a bound in `r#trait::Trait` --> $DIR/auxiliary/trait-doc.rs:LL:COL | LL | pub trait Trait: std::fmt::Display {} diff --git a/tests/ui/errors/remap-path-prefix-diagnostics.with-macro-in-deps.stderr b/tests/ui/errors/remap-path-prefix-diagnostics.with-macro-in-deps.stderr index 91c9cd90152b..9a0676ca0ea9 100644 --- a/tests/ui/errors/remap-path-prefix-diagnostics.with-macro-in-deps.stderr +++ b/tests/ui/errors/remap-path-prefix-diagnostics.with-macro-in-deps.stderr @@ -9,7 +9,7 @@ help: the trait `std::fmt::Display` is not implemented for `A` | LL | struct A; | ^^^^^^^^ -note: required by a bound in `Trait` +note: required by a bound in `r#trait::Trait` --> $DIR/auxiliary/trait-macro.rs:LL:COL | LL | pub trait Trait: std::fmt::Display {} diff --git a/tests/ui/expr/if/bad-if-let-suggestion.rs b/tests/ui/expr/if/bad-if-let-suggestion.rs index b0d0676e1ea7..c462e32c9ef5 100644 --- a/tests/ui/expr/if/bad-if-let-suggestion.rs +++ b/tests/ui/expr/if/bad-if-let-suggestion.rs @@ -1,8 +1,6 @@ fn a() { if let x = 1 && i = 2 {} - //~^ ERROR cannot find value `i` in this scope - //~| ERROR mismatched types - //~| ERROR expected expression, found `let` statement + //~^ ERROR expected expression, found `let` statement } fn b() { diff --git a/tests/ui/expr/if/bad-if-let-suggestion.stderr b/tests/ui/expr/if/bad-if-let-suggestion.stderr index 4244a3bb06ee..d0838fec67d6 100644 --- a/tests/ui/expr/if/bad-if-let-suggestion.stderr +++ b/tests/ui/expr/if/bad-if-let-suggestion.stderr @@ -15,13 +15,7 @@ LL | if let x = 1 && i == 2 {} | + error[E0425]: cannot find value `i` in this scope - --> $DIR/bad-if-let-suggestion.rs:2:21 - | -LL | if let x = 1 && i = 2 {} - | ^ not found in this scope - -error[E0425]: cannot find value `i` in this scope - --> $DIR/bad-if-let-suggestion.rs:9:9 + --> $DIR/bad-if-let-suggestion.rs:7:9 | LL | fn a() { | ------ similarly named function `a` defined here @@ -36,7 +30,7 @@ LL + if (a + j) = i {} | error[E0425]: cannot find value `j` in this scope - --> $DIR/bad-if-let-suggestion.rs:9:13 + --> $DIR/bad-if-let-suggestion.rs:7:13 | LL | fn a() { | ------ similarly named function `a` defined here @@ -51,7 +45,7 @@ LL + if (i + a) = i {} | error[E0425]: cannot find value `i` in this scope - --> $DIR/bad-if-let-suggestion.rs:9:18 + --> $DIR/bad-if-let-suggestion.rs:7:18 | LL | fn a() { | ------ similarly named function `a` defined here @@ -66,7 +60,7 @@ LL + if (i + j) = a {} | error[E0425]: cannot find value `x` in this scope - --> $DIR/bad-if-let-suggestion.rs:16:8 + --> $DIR/bad-if-let-suggestion.rs:14:8 | LL | fn a() { | ------ similarly named function `a` defined here @@ -80,18 +74,6 @@ LL - if x[0] = 1 {} LL + if a[0] = 1 {} | -error[E0308]: mismatched types - --> $DIR/bad-if-let-suggestion.rs:2:8 - | -LL | if let x = 1 && i = 2 {} - | ^^^^^^^^^^^^^^^^^^ expected `bool`, found `()` - | -help: you might have meant to compare for equality - | -LL | if let x = 1 && i == 2 {} - | + +error: aborting due to 5 previous errors -error: aborting due to 7 previous errors - -Some errors have detailed explanations: E0308, E0425. -For more information about an error, try `rustc --explain E0308`. +For more information about this error, try `rustc --explain E0425`. diff --git a/tests/ui/feature-gates/issue-43106-gating-of-builtin-attrs.stderr b/tests/ui/feature-gates/issue-43106-gating-of-builtin-attrs.stderr index fd90fe4c837b..d69daf45b352 100644 --- a/tests/ui/feature-gates/issue-43106-gating-of-builtin-attrs.stderr +++ b/tests/ui/feature-gates/issue-43106-gating-of-builtin-attrs.stderr @@ -1055,7 +1055,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits warning: `#[must_use]` attribute cannot be used on modules --> $DIR/issue-43106-gating-of-builtin-attrs.rs:766:17 @@ -1064,7 +1064,7 @@ LL | mod inner { #![must_use] } | ^^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits warning: `#[must_use]` attribute cannot be used on type aliases --> $DIR/issue-43106-gating-of-builtin-attrs.rs:775:5 @@ -1073,7 +1073,7 @@ LL | #[must_use] type T = S; | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits warning: `#[must_use]` attribute cannot be used on inherent impl blocks --> $DIR/issue-43106-gating-of-builtin-attrs.rs:780:5 @@ -1082,7 +1082,7 @@ LL | #[must_use] impl S { } | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits warning: crate-level attribute should be an inner attribute: add an exclamation mark: `#![windows_subsystem]` --> $DIR/issue-43106-gating-of-builtin-attrs.rs:786:1 @@ -1635,7 +1635,7 @@ LL | #![must_use] | ^^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits warning: 175 warnings emitted diff --git a/tests/ui/frontmatter/content-cr.rs b/tests/ui/frontmatter/content-cr.rs new file mode 100644 index 000000000000..71bede928f37 --- /dev/null +++ b/tests/ui/frontmatter/content-cr.rs @@ -0,0 +1,10 @@ +--- +package.name = " " # //~ ERROR bare CR not allowed in frontmatter +package.description = "é" +--- + +// ignore-tidy-cr + +#![feature(frontmatter)] + +pub fn main() {} diff --git a/tests/ui/frontmatter/content-cr.stderr b/tests/ui/frontmatter/content-cr.stderr new file mode 100644 index 000000000000..d59b899cc4c3 --- /dev/null +++ b/tests/ui/frontmatter/content-cr.stderr @@ -0,0 +1,8 @@ +error: bare CR not allowed in frontmatter + --> $DIR/content-cr.rs:2:17 + | +LL | package.name = "␍" # + | ^ + +error: aborting due to 1 previous error + diff --git a/tests/ui/hygiene/cross-crate-name-hiding-2.stderr b/tests/ui/hygiene/cross-crate-name-hiding-2.stderr index 336d35099c80..90dd40534ed1 100644 --- a/tests/ui/hygiene/cross-crate-name-hiding-2.stderr +++ b/tests/ui/hygiene/cross-crate-name-hiding-2.stderr @@ -1,13 +1,11 @@ error[E0422]: cannot find struct, variant or union type `MyStruct` in this scope --> $DIR/cross-crate-name-hiding-2.rs:13:13 | +LL | my_struct!(define); + | ------------------ you might have meant to refer to this struct +... LL | let x = MyStruct {}; | ^^^^^^^^ not found in this scope - | - ::: $DIR/auxiliary/use_by_macro.rs:7:24 - | -LL | pub struct MyStruct; - | -------- you might have meant to refer to this struct error: aborting due to 1 previous error diff --git a/tests/ui/imports/ambiguous-reachable.rs b/tests/ui/imports/ambiguous-reachable.rs new file mode 100644 index 000000000000..fc92315622aa --- /dev/null +++ b/tests/ui/imports/ambiguous-reachable.rs @@ -0,0 +1,8 @@ +//@ build-pass +//@ aux-crate: ambiguous_reachable_extern=ambiguous-reachable-extern.rs + +#![allow(ambiguous_glob_imports)] + +fn main() { + ambiguous_reachable_extern::generic::(); +} diff --git a/tests/ui/imports/ambiguous-reachable.stderr b/tests/ui/imports/ambiguous-reachable.stderr new file mode 100644 index 000000000000..78a0d76d68b5 --- /dev/null +++ b/tests/ui/imports/ambiguous-reachable.stderr @@ -0,0 +1,23 @@ +Future incompatibility report: Future breakage diagnostic: +warning: `generic` is ambiguous + --> $DIR/ambiguous-reachable.rs:7:33 + | +LL | ambiguous_reachable_extern::generic::(); + | ^^^^^^^ ambiguous name + | + = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! + = note: for more information, see issue #114095 + = note: ambiguous because of multiple glob imports of a name in the same module +note: `generic` could refer to the function defined here + --> $DIR/auxiliary/ambiguous-reachable-extern.rs:13:9 + | +LL | pub use m1::*; + | ^^ + = help: consider updating this dependency to resolve this error + = help: if updating the dependency does not resolve the problem report the problem to the author of the relevant crate +note: `generic` could also refer to the function defined here + --> $DIR/auxiliary/ambiguous-reachable-extern.rs:14:9 + | +LL | pub use m2::*; + | ^^ + diff --git a/tests/ui/imports/auxiliary/ambiguous-reachable-extern.rs b/tests/ui/imports/auxiliary/ambiguous-reachable-extern.rs new file mode 100644 index 000000000000..af81812560e3 --- /dev/null +++ b/tests/ui/imports/auxiliary/ambiguous-reachable-extern.rs @@ -0,0 +1,14 @@ +mod m1 { + pub fn generic() { + let x = 10; + let y = 11; + println!("hello {x} world {:?}", y); + } +} + +mod m2 { + pub fn generic() {} +} + +pub use m1::*; +pub use m2::*; diff --git a/tests/ui/lint/fn_must_use.stderr b/tests/ui/lint/fn_must_use.stderr index 0e8da873e7c3..bdf4eb6de4a5 100644 --- a/tests/ui/lint/fn_must_use.stderr +++ b/tests/ui/lint/fn_must_use.stderr @@ -5,7 +5,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, foreign functions, functions, inherent methods, provided trait methods, required trait methods, traits, and unions + = help: `#[must_use]` can be applied to data types, foreign functions, functions, inherent methods, provided trait methods, required trait methods, and traits = note: requested on the command line with `-W unused-attributes` warning: unused return value of `need_to_use_this_value` that must be used diff --git a/tests/ui/lint/invalid_value-polymorphic.rs b/tests/ui/lint/invalid_value-polymorphic.rs index 6a31ac17d96f..4ed8950d20fa 100644 --- a/tests/ui/lint/invalid_value-polymorphic.rs +++ b/tests/ui/lint/invalid_value-polymorphic.rs @@ -1,4 +1,4 @@ -//@ compile-flags: --crate-type=lib -Zmir-enable-passes=+InstSimplify +//@ compile-flags: --crate-type=lib -Zmir-enable-passes=+InstSimplify-before-inline //@ build-pass #![feature(core_intrinsics)] diff --git a/tests/ui/lint/must_not_suspend/other_items.stderr b/tests/ui/lint/must_not_suspend/other_items.stderr index 999a9d2fb3dc..289230b027ad 100644 --- a/tests/ui/lint/must_not_suspend/other_items.stderr +++ b/tests/ui/lint/must_not_suspend/other_items.stderr @@ -4,7 +4,7 @@ error: `#[must_not_suspend]` attribute cannot be used on modules LL | #[must_not_suspend] | ^^^^^^^^^^^^^^^^^^^ | - = help: `#[must_not_suspend]` can be applied to data types, traits, and unions + = help: `#[must_not_suspend]` can be applied to data types and traits error: aborting due to 1 previous error diff --git a/tests/ui/lint/must_not_suspend/return.stderr b/tests/ui/lint/must_not_suspend/return.stderr index 1a81b1a39f0c..b041491128e1 100644 --- a/tests/ui/lint/must_not_suspend/return.stderr +++ b/tests/ui/lint/must_not_suspend/return.stderr @@ -4,7 +4,7 @@ error: `#[must_not_suspend]` attribute cannot be used on functions LL | #[must_not_suspend] | ^^^^^^^^^^^^^^^^^^^ | - = help: `#[must_not_suspend]` can be applied to data types, traits, and unions + = help: `#[must_not_suspend]` can be applied to data types and traits error: aborting due to 1 previous error diff --git a/tests/ui/lint/unused/lint-unsed-in-macro-issue-151269.rs b/tests/ui/lint/unused/lint-unsed-in-macro-issue-151269.rs new file mode 100644 index 000000000000..65b8a22d383a --- /dev/null +++ b/tests/ui/lint/unused/lint-unsed-in-macro-issue-151269.rs @@ -0,0 +1,15 @@ +#![deny(unused_must_use)] + +fn error() -> Result<(), ()> { + Err(()) +} + +macro_rules! foo { + () => {{ + error(); + }}; +} + +fn main() { + let _ = foo!(); //~ ERROR unused `Result` that must be used +} diff --git a/tests/ui/lint/unused/lint-unsed-in-macro-issue-151269.stderr b/tests/ui/lint/unused/lint-unsed-in-macro-issue-151269.stderr new file mode 100644 index 000000000000..12cedf58974b --- /dev/null +++ b/tests/ui/lint/unused/lint-unsed-in-macro-issue-151269.stderr @@ -0,0 +1,19 @@ +error: unused `Result` that must be used + --> $DIR/lint-unsed-in-macro-issue-151269.rs:14:13 + | +LL | let _ = foo!(); + | ^^^^^^ + | + = note: this `Result` may be an `Err` variant, which should be handled +note: the lint level is defined here + --> $DIR/lint-unsed-in-macro-issue-151269.rs:1:9 + | +LL | #![deny(unused_must_use)] + | ^^^^^^^^^^^^^^^ +help: use `let _ = ...` to ignore the resulting value + | +LL | let _ = error(); + | +++++++ + +error: aborting due to 1 previous error + diff --git a/tests/ui/lint/unused/unused-macros.stderr b/tests/ui/lint/unused/unused-macros.stderr index d0baf5becec4..50c80b61eb5b 100644 --- a/tests/ui/lint/unused/unused-macros.stderr +++ b/tests/ui/lint/unused/unused-macros.stderr @@ -15,6 +15,11 @@ error: unused macro definition: `m` | LL | macro_rules! m { | ^ +... +LL | create_macro!(); + | --------------- in this macro invocation + | + = note: this error originates in the macro `create_macro` (in Nightly builds, run with -Z macro-backtrace for more info) error: unused macro definition: `unused` --> $DIR/unused-macros.rs:26:18 diff --git a/tests/ui/lint/unused/unused_attributes-must_use.stderr b/tests/ui/lint/unused/unused_attributes-must_use.stderr index 3192c0994548..3fc340b5188f 100644 --- a/tests/ui/lint/unused/unused_attributes-must_use.stderr +++ b/tests/ui/lint/unused/unused_attributes-must_use.stderr @@ -5,7 +5,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits note: the lint level is defined here --> $DIR/unused_attributes-must_use.rs:4:9 | @@ -19,7 +19,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits error: `#[must_use]` attribute cannot be used on modules --> $DIR/unused_attributes-must_use.rs:11:1 @@ -28,7 +28,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits error: `#[must_use]` attribute cannot be used on use statements --> $DIR/unused_attributes-must_use.rs:15:1 @@ -37,7 +37,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits error: `#[must_use]` attribute cannot be used on constants --> $DIR/unused_attributes-must_use.rs:19:1 @@ -46,7 +46,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits error: `#[must_use]` attribute cannot be used on statics --> $DIR/unused_attributes-must_use.rs:22:1 @@ -55,7 +55,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits error: `#[must_use]` attribute cannot be used on inherent impl blocks --> $DIR/unused_attributes-must_use.rs:40:1 @@ -64,7 +64,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits error: `#[must_use]` attribute cannot be used on foreign modules --> $DIR/unused_attributes-must_use.rs:55:1 @@ -73,7 +73,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits error: `#[must_use]` attribute cannot be used on foreign statics --> $DIR/unused_attributes-must_use.rs:59:5 @@ -82,7 +82,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits error: `#[must_use]` attribute cannot be used on type aliases --> $DIR/unused_attributes-must_use.rs:73:1 @@ -91,7 +91,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits error: `#[must_use]` attribute cannot be used on type parameters --> $DIR/unused_attributes-must_use.rs:77:8 @@ -100,7 +100,7 @@ LL | fn qux<#[must_use] T>(_: T) {} | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits error: `#[must_use]` attribute cannot be used on associated consts --> $DIR/unused_attributes-must_use.rs:82:5 @@ -109,7 +109,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits error: `#[must_use]` attribute cannot be used on associated types --> $DIR/unused_attributes-must_use.rs:85:5 @@ -118,7 +118,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits error: `#[must_use]` attribute cannot be used on trait impl blocks --> $DIR/unused_attributes-must_use.rs:95:1 @@ -127,7 +127,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits error: `#[must_use]` attribute cannot be used on trait methods in impl blocks --> $DIR/unused_attributes-must_use.rs:100:5 @@ -136,7 +136,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, foreign functions, functions, inherent methods, provided trait methods, required trait methods, traits, and unions + = help: `#[must_use]` can be applied to data types, foreign functions, functions, inherent methods, provided trait methods, required trait methods, and traits error: `#[must_use]` attribute cannot be used on trait aliases --> $DIR/unused_attributes-must_use.rs:107:1 @@ -145,7 +145,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits error: `#[must_use]` attribute cannot be used on macro defs --> $DIR/unused_attributes-must_use.rs:111:1 @@ -154,7 +154,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits error: `#[must_use]` attribute cannot be used on statements --> $DIR/unused_attributes-must_use.rs:120:5 @@ -163,7 +163,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits error: `#[must_use]` attribute cannot be used on closures --> $DIR/unused_attributes-must_use.rs:125:13 @@ -172,7 +172,7 @@ LL | let x = #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, foreign functions, functions, methods, traits, and unions + = help: `#[must_use]` can be applied to data types, foreign functions, functions, methods, and traits error: `#[must_use]` attribute cannot be used on match arms --> $DIR/unused_attributes-must_use.rs:148:9 @@ -181,7 +181,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits error: `#[must_use]` attribute cannot be used on struct fields --> $DIR/unused_attributes-must_use.rs:157:28 @@ -190,7 +190,7 @@ LL | let s = PatternField { #[must_use] foo: 123 }; | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits error: `#[must_use]` attribute cannot be used on pattern fields --> $DIR/unused_attributes-must_use.rs:159:24 @@ -199,7 +199,7 @@ LL | let PatternField { #[must_use] foo } = s; | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits error: unused `X` that must be used --> $DIR/unused_attributes-must_use.rs:130:5 diff --git a/tests/ui/mir/enable_passes_validation.enum_not_in_pass_names.stderr b/tests/ui/mir/enable_passes_validation.enum_not_in_pass_names.stderr new file mode 100644 index 000000000000..89229ebabe84 --- /dev/null +++ b/tests/ui/mir/enable_passes_validation.enum_not_in_pass_names.stderr @@ -0,0 +1,8 @@ +warning: MIR pass `SimplifyCfg` is unknown and will be ignored + +warning: MIR pass `SimplifyCfg` is unknown and will be ignored + | + = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no` + +warning: 2 warnings emitted + diff --git a/tests/ui/mir/enable_passes_validation.rs b/tests/ui/mir/enable_passes_validation.rs index 99b1ba528b0c..d3d22b49ac7f 100644 --- a/tests/ui/mir/enable_passes_validation.rs +++ b/tests/ui/mir/enable_passes_validation.rs @@ -1,4 +1,5 @@ //@ revisions: empty unprefixed all_unknown all_known mixed +//@ revisions: enum_not_in_pass_names enum_in_pass_names //@[empty] compile-flags: -Zmir-enable-passes= @@ -13,6 +14,12 @@ //@[mixed] check-pass //@[mixed] compile-flags: -Zmir-enable-passes=+ThisPassDoesNotExist,+CheckAlignment +//@[enum_not_in_pass_names] check-pass +//@[enum_not_in_pass_names] compile-flags: -Zmir-enable-passes=+SimplifyCfg + +//@[enum_in_pass_names] check-pass +//@[enum_in_pass_names] compile-flags: -Zmir-enable-passes=+AddCallGuards + fn main() {} //[empty]~? ERROR incorrect value `` for unstable option `mir-enable-passes` @@ -23,3 +30,5 @@ fn main() {} //[all_unknown]~? WARN MIR pass `DoesNotExist` is unknown and will be ignored //[all_unknown]~? WARN MIR pass `ThisPass` is unknown and will be ignored //[all_unknown]~? WARN MIR pass `DoesNotExist` is unknown and will be ignored +//[enum_not_in_pass_names]~? WARN MIR pass `SimplifyCfg` is unknown and will be ignored +//[enum_not_in_pass_names]~? WARN MIR pass `SimplifyCfg` is unknown and will be ignored diff --git a/tests/ui/missing/missing-let.rs b/tests/ui/missing/missing-let.rs new file mode 100644 index 000000000000..36db7bc95826 --- /dev/null +++ b/tests/ui/missing/missing-let.rs @@ -0,0 +1,6 @@ +fn main() { + let x = Some(42); + if let Some(_) = x + && Some(x) = x //~^ ERROR expected expression, found `let` statement + {} +} diff --git a/tests/ui/missing/missing-let.stderr b/tests/ui/missing/missing-let.stderr new file mode 100644 index 000000000000..897ff6329d59 --- /dev/null +++ b/tests/ui/missing/missing-let.stderr @@ -0,0 +1,18 @@ +error: expected expression, found `let` statement + --> $DIR/missing-let.rs:3:8 + | +LL | if let Some(_) = x + | ^^^^^^^^^^^^^^^ + | + = note: only supported directly in conditions of `if` and `while` expressions +help: you might have meant to continue the let-chain + | +LL | && let Some(x) = x + | +++ +help: you might have meant to compare for equality + | +LL | && Some(x) == x + | + + +error: aborting due to 1 previous error + diff --git a/tests/ui/pin-ergonomics/impl-unpin.adt.stderr b/tests/ui/pin-ergonomics/impl-unpin.adt.stderr new file mode 100644 index 000000000000..56fac42d4e32 --- /dev/null +++ b/tests/ui/pin-ergonomics/impl-unpin.adt.stderr @@ -0,0 +1,14 @@ +error: explicit impls for the `Unpin` trait are not permitted for structurally pinned types + --> $DIR/impl-unpin.rs:14:5 + | +LL | impl Unpin for Foo {} + | ^^^^^^^^^^^^^^^^^^ impl of `Unpin` not allowed + | +help: `Foo` is structurally pinned because it is marked as `#[pin_v2]` + --> $DIR/impl-unpin.rs:7:1 + | +LL | struct Foo; + | ^^^^^^^^^^ + +error: aborting due to 1 previous error + diff --git a/tests/ui/pin-ergonomics/impl-unpin.assoc.stderr b/tests/ui/pin-ergonomics/impl-unpin.assoc.stderr new file mode 100644 index 000000000000..7f0ee1ddd898 --- /dev/null +++ b/tests/ui/pin-ergonomics/impl-unpin.assoc.stderr @@ -0,0 +1,15 @@ +error[E0321]: cross-crate traits with a default impl, like `Unpin`, can only be implemented for a struct/enum type, not `::Assoc` + --> $DIR/impl-unpin.rs:68:5 + | +LL | impl Unpin for ::Assoc {} + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ can't implement cross-crate trait with a default impl for non-struct/enum type + +error[E0321]: cross-crate traits with a default impl, like `Unpin`, can only be implemented for a struct/enum type, not `::Assoc` + --> $DIR/impl-unpin.rs:70:5 + | +LL | impl Unpin for ::Assoc {} + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ can't implement cross-crate trait with a default impl for non-struct/enum type + +error: aborting due to 2 previous errors + +For more information about this error, try `rustc --explain E0321`. diff --git a/tests/ui/pin-ergonomics/impl-unpin.rs b/tests/ui/pin-ergonomics/impl-unpin.rs new file mode 100644 index 000000000000..ded8b4774dd9 --- /dev/null +++ b/tests/ui/pin-ergonomics/impl-unpin.rs @@ -0,0 +1,74 @@ +//@ revisions: adt tait ty_alias assoc +#![feature(pin_ergonomics)] +#![cfg_attr(tait, feature(type_alias_impl_trait))] +#![allow(incomplete_features)] + +#[pin_v2] +struct Foo; +struct Bar; + +#[cfg(adt)] +mod adt { + use super::*; + + impl Unpin for Foo {} + //[adt]~^ ERROR explicit impls for the `Unpin` trait are not permitted for structurally pinned types + impl Unpin for Bar {} // ok +} + +#[cfg(ty_alias)] +mod ty_alias { + use super::*; + + type Identity = T; + + impl Unpin for Identity {} + //[ty_alias]~^ ERROR explicit impls for the `Unpin` trait are not permitted for structurally pinned types + impl Unpin for Identity {} // ok +} + +#[cfg(tait)] +mod tait { + use super::*; + + trait Identity {} + + impl Identity for T {} + + type FooAlias = impl Identity; + type BarAlias = impl Identity; + + #[define_opaque(FooAlias)] + fn foo_alias() -> FooAlias { + Foo + } + #[define_opaque(BarAlias)] + fn bar_alias() -> BarAlias { + Bar + } + + impl Unpin for FooAlias {} + //[tait]~^ ERROR only traits defined in the current crate can be implemented for arbitrary types + impl Unpin for BarAlias {} + //[tait]~^ ERROR only traits defined in the current crate can be implemented for arbitrary types +} + +#[cfg(assoc)] +mod assoc { + use super::*; + + trait Identity { + type Assoc; + } + + impl Identity for T { + type Assoc = T; + } + + impl Unpin for ::Assoc {} + //[assoc]~^ ERROR cross-crate traits with a default impl, like `Unpin`, can only be implemented for a struct/enum type, not `::Assoc` + impl Unpin for ::Assoc {} + //[assoc]~^ ERROR cross-crate traits with a default impl, like `Unpin`, can only be implemented for a struct/enum type, not `::Assoc` +} + +fn main() {} diff --git a/tests/ui/pin-ergonomics/impl-unpin.tait.stderr b/tests/ui/pin-ergonomics/impl-unpin.tait.stderr new file mode 100644 index 000000000000..5d9392745df3 --- /dev/null +++ b/tests/ui/pin-ergonomics/impl-unpin.tait.stderr @@ -0,0 +1,27 @@ +error[E0117]: only traits defined in the current crate can be implemented for arbitrary types + --> $DIR/impl-unpin.rs:50:5 + | +LL | impl Unpin for FooAlias {} + | ^^^^^^^^^^^^^^^-------- + | | + | type alias impl trait is treated as if it were foreign, because its hidden type could be from a foreign crate + | + = note: impl doesn't have any local type before any uncovered type parameters + = note: for more information see https://doc.rust-lang.org/reference/items/implementations.html#orphan-rules + = note: define and implement a trait or new type instead + +error[E0117]: only traits defined in the current crate can be implemented for arbitrary types + --> $DIR/impl-unpin.rs:52:5 + | +LL | impl Unpin for BarAlias {} + | ^^^^^^^^^^^^^^^-------- + | | + | type alias impl trait is treated as if it were foreign, because its hidden type could be from a foreign crate + | + = note: impl doesn't have any local type before any uncovered type parameters + = note: for more information see https://doc.rust-lang.org/reference/items/implementations.html#orphan-rules + = note: define and implement a trait or new type instead + +error: aborting due to 2 previous errors + +For more information about this error, try `rustc --explain E0117`. diff --git a/tests/ui/pin-ergonomics/impl-unpin.ty_alias.stderr b/tests/ui/pin-ergonomics/impl-unpin.ty_alias.stderr new file mode 100644 index 000000000000..82c1a7d29ddf --- /dev/null +++ b/tests/ui/pin-ergonomics/impl-unpin.ty_alias.stderr @@ -0,0 +1,14 @@ +error: explicit impls for the `Unpin` trait are not permitted for structurally pinned types + --> $DIR/impl-unpin.rs:25:5 + | +LL | impl Unpin for Identity {} + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ impl of `Unpin` not allowed + | +help: `Foo` is structurally pinned because it is marked as `#[pin_v2]` + --> $DIR/impl-unpin.rs:7:1 + | +LL | struct Foo; + | ^^^^^^^^^^ + +error: aborting due to 1 previous error + diff --git a/tests/ui/pin-ergonomics/pin_v2-attr.stderr b/tests/ui/pin-ergonomics/pin_v2-attr.stderr index c297afa87a73..8f8a9f3b3a19 100644 --- a/tests/ui/pin-ergonomics/pin_v2-attr.stderr +++ b/tests/ui/pin-ergonomics/pin_v2-attr.stderr @@ -4,7 +4,7 @@ error: `#[pin_v2]` attribute cannot be used on macro calls LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: allow, cfg, cfg_attr, deny, expect, forbid, and warn are the only allowed built-in attributes in function parameters --> $DIR/pin_v2-attr.rs:84:12 @@ -18,7 +18,7 @@ error: `#[pin_v2]` attribute cannot be used on crates LL | #![pin_v2] | ^^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on type parameters --> $DIR/pin_v2-attr.rs:27:10 @@ -26,7 +26,7 @@ error: `#[pin_v2]` attribute cannot be used on type parameters LL | enum Foo<#[pin_v2] T, #[pin_v2] U = ()> { | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on type parameters --> $DIR/pin_v2-attr.rs:27:23 @@ -34,7 +34,7 @@ error: `#[pin_v2]` attribute cannot be used on type parameters LL | enum Foo<#[pin_v2] T, #[pin_v2] U = ()> { | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on enum variants --> $DIR/pin_v2-attr.rs:30:5 @@ -42,7 +42,7 @@ error: `#[pin_v2]` attribute cannot be used on enum variants LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on struct fields --> $DIR/pin_v2-attr.rs:32:18 @@ -50,7 +50,7 @@ error: `#[pin_v2]` attribute cannot be used on struct fields LL | TupleVariant(#[pin_v2] T), | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on struct fields --> $DIR/pin_v2-attr.rs:34:9 @@ -58,7 +58,7 @@ error: `#[pin_v2]` attribute cannot be used on struct fields LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on traits --> $DIR/pin_v2-attr.rs:39:1 @@ -66,7 +66,7 @@ error: `#[pin_v2]` attribute cannot be used on traits LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on associated consts --> $DIR/pin_v2-attr.rs:41:5 @@ -74,7 +74,7 @@ error: `#[pin_v2]` attribute cannot be used on associated consts LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on associated types --> $DIR/pin_v2-attr.rs:43:5 @@ -82,7 +82,7 @@ error: `#[pin_v2]` attribute cannot be used on associated types LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on required trait methods --> $DIR/pin_v2-attr.rs:46:5 @@ -90,7 +90,7 @@ error: `#[pin_v2]` attribute cannot be used on required trait methods LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on provided trait methods --> $DIR/pin_v2-attr.rs:48:5 @@ -98,7 +98,7 @@ error: `#[pin_v2]` attribute cannot be used on provided trait methods LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on trait aliases --> $DIR/pin_v2-attr.rs:52:1 @@ -106,7 +106,7 @@ error: `#[pin_v2]` attribute cannot be used on trait aliases LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on inherent impl blocks --> $DIR/pin_v2-attr.rs:55:1 @@ -114,7 +114,7 @@ error: `#[pin_v2]` attribute cannot be used on inherent impl blocks LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on delegations --> $DIR/pin_v2-attr.rs:58:5 @@ -122,7 +122,7 @@ error: `#[pin_v2]` attribute cannot be used on delegations LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on inherent methods --> $DIR/pin_v2-attr.rs:61:5 @@ -130,7 +130,7 @@ error: `#[pin_v2]` attribute cannot be used on inherent methods LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on trait impl blocks --> $DIR/pin_v2-attr.rs:65:1 @@ -138,7 +138,7 @@ error: `#[pin_v2]` attribute cannot be used on trait impl blocks LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on trait methods in impl blocks --> $DIR/pin_v2-attr.rs:67:5 @@ -146,7 +146,7 @@ error: `#[pin_v2]` attribute cannot be used on trait methods in impl blocks LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on extern crates --> $DIR/pin_v2-attr.rs:71:1 @@ -154,7 +154,7 @@ error: `#[pin_v2]` attribute cannot be used on extern crates LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on use statements --> $DIR/pin_v2-attr.rs:74:1 @@ -162,7 +162,7 @@ error: `#[pin_v2]` attribute cannot be used on use statements LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on statics --> $DIR/pin_v2-attr.rs:77:1 @@ -170,7 +170,7 @@ error: `#[pin_v2]` attribute cannot be used on statics LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on constants --> $DIR/pin_v2-attr.rs:80:1 @@ -178,7 +178,7 @@ error: `#[pin_v2]` attribute cannot be used on constants LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on functions --> $DIR/pin_v2-attr.rs:83:1 @@ -186,7 +186,7 @@ error: `#[pin_v2]` attribute cannot be used on functions LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on function params --> $DIR/pin_v2-attr.rs:84:12 @@ -194,7 +194,7 @@ error: `#[pin_v2]` attribute cannot be used on function params LL | fn f(#[pin_v2] param: Foo) | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on closures --> $DIR/pin_v2-attr.rs:92:5 @@ -202,7 +202,7 @@ error: `#[pin_v2]` attribute cannot be used on closures LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on expressions --> $DIR/pin_v2-attr.rs:94:5 @@ -210,7 +210,7 @@ error: `#[pin_v2]` attribute cannot be used on expressions LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on struct fields --> $DIR/pin_v2-attr.rs:98:9 @@ -218,7 +218,7 @@ error: `#[pin_v2]` attribute cannot be used on struct fields LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on statements --> $DIR/pin_v2-attr.rs:96:5 @@ -226,7 +226,7 @@ error: `#[pin_v2]` attribute cannot be used on statements LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on match arms --> $DIR/pin_v2-attr.rs:102:9 @@ -234,7 +234,7 @@ error: `#[pin_v2]` attribute cannot be used on match arms LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on pattern fields --> $DIR/pin_v2-attr.rs:106:13 @@ -242,7 +242,7 @@ error: `#[pin_v2]` attribute cannot be used on pattern fields LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on where predicates --> $DIR/pin_v2-attr.rs:88:5 @@ -250,7 +250,7 @@ error: `#[pin_v2]` attribute cannot be used on where predicates LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on modules --> $DIR/pin_v2-attr.rs:112:1 @@ -258,7 +258,7 @@ error: `#[pin_v2]` attribute cannot be used on modules LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on foreign modules --> $DIR/pin_v2-attr.rs:115:1 @@ -266,7 +266,7 @@ error: `#[pin_v2]` attribute cannot be used on foreign modules LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on foreign types --> $DIR/pin_v2-attr.rs:117:5 @@ -274,7 +274,7 @@ error: `#[pin_v2]` attribute cannot be used on foreign types LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on foreign statics --> $DIR/pin_v2-attr.rs:120:5 @@ -282,7 +282,7 @@ error: `#[pin_v2]` attribute cannot be used on foreign statics LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on foreign functions --> $DIR/pin_v2-attr.rs:123:5 @@ -290,7 +290,7 @@ error: `#[pin_v2]` attribute cannot be used on foreign functions LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on type aliases --> $DIR/pin_v2-attr.rs:127:1 @@ -298,7 +298,7 @@ error: `#[pin_v2]` attribute cannot be used on type aliases LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: `#[pin_v2]` attribute cannot be used on macro defs --> $DIR/pin_v2-attr.rs:130:1 @@ -306,7 +306,7 @@ error: `#[pin_v2]` attribute cannot be used on macro defs LL | #[pin_v2] | ^^^^^^^^^ | - = help: `#[pin_v2]` can be applied to data types and unions + = help: `#[pin_v2]` can only be applied to data types error: aborting due to 39 previous errors diff --git a/tests/ui/privacy/private-inferred-type.rs b/tests/ui/privacy/private-inferred-type.rs index 8c07226fe0e4..ed22ad44c449 100644 --- a/tests/ui/privacy/private-inferred-type.rs +++ b/tests/ui/privacy/private-inferred-type.rs @@ -115,11 +115,11 @@ fn main() { m::m!(); - m::leak_anon1(); //~ ERROR trait `Trait` is private + m::leak_anon1(); //~ ERROR trait `m::Trait` is private m::leak_anon2(); //~ ERROR type `Priv` is private m::leak_anon3(); //~ ERROR type `Priv` is private - m::leak_dyn1(); //~ ERROR trait `Trait` is private + m::leak_dyn1(); //~ ERROR trait `m::Trait` is private m::leak_dyn2(); //~ ERROR type `Priv` is private m::leak_dyn3(); //~ ERROR type `Priv` is private diff --git a/tests/ui/privacy/private-inferred-type.stderr b/tests/ui/privacy/private-inferred-type.stderr index fc3f9ab62bfa..0dfa799a4d95 100644 --- a/tests/ui/privacy/private-inferred-type.stderr +++ b/tests/ui/privacy/private-inferred-type.stderr @@ -172,7 +172,7 @@ LL | m::m!(); | = note: this error originates in the macro `m::m` (in Nightly builds, run with -Z macro-backtrace for more info) -error: trait `Trait` is private +error: trait `m::Trait` is private --> $DIR/private-inferred-type.rs:118:5 | LL | m::leak_anon1(); @@ -190,7 +190,7 @@ error: type `Priv` is private LL | m::leak_anon3(); | ^^^^^^^^^^^^^^^ private type -error: trait `Trait` is private +error: trait `m::Trait` is private --> $DIR/private-inferred-type.rs:122:5 | LL | m::leak_dyn1(); diff --git a/tests/ui/proc-macro/dollar-crate-issue-62325.stdout b/tests/ui/proc-macro/dollar-crate-issue-62325.stdout index bfd013476f3a..d1b7227c138d 100644 --- a/tests/ui/proc-macro/dollar-crate-issue-62325.stdout +++ b/tests/ui/proc-macro/dollar-crate-issue-62325.stdout @@ -57,54 +57,54 @@ PRINT-ATTR INPUT (DISPLAY): struct B(identity! ($crate :: S)); PRINT-ATTR INPUT (DEBUG): TokenStream [ Ident { ident: "struct", - span: $DIR/auxiliary/dollar-crate-external.rs:21:5: 21:11 (#11), + span: $DIR/auxiliary/dollar-crate-external.rs:21:5: 21:11 (#12), }, Ident { ident: "B", - span: $DIR/auxiliary/dollar-crate-external.rs:21:12: 21:13 (#11), + span: $DIR/auxiliary/dollar-crate-external.rs:21:12: 21:13 (#12), }, Group { delimiter: Parenthesis, stream: TokenStream [ Ident { ident: "identity", - span: $DIR/auxiliary/dollar-crate-external.rs:21:14: 21:22 (#11), + span: $DIR/auxiliary/dollar-crate-external.rs:21:14: 21:22 (#12), }, Punct { ch: '!', spacing: Alone, - span: $DIR/auxiliary/dollar-crate-external.rs:21:22: 21:23 (#11), + span: $DIR/auxiliary/dollar-crate-external.rs:21:22: 21:23 (#12), }, Group { delimiter: Parenthesis, stream: TokenStream [ Ident { ident: "$crate", - span: $DIR/auxiliary/dollar-crate-external.rs:21:24: 21:30 (#11), + span: $DIR/auxiliary/dollar-crate-external.rs:21:24: 21:30 (#12), }, Punct { ch: ':', spacing: Joint, - span: $DIR/auxiliary/dollar-crate-external.rs:21:30: 21:31 (#11), + span: $DIR/auxiliary/dollar-crate-external.rs:21:30: 21:31 (#12), }, Punct { ch: ':', spacing: Alone, - span: $DIR/auxiliary/dollar-crate-external.rs:21:31: 21:32 (#11), + span: $DIR/auxiliary/dollar-crate-external.rs:21:31: 21:32 (#12), }, Ident { ident: "S", - span: $DIR/auxiliary/dollar-crate-external.rs:21:32: 21:33 (#11), + span: $DIR/auxiliary/dollar-crate-external.rs:21:32: 21:33 (#12), }, ], - span: $DIR/auxiliary/dollar-crate-external.rs:21:23: 21:34 (#11), + span: $DIR/auxiliary/dollar-crate-external.rs:21:23: 21:34 (#12), }, ], - span: $DIR/auxiliary/dollar-crate-external.rs:21:13: 21:35 (#11), + span: $DIR/auxiliary/dollar-crate-external.rs:21:13: 21:35 (#12), }, Punct { ch: ';', spacing: Alone, - span: $DIR/auxiliary/dollar-crate-external.rs:21:35: 21:36 (#11), + span: $DIR/auxiliary/dollar-crate-external.rs:21:35: 21:36 (#12), }, ] diff --git a/tests/ui/proc-macro/dollar-crate.stdout b/tests/ui/proc-macro/dollar-crate.stdout index 0278ef1ad0fc..f39d03540916 100644 --- a/tests/ui/proc-macro/dollar-crate.stdout +++ b/tests/ui/proc-macro/dollar-crate.stdout @@ -122,119 +122,119 @@ PRINT-BANG INPUT (DISPLAY): struct M($crate :: S); PRINT-BANG INPUT (DEBUG): TokenStream [ Ident { ident: "struct", - span: $DIR/auxiliary/dollar-crate-external.rs:7:13: 7:19 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:7:13: 7:19 (#15), }, Ident { ident: "M", - span: $DIR/auxiliary/dollar-crate-external.rs:7:20: 7:21 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:7:20: 7:21 (#15), }, Group { delimiter: Parenthesis, stream: TokenStream [ Ident { ident: "$crate", - span: $DIR/auxiliary/dollar-crate-external.rs:7:22: 7:28 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:7:22: 7:28 (#15), }, Punct { ch: ':', spacing: Joint, - span: $DIR/auxiliary/dollar-crate-external.rs:7:28: 7:29 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:7:28: 7:29 (#15), }, Punct { ch: ':', spacing: Alone, - span: $DIR/auxiliary/dollar-crate-external.rs:7:29: 7:30 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:7:29: 7:30 (#15), }, Ident { ident: "S", - span: $DIR/auxiliary/dollar-crate-external.rs:7:30: 7:31 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:7:30: 7:31 (#15), }, ], - span: $DIR/auxiliary/dollar-crate-external.rs:7:21: 7:32 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:7:21: 7:32 (#15), }, Punct { ch: ';', spacing: Alone, - span: $DIR/auxiliary/dollar-crate-external.rs:7:32: 7:33 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:7:32: 7:33 (#15), }, ] PRINT-ATTR INPUT (DISPLAY): struct A($crate :: S); PRINT-ATTR INPUT (DEBUG): TokenStream [ Ident { ident: "struct", - span: $DIR/auxiliary/dollar-crate-external.rs:11:9: 11:15 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:11:9: 11:15 (#15), }, Ident { ident: "A", - span: $DIR/auxiliary/dollar-crate-external.rs:11:16: 11:17 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:11:16: 11:17 (#15), }, Group { delimiter: Parenthesis, stream: TokenStream [ Ident { ident: "$crate", - span: $DIR/auxiliary/dollar-crate-external.rs:11:18: 11:24 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:11:18: 11:24 (#15), }, Punct { ch: ':', spacing: Joint, - span: $DIR/auxiliary/dollar-crate-external.rs:11:24: 11:25 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:11:24: 11:25 (#15), }, Punct { ch: ':', spacing: Alone, - span: $DIR/auxiliary/dollar-crate-external.rs:11:25: 11:26 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:11:25: 11:26 (#15), }, Ident { ident: "S", - span: $DIR/auxiliary/dollar-crate-external.rs:11:26: 11:27 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:11:26: 11:27 (#15), }, ], - span: $DIR/auxiliary/dollar-crate-external.rs:11:17: 11:28 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:11:17: 11:28 (#15), }, Punct { ch: ';', spacing: Alone, - span: $DIR/auxiliary/dollar-crate-external.rs:11:28: 11:29 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:11:28: 11:29 (#15), }, ] PRINT-DERIVE INPUT (DISPLAY): struct D($crate :: S); PRINT-DERIVE INPUT (DEBUG): TokenStream [ Ident { ident: "struct", - span: $DIR/auxiliary/dollar-crate-external.rs:14:9: 14:15 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:14:9: 14:15 (#15), }, Ident { ident: "D", - span: $DIR/auxiliary/dollar-crate-external.rs:14:16: 14:17 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:14:16: 14:17 (#15), }, Group { delimiter: Parenthesis, stream: TokenStream [ Ident { ident: "$crate", - span: $DIR/auxiliary/dollar-crate-external.rs:14:18: 14:24 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:14:18: 14:24 (#15), }, Punct { ch: ':', spacing: Joint, - span: $DIR/auxiliary/dollar-crate-external.rs:14:24: 14:25 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:14:24: 14:25 (#15), }, Punct { ch: ':', spacing: Alone, - span: $DIR/auxiliary/dollar-crate-external.rs:14:25: 14:26 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:14:25: 14:26 (#15), }, Ident { ident: "S", - span: $DIR/auxiliary/dollar-crate-external.rs:14:26: 14:27 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:14:26: 14:27 (#15), }, ], - span: $DIR/auxiliary/dollar-crate-external.rs:14:17: 14:28 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:14:17: 14:28 (#15), }, Punct { ch: ';', spacing: Alone, - span: $DIR/auxiliary/dollar-crate-external.rs:14:28: 14:29 (#14), + span: $DIR/auxiliary/dollar-crate-external.rs:14:28: 14:29 (#15), }, ] diff --git a/tests/ui/proc-macro/generate-mod.stderr b/tests/ui/proc-macro/generate-mod.stderr index 371fd73e507b..af90df2c3dc3 100644 --- a/tests/ui/proc-macro/generate-mod.stderr +++ b/tests/ui/proc-macro/generate-mod.stderr @@ -47,6 +47,7 @@ LL | #[derive(generate_mod::CheckDerive)] = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! = note: for more information, see issue #83583 = note: `#[deny(proc_macro_derive_resolution_fallback)]` (part of `#[deny(future_incompatible)]`) on by default + = note: this error originates in the derive macro `generate_mod::CheckDerive` (in Nightly builds, run with -Z macro-backtrace for more info) error: cannot find type `OuterDerive` in this scope --> $DIR/generate-mod.rs:18:10 @@ -56,6 +57,7 @@ LL | #[derive(generate_mod::CheckDerive)] | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! = note: for more information, see issue #83583 + = note: this error originates in the derive macro `generate_mod::CheckDerive` (in Nightly builds, run with -Z macro-backtrace for more info) error: cannot find type `FromOutside` in this scope --> $DIR/generate-mod.rs:25:14 @@ -65,6 +67,7 @@ LL | #[derive(generate_mod::CheckDerive)] | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! = note: for more information, see issue #83583 + = note: this error originates in the derive macro `generate_mod::CheckDerive` (in Nightly builds, run with -Z macro-backtrace for more info) error: cannot find type `OuterDerive` in this scope --> $DIR/generate-mod.rs:25:14 @@ -74,6 +77,7 @@ LL | #[derive(generate_mod::CheckDerive)] | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! = note: for more information, see issue #83583 + = note: this error originates in the derive macro `generate_mod::CheckDerive` (in Nightly builds, run with -Z macro-backtrace for more info) error: aborting due to 8 previous errors @@ -88,6 +92,7 @@ LL | #[derive(generate_mod::CheckDerive)] = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! = note: for more information, see issue #83583 = note: `#[deny(proc_macro_derive_resolution_fallback)]` (part of `#[deny(future_incompatible)]`) on by default + = note: this error originates in the derive macro `generate_mod::CheckDerive` (in Nightly builds, run with -Z macro-backtrace for more info) Future breakage diagnostic: error: cannot find type `OuterDerive` in this scope @@ -99,6 +104,7 @@ LL | #[derive(generate_mod::CheckDerive)] = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! = note: for more information, see issue #83583 = note: `#[deny(proc_macro_derive_resolution_fallback)]` (part of `#[deny(future_incompatible)]`) on by default + = note: this error originates in the derive macro `generate_mod::CheckDerive` (in Nightly builds, run with -Z macro-backtrace for more info) Future breakage diagnostic: error: cannot find type `FromOutside` in this scope @@ -110,6 +116,7 @@ LL | #[derive(generate_mod::CheckDerive)] = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! = note: for more information, see issue #83583 = note: `#[deny(proc_macro_derive_resolution_fallback)]` (part of `#[deny(future_incompatible)]`) on by default + = note: this error originates in the derive macro `generate_mod::CheckDerive` (in Nightly builds, run with -Z macro-backtrace for more info) Future breakage diagnostic: error: cannot find type `OuterDerive` in this scope @@ -121,6 +128,7 @@ LL | #[derive(generate_mod::CheckDerive)] = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! = note: for more information, see issue #83583 = note: `#[deny(proc_macro_derive_resolution_fallback)]` (part of `#[deny(future_incompatible)]`) on by default + = note: this error originates in the derive macro `generate_mod::CheckDerive` (in Nightly builds, run with -Z macro-backtrace for more info) Future breakage diagnostic: warning: cannot find type `FromOutside` in this scope @@ -131,6 +139,7 @@ LL | #[derive(generate_mod::CheckDeriveLint)] // OK, lint is suppressed | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! = note: for more information, see issue #83583 + = note: this warning originates in the derive macro `generate_mod::CheckDeriveLint` (in Nightly builds, run with -Z macro-backtrace for more info) Future breakage diagnostic: warning: cannot find type `OuterDeriveLint` in this scope @@ -141,4 +150,5 @@ LL | #[derive(generate_mod::CheckDeriveLint)] // OK, lint is suppressed | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! = note: for more information, see issue #83583 + = note: this warning originates in the derive macro `generate_mod::CheckDeriveLint` (in Nightly builds, run with -Z macro-backtrace for more info) diff --git a/tests/ui/proc-macro/nested-macro-rules.stdout b/tests/ui/proc-macro/nested-macro-rules.stdout index 5b678554b9e0..89fb7b042218 100644 --- a/tests/ui/proc-macro/nested-macro-rules.stdout +++ b/tests/ui/proc-macro/nested-macro-rules.stdout @@ -2,45 +2,45 @@ PRINT-BANG INPUT (DISPLAY): FirstStruct PRINT-BANG INPUT (DEBUG): TokenStream [ Ident { ident: "FirstStruct", - span: $DIR/auxiliary/nested-macro-rules.rs:16:14: 16:25 (#6), + span: $DIR/auxiliary/nested-macro-rules.rs:16:14: 16:25 (#7), }, ] PRINT-ATTR INPUT (DISPLAY): struct FirstAttrStruct {} PRINT-ATTR INPUT (DEBUG): TokenStream [ Ident { ident: "struct", - span: $DIR/auxiliary/nested-macro-rules.rs:10:32: 10:38 (#5), + span: $DIR/auxiliary/nested-macro-rules.rs:10:32: 10:38 (#6), }, Ident { ident: "FirstAttrStruct", - span: $DIR/auxiliary/nested-macro-rules.rs:16:27: 16:42 (#6), + span: $DIR/auxiliary/nested-macro-rules.rs:16:27: 16:42 (#7), }, Group { delimiter: Brace, stream: TokenStream [], - span: $DIR/auxiliary/nested-macro-rules.rs:10:57: 10:59 (#5), + span: $DIR/auxiliary/nested-macro-rules.rs:10:57: 10:59 (#6), }, ] PRINT-BANG INPUT (DISPLAY): SecondStruct PRINT-BANG INPUT (DEBUG): TokenStream [ Ident { ident: "SecondStruct", - span: $DIR/nested-macro-rules.rs:23:38: 23:50 (#15), + span: $DIR/nested-macro-rules.rs:23:38: 23:50 (#16), }, ] PRINT-ATTR INPUT (DISPLAY): struct SecondAttrStruct {} PRINT-ATTR INPUT (DEBUG): TokenStream [ Ident { ident: "struct", - span: $DIR/auxiliary/nested-macro-rules.rs:10:32: 10:38 (#14), + span: $DIR/auxiliary/nested-macro-rules.rs:10:32: 10:38 (#15), }, Ident { ident: "SecondAttrStruct", - span: $DIR/nested-macro-rules.rs:23:52: 23:68 (#15), + span: $DIR/nested-macro-rules.rs:23:52: 23:68 (#16), }, Group { delimiter: Brace, stream: TokenStream [], - span: $DIR/auxiliary/nested-macro-rules.rs:10:57: 10:59 (#14), + span: $DIR/auxiliary/nested-macro-rules.rs:10:57: 10:59 (#15), }, ] diff --git a/tests/ui/proc-macro/quote/not-repeatable.stderr b/tests/ui/proc-macro/quote/not-repeatable.stderr index 5943111efd58..6a867350a3b3 100644 --- a/tests/ui/proc-macro/quote/not-repeatable.stderr +++ b/tests/ui/proc-macro/quote/not-repeatable.stderr @@ -2,7 +2,7 @@ error[E0599]: the method `quote_into_iter` exists for struct `Ipv4Addr`, but its --> $DIR/not-repeatable.rs:11:13 | LL | struct Ipv4Addr; - | --------------- method `quote_into_iter` not found for this struct because it doesn't satisfy `Ipv4Addr: Iterator`, `Ipv4Addr: ToTokens`, `Ipv4Addr: proc_macro::ext::RepIteratorExt` or `Ipv4Addr: proc_macro::ext::RepToTokensExt` + | --------------- method `quote_into_iter` not found for this struct because `Ipv4Addr` doesn't implement `Iterator` or `ToTokens` ... LL | let _ = quote! { $($ip)* }; | ^^^^^^^^^^^^^^^^^^ method cannot be called on `Ipv4Addr` due to unsatisfied trait bounds diff --git a/tests/ui/rfcs/rfc-1861-extern-types/comparison.rs b/tests/ui/rfcs/rfc-1861-extern-types/comparison.rs new file mode 100644 index 000000000000..6504fd64f64d --- /dev/null +++ b/tests/ui/rfcs/rfc-1861-extern-types/comparison.rs @@ -0,0 +1,35 @@ +// Foreign type tests not covering all operations +//@ only-nightly +//@ build-pass + +#![feature(extern_types)] + +#![allow(ambiguous_wide_pointer_comparisons)] + +extern "C" { + type ForeignType; +} + +#[repr(C)] +struct Example { + field: ForeignType, +} + +fn main() { + // pointer comparison + let a = std::ptr::null::(); + let b = std::ptr::null::(); + + assert!(a == b); + + // field address computation + let p = std::ptr::null::(); + unsafe { + let _ = &(*p).field; + } + + // pointer casts involving extern types + let raw = std::ptr::null::<()>(); + let ext = raw as *const ForeignType; + let _ = ext as *const (); +} diff --git a/tests/ui/rfcs/rfc-2008-non-exhaustive/invalid-attribute.stderr b/tests/ui/rfcs/rfc-2008-non-exhaustive/invalid-attribute.stderr index 98e8f1235e6b..d711c3f2eb12 100644 --- a/tests/ui/rfcs/rfc-2008-non-exhaustive/invalid-attribute.stderr +++ b/tests/ui/rfcs/rfc-2008-non-exhaustive/invalid-attribute.stderr @@ -21,7 +21,7 @@ error: `#[non_exhaustive]` attribute cannot be used on unions LL | #[non_exhaustive] | ^^^^^^^^^^^^^^^^^ | - = help: `#[non_exhaustive]` can be applied to data types and enum variants + = help: `#[non_exhaustive]` can be applied to enum variants, enums, and structs error: aborting due to 3 previous errors diff --git a/tests/ui/rfcs/rfc-2565-param-attrs/param-attrs-builtin-attrs.stderr b/tests/ui/rfcs/rfc-2565-param-attrs/param-attrs-builtin-attrs.stderr index cc08307a18d0..c234cb31bc56 100644 --- a/tests/ui/rfcs/rfc-2565-param-attrs/param-attrs-builtin-attrs.stderr +++ b/tests/ui/rfcs/rfc-2565-param-attrs/param-attrs-builtin-attrs.stderr @@ -389,7 +389,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits = note: requested on the command line with `-W unused-attributes` warning: `#[no_mangle]` attribute cannot be used on function params @@ -408,7 +408,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits warning: `#[no_mangle]` attribute cannot be used on function params --> $DIR/param-attrs-builtin-attrs.rs:70:9 @@ -426,7 +426,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits warning: `#[no_mangle]` attribute cannot be used on function params --> $DIR/param-attrs-builtin-attrs.rs:89:9 @@ -444,7 +444,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits warning: `#[no_mangle]` attribute cannot be used on function params --> $DIR/param-attrs-builtin-attrs.rs:114:9 @@ -462,7 +462,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits warning: `#[no_mangle]` attribute cannot be used on function params --> $DIR/param-attrs-builtin-attrs.rs:137:9 @@ -480,7 +480,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits warning: `#[no_mangle]` attribute cannot be used on function params --> $DIR/param-attrs-builtin-attrs.rs:156:9 @@ -498,7 +498,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits warning: `#[no_mangle]` attribute cannot be used on function params --> $DIR/param-attrs-builtin-attrs.rs:180:9 @@ -516,7 +516,7 @@ LL | #[must_use] | ^^^^^^^^^^^ | = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release! - = help: `#[must_use]` can be applied to data types, functions, traits, and unions + = help: `#[must_use]` can be applied to data types, functions, and traits warning: `#[no_mangle]` attribute cannot be used on function params --> $DIR/param-attrs-builtin-attrs.rs:201:9 diff --git a/tests/ui/simd/dont-invalid-bitcast-masks.rs b/tests/ui/simd/dont-invalid-bitcast-masks.rs index 3d8376207cd0..1e2d097198d0 100644 --- a/tests/ui/simd/dont-invalid-bitcast-masks.rs +++ b/tests/ui/simd/dont-invalid-bitcast-masks.rs @@ -12,6 +12,6 @@ use std::simd::num::*; pub unsafe fn mask_to_array(mask: u8) -> [i32; 8] { let mut output = [0; 8]; let m = masksizex8::from_bitmask(mask as _); - output.copy_from_slice(&m.to_int().cast::().to_array()); + output.copy_from_slice(&m.to_simd().cast::().to_array()); output } diff --git a/tests/ui/suggestions/derive-clone-already-present-issue-146515.rs b/tests/ui/suggestions/derive-clone-already-present-issue-146515.rs new file mode 100644 index 000000000000..083d73711a51 --- /dev/null +++ b/tests/ui/suggestions/derive-clone-already-present-issue-146515.rs @@ -0,0 +1,20 @@ +// issue: https://github.com/rust-lang/rust/issues/146515 + +use std::rc::Rc; + +#[derive(Clone)] +struct ContainsRc { + value: Rc, +} + +fn clone_me(x: &ContainsRc) -> ContainsRc { + //~^ NOTE expected `ContainsRc` because of return type + x.clone() + //~^ ERROR mismatched types + //~| NOTE expected `ContainsRc`, found `&ContainsRc` + //~| NOTE expected struct `ContainsRc<_>` + //~| NOTE `ContainsRc` does not implement `Clone`, so `&ContainsRc` was cloned instead + //~| NOTE the trait `Clone` must be implemented +} + +fn main() {} diff --git a/tests/ui/suggestions/derive-clone-already-present-issue-146515.stderr b/tests/ui/suggestions/derive-clone-already-present-issue-146515.stderr new file mode 100644 index 000000000000..516ef38f668d --- /dev/null +++ b/tests/ui/suggestions/derive-clone-already-present-issue-146515.stderr @@ -0,0 +1,23 @@ +error[E0308]: mismatched types + --> $DIR/derive-clone-already-present-issue-146515.rs:12:5 + | +LL | fn clone_me(x: &ContainsRc) -> ContainsRc { + | ------------- expected `ContainsRc` because of return type +LL | +LL | x.clone() + | ^^^^^^^^^ expected `ContainsRc`, found `&ContainsRc` + | + = note: expected struct `ContainsRc<_>` + found reference `&ContainsRc<_>` +note: `ContainsRc` does not implement `Clone`, so `&ContainsRc` was cloned instead + --> $DIR/derive-clone-already-present-issue-146515.rs:12:5 + | +LL | x.clone() + | ^ + = help: `Clone` is not implemented because the trait bound `T: Clone` is not satisfied +note: the trait `Clone` must be implemented + --> $SRC_DIR/core/src/clone.rs:LL:COL + +error: aborting due to 1 previous error + +For more information about this error, try `rustc --explain E0308`. diff --git a/tests/ui/trait-bounds/suggest-maybe-sized-bound.stderr b/tests/ui/trait-bounds/suggest-maybe-sized-bound.stderr index 4ce936582f43..b459ad47e067 100644 --- a/tests/ui/trait-bounds/suggest-maybe-sized-bound.stderr +++ b/tests/ui/trait-bounds/suggest-maybe-sized-bound.stderr @@ -22,7 +22,7 @@ LL | type P = [u8]; | ^^^^ doesn't have a size known at compile-time | = help: the trait `Sized` is not implemented for `[u8]` -note: required by a bound in `Trait::P` +note: required by a bound in `main::Trait::P` --> $DIR/suggest-maybe-sized-bound.rs:13:9 | LL | type P; diff --git a/tests/ui/traits/associated-item-unsatisfied-trait-bounds.rs b/tests/ui/traits/associated-item-unsatisfied-trait-bounds.rs new file mode 100644 index 000000000000..4fb4cd61ac51 --- /dev/null +++ b/tests/ui/traits/associated-item-unsatisfied-trait-bounds.rs @@ -0,0 +1,9 @@ +struct Foo; +trait Bar {} +trait Baz {} +trait Bat { fn bat(&self); } +impl Bat for T where T: 'static + Bar + Baz { fn bat(&self) { println!("generic bat"); } } + +pub fn main() { + Foo::bat(()); //~ ERROR E0599 +} diff --git a/tests/ui/traits/associated-item-unsatisfied-trait-bounds.stderr b/tests/ui/traits/associated-item-unsatisfied-trait-bounds.stderr new file mode 100644 index 000000000000..42969de715eb --- /dev/null +++ b/tests/ui/traits/associated-item-unsatisfied-trait-bounds.stderr @@ -0,0 +1,33 @@ +error[E0599]: the function or associated item `bat` exists for struct `Foo`, but its trait bounds were not satisfied + --> $DIR/associated-item-unsatisfied-trait-bounds.rs:8:10 + | +LL | struct Foo; + | ---------- function or associated item `bat` not found for this struct because `Foo` doesn't implement `Bar` or `Baz` +... +LL | Foo::bat(()); + | ^^^ function or associated item cannot be called on `Foo` due to unsatisfied trait bounds + | +note: for `bat` to be available, `Foo` must implement `Bar` and `Baz` + --> $DIR/associated-item-unsatisfied-trait-bounds.rs:5:38 + | +LL | impl Bat for T where T: 'static + Bar + Baz { fn bat(&self) { println!("generic bat"); } } + | --- - ^^^ ^^^ unsatisfied trait bound introduced here + | | + | unsatisfied trait bound introduced here +note: the traits `Bar` and `Baz` must be implemented + --> $DIR/associated-item-unsatisfied-trait-bounds.rs:2:1 + | +LL | trait Bar {} + | ^^^^^^^^^ +LL | trait Baz {} + | ^^^^^^^^^ + = help: items from traits can only be used if the trait is implemented and in scope +note: `Bat` defines an item `bat`, perhaps you need to implement it + --> $DIR/associated-item-unsatisfied-trait-bounds.rs:4:1 + | +LL | trait Bat { fn bat(&self); } + | ^^^^^^^^^ + +error: aborting due to 1 previous error + +For more information about this error, try `rustc --explain E0599`. diff --git a/tests/ui/traits/bound/on-structs-and-enums-xc.stderr b/tests/ui/traits/bound/on-structs-and-enums-xc.stderr index 5064b60bfd57..472ac187a966 100644 --- a/tests/ui/traits/bound/on-structs-and-enums-xc.stderr +++ b/tests/ui/traits/bound/on-structs-and-enums-xc.stderr @@ -1,8 +1,8 @@ -error[E0277]: the trait bound `usize: Trait` is not satisfied +error[E0277]: the trait bound `usize: on_structs_and_enums_xc::Trait` is not satisfied --> $DIR/on-structs-and-enums-xc.rs:7:15 | LL | fn explode(x: Foo) {} - | ^^^^^^^^^^ the trait `Trait` is not implemented for `usize` + | ^^^^^^^^^^ the trait `on_structs_and_enums_xc::Trait` is not implemented for `usize` | note: required by a bound in `Foo` --> $DIR/auxiliary/on_structs_and_enums_xc.rs:5:18 @@ -10,11 +10,11 @@ note: required by a bound in `Foo` LL | pub struct Foo { | ^^^^^ required by this bound in `Foo` -error[E0277]: the trait bound `f32: Trait` is not satisfied +error[E0277]: the trait bound `f32: on_structs_and_enums_xc::Trait` is not satisfied --> $DIR/on-structs-and-enums-xc.rs:10:14 | LL | fn kaboom(y: Bar) {} - | ^^^^^^^^ the trait `Trait` is not implemented for `f32` + | ^^^^^^^^ the trait `on_structs_and_enums_xc::Trait` is not implemented for `f32` | note: required by a bound in `Bar` --> $DIR/auxiliary/on_structs_and_enums_xc.rs:9:16 diff --git a/tests/ui/traits/bound/on-structs-and-enums-xc1.stderr b/tests/ui/traits/bound/on-structs-and-enums-xc1.stderr index 1f46415e2436..5cf682a5045e 100644 --- a/tests/ui/traits/bound/on-structs-and-enums-xc1.stderr +++ b/tests/ui/traits/bound/on-structs-and-enums-xc1.stderr @@ -1,8 +1,8 @@ -error[E0277]: the trait bound `{integer}: Trait` is not satisfied +error[E0277]: the trait bound `{integer}: on_structs_and_enums_xc::Trait` is not satisfied --> $DIR/on-structs-and-enums-xc1.rs:9:12 | LL | x: 3 - | ^ the trait `Trait` is not implemented for `{integer}` + | ^ the trait `on_structs_and_enums_xc::Trait` is not implemented for `{integer}` | note: required by a bound in `Foo` --> $DIR/auxiliary/on_structs_and_enums_xc.rs:5:18 @@ -10,11 +10,11 @@ note: required by a bound in `Foo` LL | pub struct Foo { | ^^^^^ required by this bound in `Foo` -error[E0277]: the trait bound `f64: Trait` is not satisfied +error[E0277]: the trait bound `f64: on_structs_and_enums_xc::Trait` is not satisfied --> $DIR/on-structs-and-enums-xc1.rs:12:14 | LL | let bar: Bar = return; - | ^^^^^^^^ the trait `Trait` is not implemented for `f64` + | ^^^^^^^^ the trait `on_structs_and_enums_xc::Trait` is not implemented for `f64` | note: required by a bound in `Bar` --> $DIR/auxiliary/on_structs_and_enums_xc.rs:9:16 diff --git a/tests/ui/traits/wrong-multiple-different-versions-of-a-crate.rs b/tests/ui/traits/wrong-multiple-different-versions-of-a-crate.rs index ec6bb7bbcc59..35465183001a 100644 --- a/tests/ui/traits/wrong-multiple-different-versions-of-a-crate.rs +++ b/tests/ui/traits/wrong-multiple-different-versions-of-a-crate.rs @@ -5,8 +5,8 @@ // Issue #148892. //@ aux-crate:crate1=crate1.rs -struct MyStruct; //~ HELP the trait `Trait` is not implemented for `MyStruct` +struct MyStruct; //~ HELP the trait `crate1::Trait` is not implemented for `MyStruct` fn main() { - crate1::foo(MyStruct); //~ ERROR the trait bound `MyStruct: Trait` is not satisfied + crate1::foo(MyStruct); //~ ERROR the trait bound `MyStruct: crate1::Trait` is not satisfied } diff --git a/tests/ui/traits/wrong-multiple-different-versions-of-a-crate.stderr b/tests/ui/traits/wrong-multiple-different-versions-of-a-crate.stderr index 7fec237f54d4..5bcda9f2a95b 100644 --- a/tests/ui/traits/wrong-multiple-different-versions-of-a-crate.stderr +++ b/tests/ui/traits/wrong-multiple-different-versions-of-a-crate.stderr @@ -1,4 +1,4 @@ -error[E0277]: the trait bound `MyStruct: Trait` is not satisfied +error[E0277]: the trait bound `MyStruct: crate1::Trait` is not satisfied --> $DIR/wrong-multiple-different-versions-of-a-crate.rs:11:17 | LL | crate1::foo(MyStruct); @@ -6,7 +6,7 @@ LL | crate1::foo(MyStruct); | | | required by a bound introduced by this call | -help: the trait `Trait` is not implemented for `MyStruct` +help: the trait `crate1::Trait` is not implemented for `MyStruct` --> $DIR/wrong-multiple-different-versions-of-a-crate.rs:8:1 | LL | struct MyStruct; diff --git a/tests/ui/unresolved/unresolved-candidates.stderr b/tests/ui/unresolved/unresolved-candidates.stderr index 55b9d8ec6e8f..7d8e894a5582 100644 --- a/tests/ui/unresolved/unresolved-candidates.stderr +++ b/tests/ui/unresolved/unresolved-candidates.stderr @@ -4,8 +4,10 @@ error[E0432]: unresolved import `Trait` LL | use Trait; | ^^^^^ no `Trait` in the root | -help: consider importing this trait instead +help: consider importing one of these items instead | +LL | use std::mem::type_info::Trait; + | +++++++++++++++++++++ LL | use a::Trait; | +++ diff --git a/tests/ui/unstable-feature-bound/unstable_impl_coherence.disabled.stderr b/tests/ui/unstable-feature-bound/unstable_impl_coherence.disabled.stderr index afef024e1b9c..60bb2117df24 100644 --- a/tests/ui/unstable-feature-bound/unstable_impl_coherence.disabled.stderr +++ b/tests/ui/unstable-feature-bound/unstable_impl_coherence.disabled.stderr @@ -1,11 +1,11 @@ -error[E0119]: conflicting implementations of trait `Trait` for type `LocalTy` +error[E0119]: conflicting implementations of trait `aux::Trait` for type `LocalTy` --> $DIR/unstable_impl_coherence.rs:14:1 | LL | impl aux::Trait for LocalTy {} | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ | = note: conflicting implementation in crate `unstable_impl_coherence_aux`: - - impl Trait for T + - impl aux::Trait for T where feature(foo) is enabled; error: aborting due to 1 previous error diff --git a/tests/ui/unstable-feature-bound/unstable_impl_coherence.enabled.stderr b/tests/ui/unstable-feature-bound/unstable_impl_coherence.enabled.stderr index afef024e1b9c..60bb2117df24 100644 --- a/tests/ui/unstable-feature-bound/unstable_impl_coherence.enabled.stderr +++ b/tests/ui/unstable-feature-bound/unstable_impl_coherence.enabled.stderr @@ -1,11 +1,11 @@ -error[E0119]: conflicting implementations of trait `Trait` for type `LocalTy` +error[E0119]: conflicting implementations of trait `aux::Trait` for type `LocalTy` --> $DIR/unstable_impl_coherence.rs:14:1 | LL | impl aux::Trait for LocalTy {} | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ | = note: conflicting implementation in crate `unstable_impl_coherence_aux`: - - impl Trait for T + - impl aux::Trait for T where feature(foo) is enabled; error: aborting due to 1 previous error diff --git a/tests/ui/unstable-feature-bound/unstable_impl_coherence.rs b/tests/ui/unstable-feature-bound/unstable_impl_coherence.rs index 22100f85f715..c36316dc5fa1 100644 --- a/tests/ui/unstable-feature-bound/unstable_impl_coherence.rs +++ b/tests/ui/unstable-feature-bound/unstable_impl_coherence.rs @@ -12,6 +12,6 @@ use aux::Trait; struct LocalTy; impl aux::Trait for LocalTy {} -//~^ ERROR: conflicting implementations of trait `Trait` for type `LocalTy` +//~^ ERROR: conflicting implementations of trait `aux::Trait` for type `LocalTy` fn main(){} diff --git a/tests/ui/unstable-feature-bound/unstable_impl_method_selection.stderr b/tests/ui/unstable-feature-bound/unstable_impl_method_selection.stderr index 840af730154d..b2e4eb730d84 100644 --- a/tests/ui/unstable-feature-bound/unstable_impl_method_selection.stderr +++ b/tests/ui/unstable-feature-bound/unstable_impl_method_selection.stderr @@ -4,9 +4,9 @@ error[E0283]: type annotations needed LL | vec![].foo(); | ^^^ cannot infer type for struct `Vec<_>` | - = note: multiple `impl`s satisfying `Vec<_>: Trait` found in the `unstable_impl_method_selection_aux` crate: - - impl Trait for Vec; - - impl Trait for Vec + = note: multiple `impl`s satisfying `Vec<_>: aux::Trait` found in the `unstable_impl_method_selection_aux` crate: + - impl aux::Trait for Vec; + - impl aux::Trait for Vec where feature(bar) is enabled; error: aborting due to 1 previous error diff --git a/tests/ui/use/issue-18986.stderr b/tests/ui/use/issue-18986.stderr index 350cb18f9527..084fa80c3b6d 100644 --- a/tests/ui/use/issue-18986.stderr +++ b/tests/ui/use/issue-18986.stderr @@ -3,6 +3,11 @@ error[E0574]: expected struct, variant or union type, found trait `Trait` | LL | Trait { x: 42 } => () | ^^^^^ not a struct, variant or union type + | +help: consider importing this struct instead + | +LL + use std::mem::type_info::Trait; + | error: aborting due to 1 previous error diff --git a/tests/ui/where-clauses/unsupported_attribute.stderr b/tests/ui/where-clauses/unsupported_attribute.stderr index 9ebc14c40a14..e69eff976c3f 100644 --- a/tests/ui/where-clauses/unsupported_attribute.stderr +++ b/tests/ui/where-clauses/unsupported_attribute.stderr @@ -64,7 +64,7 @@ error: `#[deprecated]` attribute cannot be used on where predicates LL | #[deprecated] T: Trait, | ^^^^^^^^^^^^^ | - = help: `#[deprecated]` can be applied to associated consts, associated types, constants, crates, data types, enum variants, foreign statics, functions, inherent impl blocks, macro defs, modules, statics, struct fields, traits, type aliases, unions, and use statements + = help: `#[deprecated]` can be applied to associated consts, associated types, constants, crates, data types, enum variants, foreign statics, functions, inherent impl blocks, macro defs, modules, statics, struct fields, traits, type aliases, and use statements error: `#[deprecated]` attribute cannot be used on where predicates --> $DIR/unsupported_attribute.rs:25:5 @@ -72,7 +72,7 @@ error: `#[deprecated]` attribute cannot be used on where predicates LL | #[deprecated] 'a: 'static, | ^^^^^^^^^^^^^ | - = help: `#[deprecated]` can be applied to associated consts, associated types, constants, crates, data types, enum variants, foreign statics, functions, inherent impl blocks, macro defs, modules, statics, struct fields, traits, type aliases, unions, and use statements + = help: `#[deprecated]` can be applied to associated consts, associated types, constants, crates, data types, enum variants, foreign statics, functions, inherent impl blocks, macro defs, modules, statics, struct fields, traits, type aliases, and use statements error: `#[automatically_derived]` attribute cannot be used on where predicates --> $DIR/unsupported_attribute.rs:26:5 diff --git a/triagebot.toml b/triagebot.toml index 1572c4c8d045..eb25d6e1b201 100644 --- a/triagebot.toml +++ b/triagebot.toml @@ -1182,11 +1182,11 @@ cc = ["@Muscraft"] [mentions."compiler/rustc_errors/src/translation.rs"] message = "`rustc_errors::translation` was changed" -cc = ["@davidtwco", "@TaKO8Ki"] +cc = ["@davidtwco", "@TaKO8Ki", "@JonathanBrouwer"] [mentions."compiler/rustc_macros/src/diagnostics"] message = "`rustc_macros::diagnostics` was changed" -cc = ["@davidtwco", "@TaKO8Ki"] +cc = ["@davidtwco", "@TaKO8Ki", "@JonathanBrouwer"] [mentions."compiler/rustc_public"] message = "This PR changes rustc_public" diff --git a/typos.toml b/typos.toml index 920234a9381b..25083174cb8f 100644 --- a/typos.toml +++ b/typos.toml @@ -1,3 +1,6 @@ +# Config for the `typos` crate, used by `./x test tidy --extra-checks=spellcheck`. +# See also: https://github.com/crate-ci/typos/blob/v1.28.2/docs/reference.md + [files] extend-exclude = [ # exclude git (sub)modules and generated content @@ -13,57 +16,65 @@ extend-exclude = [ ] [default.extend-words] -# Add exclusions here, lines should be like `x = "x"`, where `x` is excluded word. +# Allowlist for words that look like typos but are not, or aren't worth fixing +# right now. Entries should look like `mipsel = "mipsel"`. # -# Also see docs: https://github.com/crate-ci/typos/blob/v1.28.2/docs/reference.md -arange = "arange" +# tidy-alphabetical-start +arange = "arange" # short for A-range childs = "childs" clonable = "clonable" -Datas = "Datas" -filetimes = "filetimes" +filetimes = "filetimes" # short for "file times", not a typo for "lifetimes" leafs = "leafs" -makro = "makro" +makro = "makro" # deliberate misspelling to avoid `macro` keyword misformed = "misformed" moreso = "moreso" -optin = "optin" +numer = "numer" # short for numerator, not a typo for "number" +optin = "optin" # short for opt-in publically = "publically" -rplace = "rplace" -smove = "smove" +rplace = "rplace" # short for R-place splitted = "splitted" -taits = "taits" +taits = "taits" # lowercase for TAITs (type alias impl trait) targetting = "targetting" unparseable = "unparseable" unstability = "unstability" -unstalled = "unstalled" -numer = "numer" +unstalled = "unstalled" # short for un-stalled +# tidy-alphabetical-end -# this can be valid word, depends on dictionary edition -#matcheable = "matcheable" +# Denylist to forbid misspelled words that aren't detected by the built-in +# dictionary. Entries should look like `mipsel = ""` or `mipsel = "misspell"`; +# the non-empty form can be automatically fixed by `--bless`. +# +# tidy-alphabetical-start +definitinon = "definition" +# tidy-alphabetical-end [default.extend-identifiers] -# An entry goes here if the typo is part of some existing ident -# where you want to keep it, but don't want to allow -# such typos everywhere. +# Allowlist for specific identifiers that should be permitted even though they +# appear to contain typos that would be forbidden in other identifiers. # -# I.e. you don't want (or can't) fix some constant name, like -# `DNS_ERROR_INVAILD_VIRTUALIZATION_INSTANCE_NAME` but actually -# want to see `INVAILD` typo fixed in other places. -debug_aranges = "debug_aranges" +# For example, you might want to allow a specific constant like +# `DNS_ERROR_INVAILD_VIRTUALIZATION_INSTANCE_NAME`, but still want to forbid +# the typo `INVAILD` in other places. +# +# tidy-alphabetical-start DNS_ERROR_INVAILD_VIRTUALIZATION_INSTANCE_NAME = "DNS_ERROR_INVAILD_VIRTUALIZATION_INSTANCE_NAME" -EnzymeTypeTreeShiftIndiciesEq = "EnzymeTypeTreeShiftIndiciesEq" -EnzymeTypeTreeShiftIndiciesEqFn = "EnzymeTypeTreeShiftIndiciesEqFn" -shift_indicies_eq = "shift_indicies_eq" ERRNO_ACCES = "ERRNO_ACCES" ERROR_DS_FILTER_USES_CONTRUCTED_ATTRS = "ERROR_DS_FILTER_USES_CONTRUCTED_ATTRS" ERROR_DS_NOT_AUTHORITIVE_FOR_DST_NC = "ERROR_DS_NOT_AUTHORITIVE_FOR_DST_NC" ERROR_FILENAME_EXCED_RANGE = "ERROR_FILENAME_EXCED_RANGE" ERROR_MCA_OCCURED = "ERROR_MCA_OCCURED" ERROR_REQ_NOT_ACCEP = "ERROR_REQ_NOT_ACCEP" -Oppen = "Oppen" +EnzymeTypeTreeShiftIndiciesEq = "EnzymeTypeTreeShiftIndiciesEq" +EnzymeTypeTreeShiftIndiciesEqFn = "EnzymeTypeTreeShiftIndiciesEqFn" +Oppen = "Oppen" # Derek C. Oppen, author of "Pretty Printing" (1979) # typos treats this as two different camelcase words (`SETTIN` and `Gs`) # Tracked in: https://github.com/crate-ci/typos/issues/745 SETTINGs = "SETTINGs" -tolen = "tolen" +debug_aranges = "debug_aranges" # debug A-ranges +key_smove = "key_smove" # shifted move key, used by terminfo +shift_indicies_eq = "shift_indicies_eq" +tolen = "tolen" # length of "to" buffer, used by `sendto` in Windows sockets +# tidy-alphabetical-end [default] extend-ignore-words-re = [