From cd862a8ff3a936c354bc394beef74e4681abfd35 Mon Sep 17 00:00:00 2001
From: David Craven <david@craven.ch>
Date: Thu, 30 Aug 2018 14:19:02 +0200
Subject: [PATCH] [RISCV] Enable C extension.

---
 src/librustc_target/spec/riscv32imac_unknown_none_elf.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/librustc_target/spec/riscv32imac_unknown_none_elf.rs b/src/librustc_target/spec/riscv32imac_unknown_none_elf.rs
index 78a49a91208e..f8e57c08e06b 100644
--- a/src/librustc_target/spec/riscv32imac_unknown_none_elf.rs
+++ b/src/librustc_target/spec/riscv32imac_unknown_none_elf.rs
@@ -30,7 +30,7 @@ pub fn target() -> TargetResult {
             cpu: "generic-rv32".to_string(),
             max_atomic_width: Some(32),
             atomic_cas: false, // incomplete +a extension
-            features: "+m,+a".to_string(), // disable +c extension
+            features: "+m,+a,+c".to_string(),
             executables: true,
             panic_strategy: PanicStrategy::Abort,
             relocation_model: "static".to_string(),